From fccbcfc88977ebdfb1448f6787cb052cfa949788 Mon Sep 17 00:00:00 2001 From: Greg Davill Date: Mon, 21 Mar 2022 10:01:11 +1030 Subject: Add WCH CH32V307 port Add WCH mcu submodule Add CH32V307V-R1-1v0 bsp --- src/common/tusb_mcu.h | 4 + src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h | 345 ++++++++++++++++++++++ src/portable/wch/ch32v307/usb_dc_usbhs.c | 388 +++++++++++++++++++++++++ src/tusb_option.h | 3 + 4 files changed, 740 insertions(+) create mode 100644 src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h create mode 100644 src/portable/wch/ch32v307/usb_dc_usbhs.c (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 8eb4ad475..84d629eac 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -266,6 +266,10 @@ #elif TU_CHECK_MCU(OPT_MCU_F1C100S) #define TUP_DCD_ENDPOINT_MAX 4 +//------------- WCH -------------// +#elif TU_CHECK_MCU(OPT_MCU_CH32VF307) + #define TUP_DCD_ENDPOINT_MAX 8 + #endif //--------------------------------------------------------------------+ diff --git a/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h b/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h new file mode 100644 index 000000000..1b7c0e791 --- /dev/null +++ b/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h @@ -0,0 +1,345 @@ +#ifndef _USB_CH32_USBHS_REG_H +#define _USB_CH32_USBHS_REG_H + +#include + +/******************* GLOBAL ******************/ + +// USB CONTROL +#define USBHS_CONTROL_OFFSET 0x00 +#define USBHS_DMA_EN (1 << 0) +#define USBHS_ALL_CLR (1 << 1) +#define USBHS_FORCE_RST (1 << 2) +#define USBHS_INT_BUSY_EN (1 << 3) +#define USBHS_DEV_PU_EN (1 << 4) +#define USBHS_SPEED_MASK (3 << 5) +#define USBHS_FULL_SPEED (0 << 5) +#define USBHS_HIGH_SPEED (1 << 5) +#define USBHS_LOW_SPEED (2 << 5) +#define USBHS_HOST_MODE (1 << 7) + +// USB_INT_EN +#define USBHS_INT_EN_OFFSET 0x02 +#define USBHS_BUS_RST_EN (1 << 0) +#define USBHS_DETECT_EN (1 << 0) +#define USBHS_TRANSFER_EN (1 << 1) +#define USBHS_SUSPEND_EN (1 << 2) +#define USBHS_SOF_ACT_EN (1 << 3) +#define USBHS_FIFO_OV_EN (1 << 4) +#define USBHS_SETUP_ACT_EN (1 << 5) +#define USBHS_ISO_ACT_EN (1 << 6) +#define USBHS_DEV_NAK_EN (1 << 7) + +// USB DEV AD +#define USBHS_DEV_AD_OFFSET 0x03 +// USB FRAME_NO +#define USBHS_FRAME_NO_OFFSET 0x04 +// USB SUSPEND +#define USBHS_SUSPEND_OFFSET 0x06 +#define USBHS_DEV_REMOTE_WAKEUP (1 << 2) +#define USBHS_LINESTATE_MASK (2 << 4) /* Read Only */ + +// RESERVED0 + +// USB SPEED TYPE +#define USBHS_SPEED_TYPE_OFFSET 0x08 +#define USBSPEED_MASK (0x03) + +// USB_MIS_ST +#define USBHS_MIS_ST_OFFSET 0x09 +#define USBHS_SPLIT_CAN (1 << 0) +#define USBHS_ATTACH (1 << 1) +#define USBHS_SUSPEND (1 << 2) +#define USBHS_BUS_RESET (1 << 3) +#define USBHS_R_FIFO_RDY (1 << 4) +#define USBHS_SIE_FREE (1 << 5) +#define USBHS_SOF_ACT (1 << 6) +#define USBHS_SOF_PRES (1 << 7) + +// INT_FLAG +#define USBHS_INT_FLAG_OFFSET 0x0A +#define USBHS_BUS_RST_FLAG (1 << 0) +#define USBHS_DETECT_FLAG (1 << 0) +#define USBHS_TRANSFER_FLAG (1 << 1) +#define USBHS_SUSPEND_FLAG (1 << 2) +#define USBHS_HST_SOF_FLAG (1 << 3) +#define USBHS_FIFO_OV_FLAG (1 << 4) +#define USBHS_SETUP_FLAG (1 << 5) +#define USBHS_ISO_ACT_FLAG (1 << 6) + +// INT_ST +#define USBHS_INT_ST_OFFSET 0x0B +#define USBHS_DEV_UIS_IS_NAK (1 << 7) +#define USBHS_DEV_UIS_TOG_OK (1 << 6) +#define MASK_UIS_TOKEN (3 << 4) +#define MASK_UIS_ENDP (0x0F) +#define MASK_UIS_H_RES (0x0F) + +#define USBHS_TOGGLE_OK (0x40) +#define USBHS_HOST_RES (0x0f) + +//USB_RX_LEN +#define USBHS_RX_LEN_OFFSET 0x0C +/******************* DEVICE ******************/ + +//UEP_CONFIG +#define USBHS_UEP_CONFIG_OFFSET 0x10 +#define USBHS_EP0_T_EN (1 << 0) +#define USBHS_EP0_R_EN (1 << 16) + +#define USBHS_EP1_T_EN (1 << 1) +#define USBHS_EP1_R_EN (1 << 17) + +#define USBHS_EP2_T_EN (1 << 2) +#define USBHS_EP2_R_EN (1 << 18) + +#define USBHS_EP3_T_EN (1 << 3) +#define USBHS_EP3_R_EN (1 << 19) + +#define USBHS_EP4_T_EN (1 << 4) +#define USBHS_EP4_R_EN (1 << 20) + +#define USBHS_EP5_T_EN (1 << 5) +#define USBHS_EP5_R_EN (1 << 21) + +#define USBHS_EP6_T_EN (1 << 6) +#define USBHS_EP6_R_EN (1 << 22) + +#define USBHS_EP7_T_EN (1 << 7) +#define USBHS_EP7_R_EN (1 << 23) + +#define USBHS_EP8_T_EN (1 << 8) +#define USBHS_EP8_R_EN (1 << 24) + +#define USBHS_EP9_T_EN (1 << 9) +#define USBHS_EP9_R_EN (1 << 25) + +#define USBHS_EP10_T_EN (1 << 10) +#define USBHS_EP10_R_EN (1 << 26) + +#define USBHS_EP11_T_EN (1 << 11) +#define USBHS_EP11_R_EN (1 << 27) + +#define USBHS_EP12_T_EN (1 << 12) +#define USBHS_EP12_R_EN (1 << 28) + +#define USBHS_EP13_T_EN (1 << 13) +#define USBHS_EP13_R_EN (1 << 29) + +#define USBHS_EP14_T_EN (1 << 14) +#define USBHS_EP14_R_EN (1 << 30) + +#define USBHS_EP15_T_EN (1 << 15) +#define USBHS_EP15_R_EN (1 << 31) + +//UEP_TYPE +#define USBHS_UEP_TYPE_OFFSET 0x14 +#define USBHS_EP0_T_TYP (1 << 0) +#define USBHS_EP0_R_TYP (1 << 16) + +#define USBHS_EP1_T_TYP (1 << 1) +#define USBHS_EP1_R_TYP (1 << 17) + +#define USBHS_EP2_T_TYP (1 << 2) +#define USBHS_EP2_R_TYP (1 << 18) + +#define USBHS_EP3_T_TYP (1 << 3) +#define USBHS_EP3_R_TYP (1 << 19) + +#define USBHS_EP4_T_TYP (1 << 4) +#define USBHS_EP4_R_TYP (1 << 20) + +#define USBHS_EP5_T_TYP (1 << 5) +#define USBHS_EP5_R_TYP (1 << 21) + +#define USBHS_EP6_T_TYP (1 << 6) +#define USBHS_EP6_R_TYP (1 << 22) + +#define USBHS_EP7_T_TYP (1 << 7) +#define USBHS_EP7_R_TYP (1 << 23) + +#define USBHS_EP8_T_TYP (1 << 8) +#define USBHS_EP8_R_TYP (1 << 24) + +#define USBHS_EP9_T_TYP (1 << 8) +#define USBHS_EP9_R_TYP (1 << 25) + +#define USBHS_EP10_T_TYP (1 << 10) +#define USBHS_EP10_R_TYP (1 << 26) + +#define USBHS_EP11_T_TYP (1 << 11) +#define USBHS_EP11_R_TYP (1 << 27) + +#define USBHS_EP12_T_TYP (1 << 12) +#define USBHS_EP12_R_TYP (1 << 28) + +#define USBHS_EP13_T_TYP (1 << 13) +#define USBHS_EP13_R_TYP (1 << 29) + +#define USBHS_EP14_T_TYP (1 << 14) +#define USBHS_EP14_R_TYP (1 << 30) + +#define USBHS_EP15_T_TYP (1 << 15) +#define USBHS_EP15_R_TYP (1 << 31) + +/* BUF_MOD UEP1~15 */ +#define USBHS_BUF_MOD_OFFSET 0x18 +#define USBHS_EP0_BUF_MOD (1 << 0) +#define USBHS_EP0_ISO_BUF_MOD (1 << 16) + +#define USBHS_EP1_BUF_MOD (1 << 1) +#define USBHS_EP1_ISO_BUF_MOD (1 << 17) + +#define USBHS_EP2_BUF_MOD (1 << 2) +#define USBHS_EP2_ISO_BUF_MOD (1 << 18) + +#define USBHS_EP3_BUF_MOD (1 << 3) +#define USBHS_EP3_ISO_BUF_MOD (1 << 19) + +#define USBHS_EP4_BUF_MOD (1 << 4) +#define USBHS_EP4_ISO_BUF_MOD (1 << 20) + +#define USBHS_EP5_BUF_MOD (1 << 5) +#define USBHS_EP5_ISO_BUF_MOD (1 << 21) + +#define USBHS_EP6_BUF_MOD (1 << 6) +#define USBHS_EP6_ISO_BUF_MOD (1 << 22) + +#define USBHS_EP7_BUF_MOD (1 << 7) +#define USBHS_EP7_ISO_BUF_MOD (1 << 23) + +#define USBHS_EP8_BUF_MOD (1 << 8) +#define USBHS_EP8_ISO_BUF_MOD (1 << 24) + +#define USBHS_EP9_BUF_MOD (1 << 9) +#define USBHS_EP9_ISO_BUF_MOD (1 << 25) + +#define USBHS_EP10_BUF_MOD (1 << 10) +#define USBHS_EP10_ISO_BUF_MOD (1 << 26) + +#define USBHS_EP11_BUF_MOD (1 << 11) +#define USBHS_EP11_ISO_BUF_MOD (1 << 27) + +#define USBHS_EP12_BUF_MOD (1 << 12) +#define USBHS_EP12_ISO_BUF_MOD (1 << 28) + +#define USBHS_EP13_BUF_MOD (1 << 13) +#define USBHS_EP13_ISO_BUF_MOD (1 << 29) + +#define USBHS_EP14_BUF_MOD (1 << 14) +#define USBHS_EP14_ISO_BUF_MOD (1 << 30) + +#define USBHS_EP15_BUF_MOD (1 << 15) +#define USBHS_EP15_ISO_BUF_MOD (1 << 31) +//USBHS_EPn_T_EN USBHS_EPn_R_EN USBHS_EPn_BUF_MOD 锟斤拷锟斤拷锟斤拷锟斤拷UEPn_DMA为锟斤拷始锟斤拷址锟缴碉拷锟斤拷锟斤拷锟斤拷锟� +// 0 0 x 锟剿点被锟斤拷锟矫ｏ拷未锟矫碉拷UEPn_*_DMA锟斤拷锟斤拷锟斤拷锟斤拷 +// 1 0 0 锟斤拷锟秸ｏ拷OUT锟斤拷锟斤拷锟斤拷锟斤拷锟阶碉拷址为UEPn_RX_DMA +// 1 0 1 bUEPn_RX_TOG[0]=0,使锟矫伙拷锟斤拷锟斤拷UEPn_RX_DMA锟斤拷bUEPn_RX_TOG[0]=1,使锟矫伙拷锟斤拷锟斤拷UEPn_TX_DMA +// 0 1 0 锟斤拷锟斤拷(IN)锟斤拷锟斤拷锟斤拷锟阶碉拷址为UEPn_TX_DMA锟斤拷 +// 0 1 1 bUEPn_TX_TOG[0]=0,使锟矫伙拷锟斤拷锟斤拷UEPn_TX_DMA锟斤拷bUEPn_TX_TOG[0]=1,使锟矫伙拷锟斤拷锟斤拷UEPn_RX_DMA + +/* USB0_DMA */ +#define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address + +/* USBX_RX_DMA */ +#define USBHS_UEPx_RX_DMA_OFFSET(n) (0x1C + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_TX_DMA_OFFSET(n) (0x58 + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_MAX_LEN_OFFSET(n) (0x98 + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_T_LEN_OFFSET(n) (0xD8 + 4 * (n)) // endpoint x DMA buffer address +#define USBHS_UEPx_TX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 2) // endpoint x DMA buffer address +#define USBHS_UEPx_RX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 3) // endpoint x DMA buffer address + +// UEPn_T_LEN +#define USBHS_EP_T_LEN_MASK (0x7FF) + +//UEPn_TX_CTRL +#define USBHS_EP_T_RES_MASK (3 << 0) +#define USBHS_EP_T_RES_ACK (0 << 0) +#define USBHS_EP_T_RES_NYET (1 << 0) +#define USBHS_EP_T_RES_NAK (2 << 0) +#define USBHS_EP_T_RES_STALL (3 << 0) + +#define USBHS_EP_T_TOG_MASK (3 << 3) +#define USBHS_EP_T_TOG_0 (0 << 3) +#define USBHS_EP_T_TOG_1 (1 << 3) +#define USBHS_EP_T_TOG_2 (2 << 3) +#define USBHS_EP_T_TOG_M (3 << 3) + +#define USBHS_EP_T_AUTOTOG (1 << 5) + +//UEPn_RX_CTRL +#define USBHS_EP_R_RES_MASK (3 << 0) +#define USBHS_EP_R_RES_ACK (0 << 0) +#define USBHS_EP_R_RES_NYET (1 << 0) +#define USBHS_EP_R_RES_NAK (2 << 0) +#define USBHS_EP_R_RES_STALL (3 << 0) + +#define USBHS_EP_R_TOG_MASK (3 << 3) +#define USBHS_EP_R_TOG_0 (0 << 3) +#define USBHS_EP_R_TOG_1 (1 << 3) +#define USBHS_EP_R_TOG_2 (2 << 3) +#define USBHS_EP_R_TOG_M (3 << 3) + +#define USBHS_EP_R_AUTOTOG (1 << 5) + +#define USBHS_TOG_MATCH (1 << 6) + +/******************* HOST ******************/ +// USB HOST_CTRL +#define USBHS_SEND_BUS_RESET (1 << 0) +#define USBHS_SEND_BUS_SUSPEND (1 << 1) +#define USBHS_SEND_BUS_RESUME (1 << 2) +#define USBHS_REMOTE_WAKE (1 << 3) +#define USBHS_PHY_SUSPENDM (1 << 4) +#define USBHS_UH_SOFT_FREE (1 << 6) +#define USBHS_SEND_SOF_EN (1 << 7) + +//UH_CONFIG +#define USBHS_HOST_TX_EN (1 << 3) +#define USBHS_HOST_RX_EN (1 << 18) + +// HOST_EP_TYPE +#define USBHS_ENDP_TX_ISO (1 << 3) +#define USBHS_ENDP_RX_ISO (1 << (16 + 2)) + +// R32_UH_EP_PID +#define USBHS_HOST_MASK_TOKEN (0x0f) +#define USBHS_HOST_MASK_ENDP (0x0f << 4) + +//R8_UH_RX_CTRL +#define USBHS_EP_R_RES_MASK (3 << 0) +#define USBHS_EP_R_RES_ACK (0 << 0) +#define USBHS_EP_R_RES_NYET (1 << 0) +#define USBHS_EP_R_RES_NAK (2 << 0) +#define USBHS_EP_R_RES_STALL (3 << 0) + +#define USBHS_UH_R_RES_NO (1 << 2) +#define USBHS_UH_R_TOG_1 (1 << 3) +#define USBHS_UH_R_TOG_2 (2 << 3) +#define USBHS_UH_R_TOG_3 (3 << 3) +#define USBHS_UH_R_TOG_AUTO (1 << 5) +#define USBHS_UH_R_DATA_NO (1 << 6) +//R8_UH_TX_CTRL +#define USBHS_UH_T_RES_MASK (3 << 0) +#define USBHS_UH_T_RES_ACK (0 << 0) +#define USBHS_UH_T_RES_NYET (1 << 0) +#define USBHS_UH_T_RES_NAK (2 << 0) +#define USBHS_UH_T_RES_STALL (3 << 0) + +#define USBHS_UH_T_RES_NO (1 << 2) +#define USBHS_UH_T_TOG_1 (1 << 3) +#define USBHS_UH_T_TOG_2 (2 << 3) +#define USBHS_UH_T_TOG_3 (3 << 3) +#define USBHS_UH_T_TOG_AUTO (1 << 5) +#define USBHS_UH_T_DATA_NO (1 << 6) + +// 00: OUT, 01:SOF, 10:IN, 11:SETUP +#define PID_OUT 0 +#define PID_SOF 1 +#define PID_IN 2 +#define PID_SETUP 3 + +#endif diff --git a/src/portable/wch/ch32v307/usb_dc_usbhs.c b/src/portable/wch/ch32v307/usb_dc_usbhs.c new file mode 100644 index 000000000..32645dc5f --- /dev/null +++ b/src/portable/wch/ch32v307/usb_dc_usbhs.c @@ -0,0 +1,388 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2022 Greg Davill + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_CH32VF307) +#include "device/dcd.h" + +#include "usb_ch32_usbhs_reg.h" +#include "core_riscv.h" + +// Max number of bi-directional endpoints including EP0 +#define EP_MAX 16 + +typedef struct { + uint8_t *buffer; + // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API + uint16_t total_len; + uint16_t queued_len; + uint16_t max_size; + bool short_packet; +} xfer_ctl_t; + +#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] +static xfer_ctl_t xfer_status[EP_MAX][2]; + +#define EP_TX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_TX_LEN) + (ep)*2) +#define EP_TX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_TX_CTRL) + (ep)*4) +#define EP_RX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_RX_CTRL) + (ep)*4) +#define EP_RX_MAX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_MAX_LEN) + (ep)*2) + +#define EP_TX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_TX_DMA) + (ep - 1)) +#define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1)) + +/* Endpoint Buffer */ +__attribute__((aligned(4))) uint8_t setup[8]; // ep0(64) +__attribute__((aligned(4))) uint8_t EP0_DatabufHD[64]; // ep0(64) + +volatile uint8_t mps_over_flag = 0; +volatile uint8_t USBHS_Dev_Endp0_Tog = 0x01; + +void dcd_init(uint8_t rhport) { + (void)rhport; + + memset(&xfer_status, 0, sizeof(xfer_status)); + + // usb_dc_low_level_init(); + + USBHSD->HOST_CTRL = 0x00; + USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM; + + USBHSD->CONTROL = 0; +#if 1 + USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED; +#else + USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED; +#endif + + USBHSD->INT_EN = 0; + USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN | USBHS_SUSPEND_EN; + + /* ALL endpoint enable */ + USBHSD->ENDP_CONFIG = 0xffffffff; + + USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN; + USBHSD->ENDP_TYPE = 0x00; + USBHSD->BUF_MODE = 0x00; + + USBHSD->UEP0_MAX_LEN = 64; + + USBHSD->UEP0_DMA = (uint32_t)EP0_DatabufHD; + + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_NAK; + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + + for (int ep = 1; ep < EP_MAX; ep++) { + EP_TX_LEN(ep) = 0; + EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK; + EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK; + + EP_RX_MAX_LEN(ep) = 512; + } + + USBHSD->DEV_AD = 0; + USBHSD->CONTROL |= USBHS_DEV_PU_EN; +} + +void dcd_int_enable(uint8_t rhport) { + (void)rhport; + + NVIC_EnableIRQ(USBHS_IRQn); +} + +void dcd_int_disable(uint8_t rhport) { + (void)rhport; + + NVIC_DisableIRQ(USBHS_IRQn); +} + +void dcd_edpt_close_all(uint8_t rhport) { + (void)rhport; +} + +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { + (void)dev_addr; + + // Response with zlp status + dcd_edpt_xfer(rhport, 0x80, NULL, 0); +} + +void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) { + (void)rhport; + + if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && + request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && + request->bRequest == TUSB_REQ_SET_ADDRESS) { + USBHSD->DEV_AD = (uint8_t)request->wValue; + } + + EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK; + EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK; +} + +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) { + (void)rhport; + + uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); + + TU_ASSERT(epnum < EP_MAX); + + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->max_size = tu_edpt_packet_size(desc_edpt); + + if (epnum != 0) { + if (tu_edpt_dir(desc_edpt->bEndpointAddress) == TUSB_DIR_OUT) { + EP_RX_CTRL(epnum) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_ACK; + } else { + EP_TX_LEN(epnum) = 0; + EP_TX_CTRL(epnum) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0; + } + } + + return true; +} + +int usbd_ep_close(const uint8_t ep) { + (void)ep; + + return 0; +} +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { + (void)rhport; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if (epnum == 0) { + if (dir == TUSB_DIR_OUT) { + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_STALL; + } else { + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_STALL; + } + } else { + if (dir == TUSB_DIR_OUT) { + EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_STALL; + + } else { + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~USBHS_EP_T_RES_MASK) | USBHS_EP_T_RES_STALL; + } + } +} + +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { + (void)rhport; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if (epnum == 0) { + if (dir == TUSB_DIR_OUT) { + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + } else { + } + } else { + if (dir == TUSB_DIR_OUT) { + EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~(USBHS_EP_R_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_ACK; + + } else { + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_NAK; + } + } +} + +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { + (void)rhport; + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = buffer; + // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API + xfer->total_len = total_bytes; + xfer->queued_len = 0; + xfer->short_packet = false; + + // uint16_t num_packets = (total_bytes / xfer->max_size); + uint16_t short_packet_size = total_bytes % (xfer->max_size + 1); + + // Zero-size packet is special case. + if (short_packet_size == 0 || (total_bytes == 0)) { + xfer->short_packet = true; + } + + if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) { + if (!total_bytes) { + xfer->short_packet = true; + if (epnum == 0) { + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); + USBHS_Dev_Endp0_Tog ^= 1; + } else { + EP_TX_LEN(epnum) = 0; + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK; + } + } else { + if (epnum == 0) { + xfer->queued_len += short_packet_size; + memcpy(&EP0_DatabufHD[0], buffer, short_packet_size); + + USBHSD->UEP0_TX_LEN = short_packet_size; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); + USBHS_Dev_Endp0_Tog ^= 1; + } else { + xfer->queued_len += short_packet_size; + + EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer; + USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum); + EP_TX_LEN(epnum) = short_packet_size; + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK; + } + } + } else { /* TUSB_DIR_OUT */ + if (epnum == 0) { + uint32_t read_count = USBHSD->RX_LEN; + read_count = TU_MIN(read_count, total_bytes); + + if ((total_bytes == 8)) { + read_count = 8; + memcpy(buffer, &EP0_DatabufHD[0], 8); + } else { + memcpy(buffer, &EP0_DatabufHD[0], read_count); + } + } else { + EP_RX_DMA_ADDR(epnum) = (uint32_t)xfer->buffer; + USBHSD->ENDP_CONFIG |= (USBHS_EP0_R_EN << epnum); + } + + // usbd_ep_read(ep_addr, buffer, total_bytes, &ret_bytes); + } + return true; +} + + +static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size) { + // xfer->queued_len = xfer->total_len - remaining; + + uint16_t remaining = xfer->total_len - xfer->queued_len; + uint16_t to_recv_size; + + if (remaining <= xfer->max_size) { + // Avoid buffer overflow. + to_recv_size = (xfer_size > remaining) ? remaining : xfer_size; + } else { + // Room for full packet, choose recv_size based on what the microcontroller + // claims. + to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size; + } + + if (to_recv_size) { + } + + xfer->queued_len += xfer_size; + + // Per USB spec, a short OUT packet (including length 0) is always + // indicative of the end of a transfer (at least for ctl, bulk, int). + xfer->short_packet = (xfer_size < xfer->max_size); +} + +void dcd_int_handler(uint8_t rhport) { + (void)rhport; + + uint32_t end_num, rx_token; + uint8_t intflag = 0; + + intflag = USBHSD->INT_FG; + + if (intflag & USBHS_TRANSFER_FLAG) { + + end_num = (USBHSD->INT_ST) & MASK_UIS_ENDP; + rx_token = (((USBHSD->INT_ST) & MASK_UIS_TOKEN) >> 4) & 0x03; + + uint8_t endp = end_num | (rx_token == PID_IN ? TUSB_DIR_IN_MASK : 0); + + xfer_ctl_t *xfer = XFER_CTL_BASE(end_num, tu_edpt_dir(endp)); + + if (rx_token == PID_OUT) { + uint16_t rx_len = USBHSD->RX_LEN; + + receive_packet(xfer, rx_len); + + if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { + xfer->short_packet = false; + + dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true); + } + + if (end_num == 0) { + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0; + } + + } else if (rx_token == PID_IN) { + if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { + xfer->short_packet = false; + xfer->total_len = 0; + dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true); + + EP_TX_CTRL(end_num) = (EP_TX_CTRL(end_num) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_NAK; + + if (end_num == 0) { + } + } else { + dcd_edpt_xfer(0, endp, xfer->buffer + xfer->queued_len, xfer->total_len - xfer->queued_len); + } + } + + USBHSD->INT_FG = USBHS_TRANSFER_FLAG; /* Clear flag */ + } else if (intflag & USBHS_SETUP_FLAG) { + USBHS_Dev_Endp0_Tog = 1; + dcd_event_setup_received(0, EP0_DatabufHD, true); + + USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */ + } else if (intflag & USBHS_DETECT_FLAG) { + USBHS_Dev_Endp0_Tog = 1; + + xfer_status[0][TUSB_DIR_OUT].max_size = 64; + xfer_status[0][TUSB_DIR_IN].max_size = 64; + + dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true); + + USBHSD->DEV_AD = 0; + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0; + + USBHSD->INT_FG = USBHS_DETECT_FLAG; /* Clear flag */ + } else if (intflag & USBHS_SUSPEND_FLAG) { + dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SUSPEND }; + dcd_event_handler(&event, true); + + USBHSD->INT_FG = USBHS_SUSPEND_FLAG; /* Clear flag */ + } +} + +#endif \ No newline at end of file diff --git a/src/tusb_option.h b/src/tusb_option.h index bd87a953c..ffeec2241 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -149,6 +149,9 @@ // Allwinner #define OPT_MCU_F1C100S 2100 ///< Allwinner F1C100s family +// WCH +#define OPT_MCU_CH32VF307 2200 ///< WCH CH32V307 config + // Helper to check if configured MCU is one of listed // Apply _TU_CHECK_MCU with || as separator to list of input #define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m) -- cgit v1.3.1 From a09c1648f56580bcdb59b08af255442d9240281c Mon Sep 17 00:00:00 2001 From: Greg Davill Date: Tue, 22 Mar 2022 23:31:20 +1030 Subject: Fix typo --- hw/bsp/ch32v307/family.mk | 2 +- src/common/tusb_mcu.h | 2 +- src/portable/wch/ch32v307/usb_dc_usbhs.c | 2 +- src/tusb_option.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk index dfb4853d9..ef2af26e6 100644 --- a/hw/bsp/ch32v307/family.mk +++ b/hw/bsp/ch32v307/family.mk @@ -28,7 +28,7 @@ CFLAGS += \ -ffunction-sections \ -fdata-sections \ -nostdlib -nostartfiles \ - -DCFG_TUSB_MCU=OPT_MCU_CH32VF307 \ + -DCFG_TUSB_MCU=OPT_MCU_CH32V307 \ -Xlinker --gc-sections \ -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 84d629eac..9de092e34 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -267,7 +267,7 @@ #define TUP_DCD_ENDPOINT_MAX 4 //------------- WCH -------------// -#elif TU_CHECK_MCU(OPT_MCU_CH32VF307) +#elif TU_CHECK_MCU(OPT_MCU_CH32V307) #define TUP_DCD_ENDPOINT_MAX 8 #endif diff --git a/src/portable/wch/ch32v307/usb_dc_usbhs.c b/src/portable/wch/ch32v307/usb_dc_usbhs.c index 32645dc5f..3a2c9979e 100644 --- a/src/portable/wch/ch32v307/usb_dc_usbhs.c +++ b/src/portable/wch/ch32v307/usb_dc_usbhs.c @@ -26,7 +26,7 @@ #include "tusb_option.h" -#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_CH32VF307) +#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_CH32V307) #include "device/dcd.h" #include "usb_ch32_usbhs_reg.h" diff --git a/src/tusb_option.h b/src/tusb_option.h index ffeec2241..28bf8a60d 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -150,7 +150,7 @@ #define OPT_MCU_F1C100S 2100 ///< Allwinner F1C100s family // WCH -#define OPT_MCU_CH32VF307 2200 ///< WCH CH32V307 config +#define OPT_MCU_CH32V307 2200 ///< WCH CH32V307 config // Helper to check if configured MCU is one of listed // Apply _TU_CHECK_MCU with || as separator to list of input -- cgit v1.3.1 From 325923b6c61d0a914a0c6f78e650c6b85fbd13d2 Mon Sep 17 00:00:00 2001 From: Greg Davill Date: Tue, 22 Mar 2022 23:40:54 +1030 Subject: Update comments about endpoint buffer modes --- src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h b/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h index 1b7c0e791..5a2c1fbc9 100644 --- a/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h +++ b/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h @@ -231,12 +231,12 @@ #define USBHS_EP15_BUF_MOD (1 << 15) #define USBHS_EP15_ISO_BUF_MOD (1 << 31) -//USBHS_EPn_T_EN USBHS_EPn_R_EN USBHS_EPn_BUF_MOD 锟斤拷锟斤拷锟斤拷锟斤拷UEPn_DMA为锟斤拷始锟斤拷址锟缴碉拷锟斤拷锟斤拷锟斤拷锟� -// 0 0 x 锟剿点被锟斤拷锟矫ｏ拷未锟矫碉拷UEPn_*_DMA锟斤拷锟斤拷锟斤拷锟斤拷 -// 1 0 0 锟斤拷锟秸ｏ拷OUT锟斤拷锟斤拷锟斤拷锟斤拷锟阶碉拷址为UEPn_RX_DMA -// 1 0 1 bUEPn_RX_TOG[0]=0,使锟矫伙拷锟斤拷锟斤拷UEPn_RX_DMA锟斤拷bUEPn_RX_TOG[0]=1,使锟矫伙拷锟斤拷锟斤拷UEPn_TX_DMA -// 0 1 0 锟斤拷锟斤拷(IN)锟斤拷锟斤拷锟斤拷锟阶碉拷址为UEPn_TX_DMA锟斤拷 -// 0 1 1 bUEPn_TX_TOG[0]=0,使锟矫伙拷锟斤拷锟斤拷UEPn_TX_DMA锟斤拷bUEPn_TX_TOG[0]=1,使锟矫伙拷锟斤拷锟斤拷UEPn_RX_DMA +//USBHS_EPn_T_EN USBHS_EPn_R_EN USBHS_EPn_BUF_MOD Description: Arrange from low to high with UEPn_DMA as the starting address +// 0 0 x The endpoint is disabled and the UEPn_*_DMA buffers are not used. +// 1 0 0 The first address of the receive (OUT) buffer is UEPn_RX_DMA +// 1 0 1 RB_UEPn_RX_TOG[0]=0, use buffer UEPn_RX_DMA RB_UEPn_RX_TOG[0]=1, use buffer UEPn_TX_DMA +// 0 1 0 The first address of the transmit (IN) buffer is UEPn_TX_DMA. +// 0 1 1 RB_UEPn_TX_TOG[0]=0, use buffer UEPn_TX_DMA RB_UEPn_TX_TOG[0]=1, use buffer UEPn_RX_DMA /* USB0_DMA */ #define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address -- cgit v1.3.1 From cdb8a1a2a1dd863f35fd91d58c18ec83115f9326 Mon Sep 17 00:00:00 2001 From: Greg Davill Date: Wed, 23 Mar 2022 00:00:06 +1030 Subject: Clean up driver --- src/common/tusb_mcu.h | 2 +- src/portable/wch/ch32v307/usb_dc_usbhs.c | 10 ++++------ 2 files changed, 5 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 9de092e34..fb0cdd361 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -268,7 +268,7 @@ //------------- WCH -------------// #elif TU_CHECK_MCU(OPT_MCU_CH32V307) - #define TUP_DCD_ENDPOINT_MAX 8 + #define TUP_DCD_ENDPOINT_MAX 16 #endif diff --git a/src/portable/wch/ch32v307/usb_dc_usbhs.c b/src/portable/wch/ch32v307/usb_dc_usbhs.c index 3a2c9979e..e647389ee 100644 --- a/src/portable/wch/ch32v307/usb_dc_usbhs.c +++ b/src/portable/wch/ch32v307/usb_dc_usbhs.c @@ -56,10 +56,8 @@ static xfer_ctl_t xfer_status[EP_MAX][2]; #define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1)) /* Endpoint Buffer */ -__attribute__((aligned(4))) uint8_t setup[8]; // ep0(64) -__attribute__((aligned(4))) uint8_t EP0_DatabufHD[64]; // ep0(64) +TU_ATTR_ALIGNED(4) uint8_t EP0_DatabufHD[64]; // ep0(64) -volatile uint8_t mps_over_flag = 0; volatile uint8_t USBHS_Dev_Endp0_Tog = 0x01; void dcd_init(uint8_t rhport) { @@ -67,15 +65,15 @@ void dcd_init(uint8_t rhport) { memset(&xfer_status, 0, sizeof(xfer_status)); - // usb_dc_low_level_init(); - USBHSD->HOST_CTRL = 0x00; USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM; USBHSD->CONTROL = 0; -#if 1 + +#if (BOARD_DEVICE_RHPORT_SPEED == OPT_MODE_HIGH_SPEED) USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED; #else + #error OPT_MODE_FULL_SPEED not currently supported on CH32V307 USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED; #endif -- cgit v1.3.1 From 16c13bc110fb0959e704b417706dd303afc69981 Mon Sep 17 00:00:00 2001 From: Skyler Mansfield Date: Sun, 17 Apr 2022 01:16:49 +0100 Subject: tusb_types: Added descriptive strings for edpt_dir and edpt_type --- src/common/tusb_types.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src') diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index e2fa17532..7eab396ef 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -513,6 +513,16 @@ static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep) return tu_le16toh(desc_ep->wMaxPacketSize) & TU_GENMASK(10, 0); } +static inline const char *tu_edpt_dir_str(tusb_dir_t dir) { + static const char *str[] = {"out", "in"}; + return str[dir]; +} + +static inline const char *tu_edpt_type_str(tusb_xfer_type_t t) { + static const char *str[] = {"control", "isochronous", "bulk", "interrupt"}; + return str[t]; +} + //--------------------------------------------------------------------+ // Descriptor helper //--------------------------------------------------------------------+ -- cgit v1.3.1 From 35668fc523c7c972bf91f32dbb3b50ad8b4f3c74 Mon Sep 17 00:00:00 2001 From: Skyler Mansfield Date: Sun, 17 Apr 2022 01:30:03 +0100 Subject: hcd_rp2040: Add bulk in/out+interrupt out support. Added support for allocating hw_endpoints for non-interrupt endpoints. Allow endpoints to be used in either direction by updating bit checks. --- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 33 ++++++++++++++++++---------- 1 file changed, 21 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 234bea203..0c7a5220d 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -139,16 +139,20 @@ static void hw_handle_buff_status(void) for (uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++) { // EPX is bit 0 - // IEP1 is bit 2 - // IEP2 is bit 4 - // IEP3 is bit 6 + // IEP1 IN is bit 2 + // IEP1 OUT is bit 3 + // IEP2 IN is bit 4 + // IEP2 OUT is bit 5 + // IEP3 IN is bit 6 + // IEP3 OUT is bit 7 // etc - bit = 1 << (i*2); - - if (remaining_buffers & bit) - { - remaining_buffers &= ~bit; - _handle_buff_status_bit(bit, &ep_pool[i]); + for(int j = 0; j < 2; j++){ + bit = 1 << (i*2+j); + if (remaining_buffers & bit) + { + remaining_buffers &= ~bit; + _handle_buff_status_bit(bit, &ep_pool[i]); + } } } @@ -259,10 +263,10 @@ static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type) { struct hw_endpoint *ep = NULL; - if (transfer_type == TUSB_XFER_INTERRUPT) + if (transfer_type != TUSB_XFER_CONTROL) { ep = _next_free_interrupt_ep(); - pico_info("Allocate interrupt ep %d\n", ep->interrupt_num); + pico_info("Allocate %s ep %d\n", tu_edpt_type_str(transfer_type), ep->interrupt_num); assert(ep); ep->buffer_control = &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl; ep->endpoint_control = &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl; @@ -320,8 +324,9 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg); ep->configured = true; - if (bmInterval) + if (ep != &epx) { + // Endpoint has its own addr_endp and interrupt bits to be setup! // This is an interrupt endpoint // so need to set up interrupt endpoint address control register with: // device address @@ -492,6 +497,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * // Get appropriate ep. Either EPX or interrupt endpoint struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr); assert(ep); + // Should we maybe be able to check if endpt is busy/active instead? + if(ep->active) + return false; // Control endpoint can change direction 0x00 <-> 0x80 if ( ep_addr != ep->ep_addr ) @@ -535,6 +543,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet // Configure EP0 struct with setup info for the trans complete struct hw_endpoint *ep = _hw_endpoint_allocate(0); + assert(ep == &epx); // EP0 out _hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0); -- cgit v1.3.1 From dcadbf3364778814c8a0e7e73481d12e8687f1bd Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Tue, 8 Mar 2022 16:05:29 +0000 Subject: rename renesas driver to link link was chosen according to the name for the usb core on datasheets, LINK core Signed-off-by: Rafael Silva --- docs/reference/supported.rst | 6 +- hw/bsp/rx/family.mk | 4 +- src/portable/renesas/link/dcd_link.c | 915 +++++++++++++++++++++++++++++++++++ src/portable/renesas/link/hcd_link.c | 875 +++++++++++++++++++++++++++++++++ src/portable/renesas/usba/dcd_usba.c | 915 ----------------------------------- src/portable/renesas/usba/hcd_usba.c | 875 --------------------------------- 6 files changed, 1795 insertions(+), 1795 deletions(-) create mode 100644 src/portable/renesas/link/dcd_link.c create mode 100644 src/portable/renesas/link/hcd_link.c delete mode 100644 src/portable/renesas/usba/dcd_usba.c delete mode 100644 src/portable/renesas/usba/hcd_usba.c (limited to 'src') diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index 7ce982713..3c1b94623 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -59,9 +59,9 @@ Supported MCUs | | | 55 | ✔ | | ✔ | lpc_ip3511 | | +--------------+---------+-------------+--------+------+-----------+-------------------+--------------+ | Raspberry Pi | RP2040 | ✔ | ✔ | ✖ | rp2040 | | -+--------------+-----------------------+--------+------+-----------+-------------------+--------------+ -| Renesas | RX 63N, 65N, 72N | ✔ | ✔ | ✖ | usba | | -+--------------+-----------------------+--------+------+-----------+-------------------+--------------+ ++--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+ +| Renesas | RX | 63N, 65N, 72N | ✔ | ✔ | ✖ | link | | ++--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+ | Silabs | EFM32GG12 | ✔ | | ✖ | dwc2 | | +--------------+-----------------------+--------+------+-----------+-------------------+--------------+ | Sony | CXD56 | ✔ | ✖ | ✔ | cxd56 | | diff --git a/hw/bsp/rx/family.mk b/hw/bsp/rx/family.mk index aba05812d..22b9031b3 100644 --- a/hw/bsp/rx/family.mk +++ b/hw/bsp/rx/family.mk @@ -14,8 +14,8 @@ CFLAGS += \ -DSSIZE_MAX=__INT_MAX__ SRC_C += \ - src/portable/renesas/usba/dcd_usba.c \ - src/portable/renesas/usba/hcd_usba.c \ + src/portable/renesas/link/dcd_link.c \ + src/portable/renesas/link/hcd_link.c \ $(MCU_DIR)/vects.c INC += \ diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c new file mode 100644 index 000000000..fa87c9f4d --- /dev/null +++ b/src/portable/renesas/link/dcd_link.c @@ -0,0 +1,915 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Koji Kitayama + * Portions copyrighted (c) 2021 Roland Winistoerfer + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) +// We disable SOF for now until needed later on +#define USE_SOF 0 + +#if CFG_TUD_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \ + CFG_TUSB_MCU == OPT_MCU_RX65X || \ + CFG_TUSB_MCU == OPT_MCU_RX72N ) +#include "device/dcd.h" +#include "iodefine.h" + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ +#define SYSTEM_PRCR_PRC1 (1<<1) +#define SYSTEM_PRCR_PRKEY (0xA5u<<8) + +#define USB_FIFOSEL_TX ((uint16_t)(1u<<5)) +#define USB_FIFOSEL_BIGEND ((uint16_t)(1u<<8)) +#define USB_FIFOSEL_MBW_8 ((uint16_t)(0u<<10)) +#define USB_FIFOSEL_MBW_16 ((uint16_t)(1u<<10)) +#define USB_IS0_CTSQ ((uint16_t)(7u)) +#define USB_IS0_DVSQ ((uint16_t)(7u<<4)) +#define USB_IS0_VALID ((uint16_t)(1u<<3)) +#define USB_IS0_BRDY ((uint16_t)(1u<<8)) +#define USB_IS0_NRDY ((uint16_t)(1u<<9)) +#define USB_IS0_BEMP ((uint16_t)(1u<<10)) +#define USB_IS0_CTRT ((uint16_t)(1u<<11)) +#define USB_IS0_DVST ((uint16_t)(1u<<12)) +#define USB_IS0_SOFR ((uint16_t)(1u<<13)) +#define USB_IS0_RESM ((uint16_t)(1u<<14)) +#define USB_IS0_VBINT ((uint16_t)(1u<<15)) +#define USB_IS1_SACK ((uint16_t)(1u<<4)) +#define USB_IS1_SIGN ((uint16_t)(1u<<5)) +#define USB_IS1_EOFERR ((uint16_t)(1u<<6)) +#define USB_IS1_ATTCH ((uint16_t)(1u<<11)) +#define USB_IS1_DTCH ((uint16_t)(1u<<12)) +#define USB_IS1_BCHG ((uint16_t)(1u<<14)) +#define USB_IS1_OVRCR ((uint16_t)(1u<<15)) + +#define USB_IS0_CTSQ_MSK (7u) +#define USB_IS0_CTSQ_SETUP (1u) +#define USB_IS0_DVSQ_DEF (1u<<4) +#define USB_IS0_DVSQ_ADDR (2u<<4) +#define USB_IS0_DVSQ_SUSP0 (4u<<4) +#define USB_IS0_DVSQ_SUSP1 (5u<<4) +#define USB_IS0_DVSQ_SUSP2 (6u<<4) +#define USB_IS0_DVSQ_SUSP3 (7u<<4) + +#define USB_PIPECTR_PID_NAK (0u) +#define USB_PIPECTR_PID_BUF (1u) +#define USB_PIPECTR_PID_STALL (2u) +#define USB_PIPECTR_CCPL (1u<<2) +#define USB_PIPECTR_SQMON (1u<<6) +#define USB_PIPECTR_SQCLR (1u<<8) +#define USB_PIPECTR_ACLRM (1u<<9) +#define USB_PIPECTR_INBUFM (1u<<14) +#define USB_PIPECTR_BSTS (1u<<15) + +#define USB_FIFOCTR_DTLN (0x1FF) +#define USB_FIFOCTR_FRDY (1u<<13) +#define USB_FIFOCTR_BCLR (1u<<14) +#define USB_FIFOCTR_BVAL (1u<<15) + +#define USB_PIPECFG_SHTNAK (1u<<7) +#define USB_PIPECFG_DBLB (1u<<9) +#define USB_PIPECFG_BULK (1u<<14) +#define USB_PIPECFG_ISO (3u<<14) +#define USB_PIPECFG_INT (2u<<14) + +#define FIFO_REQ_CLR (1u) +#define FIFO_COMPLETE (1u<<1) + +// Start of definition of packed structs (used by the CCRX toolchain) +TU_ATTR_PACKED_BEGIN +TU_ATTR_BIT_FIELD_ORDER_BEGIN + +typedef struct { + union { + struct { + uint16_t : 8; + uint16_t TRCLR: 1; + uint16_t TRENB: 1; + uint16_t : 0; + }; + uint16_t TRE; + }; + uint16_t TRN; +} reg_pipetre_t; + +typedef union { + struct { + volatile uint16_t u8: 8; + volatile uint16_t : 0; + }; + volatile uint16_t u16; +} hw_fifo_t; + +typedef struct TU_ATTR_PACKED +{ + void *buf; /* the start address of a transfer data buffer */ + uint16_t length; /* the number of bytes in the buffer */ + uint16_t remaining; /* the number of bytes remaining in the buffer */ + struct { + uint32_t ep : 8; /* an assigned endpoint address */ + uint32_t ff : 1; /* `buf` is TU_FUFO or POD */ + uint32_t : 0; + }; +} pipe_state_t; + +TU_ATTR_PACKED_END // End of definition of packed structs (used by the CCRX toolchain) +TU_ATTR_BIT_FIELD_ORDER_END + +typedef struct +{ + pipe_state_t pipe[10]; + uint8_t ep[2][16]; /* a lookup table for a pipe index from an endpoint address */ +} dcd_data_t; + +//--------------------------------------------------------------------+ +// INTERNAL OBJECT & FUNCTION DECLARATION +//--------------------------------------------------------------------+ +static dcd_data_t _dcd; + +static uint32_t disable_interrupt(void) +{ + uint32_t pswi; +#if defined(__CCRX__) + pswi = get_psw() & 0x010000; + clrpsw_i(); +#else + pswi = __builtin_rx_mvfc(0) & 0x010000; + __builtin_rx_clrpsw('I'); +#endif + return pswi; +} + +static void enable_interrupt(uint32_t pswi) +{ +#if defined(__CCRX__) + set_psw(get_psw() | pswi); +#else + __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi); +#endif +} + +static unsigned find_pipe(unsigned xfer) +{ + switch (xfer) { + case TUSB_XFER_ISOCHRONOUS: + for (int i = 1; i <= 2; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + break; + case TUSB_XFER_BULK: + for (int i = 3; i <= 5; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + for (int i = 1; i <= 1; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + break; + case TUSB_XFER_INTERRUPT: + for (int i = 6; i <= 9; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + break; + default: + /* No support for control transfer */ + break; + } + return 0; +} + +static volatile uint16_t* get_pipectr(unsigned num) +{ + volatile uint16_t *ctr = NULL; + if (num) { + ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD; + ctr += num - 1; + } else { + ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD; + } + return ctr; +} + +static volatile reg_pipetre_t* get_pipetre(unsigned num) +{ + volatile reg_pipetre_t* tre = NULL; + if ((1 <= num) && (num <= 5)) { + tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD; + tre += num - 1; + } + return tre; +} + +static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr) +{ + (void)rhport; + volatile uint16_t *ctr = NULL; + const unsigned epn = tu_edpt_number(ep_addr); + if (epn) { + const unsigned dir = tu_edpt_dir(ep_addr); + const unsigned num = _dcd.ep[dir][epn]; + if (num) { + ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD; + ctr += num - 1; + } + } else { + ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD; + } + return ctr; +} + +static unsigned edpt0_max_packet_size(void) +{ + return USB0.DCPMAXP.BIT.MXPS; +} + +static unsigned edpt_max_packet_size(unsigned num) +{ + USB0.PIPESEL.WORD = num; + return USB0.PIPEMAXP.WORD; +} + +static inline void pipe_wait_for_ready(unsigned num) +{ + while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ; + while (!USB0.D0FIFOCTR.BIT.FRDY) ; +} + +static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) +{ + volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo; + uintptr_t addr = (uintptr_t)buf; + while (len >= 2) { + reg->u16 = *(const uint16_t *)addr; + addr += 2; + len -= 2; + } + if (len) { + reg->u8 = *(const uint8_t *)addr; + ++addr; + } +} + +static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) +{ + uint8_t *p = (uint8_t*)buf; + volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ + while (len--) *p++ = *reg; +} + +static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) +{ + static const struct { + void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info); + void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n); + void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len); + } ops[] = { + /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet}, + /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, + }; + tu_fifo_buffer_info_t info; + ops[dir].tu_fifo_get_info(f, &info); + unsigned total_len = len; + len = TU_MIN(total_len, info.len_lin); + ops[dir].pipe_read_write(info.ptr_lin, fifo, len); + unsigned rem = total_len - len; + if (rem) { + len = TU_MIN(rem, info.len_wrap); + ops[dir].pipe_read_write(info.ptr_wrap, fifo, len); + rem -= len; + } + ops[dir].tu_fifo_advance(f, total_len - rem); +} + +static bool pipe0_xfer_in(void) +{ + pipe_state_t *pipe = &_dcd.pipe[0]; + const unsigned rem = pipe->remaining; + if (!rem) { + pipe->buf = NULL; + return true; + } + const unsigned mps = edpt0_max_packet_size(); + const unsigned len = TU_MIN(mps, rem); + void *buf = pipe->buf; + if (len) { + if (pipe->ff) { + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.CFIFO.WORD, len, TUSB_DIR_IN); + } else { + pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len); + pipe->buf = (uint8_t*)buf + len; + } + } + if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL; + pipe->remaining = rem - len; + return false; +} + +static bool pipe0_xfer_out(void) +{ + pipe_state_t *pipe = &_dcd.pipe[0]; + const unsigned rem = pipe->remaining; + + const unsigned mps = edpt0_max_packet_size(); + const unsigned vld = USB0.CFIFOCTR.BIT.DTLN; + const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + void *buf = pipe->buf; + if (len) { + if (pipe->ff) { + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.CFIFO.WORD, len, TUSB_DIR_OUT); + } else { + pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len); + pipe->buf = (uint8_t*)buf + len; + } + } + if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR; + pipe->remaining = rem - len; + if ((len < mps) || (rem == len)) { + pipe->buf = NULL; + return true; + } + return false; +} + +static bool pipe_xfer_in(unsigned num) +{ + pipe_state_t *pipe = &_dcd.pipe[num]; + const unsigned rem = pipe->remaining; + + if (!rem) { + pipe->buf = NULL; + return true; + } + + USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); + const unsigned mps = edpt_max_packet_size(num); + pipe_wait_for_ready(num); + const unsigned len = TU_MIN(rem, mps); + void *buf = pipe->buf; + if (len) { + if (pipe->ff) { + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.D0FIFO.WORD, len, TUSB_DIR_IN); + } else { + pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len); + pipe->buf = (uint8_t*)buf + len; + } + } + if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL; + USB0.D0FIFOSEL.WORD = 0; + while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + pipe->remaining = rem - len; + return false; +} + +static bool pipe_xfer_out(unsigned num) +{ + pipe_state_t *pipe = &_dcd.pipe[num]; + const unsigned rem = pipe->remaining; + + USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8; + const unsigned mps = edpt_max_packet_size(num); + pipe_wait_for_ready(num); + const unsigned vld = USB0.D0FIFOCTR.BIT.DTLN; + const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + void *buf = pipe->buf; + if (len) { + if (pipe->ff) { + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.D0FIFO.WORD, len, TUSB_DIR_OUT); + } else { + pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len); + pipe->buf = (uint8_t*)buf + len; + } + } + if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR; + USB0.D0FIFOSEL.WORD = 0; + while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + pipe->remaining = rem - len; + if ((len < mps) || (rem == len)) { + pipe->buf = NULL; + return NULL != buf; + } + return false; +} + +static void process_setup_packet(uint8_t rhport) +{ + uint16_t setup_packet[4]; + if (0 == (USB0.INTSTS0.WORD & USB_IS0_VALID)) return; + USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR; + setup_packet[0] = tu_le16toh(USB0.USBREQ.WORD); + setup_packet[1] = USB0.USBVAL; + setup_packet[2] = USB0.USBINDX; + setup_packet[3] = USB0.USBLENG; + USB0.INTSTS0.WORD = ~USB_IS0_VALID; + dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true); +} + +static void process_status_completion(uint8_t rhport) +{ + uint8_t ep_addr; + /* Check the data stage direction */ + if (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) { + /* IN transfer. */ + ep_addr = tu_edpt_addr(0, TUSB_DIR_IN); + } else { + /* OUT transfer. */ + ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT); + } + dcd_event_xfer_complete(rhport, ep_addr, 0, XFER_RESULT_SUCCESS, true); +} + +static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) +{ + /* configure fifo direction and access unit settings */ + if (ep_addr) { /* IN, 2 bytes */ + USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); + while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ; + } else { /* OUT, a byte */ + USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8; + while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ; + } + + pipe_state_t *pipe = &_dcd.pipe[0]; + pipe->ff = buffer_type; + pipe->length = total_bytes; + pipe->remaining = total_bytes; + if (total_bytes) { + pipe->buf = buffer; + if (ep_addr) { /* IN */ + TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80)); + pipe0_xfer_in(); + } + USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF; + } else { + /* ZLP */ + pipe->buf = NULL; + USB0.DCPCTR.WORD = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF; + } + return true; +} + +static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) +{ + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir = tu_edpt_dir(ep_addr); + const unsigned num = _dcd.ep[dir][epn]; + + TU_ASSERT(num); + + pipe_state_t *pipe = &_dcd.pipe[num]; + pipe->ff = buffer_type; + pipe->buf = buffer; + pipe->length = total_bytes; + pipe->remaining = total_bytes; + if (dir) { /* IN */ + if (total_bytes) { + pipe_xfer_in(num); + } else { /* ZLP */ + USB0.D0FIFOSEL.WORD = num; + pipe_wait_for_ready(num); + USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL; + USB0.D0FIFOSEL.WORD = 0; + while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + } + } else { +#if defined(__CCRX__) + __evenaccess volatile reg_pipetre_t *pt = get_pipetre(num); +#else + volatile reg_pipetre_t *pt = get_pipetre(num); +#endif + if (pt) { + const unsigned mps = edpt_max_packet_size(num); + volatile uint16_t *ctr = get_pipectr(num); + if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK; + pt->TRE = TU_BIT(8); + pt->TRN = (total_bytes + mps - 1) / mps; + pt->TRENB = 1; + *ctr = USB_PIPECTR_PID_BUF; + } + } + // TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type); + return true; +} + +static bool process_edpt_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) +{ + const unsigned epn = tu_edpt_number(ep_addr); + if (0 == epn) { + return process_pipe0_xfer(buffer_type, ep_addr, buffer, total_bytes); + } else { + return process_pipe_xfer(buffer_type, ep_addr, buffer, total_bytes); + } +} + +static void process_pipe0_bemp(uint8_t rhport) +{ + bool completed = pipe0_xfer_in(); + if (completed) { + pipe_state_t *pipe = &_dcd.pipe[0]; + dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN), + pipe->length, XFER_RESULT_SUCCESS, true); + } +} + +static void process_pipe_brdy(uint8_t rhport, unsigned num) +{ + pipe_state_t *pipe = &_dcd.pipe[num]; + const unsigned dir = tu_edpt_dir(pipe->ep); + bool completed; + + if (dir) { /* IN */ + completed = pipe_xfer_in(num); + } else { + if (num) { + completed = pipe_xfer_out(num); + } else { + completed = pipe0_xfer_out(); + } + } + if (completed) { + dcd_event_xfer_complete(rhport, pipe->ep, + pipe->length - pipe->remaining, + XFER_RESULT_SUCCESS, true); + // TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining); + } +} + +static void process_bus_reset(uint8_t rhport) +{ + USB0.BEMPENB.WORD = 1; + USB0.BRDYENB.WORD = 1; + USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR; + USB0.D0FIFOSEL.WORD = 0; + while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + USB0.D1FIFOSEL.WORD = 0; + while (USB0.D1FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1CTR.WORD)); + volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1TRE.WORD)); + for (int i = 1; i <= 5; ++i) { + USB0.PIPESEL.WORD = i; + USB0.PIPECFG.WORD = 0; + *ctr = USB_PIPECTR_ACLRM; + *ctr = 0; + ++ctr; + *tre = TU_BIT(8); + tre += 2; + } + for (int i = 6; i <= 9; ++i) { + USB0.PIPESEL.WORD = i; + USB0.PIPECFG.WORD = 0; + *ctr = USB_PIPECTR_ACLRM; + *ctr = 0; + ++ctr; + } + tu_varclr(&_dcd); + dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); +} + +static void process_set_address(uint8_t rhport) +{ + const uint32_t addr = USB0.USBADDR.BIT.USBADDR; + if (!addr) return; + const tusb_control_request_t setup_packet = { +#if defined(__CCRX__) + .bmRequestType = { 0 }, /* Note: CCRX needs the braces over this struct member */ +#else + .bmRequestType = 0, +#endif + .bRequest = TUSB_REQ_SET_ADDRESS, + .wValue = addr, + .wIndex = 0, + .wLength = 0, + }; + dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet, true); +} + +/*------------------------------------------------------------------*/ +/* Device API + *------------------------------------------------------------------*/ +void dcd_init(uint8_t rhport) +{ + (void)rhport; + /* Enable USB0 */ + uint32_t pswi = disable_interrupt(); + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; + MSTP(USB0) = 0; + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; + enable_interrupt(pswi); + USB0.SYSCFG.BIT.SCKE = 1; + while (!USB0.SYSCFG.BIT.SCKE) ; + USB0.SYSCFG.BIT.DRPD = 0; + USB0.SYSCFG.BIT.DCFM = 0; + USB0.SYSCFG.BIT.USBE = 1; + + USB.DPUSR0R.BIT.FIXPHY0 = 0u; /* USB0 Transceiver Output fixed */ +#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) + USB0.PHYSLEW.LONG = 0x5; + IR(PERIB, INTB185) = 0; +#else + IR(USB0, USBI0) = 0; +#endif + + /* Setup default control pipe */ + USB0.DCPMAXP.BIT.MXPS = 64; + USB0.INTENB0.WORD = USB_IS0_VBINT | USB_IS0_BRDY | USB_IS0_BEMP | + USB_IS0_DVST | USB_IS0_CTRT | (USE_SOF ? USB_IS0_SOFR: 0) | USB_IS0_RESM; + USB0.BEMPENB.WORD = 1; + USB0.BRDYENB.WORD = 1; + + if (USB0.INTSTS0.BIT.VBSTS) { + dcd_connect(rhport); + } +} + +void dcd_int_enable(uint8_t rhport) +{ + (void)rhport; +#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) + IEN(PERIB, INTB185) = 1; +#else + IEN(USB0, USBI0) = 1; +#endif +} + +void dcd_int_disable(uint8_t rhport) +{ + (void)rhport; +#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) + IEN(PERIB, INTB185) = 0; +#else + IEN(USB0, USBI0) = 0; +#endif +} + +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) +{ + (void)rhport; + (void)dev_addr; +} + +void dcd_remote_wakeup(uint8_t rhport) +{ + (void)rhport; + USB0.DVSTCTR0.BIT.WKUP = 1; +} + +void dcd_connect(uint8_t rhport) +{ + (void)rhport; + USB0.SYSCFG.BIT.DPRPU = 1; +} + +void dcd_disconnect(uint8_t rhport) +{ + (void)rhport; + USB0.SYSCFG.BIT.DPRPU = 0; +} + +void dcd_sof_enable(uint8_t rhport, bool en) +{ + (void) rhport; + (void) en; + + // TODO implement later +} + +//--------------------------------------------------------------------+ +// Endpoint API +//--------------------------------------------------------------------+ +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) +{ + (void)rhport; + + const unsigned ep_addr = ep_desc->bEndpointAddress; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir = tu_edpt_dir(ep_addr); + const unsigned xfer = ep_desc->bmAttributes.xfer; + + const unsigned mps = tu_edpt_packet_size(ep_desc); + if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) { + /* USBa supports up to 256 bytes */ + return false; + } + + const unsigned num = find_pipe(xfer); + if (!num) return false; + _dcd.pipe[num].ep = ep_addr; + _dcd.ep[dir][epn] = num; + + /* setup pipe */ + dcd_int_disable(rhport); + USB0.PIPESEL.WORD = num; + USB0.PIPEMAXP.WORD = mps; + volatile uint16_t *ctr = get_pipectr(num); + *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR; + *ctr = 0; + unsigned cfg = (dir << 4) | epn; + if (xfer == TUSB_XFER_BULK) { + cfg |= (USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB); + } else if (xfer == TUSB_XFER_INTERRUPT) { + cfg |= USB_PIPECFG_INT; + } else { + cfg |= (USB_PIPECFG_ISO | USB_PIPECFG_DBLB); + } + USB0.PIPECFG.WORD = cfg; + USB0.BRDYSTS.WORD = 0x1FFu ^ TU_BIT(num); + USB0.BRDYENB.WORD |= TU_BIT(num); + if (dir || (xfer != TUSB_XFER_BULK)) { + *ctr = USB_PIPECTR_PID_BUF; + } + // TU_LOG1("O %d %x %x\r\n", USB0.PIPESEL.WORD, USB0.PIPECFG.WORD, USB0.PIPEMAXP.WORD); + dcd_int_enable(rhport); + + return true; +} + +void dcd_edpt_close_all(uint8_t rhport) +{ + unsigned i = TU_ARRAY_SIZE(_dcd.pipe); + dcd_int_disable(rhport); + while (--i) { /* Close all pipes except 0 */ + const unsigned ep_addr = _dcd.pipe[i].ep; + if (!ep_addr) continue; + dcd_edpt_close(rhport, ep_addr); + } + dcd_int_enable(rhport); +} + +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir = tu_edpt_dir(ep_addr); + const unsigned num = _dcd.ep[dir][epn]; + + USB0.BRDYENB.WORD &= ~TU_BIT(num); + volatile uint16_t *ctr = get_pipectr(num); + *ctr = 0; + USB0.PIPESEL.WORD = num; + USB0.PIPECFG.WORD = 0; + _dcd.pipe[num].ep = 0; + _dcd.ep[dir][epn] = 0; +} + +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) +{ + bool r; + dcd_int_disable(rhport); + r = process_edpt_xfer(0, ep_addr, buffer, total_bytes); + dcd_int_enable(rhport); + return r; +} + +bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) +{ + // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1 + TU_ASSERT(ff->item_size == 1); + bool r; + dcd_int_disable(rhport); + r = process_edpt_xfer(1, ep_addr, ff, total_bytes); + dcd_int_enable(rhport); + return r; +} + +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) +{ + volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr); + if (!ctr) return; + dcd_int_disable(rhport); + const uint32_t pid = *ctr & 0x3; + *ctr = pid | USB_PIPECTR_PID_STALL; + *ctr = USB_PIPECTR_PID_STALL; + dcd_int_enable(rhport); +} + +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) +{ + volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr); + if (!ctr) return; + dcd_int_disable(rhport); + *ctr = USB_PIPECTR_SQCLR; + + if (tu_edpt_dir(ep_addr)) { /* IN */ + *ctr = USB_PIPECTR_PID_BUF; + } else { + const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)]; + USB0.PIPESEL.WORD = num; + if (USB0.PIPECFG.BIT.TYPE != 1) { + *ctr = USB_PIPECTR_PID_BUF; + } + } + dcd_int_enable(rhport); +} + +//--------------------------------------------------------------------+ +// ISR +//--------------------------------------------------------------------+ +void dcd_int_handler(uint8_t rhport) +{ + (void)rhport; + + unsigned is0 = USB0.INTSTS0.WORD; + /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ + USB0.INTSTS0.WORD = ~((USB_IS0_CTRT | USB_IS0_DVST | USB_IS0_SOFR | USB_IS0_RESM | USB_IS0_VBINT) & is0) | USB_IS0_VALID; + if (is0 & USB_IS0_VBINT) { + if (USB0.INTSTS0.BIT.VBSTS) { + dcd_connect(rhport); + } else { + dcd_disconnect(rhport); + } + } + if (is0 & USB_IS0_RESM) { + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); +#if (0==USE_SOF) + USB0.INTENB0.BIT.SOFE = 0; +#endif + } + if ((is0 & USB_IS0_SOFR) && USB0.INTENB0.BIT.SOFE) { + // USBD will exit suspended mode when SOF event is received + dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); +#if (0==USE_SOF) + USB0.INTENB0.BIT.SOFE = 0; +#endif + } + if (is0 & USB_IS0_DVST) { + switch (is0 & USB_IS0_DVSQ) { + case USB_IS0_DVSQ_DEF: + process_bus_reset(rhport); + break; + case USB_IS0_DVSQ_ADDR: + process_set_address(rhport); + break; + case USB_IS0_DVSQ_SUSP0: + case USB_IS0_DVSQ_SUSP1: + case USB_IS0_DVSQ_SUSP2: + case USB_IS0_DVSQ_SUSP3: + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); +#if (0==USE_SOF) + USB0.INTENB0.BIT.SOFE = 1; +#endif + default: + break; + } + } + if (is0 & USB_IS0_CTRT) { + if (is0 & USB_IS0_CTSQ_SETUP) { + /* A setup packet has been received. */ + process_setup_packet(rhport); + } else if (0 == (is0 & USB_IS0_CTSQ_MSK)) { + /* A ZLP has been sent/received. */ + process_status_completion(rhport); + } + } + if (is0 & USB_IS0_BEMP) { + const unsigned s = USB0.BEMPSTS.WORD; + USB0.BEMPSTS.WORD = 0; + if (s & 1) { + process_pipe0_bemp(rhport); + } + } + if (is0 & USB_IS0_BRDY) { + const unsigned m = USB0.BRDYENB.WORD; + unsigned s = USB0.BRDYSTS.WORD & m; + /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ + USB0.BRDYSTS.WORD = ~s; + while (s) { +#if defined(__CCRX__) + static const int Mod37BitPosition[] = { + -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4, + 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5, + 20, 8, 19, 18 + }; + + const unsigned num = Mod37BitPosition[(-s & s) % 37]; +#else + const unsigned num = __builtin_ctz(s); +#endif + process_pipe_brdy(rhport, num); + s &= ~TU_BIT(num); + } + } +} + +#endif diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c new file mode 100644 index 000000000..5246ecb94 --- /dev/null +++ b/src/portable/renesas/link/hcd_link.c @@ -0,0 +1,875 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Koji Kitayama + * Portions copyrighted (c) 2021 Roland Winistoerfer + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUH_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \ + CFG_TUSB_MCU == OPT_MCU_RX65X || \ + CFG_TUSB_MCU == OPT_MCU_RX72N ) +#include "host/hcd.h" +#include "iodefine.h" + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ +#define SYSTEM_PRCR_PRC1 (1<<1) +#define SYSTEM_PRCR_PRKEY (0xA5u<<8) + +#define USB_DVSTCTR0_LOW (1u) +#define USB_DVSTCTR0_FULL (2u) + +#define USB_FIFOSEL_TX ((uint16_t)(1u<<5)) +#define USB_FIFOSEL_BIGEND ((uint16_t)(1u<<8)) +#define USB_FIFOSEL_MBW_8 ((uint16_t)(0u<<10)) +#define USB_FIFOSEL_MBW_16 ((uint16_t)(1u<<10)) +#define USB_IS0_CTSQ ((uint16_t)(7u)) +#define USB_IS0_DVSQ ((uint16_t)(7u<<4)) +#define USB_IS0_VALID ((uint16_t)(1u<<3)) +#define USB_IS0_BRDY ((uint16_t)(1u<<8)) +#define USB_IS0_NRDY ((uint16_t)(1u<<9)) +#define USB_IS0_BEMP ((uint16_t)(1u<<10)) +#define USB_IS0_CTRT ((uint16_t)(1u<<11)) +#define USB_IS0_DVST ((uint16_t)(1u<<12)) +#define USB_IS0_SOFR ((uint16_t)(1u<<13)) +#define USB_IS0_RESM ((uint16_t)(1u<<14)) +#define USB_IS0_VBINT ((uint16_t)(1u<<15)) +#define USB_IS1_SACK ((uint16_t)(1u<<4)) +#define USB_IS1_SIGN ((uint16_t)(1u<<5)) +#define USB_IS1_EOFERR ((uint16_t)(1u<<6)) +#define USB_IS1_ATTCH ((uint16_t)(1u<<11)) +#define USB_IS1_DTCH ((uint16_t)(1u<<12)) +#define USB_IS1_BCHG ((uint16_t)(1u<<14)) +#define USB_IS1_OVRCR ((uint16_t)(1u<<15)) + +#define USB_IS0_CTSQ_MSK (7u) +#define USB_IS0_CTSQ_SETUP (1u) +#define USB_IS0_DVSQ_DEF (1u<<4) +#define USB_IS0_DVSQ_ADDR (2u<<4) +#define USB_IS0_DVSQ_SUSP0 (4u<<4) +#define USB_IS0_DVSQ_SUSP1 (5u<<4) +#define USB_IS0_DVSQ_SUSP2 (6u<<4) +#define USB_IS0_DVSQ_SUSP3 (7u<<4) + +#define USB_PIPECTR_PID_MSK (3u) +#define USB_PIPECTR_PID_NAK (0u) +#define USB_PIPECTR_PID_BUF (1u) +#define USB_PIPECTR_PID_STALL (2u) +#define USB_PIPECTR_CCPL (1u<<2) +#define USB_PIPECTR_SQMON (1u<<6) +#define USB_PIPECTR_SQCLR (1u<<8) +#define USB_PIPECTR_ACLRM (1u<<9) +#define USB_PIPECTR_INBUFM (1u<<14) +#define USB_PIPECTR_BSTS (1u<<15) + +#define USB_FIFOCTR_DTLN (0x1FF) +#define USB_FIFOCTR_FRDY (1u<<13) +#define USB_FIFOCTR_BCLR (1u<<14) +#define USB_FIFOCTR_BVAL (1u<<15) + +#define USB_PIPECFG_SHTNAK (1u<<7) +#define USB_PIPECFG_DBLB (1u<<9) +#define USB_PIPECFG_BULK (1u<<14) +#define USB_PIPECFG_ISO (3u<<14) +#define USB_PIPECFG_INT (2u<<14) + +#define USB_DEVADD_LOW (1u<<6) +#define USB_DEVADD_FULL (2u<<6) + +#define FIFO_REQ_CLR (1u) +#define FIFO_COMPLETE (1u<<1) + +// Start of definition of packed structs (used by the CCRX toolchain) +TU_ATTR_PACKED_BEGIN +TU_ATTR_BIT_FIELD_ORDER_BEGIN + +typedef struct { + union { + struct { + uint16_t : 8; + uint16_t TRCLR: 1; + uint16_t TRENB: 1; + uint16_t : 0; + }; + uint16_t TRE; + }; + uint16_t TRN; +} reg_pipetre_t; + +typedef union { + struct { + volatile uint16_t u8: 8; + volatile uint16_t : 0; + }; + volatile uint16_t u16; +} hw_fifo_t; + +typedef struct TU_ATTR_PACKED +{ + void *buf; /* the start address of a transfer data buffer */ + uint16_t length; /* the number of bytes in the buffer */ + uint16_t remaining; /* the number of bytes remaining in the buffer */ + struct { + uint32_t ep : 8; /* an assigned endpoint address */ + uint32_t dev : 8; /* an assigned device address */ + uint32_t ff : 1; /* `buf` is TU_FUFO or POD */ + uint32_t : 0; + }; +} pipe_state_t; + +TU_ATTR_PACKED_END // End of definition of packed structs (used by the CCRX toolchain) +TU_ATTR_BIT_FIELD_ORDER_END + +typedef struct +{ + bool need_reset; /* The device has not been reset after connection. */ + pipe_state_t pipe[10]; + uint8_t ep[4][2][15]; /* a lookup table for a pipe index from an endpoint address */ + uint8_t ctl_mps[5]; /* EP0 max packet size for each device */ +} hcd_data_t; + +//--------------------------------------------------------------------+ +// INTERNAL OBJECT & FUNCTION DECLARATION +//--------------------------------------------------------------------+ +static hcd_data_t _hcd; + +static uint32_t disable_interrupt(void) +{ + uint32_t pswi; +#if defined(__CCRX__) + pswi = get_psw() & 0x010000; + clrpsw_i(); +#else + pswi = __builtin_rx_mvfc(0) & 0x010000; + __builtin_rx_clrpsw('I'); +#endif + return pswi; +} + +static void enable_interrupt(uint32_t pswi) +{ +#if defined(__CCRX__) + set_psw(get_psw() | pswi); +#else + __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi); +#endif +} + +static unsigned find_pipe(unsigned xfer) +{ + switch (xfer) { + case TUSB_XFER_ISOCHRONOUS: + for (int i = 1; i <= 2; ++i) { + if (0 == _hcd.pipe[i].ep) return i; + } + break; + case TUSB_XFER_BULK: + for (int i = 3; i <= 5; ++i) { + if (0 == _hcd.pipe[i].ep) return i; + } + for (int i = 1; i <= 1; ++i) { + if (0 == _hcd.pipe[i].ep) return i; + } + break; + case TUSB_XFER_INTERRUPT: + for (int i = 6; i <= 9; ++i) { + if (0 == _hcd.pipe[i].ep) return i; + } + break; + default: + /* No support for control transfer */ + break; + } + return 0; +} + +static volatile uint16_t* get_pipectr(unsigned num) +{ + volatile uint16_t *ctr = NULL; + if (num) { + ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD; + ctr += num - 1; + } else { + ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD; + } + return ctr; +} + +static volatile reg_pipetre_t* get_pipetre(unsigned num) +{ + volatile reg_pipetre_t* tre = NULL; + if ((1 <= num) && (num <= 5)) { + tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD; + tre += num - 1; + } + return tre; +} + +static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr) +{ + volatile uint16_t *ctr = NULL; + const unsigned epn = tu_edpt_number(ep_addr); + if (epn) { + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1]; + if (num) { + ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD; + ctr += num - 1; + } + } else { + ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD; + } + return ctr; +} + +static unsigned edpt0_max_packet_size(void) +{ + return USB0.DCPMAXP.BIT.MXPS; +} + +static unsigned edpt_max_packet_size(unsigned num) +{ + USB0.PIPESEL.WORD = num; + return USB0.PIPEMAXP.BIT.MXPS; +} + +static inline void pipe_wait_for_ready(unsigned num) +{ + while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ; + while (!USB0.D0FIFOCTR.BIT.FRDY) ; +} + +static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) +{ + volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; + uintptr_t addr = (uintptr_t)buf; + while (len >= 2) { + reg->u16 = *(const uint16_t *)addr; + addr += 2; + len -= 2; + } + if (len) { + reg->u8 = *(const uint8_t *)addr; + ++addr; + } +} + +static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) +{ + uint8_t *p = (uint8_t*)buf; + volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ + while (len--) *p++ = *reg; +} + +static bool pipe0_xfer_in(void) +{ + pipe_state_t *pipe = &_hcd.pipe[0]; + const unsigned rem = pipe->remaining; + + const unsigned mps = edpt0_max_packet_size(); + const unsigned vld = USB0.CFIFOCTR.BIT.DTLN; + const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + void *buf = pipe->buf; + if (len) { + USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; + pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len); + pipe->buf = (uint8_t*)buf + len; + } + if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR; + pipe->remaining = rem - len; + if ((len < mps) || (rem == len)) { + pipe->buf = NULL; + return true; + } + USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF; + return false; +} + +static bool pipe0_xfer_out(void) +{ + pipe_state_t *pipe = &_hcd.pipe[0]; + const unsigned rem = pipe->remaining; + if (!rem) { + pipe->buf = NULL; + return true; + } + const unsigned mps = edpt0_max_packet_size(); + const unsigned len = TU_MIN(mps, rem); + void *buf = pipe->buf; + if (len) { + pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len); + pipe->buf = (uint8_t*)buf + len; + } + if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL; + pipe->remaining = rem - len; + return false; +} + +static bool pipe_xfer_in(unsigned num) +{ + pipe_state_t *pipe = &_hcd.pipe[num]; + const unsigned rem = pipe->remaining; + + USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8; + const unsigned mps = edpt_max_packet_size(num); + pipe_wait_for_ready(num); + const unsigned vld = USB0.D0FIFOCTR.BIT.DTLN; + const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + void *buf = pipe->buf; + if (len) { + pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len); + pipe->buf = (uint8_t*)buf + len; + } + if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR; + USB0.D0FIFOSEL.WORD = 0; + while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + pipe->remaining = rem - len; + if ((len < mps) || (rem == len)) { + pipe->buf = NULL; + return NULL != buf; + } + return false; +} + +static bool pipe_xfer_out(unsigned num) +{ + pipe_state_t *pipe = &_hcd.pipe[num]; + const unsigned rem = pipe->remaining; + + if (!rem) { + pipe->buf = NULL; + return true; + } + + USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); + const unsigned mps = edpt_max_packet_size(num); + pipe_wait_for_ready(num); + const unsigned len = TU_MIN(rem, mps); + void *buf = pipe->buf; + if (len) { + pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len); + pipe->buf = (uint8_t*)buf + len; + } + if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL; + USB0.D0FIFOSEL.WORD = 0; + while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + pipe->remaining = rem - len; + return false; +} + +static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) +{ + (void)dev_addr; + const unsigned dir_in = tu_edpt_dir(ep_addr); + + /* configure fifo direction and access unit settings */ + if (dir_in) { /* IN, a byte */ + USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8; + while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ; + } else { /* OUT, 2 bytes */ + USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); + while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ; + } + + pipe_state_t *pipe = &_hcd.pipe[0]; + pipe->ep = ep_addr; + pipe->length = buflen; + pipe->remaining = buflen; + if (buflen) { + pipe->buf = buffer; + if (!dir_in) { /* OUT */ + TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80)); + pipe0_xfer_out(); + } + } else { /* ZLP */ + pipe->buf = NULL; + if (!dir_in) { /* OUT */ + USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL; + } + if (dir_in == USB0.DCPCFG.BIT.DIR) { + TU_ASSERT(USB_PIPECTR_PID_NAK == USB0.DCPCTR.BIT.PID); + USB0.DCPCTR.BIT.SQSET = 1; + USB0.DCPCFG.BIT.DIR = dir_in ^ 1; + } + } + USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF; + return true; +} + +static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) +{ + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned num = _hcd.ep[dev_addr - 1][dir_in][epn - 1]; + + TU_ASSERT(num); + + pipe_state_t *pipe = &_hcd.pipe[num]; + pipe->buf = buffer; + pipe->length = buflen; + pipe->remaining = buflen; + if (!dir_in) { /* OUT */ + if (buflen) { + pipe_xfer_out(num); + } else { /* ZLP */ + USB0.D0FIFOSEL.WORD = num; + pipe_wait_for_ready(num); + USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL; + USB0.D0FIFOSEL.WORD = 0; + while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + } + } else { + volatile uint16_t *ctr = get_pipectr(num); + volatile reg_pipetre_t *pt = get_pipetre(num); + if (pt) { + const unsigned mps = edpt_max_packet_size(num); + if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK; + pt->TRE = TU_BIT(8); + pt->TRN = (buflen + mps - 1) / mps; + pt->TRENB = 1; + } + *ctr = USB_PIPECTR_PID_BUF; + } + return true; +} + +static bool process_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) +{ + const unsigned epn = tu_edpt_number(ep_addr); + if (0 == epn) { + return process_pipe0_xfer(dev_addr, ep_addr, buffer, buflen); + } else { + return process_pipe_xfer(dev_addr, ep_addr, buffer, buflen); + } +} + +static void process_pipe0_bemp(uint8_t rhport) +{ + (void)rhport; + bool completed = pipe0_xfer_out(); + if (completed) { + pipe_state_t *pipe = &_hcd.pipe[0]; + hcd_event_xfer_complete(pipe->dev, + tu_edpt_addr(0, TUSB_DIR_OUT), + pipe->length - pipe->remaining, + XFER_RESULT_SUCCESS, true); + } +} + +static void process_pipe_nrdy(uint8_t rhport, unsigned num) +{ + (void)rhport; + unsigned result; + uint16_t volatile *ctr = get_pipectr(num); + // TU_LOG1("NRDY %d %x\n", num, *ctr); + switch (*ctr & USB_PIPECTR_PID_MSK) { + default: return; + case USB_PIPECTR_PID_STALL: result = XFER_RESULT_STALLED; break; + case USB_PIPECTR_PID_NAK: result = XFER_RESULT_FAILED; break; + } + pipe_state_t *pipe = &_hcd.pipe[num]; + hcd_event_xfer_complete(pipe->dev, pipe->ep, + pipe->length - pipe->remaining, + result, true); +} + +static void process_pipe_brdy(uint8_t rhport, unsigned num) +{ + (void)rhport; + pipe_state_t *pipe = &_hcd.pipe[num]; + const unsigned dir_in = tu_edpt_dir(pipe->ep); + bool completed; + + if (dir_in) { /* IN */ + if (num) { + completed = pipe_xfer_in(num); + } else { + completed = pipe0_xfer_in(); + } + } else { + completed = pipe_xfer_out(num); + } + if (completed) { + hcd_event_xfer_complete(pipe->dev, pipe->ep, + pipe->length - pipe->remaining, + XFER_RESULT_SUCCESS, true); + // TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining); + } +} + + +/*------------------------------------------------------------------*/ +/* Host API + *------------------------------------------------------------------*/ +bool hcd_init(uint8_t rhport) +{ + (void)rhport; + /* Enable USB0 */ + uint32_t pswi = disable_interrupt(); + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; + MSTP(USB0) = 0; + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; + enable_interrupt(pswi); + USB0.SYSCFG.BIT.SCKE = 1; + while (!USB0.SYSCFG.BIT.SCKE) ; + USB0.SYSCFG.BIT.DPRPU = 0; + USB0.SYSCFG.BIT.DRPD = 0; + USB0.SYSCFG.BIT.DCFM = 1; + + USB0.DVSTCTR0.BIT.VBUSEN = 1; + + USB0.SYSCFG.BIT.DRPD = 1; + for (volatile int i = 0; i < 30000; ++i) ; + USB0.SYSCFG.BIT.USBE = 1; + + USB.DPUSR0R.BIT.FIXPHY0 = 0u; /* USB0 Transceiver Output fixed */ +#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) + USB0.PHYSLEW.LONG = 0x5; + IR(PERIB, INTB185) = 0; +#else + IR(USB0, USBI0) = 0; +#endif + + /* Setup default control pipe */ + USB0.DCPCFG.WORD = USB_PIPECFG_SHTNAK; + USB0.DCPMAXP.WORD = 64; + USB0.INTENB0.WORD = USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP; + USB0.INTENB1.WORD = USB_IS1_SACK | USB_IS1_SIGN | + USB_IS1_ATTCH | USB_IS1_DTCH; + USB0.BEMPENB.WORD = 1; + USB0.NRDYENB.WORD = 1; + USB0.BRDYENB.WORD = 1; + return true; +} + +void hcd_int_enable(uint8_t rhport) +{ + (void)rhport; +#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) + IEN(PERIB, INTB185) = 1; +#else + IEN(USB0, USBI0) = 1; +#endif +} + +void hcd_int_disable(uint8_t rhport) +{ + (void)rhport; +#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) + IEN(PERIB, INTB185) = 0; +#else + IEN(USB0, USBI0) = 0; +#endif +} + +uint32_t hcd_frame_number(uint8_t rhport) +{ + (void)rhport; + /* The device must be reset at least once after connection + * in order to start the frame counter. */ + if (_hcd.need_reset) hcd_port_reset(rhport); + return USB0.FRMNUM.BIT.FRNM; +} + +/*--------------------------------------------------------------------+ + * Port API + *--------------------------------------------------------------------+*/ +bool hcd_port_connect_status(uint8_t rhport) +{ + (void)rhport; + return USB0.INTSTS1.BIT.ATTCH ? true: false; +} + +void hcd_port_reset(uint8_t rhport) +{ + USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; + while (USB0.DCPCTR.BIT.PBUSY) ; + hcd_int_disable(rhport); + USB0.DVSTCTR0.BIT.UACT = 0; + if (USB0.DCPCTR.BIT.SUREQ) + USB0.DCPCTR.BIT.SUREQCLR = 1; + hcd_int_enable(rhport); + /* Reset should be asserted 10-20ms. */ + USB0.DVSTCTR0.BIT.USBRST = 1; + for (volatile int i = 0; i < 2400000; ++i) ; + USB0.DVSTCTR0.BIT.USBRST = 0; + USB0.DVSTCTR0.BIT.UACT = 1; + _hcd.need_reset = false; +} + +void hcd_port_reset_end(uint8_t rhport) +{ + (void) rhport; +} + +tusb_speed_t hcd_port_speed_get(uint8_t rhport) +{ + (void)rhport; + switch (USB0.DVSTCTR0.BIT.RHST) { + default: return TUSB_SPEED_INVALID; + case USB_DVSTCTR0_FULL: return TUSB_SPEED_FULL; + case USB_DVSTCTR0_LOW: return TUSB_SPEED_LOW; + } +} + +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) +{ + (void)rhport; + uint16_t volatile *ctr; + TU_ASSERT(dev_addr < 6,); /* USBa can only handle addresses from 0 to 5. */ + if (!dev_addr) return; + _hcd.ctl_mps[dev_addr] = 0; + uint8_t *ep = &_hcd.ep[dev_addr - 1][0][0]; + for (int i = 0; i < 2 * 15; ++i, ++ep) { + unsigned num = *ep; + if (!num || dev_addr != _hcd.pipe[num].dev) continue; + + ctr = (uint16_t volatile*)&USB0.PIPE1CTR.WORD + num - 1; + *ctr = 0; + USB0.NRDYENB.WORD &= ~TU_BIT(num); + USB0.BRDYENB.WORD &= ~TU_BIT(num); + USB0.PIPESEL.WORD = num; + USB0.PIPECFG.WORD = 0; + USB0.PIPEMAXP.WORD = 0; + + _hcd.pipe[num].ep = 0; + _hcd.pipe[num].dev = 0; + *ep = 0; + } +} + +/*--------------------------------------------------------------------+ + * Endpoints API + *--------------------------------------------------------------------+*/ +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) +{ + (void)rhport; + // TU_LOG1("S %d %x\n", dev_addr, USB0.DCPCTR.WORD); + + TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ + TU_ASSERT(0 == USB0.DCPCTR.BIT.SUREQ); + + USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; + + _hcd.pipe[0].buf = NULL; + _hcd.pipe[0].length = 8; + _hcd.pipe[0].remaining = 0; + _hcd.pipe[0].dev = dev_addr; + + while (USB0.DCPCTR.BIT.PBUSY) ; + USB0.DCPMAXP.WORD = (dev_addr << 12) | _hcd.ctl_mps[dev_addr]; + + /* Set direction in advance for DATA stage */ + uint8_t const bmRequesttype = setup_packet[0]; + USB0.DCPCFG.BIT.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1; + + uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0]; + USB0.USBREQ.WORD = tu_htole16(p[0]); + USB0.USBVAL = p[1]; + USB0.USBINDX = p[2]; + USB0.USBLENG = p[3]; + + USB0.DCPCTR.BIT.SUREQ = 1; + return true; +} + +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) +{ + (void)rhport; + TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ + + const unsigned ep_addr = ep_desc->bEndpointAddress; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned mps = tu_edpt_packet_size(ep_desc); + if (0 == epn) { + USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; + hcd_devtree_info_t devtree; + hcd_devtree_get_info(dev_addr, &devtree); + uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t)&USB0.DEVADD0.WORD; + devadd += dev_addr; + while (USB0.DCPCTR.BIT.PBUSY) ; + USB0.DCPMAXP.WORD = (dev_addr << 12) | mps; + *devadd = (TUSB_SPEED_FULL == devtree.speed) ? USB_DEVADD_FULL : USB_DEVADD_LOW; + _hcd.ctl_mps[dev_addr] = mps; + return true; + } + + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned xfer = ep_desc->bmAttributes.xfer; + if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) { + /* USBa supports up to 256 bytes */ + return false; + } + const unsigned num = find_pipe(xfer); + if (!num) return false; + _hcd.pipe[num].dev = dev_addr; + _hcd.pipe[num].ep = ep_addr; + _hcd.ep[dev_addr - 1][dir_in][epn - 1] = num; + + /* setup pipe */ + hcd_int_disable(rhport); + USB0.PIPESEL.WORD = num; + USB0.PIPEMAXP.WORD = (dev_addr << 12) | mps; + volatile uint16_t *ctr = get_pipectr(num); + *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR; + *ctr = 0; + unsigned cfg = ((1 ^ dir_in) << 4) | epn; + if (xfer == TUSB_XFER_BULK) { + cfg |= USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB; + } else if (xfer == TUSB_XFER_INTERRUPT) { + cfg |= USB_PIPECFG_INT; + } else { + cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB; + } + USB0.PIPECFG.WORD = cfg; + USB0.BRDYSTS.WORD = 0x1FFu ^ TU_BIT(num); + USB0.NRDYENB.WORD |= TU_BIT(num); + USB0.BRDYENB.WORD |= TU_BIT(num); + if (!dir_in) { + *ctr = USB_PIPECTR_PID_BUF; + } + hcd_int_enable(rhport); + + return true; +} + +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) +{ + bool r; + hcd_int_disable(rhport); + // TU_LOG1("X %d %x %u\n", dev_addr, ep_addr, buflen); + r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen); + hcd_int_enable(rhport); + return r; +} + +bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) +{ + uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr); + TU_ASSERT(ctr); + + const uint32_t pid = *ctr & 0x3; + if (pid & 2) { + *ctr = pid & 2; + *ctr = 0; + } + *ctr = USB_PIPECTR_SQCLR; + unsigned const epn = tu_edpt_number(ep_addr); + if (!epn) return true; + + if (!tu_edpt_dir(ep_addr)) { /* OUT */ + *ctr = USB_PIPECTR_PID_BUF; + } + return true; +} + +//--------------------------------------------------------------------+ +// ISR +//--------------------------------------------------------------------+ +void hcd_int_handler(uint8_t rhport) +{ + (void)rhport; +#if defined(__CCRX__) + static const int Mod37BitPosition[] = { + -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4, + 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5, + 20, 8, 19, 18}; +#endif + + unsigned is1 = USB0.INTSTS1.WORD; + unsigned is0 = USB0.INTSTS0.WORD; + /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ + USB0.INTSTS1.WORD = ~((USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH) & is1); + USB0.INTSTS0.WORD = ~((USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP) & is0); + // TU_LOG1("IS %04x %04x\n", is0, is1); + is1 &= USB0.INTENB1.WORD; + is0 &= USB0.INTENB0.WORD; + + if (is1 & USB_IS1_SACK) { + /* Set DATA1 in advance for the next transfer. */ + USB0.DCPCTR.BIT.SQSET = 1; + hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL, + tu_edpt_addr(0, TUSB_DIR_OUT), + 8, XFER_RESULT_SUCCESS, true); + } + if (is1 & USB_IS1_SIGN) { + hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL, + tu_edpt_addr(0, TUSB_DIR_OUT), + 8, XFER_RESULT_FAILED, true); + } + if (is1 & USB_IS1_ATTCH) { + USB0.DVSTCTR0.BIT.UACT = 1; + _hcd.need_reset = true; + USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_ATTCH) | USB_IS1_DTCH; + hcd_event_device_attach(rhport, true); + } + if (is1 & USB_IS1_DTCH) { + USB0.DVSTCTR0.BIT.UACT = 0; + if (USB0.DCPCTR.BIT.SUREQ) + USB0.DCPCTR.BIT.SUREQCLR = 1; + USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_DTCH) | USB_IS1_ATTCH; + hcd_event_device_remove(rhport, true); + } + + if (is0 & USB_IS0_BEMP) { + const unsigned s = USB0.BEMPSTS.WORD; + USB0.BEMPSTS.WORD = 0; + if (s & 1) { + process_pipe0_bemp(rhport); + } + } + if (is0 & USB_IS0_NRDY) { + const unsigned m = USB0.NRDYENB.WORD; + unsigned s = USB0.NRDYSTS.WORD & m; + USB0.NRDYSTS.WORD = ~s; + while (s) { +#if defined(__CCRX__) + const unsigned num = Mod37BitPosition[(-s & s) % 37]; +#else + const unsigned num = __builtin_ctz(s); +#endif + process_pipe_nrdy(rhport, num); + s &= ~TU_BIT(num); + } + } + if (is0 & USB_IS0_BRDY) { + const unsigned m = USB0.BRDYENB.WORD; + unsigned s = USB0.BRDYSTS.WORD & m; + /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ + USB0.BRDYSTS.WORD = ~s; + while (s) { +#if defined(__CCRX__) + const unsigned num = Mod37BitPosition[(-s & s) % 37]; +#else + const unsigned num = __builtin_ctz(s); +#endif + process_pipe_brdy(rhport, num); + s &= ~TU_BIT(num); + } + } +} + +#endif diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c deleted file mode 100644 index fa87c9f4d..000000000 --- a/src/portable/renesas/usba/dcd_usba.c +++ /dev/null @@ -1,915 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 Koji Kitayama - * Portions copyrighted (c) 2021 Roland Winistoerfer - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) -// We disable SOF for now until needed later on -#define USE_SOF 0 - -#if CFG_TUD_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \ - CFG_TUSB_MCU == OPT_MCU_RX65X || \ - CFG_TUSB_MCU == OPT_MCU_RX72N ) -#include "device/dcd.h" -#include "iodefine.h" - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM DECLARATION -//--------------------------------------------------------------------+ -#define SYSTEM_PRCR_PRC1 (1<<1) -#define SYSTEM_PRCR_PRKEY (0xA5u<<8) - -#define USB_FIFOSEL_TX ((uint16_t)(1u<<5)) -#define USB_FIFOSEL_BIGEND ((uint16_t)(1u<<8)) -#define USB_FIFOSEL_MBW_8 ((uint16_t)(0u<<10)) -#define USB_FIFOSEL_MBW_16 ((uint16_t)(1u<<10)) -#define USB_IS0_CTSQ ((uint16_t)(7u)) -#define USB_IS0_DVSQ ((uint16_t)(7u<<4)) -#define USB_IS0_VALID ((uint16_t)(1u<<3)) -#define USB_IS0_BRDY ((uint16_t)(1u<<8)) -#define USB_IS0_NRDY ((uint16_t)(1u<<9)) -#define USB_IS0_BEMP ((uint16_t)(1u<<10)) -#define USB_IS0_CTRT ((uint16_t)(1u<<11)) -#define USB_IS0_DVST ((uint16_t)(1u<<12)) -#define USB_IS0_SOFR ((uint16_t)(1u<<13)) -#define USB_IS0_RESM ((uint16_t)(1u<<14)) -#define USB_IS0_VBINT ((uint16_t)(1u<<15)) -#define USB_IS1_SACK ((uint16_t)(1u<<4)) -#define USB_IS1_SIGN ((uint16_t)(1u<<5)) -#define USB_IS1_EOFERR ((uint16_t)(1u<<6)) -#define USB_IS1_ATTCH ((uint16_t)(1u<<11)) -#define USB_IS1_DTCH ((uint16_t)(1u<<12)) -#define USB_IS1_BCHG ((uint16_t)(1u<<14)) -#define USB_IS1_OVRCR ((uint16_t)(1u<<15)) - -#define USB_IS0_CTSQ_MSK (7u) -#define USB_IS0_CTSQ_SETUP (1u) -#define USB_IS0_DVSQ_DEF (1u<<4) -#define USB_IS0_DVSQ_ADDR (2u<<4) -#define USB_IS0_DVSQ_SUSP0 (4u<<4) -#define USB_IS0_DVSQ_SUSP1 (5u<<4) -#define USB_IS0_DVSQ_SUSP2 (6u<<4) -#define USB_IS0_DVSQ_SUSP3 (7u<<4) - -#define USB_PIPECTR_PID_NAK (0u) -#define USB_PIPECTR_PID_BUF (1u) -#define USB_PIPECTR_PID_STALL (2u) -#define USB_PIPECTR_CCPL (1u<<2) -#define USB_PIPECTR_SQMON (1u<<6) -#define USB_PIPECTR_SQCLR (1u<<8) -#define USB_PIPECTR_ACLRM (1u<<9) -#define USB_PIPECTR_INBUFM (1u<<14) -#define USB_PIPECTR_BSTS (1u<<15) - -#define USB_FIFOCTR_DTLN (0x1FF) -#define USB_FIFOCTR_FRDY (1u<<13) -#define USB_FIFOCTR_BCLR (1u<<14) -#define USB_FIFOCTR_BVAL (1u<<15) - -#define USB_PIPECFG_SHTNAK (1u<<7) -#define USB_PIPECFG_DBLB (1u<<9) -#define USB_PIPECFG_BULK (1u<<14) -#define USB_PIPECFG_ISO (3u<<14) -#define USB_PIPECFG_INT (2u<<14) - -#define FIFO_REQ_CLR (1u) -#define FIFO_COMPLETE (1u<<1) - -// Start of definition of packed structs (used by the CCRX toolchain) -TU_ATTR_PACKED_BEGIN -TU_ATTR_BIT_FIELD_ORDER_BEGIN - -typedef struct { - union { - struct { - uint16_t : 8; - uint16_t TRCLR: 1; - uint16_t TRENB: 1; - uint16_t : 0; - }; - uint16_t TRE; - }; - uint16_t TRN; -} reg_pipetre_t; - -typedef union { - struct { - volatile uint16_t u8: 8; - volatile uint16_t : 0; - }; - volatile uint16_t u16; -} hw_fifo_t; - -typedef struct TU_ATTR_PACKED -{ - void *buf; /* the start address of a transfer data buffer */ - uint16_t length; /* the number of bytes in the buffer */ - uint16_t remaining; /* the number of bytes remaining in the buffer */ - struct { - uint32_t ep : 8; /* an assigned endpoint address */ - uint32_t ff : 1; /* `buf` is TU_FUFO or POD */ - uint32_t : 0; - }; -} pipe_state_t; - -TU_ATTR_PACKED_END // End of definition of packed structs (used by the CCRX toolchain) -TU_ATTR_BIT_FIELD_ORDER_END - -typedef struct -{ - pipe_state_t pipe[10]; - uint8_t ep[2][16]; /* a lookup table for a pipe index from an endpoint address */ -} dcd_data_t; - -//--------------------------------------------------------------------+ -// INTERNAL OBJECT & FUNCTION DECLARATION -//--------------------------------------------------------------------+ -static dcd_data_t _dcd; - -static uint32_t disable_interrupt(void) -{ - uint32_t pswi; -#if defined(__CCRX__) - pswi = get_psw() & 0x010000; - clrpsw_i(); -#else - pswi = __builtin_rx_mvfc(0) & 0x010000; - __builtin_rx_clrpsw('I'); -#endif - return pswi; -} - -static void enable_interrupt(uint32_t pswi) -{ -#if defined(__CCRX__) - set_psw(get_psw() | pswi); -#else - __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi); -#endif -} - -static unsigned find_pipe(unsigned xfer) -{ - switch (xfer) { - case TUSB_XFER_ISOCHRONOUS: - for (int i = 1; i <= 2; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_BULK: - for (int i = 3; i <= 5; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - for (int i = 1; i <= 1; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_INTERRUPT: - for (int i = 6; i <= 9; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - break; - default: - /* No support for control transfer */ - break; - } - return 0; -} - -static volatile uint16_t* get_pipectr(unsigned num) -{ - volatile uint16_t *ctr = NULL; - if (num) { - ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD; - ctr += num - 1; - } else { - ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD; - } - return ctr; -} - -static volatile reg_pipetre_t* get_pipetre(unsigned num) -{ - volatile reg_pipetre_t* tre = NULL; - if ((1 <= num) && (num <= 5)) { - tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD; - tre += num - 1; - } - return tre; -} - -static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr) -{ - (void)rhport; - volatile uint16_t *ctr = NULL; - const unsigned epn = tu_edpt_number(ep_addr); - if (epn) { - const unsigned dir = tu_edpt_dir(ep_addr); - const unsigned num = _dcd.ep[dir][epn]; - if (num) { - ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD; - ctr += num - 1; - } - } else { - ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD; - } - return ctr; -} - -static unsigned edpt0_max_packet_size(void) -{ - return USB0.DCPMAXP.BIT.MXPS; -} - -static unsigned edpt_max_packet_size(unsigned num) -{ - USB0.PIPESEL.WORD = num; - return USB0.PIPEMAXP.WORD; -} - -static inline void pipe_wait_for_ready(unsigned num) -{ - while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ; - while (!USB0.D0FIFOCTR.BIT.FRDY) ; -} - -static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) -{ - volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo; - uintptr_t addr = (uintptr_t)buf; - while (len >= 2) { - reg->u16 = *(const uint16_t *)addr; - addr += 2; - len -= 2; - } - if (len) { - reg->u8 = *(const uint8_t *)addr; - ++addr; - } -} - -static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) -{ - uint8_t *p = (uint8_t*)buf; - volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ - while (len--) *p++ = *reg; -} - -static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) -{ - static const struct { - void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info); - void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n); - void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len); - } ops[] = { - /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet}, - /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, - }; - tu_fifo_buffer_info_t info; - ops[dir].tu_fifo_get_info(f, &info); - unsigned total_len = len; - len = TU_MIN(total_len, info.len_lin); - ops[dir].pipe_read_write(info.ptr_lin, fifo, len); - unsigned rem = total_len - len; - if (rem) { - len = TU_MIN(rem, info.len_wrap); - ops[dir].pipe_read_write(info.ptr_wrap, fifo, len); - rem -= len; - } - ops[dir].tu_fifo_advance(f, total_len - rem); -} - -static bool pipe0_xfer_in(void) -{ - pipe_state_t *pipe = &_dcd.pipe[0]; - const unsigned rem = pipe->remaining; - if (!rem) { - pipe->buf = NULL; - return true; - } - const unsigned mps = edpt0_max_packet_size(); - const unsigned len = TU_MIN(mps, rem); - void *buf = pipe->buf; - if (len) { - if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.CFIFO.WORD, len, TUSB_DIR_IN); - } else { - pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len); - pipe->buf = (uint8_t*)buf + len; - } - } - if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL; - pipe->remaining = rem - len; - return false; -} - -static bool pipe0_xfer_out(void) -{ - pipe_state_t *pipe = &_dcd.pipe[0]; - const unsigned rem = pipe->remaining; - - const unsigned mps = edpt0_max_packet_size(); - const unsigned vld = USB0.CFIFOCTR.BIT.DTLN; - const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); - void *buf = pipe->buf; - if (len) { - if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.CFIFO.WORD, len, TUSB_DIR_OUT); - } else { - pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len); - pipe->buf = (uint8_t*)buf + len; - } - } - if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR; - pipe->remaining = rem - len; - if ((len < mps) || (rem == len)) { - pipe->buf = NULL; - return true; - } - return false; -} - -static bool pipe_xfer_in(unsigned num) -{ - pipe_state_t *pipe = &_dcd.pipe[num]; - const unsigned rem = pipe->remaining; - - if (!rem) { - pipe->buf = NULL; - return true; - } - - USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); - const unsigned len = TU_MIN(rem, mps); - void *buf = pipe->buf; - if (len) { - if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.D0FIFO.WORD, len, TUSB_DIR_IN); - } else { - pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len); - pipe->buf = (uint8_t*)buf + len; - } - } - if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - pipe->remaining = rem - len; - return false; -} - -static bool pipe_xfer_out(unsigned num) -{ - pipe_state_t *pipe = &_dcd.pipe[num]; - const unsigned rem = pipe->remaining; - - USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8; - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); - const unsigned vld = USB0.D0FIFOCTR.BIT.DTLN; - const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); - void *buf = pipe->buf; - if (len) { - if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.D0FIFO.WORD, len, TUSB_DIR_OUT); - } else { - pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len); - pipe->buf = (uint8_t*)buf + len; - } - } - if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - pipe->remaining = rem - len; - if ((len < mps) || (rem == len)) { - pipe->buf = NULL; - return NULL != buf; - } - return false; -} - -static void process_setup_packet(uint8_t rhport) -{ - uint16_t setup_packet[4]; - if (0 == (USB0.INTSTS0.WORD & USB_IS0_VALID)) return; - USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR; - setup_packet[0] = tu_le16toh(USB0.USBREQ.WORD); - setup_packet[1] = USB0.USBVAL; - setup_packet[2] = USB0.USBINDX; - setup_packet[3] = USB0.USBLENG; - USB0.INTSTS0.WORD = ~USB_IS0_VALID; - dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true); -} - -static void process_status_completion(uint8_t rhport) -{ - uint8_t ep_addr; - /* Check the data stage direction */ - if (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) { - /* IN transfer. */ - ep_addr = tu_edpt_addr(0, TUSB_DIR_IN); - } else { - /* OUT transfer. */ - ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT); - } - dcd_event_xfer_complete(rhport, ep_addr, 0, XFER_RESULT_SUCCESS, true); -} - -static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) -{ - /* configure fifo direction and access unit settings */ - if (ep_addr) { /* IN, 2 bytes */ - USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); - while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ; - } else { /* OUT, a byte */ - USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8; - while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ; - } - - pipe_state_t *pipe = &_dcd.pipe[0]; - pipe->ff = buffer_type; - pipe->length = total_bytes; - pipe->remaining = total_bytes; - if (total_bytes) { - pipe->buf = buffer; - if (ep_addr) { /* IN */ - TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80)); - pipe0_xfer_in(); - } - USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF; - } else { - /* ZLP */ - pipe->buf = NULL; - USB0.DCPCTR.WORD = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF; - } - return true; -} - -static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) -{ - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir = tu_edpt_dir(ep_addr); - const unsigned num = _dcd.ep[dir][epn]; - - TU_ASSERT(num); - - pipe_state_t *pipe = &_dcd.pipe[num]; - pipe->ff = buffer_type; - pipe->buf = buffer; - pipe->length = total_bytes; - pipe->remaining = total_bytes; - if (dir) { /* IN */ - if (total_bytes) { - pipe_xfer_in(num); - } else { /* ZLP */ - USB0.D0FIFOSEL.WORD = num; - pipe_wait_for_ready(num); - USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - } - } else { -#if defined(__CCRX__) - __evenaccess volatile reg_pipetre_t *pt = get_pipetre(num); -#else - volatile reg_pipetre_t *pt = get_pipetre(num); -#endif - if (pt) { - const unsigned mps = edpt_max_packet_size(num); - volatile uint16_t *ctr = get_pipectr(num); - if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK; - pt->TRE = TU_BIT(8); - pt->TRN = (total_bytes + mps - 1) / mps; - pt->TRENB = 1; - *ctr = USB_PIPECTR_PID_BUF; - } - } - // TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type); - return true; -} - -static bool process_edpt_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) -{ - const unsigned epn = tu_edpt_number(ep_addr); - if (0 == epn) { - return process_pipe0_xfer(buffer_type, ep_addr, buffer, total_bytes); - } else { - return process_pipe_xfer(buffer_type, ep_addr, buffer, total_bytes); - } -} - -static void process_pipe0_bemp(uint8_t rhport) -{ - bool completed = pipe0_xfer_in(); - if (completed) { - pipe_state_t *pipe = &_dcd.pipe[0]; - dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN), - pipe->length, XFER_RESULT_SUCCESS, true); - } -} - -static void process_pipe_brdy(uint8_t rhport, unsigned num) -{ - pipe_state_t *pipe = &_dcd.pipe[num]; - const unsigned dir = tu_edpt_dir(pipe->ep); - bool completed; - - if (dir) { /* IN */ - completed = pipe_xfer_in(num); - } else { - if (num) { - completed = pipe_xfer_out(num); - } else { - completed = pipe0_xfer_out(); - } - } - if (completed) { - dcd_event_xfer_complete(rhport, pipe->ep, - pipe->length - pipe->remaining, - XFER_RESULT_SUCCESS, true); - // TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining); - } -} - -static void process_bus_reset(uint8_t rhport) -{ - USB0.BEMPENB.WORD = 1; - USB0.BRDYENB.WORD = 1; - USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - USB0.D1FIFOSEL.WORD = 0; - while (USB0.D1FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1CTR.WORD)); - volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1TRE.WORD)); - for (int i = 1; i <= 5; ++i) { - USB0.PIPESEL.WORD = i; - USB0.PIPECFG.WORD = 0; - *ctr = USB_PIPECTR_ACLRM; - *ctr = 0; - ++ctr; - *tre = TU_BIT(8); - tre += 2; - } - for (int i = 6; i <= 9; ++i) { - USB0.PIPESEL.WORD = i; - USB0.PIPECFG.WORD = 0; - *ctr = USB_PIPECTR_ACLRM; - *ctr = 0; - ++ctr; - } - tu_varclr(&_dcd); - dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); -} - -static void process_set_address(uint8_t rhport) -{ - const uint32_t addr = USB0.USBADDR.BIT.USBADDR; - if (!addr) return; - const tusb_control_request_t setup_packet = { -#if defined(__CCRX__) - .bmRequestType = { 0 }, /* Note: CCRX needs the braces over this struct member */ -#else - .bmRequestType = 0, -#endif - .bRequest = TUSB_REQ_SET_ADDRESS, - .wValue = addr, - .wIndex = 0, - .wLength = 0, - }; - dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet, true); -} - -/*------------------------------------------------------------------*/ -/* Device API - *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport) -{ - (void)rhport; - /* Enable USB0 */ - uint32_t pswi = disable_interrupt(); - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; - MSTP(USB0) = 0; - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; - enable_interrupt(pswi); - USB0.SYSCFG.BIT.SCKE = 1; - while (!USB0.SYSCFG.BIT.SCKE) ; - USB0.SYSCFG.BIT.DRPD = 0; - USB0.SYSCFG.BIT.DCFM = 0; - USB0.SYSCFG.BIT.USBE = 1; - - USB.DPUSR0R.BIT.FIXPHY0 = 0u; /* USB0 Transceiver Output fixed */ -#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) - USB0.PHYSLEW.LONG = 0x5; - IR(PERIB, INTB185) = 0; -#else - IR(USB0, USBI0) = 0; -#endif - - /* Setup default control pipe */ - USB0.DCPMAXP.BIT.MXPS = 64; - USB0.INTENB0.WORD = USB_IS0_VBINT | USB_IS0_BRDY | USB_IS0_BEMP | - USB_IS0_DVST | USB_IS0_CTRT | (USE_SOF ? USB_IS0_SOFR: 0) | USB_IS0_RESM; - USB0.BEMPENB.WORD = 1; - USB0.BRDYENB.WORD = 1; - - if (USB0.INTSTS0.BIT.VBSTS) { - dcd_connect(rhport); - } -} - -void dcd_int_enable(uint8_t rhport) -{ - (void)rhport; -#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) - IEN(PERIB, INTB185) = 1; -#else - IEN(USB0, USBI0) = 1; -#endif -} - -void dcd_int_disable(uint8_t rhport) -{ - (void)rhport; -#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) - IEN(PERIB, INTB185) = 0; -#else - IEN(USB0, USBI0) = 0; -#endif -} - -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) -{ - (void)rhport; - (void)dev_addr; -} - -void dcd_remote_wakeup(uint8_t rhport) -{ - (void)rhport; - USB0.DVSTCTR0.BIT.WKUP = 1; -} - -void dcd_connect(uint8_t rhport) -{ - (void)rhport; - USB0.SYSCFG.BIT.DPRPU = 1; -} - -void dcd_disconnect(uint8_t rhport) -{ - (void)rhport; - USB0.SYSCFG.BIT.DPRPU = 0; -} - -void dcd_sof_enable(uint8_t rhport, bool en) -{ - (void) rhport; - (void) en; - - // TODO implement later -} - -//--------------------------------------------------------------------+ -// Endpoint API -//--------------------------------------------------------------------+ -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) -{ - (void)rhport; - - const unsigned ep_addr = ep_desc->bEndpointAddress; - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir = tu_edpt_dir(ep_addr); - const unsigned xfer = ep_desc->bmAttributes.xfer; - - const unsigned mps = tu_edpt_packet_size(ep_desc); - if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) { - /* USBa supports up to 256 bytes */ - return false; - } - - const unsigned num = find_pipe(xfer); - if (!num) return false; - _dcd.pipe[num].ep = ep_addr; - _dcd.ep[dir][epn] = num; - - /* setup pipe */ - dcd_int_disable(rhport); - USB0.PIPESEL.WORD = num; - USB0.PIPEMAXP.WORD = mps; - volatile uint16_t *ctr = get_pipectr(num); - *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR; - *ctr = 0; - unsigned cfg = (dir << 4) | epn; - if (xfer == TUSB_XFER_BULK) { - cfg |= (USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB); - } else if (xfer == TUSB_XFER_INTERRUPT) { - cfg |= USB_PIPECFG_INT; - } else { - cfg |= (USB_PIPECFG_ISO | USB_PIPECFG_DBLB); - } - USB0.PIPECFG.WORD = cfg; - USB0.BRDYSTS.WORD = 0x1FFu ^ TU_BIT(num); - USB0.BRDYENB.WORD |= TU_BIT(num); - if (dir || (xfer != TUSB_XFER_BULK)) { - *ctr = USB_PIPECTR_PID_BUF; - } - // TU_LOG1("O %d %x %x\r\n", USB0.PIPESEL.WORD, USB0.PIPECFG.WORD, USB0.PIPEMAXP.WORD); - dcd_int_enable(rhport); - - return true; -} - -void dcd_edpt_close_all(uint8_t rhport) -{ - unsigned i = TU_ARRAY_SIZE(_dcd.pipe); - dcd_int_disable(rhport); - while (--i) { /* Close all pipes except 0 */ - const unsigned ep_addr = _dcd.pipe[i].ep; - if (!ep_addr) continue; - dcd_edpt_close(rhport, ep_addr); - } - dcd_int_enable(rhport); -} - -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir = tu_edpt_dir(ep_addr); - const unsigned num = _dcd.ep[dir][epn]; - - USB0.BRDYENB.WORD &= ~TU_BIT(num); - volatile uint16_t *ctr = get_pipectr(num); - *ctr = 0; - USB0.PIPESEL.WORD = num; - USB0.PIPECFG.WORD = 0; - _dcd.pipe[num].ep = 0; - _dcd.ep[dir][epn] = 0; -} - -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) -{ - bool r; - dcd_int_disable(rhport); - r = process_edpt_xfer(0, ep_addr, buffer, total_bytes); - dcd_int_enable(rhport); - return r; -} - -bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) -{ - // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1 - TU_ASSERT(ff->item_size == 1); - bool r; - dcd_int_disable(rhport); - r = process_edpt_xfer(1, ep_addr, ff, total_bytes); - dcd_int_enable(rhport); - return r; -} - -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) -{ - volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr); - if (!ctr) return; - dcd_int_disable(rhport); - const uint32_t pid = *ctr & 0x3; - *ctr = pid | USB_PIPECTR_PID_STALL; - *ctr = USB_PIPECTR_PID_STALL; - dcd_int_enable(rhport); -} - -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) -{ - volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr); - if (!ctr) return; - dcd_int_disable(rhport); - *ctr = USB_PIPECTR_SQCLR; - - if (tu_edpt_dir(ep_addr)) { /* IN */ - *ctr = USB_PIPECTR_PID_BUF; - } else { - const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)]; - USB0.PIPESEL.WORD = num; - if (USB0.PIPECFG.BIT.TYPE != 1) { - *ctr = USB_PIPECTR_PID_BUF; - } - } - dcd_int_enable(rhport); -} - -//--------------------------------------------------------------------+ -// ISR -//--------------------------------------------------------------------+ -void dcd_int_handler(uint8_t rhport) -{ - (void)rhport; - - unsigned is0 = USB0.INTSTS0.WORD; - /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ - USB0.INTSTS0.WORD = ~((USB_IS0_CTRT | USB_IS0_DVST | USB_IS0_SOFR | USB_IS0_RESM | USB_IS0_VBINT) & is0) | USB_IS0_VALID; - if (is0 & USB_IS0_VBINT) { - if (USB0.INTSTS0.BIT.VBSTS) { - dcd_connect(rhport); - } else { - dcd_disconnect(rhport); - } - } - if (is0 & USB_IS0_RESM) { - dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); -#if (0==USE_SOF) - USB0.INTENB0.BIT.SOFE = 0; -#endif - } - if ((is0 & USB_IS0_SOFR) && USB0.INTENB0.BIT.SOFE) { - // USBD will exit suspended mode when SOF event is received - dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); -#if (0==USE_SOF) - USB0.INTENB0.BIT.SOFE = 0; -#endif - } - if (is0 & USB_IS0_DVST) { - switch (is0 & USB_IS0_DVSQ) { - case USB_IS0_DVSQ_DEF: - process_bus_reset(rhport); - break; - case USB_IS0_DVSQ_ADDR: - process_set_address(rhport); - break; - case USB_IS0_DVSQ_SUSP0: - case USB_IS0_DVSQ_SUSP1: - case USB_IS0_DVSQ_SUSP2: - case USB_IS0_DVSQ_SUSP3: - dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); -#if (0==USE_SOF) - USB0.INTENB0.BIT.SOFE = 1; -#endif - default: - break; - } - } - if (is0 & USB_IS0_CTRT) { - if (is0 & USB_IS0_CTSQ_SETUP) { - /* A setup packet has been received. */ - process_setup_packet(rhport); - } else if (0 == (is0 & USB_IS0_CTSQ_MSK)) { - /* A ZLP has been sent/received. */ - process_status_completion(rhport); - } - } - if (is0 & USB_IS0_BEMP) { - const unsigned s = USB0.BEMPSTS.WORD; - USB0.BEMPSTS.WORD = 0; - if (s & 1) { - process_pipe0_bemp(rhport); - } - } - if (is0 & USB_IS0_BRDY) { - const unsigned m = USB0.BRDYENB.WORD; - unsigned s = USB0.BRDYSTS.WORD & m; - /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ - USB0.BRDYSTS.WORD = ~s; - while (s) { -#if defined(__CCRX__) - static const int Mod37BitPosition[] = { - -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4, - 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5, - 20, 8, 19, 18 - }; - - const unsigned num = Mod37BitPosition[(-s & s) % 37]; -#else - const unsigned num = __builtin_ctz(s); -#endif - process_pipe_brdy(rhport, num); - s &= ~TU_BIT(num); - } - } -} - -#endif diff --git a/src/portable/renesas/usba/hcd_usba.c b/src/portable/renesas/usba/hcd_usba.c deleted file mode 100644 index 5246ecb94..000000000 --- a/src/portable/renesas/usba/hcd_usba.c +++ /dev/null @@ -1,875 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2021 Koji Kitayama - * Portions copyrighted (c) 2021 Roland Winistoerfer - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -#if CFG_TUH_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \ - CFG_TUSB_MCU == OPT_MCU_RX65X || \ - CFG_TUSB_MCU == OPT_MCU_RX72N ) -#include "host/hcd.h" -#include "iodefine.h" - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM DECLARATION -//--------------------------------------------------------------------+ -#define SYSTEM_PRCR_PRC1 (1<<1) -#define SYSTEM_PRCR_PRKEY (0xA5u<<8) - -#define USB_DVSTCTR0_LOW (1u) -#define USB_DVSTCTR0_FULL (2u) - -#define USB_FIFOSEL_TX ((uint16_t)(1u<<5)) -#define USB_FIFOSEL_BIGEND ((uint16_t)(1u<<8)) -#define USB_FIFOSEL_MBW_8 ((uint16_t)(0u<<10)) -#define USB_FIFOSEL_MBW_16 ((uint16_t)(1u<<10)) -#define USB_IS0_CTSQ ((uint16_t)(7u)) -#define USB_IS0_DVSQ ((uint16_t)(7u<<4)) -#define USB_IS0_VALID ((uint16_t)(1u<<3)) -#define USB_IS0_BRDY ((uint16_t)(1u<<8)) -#define USB_IS0_NRDY ((uint16_t)(1u<<9)) -#define USB_IS0_BEMP ((uint16_t)(1u<<10)) -#define USB_IS0_CTRT ((uint16_t)(1u<<11)) -#define USB_IS0_DVST ((uint16_t)(1u<<12)) -#define USB_IS0_SOFR ((uint16_t)(1u<<13)) -#define USB_IS0_RESM ((uint16_t)(1u<<14)) -#define USB_IS0_VBINT ((uint16_t)(1u<<15)) -#define USB_IS1_SACK ((uint16_t)(1u<<4)) -#define USB_IS1_SIGN ((uint16_t)(1u<<5)) -#define USB_IS1_EOFERR ((uint16_t)(1u<<6)) -#define USB_IS1_ATTCH ((uint16_t)(1u<<11)) -#define USB_IS1_DTCH ((uint16_t)(1u<<12)) -#define USB_IS1_BCHG ((uint16_t)(1u<<14)) -#define USB_IS1_OVRCR ((uint16_t)(1u<<15)) - -#define USB_IS0_CTSQ_MSK (7u) -#define USB_IS0_CTSQ_SETUP (1u) -#define USB_IS0_DVSQ_DEF (1u<<4) -#define USB_IS0_DVSQ_ADDR (2u<<4) -#define USB_IS0_DVSQ_SUSP0 (4u<<4) -#define USB_IS0_DVSQ_SUSP1 (5u<<4) -#define USB_IS0_DVSQ_SUSP2 (6u<<4) -#define USB_IS0_DVSQ_SUSP3 (7u<<4) - -#define USB_PIPECTR_PID_MSK (3u) -#define USB_PIPECTR_PID_NAK (0u) -#define USB_PIPECTR_PID_BUF (1u) -#define USB_PIPECTR_PID_STALL (2u) -#define USB_PIPECTR_CCPL (1u<<2) -#define USB_PIPECTR_SQMON (1u<<6) -#define USB_PIPECTR_SQCLR (1u<<8) -#define USB_PIPECTR_ACLRM (1u<<9) -#define USB_PIPECTR_INBUFM (1u<<14) -#define USB_PIPECTR_BSTS (1u<<15) - -#define USB_FIFOCTR_DTLN (0x1FF) -#define USB_FIFOCTR_FRDY (1u<<13) -#define USB_FIFOCTR_BCLR (1u<<14) -#define USB_FIFOCTR_BVAL (1u<<15) - -#define USB_PIPECFG_SHTNAK (1u<<7) -#define USB_PIPECFG_DBLB (1u<<9) -#define USB_PIPECFG_BULK (1u<<14) -#define USB_PIPECFG_ISO (3u<<14) -#define USB_PIPECFG_INT (2u<<14) - -#define USB_DEVADD_LOW (1u<<6) -#define USB_DEVADD_FULL (2u<<6) - -#define FIFO_REQ_CLR (1u) -#define FIFO_COMPLETE (1u<<1) - -// Start of definition of packed structs (used by the CCRX toolchain) -TU_ATTR_PACKED_BEGIN -TU_ATTR_BIT_FIELD_ORDER_BEGIN - -typedef struct { - union { - struct { - uint16_t : 8; - uint16_t TRCLR: 1; - uint16_t TRENB: 1; - uint16_t : 0; - }; - uint16_t TRE; - }; - uint16_t TRN; -} reg_pipetre_t; - -typedef union { - struct { - volatile uint16_t u8: 8; - volatile uint16_t : 0; - }; - volatile uint16_t u16; -} hw_fifo_t; - -typedef struct TU_ATTR_PACKED -{ - void *buf; /* the start address of a transfer data buffer */ - uint16_t length; /* the number of bytes in the buffer */ - uint16_t remaining; /* the number of bytes remaining in the buffer */ - struct { - uint32_t ep : 8; /* an assigned endpoint address */ - uint32_t dev : 8; /* an assigned device address */ - uint32_t ff : 1; /* `buf` is TU_FUFO or POD */ - uint32_t : 0; - }; -} pipe_state_t; - -TU_ATTR_PACKED_END // End of definition of packed structs (used by the CCRX toolchain) -TU_ATTR_BIT_FIELD_ORDER_END - -typedef struct -{ - bool need_reset; /* The device has not been reset after connection. */ - pipe_state_t pipe[10]; - uint8_t ep[4][2][15]; /* a lookup table for a pipe index from an endpoint address */ - uint8_t ctl_mps[5]; /* EP0 max packet size for each device */ -} hcd_data_t; - -//--------------------------------------------------------------------+ -// INTERNAL OBJECT & FUNCTION DECLARATION -//--------------------------------------------------------------------+ -static hcd_data_t _hcd; - -static uint32_t disable_interrupt(void) -{ - uint32_t pswi; -#if defined(__CCRX__) - pswi = get_psw() & 0x010000; - clrpsw_i(); -#else - pswi = __builtin_rx_mvfc(0) & 0x010000; - __builtin_rx_clrpsw('I'); -#endif - return pswi; -} - -static void enable_interrupt(uint32_t pswi) -{ -#if defined(__CCRX__) - set_psw(get_psw() | pswi); -#else - __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi); -#endif -} - -static unsigned find_pipe(unsigned xfer) -{ - switch (xfer) { - case TUSB_XFER_ISOCHRONOUS: - for (int i = 1; i <= 2; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_BULK: - for (int i = 3; i <= 5; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - for (int i = 1; i <= 1; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_INTERRUPT: - for (int i = 6; i <= 9; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - break; - default: - /* No support for control transfer */ - break; - } - return 0; -} - -static volatile uint16_t* get_pipectr(unsigned num) -{ - volatile uint16_t *ctr = NULL; - if (num) { - ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD; - ctr += num - 1; - } else { - ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD; - } - return ctr; -} - -static volatile reg_pipetre_t* get_pipetre(unsigned num) -{ - volatile reg_pipetre_t* tre = NULL; - if ((1 <= num) && (num <= 5)) { - tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD; - tre += num - 1; - } - return tre; -} - -static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr) -{ - volatile uint16_t *ctr = NULL; - const unsigned epn = tu_edpt_number(ep_addr); - if (epn) { - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1]; - if (num) { - ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD; - ctr += num - 1; - } - } else { - ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD; - } - return ctr; -} - -static unsigned edpt0_max_packet_size(void) -{ - return USB0.DCPMAXP.BIT.MXPS; -} - -static unsigned edpt_max_packet_size(unsigned num) -{ - USB0.PIPESEL.WORD = num; - return USB0.PIPEMAXP.BIT.MXPS; -} - -static inline void pipe_wait_for_ready(unsigned num) -{ - while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ; - while (!USB0.D0FIFOCTR.BIT.FRDY) ; -} - -static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) -{ - volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; - uintptr_t addr = (uintptr_t)buf; - while (len >= 2) { - reg->u16 = *(const uint16_t *)addr; - addr += 2; - len -= 2; - } - if (len) { - reg->u8 = *(const uint8_t *)addr; - ++addr; - } -} - -static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) -{ - uint8_t *p = (uint8_t*)buf; - volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ - while (len--) *p++ = *reg; -} - -static bool pipe0_xfer_in(void) -{ - pipe_state_t *pipe = &_hcd.pipe[0]; - const unsigned rem = pipe->remaining; - - const unsigned mps = edpt0_max_packet_size(); - const unsigned vld = USB0.CFIFOCTR.BIT.DTLN; - const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); - void *buf = pipe->buf; - if (len) { - USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; - pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len); - pipe->buf = (uint8_t*)buf + len; - } - if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR; - pipe->remaining = rem - len; - if ((len < mps) || (rem == len)) { - pipe->buf = NULL; - return true; - } - USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF; - return false; -} - -static bool pipe0_xfer_out(void) -{ - pipe_state_t *pipe = &_hcd.pipe[0]; - const unsigned rem = pipe->remaining; - if (!rem) { - pipe->buf = NULL; - return true; - } - const unsigned mps = edpt0_max_packet_size(); - const unsigned len = TU_MIN(mps, rem); - void *buf = pipe->buf; - if (len) { - pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len); - pipe->buf = (uint8_t*)buf + len; - } - if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL; - pipe->remaining = rem - len; - return false; -} - -static bool pipe_xfer_in(unsigned num) -{ - pipe_state_t *pipe = &_hcd.pipe[num]; - const unsigned rem = pipe->remaining; - - USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8; - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); - const unsigned vld = USB0.D0FIFOCTR.BIT.DTLN; - const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); - void *buf = pipe->buf; - if (len) { - pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len); - pipe->buf = (uint8_t*)buf + len; - } - if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - pipe->remaining = rem - len; - if ((len < mps) || (rem == len)) { - pipe->buf = NULL; - return NULL != buf; - } - return false; -} - -static bool pipe_xfer_out(unsigned num) -{ - pipe_state_t *pipe = &_hcd.pipe[num]; - const unsigned rem = pipe->remaining; - - if (!rem) { - pipe->buf = NULL; - return true; - } - - USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); - const unsigned len = TU_MIN(rem, mps); - void *buf = pipe->buf; - if (len) { - pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len); - pipe->buf = (uint8_t*)buf + len; - } - if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - pipe->remaining = rem - len; - return false; -} - -static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) -{ - (void)dev_addr; - const unsigned dir_in = tu_edpt_dir(ep_addr); - - /* configure fifo direction and access unit settings */ - if (dir_in) { /* IN, a byte */ - USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8; - while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ; - } else { /* OUT, 2 bytes */ - USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); - while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ; - } - - pipe_state_t *pipe = &_hcd.pipe[0]; - pipe->ep = ep_addr; - pipe->length = buflen; - pipe->remaining = buflen; - if (buflen) { - pipe->buf = buffer; - if (!dir_in) { /* OUT */ - TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80)); - pipe0_xfer_out(); - } - } else { /* ZLP */ - pipe->buf = NULL; - if (!dir_in) { /* OUT */ - USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL; - } - if (dir_in == USB0.DCPCFG.BIT.DIR) { - TU_ASSERT(USB_PIPECTR_PID_NAK == USB0.DCPCTR.BIT.PID); - USB0.DCPCTR.BIT.SQSET = 1; - USB0.DCPCFG.BIT.DIR = dir_in ^ 1; - } - } - USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF; - return true; -} - -static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) -{ - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned num = _hcd.ep[dev_addr - 1][dir_in][epn - 1]; - - TU_ASSERT(num); - - pipe_state_t *pipe = &_hcd.pipe[num]; - pipe->buf = buffer; - pipe->length = buflen; - pipe->remaining = buflen; - if (!dir_in) { /* OUT */ - if (buflen) { - pipe_xfer_out(num); - } else { /* ZLP */ - USB0.D0FIFOSEL.WORD = num; - pipe_wait_for_ready(num); - USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - } - } else { - volatile uint16_t *ctr = get_pipectr(num); - volatile reg_pipetre_t *pt = get_pipetre(num); - if (pt) { - const unsigned mps = edpt_max_packet_size(num); - if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK; - pt->TRE = TU_BIT(8); - pt->TRN = (buflen + mps - 1) / mps; - pt->TRENB = 1; - } - *ctr = USB_PIPECTR_PID_BUF; - } - return true; -} - -static bool process_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) -{ - const unsigned epn = tu_edpt_number(ep_addr); - if (0 == epn) { - return process_pipe0_xfer(dev_addr, ep_addr, buffer, buflen); - } else { - return process_pipe_xfer(dev_addr, ep_addr, buffer, buflen); - } -} - -static void process_pipe0_bemp(uint8_t rhport) -{ - (void)rhport; - bool completed = pipe0_xfer_out(); - if (completed) { - pipe_state_t *pipe = &_hcd.pipe[0]; - hcd_event_xfer_complete(pipe->dev, - tu_edpt_addr(0, TUSB_DIR_OUT), - pipe->length - pipe->remaining, - XFER_RESULT_SUCCESS, true); - } -} - -static void process_pipe_nrdy(uint8_t rhport, unsigned num) -{ - (void)rhport; - unsigned result; - uint16_t volatile *ctr = get_pipectr(num); - // TU_LOG1("NRDY %d %x\n", num, *ctr); - switch (*ctr & USB_PIPECTR_PID_MSK) { - default: return; - case USB_PIPECTR_PID_STALL: result = XFER_RESULT_STALLED; break; - case USB_PIPECTR_PID_NAK: result = XFER_RESULT_FAILED; break; - } - pipe_state_t *pipe = &_hcd.pipe[num]; - hcd_event_xfer_complete(pipe->dev, pipe->ep, - pipe->length - pipe->remaining, - result, true); -} - -static void process_pipe_brdy(uint8_t rhport, unsigned num) -{ - (void)rhport; - pipe_state_t *pipe = &_hcd.pipe[num]; - const unsigned dir_in = tu_edpt_dir(pipe->ep); - bool completed; - - if (dir_in) { /* IN */ - if (num) { - completed = pipe_xfer_in(num); - } else { - completed = pipe0_xfer_in(); - } - } else { - completed = pipe_xfer_out(num); - } - if (completed) { - hcd_event_xfer_complete(pipe->dev, pipe->ep, - pipe->length - pipe->remaining, - XFER_RESULT_SUCCESS, true); - // TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining); - } -} - - -/*------------------------------------------------------------------*/ -/* Host API - *------------------------------------------------------------------*/ -bool hcd_init(uint8_t rhport) -{ - (void)rhport; - /* Enable USB0 */ - uint32_t pswi = disable_interrupt(); - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; - MSTP(USB0) = 0; - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; - enable_interrupt(pswi); - USB0.SYSCFG.BIT.SCKE = 1; - while (!USB0.SYSCFG.BIT.SCKE) ; - USB0.SYSCFG.BIT.DPRPU = 0; - USB0.SYSCFG.BIT.DRPD = 0; - USB0.SYSCFG.BIT.DCFM = 1; - - USB0.DVSTCTR0.BIT.VBUSEN = 1; - - USB0.SYSCFG.BIT.DRPD = 1; - for (volatile int i = 0; i < 30000; ++i) ; - USB0.SYSCFG.BIT.USBE = 1; - - USB.DPUSR0R.BIT.FIXPHY0 = 0u; /* USB0 Transceiver Output fixed */ -#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) - USB0.PHYSLEW.LONG = 0x5; - IR(PERIB, INTB185) = 0; -#else - IR(USB0, USBI0) = 0; -#endif - - /* Setup default control pipe */ - USB0.DCPCFG.WORD = USB_PIPECFG_SHTNAK; - USB0.DCPMAXP.WORD = 64; - USB0.INTENB0.WORD = USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP; - USB0.INTENB1.WORD = USB_IS1_SACK | USB_IS1_SIGN | - USB_IS1_ATTCH | USB_IS1_DTCH; - USB0.BEMPENB.WORD = 1; - USB0.NRDYENB.WORD = 1; - USB0.BRDYENB.WORD = 1; - return true; -} - -void hcd_int_enable(uint8_t rhport) -{ - (void)rhport; -#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) - IEN(PERIB, INTB185) = 1; -#else - IEN(USB0, USBI0) = 1; -#endif -} - -void hcd_int_disable(uint8_t rhport) -{ - (void)rhport; -#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) - IEN(PERIB, INTB185) = 0; -#else - IEN(USB0, USBI0) = 0; -#endif -} - -uint32_t hcd_frame_number(uint8_t rhport) -{ - (void)rhport; - /* The device must be reset at least once after connection - * in order to start the frame counter. */ - if (_hcd.need_reset) hcd_port_reset(rhport); - return USB0.FRMNUM.BIT.FRNM; -} - -/*--------------------------------------------------------------------+ - * Port API - *--------------------------------------------------------------------+*/ -bool hcd_port_connect_status(uint8_t rhport) -{ - (void)rhport; - return USB0.INTSTS1.BIT.ATTCH ? true: false; -} - -void hcd_port_reset(uint8_t rhport) -{ - USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; - while (USB0.DCPCTR.BIT.PBUSY) ; - hcd_int_disable(rhport); - USB0.DVSTCTR0.BIT.UACT = 0; - if (USB0.DCPCTR.BIT.SUREQ) - USB0.DCPCTR.BIT.SUREQCLR = 1; - hcd_int_enable(rhport); - /* Reset should be asserted 10-20ms. */ - USB0.DVSTCTR0.BIT.USBRST = 1; - for (volatile int i = 0; i < 2400000; ++i) ; - USB0.DVSTCTR0.BIT.USBRST = 0; - USB0.DVSTCTR0.BIT.UACT = 1; - _hcd.need_reset = false; -} - -void hcd_port_reset_end(uint8_t rhport) -{ - (void) rhport; -} - -tusb_speed_t hcd_port_speed_get(uint8_t rhport) -{ - (void)rhport; - switch (USB0.DVSTCTR0.BIT.RHST) { - default: return TUSB_SPEED_INVALID; - case USB_DVSTCTR0_FULL: return TUSB_SPEED_FULL; - case USB_DVSTCTR0_LOW: return TUSB_SPEED_LOW; - } -} - -void hcd_device_close(uint8_t rhport, uint8_t dev_addr) -{ - (void)rhport; - uint16_t volatile *ctr; - TU_ASSERT(dev_addr < 6,); /* USBa can only handle addresses from 0 to 5. */ - if (!dev_addr) return; - _hcd.ctl_mps[dev_addr] = 0; - uint8_t *ep = &_hcd.ep[dev_addr - 1][0][0]; - for (int i = 0; i < 2 * 15; ++i, ++ep) { - unsigned num = *ep; - if (!num || dev_addr != _hcd.pipe[num].dev) continue; - - ctr = (uint16_t volatile*)&USB0.PIPE1CTR.WORD + num - 1; - *ctr = 0; - USB0.NRDYENB.WORD &= ~TU_BIT(num); - USB0.BRDYENB.WORD &= ~TU_BIT(num); - USB0.PIPESEL.WORD = num; - USB0.PIPECFG.WORD = 0; - USB0.PIPEMAXP.WORD = 0; - - _hcd.pipe[num].ep = 0; - _hcd.pipe[num].dev = 0; - *ep = 0; - } -} - -/*--------------------------------------------------------------------+ - * Endpoints API - *--------------------------------------------------------------------+*/ -bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) -{ - (void)rhport; - // TU_LOG1("S %d %x\n", dev_addr, USB0.DCPCTR.WORD); - - TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ - TU_ASSERT(0 == USB0.DCPCTR.BIT.SUREQ); - - USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; - - _hcd.pipe[0].buf = NULL; - _hcd.pipe[0].length = 8; - _hcd.pipe[0].remaining = 0; - _hcd.pipe[0].dev = dev_addr; - - while (USB0.DCPCTR.BIT.PBUSY) ; - USB0.DCPMAXP.WORD = (dev_addr << 12) | _hcd.ctl_mps[dev_addr]; - - /* Set direction in advance for DATA stage */ - uint8_t const bmRequesttype = setup_packet[0]; - USB0.DCPCFG.BIT.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1; - - uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0]; - USB0.USBREQ.WORD = tu_htole16(p[0]); - USB0.USBVAL = p[1]; - USB0.USBINDX = p[2]; - USB0.USBLENG = p[3]; - - USB0.DCPCTR.BIT.SUREQ = 1; - return true; -} - -bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) -{ - (void)rhport; - TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ - - const unsigned ep_addr = ep_desc->bEndpointAddress; - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned mps = tu_edpt_packet_size(ep_desc); - if (0 == epn) { - USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; - hcd_devtree_info_t devtree; - hcd_devtree_get_info(dev_addr, &devtree); - uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t)&USB0.DEVADD0.WORD; - devadd += dev_addr; - while (USB0.DCPCTR.BIT.PBUSY) ; - USB0.DCPMAXP.WORD = (dev_addr << 12) | mps; - *devadd = (TUSB_SPEED_FULL == devtree.speed) ? USB_DEVADD_FULL : USB_DEVADD_LOW; - _hcd.ctl_mps[dev_addr] = mps; - return true; - } - - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned xfer = ep_desc->bmAttributes.xfer; - if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) { - /* USBa supports up to 256 bytes */ - return false; - } - const unsigned num = find_pipe(xfer); - if (!num) return false; - _hcd.pipe[num].dev = dev_addr; - _hcd.pipe[num].ep = ep_addr; - _hcd.ep[dev_addr - 1][dir_in][epn - 1] = num; - - /* setup pipe */ - hcd_int_disable(rhport); - USB0.PIPESEL.WORD = num; - USB0.PIPEMAXP.WORD = (dev_addr << 12) | mps; - volatile uint16_t *ctr = get_pipectr(num); - *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR; - *ctr = 0; - unsigned cfg = ((1 ^ dir_in) << 4) | epn; - if (xfer == TUSB_XFER_BULK) { - cfg |= USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB; - } else if (xfer == TUSB_XFER_INTERRUPT) { - cfg |= USB_PIPECFG_INT; - } else { - cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB; - } - USB0.PIPECFG.WORD = cfg; - USB0.BRDYSTS.WORD = 0x1FFu ^ TU_BIT(num); - USB0.NRDYENB.WORD |= TU_BIT(num); - USB0.BRDYENB.WORD |= TU_BIT(num); - if (!dir_in) { - *ctr = USB_PIPECTR_PID_BUF; - } - hcd_int_enable(rhport); - - return true; -} - -bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) -{ - bool r; - hcd_int_disable(rhport); - // TU_LOG1("X %d %x %u\n", dev_addr, ep_addr, buflen); - r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen); - hcd_int_enable(rhport); - return r; -} - -bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) -{ - uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr); - TU_ASSERT(ctr); - - const uint32_t pid = *ctr & 0x3; - if (pid & 2) { - *ctr = pid & 2; - *ctr = 0; - } - *ctr = USB_PIPECTR_SQCLR; - unsigned const epn = tu_edpt_number(ep_addr); - if (!epn) return true; - - if (!tu_edpt_dir(ep_addr)) { /* OUT */ - *ctr = USB_PIPECTR_PID_BUF; - } - return true; -} - -//--------------------------------------------------------------------+ -// ISR -//--------------------------------------------------------------------+ -void hcd_int_handler(uint8_t rhport) -{ - (void)rhport; -#if defined(__CCRX__) - static const int Mod37BitPosition[] = { - -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4, - 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5, - 20, 8, 19, 18}; -#endif - - unsigned is1 = USB0.INTSTS1.WORD; - unsigned is0 = USB0.INTSTS0.WORD; - /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ - USB0.INTSTS1.WORD = ~((USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH) & is1); - USB0.INTSTS0.WORD = ~((USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP) & is0); - // TU_LOG1("IS %04x %04x\n", is0, is1); - is1 &= USB0.INTENB1.WORD; - is0 &= USB0.INTENB0.WORD; - - if (is1 & USB_IS1_SACK) { - /* Set DATA1 in advance for the next transfer. */ - USB0.DCPCTR.BIT.SQSET = 1; - hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL, - tu_edpt_addr(0, TUSB_DIR_OUT), - 8, XFER_RESULT_SUCCESS, true); - } - if (is1 & USB_IS1_SIGN) { - hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL, - tu_edpt_addr(0, TUSB_DIR_OUT), - 8, XFER_RESULT_FAILED, true); - } - if (is1 & USB_IS1_ATTCH) { - USB0.DVSTCTR0.BIT.UACT = 1; - _hcd.need_reset = true; - USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_ATTCH) | USB_IS1_DTCH; - hcd_event_device_attach(rhport, true); - } - if (is1 & USB_IS1_DTCH) { - USB0.DVSTCTR0.BIT.UACT = 0; - if (USB0.DCPCTR.BIT.SUREQ) - USB0.DCPCTR.BIT.SUREQCLR = 1; - USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_DTCH) | USB_IS1_ATTCH; - hcd_event_device_remove(rhport, true); - } - - if (is0 & USB_IS0_BEMP) { - const unsigned s = USB0.BEMPSTS.WORD; - USB0.BEMPSTS.WORD = 0; - if (s & 1) { - process_pipe0_bemp(rhport); - } - } - if (is0 & USB_IS0_NRDY) { - const unsigned m = USB0.NRDYENB.WORD; - unsigned s = USB0.NRDYSTS.WORD & m; - USB0.NRDYSTS.WORD = ~s; - while (s) { -#if defined(__CCRX__) - const unsigned num = Mod37BitPosition[(-s & s) % 37]; -#else - const unsigned num = __builtin_ctz(s); -#endif - process_pipe_nrdy(rhport, num); - s &= ~TU_BIT(num); - } - } - if (is0 & USB_IS0_BRDY) { - const unsigned m = USB0.BRDYENB.WORD; - unsigned s = USB0.BRDYSTS.WORD & m; - /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ - USB0.BRDYSTS.WORD = ~s; - while (s) { -#if defined(__CCRX__) - const unsigned num = Mod37BitPosition[(-s & s) % 37]; -#else - const unsigned num = __builtin_ctz(s); -#endif - process_pipe_brdy(rhport, num); - s &= ~TU_BIT(num); - } - } -} - -#endif -- cgit v1.3.1 From 03777f4a467c7ff7e0e764cfcf79d04235a2659d Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Wed, 9 Mar 2022 11:52:39 +0000 Subject: generalize renesas LINK core driver create local register access struct and move mcu specific code in preparation of support for other mcu families that use the LINK usb core Signed-off-by: Rafael Silva --- hw/bsp/rx/boards/gr_citrus/gr_citrus.c | 5 + hw/bsp/rx/boards/rx65n_target/rx65n_target.c | 5 + src/portable/renesas/link/dcd_link.c | 363 +++--- src/portable/renesas/link/hcd_link.c | 429 +++---- src/portable/renesas/link/link_rx.h | 76 ++ src/portable/renesas/link/link_type.h | 1658 ++++++++++++++++++++++++++ 6 files changed, 2041 insertions(+), 495 deletions(-) create mode 100644 src/portable/renesas/link/link_rx.h create mode 100644 src/portable/renesas/link/link_type.h (limited to 'src') diff --git a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c index 633ddad16..9bd9399f6 100644 --- a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c +++ b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c @@ -201,6 +201,11 @@ void board_init(void) IEN(SCI0, RXI0) = 1; IEN(SCI0, TXI0) = 1; IEN(SCI0, TEI0) = 1; + + /* Enable USB0 */ + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; + MSTP(USB0) = 0; + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; } //--------------------------------------------------------------------+ diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c index f189e40e4..3c729ad50 100644 --- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c +++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c @@ -248,6 +248,11 @@ void board_init(void) IEN(ICU,GROUPBL0) = 1; EN(SCI5, TEI5) = 1; + /* Enable USB0 */ + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; + MSTP(USB0) = 0; + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; + /* setup USBI0 interrupt. */ IR(USB0, USBI0) = 0; IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0; diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c index fa87c9f4d..3aeda9e4c 100644 --- a/src/portable/renesas/link/dcd_link.c +++ b/src/portable/renesas/link/dcd_link.c @@ -31,79 +31,29 @@ // We disable SOF for now until needed later on #define USE_SOF 0 -#if CFG_TUD_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \ - CFG_TUSB_MCU == OPT_MCU_RX65X || \ - CFG_TUSB_MCU == OPT_MCU_RX72N ) +#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N) + #include "device/dcd.h" -#include "iodefine.h" +#include "link_type.h" + +#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) +#include "link_rx.h" +#else +#error "Unsupported MCU" +#endif //--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM DECLARATION +// MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -#define SYSTEM_PRCR_PRC1 (1<<1) -#define SYSTEM_PRCR_PRKEY (0xA5u<<8) - -#define USB_FIFOSEL_TX ((uint16_t)(1u<<5)) -#define USB_FIFOSEL_BIGEND ((uint16_t)(1u<<8)) -#define USB_FIFOSEL_MBW_8 ((uint16_t)(0u<<10)) -#define USB_FIFOSEL_MBW_16 ((uint16_t)(1u<<10)) -#define USB_IS0_CTSQ ((uint16_t)(7u)) -#define USB_IS0_DVSQ ((uint16_t)(7u<<4)) -#define USB_IS0_VALID ((uint16_t)(1u<<3)) -#define USB_IS0_BRDY ((uint16_t)(1u<<8)) -#define USB_IS0_NRDY ((uint16_t)(1u<<9)) -#define USB_IS0_BEMP ((uint16_t)(1u<<10)) -#define USB_IS0_CTRT ((uint16_t)(1u<<11)) -#define USB_IS0_DVST ((uint16_t)(1u<<12)) -#define USB_IS0_SOFR ((uint16_t)(1u<<13)) -#define USB_IS0_RESM ((uint16_t)(1u<<14)) -#define USB_IS0_VBINT ((uint16_t)(1u<<15)) -#define USB_IS1_SACK ((uint16_t)(1u<<4)) -#define USB_IS1_SIGN ((uint16_t)(1u<<5)) -#define USB_IS1_EOFERR ((uint16_t)(1u<<6)) -#define USB_IS1_ATTCH ((uint16_t)(1u<<11)) -#define USB_IS1_DTCH ((uint16_t)(1u<<12)) -#define USB_IS1_BCHG ((uint16_t)(1u<<14)) -#define USB_IS1_OVRCR ((uint16_t)(1u<<15)) - -#define USB_IS0_CTSQ_MSK (7u) -#define USB_IS0_CTSQ_SETUP (1u) -#define USB_IS0_DVSQ_DEF (1u<<4) -#define USB_IS0_DVSQ_ADDR (2u<<4) -#define USB_IS0_DVSQ_SUSP0 (4u<<4) -#define USB_IS0_DVSQ_SUSP1 (5u<<4) -#define USB_IS0_DVSQ_SUSP2 (6u<<4) -#define USB_IS0_DVSQ_SUSP3 (7u<<4) - -#define USB_PIPECTR_PID_NAK (0u) -#define USB_PIPECTR_PID_BUF (1u) -#define USB_PIPECTR_PID_STALL (2u) -#define USB_PIPECTR_CCPL (1u<<2) -#define USB_PIPECTR_SQMON (1u<<6) -#define USB_PIPECTR_SQCLR (1u<<8) -#define USB_PIPECTR_ACLRM (1u<<9) -#define USB_PIPECTR_INBUFM (1u<<14) -#define USB_PIPECTR_BSTS (1u<<15) - -#define USB_FIFOCTR_DTLN (0x1FF) -#define USB_FIFOCTR_FRDY (1u<<13) -#define USB_FIFOCTR_BCLR (1u<<14) -#define USB_FIFOCTR_BVAL (1u<<15) - -#define USB_PIPECFG_SHTNAK (1u<<7) -#define USB_PIPECFG_DBLB (1u<<9) -#define USB_PIPECFG_BULK (1u<<14) -#define USB_PIPECFG_ISO (3u<<14) -#define USB_PIPECFG_INT (2u<<14) - -#define FIFO_REQ_CLR (1u) -#define FIFO_COMPLETE (1u<<1) - -// Start of definition of packed structs (used by the CCRX toolchain) + +/* LINK core registers */ +#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE) + +/* Start of definition of packed structs (used by the CCRX toolchain) */ TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN -typedef struct { +typedef struct TU_ATTR_PACKED { union { struct { uint16_t : 8; @@ -116,7 +66,7 @@ typedef struct { uint16_t TRN; } reg_pipetre_t; -typedef union { +typedef union TU_ATTR_PACKED { struct { volatile uint16_t u8: 8; volatile uint16_t : 0; @@ -150,28 +100,6 @@ typedef struct //--------------------------------------------------------------------+ static dcd_data_t _dcd; -static uint32_t disable_interrupt(void) -{ - uint32_t pswi; -#if defined(__CCRX__) - pswi = get_psw() & 0x010000; - clrpsw_i(); -#else - pswi = __builtin_rx_mvfc(0) & 0x010000; - __builtin_rx_clrpsw('I'); -#endif - return pswi; -} - -static void enable_interrupt(uint32_t pswi) -{ -#if defined(__CCRX__) - set_psw(get_psw() | pswi); -#else - __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi); -#endif -} - static unsigned find_pipe(unsigned xfer) { switch (xfer) { @@ -202,22 +130,18 @@ static unsigned find_pipe(unsigned xfer) static volatile uint16_t* get_pipectr(unsigned num) { - volatile uint16_t *ctr = NULL; if (num) { - ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD; - ctr += num - 1; + return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]); } else { - ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD; + return (volatile uint16_t*)&(LINK_REG->DCPCTR); } - return ctr; } static volatile reg_pipetre_t* get_pipetre(unsigned num) { volatile reg_pipetre_t* tre = NULL; if ((1 <= num) && (num <= 5)) { - tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD; - tre += num - 1; + tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E); } return tre; } @@ -225,36 +149,31 @@ static volatile reg_pipetre_t* get_pipetre(unsigned num) static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr) { (void)rhport; - volatile uint16_t *ctr = NULL; - const unsigned epn = tu_edpt_number(ep_addr); + const unsigned epn = tu_edpt_number(ep_addr); if (epn) { const unsigned dir = tu_edpt_dir(ep_addr); const unsigned num = _dcd.ep[dir][epn]; - if (num) { - ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD; - ctr += num - 1; - } + return get_pipectr(num); } else { - ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD; + return get_pipectr(0); } - return ctr; } static unsigned edpt0_max_packet_size(void) { - return USB0.DCPMAXP.BIT.MXPS; + return LINK_REG->DCPMAXP_b.MXPS; } static unsigned edpt_max_packet_size(unsigned num) { - USB0.PIPESEL.WORD = num; - return USB0.PIPEMAXP.WORD; + LINK_REG->PIPESEL = num; + return LINK_REG->PIPEMAXP; } static inline void pipe_wait_for_ready(unsigned num) { - while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ; - while (!USB0.D0FIFOCTR.BIT.FRDY) ; + while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ; + while (!LINK_REG->D0FIFOCTR_b.FRDY) ; } static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) @@ -316,13 +235,14 @@ static bool pipe0_xfer_in(void) void *buf = pipe->buf; if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.CFIFO.WORD, len, TUSB_DIR_IN); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->CFIFO, len, TUSB_DIR_IN); } else { - pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len); + pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } } - if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL; + if (len < mps) + LINK_REG->CFIFOCTR = USB_FIFOCTR_BVAL; pipe->remaining = rem - len; return false; } @@ -333,18 +253,19 @@ static bool pipe0_xfer_out(void) const unsigned rem = pipe->remaining; const unsigned mps = edpt0_max_packet_size(); - const unsigned vld = USB0.CFIFOCTR.BIT.DTLN; + const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.CFIFO.WORD, len, TUSB_DIR_OUT); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->CFIFO, len, TUSB_DIR_OUT); } else { - pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len); + pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } } - if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR; + if (len < mps) + LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR; pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; @@ -363,22 +284,23 @@ static bool pipe_xfer_in(unsigned num) return true; } - USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); + LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); const unsigned mps = edpt_max_packet_size(num); pipe_wait_for_ready(num); const unsigned len = TU_MIN(rem, mps); void *buf = pipe->buf; if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.D0FIFO.WORD, len, TUSB_DIR_IN); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->D0FIFO, len, TUSB_DIR_IN); } else { - pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len); + pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } } - if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + if (len < mps) + LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL; + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; return false; } @@ -388,24 +310,25 @@ static bool pipe_xfer_out(unsigned num) pipe_state_t *pipe = &_dcd.pipe[num]; const unsigned rem = pipe->remaining; - USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8; + LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_8; const unsigned mps = edpt_max_packet_size(num); pipe_wait_for_ready(num); - const unsigned vld = USB0.D0FIFOCTR.BIT.DTLN; + const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.D0FIFO.WORD, len, TUSB_DIR_OUT); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->D0FIFO, len, TUSB_DIR_OUT); } else { - pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len); + pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } } - if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - pipe->remaining = rem - len; + if (len < mps) + LINK_REG->D0FIFOCTR = USB_FIFOCTR_BCLR; + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; return NULL != buf; @@ -416,13 +339,13 @@ static bool pipe_xfer_out(unsigned num) static void process_setup_packet(uint8_t rhport) { uint16_t setup_packet[4]; - if (0 == (USB0.INTSTS0.WORD & USB_IS0_VALID)) return; - USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR; - setup_packet[0] = tu_le16toh(USB0.USBREQ.WORD); - setup_packet[1] = USB0.USBVAL; - setup_packet[2] = USB0.USBINDX; - setup_packet[3] = USB0.USBLENG; - USB0.INTSTS0.WORD = ~USB_IS0_VALID; + if (0 == (LINK_REG->INTSTS0 & USB_IS0_VALID)) return; + LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR; + setup_packet[0] = tu_le16toh(LINK_REG->USBREQ); + setup_packet[1] = LINK_REG->USBVAL; + setup_packet[2] = LINK_REG->USBINDX; + setup_packet[3] = LINK_REG->USBLENG; + LINK_REG->INTSTS0 = ~USB_IS0_VALID; dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true); } @@ -430,7 +353,7 @@ static void process_status_completion(uint8_t rhport) { uint8_t ep_addr; /* Check the data stage direction */ - if (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) { + if (LINK_REG->CFIFOSEL & USB_FIFOSEL_TX) { /* IN transfer. */ ep_addr = tu_edpt_addr(0, TUSB_DIR_IN); } else { @@ -444,11 +367,12 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u { /* configure fifo direction and access unit settings */ if (ep_addr) { /* IN, 2 bytes */ - USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); - while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ; - } else { /* OUT, a byte */ - USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8; - while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ; + LINK_REG->CFIFOSEL = + USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); + while (!(LINK_REG->CFIFOSEL & USB_FIFOSEL_TX)) ; + } else { /* OUT, a byte */ + LINK_REG->CFIFOSEL = USB_FIFOSEL_MBW_8; + while (LINK_REG->CFIFOSEL & USB_FIFOSEL_TX) ; } pipe_state_t *pipe = &_dcd.pipe[0]; @@ -458,14 +382,14 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u if (total_bytes) { pipe->buf = buffer; if (ep_addr) { /* IN */ - TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80)); + TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80)); pipe0_xfer_in(); } - USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF; + LINK_REG->DCPCTR = USB_PIPECTR_PID_BUF; } else { /* ZLP */ pipe->buf = NULL; - USB0.DCPCTR.WORD = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF; + LINK_REG->DCPCTR = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF; } return true; } @@ -487,11 +411,11 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui if (total_bytes) { pipe_xfer_in(num); } else { /* ZLP */ - USB0.D0FIFOSEL.WORD = num; + LINK_REG->D0FIFOSEL = num; pipe_wait_for_ready(num); - USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL; + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ } } else { #if defined(__CCRX__) @@ -558,18 +482,18 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num) static void process_bus_reset(uint8_t rhport) { - USB0.BEMPENB.WORD = 1; - USB0.BRDYENB.WORD = 1; - USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - USB0.D1FIFOSEL.WORD = 0; - while (USB0.D1FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1CTR.WORD)); - volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1TRE.WORD)); + LINK_REG->BEMPENB = 1; + LINK_REG->BRDYENB = 1; + LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR; + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + LINK_REG->D1FIFOSEL = 0; + while (LINK_REG->D1FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&LINK_REG->PIPE_CTR[0])); + volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&LINK_REG->PIPE_TR[0].E)); for (int i = 1; i <= 5; ++i) { - USB0.PIPESEL.WORD = i; - USB0.PIPECFG.WORD = 0; + LINK_REG->PIPESEL = i; + LINK_REG->PIPECFG = 0; *ctr = USB_PIPECTR_ACLRM; *ctr = 0; ++ctr; @@ -577,8 +501,8 @@ static void process_bus_reset(uint8_t rhport) tre += 2; } for (int i = 6; i <= 9; ++i) { - USB0.PIPESEL.WORD = i; - USB0.PIPECFG.WORD = 0; + LINK_REG->PIPESEL = i; + LINK_REG->PIPECFG = 0; *ctr = USB_PIPECTR_ACLRM; *ctr = 0; ++ctr; @@ -589,7 +513,7 @@ static void process_bus_reset(uint8_t rhport) static void process_set_address(uint8_t rhport) { - const uint32_t addr = USB0.USBADDR.BIT.USBADDR; + const uint32_t addr = LINK_REG->USBADDR_b.USBADDR; if (!addr) return; const tusb_control_request_t setup_packet = { #if defined(__CCRX__) @@ -611,56 +535,39 @@ static void process_set_address(uint8_t rhport) void dcd_init(uint8_t rhport) { (void)rhport; - /* Enable USB0 */ - uint32_t pswi = disable_interrupt(); - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; - MSTP(USB0) = 0; - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; - enable_interrupt(pswi); - USB0.SYSCFG.BIT.SCKE = 1; - while (!USB0.SYSCFG.BIT.SCKE) ; - USB0.SYSCFG.BIT.DRPD = 0; - USB0.SYSCFG.BIT.DCFM = 0; - USB0.SYSCFG.BIT.USBE = 1; - - USB.DPUSR0R.BIT.FIXPHY0 = 0u; /* USB0 Transceiver Output fixed */ -#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) - USB0.PHYSLEW.LONG = 0x5; - IR(PERIB, INTB185) = 0; -#else - IR(USB0, USBI0) = 0; -#endif + + LINK_REG->SYSCFG_b.SCKE = 1; + while (!LINK_REG->SYSCFG_b.SCKE) ; + LINK_REG->SYSCFG_b.DRPD = 0; + LINK_REG->SYSCFG_b.DCFM = 0; + LINK_REG->SYSCFG_b.USBE = 1; + + // MCU specific PHY init + link_phy_init(); + + LINK_REG->PHYSLEW = 0x5; + LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */ /* Setup default control pipe */ - USB0.DCPMAXP.BIT.MXPS = 64; - USB0.INTENB0.WORD = USB_IS0_VBINT | USB_IS0_BRDY | USB_IS0_BEMP | - USB_IS0_DVST | USB_IS0_CTRT | (USE_SOF ? USB_IS0_SOFR: 0) | USB_IS0_RESM; - USB0.BEMPENB.WORD = 1; - USB0.BRDYENB.WORD = 1; + LINK_REG->DCPMAXP_b.MXPS = 64; + LINK_REG->INTENB0 = USB_IS0_VBINT | USB_IS0_BRDY | USB_IS0_BEMP | USB_IS0_DVST | USB_IS0_CTRT | + (USE_SOF ? USB_IS0_SOFR : 0) | USB_IS0_RESM; + LINK_REG->BEMPENB = 1; + LINK_REG->BRDYENB = 1; - if (USB0.INTSTS0.BIT.VBSTS) { + if (LINK_REG->INTSTS0_b.VBSTS) { dcd_connect(rhport); } } void dcd_int_enable(uint8_t rhport) { - (void)rhport; -#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) - IEN(PERIB, INTB185) = 1; -#else - IEN(USB0, USBI0) = 1; -#endif + link_int_enable(rhport); } void dcd_int_disable(uint8_t rhport) { - (void)rhport; -#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) - IEN(PERIB, INTB185) = 0; -#else - IEN(USB0, USBI0) = 0; -#endif + link_int_disable(rhport); } void dcd_set_address(uint8_t rhport, uint8_t dev_addr) @@ -672,19 +579,19 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) void dcd_remote_wakeup(uint8_t rhport) { (void)rhport; - USB0.DVSTCTR0.BIT.WKUP = 1; + LINK_REG->DVSTCTR0_b.WKUP = 1; } void dcd_connect(uint8_t rhport) { (void)rhport; - USB0.SYSCFG.BIT.DPRPU = 1; + LINK_REG->SYSCFG_b.DPRPU = 1; } void dcd_disconnect(uint8_t rhport) { (void)rhport; - USB0.SYSCFG.BIT.DPRPU = 0; + LINK_REG->SYSCFG_b.DPRPU = 0; } void dcd_sof_enable(uint8_t rhport, bool en) @@ -720,8 +627,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) /* setup pipe */ dcd_int_disable(rhport); - USB0.PIPESEL.WORD = num; - USB0.PIPEMAXP.WORD = mps; + LINK_REG->PIPESEL = num; + LINK_REG->PIPEMAXP = mps; volatile uint16_t *ctr = get_pipectr(num); *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR; *ctr = 0; @@ -733,13 +640,13 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) } else { cfg |= (USB_PIPECFG_ISO | USB_PIPECFG_DBLB); } - USB0.PIPECFG.WORD = cfg; - USB0.BRDYSTS.WORD = 0x1FFu ^ TU_BIT(num); - USB0.BRDYENB.WORD |= TU_BIT(num); + LINK_REG->PIPECFG = cfg; + LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num); + LINK_REG->BRDYENB |= TU_BIT(num); if (dir || (xfer != TUSB_XFER_BULK)) { *ctr = USB_PIPECTR_PID_BUF; } - // TU_LOG1("O %d %x %x\r\n", USB0.PIPESEL.WORD, USB0.PIPECFG.WORD, USB0.PIPEMAXP.WORD); + // TU_LOG1("O %d %x %x\r\n", LINK_REG->PIPESEL, LINK_REG->PIPECFG, LINK_REG->PIPEMAXP); dcd_int_enable(rhport); return true; @@ -764,11 +671,11 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) const unsigned dir = tu_edpt_dir(ep_addr); const unsigned num = _dcd.ep[dir][epn]; - USB0.BRDYENB.WORD &= ~TU_BIT(num); + LINK_REG->BRDYENB &= ~TU_BIT(num); volatile uint16_t *ctr = get_pipectr(num); *ctr = 0; - USB0.PIPESEL.WORD = num; - USB0.PIPECFG.WORD = 0; + LINK_REG->PIPESEL = num; + LINK_REG->PIPECFG = 0; _dcd.pipe[num].ep = 0; _dcd.ep[dir][epn] = 0; } @@ -815,8 +722,8 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) *ctr = USB_PIPECTR_PID_BUF; } else { const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)]; - USB0.PIPESEL.WORD = num; - if (USB0.PIPECFG.BIT.TYPE != 1) { + LINK_REG->PIPESEL = num; + if (LINK_REG->PIPECFG_b.TYPE != 1) { *ctr = USB_PIPECTR_PID_BUF; } } @@ -830,11 +737,11 @@ void dcd_int_handler(uint8_t rhport) { (void)rhport; - unsigned is0 = USB0.INTSTS0.WORD; + unsigned is0 = LINK_REG->INTSTS0; /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ - USB0.INTSTS0.WORD = ~((USB_IS0_CTRT | USB_IS0_DVST | USB_IS0_SOFR | USB_IS0_RESM | USB_IS0_VBINT) & is0) | USB_IS0_VALID; + LINK_REG->INTSTS0 = ~((USB_IS0_CTRT | USB_IS0_DVST | USB_IS0_SOFR | USB_IS0_RESM | USB_IS0_VBINT) & is0) | USB_IS0_VALID; if (is0 & USB_IS0_VBINT) { - if (USB0.INTSTS0.BIT.VBSTS) { + if (LINK_REG->INTSTS0_b.VBSTS) { dcd_connect(rhport); } else { dcd_disconnect(rhport); @@ -843,14 +750,14 @@ void dcd_int_handler(uint8_t rhport) if (is0 & USB_IS0_RESM) { dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); #if (0==USE_SOF) - USB0.INTENB0.BIT.SOFE = 0; + LINK_REG->INTENB0_b.SOFE = 0; #endif } - if ((is0 & USB_IS0_SOFR) && USB0.INTENB0.BIT.SOFE) { + if ((is0 & USB_IS0_SOFR) && LINK_REG->INTENB0_b.SOFE) { // USBD will exit suspended mode when SOF event is received dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); -#if (0==USE_SOF) - USB0.INTENB0.BIT.SOFE = 0; +#if (0 == USE_SOF) + LINK_REG->INTENB0_b.SOFE = 0; #endif } if (is0 & USB_IS0_DVST) { @@ -867,7 +774,7 @@ void dcd_int_handler(uint8_t rhport) case USB_IS0_DVSQ_SUSP3: dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); #if (0==USE_SOF) - USB0.INTENB0.BIT.SOFE = 1; + LINK_REG->INTENB0_b.SOFE = 1; #endif default: break; @@ -883,17 +790,17 @@ void dcd_int_handler(uint8_t rhport) } } if (is0 & USB_IS0_BEMP) { - const unsigned s = USB0.BEMPSTS.WORD; - USB0.BEMPSTS.WORD = 0; + const unsigned s = LINK_REG->BEMPSTS; + LINK_REG->BEMPSTS = 0; if (s & 1) { process_pipe0_bemp(rhport); } } if (is0 & USB_IS0_BRDY) { - const unsigned m = USB0.BRDYENB.WORD; - unsigned s = USB0.BRDYSTS.WORD & m; + const unsigned m = LINK_REG->BRDYENB; + unsigned s = LINK_REG->BRDYSTS & m; /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ - USB0.BRDYSTS.WORD = ~s; + LINK_REG->BRDYSTS = ~s; while (s) { #if defined(__CCRX__) static const int Mod37BitPosition[] = { diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c index 5246ecb94..46a4aae8f 100644 --- a/src/portable/renesas/link/hcd_link.c +++ b/src/portable/renesas/link/hcd_link.c @@ -27,86 +27,28 @@ #include "tusb_option.h" -#if CFG_TUH_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \ - CFG_TUSB_MCU == OPT_MCU_RX65X || \ - CFG_TUSB_MCU == OPT_MCU_RX72N ) +#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N) + #include "host/hcd.h" -#include "iodefine.h" +#include "link_type.h" + +#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) +#include "link_rx.h" +#else +#error "Unsupported MCU" +#endif //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ -#define SYSTEM_PRCR_PRC1 (1<<1) -#define SYSTEM_PRCR_PRKEY (0xA5u<<8) - -#define USB_DVSTCTR0_LOW (1u) -#define USB_DVSTCTR0_FULL (2u) - -#define USB_FIFOSEL_TX ((uint16_t)(1u<<5)) -#define USB_FIFOSEL_BIGEND ((uint16_t)(1u<<8)) -#define USB_FIFOSEL_MBW_8 ((uint16_t)(0u<<10)) -#define USB_FIFOSEL_MBW_16 ((uint16_t)(1u<<10)) -#define USB_IS0_CTSQ ((uint16_t)(7u)) -#define USB_IS0_DVSQ ((uint16_t)(7u<<4)) -#define USB_IS0_VALID ((uint16_t)(1u<<3)) -#define USB_IS0_BRDY ((uint16_t)(1u<<8)) -#define USB_IS0_NRDY ((uint16_t)(1u<<9)) -#define USB_IS0_BEMP ((uint16_t)(1u<<10)) -#define USB_IS0_CTRT ((uint16_t)(1u<<11)) -#define USB_IS0_DVST ((uint16_t)(1u<<12)) -#define USB_IS0_SOFR ((uint16_t)(1u<<13)) -#define USB_IS0_RESM ((uint16_t)(1u<<14)) -#define USB_IS0_VBINT ((uint16_t)(1u<<15)) -#define USB_IS1_SACK ((uint16_t)(1u<<4)) -#define USB_IS1_SIGN ((uint16_t)(1u<<5)) -#define USB_IS1_EOFERR ((uint16_t)(1u<<6)) -#define USB_IS1_ATTCH ((uint16_t)(1u<<11)) -#define USB_IS1_DTCH ((uint16_t)(1u<<12)) -#define USB_IS1_BCHG ((uint16_t)(1u<<14)) -#define USB_IS1_OVRCR ((uint16_t)(1u<<15)) - -#define USB_IS0_CTSQ_MSK (7u) -#define USB_IS0_CTSQ_SETUP (1u) -#define USB_IS0_DVSQ_DEF (1u<<4) -#define USB_IS0_DVSQ_ADDR (2u<<4) -#define USB_IS0_DVSQ_SUSP0 (4u<<4) -#define USB_IS0_DVSQ_SUSP1 (5u<<4) -#define USB_IS0_DVSQ_SUSP2 (6u<<4) -#define USB_IS0_DVSQ_SUSP3 (7u<<4) - -#define USB_PIPECTR_PID_MSK (3u) -#define USB_PIPECTR_PID_NAK (0u) -#define USB_PIPECTR_PID_BUF (1u) -#define USB_PIPECTR_PID_STALL (2u) -#define USB_PIPECTR_CCPL (1u<<2) -#define USB_PIPECTR_SQMON (1u<<6) -#define USB_PIPECTR_SQCLR (1u<<8) -#define USB_PIPECTR_ACLRM (1u<<9) -#define USB_PIPECTR_INBUFM (1u<<14) -#define USB_PIPECTR_BSTS (1u<<15) - -#define USB_FIFOCTR_DTLN (0x1FF) -#define USB_FIFOCTR_FRDY (1u<<13) -#define USB_FIFOCTR_BCLR (1u<<14) -#define USB_FIFOCTR_BVAL (1u<<15) - -#define USB_PIPECFG_SHTNAK (1u<<7) -#define USB_PIPECFG_DBLB (1u<<9) -#define USB_PIPECFG_BULK (1u<<14) -#define USB_PIPECFG_ISO (3u<<14) -#define USB_PIPECFG_INT (2u<<14) - -#define USB_DEVADD_LOW (1u<<6) -#define USB_DEVADD_FULL (2u<<6) - -#define FIFO_REQ_CLR (1u) -#define FIFO_COMPLETE (1u<<1) - -// Start of definition of packed structs (used by the CCRX toolchain) + +/* LINK core registers */ +#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE) + TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN -typedef struct { +typedef struct TU_ATTR_PACKED { union { struct { uint16_t : 8; @@ -119,7 +61,7 @@ typedef struct { uint16_t TRN; } reg_pipetre_t; -typedef union { +typedef union TU_ATTR_PACKED { struct { volatile uint16_t u8: 8; volatile uint16_t : 0; @@ -127,8 +69,7 @@ typedef union { volatile uint16_t u16; } hw_fifo_t; -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { void *buf; /* the start address of a transfer data buffer */ uint16_t length; /* the number of bytes in the buffer */ uint16_t remaining; /* the number of bytes remaining in the buffer */ @@ -156,28 +97,6 @@ typedef struct //--------------------------------------------------------------------+ static hcd_data_t _hcd; -static uint32_t disable_interrupt(void) -{ - uint32_t pswi; -#if defined(__CCRX__) - pswi = get_psw() & 0x010000; - clrpsw_i(); -#else - pswi = __builtin_rx_mvfc(0) & 0x010000; - __builtin_rx_clrpsw('I'); -#endif - return pswi; -} - -static void enable_interrupt(uint32_t pswi) -{ -#if defined(__CCRX__) - set_psw(get_psw() | pswi); -#else - __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi); -#endif -} - static unsigned find_pipe(unsigned xfer) { switch (xfer) { @@ -208,58 +127,49 @@ static unsigned find_pipe(unsigned xfer) static volatile uint16_t* get_pipectr(unsigned num) { - volatile uint16_t *ctr = NULL; if (num) { - ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD; - ctr += num - 1; + return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]); } else { - ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD; + return (volatile uint16_t*)&(LINK_REG->DCPCTR); } - return ctr; } static volatile reg_pipetre_t* get_pipetre(unsigned num) { volatile reg_pipetre_t* tre = NULL; if ((1 <= num) && (num <= 5)) { - tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD; - tre += num - 1; + tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E); } return tre; } static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr) { - volatile uint16_t *ctr = NULL; - const unsigned epn = tu_edpt_number(ep_addr); + const unsigned epn = tu_edpt_number(ep_addr); if (epn) { const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1]; - if (num) { - ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD; - ctr += num - 1; - } + const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1]; + return get_pipectr(num); } else { - ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD; + return get_pipectr(0); } - return ctr; } static unsigned edpt0_max_packet_size(void) { - return USB0.DCPMAXP.BIT.MXPS; + return LINK_REG->DCPMAXP_b.MXPS; } static unsigned edpt_max_packet_size(unsigned num) { - USB0.PIPESEL.WORD = num; - return USB0.PIPEMAXP.BIT.MXPS; + LINK_REG->PIPESEL = num; + return LINK_REG->PIPEMAXP_b.MXPS; } static inline void pipe_wait_for_ready(unsigned num) { - while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ; - while (!USB0.D0FIFOCTR.BIT.FRDY) ; + while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ; + while (!LINK_REG->D0FIFOCTR_b.FRDY) ; } static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) @@ -290,21 +200,22 @@ static bool pipe0_xfer_in(void) const unsigned rem = pipe->remaining; const unsigned mps = edpt0_max_packet_size(); - const unsigned vld = USB0.CFIFOCTR.BIT.DTLN; + const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { - USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; - pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len); + LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK; + pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } - if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR; + if (len < mps) + LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR; pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; return true; } - USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF; + LINK_REG->DCPCTR = USB_PIPECTR_PID_BUF; return false; } @@ -320,10 +231,11 @@ static bool pipe0_xfer_out(void) const unsigned len = TU_MIN(mps, rem); void *buf = pipe->buf; if (len) { - pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len); + pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } - if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL; + if (len < mps) + LINK_REG->CFIFOCTR = USB_FIFOCTR_BVAL; pipe->remaining = rem - len; return false; } @@ -333,20 +245,21 @@ static bool pipe_xfer_in(unsigned num) pipe_state_t *pipe = &_hcd.pipe[num]; const unsigned rem = pipe->remaining; - USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8; + LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_8; const unsigned mps = edpt_max_packet_size(num); pipe_wait_for_ready(num); - const unsigned vld = USB0.D0FIFOCTR.BIT.DTLN; + const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { - pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len); + pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } - if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - pipe->remaining = rem - len; + if (len < mps) + LINK_REG->D0FIFOCTR = USB_FIFOCTR_BCLR; + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; return NULL != buf; @@ -364,18 +277,19 @@ static bool pipe_xfer_out(unsigned num) return true; } - USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); + LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); const unsigned mps = edpt_max_packet_size(num); pipe_wait_for_ready(num); const unsigned len = TU_MIN(rem, mps); void *buf = pipe->buf; if (len) { - pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len); + pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } - if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + if (len < mps) + LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL; + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; return false; } @@ -387,11 +301,12 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, /* configure fifo direction and access unit settings */ if (dir_in) { /* IN, a byte */ - USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8; - while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ; - } else { /* OUT, 2 bytes */ - USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); - while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ; + LINK_REG->CFIFOSEL = USB_FIFOSEL_MBW_8; + while (LINK_REG->CFIFOSEL & USB_FIFOSEL_TX) ; + } else { /* OUT, 2 bytes */ + LINK_REG->CFIFOSEL = + USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); + while (!(LINK_REG->CFIFOSEL & USB_FIFOSEL_TX)) ; } pipe_state_t *pipe = &_hcd.pipe[0]; @@ -401,25 +316,25 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, if (buflen) { pipe->buf = buffer; if (!dir_in) { /* OUT */ - TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80)); + TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80)); pipe0_xfer_out(); } } else { /* ZLP */ pipe->buf = NULL; if (!dir_in) { /* OUT */ - USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL; + LINK_REG->CFIFOCTR = USB_FIFOCTR_BVAL; } - if (dir_in == USB0.DCPCFG.BIT.DIR) { - TU_ASSERT(USB_PIPECTR_PID_NAK == USB0.DCPCTR.BIT.PID); - USB0.DCPCTR.BIT.SQSET = 1; - USB0.DCPCFG.BIT.DIR = dir_in ^ 1; + if (dir_in == LINK_REG->DCPCFG_b.DIR) { + TU_ASSERT(USB_PIPECTR_PID_NAK == LINK_REG->DCPCTR_b.PID); + LINK_REG->DCPCTR_b.SQSET = 1; + LINK_REG->DCPCFG_b.DIR = dir_in ^ 1; } } - USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF; + LINK_REG->DCPCTR = USB_PIPECTR_PID_BUF; return true; } -static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) +static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen) { const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir_in = tu_edpt_dir(ep_addr); @@ -435,11 +350,11 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, u if (buflen) { pipe_xfer_out(num); } else { /* ZLP */ - USB0.D0FIFOSEL.WORD = num; + LINK_REG->D0FIFOSEL = num; pipe_wait_for_ready(num); - USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL; + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */ } } else { volatile uint16_t *ctr = get_pipectr(num); @@ -520,69 +435,51 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num) } } - /*------------------------------------------------------------------*/ /* Host API *------------------------------------------------------------------*/ bool hcd_init(uint8_t rhport) { (void)rhport; - /* Enable USB0 */ - uint32_t pswi = disable_interrupt(); - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; - MSTP(USB0) = 0; - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; - enable_interrupt(pswi); - USB0.SYSCFG.BIT.SCKE = 1; - while (!USB0.SYSCFG.BIT.SCKE) ; - USB0.SYSCFG.BIT.DPRPU = 0; - USB0.SYSCFG.BIT.DRPD = 0; - USB0.SYSCFG.BIT.DCFM = 1; - - USB0.DVSTCTR0.BIT.VBUSEN = 1; - - USB0.SYSCFG.BIT.DRPD = 1; + + LINK_REG->SYSCFG_b.SCKE = 1; + while (!LINK_REG->SYSCFG_b.SCKE) ; + LINK_REG->SYSCFG_b.DPRPU = 0; + LINK_REG->SYSCFG_b.DRPD = 0; + LINK_REG->SYSCFG_b.DCFM = 1; + + LINK_REG->DVSTCTR0_b.VBUSEN = 1; + + LINK_REG->SYSCFG_b.DRPD = 1; for (volatile int i = 0; i < 30000; ++i) ; - USB0.SYSCFG.BIT.USBE = 1; + LINK_REG->SYSCFG_b.USBE = 1; - USB.DPUSR0R.BIT.FIXPHY0 = 0u; /* USB0 Transceiver Output fixed */ -#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) - USB0.PHYSLEW.LONG = 0x5; - IR(PERIB, INTB185) = 0; -#else - IR(USB0, USBI0) = 0; -#endif + // MCU specific PHY init + link_phy_init(); + + LINK_REG->PHYSLEW = 0x5; + LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */ /* Setup default control pipe */ - USB0.DCPCFG.WORD = USB_PIPECFG_SHTNAK; - USB0.DCPMAXP.WORD = 64; - USB0.INTENB0.WORD = USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP; - USB0.INTENB1.WORD = USB_IS1_SACK | USB_IS1_SIGN | - USB_IS1_ATTCH | USB_IS1_DTCH; - USB0.BEMPENB.WORD = 1; - USB0.NRDYENB.WORD = 1; - USB0.BRDYENB.WORD = 1; + LINK_REG->DCPCFG = USB_PIPECFG_SHTNAK; + LINK_REG->DCPMAXP = 64; + LINK_REG->INTENB0 = USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP; + LINK_REG->INTENB1 = USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH; + LINK_REG->BEMPENB = 1; + LINK_REG->NRDYENB = 1; + LINK_REG->BRDYENB = 1; + return true; } void hcd_int_enable(uint8_t rhport) { - (void)rhport; -#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) - IEN(PERIB, INTB185) = 1; -#else - IEN(USB0, USBI0) = 1; -#endif + link_int_enable(rhport); } void hcd_int_disable(uint8_t rhport) { - (void)rhport; -#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) - IEN(PERIB, INTB185) = 0; -#else - IEN(USB0, USBI0) = 0; -#endif + link_int_disable(rhport); } uint32_t hcd_frame_number(uint8_t rhport) @@ -591,7 +488,7 @@ uint32_t hcd_frame_number(uint8_t rhport) /* The device must be reset at least once after connection * in order to start the frame counter. */ if (_hcd.need_reset) hcd_port_reset(rhport); - return USB0.FRMNUM.BIT.FRNM; + return LINK_REG->FRMNUM_b.FRNM; } /*--------------------------------------------------------------------+ @@ -600,23 +497,23 @@ uint32_t hcd_frame_number(uint8_t rhport) bool hcd_port_connect_status(uint8_t rhport) { (void)rhport; - return USB0.INTSTS1.BIT.ATTCH ? true: false; + return LINK_REG->INTSTS1_b.ATTCH ? true : false; } void hcd_port_reset(uint8_t rhport) { - USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; - while (USB0.DCPCTR.BIT.PBUSY) ; + LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK; + while (LINK_REG->DCPCTR_b.PBUSY) ; hcd_int_disable(rhport); - USB0.DVSTCTR0.BIT.UACT = 0; - if (USB0.DCPCTR.BIT.SUREQ) - USB0.DCPCTR.BIT.SUREQCLR = 1; + LINK_REG->DVSTCTR0_b.UACT = 0; + if (LINK_REG->DCPCTR_b.SUREQ) + LINK_REG->DCPCTR_b.SUREQCLR = 1; hcd_int_enable(rhport); /* Reset should be asserted 10-20ms. */ - USB0.DVSTCTR0.BIT.USBRST = 1; + LINK_REG->DVSTCTR0_b.USBRST = 1; for (volatile int i = 0; i < 2400000; ++i) ; - USB0.DVSTCTR0.BIT.USBRST = 0; - USB0.DVSTCTR0.BIT.UACT = 1; + LINK_REG->DVSTCTR0_b.USBRST = 0; + LINK_REG->DVSTCTR0_b.UACT = 1; _hcd.need_reset = false; } @@ -628,7 +525,7 @@ void hcd_port_reset_end(uint8_t rhport) tusb_speed_t hcd_port_speed_get(uint8_t rhport) { (void)rhport; - switch (USB0.DVSTCTR0.BIT.RHST) { + switch (LINK_REG->DVSTCTR0_b.RHST) { default: return TUSB_SPEED_INVALID; case USB_DVSTCTR0_FULL: return TUSB_SPEED_FULL; case USB_DVSTCTR0_LOW: return TUSB_SPEED_LOW; @@ -647,13 +544,13 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) unsigned num = *ep; if (!num || dev_addr != _hcd.pipe[num].dev) continue; - ctr = (uint16_t volatile*)&USB0.PIPE1CTR.WORD + num - 1; + ctr = (uint16_t volatile*)&LINK_REG->PIPE_CTR[num - 1]; *ctr = 0; - USB0.NRDYENB.WORD &= ~TU_BIT(num); - USB0.BRDYENB.WORD &= ~TU_BIT(num); - USB0.PIPESEL.WORD = num; - USB0.PIPECFG.WORD = 0; - USB0.PIPEMAXP.WORD = 0; + LINK_REG->NRDYENB &= ~TU_BIT(num); + LINK_REG->BRDYENB &= ~TU_BIT(num); + LINK_REG->PIPESEL = num; + LINK_REG->PIPECFG = 0; + LINK_REG->PIPEMAXP = 0; _hcd.pipe[num].ep = 0; _hcd.pipe[num].dev = 0; @@ -667,36 +564,36 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { (void)rhport; - // TU_LOG1("S %d %x\n", dev_addr, USB0.DCPCTR.WORD); + // TU_LOG1("S %d %x\n", dev_addr, LINK_REG->DCPCTR); TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ - TU_ASSERT(0 == USB0.DCPCTR.BIT.SUREQ); + TU_ASSERT(0 == LINK_REG->DCPCTR_b.SUREQ); - USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; + LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK; - _hcd.pipe[0].buf = NULL; - _hcd.pipe[0].length = 8; + _hcd.pipe[0].buf = NULL; + _hcd.pipe[0].length = 8; _hcd.pipe[0].remaining = 0; - _hcd.pipe[0].dev = dev_addr; + _hcd.pipe[0].dev = dev_addr; - while (USB0.DCPCTR.BIT.PBUSY) ; - USB0.DCPMAXP.WORD = (dev_addr << 12) | _hcd.ctl_mps[dev_addr]; + while (LINK_REG->DCPCTR_b.PBUSY) ; + LINK_REG->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr]; /* Set direction in advance for DATA stage */ uint8_t const bmRequesttype = setup_packet[0]; - USB0.DCPCFG.BIT.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1; + LINK_REG->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1; uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0]; - USB0.USBREQ.WORD = tu_htole16(p[0]); - USB0.USBVAL = p[1]; - USB0.USBINDX = p[2]; - USB0.USBLENG = p[3]; + LINK_REG->USBREQ = tu_htole16(p[0]); + LINK_REG->USBVAL = p[1]; + LINK_REG->USBINDX = p[2]; + LINK_REG->USBLENG = p[3]; - USB0.DCPCTR.BIT.SUREQ = 1; + LINK_REG->DCPCTR_b.SUREQ = 1; return true; } -bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *ep_desc) { (void)rhport; TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ @@ -705,13 +602,13 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const const unsigned epn = tu_edpt_number(ep_addr); const unsigned mps = tu_edpt_packet_size(ep_desc); if (0 == epn) { - USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; + LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK; hcd_devtree_info_t devtree; hcd_devtree_get_info(dev_addr, &devtree); - uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t)&USB0.DEVADD0.WORD; + uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &LINK_REG->DEVADD[0]; devadd += dev_addr; - while (USB0.DCPCTR.BIT.PBUSY) ; - USB0.DCPMAXP.WORD = (dev_addr << 12) | mps; + while (LINK_REG->DCPCTR_b.PBUSY) ; + LINK_REG->DCPMAXP = (dev_addr << 12) | mps; *devadd = (TUSB_SPEED_FULL == devtree.speed) ? USB_DEVADD_FULL : USB_DEVADD_LOW; _hcd.ctl_mps[dev_addr] = mps; return true; @@ -731,8 +628,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const /* setup pipe */ hcd_int_disable(rhport); - USB0.PIPESEL.WORD = num; - USB0.PIPEMAXP.WORD = (dev_addr << 12) | mps; + LINK_REG->PIPESEL = num; + LINK_REG->PIPEMAXP = (dev_addr << 12) | mps; volatile uint16_t *ctr = get_pipectr(num); *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR; *ctr = 0; @@ -744,10 +641,10 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const } else { cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB; } - USB0.PIPECFG.WORD = cfg; - USB0.BRDYSTS.WORD = 0x1FFu ^ TU_BIT(num); - USB0.NRDYENB.WORD |= TU_BIT(num); - USB0.BRDYENB.WORD |= TU_BIT(num); + LINK_REG->PIPECFG = cfg; + LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num); + LINK_REG->NRDYENB |= TU_BIT(num); + LINK_REG->BRDYENB |= TU_BIT(num); if (!dir_in) { *ctr = USB_PIPECTR_PID_BUF; } @@ -799,52 +696,50 @@ void hcd_int_handler(uint8_t rhport) 20, 8, 19, 18}; #endif - unsigned is1 = USB0.INTSTS1.WORD; - unsigned is0 = USB0.INTSTS0.WORD; + unsigned is1 = LINK_REG->INTSTS1; + unsigned is0 = LINK_REG->INTSTS0; /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ - USB0.INTSTS1.WORD = ~((USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH) & is1); - USB0.INTSTS0.WORD = ~((USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP) & is0); + LINK_REG->INTSTS1 = ~((USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH) & is1); + LINK_REG->INTSTS0 = ~((USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP) & is0); // TU_LOG1("IS %04x %04x\n", is0, is1); - is1 &= USB0.INTENB1.WORD; - is0 &= USB0.INTENB0.WORD; + is1 &= LINK_REG->INTENB1; + is0 &= LINK_REG->INTENB0; if (is1 & USB_IS1_SACK) { /* Set DATA1 in advance for the next transfer. */ - USB0.DCPCTR.BIT.SQSET = 1; - hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL, - tu_edpt_addr(0, TUSB_DIR_OUT), - 8, XFER_RESULT_SUCCESS, true); + LINK_REG->DCPCTR_b.SQSET = 1; + hcd_event_xfer_complete( + LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); } if (is1 & USB_IS1_SIGN) { - hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL, - tu_edpt_addr(0, TUSB_DIR_OUT), - 8, XFER_RESULT_FAILED, true); + hcd_event_xfer_complete( + LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); } if (is1 & USB_IS1_ATTCH) { - USB0.DVSTCTR0.BIT.UACT = 1; + LINK_REG->DVSTCTR0_b.UACT = 1; _hcd.need_reset = true; - USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_ATTCH) | USB_IS1_DTCH; + LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~USB_IS1_ATTCH) | USB_IS1_DTCH; hcd_event_device_attach(rhport, true); } if (is1 & USB_IS1_DTCH) { - USB0.DVSTCTR0.BIT.UACT = 0; - if (USB0.DCPCTR.BIT.SUREQ) - USB0.DCPCTR.BIT.SUREQCLR = 1; - USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_DTCH) | USB_IS1_ATTCH; + LINK_REG->DVSTCTR0_b.UACT = 0; + if (LINK_REG->DCPCTR_b.SUREQ) + LINK_REG->DCPCTR_b.SUREQCLR = 1; + LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~USB_IS1_DTCH) | USB_IS1_ATTCH; hcd_event_device_remove(rhport, true); } if (is0 & USB_IS0_BEMP) { - const unsigned s = USB0.BEMPSTS.WORD; - USB0.BEMPSTS.WORD = 0; + const unsigned s = LINK_REG->BEMPSTS; + LINK_REG->BEMPSTS = 0; if (s & 1) { process_pipe0_bemp(rhport); } } if (is0 & USB_IS0_NRDY) { - const unsigned m = USB0.NRDYENB.WORD; - unsigned s = USB0.NRDYSTS.WORD & m; - USB0.NRDYSTS.WORD = ~s; + const unsigned m = LINK_REG->NRDYENB; + unsigned s = LINK_REG->NRDYSTS & m; + LINK_REG->NRDYSTS = ~s; while (s) { #if defined(__CCRX__) const unsigned num = Mod37BitPosition[(-s & s) % 37]; @@ -856,10 +751,10 @@ void hcd_int_handler(uint8_t rhport) } } if (is0 & USB_IS0_BRDY) { - const unsigned m = USB0.BRDYENB.WORD; - unsigned s = USB0.BRDYSTS.WORD & m; + const unsigned m = LINK_REG->BRDYENB; + unsigned s = LINK_REG->BRDYSTS & m; /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ - USB0.BRDYSTS.WORD = ~s; + LINK_REG->BRDYSTS = ~s; while (s) { #if defined(__CCRX__) const unsigned num = Mod37BitPosition[(-s & s) % 37]; diff --git a/src/portable/renesas/link/link_rx.h b/src/portable/renesas/link/link_rx.h new file mode 100644 index 000000000..b15084bb3 --- /dev/null +++ b/src/portable/renesas/link/link_rx.h @@ -0,0 +1,76 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Koji Kitayama + * Portions copyrighted (c) 2021 Roland Winistoerfer + * Copyright (c) 2022 Rafael Silva (@perigoso) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _LINK_RX_H_ +#define _LINK_RX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "link_type.h" + +#include "iodefine.h" + +#define LINK_REG_BASE (0x000A0000) + +static inline void link_int_enable(uint8_t rhport) +{ + (void) rhport; +#if (CFG_TUSB_MCU == OPT_MCU_RX72N) + IEN(PERIB, INTB185) = 1; +#else + IEN(USB0, USBI0) = 1; +#endif +} + +static inline void link_int_disable(uint8_t rhport) +{ + (void) rhport; +#if (CFG_TUSB_MCU == OPT_MCU_RX72N) + IEN(PERIB, INTB185) = 0; +#else + IEN(USB0, USBI0) = 0; +#endif +} + +// MCU specific PHY init +static inline void link_phy_init(void) +{ +#if (CFG_TUSB_MCU == OPT_MCU_RX72N) + IR(PERIB, INTB185) = 0; +#else + IR(USB0, USBI0) = 0; +#endif +} + +#ifdef __cplusplus +} +#endif + +#endif /* _LINK_RX_H_ */ diff --git a/src/portable/renesas/link/link_type.h b/src/portable/renesas/link/link_type.h new file mode 100644 index 000000000..33cf7879e --- /dev/null +++ b/src/portable/renesas/link/link_type.h @@ -0,0 +1,1658 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2022 Rafael Silva (@perigoso) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_LINK_TYPE_H_ +#define _TUSB_LINK_TYPE_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ +#define USB_DVSTCTR0_LOW (1u) +#define USB_DVSTCTR0_FULL (2u) + +#define USB_FIFOSEL_TX ((uint16_t) (1u << 5)) +#define USB_FIFOSEL_BIGEND ((uint16_t) (1u << 8)) +#define USB_FIFOSEL_MBW_8 ((uint16_t) (0u << 10)) +#define USB_FIFOSEL_MBW_16 ((uint16_t) (1u << 10)) +#define USB_IS0_CTSQ ((uint16_t) (7u)) +#define USB_IS0_DVSQ ((uint16_t) (7u << 4)) +#define USB_IS0_VALID ((uint16_t) (1u << 3)) +#define USB_IS0_BRDY ((uint16_t) (1u << 8)) +#define USB_IS0_NRDY ((uint16_t) (1u << 9)) +#define USB_IS0_BEMP ((uint16_t) (1u << 10)) +#define USB_IS0_CTRT ((uint16_t) (1u << 11)) +#define USB_IS0_DVST ((uint16_t) (1u << 12)) +#define USB_IS0_SOFR ((uint16_t) (1u << 13)) +#define USB_IS0_RESM ((uint16_t) (1u << 14)) +#define USB_IS0_VBINT ((uint16_t) (1u << 15)) +#define USB_IS1_SACK ((uint16_t) (1u << 4)) +#define USB_IS1_SIGN ((uint16_t) (1u << 5)) +#define USB_IS1_EOFERR ((uint16_t) (1u << 6)) +#define USB_IS1_ATTCH ((uint16_t) (1u << 11)) +#define USB_IS1_DTCH ((uint16_t) (1u << 12)) +#define USB_IS1_BCHG ((uint16_t) (1u << 14)) +#define USB_IS1_OVRCR ((uint16_t) (1u << 15)) + +#define USB_IS0_CTSQ_MSK (7u) +#define USB_IS0_CTSQ_SETUP (1u) +#define USB_IS0_DVSQ_DEF (1u << 4) +#define USB_IS0_DVSQ_ADDR (2u << 4) +#define USB_IS0_DVSQ_SUSP0 (4u << 4) +#define USB_IS0_DVSQ_SUSP1 (5u << 4) +#define USB_IS0_DVSQ_SUSP2 (6u << 4) +#define USB_IS0_DVSQ_SUSP3 (7u << 4) + +#define USB_PIPECTR_PID_MSK (3u) +#define USB_PIPECTR_PID_NAK (0u) +#define USB_PIPECTR_PID_BUF (1u) +#define USB_PIPECTR_PID_STALL (2u) +#define USB_PIPECTR_CCPL (1u << 2) +#define USB_PIPECTR_SQMON (1u << 6) +#define USB_PIPECTR_SQCLR (1u << 8) +#define USB_PIPECTR_ACLRM (1u << 9) +#define USB_PIPECTR_INBUFM (1u << 14) +#define USB_PIPECTR_BSTS (1u << 15) + +#define USB_FIFOCTR_DTLN (0x1FF) +#define USB_FIFOCTR_FRDY (1u << 13) +#define USB_FIFOCTR_BCLR (1u << 14) +#define USB_FIFOCTR_BVAL (1u << 15) + +#define USB_PIPECFG_SHTNAK (1u << 7) +#define USB_PIPECFG_DBLB (1u << 9) +#define USB_PIPECFG_BULK (1u << 14) +#define USB_PIPECFG_ISO (3u << 14) +#define USB_PIPECFG_INT (2u << 14) + +#define FIFO_REQ_CLR (1u) +#define FIFO_COMPLETE (1u << 1) + +#define USB_DEVADD_LOW (1u << 6) +#define USB_DEVADD_FULL (2u << 6) + +/*--------------------------------------------------------------------*/ +/* Register Definitions */ +/*--------------------------------------------------------------------*/ + +/* Start of definition of packed structs (used by the CCRX toolchain) */ +TU_ATTR_PACKED_BEGIN +TU_ATTR_BIT_FIELD_ORDER_BEGIN + +typedef struct TU_ATTR_PACKED { + union { + volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct { + uint16_t : 8; + volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */ + volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union { + volatile uint16_t N; /* (@ 0x00000002) Pipe Transaction Counter Register */ + + struct { + volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */ + } N_b; + }; +} LINK_REG_PIPE_TR_t; /* Size = 4 (0x4) */ + +TU_VERIFY_STATIC(sizeof(LINK_REG_PIPE_TR_t) == 4, "incorrect size"); + +/* LINK_REG Structure */ +typedef struct TU_ATTR_PACKED { + union { + volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */ + + struct { + volatile uint16_t USBE : 1; /* [0..0] USB Operation Enable */ + uint16_t : 2; + volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */ + volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */ + volatile uint16_t DRPD : 1; /* [5..5] D+/D- Line Resistor Control */ + volatile uint16_t DCFM : 1; /* [6..6] Controller Function Select */ + uint16_t : 1; + volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union { + volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */ + + struct { + volatile uint16_t + BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union { + volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */ + + struct { + volatile const uint16_t LNST : 2; /* [1..0] USB Data Line Status Monitor */ + volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + volatile const uint16_t + SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */ + volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + volatile const uint16_t + OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */ + } SYSSTS0_b; + }; + + union { + volatile const uint16_t PLLSTA; /* (@ 0x00000006) PLL Status Register */ + + struct { + volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union { + volatile uint16_t DVSTCTR0; /* (@ 0x00000008) Device State Control Register 0 */ + + struct { + volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */ + uint16_t : 1; + volatile uint16_t UACT : 1; /* [4..4] USB Bus Enable */ + volatile uint16_t RESUME : 1; /* [5..5] Resume Output */ + volatile uint16_t USBRST : 1; /* [6..6] USB Bus Reset Output */ + volatile uint16_t RWUPE : 1; /* [7..7] Wakeup Detection Enable */ + volatile uint16_t WKUP : 1; /* [8..8] Wakeup Output */ + volatile uint16_t VBUSEN : 1; /* [9..9] USB_VBUSEN Output Pin Control */ + volatile uint16_t EXICEN : 1; /* [10..10] USB_EXICEN Output Pin Control */ + volatile uint16_t HNPBTOA : 1; /* [11..11] Host Negotiation Protocol (HNP) */ + uint16_t : 4; + } DVSTCTR0_b; + }; + volatile const uint16_t RESERVED; + + union { + volatile uint16_t TESTMODE; /* (@ 0x0000000C) USB Test Mode Register */ + + struct { + volatile uint16_t UTST : 4; /* [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + volatile const uint16_t RESERVED1; + volatile const uint32_t RESERVED2; + + union { + volatile uint32_t CFIFO; /* (@ 0x00000014) CFIFO Port Register */ + + struct { + union { + volatile uint16_t CFIFOL; /* (@ 0x00000014) CFIFO Port Register L */ + volatile uint8_t CFIFOLL; /* (@ 0x00000014) CFIFO Port Register LL */ + }; + + union { + volatile uint16_t CFIFOH; /* (@ 0x00000016) CFIFO Port Register H */ + + struct { + volatile const uint8_t RESERVED3; + volatile uint8_t CFIFOHH; /* (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union { + volatile uint32_t D0FIFO; /* (@ 0x00000018) D0FIFO Port Register */ + + struct { + union { + volatile uint16_t D0FIFOL; /* (@ 0x00000018) D0FIFO Port Register L */ + volatile uint8_t D0FIFOLL; /* (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union { + volatile uint16_t D0FIFOH; /* (@ 0x0000001A) D0FIFO Port Register H */ + + struct { + volatile const uint8_t RESERVED4; + volatile uint8_t D0FIFOHH; /* (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union { + volatile uint32_t D1FIFO; /* (@ 0x0000001C) D1FIFO Port Register */ + + struct { + union { + volatile uint16_t D1FIFOL; /* (@ 0x0000001C) D1FIFO Port Register L */ + volatile uint8_t D1FIFOLL; /* (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union { + volatile uint16_t D1FIFOH; /* (@ 0x0000001E) D1FIFO Port Register H */ + + struct { + volatile const uint8_t RESERVED5; + volatile uint8_t D1FIFOHH; /* (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union { + volatile uint16_t CFIFOSEL; /* (@ 0x00000020) CFIFO Port Select Register */ + + struct { + volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + volatile uint16_t ISEL : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + volatile uint16_t BIGEND : 1; /* [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + volatile uint16_t MBW : 2; /* [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */ + volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union { + volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */ + + struct { + volatile const uint16_t + DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ + uint16_t : 1; + volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ + volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + volatile const uint32_t RESERVED6; + + union { + volatile uint16_t D0FIFOSEL; /* (@ 0x00000028) D0FIFO Port Select Register */ + + struct { + volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ + uint16_t : 1; + volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */ + volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */ + volatile uint16_t + DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */ + volatile uint16_t REW : 1; /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union { + volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */ + + struct { + volatile const uint16_t + DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ + uint16_t : 1; + volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ + volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union { + volatile uint16_t D1FIFOSEL; /* (@ 0x0000002C) D1FIFO Port Select Register */ + + struct { + volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ + uint16_t : 1; + volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */ + volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */ + volatile uint16_t + DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */ + volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */ + volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union { + volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */ + + struct { + volatile const uint16_t + DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ + uint16_t : 1; + volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ + volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union { + volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */ + + struct { + uint16_t : 8; + volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */ + volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */ + volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */ + volatile uint16_t CTRE : 1; /* [11..11] Control Transfer Stage Transition Interrupt Enable */ + volatile uint16_t DVSE : 1; /* [12..12] Device State Transition Interrupt Enable */ + volatile uint16_t SOFE : 1; /* [13..13] Frame Number Update Interrupt Enable */ + volatile uint16_t RSME : 1; /* [14..14] Resume Interrupt Enable */ + volatile uint16_t VBSE : 1; /* [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union { + volatile uint16_t INTENB1; /* (@ 0x00000032) Interrupt Enable Register 1 */ + + struct { + volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + volatile uint16_t SACKE : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */ + volatile uint16_t SIGNE : 1; /* [5..5] Setup Transaction Error Interrupt Enable */ + volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */ + volatile uint16_t DTCHE : 1; /* [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + volatile uint16_t BCHGE : 1; /* [14..14] USB Bus Change Interrupt Enable */ + volatile uint16_t OVRCRE : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + volatile const uint16_t RESERVED7; + + union { + volatile uint16_t BRDYENB; /* (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct { + volatile uint16_t PIPE0BRDYE : 1; /* [0..0] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE1BRDYE : 1; /* [1..1] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE2BRDYE : 1; /* [2..2] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE3BRDYE : 1; /* [3..3] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE4BRDYE : 1; /* [4..4] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE5BRDYE : 1; /* [5..5] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE6BRDYE : 1; /* [6..6] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union { + volatile uint16_t NRDYENB; /* (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct { + volatile uint16_t PIPE0NRDYE : 1; /* [0..0] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE1NRDYE : 1; /* [1..1] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE2NRDYE : 1; /* [2..2] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE3NRDYE : 1; /* [3..3] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE4NRDYE : 1; /* [4..4] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE5NRDYE : 1; /* [5..5] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE6NRDYE : 1; /* [6..6] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union { + volatile uint16_t BEMPENB; /* (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct { + volatile uint16_t PIPE0BEMPE : 1; /* [0..0] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE1BEMPE : 1; /* [1..1] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE2BEMPE : 1; /* [2..2] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE3BEMPE : 1; /* [3..3] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE4BEMPE : 1; /* [4..4] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE5BEMPE : 1; /* [5..5] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE6BEMPE : 1; /* [6..6] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union { + volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */ + + struct { + uint16_t : 4; + volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */ + volatile uint16_t INTL : 1; /* [5..5] Interrupt Output Sense Select */ + volatile uint16_t BRDYM : 1; /* [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union { + volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */ + + struct { + volatile uint16_t DIRPD : 1; /* [0..0] Power-Down Control */ + volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */ + uint16_t : 1; + volatile uint16_t CDPEN : 1; /* [3..3] Charging Downstream Port Enable */ + volatile uint16_t CLKSEL : 2; /* [5..4] Input System Clock Frequency */ + uint16_t : 2; + volatile uint16_t REPSEL : 2; /* [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + volatile uint16_t REPSTART : 1; /* [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + volatile uint16_t HSEB : 1; /* [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union { + volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */ + + struct { + volatile const uint16_t CTSQ : 3; /* [2..0] Control Transfer Stage */ + volatile uint16_t VALID : 1; /* [3..3] USB Request Reception */ + volatile const uint16_t DVSQ : 3; /* [6..4] Device State */ + volatile const uint16_t VBSTS : 1; /* [7..7] VBUS Input Status */ + volatile const uint16_t BRDY : 1; /* [8..8] Buffer Ready Interrupt Status */ + volatile const uint16_t NRDY : 1; /* [9..9] Buffer Not Ready Interrupt Status */ + volatile const uint16_t BEMP : 1; /* [10..10] Buffer Empty Interrupt Status */ + volatile uint16_t CTRT : 1; /* [11..11] Control Transfer Stage Transition Interrupt Status */ + volatile uint16_t DVST : 1; /* [12..12] Device State Transition Interrupt Status */ + volatile uint16_t SOFR : 1; /* [13..13] Frame Number Refresh Interrupt Status */ + volatile uint16_t RESM : 1; /* [14..14] Resume Interrupt Status */ + volatile uint16_t VBINT : 1; /* [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union { + volatile uint16_t INTSTS1; /* (@ 0x00000042) Interrupt Status Register 1 */ + + struct { + volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + volatile uint16_t SACK : 1; /* [4..4] Setup Transaction Normal Response Interrupt Status */ + volatile uint16_t SIGN : 1; /* [5..5] Setup Transaction Error Interrupt Status */ + volatile uint16_t EOFERR : 1; /* [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + volatile uint16_t LPMEND : 1; /* [8..8] LPM Transaction End Interrupt Status */ + volatile uint16_t L1RSMEND : 1; /* [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */ + volatile uint16_t DTCH : 1; /* [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + volatile uint16_t BCHG : 1; /* [14..14] USB Bus Change Interrupt Status */ + volatile uint16_t OVRCR : 1; /* [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + volatile const uint16_t RESERVED8; + + union { + volatile uint16_t BRDYSTS; /* (@ 0x00000046) BRDY Interrupt Status Register */ + + struct { + volatile uint16_t PIPE0BRDY : 1; /* [0..0] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE1BRDY : 1; /* [1..1] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE2BRDY : 1; /* [2..2] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE3BRDY : 1; /* [3..3] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE4BRDY : 1; /* [4..4] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE5BRDY : 1; /* [5..5] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE6BRDY : 1; /* [6..6] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union { + volatile uint16_t NRDYSTS; /* (@ 0x00000048) NRDY Interrupt Status Register */ + + struct { + volatile uint16_t PIPE0NRDY : 1; /* [0..0] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE1NRDY : 1; /* [1..1] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE2NRDY : 1; /* [2..2] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE3NRDY : 1; /* [3..3] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE4NRDY : 1; /* [4..4] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE5NRDY : 1; /* [5..5] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE6NRDY : 1; /* [6..6] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union { + volatile uint16_t BEMPSTS; /* (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct { + volatile uint16_t PIPE0BEMP : 1; /* [0..0] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE1BEMP : 1; /* [1..1] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE2BEMP : 1; /* [2..2] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE3BEMP : 1; /* [3..3] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE4BEMP : 1; /* [4..4] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE5BEMP : 1; /* [5..5] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE6BEMP : 1; /* [6..6] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union { + volatile uint16_t FRMNUM; /* (@ 0x0000004C) Frame Number Register */ + + struct { + volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + volatile uint16_t CRCE : 1; /* [14..14] Receive Data Error */ + volatile uint16_t OVRN : 1; /* [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union { + volatile uint16_t UFRMNUM; /* (@ 0x0000004E) uFrame Number Register */ + + struct { + volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + volatile uint16_t DVCHG : 1; /* [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union { + volatile uint16_t USBADDR; /* (@ 0x00000050) USB Address Register */ + + struct { + volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */ + uint16_t : 1; + volatile uint16_t STSRECOV0 : 3; /* [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + volatile const uint16_t RESERVED9; + + union { + volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */ + + struct { + volatile uint16_t + BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */ + volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union { + volatile uint16_t USBVAL; /* (@ 0x00000056) USB Request Value Register */ + + struct { + volatile uint16_t WVALUE : 16; /* [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union { + volatile uint16_t USBINDX; /* (@ 0x00000058) USB Request Index Register */ + + struct { + volatile uint16_t WINDEX : 16; /* [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union { + volatile uint16_t USBLENG; /* (@ 0x0000005A) USB Request Length Register */ + + struct { + volatile uint16_t WLENGTH : 16; /* [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union { + volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */ + + struct { + uint16_t : 4; + volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ + uint16_t : 2; + volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */ + volatile uint16_t CNTMD : 1; /* [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union { + volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct { + volatile uint16_t MXPS : 7; /* [6..0] Maximum Packet Size */ + uint16_t : 5; + volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ + } DCPMAXP_b; + }; + + union { + volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */ + + struct { + volatile uint16_t PID : 2; /* [1..0] Response PID */ + volatile uint16_t CCPL : 1; /* [2..2] Control Transfer End Enable */ + uint16_t : 2; + volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */ + volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Monitor */ + volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */ + volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */ + uint16_t : 2; + volatile uint16_t SUREQ : 1; /* [14..14] Setup Token Transmission */ + volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ + } DCPCTR_b; + }; + volatile const uint16_t RESERVED10; + + union { + volatile uint16_t PIPESEL; /* (@ 0x00000064) Pipe Window Select Register */ + + struct { + volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + volatile const uint16_t RESERVED11; + + union { + volatile uint16_t PIPECFG; /* (@ 0x00000068) Pipe Configuration Register */ + + struct { + volatile uint16_t EPNUM : 4; /* [3..0] Endpoint Number */ + volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ + uint16_t : 2; + volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */ + volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */ + } PIPECFG_b; + }; + volatile const uint16_t RESERVED12; + + union { + volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct { + volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */ + uint16_t : 3; + volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union { + volatile uint16_t PIPEPERI; /* (@ 0x0000006E) Pipe Cycle Control Register */ + + struct { + volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */ + uint16_t : 9; + volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union { + volatile uint16_t PIPE_CTR[9]; /* (@ 0x00000070) Pipe [0..8] Control Register */ + + struct { + volatile uint16_t PID : 2; /* [1..0] Response PID */ + uint16_t : 3; + volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */ + volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Confirmation */ + volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */ + volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ + volatile uint16_t ACLRM : 1; /* [9..9] Auto Buffer Clear Mode */ + volatile uint16_t ATREPM : 1; /* [10..10] Auto Response Mode */ + uint16_t : 1; + volatile const uint16_t CSSTS : 1; /* [12..12] CSSTS Status */ + volatile uint16_t CSCLR : 1; /* [13..13] CSPLIT Status Clear */ + volatile const uint16_t INBUFM : 1; /* [14..14] Transmit Buffer Monitor */ + volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + volatile const uint16_t RESERVED13; + volatile const uint32_t RESERVED14[3]; + volatile LINK_REG_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */ + volatile const uint32_t RESERVED15[3]; + + union { + volatile uint16_t USBBCCTRL0; /* (@ 0x000000B0) BC Control Register 0 */ + + struct { + volatile uint16_t RPDME0 : 1; /* [0..0] D- Pin Pull-Down Control */ + volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */ + volatile uint16_t + IDMSINKE0 : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + volatile uint16_t + IDPSINKE0 : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + volatile const uint16_t CHGDETSTS0 : 1; /* [8..8] D- Pin 0.6 V Input Detection Status */ + volatile const uint16_t PDDETSTS0 : 1; /* [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + volatile const uint16_t RESERVED16; + volatile const uint32_t RESERVED17[4]; + + union { + volatile uint16_t UCKSEL; /* (@ 0x000000C4) USB Clock Selection Register */ + + struct { + volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + volatile const uint16_t RESERVED18; + volatile const uint32_t RESERVED19; + + union { + volatile uint16_t USBMC; /* (@ 0x000000CC) USB Module Control Register */ + + struct { + volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + volatile uint16_t VDCEN : 1; /* [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + volatile const uint16_t RESERVED20; + + union { + volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */ + + struct { + uint16_t : 6; + volatile uint16_t USBSPD : 2; /* [7..6] Transfer Speed of Communication Target Device */ + volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */ + volatile uint16_t UPPHUB : 4; /* [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + volatile const uint32_t RESERVED21[3]; + + union { + volatile uint32_t PHYSLEW; /* (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct { + volatile uint32_t SLEWR00 : 1; /* [0..0] Receiver Cross Point Adjustment 00 */ + volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */ + volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */ + volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + volatile const uint32_t RESERVED22[3]; + + union { + volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */ + + struct { + uint16_t : 7; + volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union { + volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */ + + struct { + uint16_t : 14; + volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + volatile const uint32_t RESERVED23[15]; + + union { + volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */ + + struct { + volatile uint16_t IDPSRCE : 1; /* [0..0] IDPSRC Control */ + volatile uint16_t IDMSINKE : 1; /* [1..1] IDMSINK Control */ + volatile uint16_t VDPSRCE : 1; /* [2..2] VDPSRC Control */ + volatile uint16_t IDPSINKE : 1; /* [3..3] IDPSINK Control */ + volatile uint16_t VDMSRCE : 1; /* [4..4] VDMSRC Control */ + volatile uint16_t DCPMODE : 1; /* [5..5] DCP Mode Control */ + uint16_t : 2; + volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */ + volatile const uint16_t PDDETSTS : 1; /* [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + volatile const uint16_t RESERVED24; + + union { + volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */ + + struct { + volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */ + volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */ + volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */ + volatile const uint16_t + DVSQ : 4; /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */ + volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */ + uint16_t : 2; + volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union { + volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */ + + struct { + uint16_t : 8; + volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */ + volatile uint16_t RWEMON : 1; /* [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union { + volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */ + + struct { + volatile uint16_t L1REQ : 1; /* [0..0] L1 Transition Request */ + volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union { + volatile uint16_t HL1CTRL2; /* (@ 0x0000014A) Host L1 Control Register 2 */ + + struct { + volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */ + uint16_t : 4; + volatile uint16_t HIRD : 4; /* [11..8] LPM Token HIRD */ + volatile uint16_t L1RWE : 1; /* [12..12] LPM Token L1 Remote Wake Enable */ + uint16_t : 2; + volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */ + } HL1CTRL2_b; + }; + volatile const uint32_t RESERVED25[5]; + + union { + volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */ + + struct { + uint32_t : 20; + volatile const uint32_t + DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */ + volatile const uint32_t + DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */ + uint32_t : 1; + volatile const uint32_t + DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union { + volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct { + uint32_t : 4; + volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */ + volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + volatile uint32_t DVBSTSHE : 1; /* [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + volatile const uint32_t DOVCAH : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */ + volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union { + volatile uint16_t DPUSR2R; /* (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct { + volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */ + volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + volatile const uint16_t + DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */ + volatile const uint16_t + DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */ + uint16_t : 2; + volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */ + volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union { + volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct { + volatile uint16_t FIXPHY : 1; /* [0..0] USB Transceiver Control Fix */ + volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + volatile const uint32_t RESERVED26[165]; + + union { + volatile uint32_t + DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */ + + struct { + volatile uint32_t SRPC0 : 1; /* [0..0] USB Single End Receiver Control */ + volatile uint32_t RPUE0 : 1; /* [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + volatile uint32_t DRPD0 : 1; /* [3..3] D+/D- Pull-Down Resistor Control */ + volatile uint32_t FIXPHY0 : 1; /* [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + volatile const uint32_t DP0 : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + volatile const uint32_t DM0 : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + volatile const uint32_t + DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */ + volatile const uint32_t + DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */ + uint32_t : 1; + volatile const uint32_t + DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union { + volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */ + + struct { + volatile uint32_t DPINTE0 : 1; /* [0..0] USB DP Interrupt Enable/Clear */ + volatile uint32_t DMINTE0 : 1; /* [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + volatile uint32_t DOVRCRAE0 : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */ + volatile uint32_t DOVRCRBE0 : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + volatile uint32_t DVBSE0 : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + volatile const uint32_t DPINT0 : 1; /* [16..16] USB DP Interrupt Source Recovery */ + volatile const uint32_t DMINT0 : 1; /* [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + volatile const uint32_t DOVRCRA0 : 1; /* [20..20] USB OVRCURA Interrupt Source Recovery */ + volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} LINK_REG_t; /* Size = 1032 (0x408) */ + +TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSCFG) == 0x00000000, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BUSWAIT) == 0x00000002, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSSTS0) == 0x00000004, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PLLSTA) == 0x00000006, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DVSTCTR0) == 0x00000008, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, TESTMODE) == 0x0000000C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFO) == 0x00000014, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFO) == 0x00000018, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFO) == 0x0000001C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOSEL) == 0x00000020, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOCTR) == 0x00000022, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOSEL) == 0x00000028, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOCTR) == 0x0000002A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOSEL) == 0x0000002C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOCTR) == 0x0000002E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB0) == 0x00000030, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB1) == 0x00000032, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYENB) == 0x00000036, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYENB) == 0x00000038, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPENB) == 0x0000003A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, SOFCFG) == 0x0000003C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSET) == 0x0000003E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS0) == 0x00000040, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS1) == 0x00000042, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYSTS) == 0x00000046, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYSTS) == 0x00000048, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPSTS) == 0x0000004A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, FRMNUM) == 0x0000004C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, UFRMNUM) == 0x0000004E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBADDR) == 0x00000050, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBREQ) == 0x00000054, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBVAL) == 0x00000056, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBINDX) == 0x00000058, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBLENG) == 0x0000005A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCFG) == 0x0000005C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPMAXP) == 0x0000005E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCTR) == 0x00000060, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPESEL) == 0x00000064, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPECFG) == 0x00000068, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEMAXP) == 0x0000006C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEPERI) == 0x0000006E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_CTR) == 0x00000070, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_TR) == 0x00000090, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBBCCTRL0) == 0x000000B0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, UCKSEL) == 0x000000C4, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBMC) == 0x000000CC, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DEVADD) == 0x000000D0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSLEW) == 0x000000F0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPCTRL) == 0x00000100, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPSTS) == 0x00000102, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BCCTRL) == 0x00000140, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL1) == 0x00000144, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL2) == 0x00000146, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL1) == 0x00000148, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL2) == 0x0000014A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R) == 0x00000160, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R) == 0x00000164, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR2R) == 0x00000168, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSRCR) == 0x0000016A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R_FS) == 0x00000400, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R_FS) == 0x00000404, "incorrect offset"); + +TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */ + TU_ATTR_BIT_FIELD_ORDER_END + +/*--------------------------------------------------------------------*/ +/* Register Bit Definitions */ +/*--------------------------------------------------------------------*/ + +/* PIPE_TR */ +/* E */ +#define LINK_REG_PIPE_TR_E_TRENB_Pos (9UL) /* TRENB (Bit 9) */ +#define LINK_REG_PIPE_TR_E_TRENB_Msk (0x200UL) /* TRENB (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_TR_E_TRCLR_Pos (8UL) /* TRCLR (Bit 8) */ +#define LINK_REG_PIPE_TR_E_TRCLR_Msk (0x100UL) /* TRCLR (Bitfield-Mask: 0x01) */ +/* N */ +#define LINK_REG_PIPE_TR_N_TRNCNT_Pos (0UL) /* TRNCNT (Bit 0) */ +#define LINK_REG_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /* TRNCNT (Bitfield-Mask: 0xffff) */ + +/* LINK_REG */ +/* SYSCFG */ +#define LINK_REG_SYSCFG_SCKE_Pos (10UL) /* SCKE (Bit 10) */ +#define LINK_REG_SYSCFG_SCKE_Msk (0x400UL) /* SCKE (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_CNEN_Pos (8UL) /* CNEN (Bit 8) */ +#define LINK_REG_SYSCFG_CNEN_Msk (0x100UL) /* CNEN (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_DCFM_Pos (6UL) /* DCFM (Bit 6) */ +#define LINK_REG_SYSCFG_DCFM_Msk (0x40UL) /* DCFM (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_DRPD_Pos (5UL) /* DRPD (Bit 5) */ +#define LINK_REG_SYSCFG_DRPD_Msk (0x20UL) /* DRPD (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_DPRPU_Pos (4UL) /* DPRPU (Bit 4) */ +#define LINK_REG_SYSCFG_DPRPU_Msk (0x10UL) /* DPRPU (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_DMRPU_Pos (3UL) /* DMRPU (Bit 3) */ +#define LINK_REG_SYSCFG_DMRPU_Msk (0x8UL) /* DMRPU (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_USBE_Pos (0UL) /* USBE (Bit 0) */ +#define LINK_REG_SYSCFG_USBE_Msk (0x1UL) /* USBE (Bitfield-Mask: 0x01) */ +/* BUSWAIT */ +#define LINK_REG_BUSWAIT_BWAIT_Pos (0UL) /* BWAIT (Bit 0) */ +#define LINK_REG_BUSWAIT_BWAIT_Msk (0xfUL) /* BWAIT (Bitfield-Mask: 0x0f) */ +/* SYSSTS0 */ +#define LINK_REG_SYSSTS0_OVCMON_Pos (14UL) /* OVCMON (Bit 14) */ +#define LINK_REG_SYSSTS0_OVCMON_Msk (0xc000UL) /* OVCMON (Bitfield-Mask: 0x03) */ +#define LINK_REG_SYSSTS0_HTACT_Pos (6UL) /* HTACT (Bit 6) */ +#define LINK_REG_SYSSTS0_HTACT_Msk (0x40UL) /* HTACT (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSSTS0_SOFEA_Pos (5UL) /* SOFEA (Bit 5) */ +#define LINK_REG_SYSSTS0_SOFEA_Msk (0x20UL) /* SOFEA (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSSTS0_IDMON_Pos (2UL) /* IDMON (Bit 2) */ +#define LINK_REG_SYSSTS0_IDMON_Msk (0x4UL) /* IDMON (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSSTS0_LNST_Pos (0UL) /* LNST (Bit 0) */ +#define LINK_REG_SYSSTS0_LNST_Msk (0x3UL) /* LNST (Bitfield-Mask: 0x03) */ +/* PLLSTA */ +#define LINK_REG_PLLSTA_PLLLOCK_Pos (0UL) /* PLLLOCK (Bit 0) */ +#define LINK_REG_PLLSTA_PLLLOCK_Msk (0x1UL) /* PLLLOCK (Bitfield-Mask: 0x01) */ +/* DVSTCTR0 */ +#define LINK_REG_DVSTCTR0_HNPBTOA_Pos (11UL) /* HNPBTOA (Bit 11) */ +#define LINK_REG_DVSTCTR0_HNPBTOA_Msk (0x800UL) /* HNPBTOA (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_EXICEN_Pos (10UL) /* EXICEN (Bit 10) */ +#define LINK_REG_DVSTCTR0_EXICEN_Msk (0x400UL) /* EXICEN (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_VBUSEN_Pos (9UL) /* VBUSEN (Bit 9) */ +#define LINK_REG_DVSTCTR0_VBUSEN_Msk (0x200UL) /* VBUSEN (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_WKUP_Pos (8UL) /* WKUP (Bit 8) */ +#define LINK_REG_DVSTCTR0_WKUP_Msk (0x100UL) /* WKUP (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_RWUPE_Pos (7UL) /* RWUPE (Bit 7) */ +#define LINK_REG_DVSTCTR0_RWUPE_Msk (0x80UL) /* RWUPE (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_USBRST_Pos (6UL) /* USBRST (Bit 6) */ +#define LINK_REG_DVSTCTR0_USBRST_Msk (0x40UL) /* USBRST (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_RESUME_Pos (5UL) /* RESUME (Bit 5) */ +#define LINK_REG_DVSTCTR0_RESUME_Msk (0x20UL) /* RESUME (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_UACT_Pos (4UL) /* UACT (Bit 4) */ +#define LINK_REG_DVSTCTR0_UACT_Msk (0x10UL) /* UACT (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_RHST_Pos (0UL) /* RHST (Bit 0) */ +#define LINK_REG_DVSTCTR0_RHST_Msk (0x7UL) /* RHST (Bitfield-Mask: 0x07) */ +/* TESTMODE */ +#define LINK_REG_TESTMODE_UTST_Pos (0UL) /* UTST (Bit 0) */ +#define LINK_REG_TESTMODE_UTST_Msk (0xfUL) /* UTST (Bitfield-Mask: 0x0f) */ +/* CFIFOSEL */ +#define LINK_REG_CFIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ +#define LINK_REG_CFIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ +#define LINK_REG_CFIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ +#define LINK_REG_CFIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ +#define LINK_REG_CFIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ +#define LINK_REG_CFIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOSEL_ISEL_Pos (5UL) /* ISEL (Bit 5) */ +#define LINK_REG_CFIFOSEL_ISEL_Msk (0x20UL) /* ISEL (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ +#define LINK_REG_CFIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ +/* CFIFOCTR */ +#define LINK_REG_CFIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ +#define LINK_REG_CFIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ +#define LINK_REG_CFIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ +#define LINK_REG_CFIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ +#define LINK_REG_CFIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ +/* D0FIFOSEL */ +#define LINK_REG_D0FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ +#define LINK_REG_D0FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ +#define LINK_REG_D0FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ +#define LINK_REG_D0FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ +#define LINK_REG_D0FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ +#define LINK_REG_D0FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ +#define LINK_REG_D0FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ +#define LINK_REG_D0FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ +#define LINK_REG_D0FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ +/* D0FIFOCTR */ +#define LINK_REG_D0FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ +#define LINK_REG_D0FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ +#define LINK_REG_D0FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ +#define LINK_REG_D0FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ +#define LINK_REG_D0FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ +/* D1FIFOSEL */ +#define LINK_REG_D1FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ +#define LINK_REG_D1FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ +#define LINK_REG_D1FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ +#define LINK_REG_D1FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ +#define LINK_REG_D1FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ +#define LINK_REG_D1FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ +#define LINK_REG_D1FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ +#define LINK_REG_D1FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ +#define LINK_REG_D1FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ +/* D1FIFOCTR */ +#define LINK_REG_D1FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ +#define LINK_REG_D1FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ +#define LINK_REG_D1FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ +#define LINK_REG_D1FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ +#define LINK_REG_D1FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ +/* INTENB0 */ +#define LINK_REG_INTENB0_VBSE_Pos (15UL) /* VBSE (Bit 15) */ +#define LINK_REG_INTENB0_VBSE_Msk (0x8000UL) /* VBSE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_RSME_Pos (14UL) /* RSME (Bit 14) */ +#define LINK_REG_INTENB0_RSME_Msk (0x4000UL) /* RSME (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_SOFE_Pos (13UL) /* SOFE (Bit 13) */ +#define LINK_REG_INTENB0_SOFE_Msk (0x2000UL) /* SOFE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_DVSE_Pos (12UL) /* DVSE (Bit 12) */ +#define LINK_REG_INTENB0_DVSE_Msk (0x1000UL) /* DVSE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_CTRE_Pos (11UL) /* CTRE (Bit 11) */ +#define LINK_REG_INTENB0_CTRE_Msk (0x800UL) /* CTRE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_BEMPE_Pos (10UL) /* BEMPE (Bit 10) */ +#define LINK_REG_INTENB0_BEMPE_Msk (0x400UL) /* BEMPE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_NRDYE_Pos (9UL) /* NRDYE (Bit 9) */ +#define LINK_REG_INTENB0_NRDYE_Msk (0x200UL) /* NRDYE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_BRDYE_Pos (8UL) /* BRDYE (Bit 8) */ +#define LINK_REG_INTENB0_BRDYE_Msk (0x100UL) /* BRDYE (Bitfield-Mask: 0x01) */ +/* INTENB1 */ +#define LINK_REG_INTENB1_OVRCRE_Pos (15UL) /* OVRCRE (Bit 15) */ +#define LINK_REG_INTENB1_OVRCRE_Msk (0x8000UL) /* OVRCRE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_BCHGE_Pos (14UL) /* BCHGE (Bit 14) */ +#define LINK_REG_INTENB1_BCHGE_Msk (0x4000UL) /* BCHGE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_DTCHE_Pos (12UL) /* DTCHE (Bit 12) */ +#define LINK_REG_INTENB1_DTCHE_Msk (0x1000UL) /* DTCHE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_ATTCHE_Pos (11UL) /* ATTCHE (Bit 11) */ +#define LINK_REG_INTENB1_ATTCHE_Msk (0x800UL) /* ATTCHE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_EOFERRE_Pos (6UL) /* EOFERRE (Bit 6) */ +#define LINK_REG_INTENB1_EOFERRE_Msk (0x40UL) /* EOFERRE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_SIGNE_Pos (5UL) /* SIGNE (Bit 5) */ +#define LINK_REG_INTENB1_SIGNE_Msk (0x20UL) /* SIGNE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_SACKE_Pos (4UL) /* SACKE (Bit 4) */ +#define LINK_REG_INTENB1_SACKE_Msk (0x10UL) /* SACKE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_PDDETINTE0_Pos (0UL) /* PDDETINTE0 (Bit 0) */ +#define LINK_REG_INTENB1_PDDETINTE0_Msk (0x1UL) /* PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* BRDYENB */ +#define LINK_REG_BRDYENB_PIPEBRDYE_Pos (0UL) /* PIPEBRDYE (Bit 0) */ +#define LINK_REG_BRDYENB_PIPEBRDYE_Msk (0x1UL) /* PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* NRDYENB */ +#define LINK_REG_NRDYENB_PIPENRDYE_Pos (0UL) /* PIPENRDYE (Bit 0) */ +#define LINK_REG_NRDYENB_PIPENRDYE_Msk (0x1UL) /* PIPENRDYE (Bitfield-Mask: 0x01) */ +/* BEMPENB */ +#define LINK_REG_BEMPENB_PIPEBEMPE_Pos (0UL) /* PIPEBEMPE (Bit 0) */ +#define LINK_REG_BEMPENB_PIPEBEMPE_Msk (0x1UL) /* PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* SOFCFG */ +#define LINK_REG_SOFCFG_TRNENSEL_Pos (8UL) /* TRNENSEL (Bit 8) */ +#define LINK_REG_SOFCFG_TRNENSEL_Msk (0x100UL) /* TRNENSEL (Bitfield-Mask: 0x01) */ +#define LINK_REG_SOFCFG_BRDYM_Pos (6UL) /* BRDYM (Bit 6) */ +#define LINK_REG_SOFCFG_BRDYM_Msk (0x40UL) /* BRDYM (Bitfield-Mask: 0x01) */ +#define LINK_REG_SOFCFG_INTL_Pos (5UL) /* INTL (Bit 5) */ +#define LINK_REG_SOFCFG_INTL_Msk (0x20UL) /* INTL (Bitfield-Mask: 0x01) */ +#define LINK_REG_SOFCFG_EDGESTS_Pos (4UL) /* EDGESTS (Bit 4) */ +#define LINK_REG_SOFCFG_EDGESTS_Msk (0x10UL) /* EDGESTS (Bitfield-Mask: 0x01) */ +/* PHYSET */ +#define LINK_REG_PHYSET_HSEB_Pos (15UL) /* HSEB (Bit 15) */ +#define LINK_REG_PHYSET_HSEB_Msk (0x8000UL) /* HSEB (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSET_REPSTART_Pos (11UL) /* REPSTART (Bit 11) */ +#define LINK_REG_PHYSET_REPSTART_Msk (0x800UL) /* REPSTART (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSET_REPSEL_Pos (8UL) /* REPSEL (Bit 8) */ +#define LINK_REG_PHYSET_REPSEL_Msk (0x300UL) /* REPSEL (Bitfield-Mask: 0x03) */ +#define LINK_REG_PHYSET_CLKSEL_Pos (4UL) /* CLKSEL (Bit 4) */ +#define LINK_REG_PHYSET_CLKSEL_Msk (0x30UL) /* CLKSEL (Bitfield-Mask: 0x03) */ +#define LINK_REG_PHYSET_CDPEN_Pos (3UL) /* CDPEN (Bit 3) */ +#define LINK_REG_PHYSET_CDPEN_Msk (0x8UL) /* CDPEN (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSET_PLLRESET_Pos (1UL) /* PLLRESET (Bit 1) */ +#define LINK_REG_PHYSET_PLLRESET_Msk (0x2UL) /* PLLRESET (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSET_DIRPD_Pos (0UL) /* DIRPD (Bit 0) */ +#define LINK_REG_PHYSET_DIRPD_Msk (0x1UL) /* DIRPD (Bitfield-Mask: 0x01) */ +/* INTSTS0 */ +#define LINK_REG_INTSTS0_VBINT_Pos (15UL) /* VBINT (Bit 15) */ +#define LINK_REG_INTSTS0_VBINT_Msk (0x8000UL) /* VBINT (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_RESM_Pos (14UL) /* RESM (Bit 14) */ +#define LINK_REG_INTSTS0_RESM_Msk (0x4000UL) /* RESM (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_SOFR_Pos (13UL) /* SOFR (Bit 13) */ +#define LINK_REG_INTSTS0_SOFR_Msk (0x2000UL) /* SOFR (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_DVST_Pos (12UL) /* DVST (Bit 12) */ +#define LINK_REG_INTSTS0_DVST_Msk (0x1000UL) /* DVST (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_CTRT_Pos (11UL) /* CTRT (Bit 11) */ +#define LINK_REG_INTSTS0_CTRT_Msk (0x800UL) /* CTRT (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_BEMP_Pos (10UL) /* BEMP (Bit 10) */ +#define LINK_REG_INTSTS0_BEMP_Msk (0x400UL) /* BEMP (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_NRDY_Pos (9UL) /* NRDY (Bit 9) */ +#define LINK_REG_INTSTS0_NRDY_Msk (0x200UL) /* NRDY (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_BRDY_Pos (8UL) /* BRDY (Bit 8) */ +#define LINK_REG_INTSTS0_BRDY_Msk (0x100UL) /* BRDY (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_VBSTS_Pos (7UL) /* VBSTS (Bit 7) */ +#define LINK_REG_INTSTS0_VBSTS_Msk (0x80UL) /* VBSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ +#define LINK_REG_INTSTS0_DVSQ_Msk (0x70UL) /* DVSQ (Bitfield-Mask: 0x07) */ +#define LINK_REG_INTSTS0_VALID_Pos (3UL) /* VALID (Bit 3) */ +#define LINK_REG_INTSTS0_VALID_Msk (0x8UL) /* VALID (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_CTSQ_Pos (0UL) /* CTSQ (Bit 0) */ +#define LINK_REG_INTSTS0_CTSQ_Msk (0x7UL) /* CTSQ (Bitfield-Mask: 0x07) */ +/* INTSTS1 */ +#define LINK_REG_INTSTS1_OVRCR_Pos (15UL) /* OVRCR (Bit 15) */ +#define LINK_REG_INTSTS1_OVRCR_Msk (0x8000UL) /* OVRCR (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_BCHG_Pos (14UL) /* BCHG (Bit 14) */ +#define LINK_REG_INTSTS1_BCHG_Msk (0x4000UL) /* BCHG (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_DTCH_Pos (12UL) /* DTCH (Bit 12) */ +#define LINK_REG_INTSTS1_DTCH_Msk (0x1000UL) /* DTCH (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_ATTCH_Pos (11UL) /* ATTCH (Bit 11) */ +#define LINK_REG_INTSTS1_ATTCH_Msk (0x800UL) /* ATTCH (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_L1RSMEND_Pos (9UL) /* L1RSMEND (Bit 9) */ +#define LINK_REG_INTSTS1_L1RSMEND_Msk (0x200UL) /* L1RSMEND (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_LPMEND_Pos (8UL) /* LPMEND (Bit 8) */ +#define LINK_REG_INTSTS1_LPMEND_Msk (0x100UL) /* LPMEND (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_EOFERR_Pos (6UL) /* EOFERR (Bit 6) */ +#define LINK_REG_INTSTS1_EOFERR_Msk (0x40UL) /* EOFERR (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_SIGN_Pos (5UL) /* SIGN (Bit 5) */ +#define LINK_REG_INTSTS1_SIGN_Msk (0x20UL) /* SIGN (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_SACK_Pos (4UL) /* SACK (Bit 4) */ +#define LINK_REG_INTSTS1_SACK_Msk (0x10UL) /* SACK (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_PDDETINT0_Pos (0UL) /* PDDETINT0 (Bit 0) */ +#define LINK_REG_INTSTS1_PDDETINT0_Msk (0x1UL) /* PDDETINT0 (Bitfield-Mask: 0x01) */ +/* BRDYSTS */ +#define LINK_REG_BRDYSTS_PIPEBRDY_Pos (0UL) /* PIPEBRDY (Bit 0) */ +#define LINK_REG_BRDYSTS_PIPEBRDY_Msk (0x1UL) /* PIPEBRDY (Bitfield-Mask: 0x01) */ +/* NRDYSTS */ +#define LINK_REG_NRDYSTS_PIPENRDY_Pos (0UL) /* PIPENRDY (Bit 0) */ +#define LINK_REG_NRDYSTS_PIPENRDY_Msk (0x1UL) /* PIPENRDY (Bitfield-Mask: 0x01) */ +/* BEMPSTS */ +#define LINK_REG_BEMPSTS_PIPEBEMP_Pos (0UL) /* PIPEBEMP (Bit 0) */ +#define LINK_REG_BEMPSTS_PIPEBEMP_Msk (0x1UL) /* PIPEBEMP (Bitfield-Mask: 0x01) */ +/* FRMNUM */ +#define LINK_REG_FRMNUM_OVRN_Pos (15UL) /* OVRN (Bit 15) */ +#define LINK_REG_FRMNUM_OVRN_Msk (0x8000UL) /* OVRN (Bitfield-Mask: 0x01) */ +#define LINK_REG_FRMNUM_CRCE_Pos (14UL) /* CRCE (Bit 14) */ +#define LINK_REG_FRMNUM_CRCE_Msk (0x4000UL) /* CRCE (Bitfield-Mask: 0x01) */ +#define LINK_REG_FRMNUM_FRNM_Pos (0UL) /* FRNM (Bit 0) */ +#define LINK_REG_FRMNUM_FRNM_Msk (0x7ffUL) /* FRNM (Bitfield-Mask: 0x7ff) */ +/* UFRMNUM */ +#define LINK_REG_UFRMNUM_DVCHG_Pos (15UL) /* DVCHG (Bit 15) */ +#define LINK_REG_UFRMNUM_DVCHG_Msk (0x8000UL) /* DVCHG (Bitfield-Mask: 0x01) */ +#define LINK_REG_UFRMNUM_UFRNM_Pos (0UL) /* UFRNM (Bit 0) */ +#define LINK_REG_UFRMNUM_UFRNM_Msk (0x7UL) /* UFRNM (Bitfield-Mask: 0x07) */ +/* USBADDR */ +#define LINK_REG_USBADDR_STSRECOV0_Pos (8UL) /* STSRECOV0 (Bit 8) */ +#define LINK_REG_USBADDR_STSRECOV0_Msk (0x700UL) /* STSRECOV0 (Bitfield-Mask: 0x07) */ +#define LINK_REG_USBADDR_USBADDR_Pos (0UL) /* USBADDR (Bit 0) */ +#define LINK_REG_USBADDR_USBADDR_Msk (0x7fUL) /* USBADDR (Bitfield-Mask: 0x7f) */ +/* USBREQ */ +#define LINK_REG_USBREQ_BREQUEST_Pos (8UL) /* BREQUEST (Bit 8) */ +#define LINK_REG_USBREQ_BREQUEST_Msk (0xff00UL) /* BREQUEST (Bitfield-Mask: 0xff) */ +#define LINK_REG_USBREQ_BMREQUESTTYPE_Pos (0UL) /* BMREQUESTTYPE (Bit 0) */ +#define LINK_REG_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* USBVAL */ +#define LINK_REG_USBVAL_WVALUE_Pos (0UL) /* WVALUE (Bit 0) */ +#define LINK_REG_USBVAL_WVALUE_Msk (0xffffUL) /* WVALUE (Bitfield-Mask: 0xffff) */ +/* USBINDX */ +#define LINK_REG_USBINDX_WINDEX_Pos (0UL) /* WINDEX (Bit 0) */ +#define LINK_REG_USBINDX_WINDEX_Msk (0xffffUL) /* WINDEX (Bitfield-Mask: 0xffff) */ +/* USBLENG */ +#define LINK_REG_USBLENG_WLENGTH_Pos (0UL) /* WLENGTH (Bit 0) */ +#define LINK_REG_USBLENG_WLENGTH_Msk (0xffffUL) /* WLENGTH (Bitfield-Mask: 0xffff) */ +/* DCPCFG */ +#define LINK_REG_DCPCFG_CNTMD_Pos (8UL) /* CNTMD (Bit 8) */ +#define LINK_REG_DCPCFG_CNTMD_Msk (0x100UL) /* CNTMD (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ +#define LINK_REG_DCPCFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCFG_DIR_Pos (4UL) /* DIR (Bit 4) */ +#define LINK_REG_DCPCFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ +/* DCPMAXP */ +#define LINK_REG_DCPMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ +#define LINK_REG_DCPMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ +#define LINK_REG_DCPMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ +#define LINK_REG_DCPMAXP_MXPS_Msk (0x7fUL) /* MXPS (Bitfield-Mask: 0x7f) */ +/* DCPCTR */ +#define LINK_REG_DCPCTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ +#define LINK_REG_DCPCTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_SUREQ_Pos (14UL) /* SUREQ (Bit 14) */ +#define LINK_REG_DCPCTR_SUREQ_Msk (0x4000UL) /* SUREQ (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_SUREQCLR_Pos (11UL) /* SUREQCLR (Bit 11) */ +#define LINK_REG_DCPCTR_SUREQCLR_Msk (0x800UL) /* SUREQCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ +#define LINK_REG_DCPCTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ +#define LINK_REG_DCPCTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ +#define LINK_REG_DCPCTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ +#define LINK_REG_DCPCTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_CCPL_Pos (2UL) /* CCPL (Bit 2) */ +#define LINK_REG_DCPCTR_CCPL_Msk (0x4UL) /* CCPL (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_PID_Pos (0UL) /* PID (Bit 0) */ +#define LINK_REG_DCPCTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ +/* PIPESEL */ +#define LINK_REG_PIPESEL_PIPESEL_Pos (0UL) /* PIPESEL (Bit 0) */ +#define LINK_REG_PIPESEL_PIPESEL_Msk (0xfUL) /* PIPESEL (Bitfield-Mask: 0x0f) */ +/* PIPECFG */ +#define LINK_REG_PIPECFG_TYPE_Pos (14UL) /* TYPE (Bit 14) */ +#define LINK_REG_PIPECFG_TYPE_Msk (0xc000UL) /* TYPE (Bitfield-Mask: 0x03) */ +#define LINK_REG_PIPECFG_BFRE_Pos (10UL) /* BFRE (Bit 10) */ +#define LINK_REG_PIPECFG_BFRE_Msk (0x400UL) /* BFRE (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPECFG_DBLB_Pos (9UL) /* DBLB (Bit 9) */ +#define LINK_REG_PIPECFG_DBLB_Msk (0x200UL) /* DBLB (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPECFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ +#define LINK_REG_PIPECFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPECFG_DIR_Pos (4UL) /* DIR (Bit 4) */ +#define LINK_REG_PIPECFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPECFG_EPNUM_Pos (0UL) /* EPNUM (Bit 0) */ +#define LINK_REG_PIPECFG_EPNUM_Msk (0xfUL) /* EPNUM (Bitfield-Mask: 0x0f) */ +/* PIPEMAXP */ +#define LINK_REG_PIPEMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ +#define LINK_REG_PIPEMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ +#define LINK_REG_PIPEMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ +#define LINK_REG_PIPEMAXP_MXPS_Msk (0x1ffUL) /* MXPS (Bitfield-Mask: 0x1ff) */ +/* PIPEPERI */ +#define LINK_REG_PIPEPERI_IFIS_Pos (12UL) /* IFIS (Bit 12) */ +#define LINK_REG_PIPEPERI_IFIS_Msk (0x1000UL) /* IFIS (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPEPERI_IITV_Pos (0UL) /* IITV (Bit 0) */ +#define LINK_REG_PIPEPERI_IITV_Msk (0x7UL) /* IITV (Bitfield-Mask: 0x07) */ +/* PIPE_CTR */ +#define LINK_REG_PIPE_CTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ +#define LINK_REG_PIPE_CTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_INBUFM_Pos (14UL) /* INBUFM (Bit 14) */ +#define LINK_REG_PIPE_CTR_INBUFM_Msk (0x4000UL) /* INBUFM (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_CSCLR_Pos (13UL) /* CSCLR (Bit 13) */ +#define LINK_REG_PIPE_CTR_CSCLR_Msk (0x2000UL) /* CSCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_CSSTS_Pos (12UL) /* CSSTS (Bit 12) */ +#define LINK_REG_PIPE_CTR_CSSTS_Msk (0x1000UL) /* CSSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_ATREPM_Pos (10UL) /* ATREPM (Bit 10) */ +#define LINK_REG_PIPE_CTR_ATREPM_Msk (0x400UL) /* ATREPM (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_ACLRM_Pos (9UL) /* ACLRM (Bit 9) */ +#define LINK_REG_PIPE_CTR_ACLRM_Msk (0x200UL) /* ACLRM (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ +#define LINK_REG_PIPE_CTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ +#define LINK_REG_PIPE_CTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ +#define LINK_REG_PIPE_CTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ +#define LINK_REG_PIPE_CTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_PID_Pos (0UL) /* PID (Bit 0) */ +#define LINK_REG_PIPE_CTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ +/* DEVADD */ +#define LINK_REG_DEVADD_UPPHUB_Pos (11UL) /* UPPHUB (Bit 11) */ +#define LINK_REG_DEVADD_UPPHUB_Msk (0x7800UL) /* UPPHUB (Bitfield-Mask: 0x0f) */ +#define LINK_REG_DEVADD_HUBPORT_Pos (8UL) /* HUBPORT (Bit 8) */ +#define LINK_REG_DEVADD_HUBPORT_Msk (0x700UL) /* HUBPORT (Bitfield-Mask: 0x07) */ +#define LINK_REG_DEVADD_USBSPD_Pos (6UL) /* USBSPD (Bit 6) */ +#define LINK_REG_DEVADD_USBSPD_Msk (0xc0UL) /* USBSPD (Bitfield-Mask: 0x03) */ +/* USBBCCTRL0 */ +#define LINK_REG_USBBCCTRL0_PDDETSTS0_Pos (9UL) /* PDDETSTS0 (Bit 9) */ +#define LINK_REG_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /* PDDETSTS0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /* CHGDETSTS0 (Bit 8) */ +#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /* CHGDETSTS0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_BATCHGE0_Pos (7UL) /* BATCHGE0 (Bit 7) */ +#define LINK_REG_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /* BATCHGE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_VDMSRCE0_Pos (5UL) /* VDMSRCE0 (Bit 5) */ +#define LINK_REG_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /* VDMSRCE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_IDPSINKE0_Pos (4UL) /* IDPSINKE0 (Bit 4) */ +#define LINK_REG_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /* IDPSINKE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_VDPSRCE0_Pos (3UL) /* VDPSRCE0 (Bit 3) */ +#define LINK_REG_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /* VDPSRCE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_IDMSINKE0_Pos (2UL) /* IDMSINKE0 (Bit 2) */ +#define LINK_REG_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /* IDMSINKE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_IDPSRCE0_Pos (1UL) /* IDPSRCE0 (Bit 1) */ +#define LINK_REG_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /* IDPSRCE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_RPDME0_Pos (0UL) /* RPDME0 (Bit 0) */ +#define LINK_REG_USBBCCTRL0_RPDME0_Msk (0x1UL) /* RPDME0 (Bitfield-Mask: 0x01) */ +/* UCKSEL */ +#define LINK_REG_UCKSEL_UCKSELC_Pos (0UL) /* UCKSELC (Bit 0) */ +#define LINK_REG_UCKSEL_UCKSELC_Msk (0x1UL) /* UCKSELC (Bitfield-Mask: 0x01) */ +/* USBMC */ +#define LINK_REG_USBMC_VDCEN_Pos (7UL) /* VDCEN (Bit 7) */ +#define LINK_REG_USBMC_VDCEN_Msk (0x80UL) /* VDCEN (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBMC_VDDUSBE_Pos (0UL) /* VDDUSBE (Bit 0) */ +#define LINK_REG_USBMC_VDDUSBE_Msk (0x1UL) /* VDDUSBE (Bitfield-Mask: 0x01) */ +/* PHYSLEW */ +#define LINK_REG_PHYSLEW_SLEWF01_Pos (3UL) /* SLEWF01 (Bit 3) */ +#define LINK_REG_PHYSLEW_SLEWF01_Msk (0x8UL) /* SLEWF01 (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSLEW_SLEWF00_Pos (2UL) /* SLEWF00 (Bit 2) */ +#define LINK_REG_PHYSLEW_SLEWF00_Msk (0x4UL) /* SLEWF00 (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSLEW_SLEWR01_Pos (1UL) /* SLEWR01 (Bit 1) */ +#define LINK_REG_PHYSLEW_SLEWR01_Msk (0x2UL) /* SLEWR01 (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSLEW_SLEWR00_Pos (0UL) /* SLEWR00 (Bit 0) */ +#define LINK_REG_PHYSLEW_SLEWR00_Msk (0x1UL) /* SLEWR00 (Bitfield-Mask: 0x01) */ +/* LPCTRL */ +#define LINK_REG_LPCTRL_HWUPM_Pos (7UL) /* HWUPM (Bit 7) */ +#define LINK_REG_LPCTRL_HWUPM_Msk (0x80UL) /* HWUPM (Bitfield-Mask: 0x01) */ +/* LPSTS */ +#define LINK_REG_LPSTS_SUSPENDM_Pos (14UL) /* SUSPENDM (Bit 14) */ +#define LINK_REG_LPSTS_SUSPENDM_Msk (0x4000UL) /* SUSPENDM (Bitfield-Mask: 0x01) */ +/* BCCTRL */ +#define LINK_REG_BCCTRL_PDDETSTS_Pos (9UL) /* PDDETSTS (Bit 9) */ +#define LINK_REG_BCCTRL_PDDETSTS_Msk (0x200UL) /* PDDETSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_CHGDETSTS_Pos (8UL) /* CHGDETSTS (Bit 8) */ +#define LINK_REG_BCCTRL_CHGDETSTS_Msk (0x100UL) /* CHGDETSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_DCPMODE_Pos (5UL) /* DCPMODE (Bit 5) */ +#define LINK_REG_BCCTRL_DCPMODE_Msk (0x20UL) /* DCPMODE (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_VDMSRCE_Pos (4UL) /* VDMSRCE (Bit 4) */ +#define LINK_REG_BCCTRL_VDMSRCE_Msk (0x10UL) /* VDMSRCE (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_IDPSINKE_Pos (3UL) /* IDPSINKE (Bit 3) */ +#define LINK_REG_BCCTRL_IDPSINKE_Msk (0x8UL) /* IDPSINKE (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_VDPSRCE_Pos (2UL) /* VDPSRCE (Bit 2) */ +#define LINK_REG_BCCTRL_VDPSRCE_Msk (0x4UL) /* VDPSRCE (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_IDMSINKE_Pos (1UL) /* IDMSINKE (Bit 1) */ +#define LINK_REG_BCCTRL_IDMSINKE_Msk (0x2UL) /* IDMSINKE (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_IDPSRCE_Pos (0UL) /* IDPSRCE (Bit 0) */ +#define LINK_REG_BCCTRL_IDPSRCE_Msk (0x1UL) /* IDPSRCE (Bitfield-Mask: 0x01) */ +/* PL1CTRL1 */ +#define LINK_REG_PL1CTRL1_L1EXTMD_Pos (14UL) /* L1EXTMD (Bit 14) */ +#define LINK_REG_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /* L1EXTMD (Bitfield-Mask: 0x01) */ +#define LINK_REG_PL1CTRL1_HIRDTHR_Pos (8UL) /* HIRDTHR (Bit 8) */ +#define LINK_REG_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /* HIRDTHR (Bitfield-Mask: 0x0f) */ +#define LINK_REG_PL1CTRL1_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ +#define LINK_REG_PL1CTRL1_DVSQ_Msk (0xf0UL) /* DVSQ (Bitfield-Mask: 0x0f) */ +#define LINK_REG_PL1CTRL1_L1NEGOMD_Pos (3UL) /* L1NEGOMD (Bit 3) */ +#define LINK_REG_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /* L1NEGOMD (Bitfield-Mask: 0x01) */ +#define LINK_REG_PL1CTRL1_L1RESPMD_Pos (1UL) /* L1RESPMD (Bit 1) */ +#define LINK_REG_PL1CTRL1_L1RESPMD_Msk (0x6UL) /* L1RESPMD (Bitfield-Mask: 0x03) */ +#define LINK_REG_PL1CTRL1_L1RESPEN_Pos (0UL) /* L1RESPEN (Bit 0) */ +#define LINK_REG_PL1CTRL1_L1RESPEN_Msk (0x1UL) /* L1RESPEN (Bitfield-Mask: 0x01) */ +/* PL1CTRL2 */ +#define LINK_REG_PL1CTRL2_RWEMON_Pos (12UL) /* RWEMON (Bit 12) */ +#define LINK_REG_PL1CTRL2_RWEMON_Msk (0x1000UL) /* RWEMON (Bitfield-Mask: 0x01) */ +#define LINK_REG_PL1CTRL2_HIRDMON_Pos (8UL) /* HIRDMON (Bit 8) */ +#define LINK_REG_PL1CTRL2_HIRDMON_Msk (0xf00UL) /* HIRDMON (Bitfield-Mask: 0x0f) */ +/* HL1CTRL1 */ +#define LINK_REG_HL1CTRL1_L1STATUS_Pos (1UL) /* L1STATUS (Bit 1) */ +#define LINK_REG_HL1CTRL1_L1STATUS_Msk (0x6UL) /* L1STATUS (Bitfield-Mask: 0x03) */ +#define LINK_REG_HL1CTRL1_L1REQ_Pos (0UL) /* L1REQ (Bit 0) */ +#define LINK_REG_HL1CTRL1_L1REQ_Msk (0x1UL) /* L1REQ (Bitfield-Mask: 0x01) */ +/* HL1CTRL2 */ +#define LINK_REG_HL1CTRL2_BESL_Pos (15UL) /* BESL (Bit 15) */ +#define LINK_REG_HL1CTRL2_BESL_Msk (0x8000UL) /* BESL (Bitfield-Mask: 0x01) */ +#define LINK_REG_HL1CTRL2_L1RWE_Pos (12UL) /* L1RWE (Bit 12) */ +#define LINK_REG_HL1CTRL2_L1RWE_Msk (0x1000UL) /* L1RWE (Bitfield-Mask: 0x01) */ +#define LINK_REG_HL1CTRL2_HIRD_Pos (8UL) /* HIRD (Bit 8) */ +#define LINK_REG_HL1CTRL2_HIRD_Msk (0xf00UL) /* HIRD (Bitfield-Mask: 0x0f) */ +#define LINK_REG_HL1CTRL2_L1ADDR_Pos (0UL) /* L1ADDR (Bit 0) */ +#define LINK_REG_HL1CTRL2_L1ADDR_Msk (0xfUL) /* L1ADDR (Bitfield-Mask: 0x0f) */ +/* DPUSR0R */ +#define LINK_REG_DPUSR0R_DVBSTSHM_Pos (23UL) /* DVBSTSHM (Bit 23) */ +#define LINK_REG_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_DOVCBHM_Pos (21UL) /* DOVCBHM (Bit 21) */ +#define LINK_REG_DPUSR0R_DOVCBHM_Msk (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_DOVCAHM_Pos (20UL) /* DOVCAHM (Bit 20) */ +#define LINK_REG_DPUSR0R_DOVCAHM_Msk (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */ +/* DPUSR1R */ +#define LINK_REG_DPUSR1R_DVBSTSH_Pos (23UL) /* DVBSTSH (Bit 23) */ +#define LINK_REG_DPUSR1R_DVBSTSH_Msk (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_DOVCBH_Pos (21UL) /* DOVCBH (Bit 21) */ +#define LINK_REG_DPUSR1R_DOVCBH_Msk (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_DOVCAH_Pos (20UL) /* DOVCAH (Bit 20) */ +#define LINK_REG_DPUSR1R_DOVCAH_Msk (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_DVBSTSHE_Pos (7UL) /* DVBSTSHE (Bit 7) */ +#define LINK_REG_DPUSR1R_DVBSTSHE_Msk (0x80UL) /* DVBSTSHE (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_DOVCBHE_Pos (5UL) /* DOVCBHE (Bit 5) */ +#define LINK_REG_DPUSR1R_DOVCBHE_Msk (0x20UL) /* DOVCBHE (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_DOVCAHE_Pos (4UL) /* DOVCAHE (Bit 4) */ +#define LINK_REG_DPUSR1R_DOVCAHE_Msk (0x10UL) /* DOVCAHE (Bitfield-Mask: 0x01) */ +/* DPUSR2R */ +#define LINK_REG_DPUSR2R_DMINTE_Pos (9UL) /* DMINTE (Bit 9) */ +#define LINK_REG_DPUSR2R_DMINTE_Msk (0x200UL) /* DMINTE (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR2R_DPINTE_Pos (8UL) /* DPINTE (Bit 8) */ +#define LINK_REG_DPUSR2R_DPINTE_Msk (0x100UL) /* DPINTE (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR2R_DMVAL_Pos (5UL) /* DMVAL (Bit 5) */ +#define LINK_REG_DPUSR2R_DMVAL_Msk (0x20UL) /* DMVAL (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR2R_DPVAL_Pos (4UL) /* DPVAL (Bit 4) */ +#define LINK_REG_DPUSR2R_DPVAL_Msk (0x10UL) /* DPVAL (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR2R_DMINT_Pos (1UL) /* DMINT (Bit 1) */ +#define LINK_REG_DPUSR2R_DMINT_Msk (0x2UL) /* DMINT (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR2R_DPINT_Pos (0UL) /* DPINT (Bit 0) */ +#define LINK_REG_DPUSR2R_DPINT_Msk (0x1UL) /* DPINT (Bitfield-Mask: 0x01) */ +/* DPUSRCR */ +#define LINK_REG_DPUSRCR_FIXPHYPD_Pos (1UL) /* FIXPHYPD (Bit 1) */ +#define LINK_REG_DPUSRCR_FIXPHYPD_Msk (0x2UL) /* FIXPHYPD (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSRCR_FIXPHY_Pos (0UL) /* FIXPHY (Bit 0) */ +#define LINK_REG_DPUSRCR_FIXPHY_Msk (0x1UL) /* FIXPHY (Bitfield-Mask: 0x01) */ +/* DPUSR0R_FS */ +#define LINK_REG_DPUSR0R_FS_DVBSTS0_Pos (23UL) /* DVBSTS0 (Bit 23) */ +#define LINK_REG_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_DOVCB0_Pos (21UL) /* DOVCB0 (Bit 21) */ +#define LINK_REG_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_DOVCA0_Pos (20UL) /* DOVCA0 (Bit 20) */ +#define LINK_REG_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_DM0_Pos (17UL) /* DM0 (Bit 17) */ +#define LINK_REG_DPUSR0R_FS_DM0_Msk (0x20000UL) /* DM0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_DP0_Pos (16UL) /* DP0 (Bit 16) */ +#define LINK_REG_DPUSR0R_FS_DP0_Msk (0x10000UL) /* DP0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_FIXPHY0_Pos (4UL) /* FIXPHY0 (Bit 4) */ +#define LINK_REG_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /* FIXPHY0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_DRPD0_Pos (3UL) /* DRPD0 (Bit 3) */ +#define LINK_REG_DPUSR0R_FS_DRPD0_Msk (0x8UL) /* DRPD0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_RPUE0_Pos (1UL) /* RPUE0 (Bit 1) */ +#define LINK_REG_DPUSR0R_FS_RPUE0_Msk (0x2UL) /* RPUE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_SRPC0_Pos (0UL) /* SRPC0 (Bit 0) */ +#define LINK_REG_DPUSR0R_FS_SRPC0_Msk (0x1UL) /* SRPC0 (Bitfield-Mask: 0x01) */ +/* DPUSR1R_FS */ +#define LINK_REG_DPUSR1R_FS_DVBINT0_Pos (23UL) /* DVBINT0 (Bit 23) */ +#define LINK_REG_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /* DOVRCRB0 (Bit 21) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /* DOVRCRA0 (Bit 20) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DMINT0_Pos (17UL) /* DMINT0 (Bit 17) */ +#define LINK_REG_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /* DMINT0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DPINT0_Pos (16UL) /* DPINT0 (Bit 16) */ +#define LINK_REG_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /* DPINT0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DVBSE0_Pos (7UL) /* DVBSE0 (Bit 7) */ +#define LINK_REG_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /* DVBSE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /* DOVRCRBE0 (Bit 5) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /* DOVRCRBE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /* DOVRCRAE0 (Bit 4) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /* DOVRCRAE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DMINTE0_Pos (1UL) /* DMINTE0 (Bit 1) */ +#define LINK_REG_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /* DMINTE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DPINTE0_Pos (0UL) /* DPINTE0 (Bit 0) */ +#define LINK_REG_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /* DPINTE0 (Bitfield-Mask: 0x01) */ + +#ifdef __cplusplus +} +#endif + +#endif /* _TUSB_LINK_TYPE_H_ */ -- cgit v1.3.1 From a936bafb8c1e0c6f125fdae90ffe57bf0deed57c Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Wed, 9 Mar 2022 12:19:45 +0000 Subject: add support for renesas ra family of mcus Signed-off-by: Rafael Silva --- src/common/tusb_mcu.h | 2 +- src/portable/renesas/link/dcd_link.c | 5 ++- src/portable/renesas/link/hcd_link.c | 5 ++- src/portable/renesas/link/link_ra.h | 64 ++++++++++++++++++++++++++++++++++++ src/tusb_option.h | 2 ++ 5 files changed, 75 insertions(+), 3 deletions(-) create mode 100644 src/portable/renesas/link/link_ra.h (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index c1cf2a810..5daa37f04 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -236,7 +236,7 @@ #define TUP_DCD_ENDPOINT_MAX 7 //------------- Renesas -------------// -#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) +#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N, OPT_MCU_RAXXX) #define TUP_DCD_ENDPOINT_MAX 10 //------------- GigaDevice -------------// diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c index 3aeda9e4c..19fbfe293 100644 --- a/src/portable/renesas/link/dcd_link.c +++ b/src/portable/renesas/link/dcd_link.c @@ -31,13 +31,16 @@ // We disable SOF for now until needed later on #define USE_SOF 0 -#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N) +#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N || \ + CFG_TUSB_MCU == OPT_MCU_RAXXX) #include "device/dcd.h" #include "link_type.h" #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #include "link_rx.h" +#elif TU_CHECK_MCU(OPT_MCU_RAXXX) +#include "link_ra.h" #else #error "Unsupported MCU" #endif diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c index 46a4aae8f..2ada28105 100644 --- a/src/portable/renesas/link/hcd_link.c +++ b/src/portable/renesas/link/hcd_link.c @@ -27,13 +27,16 @@ #include "tusb_option.h" -#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N) +#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N || \ + CFG_TUSB_MCU == OPT_MCU_RAXXX) #include "host/hcd.h" #include "link_type.h" #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #include "link_rx.h" +#elif TU_CHECK_MCU(OPT_MCU_RAXXX) +#include "link_ra.h" #else #error "Unsupported MCU" #endif diff --git a/src/portable/renesas/link/link_ra.h b/src/portable/renesas/link/link_ra.h new file mode 100644 index 000000000..b42def368 --- /dev/null +++ b/src/portable/renesas/link/link_ra.h @@ -0,0 +1,64 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2022 Rafael Silva (@perigoso) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _LINK_RA_H_ +#define _LINK_RA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "link_type.h" + +/* renesas fsp api */ +#include "bsp_api.h" + +#define LINK_REG_BASE (0x40090000) + +TU_ATTR_ALWAYS_INLINE +static inline void link_int_enable(uint8_t rhport) +{ + (void) rhport; + NVIC_EnableIRQ(TU_IRQn); +} + +TU_ATTR_ALWAYS_INLINE +static inline void link_int_disable(uint8_t rhport) +{ + (void) rhport; + NVIC_DisableIRQ(TU_IRQn); +} + +// MCU specific PHY init +static inline void link_phy_init(void) +{ +} + +#ifdef __cplusplus +} +#endif + +#endif /* _LINK_RA_H_ */ diff --git a/src/tusb_option.h b/src/tusb_option.h index 3b054fc78..16bdedce5 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -127,6 +127,8 @@ typedef int make_iso_compilers_happy ; #define OPT_MCU_RX63X 1400 ///< Renesas RX63N/631 #define OPT_MCU_RX65X 1401 ///< Renesas RX65N/RX651 #define OPT_MCU_RX72N 1402 ///< Renesas RX72N +#define OPT_MCU_RAXXX 1403 ///< Renesas RAxxx families + // Mind Motion #define OPT_MCU_MM32F327X 1500 ///< Mind Motion MM32F327 -- cgit v1.3.1 From c529d0b4405aa33b4793d03ce82568990c3f507c Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Wed, 9 Mar 2022 15:55:35 +0000 Subject: remove duplicate link register bit macros Signed-off-by: Rafael Silva --- src/portable/renesas/link/dcd_link.c | 108 +++++++++++++++++----------------- src/portable/renesas/link/hcd_link.c | 98 +++++++++++++++--------------- src/portable/renesas/link/link_type.h | 98 ++++++++++-------------------- 3 files changed, 136 insertions(+), 168 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c index 19fbfe293..f2334140a 100644 --- a/src/portable/renesas/link/dcd_link.c +++ b/src/portable/renesas/link/dcd_link.c @@ -32,7 +32,7 @@ #define USE_SOF 0 #if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N || \ - CFG_TUSB_MCU == OPT_MCU_RAXXX) + CFG_TUSB_MCU == OPT_MCU_RAXXX) #include "device/dcd.h" #include "link_type.h" @@ -245,7 +245,7 @@ static bool pipe0_xfer_in(void) } } if (len < mps) - LINK_REG->CFIFOCTR = USB_FIFOCTR_BVAL; + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; pipe->remaining = rem - len; return false; } @@ -268,7 +268,7 @@ static bool pipe0_xfer_out(void) } } if (len < mps) - LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR; + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; @@ -287,7 +287,7 @@ static bool pipe_xfer_in(unsigned num) return true; } - LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); + LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); const unsigned mps = edpt_max_packet_size(num); pipe_wait_for_ready(num); const unsigned len = TU_MIN(rem, mps); @@ -301,7 +301,7 @@ static bool pipe_xfer_in(unsigned num) } } if (len < mps) - LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL; + LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; LINK_REG->D0FIFOSEL = 0; while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; @@ -313,7 +313,7 @@ static bool pipe_xfer_out(unsigned num) pipe_state_t *pipe = &_dcd.pipe[num]; const unsigned rem = pipe->remaining; - LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_8; + LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT; const unsigned mps = edpt_max_packet_size(num); pipe_wait_for_ready(num); const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN; @@ -328,7 +328,7 @@ static bool pipe_xfer_out(unsigned num) } } if (len < mps) - LINK_REG->D0FIFOCTR = USB_FIFOCTR_BCLR; + LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; LINK_REG->D0FIFOSEL = 0; while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; @@ -342,13 +342,13 @@ static bool pipe_xfer_out(unsigned num) static void process_setup_packet(uint8_t rhport) { uint16_t setup_packet[4]; - if (0 == (LINK_REG->INTSTS0 & USB_IS0_VALID)) return; - LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR; + if (0 == (LINK_REG->INTSTS0 & LINK_REG_INTSTS0_VALID_Msk)) return; + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; setup_packet[0] = tu_le16toh(LINK_REG->USBREQ); setup_packet[1] = LINK_REG->USBVAL; setup_packet[2] = LINK_REG->USBINDX; setup_packet[3] = LINK_REG->USBLENG; - LINK_REG->INTSTS0 = ~USB_IS0_VALID; + LINK_REG->INTSTS0 = ~((uint16_t)LINK_REG_INTSTS0_VALID_Msk); dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true); } @@ -356,7 +356,7 @@ static void process_status_completion(uint8_t rhport) { uint8_t ep_addr; /* Check the data stage direction */ - if (LINK_REG->CFIFOSEL & USB_FIFOSEL_TX) { + if (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) { /* IN transfer. */ ep_addr = tu_edpt_addr(0, TUSB_DIR_IN); } else { @@ -370,12 +370,12 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u { /* configure fifo direction and access unit settings */ if (ep_addr) { /* IN, 2 bytes */ - LINK_REG->CFIFOSEL = - USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); - while (!(LINK_REG->CFIFOSEL & USB_FIFOSEL_TX)) ; + LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT | + (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); + while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ; } else { /* OUT, a byte */ - LINK_REG->CFIFOSEL = USB_FIFOSEL_MBW_8; - while (LINK_REG->CFIFOSEL & USB_FIFOSEL_TX) ; + LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT; + while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ; } pipe_state_t *pipe = &_dcd.pipe[0]; @@ -388,11 +388,11 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80)); pipe0_xfer_in(); } - LINK_REG->DCPCTR = USB_PIPECTR_PID_BUF; + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF; } else { /* ZLP */ pipe->buf = NULL; - LINK_REG->DCPCTR = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF; + LINK_REG->DCPCTR = LINK_REG_DCPCTR_CCPL_Msk | LINK_REG_PIPE_CTR_PID_BUF; } return true; } @@ -416,7 +416,7 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui } else { /* ZLP */ LINK_REG->D0FIFOSEL = num; pipe_wait_for_ready(num); - LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL; + LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; LINK_REG->D0FIFOSEL = 0; while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ } @@ -429,11 +429,11 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui if (pt) { const unsigned mps = edpt_max_packet_size(num); volatile uint16_t *ctr = get_pipectr(num); - if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK; + if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK; pt->TRE = TU_BIT(8); pt->TRN = (total_bytes + mps - 1) / mps; pt->TRENB = 1; - *ctr = USB_PIPECTR_PID_BUF; + *ctr = LINK_REG_PIPE_CTR_PID_BUF; } } // TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type); @@ -487,7 +487,7 @@ static void process_bus_reset(uint8_t rhport) { LINK_REG->BEMPENB = 1; LINK_REG->BRDYENB = 1; - LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR; + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; LINK_REG->D0FIFOSEL = 0; while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ LINK_REG->D1FIFOSEL = 0; @@ -497,7 +497,7 @@ static void process_bus_reset(uint8_t rhport) for (int i = 1; i <= 5; ++i) { LINK_REG->PIPESEL = i; LINK_REG->PIPECFG = 0; - *ctr = USB_PIPECTR_ACLRM; + *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk; *ctr = 0; ++ctr; *tre = TU_BIT(8); @@ -506,7 +506,7 @@ static void process_bus_reset(uint8_t rhport) for (int i = 6; i <= 9; ++i) { LINK_REG->PIPESEL = i; LINK_REG->PIPECFG = 0; - *ctr = USB_PIPECTR_ACLRM; + *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk; *ctr = 0; ++ctr; } @@ -553,8 +553,9 @@ void dcd_init(uint8_t rhport) /* Setup default control pipe */ LINK_REG->DCPMAXP_b.MXPS = 64; - LINK_REG->INTENB0 = USB_IS0_VBINT | USB_IS0_BRDY | USB_IS0_BEMP | USB_IS0_DVST | USB_IS0_CTRT | - (USE_SOF ? USB_IS0_SOFR : 0) | USB_IS0_RESM; + LINK_REG->INTENB0 = LINK_REG_INTSTS0_VBINT_Msk | LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk | + LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_CTRT_Msk | (USE_SOF ? LINK_REG_INTSTS0_SOFR_Msk : 0) | + LINK_REG_INTSTS0_RESM_Msk; LINK_REG->BEMPENB = 1; LINK_REG->BRDYENB = 1; @@ -633,21 +634,21 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) LINK_REG->PIPESEL = num; LINK_REG->PIPEMAXP = mps; volatile uint16_t *ctr = get_pipectr(num); - *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR; + *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk; *ctr = 0; unsigned cfg = (dir << 4) | epn; if (xfer == TUSB_XFER_BULK) { - cfg |= (USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB); + cfg |= (LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk); } else if (xfer == TUSB_XFER_INTERRUPT) { - cfg |= USB_PIPECFG_INT; + cfg |= LINK_REG_PIPECFG_TYPE_ISO; } else { - cfg |= (USB_PIPECFG_ISO | USB_PIPECFG_DBLB); + cfg |= (LINK_REG_PIPECFG_TYPE_INT | LINK_REG_PIPECFG_DBLB_Msk); } LINK_REG->PIPECFG = cfg; LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num); LINK_REG->BRDYENB |= TU_BIT(num); if (dir || (xfer != TUSB_XFER_BULK)) { - *ctr = USB_PIPECTR_PID_BUF; + *ctr = LINK_REG_PIPE_CTR_PID_BUF; } // TU_LOG1("O %d %x %x\r\n", LINK_REG->PIPESEL, LINK_REG->PIPECFG, LINK_REG->PIPEMAXP); dcd_int_enable(rhport); @@ -709,8 +710,8 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) if (!ctr) return; dcd_int_disable(rhport); const uint32_t pid = *ctr & 0x3; - *ctr = pid | USB_PIPECTR_PID_STALL; - *ctr = USB_PIPECTR_PID_STALL; + *ctr = pid | LINK_REG_PIPE_CTR_PID_STALL; + *ctr = LINK_REG_PIPE_CTR_PID_STALL; dcd_int_enable(rhport); } @@ -719,15 +720,15 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr); if (!ctr) return; dcd_int_disable(rhport); - *ctr = USB_PIPECTR_SQCLR; + *ctr = LINK_REG_PIPE_CTR_SQCLR_Msk; if (tu_edpt_dir(ep_addr)) { /* IN */ - *ctr = USB_PIPECTR_PID_BUF; + *ctr = LINK_REG_PIPE_CTR_PID_BUF; } else { const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)]; LINK_REG->PIPESEL = num; if (LINK_REG->PIPECFG_b.TYPE != 1) { - *ctr = USB_PIPECTR_PID_BUF; + *ctr = LINK_REG_PIPE_CTR_PID_BUF; } } dcd_int_enable(rhport); @@ -742,39 +743,40 @@ void dcd_int_handler(uint8_t rhport) unsigned is0 = LINK_REG->INTSTS0; /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ - LINK_REG->INTSTS0 = ~((USB_IS0_CTRT | USB_IS0_DVST | USB_IS0_SOFR | USB_IS0_RESM | USB_IS0_VBINT) & is0) | USB_IS0_VALID; - if (is0 & USB_IS0_VBINT) { + LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_CTRT_Msk | LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_SOFR_Msk | + LINK_REG_INTSTS0_RESM_Msk | LINK_REG_INTSTS0_VBINT_Msk) & is0) | LINK_REG_INTSTS0_VALID_Msk; + if (is0 & LINK_REG_INTSTS0_VBINT_Msk) { if (LINK_REG->INTSTS0_b.VBSTS) { dcd_connect(rhport); } else { dcd_disconnect(rhport); } } - if (is0 & USB_IS0_RESM) { + if (is0 & LINK_REG_INTSTS0_RESM_Msk) { dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); #if (0==USE_SOF) LINK_REG->INTENB0_b.SOFE = 0; #endif } - if ((is0 & USB_IS0_SOFR) && LINK_REG->INTENB0_b.SOFE) { + if ((is0 & LINK_REG_INTSTS0_SOFR_Msk) && LINK_REG->INTENB0_b.SOFE) { // USBD will exit suspended mode when SOF event is received dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); #if (0 == USE_SOF) LINK_REG->INTENB0_b.SOFE = 0; #endif } - if (is0 & USB_IS0_DVST) { - switch (is0 & USB_IS0_DVSQ) { - case USB_IS0_DVSQ_DEF: + if (is0 & LINK_REG_INTSTS0_DVST_Msk) { + switch (is0 & LINK_REG_INTSTS0_DVSQ_Msk) { + case LINK_REG_INTSTS0_DVSQ_STATE_DEF: process_bus_reset(rhport); break; - case USB_IS0_DVSQ_ADDR: + case LINK_REG_INTSTS0_DVSQ_STATE_ADDR: process_set_address(rhport); break; - case USB_IS0_DVSQ_SUSP0: - case USB_IS0_DVSQ_SUSP1: - case USB_IS0_DVSQ_SUSP2: - case USB_IS0_DVSQ_SUSP3: + case LINK_REG_INTSTS0_DVSQ_STATE_SUSP0: + case LINK_REG_INTSTS0_DVSQ_STATE_SUSP1: + case LINK_REG_INTSTS0_DVSQ_STATE_SUSP2: + case LINK_REG_INTSTS0_DVSQ_STATE_SUSP3: dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); #if (0==USE_SOF) LINK_REG->INTENB0_b.SOFE = 1; @@ -783,23 +785,23 @@ void dcd_int_handler(uint8_t rhport) break; } } - if (is0 & USB_IS0_CTRT) { - if (is0 & USB_IS0_CTSQ_SETUP) { + if (is0 & LINK_REG_INTSTS0_CTRT_Msk) { + if (is0 & LINK_REG_INTSTS0_CTSQ_CTRL_RDATA) { /* A setup packet has been received. */ process_setup_packet(rhport); - } else if (0 == (is0 & USB_IS0_CTSQ_MSK)) { + } else if (0 == (is0 & LINK_REG_INTSTS0_CTSQ_Msk)) { /* A ZLP has been sent/received. */ process_status_completion(rhport); } } - if (is0 & USB_IS0_BEMP) { + if (is0 & LINK_REG_INTSTS0_BEMP_Msk) { const unsigned s = LINK_REG->BEMPSTS; LINK_REG->BEMPSTS = 0; if (s & 1) { process_pipe0_bemp(rhport); } } - if (is0 & USB_IS0_BRDY) { + if (is0 & LINK_REG_INTSTS0_BRDY_Msk) { const unsigned m = LINK_REG->BRDYENB; unsigned s = LINK_REG->BRDYSTS & m; /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c index 2ada28105..940013c86 100644 --- a/src/portable/renesas/link/hcd_link.c +++ b/src/portable/renesas/link/hcd_link.c @@ -207,18 +207,18 @@ static bool pipe0_xfer_in(void) const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { - LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK; + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } if (len < mps) - LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR; + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; return true; } - LINK_REG->DCPCTR = USB_PIPECTR_PID_BUF; + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF; return false; } @@ -238,7 +238,7 @@ static bool pipe0_xfer_out(void) pipe->buf = (uint8_t*)buf + len; } if (len < mps) - LINK_REG->CFIFOCTR = USB_FIFOCTR_BVAL; + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; pipe->remaining = rem - len; return false; } @@ -248,7 +248,7 @@ static bool pipe_xfer_in(unsigned num) pipe_state_t *pipe = &_hcd.pipe[num]; const unsigned rem = pipe->remaining; - LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_8; + LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT; const unsigned mps = edpt_max_packet_size(num); pipe_wait_for_ready(num); const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN; @@ -259,7 +259,7 @@ static bool pipe_xfer_in(unsigned num) pipe->buf = (uint8_t*)buf + len; } if (len < mps) - LINK_REG->D0FIFOCTR = USB_FIFOCTR_BCLR; + LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; LINK_REG->D0FIFOSEL = 0; while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; @@ -280,7 +280,7 @@ static bool pipe_xfer_out(unsigned num) return true; } - LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); + LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); const unsigned mps = edpt_max_packet_size(num); pipe_wait_for_ready(num); const unsigned len = TU_MIN(rem, mps); @@ -290,7 +290,7 @@ static bool pipe_xfer_out(unsigned num) pipe->buf = (uint8_t*)buf + len; } if (len < mps) - LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL; + LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; LINK_REG->D0FIFOSEL = 0; while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; @@ -304,12 +304,12 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, /* configure fifo direction and access unit settings */ if (dir_in) { /* IN, a byte */ - LINK_REG->CFIFOSEL = USB_FIFOSEL_MBW_8; - while (LINK_REG->CFIFOSEL & USB_FIFOSEL_TX) ; + LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT; + while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ; } else { /* OUT, 2 bytes */ - LINK_REG->CFIFOSEL = - USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); - while (!(LINK_REG->CFIFOSEL & USB_FIFOSEL_TX)) ; + LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT | + (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); + while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ; } pipe_state_t *pipe = &_hcd.pipe[0]; @@ -325,15 +325,15 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, } else { /* ZLP */ pipe->buf = NULL; if (!dir_in) { /* OUT */ - LINK_REG->CFIFOCTR = USB_FIFOCTR_BVAL; + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; } if (dir_in == LINK_REG->DCPCFG_b.DIR) { - TU_ASSERT(USB_PIPECTR_PID_NAK == LINK_REG->DCPCTR_b.PID); + TU_ASSERT(LINK_REG_PIPE_CTR_PID_NAK == LINK_REG->DCPCTR_b.PID); LINK_REG->DCPCTR_b.SQSET = 1; LINK_REG->DCPCFG_b.DIR = dir_in ^ 1; } } - LINK_REG->DCPCTR = USB_PIPECTR_PID_BUF; + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF; return true; } @@ -355,7 +355,7 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u } else { /* ZLP */ LINK_REG->D0FIFOSEL = num; pipe_wait_for_ready(num); - LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL; + LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; LINK_REG->D0FIFOSEL = 0; while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */ } @@ -364,12 +364,12 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u volatile reg_pipetre_t *pt = get_pipetre(num); if (pt) { const unsigned mps = edpt_max_packet_size(num); - if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK; + if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK; pt->TRE = TU_BIT(8); pt->TRN = (buflen + mps - 1) / mps; pt->TRENB = 1; } - *ctr = USB_PIPECTR_PID_BUF; + *ctr = LINK_REG_PIPE_CTR_PID_BUF; } return true; } @@ -403,10 +403,10 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num) unsigned result; uint16_t volatile *ctr = get_pipectr(num); // TU_LOG1("NRDY %d %x\n", num, *ctr); - switch (*ctr & USB_PIPECTR_PID_MSK) { + switch (*ctr & LINK_REG_PIPE_CTR_PID_Msk) { default: return; - case USB_PIPECTR_PID_STALL: result = XFER_RESULT_STALLED; break; - case USB_PIPECTR_PID_NAK: result = XFER_RESULT_FAILED; break; + case LINK_REG_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break; + case LINK_REG_PIPE_CTR_PID_NAK: result = XFER_RESULT_FAILED; break; } pipe_state_t *pipe = &_hcd.pipe[num]; hcd_event_xfer_complete(pipe->dev, pipe->ep, @@ -464,10 +464,10 @@ bool hcd_init(uint8_t rhport) LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */ /* Setup default control pipe */ - LINK_REG->DCPCFG = USB_PIPECFG_SHTNAK; + LINK_REG->DCPCFG = LINK_REG_PIPECFG_SHTNAK_Msk; LINK_REG->DCPMAXP = 64; - LINK_REG->INTENB0 = USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP; - LINK_REG->INTENB1 = USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH; + LINK_REG->INTENB0 = LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk; + LINK_REG->INTENB1 = LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk; LINK_REG->BEMPENB = 1; LINK_REG->NRDYENB = 1; LINK_REG->BRDYENB = 1; @@ -505,7 +505,7 @@ bool hcd_port_connect_status(uint8_t rhport) void hcd_port_reset(uint8_t rhport) { - LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK; + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; while (LINK_REG->DCPCTR_b.PBUSY) ; hcd_int_disable(rhport); LINK_REG->DVSTCTR0_b.UACT = 0; @@ -530,8 +530,8 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport) (void)rhport; switch (LINK_REG->DVSTCTR0_b.RHST) { default: return TUSB_SPEED_INVALID; - case USB_DVSTCTR0_FULL: return TUSB_SPEED_FULL; - case USB_DVSTCTR0_LOW: return TUSB_SPEED_LOW; + case LINK_REG_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL; + case LINK_REG_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW; } } @@ -572,7 +572,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ TU_ASSERT(0 == LINK_REG->DCPCTR_b.SUREQ); - LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK; + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; _hcd.pipe[0].buf = NULL; _hcd.pipe[0].length = 8; @@ -605,14 +605,14 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const const unsigned epn = tu_edpt_number(ep_addr); const unsigned mps = tu_edpt_packet_size(ep_desc); if (0 == epn) { - LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK; + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; hcd_devtree_info_t devtree; hcd_devtree_get_info(dev_addr, &devtree); uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &LINK_REG->DEVADD[0]; devadd += dev_addr; while (LINK_REG->DCPCTR_b.PBUSY) ; LINK_REG->DCPMAXP = (dev_addr << 12) | mps; - *devadd = (TUSB_SPEED_FULL == devtree.speed) ? USB_DEVADD_FULL : USB_DEVADD_LOW; + *devadd = (TUSB_SPEED_FULL == devtree.speed) ? LINK_REG_DEVADD_USBSPD_FS : LINK_REG_DEVADD_USBSPD_LS; _hcd.ctl_mps[dev_addr] = mps; return true; } @@ -634,22 +634,22 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const LINK_REG->PIPESEL = num; LINK_REG->PIPEMAXP = (dev_addr << 12) | mps; volatile uint16_t *ctr = get_pipectr(num); - *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR; + *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk; *ctr = 0; unsigned cfg = ((1 ^ dir_in) << 4) | epn; if (xfer == TUSB_XFER_BULK) { - cfg |= USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB; + cfg |= LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk; } else if (xfer == TUSB_XFER_INTERRUPT) { - cfg |= USB_PIPECFG_INT; + cfg |= LINK_REG_PIPECFG_TYPE_ISO; } else { - cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB; + cfg |= LINK_REG_PIPECFG_TYPE_INT | LINK_REG_PIPECFG_DBLB_Msk; } LINK_REG->PIPECFG = cfg; LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num); LINK_REG->NRDYENB |= TU_BIT(num); LINK_REG->BRDYENB |= TU_BIT(num); if (!dir_in) { - *ctr = USB_PIPECTR_PID_BUF; + *ctr = LINK_REG_PIPE_CTR_PID_BUF; } hcd_int_enable(rhport); @@ -676,12 +676,12 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) *ctr = pid & 2; *ctr = 0; } - *ctr = USB_PIPECTR_SQCLR; + *ctr = LINK_REG_PIPE_CTR_SQCLR_Msk; unsigned const epn = tu_edpt_number(ep_addr); if (!epn) return true; if (!tu_edpt_dir(ep_addr)) { /* OUT */ - *ctr = USB_PIPECTR_PID_BUF; + *ctr = LINK_REG_PIPE_CTR_PID_BUF; } return true; } @@ -702,44 +702,44 @@ void hcd_int_handler(uint8_t rhport) unsigned is1 = LINK_REG->INTSTS1; unsigned is0 = LINK_REG->INTSTS0; /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ - LINK_REG->INTSTS1 = ~((USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH) & is1); - LINK_REG->INTSTS0 = ~((USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP) & is0); + LINK_REG->INTSTS1 = ~((LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk) & is1); + LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk) & is0); // TU_LOG1("IS %04x %04x\n", is0, is1); is1 &= LINK_REG->INTENB1; is0 &= LINK_REG->INTENB0; - if (is1 & USB_IS1_SACK) { + if (is1 & LINK_REG_INTSTS1_SACK_Msk) { /* Set DATA1 in advance for the next transfer. */ LINK_REG->DCPCTR_b.SQSET = 1; hcd_event_xfer_complete( LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); } - if (is1 & USB_IS1_SIGN) { + if (is1 & LINK_REG_INTSTS1_SIGN_Msk) { hcd_event_xfer_complete( LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); } - if (is1 & USB_IS1_ATTCH) { + if (is1 & LINK_REG_INTSTS1_ATTCH_Msk) { LINK_REG->DVSTCTR0_b.UACT = 1; _hcd.need_reset = true; - LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~USB_IS1_ATTCH) | USB_IS1_DTCH; + LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_ATTCH_Msk) | LINK_REG_INTSTS1_DTCH_Msk; hcd_event_device_attach(rhport, true); } - if (is1 & USB_IS1_DTCH) { + if (is1 & LINK_REG_INTSTS1_DTCH_Msk) { LINK_REG->DVSTCTR0_b.UACT = 0; if (LINK_REG->DCPCTR_b.SUREQ) LINK_REG->DCPCTR_b.SUREQCLR = 1; - LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~USB_IS1_DTCH) | USB_IS1_ATTCH; + LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_DTCH_Msk) | LINK_REG_INTSTS1_ATTCH_Msk; hcd_event_device_remove(rhport, true); } - if (is0 & USB_IS0_BEMP) { + if (is0 & LINK_REG_INTSTS0_BEMP_Msk) { const unsigned s = LINK_REG->BEMPSTS; LINK_REG->BEMPSTS = 0; if (s & 1) { process_pipe0_bemp(rhport); } } - if (is0 & USB_IS0_NRDY) { + if (is0 & LINK_REG_INTSTS0_NRDY_Msk) { const unsigned m = LINK_REG->NRDYENB; unsigned s = LINK_REG->NRDYSTS & m; LINK_REG->NRDYSTS = ~s; @@ -753,7 +753,7 @@ void hcd_int_handler(uint8_t rhport) s &= ~TU_BIT(num); } } - if (is0 & USB_IS0_BRDY) { + if (is0 & LINK_REG_INTSTS0_BRDY_Msk) { const unsigned m = LINK_REG->BRDYENB; unsigned s = LINK_REG->BRDYSTS & m; /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ diff --git a/src/portable/renesas/link/link_type.h b/src/portable/renesas/link/link_type.h index 33cf7879e..f1d0130cc 100644 --- a/src/portable/renesas/link/link_type.h +++ b/src/portable/renesas/link/link_type.h @@ -33,72 +33,6 @@ extern "C" { #endif -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM DECLARATION -//--------------------------------------------------------------------+ -#define USB_DVSTCTR0_LOW (1u) -#define USB_DVSTCTR0_FULL (2u) - -#define USB_FIFOSEL_TX ((uint16_t) (1u << 5)) -#define USB_FIFOSEL_BIGEND ((uint16_t) (1u << 8)) -#define USB_FIFOSEL_MBW_8 ((uint16_t) (0u << 10)) -#define USB_FIFOSEL_MBW_16 ((uint16_t) (1u << 10)) -#define USB_IS0_CTSQ ((uint16_t) (7u)) -#define USB_IS0_DVSQ ((uint16_t) (7u << 4)) -#define USB_IS0_VALID ((uint16_t) (1u << 3)) -#define USB_IS0_BRDY ((uint16_t) (1u << 8)) -#define USB_IS0_NRDY ((uint16_t) (1u << 9)) -#define USB_IS0_BEMP ((uint16_t) (1u << 10)) -#define USB_IS0_CTRT ((uint16_t) (1u << 11)) -#define USB_IS0_DVST ((uint16_t) (1u << 12)) -#define USB_IS0_SOFR ((uint16_t) (1u << 13)) -#define USB_IS0_RESM ((uint16_t) (1u << 14)) -#define USB_IS0_VBINT ((uint16_t) (1u << 15)) -#define USB_IS1_SACK ((uint16_t) (1u << 4)) -#define USB_IS1_SIGN ((uint16_t) (1u << 5)) -#define USB_IS1_EOFERR ((uint16_t) (1u << 6)) -#define USB_IS1_ATTCH ((uint16_t) (1u << 11)) -#define USB_IS1_DTCH ((uint16_t) (1u << 12)) -#define USB_IS1_BCHG ((uint16_t) (1u << 14)) -#define USB_IS1_OVRCR ((uint16_t) (1u << 15)) - -#define USB_IS0_CTSQ_MSK (7u) -#define USB_IS0_CTSQ_SETUP (1u) -#define USB_IS0_DVSQ_DEF (1u << 4) -#define USB_IS0_DVSQ_ADDR (2u << 4) -#define USB_IS0_DVSQ_SUSP0 (4u << 4) -#define USB_IS0_DVSQ_SUSP1 (5u << 4) -#define USB_IS0_DVSQ_SUSP2 (6u << 4) -#define USB_IS0_DVSQ_SUSP3 (7u << 4) - -#define USB_PIPECTR_PID_MSK (3u) -#define USB_PIPECTR_PID_NAK (0u) -#define USB_PIPECTR_PID_BUF (1u) -#define USB_PIPECTR_PID_STALL (2u) -#define USB_PIPECTR_CCPL (1u << 2) -#define USB_PIPECTR_SQMON (1u << 6) -#define USB_PIPECTR_SQCLR (1u << 8) -#define USB_PIPECTR_ACLRM (1u << 9) -#define USB_PIPECTR_INBUFM (1u << 14) -#define USB_PIPECTR_BSTS (1u << 15) - -#define USB_FIFOCTR_DTLN (0x1FF) -#define USB_FIFOCTR_FRDY (1u << 13) -#define USB_FIFOCTR_BCLR (1u << 14) -#define USB_FIFOCTR_BVAL (1u << 15) - -#define USB_PIPECFG_SHTNAK (1u << 7) -#define USB_PIPECFG_DBLB (1u << 9) -#define USB_PIPECFG_BULK (1u << 14) -#define USB_PIPECFG_ISO (3u << 14) -#define USB_PIPECFG_INT (2u << 14) - -#define FIFO_REQ_CLR (1u) -#define FIFO_COMPLETE (1u << 1) - -#define USB_DEVADD_LOW (1u << 6) -#define USB_DEVADD_FULL (2u << 6) - /*--------------------------------------------------------------------*/ /* Register Definitions */ /*--------------------------------------------------------------------*/ @@ -1651,6 +1585,38 @@ TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX tool #define LINK_REG_DPUSR1R_FS_DPINTE0_Pos (0UL) /* DPINTE0 (Bit 0) */ #define LINK_REG_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /* DPINTE0 (Bitfield-Mask: 0x01) */ +/*--------------------------------------------------------------------*/ +/* Register Bit Utils */ +/*--------------------------------------------------------------------*/ +#define LINK_REG_PIPE_CTR_PID_NAK (0U << LINK_REG_PIPE_CTR_PID_Pos) /* NAK response */ +#define LINK_REG_PIPE_CTR_PID_BUF (1U << LINK_REG_PIPE_CTR_PID_Pos) /* BUF response (depends buffer state) */ +#define LINK_REG_PIPE_CTR_PID_STALL (2U << LINK_REG_PIPE_CTR_PID_Pos) /* STALL response */ + +#define LINK_REG_DVSTCTR0_RHST_LS (1U << LINK_REG_DVSTCTR0_RHST_Pos) /* Low-speed connection */ +#define LINK_REG_DVSTCTR0_RHST_FS (2U << LINK_REG_DVSTCTR0_RHST_Pos) /* Full-speed connection */ + +#define LINK_REG_DEVADD_USBSPD_LS (1U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Low-speed */ +#define LINK_REG_DEVADD_USBSPD_FS (2U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Full-speed */ + +#define LINK_REG_CFIFOSEL_ISEL_WRITE (1U << LINK_REG_CFIFOSEL_ISEL_Pos) /* FIFO write AKA TX*/ + +#define LINK_REG_FIFOSEL_BIGEND (1U << LINK_REG_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */ +#define LINK_REG_FIFOSEL_MBW_8BIT (0U << LINK_REG_CFIFOSEL_MBW_Pos) /* 8-bit width */ +#define LINK_REG_FIFOSEL_MBW_16BIT (1U << LINK_REG_CFIFOSEL_MBW_Pos) /* 16-bit width */ + +#define LINK_REG_INTSTS0_CTSQ_CTRL_RDATA (1U << LINK_REG_INTSTS0_CTSQ_Pos) + +#define LINK_REG_INTSTS0_DVSQ_STATE_DEF (1U << LINK_REG_INTSTS0_DVSQ_Pos) /* Default state */ +#define LINK_REG_INTSTS0_DVSQ_STATE_ADDR (2U << LINK_REG_INTSTS0_DVSQ_Pos) /* Address state */ +#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP0 (4U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ +#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP1 (5U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ +#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP2 (6U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ +#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP3 (7U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ + +#define LINK_REG_PIPECFG_TYPE_BULK (1U << LINK_REG_PIPECFG_TYPE_Pos) +#define LINK_REG_PIPECFG_TYPE_INT (2U << LINK_REG_PIPECFG_TYPE_Pos) +#define LINK_REG_PIPECFG_TYPE_ISO (3U << LINK_REG_PIPECFG_TYPE_Pos) + #ifdef __cplusplus } #endif -- cgit v1.3.1 From 60aae59eeb1f656bddf87f026fdba48735e03280 Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Mon, 21 Mar 2022 16:02:11 +0000 Subject: style code for consistency with existing codebase --- hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c | 152 +- .../boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h | 112 +- src/portable/renesas/link/dcd_link.c | 8 +- src/portable/renesas/link/hcd_link.c | 10 +- src/portable/renesas/link/link_ra.h | 8 +- src/portable/renesas/link/link_rx.h | 16 +- src/portable/renesas/link/link_type.h | 1844 ++++++++++---------- 7 files changed, 1077 insertions(+), 1073 deletions(-) (limited to 'src') diff --git a/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c b/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c index c2f2a0903..eab102de9 100644 --- a/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c +++ b/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c @@ -50,35 +50,35 @@ void usbfs_d0fifo_handler(void); void usbfs_d1fifo_handler(void); BSP_DONT_REMOVE const - fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = { - [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */ - [1] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */ - [2] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */ - [3] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */ + fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = { + [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */ + [1] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */ + [2] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */ + [3] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */ }; const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = { - [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */ - [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */ - [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */ - [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1) /* USBFS FIFO 1 (DMA transfer request 1) */ + [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */ + [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */ + [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */ + [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1) /* USBFS FIFO 1 (DMA transfer request 1) */ }; const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { - {.pin = BSP_IO_PORT_04_PIN_07, - .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)}, - {.pin = BSP_IO_PORT_05_PIN_00, - .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)}, - {.pin = BSP_IO_PORT_05_PIN_01, - .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)}, - {.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)}, - {.pin = LED2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)}, - {.pin = LED3, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)}, - {.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}, - {.pin = SW2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}}; + {.pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)}, + {.pin = BSP_IO_PORT_05_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)}, + {.pin = BSP_IO_PORT_05_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)}, + {.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)}, + {.pin = LED2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)}, + {.pin = LED3, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)}, + {.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}, + {.pin = SW2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}}; const ioport_cfg_t g_bsp_pin_cfg = { - .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), - .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], + .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], }; ioport_instance_ctrl_t g_ioport_ctrl; const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg}; @@ -88,78 +88,78 @@ const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_i //--------------------------------------------------------------------+ void usbfs_interrupt_handler(void) { - IRQn_Type irq = R_FSP_CurrentIrqGet(); - R_BSP_IrqStatusClear(irq); + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST - tuh_int_handler(0); + tuh_int_handler(0); #endif #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE - tud_int_handler(0); + tud_int_handler(0); #endif } void usbfs_resume_handler(void) { - IRQn_Type irq = R_FSP_CurrentIrqGet(); - R_BSP_IrqStatusClear(irq); + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST - tuh_int_handler(0); + tuh_int_handler(0); #endif #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE - tud_int_handler(0); + tud_int_handler(0); #endif } void usbfs_d0fifo_handler(void) { - IRQn_Type irq = R_FSP_CurrentIrqGet(); - R_BSP_IrqStatusClear(irq); + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST - tuh_int_handler(0); + tuh_int_handler(0); #endif #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE - tud_int_handler(0); + tud_int_handler(0); #endif } void usbfs_d1fifo_handler(void) { - IRQn_Type irq = R_FSP_CurrentIrqGet(); - R_BSP_IrqStatusClear(irq); + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST - tuh_int_handler(0); + tuh_int_handler(0); #endif #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE - tud_int_handler(0); + tud_int_handler(0); #endif } void board_init(void) { - /* Configure pins. */ - R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg); + /* Configure pins. */ + R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg); - /* Enable USB_BASE */ - R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK; - R_MSTP->MSTPCRB &= ~(1U << 11U); - R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; + /* Enable USB_BASE */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK; + R_MSTP->MSTPCRB &= ~(1U << 11U); + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; #if CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); - NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); - NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); - NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); #endif #if CFG_TUSB_OS == OPT_OS_NONE - /* Init systick */ - SysTick_Config(SystemCoreClock / 1000); + /* Init systick */ + SysTick_Config(SystemCoreClock / 1000); #endif } @@ -169,66 +169,66 @@ void board_init(void) void board_led_write(bool state) { - R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state); - R_IOPORT_PinWrite(&g_ioport_ctrl, LED2, state); - R_IOPORT_PinWrite(&g_ioport_ctrl, LED3, state); + R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state); + R_IOPORT_PinWrite(&g_ioport_ctrl, LED2, state); + R_IOPORT_PinWrite(&g_ioport_ctrl, LED3, state); } uint32_t board_button_read(void) { - bsp_io_level_t lvl; - R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl); - return lvl; + bsp_io_level_t lvl; + R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl); + return lvl; } int board_uart_read(uint8_t *buf, int len) { - (void) buf; - (void) len; - return 0; + (void) buf; + (void) len; + return 0; } int board_uart_write(void const *buf, int len) { - (void) buf; - (void) len; - return 0; + (void) buf; + (void) len; + return 0; } #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; void SysTick_Handler(void) { - system_ticks++; + system_ticks++; } uint32_t board_millis(void) { - return system_ticks; + return system_ticks; } #else #endif int close(int fd) { - (void) fd; - return -1; + (void) fd; + return -1; } int fstat(int fd, void *pstat) { - (void) fd; - (void) pstat; - return 0; + (void) fd; + (void) pstat; + return 0; } off_t lseek(int fd, off_t pos, int whence) { - (void) fd; - (void) pos; - (void) whence; - return 0; + (void) fd; + (void) pos; + (void) whence; + return 0; } int isatty(int fd) { - (void) fd; - return 1; + (void) fd; + return 1; } diff --git a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h index 0449bb4bc..4ecda1c66 100644 --- a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h @@ -69,40 +69,40 @@ /* Peripheral Security Attribution Register (PSAR) Settings */ #define BSP_TZ_CFG_PSARB \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */ + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */ #define BSP_TZ_CFG_PSARC \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */ + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */ #define BSP_TZ_CFG_PSARD \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ - 0xffae07f0) /* Unused */ + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ + 0xffae07f0) /* Unused */ #define BSP_TZ_CFG_PSARE \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ - (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ - (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */ + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ + (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */ #define BSP_TZ_CFG_MSSAR \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ - 0xfffffffc) /* Unused */ + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ + 0xfffffffc) /* Unused */ /* Type 2 Peripheral Security Attribution */ @@ -114,9 +114,9 @@ /* Security attribution for registers of LVD channels. */ #define BSP_TZ_CFG_LVDSAR \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ - 0xFFFFFFFCU) + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ + 0xFFFFFFFCU) /* Security attribution for LPM registers. */ #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) @@ -137,34 +137,34 @@ /* Security attribution for registers for IRQ channels. */ #define BSP_TZ_CFG_ICUSARA \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ - (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U) + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U) /* Security attribution for NMI registers. */ #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ /* Security attribution for registers for DMAC channels */ #define BSP_TZ_CFG_ICUSARC \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U) + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U) /* Security attribution registers for SELSR0. */ #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) @@ -222,7 +222,7 @@ /* Option Function Select Register 1 Security Attribution */ #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) #define BSP_CFG_ROM_REG_OFS1_SEL \ - (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) + (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) #else #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) #endif diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c index f2334140a..bb7e3b60a 100644 --- a/src/portable/renesas/link/dcd_link.c +++ b/src/portable/renesas/link/dcd_link.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Koji Kitayama @@ -31,8 +31,10 @@ // We disable SOF for now until needed later on #define USE_SOF 0 -#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N || \ - CFG_TUSB_MCU == OPT_MCU_RAXXX) +#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \ + CFG_TUSB_MCU == OPT_MCU_RX65X || \ + CFG_TUSB_MCU == OPT_MCU_RX72N || \ + CFG_TUSB_MCU == OPT_MCU_RAXXX) #include "device/dcd.h" #include "link_type.h" diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c index 940013c86..f60c49114 100644 --- a/src/portable/renesas/link/hcd_link.c +++ b/src/portable/renesas/link/hcd_link.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021 Koji Kitayama @@ -27,8 +27,10 @@ #include "tusb_option.h" -#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N || \ - CFG_TUSB_MCU == OPT_MCU_RAXXX) +#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \ + CFG_TUSB_MCU == OPT_MCU_RX65X || \ + CFG_TUSB_MCU == OPT_MCU_RX72N || \ + CFG_TUSB_MCU == OPT_MCU_RAXXX) #include "host/hcd.h" #include "link_type.h" @@ -488,7 +490,7 @@ void hcd_int_disable(uint8_t rhport) uint32_t hcd_frame_number(uint8_t rhport) { (void)rhport; - /* The device must be reset at least once after connection + /* The device must be reset at least once after connection * in order to start the frame counter. */ if (_hcd.need_reset) hcd_port_reset(rhport); return LINK_REG->FRMNUM_b.FRNM; diff --git a/src/portable/renesas/link/link_ra.h b/src/portable/renesas/link/link_ra.h index b42def368..97618ef8f 100644 --- a/src/portable/renesas/link/link_ra.h +++ b/src/portable/renesas/link/link_ra.h @@ -41,15 +41,15 @@ extern "C" { TU_ATTR_ALWAYS_INLINE static inline void link_int_enable(uint8_t rhport) { - (void) rhport; - NVIC_EnableIRQ(TU_IRQn); + (void) rhport; + NVIC_EnableIRQ(TU_IRQn); } TU_ATTR_ALWAYS_INLINE static inline void link_int_disable(uint8_t rhport) { - (void) rhport; - NVIC_DisableIRQ(TU_IRQn); + (void) rhport; + NVIC_DisableIRQ(TU_IRQn); } // MCU specific PHY init diff --git a/src/portable/renesas/link/link_rx.h b/src/portable/renesas/link/link_rx.h index b15084bb3..62f2911c2 100644 --- a/src/portable/renesas/link/link_rx.h +++ b/src/portable/renesas/link/link_rx.h @@ -41,21 +41,21 @@ extern "C" { static inline void link_int_enable(uint8_t rhport) { - (void) rhport; + (void) rhport; #if (CFG_TUSB_MCU == OPT_MCU_RX72N) - IEN(PERIB, INTB185) = 1; + IEN(PERIB, INTB185) = 1; #else - IEN(USB0, USBI0) = 1; + IEN(USB0, USBI0) = 1; #endif } static inline void link_int_disable(uint8_t rhport) { - (void) rhport; + (void) rhport; #if (CFG_TUSB_MCU == OPT_MCU_RX72N) - IEN(PERIB, INTB185) = 0; + IEN(PERIB, INTB185) = 0; #else - IEN(USB0, USBI0) = 0; + IEN(USB0, USBI0) = 0; #endif } @@ -63,9 +63,9 @@ static inline void link_int_disable(uint8_t rhport) static inline void link_phy_init(void) { #if (CFG_TUSB_MCU == OPT_MCU_RX72N) - IR(PERIB, INTB185) = 0; + IR(PERIB, INTB185) = 0; #else - IR(USB0, USBI0) = 0; + IR(USB0, USBI0) = 0; #endif } diff --git a/src/portable/renesas/link/link_type.h b/src/portable/renesas/link/link_type.h index f1d0130cc..eaf0b1ec4 100644 --- a/src/portable/renesas/link/link_type.h +++ b/src/portable/renesas/link/link_type.h @@ -42,933 +42,933 @@ TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN typedef struct TU_ATTR_PACKED { - union { - volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */ - - struct { - uint16_t : 8; - volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */ - volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */ - uint16_t : 6; - } E_b; - }; - - union { - volatile uint16_t N; /* (@ 0x00000002) Pipe Transaction Counter Register */ - - struct { - volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */ - } N_b; - }; + union { + volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct { + uint16_t : 8; + volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */ + volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union { + volatile uint16_t N; /* (@ 0x00000002) Pipe Transaction Counter Register */ + + struct { + volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */ + } N_b; + }; } LINK_REG_PIPE_TR_t; /* Size = 4 (0x4) */ TU_VERIFY_STATIC(sizeof(LINK_REG_PIPE_TR_t) == 4, "incorrect size"); /* LINK_REG Structure */ typedef struct TU_ATTR_PACKED { - union { - volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */ - - struct { - volatile uint16_t USBE : 1; /* [0..0] USB Operation Enable */ - uint16_t : 2; - volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */ - volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */ - volatile uint16_t DRPD : 1; /* [5..5] D+/D- Line Resistor Control */ - volatile uint16_t DCFM : 1; /* [6..6] Controller Function Select */ - uint16_t : 1; - volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */ - uint16_t : 1; - volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */ - uint16_t : 5; - } SYSCFG_b; - }; - - union { - volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */ - - struct { - volatile uint16_t - BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */ - uint16_t : 12; - } BUSWAIT_b; - }; - - union { - volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */ - - struct { - volatile const uint16_t LNST : 2; /* [1..0] USB Data Line Status Monitor */ - volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */ - uint16_t : 2; - volatile const uint16_t - SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */ - volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */ - uint16_t : 7; - volatile const uint16_t - OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */ - } SYSSTS0_b; - }; - - union { - volatile const uint16_t PLLSTA; /* (@ 0x00000006) PLL Status Register */ - - struct { - volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */ - uint16_t : 15; - } PLLSTA_b; - }; - - union { - volatile uint16_t DVSTCTR0; /* (@ 0x00000008) Device State Control Register 0 */ - - struct { - volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */ - uint16_t : 1; - volatile uint16_t UACT : 1; /* [4..4] USB Bus Enable */ - volatile uint16_t RESUME : 1; /* [5..5] Resume Output */ - volatile uint16_t USBRST : 1; /* [6..6] USB Bus Reset Output */ - volatile uint16_t RWUPE : 1; /* [7..7] Wakeup Detection Enable */ - volatile uint16_t WKUP : 1; /* [8..8] Wakeup Output */ - volatile uint16_t VBUSEN : 1; /* [9..9] USB_VBUSEN Output Pin Control */ - volatile uint16_t EXICEN : 1; /* [10..10] USB_EXICEN Output Pin Control */ - volatile uint16_t HNPBTOA : 1; /* [11..11] Host Negotiation Protocol (HNP) */ - uint16_t : 4; - } DVSTCTR0_b; - }; - volatile const uint16_t RESERVED; - - union { - volatile uint16_t TESTMODE; /* (@ 0x0000000C) USB Test Mode Register */ - - struct { - volatile uint16_t UTST : 4; /* [3..0] Test Mode */ - uint16_t : 12; - } TESTMODE_b; - }; - volatile const uint16_t RESERVED1; - volatile const uint32_t RESERVED2; - - union { - volatile uint32_t CFIFO; /* (@ 0x00000014) CFIFO Port Register */ - - struct { - union { - volatile uint16_t CFIFOL; /* (@ 0x00000014) CFIFO Port Register L */ - volatile uint8_t CFIFOLL; /* (@ 0x00000014) CFIFO Port Register LL */ - }; - - union { - volatile uint16_t CFIFOH; /* (@ 0x00000016) CFIFO Port Register H */ - - struct { - volatile const uint8_t RESERVED3; - volatile uint8_t CFIFOHH; /* (@ 0x00000017) CFIFO Port Register HH */ - }; - }; - }; - }; - - union { - volatile uint32_t D0FIFO; /* (@ 0x00000018) D0FIFO Port Register */ - - struct { - union { - volatile uint16_t D0FIFOL; /* (@ 0x00000018) D0FIFO Port Register L */ - volatile uint8_t D0FIFOLL; /* (@ 0x00000018) D0FIFO Port Register LL */ - }; - - union { - volatile uint16_t D0FIFOH; /* (@ 0x0000001A) D0FIFO Port Register H */ - - struct { - volatile const uint8_t RESERVED4; - volatile uint8_t D0FIFOHH; /* (@ 0x0000001B) D0FIFO Port Register HH */ - }; - }; - }; - }; - - union { - volatile uint32_t D1FIFO; /* (@ 0x0000001C) D1FIFO Port Register */ - - struct { - union { - volatile uint16_t D1FIFOL; /* (@ 0x0000001C) D1FIFO Port Register L */ - volatile uint8_t D1FIFOLL; /* (@ 0x0000001C) D1FIFO Port Register LL */ - }; - - union { - volatile uint16_t D1FIFOH; /* (@ 0x0000001E) D1FIFO Port Register H */ - - struct { - volatile const uint8_t RESERVED5; - volatile uint8_t D1FIFOHH; /* (@ 0x0000001F) D1FIFO Port Register HH */ - }; - }; - }; - }; - - union { - volatile uint16_t CFIFOSEL; /* (@ 0x00000020) CFIFO Port Select Register */ - - struct { - volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */ - uint16_t : 1; - volatile uint16_t ISEL : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */ - uint16_t : 2; - volatile uint16_t BIGEND : 1; /* [8..8] CFIFO Port Endian Control */ - uint16_t : 1; - volatile uint16_t MBW : 2; /* [11..10] CFIFO Port Access Bit Width */ - uint16_t : 2; - volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */ - volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ - } CFIFOSEL_b; - }; - - union { - volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */ - - struct { - volatile const uint16_t - DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ - uint16_t : 1; - volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ - volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ - } CFIFOCTR_b; - }; - volatile const uint32_t RESERVED6; - - union { - volatile uint16_t D0FIFOSEL; /* (@ 0x00000028) D0FIFO Port Select Register */ - - struct { - volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ - uint16_t : 1; - volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */ - volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */ - volatile uint16_t - DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */ - volatile uint16_t REW : 1; /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ - volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ - } D0FIFOSEL_b; - }; - - union { - volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */ - - struct { - volatile const uint16_t - DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ - uint16_t : 1; - volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ - volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ - } D0FIFOCTR_b; - }; - - union { - volatile uint16_t D1FIFOSEL; /* (@ 0x0000002C) D1FIFO Port Select Register */ - - struct { - volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ - uint16_t : 1; - volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */ - volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */ - volatile uint16_t - DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */ - volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */ - volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ - } D1FIFOSEL_b; - }; - - union { - volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */ - - struct { - volatile const uint16_t - DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ - uint16_t : 1; - volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ - volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ - } D1FIFOCTR_b; - }; - - union { - volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */ - - struct { - uint16_t : 8; - volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */ - volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */ - volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */ - volatile uint16_t CTRE : 1; /* [11..11] Control Transfer Stage Transition Interrupt Enable */ - volatile uint16_t DVSE : 1; /* [12..12] Device State Transition Interrupt Enable */ - volatile uint16_t SOFE : 1; /* [13..13] Frame Number Update Interrupt Enable */ - volatile uint16_t RSME : 1; /* [14..14] Resume Interrupt Enable */ - volatile uint16_t VBSE : 1; /* [15..15] VBUS Interrupt Enable */ - } INTENB0_b; - }; - - union { - volatile uint16_t INTENB1; /* (@ 0x00000032) Interrupt Enable Register 1 */ - - struct { - volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */ - uint16_t : 3; - volatile uint16_t SACKE : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */ - volatile uint16_t SIGNE : 1; /* [5..5] Setup Transaction Error Interrupt Enable */ - volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 4; - volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */ - volatile uint16_t DTCHE : 1; /* [12..12] Disconnection Detection Interrupt Enable */ - uint16_t : 1; - volatile uint16_t BCHGE : 1; /* [14..14] USB Bus Change Interrupt Enable */ - volatile uint16_t OVRCRE : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */ - } INTENB1_b; - }; - volatile const uint16_t RESERVED7; - - union { - volatile uint16_t BRDYENB; /* (@ 0x00000036) BRDY Interrupt Enable Register */ - - struct { - volatile uint16_t PIPE0BRDYE : 1; /* [0..0] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE1BRDYE : 1; /* [1..1] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE2BRDYE : 1; /* [2..2] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE3BRDYE : 1; /* [3..3] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE4BRDYE : 1; /* [4..4] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE5BRDYE : 1; /* [5..5] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE6BRDYE : 1; /* [6..6] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } BRDYENB_b; - }; - - union { - volatile uint16_t NRDYENB; /* (@ 0x00000038) NRDY Interrupt Enable Register */ - - struct { - volatile uint16_t PIPE0NRDYE : 1; /* [0..0] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE1NRDYE : 1; /* [1..1] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE2NRDYE : 1; /* [2..2] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE3NRDYE : 1; /* [3..3] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE4NRDYE : 1; /* [4..4] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE5NRDYE : 1; /* [5..5] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE6NRDYE : 1; /* [6..6] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } NRDYENB_b; - }; - - union { - volatile uint16_t BEMPENB; /* (@ 0x0000003A) BEMP Interrupt Enable Register */ - - struct { - volatile uint16_t PIPE0BEMPE : 1; /* [0..0] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE1BEMPE : 1; /* [1..1] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE2BEMPE : 1; /* [2..2] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE3BEMPE : 1; /* [3..3] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE4BEMPE : 1; /* [4..4] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE5BEMPE : 1; /* [5..5] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE6BEMPE : 1; /* [6..6] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */ - uint16_t : 6; - } BEMPENB_b; - }; - - union { - volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */ - - struct { - uint16_t : 4; - volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */ - volatile uint16_t INTL : 1; /* [5..5] Interrupt Output Sense Select */ - volatile uint16_t BRDYM : 1; /* [6..6] BRDY Interrupt Status Clear Timing */ - uint16_t : 1; - volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */ - uint16_t : 7; - } SOFCFG_b; - }; - - union { - volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */ - - struct { - volatile uint16_t DIRPD : 1; /* [0..0] Power-Down Control */ - volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */ - uint16_t : 1; - volatile uint16_t CDPEN : 1; /* [3..3] Charging Downstream Port Enable */ - volatile uint16_t CLKSEL : 2; /* [5..4] Input System Clock Frequency */ - uint16_t : 2; - volatile uint16_t REPSEL : 2; /* [9..8] Terminating Resistance Adjustment Cycle */ - uint16_t : 1; - volatile uint16_t REPSTART : 1; /* [11..11] Forcibly Start Terminating Resistance Adjustment */ - uint16_t : 3; - volatile uint16_t HSEB : 1; /* [15..15] CL-Only Mode */ - } PHYSET_b; - }; - - union { - volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */ - - struct { - volatile const uint16_t CTSQ : 3; /* [2..0] Control Transfer Stage */ - volatile uint16_t VALID : 1; /* [3..3] USB Request Reception */ - volatile const uint16_t DVSQ : 3; /* [6..4] Device State */ - volatile const uint16_t VBSTS : 1; /* [7..7] VBUS Input Status */ - volatile const uint16_t BRDY : 1; /* [8..8] Buffer Ready Interrupt Status */ - volatile const uint16_t NRDY : 1; /* [9..9] Buffer Not Ready Interrupt Status */ - volatile const uint16_t BEMP : 1; /* [10..10] Buffer Empty Interrupt Status */ - volatile uint16_t CTRT : 1; /* [11..11] Control Transfer Stage Transition Interrupt Status */ - volatile uint16_t DVST : 1; /* [12..12] Device State Transition Interrupt Status */ - volatile uint16_t SOFR : 1; /* [13..13] Frame Number Refresh Interrupt Status */ - volatile uint16_t RESM : 1; /* [14..14] Resume Interrupt Status */ - volatile uint16_t VBINT : 1; /* [15..15] VBUS Interrupt Status */ - } INTSTS0_b; - }; - - union { - volatile uint16_t INTSTS1; /* (@ 0x00000042) Interrupt Status Register 1 */ - - struct { - volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */ - uint16_t : 3; - volatile uint16_t SACK : 1; /* [4..4] Setup Transaction Normal Response Interrupt Status */ - volatile uint16_t SIGN : 1; /* [5..5] Setup Transaction Error Interrupt Status */ - volatile uint16_t EOFERR : 1; /* [6..6] EOF Error Detection Interrupt Status */ - uint16_t : 1; - volatile uint16_t LPMEND : 1; /* [8..8] LPM Transaction End Interrupt Status */ - volatile uint16_t L1RSMEND : 1; /* [9..9] L1 Resume End Interrupt Status */ - uint16_t : 1; - volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */ - volatile uint16_t DTCH : 1; /* [12..12] USB Disconnection Detection Interrupt Status */ - uint16_t : 1; - volatile uint16_t BCHG : 1; /* [14..14] USB Bus Change Interrupt Status */ - volatile uint16_t OVRCR : 1; /* [15..15] Overcurrent Input Change Interrupt Status */ - } INTSTS1_b; - }; - volatile const uint16_t RESERVED8; - - union { - volatile uint16_t BRDYSTS; /* (@ 0x00000046) BRDY Interrupt Status Register */ - - struct { - volatile uint16_t PIPE0BRDY : 1; /* [0..0] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE1BRDY : 1; /* [1..1] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE2BRDY : 1; /* [2..2] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE3BRDY : 1; /* [3..3] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE4BRDY : 1; /* [4..4] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE5BRDY : 1; /* [5..5] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE6BRDY : 1; /* [6..6] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */ - uint16_t : 6; - } BRDYSTS_b; - }; - - union { - volatile uint16_t NRDYSTS; /* (@ 0x00000048) NRDY Interrupt Status Register */ - - struct { - volatile uint16_t PIPE0NRDY : 1; /* [0..0] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE1NRDY : 1; /* [1..1] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE2NRDY : 1; /* [2..2] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE3NRDY : 1; /* [3..3] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE4NRDY : 1; /* [4..4] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE5NRDY : 1; /* [5..5] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE6NRDY : 1; /* [6..6] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */ - uint16_t : 6; - } NRDYSTS_b; - }; - - union { - volatile uint16_t BEMPSTS; /* (@ 0x0000004A) BEMP Interrupt Status Register */ - - struct { - volatile uint16_t PIPE0BEMP : 1; /* [0..0] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE1BEMP : 1; /* [1..1] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE2BEMP : 1; /* [2..2] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE3BEMP : 1; /* [3..3] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE4BEMP : 1; /* [4..4] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE5BEMP : 1; /* [5..5] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE6BEMP : 1; /* [6..6] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */ - uint16_t : 6; - } BEMPSTS_b; - }; - - union { - volatile uint16_t FRMNUM; /* (@ 0x0000004C) Frame Number Register */ - - struct { - volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */ - uint16_t : 3; - volatile uint16_t CRCE : 1; /* [14..14] Receive Data Error */ - volatile uint16_t OVRN : 1; /* [15..15] Overrun/Underrun Detection Status */ - } FRMNUM_b; - }; - - union { - volatile uint16_t UFRMNUM; /* (@ 0x0000004E) uFrame Number Register */ - - struct { - volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; - volatile uint16_t DVCHG : 1; /* [15..15] Device State Change */ - } UFRMNUM_b; - }; - - union { - volatile uint16_t USBADDR; /* (@ 0x00000050) USB Address Register */ - - struct { - volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */ - uint16_t : 1; - volatile uint16_t STSRECOV0 : 3; /* [10..8] Status Recovery */ - uint16_t : 5; - } USBADDR_b; - }; - volatile const uint16_t RESERVED9; - - union { - volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */ - - struct { - volatile uint16_t - BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */ - volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */ - } USBREQ_b; - }; - - union { - volatile uint16_t USBVAL; /* (@ 0x00000056) USB Request Value Register */ - - struct { - volatile uint16_t WVALUE : 16; /* [15..0] ValueThese bits store the USB request Value value. */ - } USBVAL_b; - }; - - union { - volatile uint16_t USBINDX; /* (@ 0x00000058) USB Request Index Register */ - - struct { - volatile uint16_t WINDEX : 16; /* [15..0] IndexThese bits store the USB request wIndex value. */ - } USBINDX_b; - }; - - union { - volatile uint16_t USBLENG; /* (@ 0x0000005A) USB Request Length Register */ - - struct { - volatile uint16_t WLENGTH : 16; /* [15..0] LengthThese bits store the USB request wLength value. */ - } USBLENG_b; - }; - - union { - volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */ - - struct { - uint16_t : 4; - volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ - uint16_t : 2; - volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */ - volatile uint16_t CNTMD : 1; /* [8..8] Continuous Transfer Mode */ - uint16_t : 7; - } DCPCFG_b; - }; - - union { - volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */ - - struct { - volatile uint16_t MXPS : 7; /* [6..0] Maximum Packet Size */ - uint16_t : 5; - volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ - } DCPMAXP_b; - }; - - union { - volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */ - - struct { - volatile uint16_t PID : 2; /* [1..0] Response PID */ - volatile uint16_t CCPL : 1; /* [2..2] Control Transfer End Enable */ - uint16_t : 2; - volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */ - volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Monitor */ - volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */ - volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ - uint16_t : 2; - volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */ - uint16_t : 2; - volatile uint16_t SUREQ : 1; /* [14..14] Setup Token Transmission */ - volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ - } DCPCTR_b; - }; - volatile const uint16_t RESERVED10; - - union { - volatile uint16_t PIPESEL; /* (@ 0x00000064) Pipe Window Select Register */ - - struct { - volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */ - uint16_t : 12; - } PIPESEL_b; - }; - volatile const uint16_t RESERVED11; - - union { - volatile uint16_t PIPECFG; /* (@ 0x00000068) Pipe Configuration Register */ - - struct { - volatile uint16_t EPNUM : 4; /* [3..0] Endpoint Number */ - volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ - uint16_t : 2; - volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */ - uint16_t : 1; - volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */ - volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */ - uint16_t : 3; - volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */ - } PIPECFG_b; - }; - volatile const uint16_t RESERVED12; - - union { - volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */ - - struct { - volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */ - uint16_t : 3; - volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ - } PIPEMAXP_b; - }; - - union { - volatile uint16_t PIPEPERI; /* (@ 0x0000006E) Pipe Cycle Control Register */ - - struct { - volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */ - uint16_t : 9; - volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */ - uint16_t : 3; - } PIPEPERI_b; - }; - - union { - volatile uint16_t PIPE_CTR[9]; /* (@ 0x00000070) Pipe [0..8] Control Register */ - - struct { - volatile uint16_t PID : 2; /* [1..0] Response PID */ - uint16_t : 3; - volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */ - volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Confirmation */ - volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */ - volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ - volatile uint16_t ACLRM : 1; /* [9..9] Auto Buffer Clear Mode */ - volatile uint16_t ATREPM : 1; /* [10..10] Auto Response Mode */ - uint16_t : 1; - volatile const uint16_t CSSTS : 1; /* [12..12] CSSTS Status */ - volatile uint16_t CSCLR : 1; /* [13..13] CSPLIT Status Clear */ - volatile const uint16_t INBUFM : 1; /* [14..14] Transmit Buffer Monitor */ - volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ - } PIPE_CTR_b[9]; - }; - volatile const uint16_t RESERVED13; - volatile const uint32_t RESERVED14[3]; - volatile LINK_REG_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */ - volatile const uint32_t RESERVED15[3]; - - union { - volatile uint16_t USBBCCTRL0; /* (@ 0x000000B0) BC Control Register 0 */ - - struct { - volatile uint16_t RPDME0 : 1; /* [0..0] D- Pin Pull-Down Control */ - volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */ - volatile uint16_t - IDMSINKE0 : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ - volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ - volatile uint16_t - IDPSINKE0 : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ - volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */ - uint16_t : 1; - volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ - volatile const uint16_t CHGDETSTS0 : 1; /* [8..8] D- Pin 0.6 V Input Detection Status */ - volatile const uint16_t PDDETSTS0 : 1; /* [9..9] D+ Pin 0.6 V Input Detection Status */ - uint16_t : 6; - } USBBCCTRL0_b; - }; - volatile const uint16_t RESERVED16; - volatile const uint32_t RESERVED17[4]; - - union { - volatile uint16_t UCKSEL; /* (@ 0x000000C4) USB Clock Selection Register */ - - struct { - volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */ - uint16_t : 15; - } UCKSEL_b; - }; - volatile const uint16_t RESERVED18; - volatile const uint32_t RESERVED19; - - union { - volatile uint16_t USBMC; /* (@ 0x000000CC) USB Module Control Register */ - - struct { - volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */ - uint16_t : 6; - volatile uint16_t VDCEN : 1; /* [7..7] USB Regulator On/Off Control */ - uint16_t : 8; - } USBMC_b; - }; - volatile const uint16_t RESERVED20; - - union { - volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */ - - struct { - uint16_t : 6; - volatile uint16_t USBSPD : 2; /* [7..6] Transfer Speed of Communication Target Device */ - volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */ - volatile uint16_t UPPHUB : 4; /* [14..11] Communication Target Connecting Hub Register */ - uint16_t : 1; - } DEVADD_b[10]; - }; - volatile const uint32_t RESERVED21[3]; - - union { - volatile uint32_t PHYSLEW; /* (@ 0x000000F0) PHY Cross Point Adjustment Register */ - - struct { - volatile uint32_t SLEWR00 : 1; /* [0..0] Receiver Cross Point Adjustment 00 */ - volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */ - volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */ - volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */ - uint32_t : 28; - } PHYSLEW_b; - }; - volatile const uint32_t RESERVED22[3]; - - union { - volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */ - - struct { - uint16_t : 7; - volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */ - uint16_t : 8; - } LPCTRL_b; - }; - - union { - volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */ - - struct { - uint16_t : 14; - volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */ - uint16_t : 1; - } LPSTS_b; - }; - volatile const uint32_t RESERVED23[15]; - - union { - volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */ - - struct { - volatile uint16_t IDPSRCE : 1; /* [0..0] IDPSRC Control */ - volatile uint16_t IDMSINKE : 1; /* [1..1] IDMSINK Control */ - volatile uint16_t VDPSRCE : 1; /* [2..2] VDPSRC Control */ - volatile uint16_t IDPSINKE : 1; /* [3..3] IDPSINK Control */ - volatile uint16_t VDMSRCE : 1; /* [4..4] VDMSRC Control */ - volatile uint16_t DCPMODE : 1; /* [5..5] DCP Mode Control */ - uint16_t : 2; - volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */ - volatile const uint16_t PDDETSTS : 1; /* [9..9] PDDET Status */ - uint16_t : 6; - } BCCTRL_b; - }; - volatile const uint16_t RESERVED24; - - union { - volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */ - - struct { - volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */ - volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */ - volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */ - volatile const uint16_t - DVSQ : 4; /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */ - volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */ - uint16_t : 2; - volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */ - uint16_t : 1; - } PL1CTRL1_b; - }; - - union { - volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */ - - struct { - uint16_t : 8; - volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */ - volatile uint16_t RWEMON : 1; /* [12..12] RWE Value Monitor */ - uint16_t : 3; - } PL1CTRL2_b; - }; - - union { - volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */ - - struct { - volatile uint16_t L1REQ : 1; /* [0..0] L1 Transition Request */ - volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */ - uint16_t : 13; - } HL1CTRL1_b; - }; - - union { - volatile uint16_t HL1CTRL2; /* (@ 0x0000014A) Host L1 Control Register 2 */ - - struct { - volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */ - uint16_t : 4; - volatile uint16_t HIRD : 4; /* [11..8] LPM Token HIRD */ - volatile uint16_t L1RWE : 1; /* [12..12] LPM Token L1 Remote Wake Enable */ - uint16_t : 2; - volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */ - } HL1CTRL2_b; - }; - volatile const uint32_t RESERVED25[5]; - - union { - volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */ - - struct { - uint32_t : 20; - volatile const uint32_t - DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */ - volatile const uint32_t - DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */ - uint32_t : 1; - volatile const uint32_t - DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */ - uint32_t : 8; - } DPUSR0R_b; - }; - - union { - volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct { - uint32_t : 4; - volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */ - volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */ - uint32_t : 1; - volatile uint32_t DVBSTSHE : 1; /* [7..7] VBUS Interrupt Enable/Clear */ - uint32_t : 12; - volatile const uint32_t DOVCAH : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */ - volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */ - uint32_t : 1; - volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */ - uint32_t : 8; - } DPUSR1R_b; - }; - - union { - volatile uint16_t DPUSR2R; /* (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct { - volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */ - volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */ - uint16_t : 2; - volatile const uint16_t - DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */ - volatile const uint16_t - DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */ - uint16_t : 2; - volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */ - volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */ - uint16_t : 6; - } DPUSR2R_b; - }; - - union { - volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ - - struct { - volatile uint16_t FIXPHY : 1; /* [0..0] USB Transceiver Control Fix */ - volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */ - uint16_t : 14; - } DPUSRCR_b; - }; - volatile const uint32_t RESERVED26[165]; - - union { - volatile uint32_t - DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */ - - struct { - volatile uint32_t SRPC0 : 1; /* [0..0] USB Single End Receiver Control */ - volatile uint32_t RPUE0 : 1; /* [1..1] DP Pull-Up Resistor Control */ - uint32_t : 1; - volatile uint32_t DRPD0 : 1; /* [3..3] D+/D- Pull-Down Resistor Control */ - volatile uint32_t FIXPHY0 : 1; /* [4..4] USB Transceiver Output Fix */ - uint32_t : 11; - volatile const uint32_t DP0 : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ - volatile const uint32_t DM0 : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */ - uint32_t : 2; - volatile const uint32_t - DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */ - volatile const uint32_t - DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */ - uint32_t : 1; - volatile const uint32_t - DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */ - uint32_t : 8; - } DPUSR0R_FS_b; - }; - - union { - volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */ - - struct { - volatile uint32_t DPINTE0 : 1; /* [0..0] USB DP Interrupt Enable/Clear */ - volatile uint32_t DMINTE0 : 1; /* [1..1] USB DM Interrupt Enable/Clear */ - uint32_t : 2; - volatile uint32_t DOVRCRAE0 : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */ - volatile uint32_t DOVRCRBE0 : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */ - uint32_t : 1; - volatile uint32_t DVBSE0 : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */ - uint32_t : 8; - volatile const uint32_t DPINT0 : 1; /* [16..16] USB DP Interrupt Source Recovery */ - volatile const uint32_t DMINT0 : 1; /* [17..17] USB DM Interrupt Source Recovery */ - uint32_t : 2; - volatile const uint32_t DOVRCRA0 : 1; /* [20..20] USB OVRCURA Interrupt Source Recovery */ - volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */ - uint32_t : 1; - volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */ - uint32_t : 8; - } DPUSR1R_FS_b; - }; + union { + volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */ + + struct { + volatile uint16_t USBE : 1; /* [0..0] USB Operation Enable */ + uint16_t : 2; + volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */ + volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */ + volatile uint16_t DRPD : 1; /* [5..5] D+/D- Line Resistor Control */ + volatile uint16_t DCFM : 1; /* [6..6] Controller Function Select */ + uint16_t : 1; + volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union { + volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */ + + struct { + volatile uint16_t + BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union { + volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */ + + struct { + volatile const uint16_t LNST : 2; /* [1..0] USB Data Line Status Monitor */ + volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + volatile const uint16_t + SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */ + volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + volatile const uint16_t + OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */ + } SYSSTS0_b; + }; + + union { + volatile const uint16_t PLLSTA; /* (@ 0x00000006) PLL Status Register */ + + struct { + volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union { + volatile uint16_t DVSTCTR0; /* (@ 0x00000008) Device State Control Register 0 */ + + struct { + volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */ + uint16_t : 1; + volatile uint16_t UACT : 1; /* [4..4] USB Bus Enable */ + volatile uint16_t RESUME : 1; /* [5..5] Resume Output */ + volatile uint16_t USBRST : 1; /* [6..6] USB Bus Reset Output */ + volatile uint16_t RWUPE : 1; /* [7..7] Wakeup Detection Enable */ + volatile uint16_t WKUP : 1; /* [8..8] Wakeup Output */ + volatile uint16_t VBUSEN : 1; /* [9..9] USB_VBUSEN Output Pin Control */ + volatile uint16_t EXICEN : 1; /* [10..10] USB_EXICEN Output Pin Control */ + volatile uint16_t HNPBTOA : 1; /* [11..11] Host Negotiation Protocol (HNP) */ + uint16_t : 4; + } DVSTCTR0_b; + }; + volatile const uint16_t RESERVED; + + union { + volatile uint16_t TESTMODE; /* (@ 0x0000000C) USB Test Mode Register */ + + struct { + volatile uint16_t UTST : 4; /* [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + volatile const uint16_t RESERVED1; + volatile const uint32_t RESERVED2; + + union { + volatile uint32_t CFIFO; /* (@ 0x00000014) CFIFO Port Register */ + + struct { + union { + volatile uint16_t CFIFOL; /* (@ 0x00000014) CFIFO Port Register L */ + volatile uint8_t CFIFOLL; /* (@ 0x00000014) CFIFO Port Register LL */ + }; + + union { + volatile uint16_t CFIFOH; /* (@ 0x00000016) CFIFO Port Register H */ + + struct { + volatile const uint8_t RESERVED3; + volatile uint8_t CFIFOHH; /* (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union { + volatile uint32_t D0FIFO; /* (@ 0x00000018) D0FIFO Port Register */ + + struct { + union { + volatile uint16_t D0FIFOL; /* (@ 0x00000018) D0FIFO Port Register L */ + volatile uint8_t D0FIFOLL; /* (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union { + volatile uint16_t D0FIFOH; /* (@ 0x0000001A) D0FIFO Port Register H */ + + struct { + volatile const uint8_t RESERVED4; + volatile uint8_t D0FIFOHH; /* (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union { + volatile uint32_t D1FIFO; /* (@ 0x0000001C) D1FIFO Port Register */ + + struct { + union { + volatile uint16_t D1FIFOL; /* (@ 0x0000001C) D1FIFO Port Register L */ + volatile uint8_t D1FIFOLL; /* (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union { + volatile uint16_t D1FIFOH; /* (@ 0x0000001E) D1FIFO Port Register H */ + + struct { + volatile const uint8_t RESERVED5; + volatile uint8_t D1FIFOHH; /* (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union { + volatile uint16_t CFIFOSEL; /* (@ 0x00000020) CFIFO Port Select Register */ + + struct { + volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + volatile uint16_t ISEL : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + volatile uint16_t BIGEND : 1; /* [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + volatile uint16_t MBW : 2; /* [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */ + volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union { + volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */ + + struct { + volatile const uint16_t + DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ + uint16_t : 1; + volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ + volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + volatile const uint32_t RESERVED6; + + union { + volatile uint16_t D0FIFOSEL; /* (@ 0x00000028) D0FIFO Port Select Register */ + + struct { + volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ + uint16_t : 1; + volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */ + volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */ + volatile uint16_t + DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */ + volatile uint16_t REW : 1; /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union { + volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */ + + struct { + volatile const uint16_t + DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ + uint16_t : 1; + volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ + volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union { + volatile uint16_t D1FIFOSEL; /* (@ 0x0000002C) D1FIFO Port Select Register */ + + struct { + volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ + uint16_t : 1; + volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */ + volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */ + volatile uint16_t + DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */ + volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */ + volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union { + volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */ + + struct { + volatile const uint16_t + DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ + uint16_t : 1; + volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ + volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union { + volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */ + + struct { + uint16_t : 8; + volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */ + volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */ + volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */ + volatile uint16_t CTRE : 1; /* [11..11] Control Transfer Stage Transition Interrupt Enable */ + volatile uint16_t DVSE : 1; /* [12..12] Device State Transition Interrupt Enable */ + volatile uint16_t SOFE : 1; /* [13..13] Frame Number Update Interrupt Enable */ + volatile uint16_t RSME : 1; /* [14..14] Resume Interrupt Enable */ + volatile uint16_t VBSE : 1; /* [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union { + volatile uint16_t INTENB1; /* (@ 0x00000032) Interrupt Enable Register 1 */ + + struct { + volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + volatile uint16_t SACKE : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */ + volatile uint16_t SIGNE : 1; /* [5..5] Setup Transaction Error Interrupt Enable */ + volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */ + volatile uint16_t DTCHE : 1; /* [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + volatile uint16_t BCHGE : 1; /* [14..14] USB Bus Change Interrupt Enable */ + volatile uint16_t OVRCRE : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + volatile const uint16_t RESERVED7; + + union { + volatile uint16_t BRDYENB; /* (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct { + volatile uint16_t PIPE0BRDYE : 1; /* [0..0] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE1BRDYE : 1; /* [1..1] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE2BRDYE : 1; /* [2..2] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE3BRDYE : 1; /* [3..3] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE4BRDYE : 1; /* [4..4] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE5BRDYE : 1; /* [5..5] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE6BRDYE : 1; /* [6..6] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union { + volatile uint16_t NRDYENB; /* (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct { + volatile uint16_t PIPE0NRDYE : 1; /* [0..0] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE1NRDYE : 1; /* [1..1] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE2NRDYE : 1; /* [2..2] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE3NRDYE : 1; /* [3..3] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE4NRDYE : 1; /* [4..4] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE5NRDYE : 1; /* [5..5] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE6NRDYE : 1; /* [6..6] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union { + volatile uint16_t BEMPENB; /* (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct { + volatile uint16_t PIPE0BEMPE : 1; /* [0..0] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE1BEMPE : 1; /* [1..1] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE2BEMPE : 1; /* [2..2] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE3BEMPE : 1; /* [3..3] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE4BEMPE : 1; /* [4..4] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE5BEMPE : 1; /* [5..5] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE6BEMPE : 1; /* [6..6] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union { + volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */ + + struct { + uint16_t : 4; + volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */ + volatile uint16_t INTL : 1; /* [5..5] Interrupt Output Sense Select */ + volatile uint16_t BRDYM : 1; /* [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union { + volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */ + + struct { + volatile uint16_t DIRPD : 1; /* [0..0] Power-Down Control */ + volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */ + uint16_t : 1; + volatile uint16_t CDPEN : 1; /* [3..3] Charging Downstream Port Enable */ + volatile uint16_t CLKSEL : 2; /* [5..4] Input System Clock Frequency */ + uint16_t : 2; + volatile uint16_t REPSEL : 2; /* [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + volatile uint16_t REPSTART : 1; /* [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + volatile uint16_t HSEB : 1; /* [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union { + volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */ + + struct { + volatile const uint16_t CTSQ : 3; /* [2..0] Control Transfer Stage */ + volatile uint16_t VALID : 1; /* [3..3] USB Request Reception */ + volatile const uint16_t DVSQ : 3; /* [6..4] Device State */ + volatile const uint16_t VBSTS : 1; /* [7..7] VBUS Input Status */ + volatile const uint16_t BRDY : 1; /* [8..8] Buffer Ready Interrupt Status */ + volatile const uint16_t NRDY : 1; /* [9..9] Buffer Not Ready Interrupt Status */ + volatile const uint16_t BEMP : 1; /* [10..10] Buffer Empty Interrupt Status */ + volatile uint16_t CTRT : 1; /* [11..11] Control Transfer Stage Transition Interrupt Status */ + volatile uint16_t DVST : 1; /* [12..12] Device State Transition Interrupt Status */ + volatile uint16_t SOFR : 1; /* [13..13] Frame Number Refresh Interrupt Status */ + volatile uint16_t RESM : 1; /* [14..14] Resume Interrupt Status */ + volatile uint16_t VBINT : 1; /* [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union { + volatile uint16_t INTSTS1; /* (@ 0x00000042) Interrupt Status Register 1 */ + + struct { + volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + volatile uint16_t SACK : 1; /* [4..4] Setup Transaction Normal Response Interrupt Status */ + volatile uint16_t SIGN : 1; /* [5..5] Setup Transaction Error Interrupt Status */ + volatile uint16_t EOFERR : 1; /* [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + volatile uint16_t LPMEND : 1; /* [8..8] LPM Transaction End Interrupt Status */ + volatile uint16_t L1RSMEND : 1; /* [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */ + volatile uint16_t DTCH : 1; /* [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + volatile uint16_t BCHG : 1; /* [14..14] USB Bus Change Interrupt Status */ + volatile uint16_t OVRCR : 1; /* [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + volatile const uint16_t RESERVED8; + + union { + volatile uint16_t BRDYSTS; /* (@ 0x00000046) BRDY Interrupt Status Register */ + + struct { + volatile uint16_t PIPE0BRDY : 1; /* [0..0] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE1BRDY : 1; /* [1..1] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE2BRDY : 1; /* [2..2] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE3BRDY : 1; /* [3..3] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE4BRDY : 1; /* [4..4] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE5BRDY : 1; /* [5..5] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE6BRDY : 1; /* [6..6] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union { + volatile uint16_t NRDYSTS; /* (@ 0x00000048) NRDY Interrupt Status Register */ + + struct { + volatile uint16_t PIPE0NRDY : 1; /* [0..0] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE1NRDY : 1; /* [1..1] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE2NRDY : 1; /* [2..2] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE3NRDY : 1; /* [3..3] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE4NRDY : 1; /* [4..4] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE5NRDY : 1; /* [5..5] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE6NRDY : 1; /* [6..6] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union { + volatile uint16_t BEMPSTS; /* (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct { + volatile uint16_t PIPE0BEMP : 1; /* [0..0] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE1BEMP : 1; /* [1..1] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE2BEMP : 1; /* [2..2] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE3BEMP : 1; /* [3..3] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE4BEMP : 1; /* [4..4] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE5BEMP : 1; /* [5..5] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE6BEMP : 1; /* [6..6] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union { + volatile uint16_t FRMNUM; /* (@ 0x0000004C) Frame Number Register */ + + struct { + volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + volatile uint16_t CRCE : 1; /* [14..14] Receive Data Error */ + volatile uint16_t OVRN : 1; /* [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union { + volatile uint16_t UFRMNUM; /* (@ 0x0000004E) uFrame Number Register */ + + struct { + volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + volatile uint16_t DVCHG : 1; /* [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union { + volatile uint16_t USBADDR; /* (@ 0x00000050) USB Address Register */ + + struct { + volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */ + uint16_t : 1; + volatile uint16_t STSRECOV0 : 3; /* [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + volatile const uint16_t RESERVED9; + + union { + volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */ + + struct { + volatile uint16_t + BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */ + volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union { + volatile uint16_t USBVAL; /* (@ 0x00000056) USB Request Value Register */ + + struct { + volatile uint16_t WVALUE : 16; /* [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union { + volatile uint16_t USBINDX; /* (@ 0x00000058) USB Request Index Register */ + + struct { + volatile uint16_t WINDEX : 16; /* [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union { + volatile uint16_t USBLENG; /* (@ 0x0000005A) USB Request Length Register */ + + struct { + volatile uint16_t WLENGTH : 16; /* [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union { + volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */ + + struct { + uint16_t : 4; + volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ + uint16_t : 2; + volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */ + volatile uint16_t CNTMD : 1; /* [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union { + volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct { + volatile uint16_t MXPS : 7; /* [6..0] Maximum Packet Size */ + uint16_t : 5; + volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ + } DCPMAXP_b; + }; + + union { + volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */ + + struct { + volatile uint16_t PID : 2; /* [1..0] Response PID */ + volatile uint16_t CCPL : 1; /* [2..2] Control Transfer End Enable */ + uint16_t : 2; + volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */ + volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Monitor */ + volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */ + volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */ + uint16_t : 2; + volatile uint16_t SUREQ : 1; /* [14..14] Setup Token Transmission */ + volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ + } DCPCTR_b; + }; + volatile const uint16_t RESERVED10; + + union { + volatile uint16_t PIPESEL; /* (@ 0x00000064) Pipe Window Select Register */ + + struct { + volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + volatile const uint16_t RESERVED11; + + union { + volatile uint16_t PIPECFG; /* (@ 0x00000068) Pipe Configuration Register */ + + struct { + volatile uint16_t EPNUM : 4; /* [3..0] Endpoint Number */ + volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ + uint16_t : 2; + volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */ + volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */ + } PIPECFG_b; + }; + volatile const uint16_t RESERVED12; + + union { + volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct { + volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */ + uint16_t : 3; + volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union { + volatile uint16_t PIPEPERI; /* (@ 0x0000006E) Pipe Cycle Control Register */ + + struct { + volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */ + uint16_t : 9; + volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union { + volatile uint16_t PIPE_CTR[9]; /* (@ 0x00000070) Pipe [0..8] Control Register */ + + struct { + volatile uint16_t PID : 2; /* [1..0] Response PID */ + uint16_t : 3; + volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */ + volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Confirmation */ + volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */ + volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ + volatile uint16_t ACLRM : 1; /* [9..9] Auto Buffer Clear Mode */ + volatile uint16_t ATREPM : 1; /* [10..10] Auto Response Mode */ + uint16_t : 1; + volatile const uint16_t CSSTS : 1; /* [12..12] CSSTS Status */ + volatile uint16_t CSCLR : 1; /* [13..13] CSPLIT Status Clear */ + volatile const uint16_t INBUFM : 1; /* [14..14] Transmit Buffer Monitor */ + volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + volatile const uint16_t RESERVED13; + volatile const uint32_t RESERVED14[3]; + volatile LINK_REG_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */ + volatile const uint32_t RESERVED15[3]; + + union { + volatile uint16_t USBBCCTRL0; /* (@ 0x000000B0) BC Control Register 0 */ + + struct { + volatile uint16_t RPDME0 : 1; /* [0..0] D- Pin Pull-Down Control */ + volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */ + volatile uint16_t + IDMSINKE0 : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + volatile uint16_t + IDPSINKE0 : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + volatile const uint16_t CHGDETSTS0 : 1; /* [8..8] D- Pin 0.6 V Input Detection Status */ + volatile const uint16_t PDDETSTS0 : 1; /* [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + volatile const uint16_t RESERVED16; + volatile const uint32_t RESERVED17[4]; + + union { + volatile uint16_t UCKSEL; /* (@ 0x000000C4) USB Clock Selection Register */ + + struct { + volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + volatile const uint16_t RESERVED18; + volatile const uint32_t RESERVED19; + + union { + volatile uint16_t USBMC; /* (@ 0x000000CC) USB Module Control Register */ + + struct { + volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + volatile uint16_t VDCEN : 1; /* [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + volatile const uint16_t RESERVED20; + + union { + volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */ + + struct { + uint16_t : 6; + volatile uint16_t USBSPD : 2; /* [7..6] Transfer Speed of Communication Target Device */ + volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */ + volatile uint16_t UPPHUB : 4; /* [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + volatile const uint32_t RESERVED21[3]; + + union { + volatile uint32_t PHYSLEW; /* (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct { + volatile uint32_t SLEWR00 : 1; /* [0..0] Receiver Cross Point Adjustment 00 */ + volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */ + volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */ + volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + volatile const uint32_t RESERVED22[3]; + + union { + volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */ + + struct { + uint16_t : 7; + volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union { + volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */ + + struct { + uint16_t : 14; + volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + volatile const uint32_t RESERVED23[15]; + + union { + volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */ + + struct { + volatile uint16_t IDPSRCE : 1; /* [0..0] IDPSRC Control */ + volatile uint16_t IDMSINKE : 1; /* [1..1] IDMSINK Control */ + volatile uint16_t VDPSRCE : 1; /* [2..2] VDPSRC Control */ + volatile uint16_t IDPSINKE : 1; /* [3..3] IDPSINK Control */ + volatile uint16_t VDMSRCE : 1; /* [4..4] VDMSRC Control */ + volatile uint16_t DCPMODE : 1; /* [5..5] DCP Mode Control */ + uint16_t : 2; + volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */ + volatile const uint16_t PDDETSTS : 1; /* [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + volatile const uint16_t RESERVED24; + + union { + volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */ + + struct { + volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */ + volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */ + volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */ + volatile const uint16_t + DVSQ : 4; /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */ + volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */ + uint16_t : 2; + volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union { + volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */ + + struct { + uint16_t : 8; + volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */ + volatile uint16_t RWEMON : 1; /* [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union { + volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */ + + struct { + volatile uint16_t L1REQ : 1; /* [0..0] L1 Transition Request */ + volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union { + volatile uint16_t HL1CTRL2; /* (@ 0x0000014A) Host L1 Control Register 2 */ + + struct { + volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */ + uint16_t : 4; + volatile uint16_t HIRD : 4; /* [11..8] LPM Token HIRD */ + volatile uint16_t L1RWE : 1; /* [12..12] LPM Token L1 Remote Wake Enable */ + uint16_t : 2; + volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */ + } HL1CTRL2_b; + }; + volatile const uint32_t RESERVED25[5]; + + union { + volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */ + + struct { + uint32_t : 20; + volatile const uint32_t + DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */ + volatile const uint32_t + DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */ + uint32_t : 1; + volatile const uint32_t + DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union { + volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct { + uint32_t : 4; + volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */ + volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + volatile uint32_t DVBSTSHE : 1; /* [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + volatile const uint32_t DOVCAH : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */ + volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union { + volatile uint16_t DPUSR2R; /* (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct { + volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */ + volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + volatile const uint16_t + DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */ + volatile const uint16_t + DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */ + uint16_t : 2; + volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */ + volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union { + volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct { + volatile uint16_t FIXPHY : 1; /* [0..0] USB Transceiver Control Fix */ + volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + volatile const uint32_t RESERVED26[165]; + + union { + volatile uint32_t + DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */ + + struct { + volatile uint32_t SRPC0 : 1; /* [0..0] USB Single End Receiver Control */ + volatile uint32_t RPUE0 : 1; /* [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + volatile uint32_t DRPD0 : 1; /* [3..3] D+/D- Pull-Down Resistor Control */ + volatile uint32_t FIXPHY0 : 1; /* [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + volatile const uint32_t DP0 : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + volatile const uint32_t DM0 : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + volatile const uint32_t + DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */ + volatile const uint32_t + DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */ + uint32_t : 1; + volatile const uint32_t + DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union { + volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */ + + struct { + volatile uint32_t DPINTE0 : 1; /* [0..0] USB DP Interrupt Enable/Clear */ + volatile uint32_t DMINTE0 : 1; /* [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + volatile uint32_t DOVRCRAE0 : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */ + volatile uint32_t DOVRCRBE0 : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + volatile uint32_t DVBSE0 : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + volatile const uint32_t DPINT0 : 1; /* [16..16] USB DP Interrupt Source Recovery */ + volatile const uint32_t DMINT0 : 1; /* [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + volatile const uint32_t DOVRCRA0 : 1; /* [20..20] USB OVRCURA Interrupt Source Recovery */ + volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; } LINK_REG_t; /* Size = 1032 (0x408) */ TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSCFG) == 0x00000000, "incorrect offset"); @@ -1034,7 +1034,7 @@ TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R_FS) == 0x00000400, "incorrect offs TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R_FS) == 0x00000404, "incorrect offset"); TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */ - TU_ATTR_BIT_FIELD_ORDER_END +TU_ATTR_BIT_FIELD_ORDER_END /*--------------------------------------------------------------------*/ /* Register Bit Definitions */ -- cgit v1.3.1 From 79fd23974c04b18a7ebb2dfe14a170cb7c3e6f41 Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Wed, 30 Mar 2022 13:56:00 +0100 Subject: fix host preprocessor flag typo Co-authored-by: Koji KITAYAMA <45088311+kkitayam@users.noreply.github.com> --- src/portable/renesas/link/hcd_link.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c index f60c49114..4bb103936 100644 --- a/src/portable/renesas/link/hcd_link.c +++ b/src/portable/renesas/link/hcd_link.c @@ -27,7 +27,7 @@ #include "tusb_option.h" -#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \ +#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \ CFG_TUSB_MCU == OPT_MCU_RX65X || \ CFG_TUSB_MCU == OPT_MCU_RX72N || \ CFG_TUSB_MCU == OPT_MCU_RAXXX) -- cgit v1.3.1 From fbc29794287b1f22388a09e289ff7b7698ef3eab Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Wed, 30 Mar 2022 15:38:31 +0100 Subject: fix iso int register typo druing the renaming int and iso endpoint configurations were swapped Co-authored-by: Koji KITAYAMA <45088311+kkitayam@users.noreply.github.com> --- src/portable/renesas/link/dcd_link.c | 4 ++-- src/portable/renesas/link/hcd_link.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c index bb7e3b60a..0f9037593 100644 --- a/src/portable/renesas/link/dcd_link.c +++ b/src/portable/renesas/link/dcd_link.c @@ -642,9 +642,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) if (xfer == TUSB_XFER_BULK) { cfg |= (LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk); } else if (xfer == TUSB_XFER_INTERRUPT) { - cfg |= LINK_REG_PIPECFG_TYPE_ISO; + cfg |= LINK_REG_PIPECFG_TYPE_INT; } else { - cfg |= (LINK_REG_PIPECFG_TYPE_INT | LINK_REG_PIPECFG_DBLB_Msk); + cfg |= (LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk); } LINK_REG->PIPECFG = cfg; LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num); diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c index 4bb103936..1197e1de5 100644 --- a/src/portable/renesas/link/hcd_link.c +++ b/src/portable/renesas/link/hcd_link.c @@ -642,9 +642,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const if (xfer == TUSB_XFER_BULK) { cfg |= LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk; } else if (xfer == TUSB_XFER_INTERRUPT) { - cfg |= LINK_REG_PIPECFG_TYPE_ISO; + cfg |= LINK_REG_PIPECFG_TYPE_INT; } else { - cfg |= LINK_REG_PIPECFG_TYPE_INT | LINK_REG_PIPECFG_DBLB_Msk; + cfg |= LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk; } LINK_REG->PIPECFG = cfg; LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num); -- cgit v1.3.1 From ea81d22f184fa8fd6c46c35c8be86e47996b46c8 Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Thu, 7 Apr 2022 11:13:34 +0100 Subject: add __evenaccess keyword for CCRX compiler compatibility Signed-off-by: Rafael Silva --- src/portable/renesas/link/dcd_link.c | 4 ++++ src/portable/renesas/link/hcd_link.c | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'src') diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c index 0f9037593..dcbd68b8d 100644 --- a/src/portable/renesas/link/dcd_link.c +++ b/src/portable/renesas/link/dcd_link.c @@ -52,7 +52,11 @@ //--------------------------------------------------------------------+ /* LINK core registers */ +#if defined(__CCRX__) +#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE) +#else #define LINK_REG ((LINK_REG_t*)LINK_REG_BASE) +#endif /* Start of definition of packed structs (used by the CCRX toolchain) */ TU_ATTR_PACKED_BEGIN diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c index 1197e1de5..f1ea2b821 100644 --- a/src/portable/renesas/link/hcd_link.c +++ b/src/portable/renesas/link/hcd_link.c @@ -48,7 +48,11 @@ //--------------------------------------------------------------------+ /* LINK core registers */ +#if defined(__CCRX__) +#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE) +#else #define LINK_REG ((LINK_REG_t*)LINK_REG_BASE) +#endif TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN -- cgit v1.3.1 From e5355d0335082541ae47b128add049a9d91ec070 Mon Sep 17 00:00:00 2001 From: Ben Avison Date: Fri, 15 Jul 2022 17:32:20 +0100 Subject: [rp2040] Remove non-portable return statements IAR generates error Pe118 'a void function may not return a value'. --- src/portable/raspberrypi/rp2040/rp2040_usb.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h index c72dae64c..87fa999ca 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.h +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h @@ -87,15 +87,15 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t _hw_endpoint_buffer_control_get_val } TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_value32(struct hw_endpoint *ep, uint32_t value) { - return _hw_endpoint_buffer_control_update32(ep, 0, value); + _hw_endpoint_buffer_control_update32(ep, 0, value); } TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_mask32(struct hw_endpoint *ep, uint32_t value) { - return _hw_endpoint_buffer_control_update32(ep, ~value, value); + _hw_endpoint_buffer_control_update32(ep, ~value, value); } TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_clear_mask32(struct hw_endpoint *ep, uint32_t value) { - return _hw_endpoint_buffer_control_update32(ep, ~value, 0); + _hw_endpoint_buffer_control_update32(ep, ~value, 0); } static inline uintptr_t hw_data_offset(uint8_t *buf) -- cgit v1.3.1 From 6dfc857b916855e57a15813f423987449dd1a935 Mon Sep 17 00:00:00 2001 From: Ben Avison Date: Wed, 24 Aug 2022 19:53:12 +0100 Subject: [rp2040] Explicit cast value of `hw_set_alias` Some compilers don't support the GNU extension `typeof` so their definitions of `hw_set_alias` can't inherit their type from their argument, and the best we can do is have `hw_set_alias` act the same as `hw_set_alias_untyped`. This requires an explicit cast when the macro is used instead, otherwise IAR generates error Pe132 'expression must have pointer-to-struct-or-union type but it has type "void *"'. The same goes for `hw_clear_alias`. --- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 4 ++-- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 2003f72fd..89fd6b82d 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -46,8 +46,8 @@ /* Low level controller *------------------------------------------------------------------*/ -#define usb_hw_set hw_set_alias(usb_hw) -#define usb_hw_clear hw_clear_alias(usb_hw) +#define usb_hw_set ((usb_hw_t *)hw_set_alias(usb_hw)) +#define usb_hw_clear ((usb_hw_t *)hw_clear_alias(usb_hw)) // Init these in dcd_init static uint8_t *next_buffer_ptr; diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index e9118c6a3..5badb261a 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -56,8 +56,8 @@ static_assert(PICO_USB_HOST_INTERRUPT_ENDPOINTS <= USB_MAX_ENDPOINTS, ""); static struct hw_endpoint ep_pool[1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS]; #define epx (ep_pool[0]) -#define usb_hw_set hw_set_alias(usb_hw) -#define usb_hw_clear hw_clear_alias(usb_hw) +#define usb_hw_set ((usb_hw_t *)hw_set_alias(usb_hw)) +#define usb_hw_clear ((usb_hw_t *)hw_clear_alias(usb_hw)) // Flags we set by default in sie_ctrl (we add other bits on top) enum { -- cgit v1.3.1 From 16518dcbbb6f20182a6f69556908afe35a7f6e25 Mon Sep 17 00:00:00 2001 From: Ben Avison Date: Mon, 5 Sep 2022 12:50:05 +0100 Subject: Refactor pointer arithmetic on void* This is a GCC extension, illegal in ISO C. IAR generates errors Pa152 'these operand types cannot be used here' and Pe852 'expression must be a pointer to a complete object type'. Replace with uint8_t*. --- src/class/video/video_device.c | 89 +++++++++++++++++++++--------------------- 1 file changed, 44 insertions(+), 45 deletions(-) (limited to 'src') diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 7636db5fe..1f653f5c5 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -80,7 +80,7 @@ typedef struct TU_ATTR_PACKED { /* video control interface */ typedef struct TU_ATTR_PACKED { - void const *beg; /* The head of the first video control interface descriptor */ + uint8_t const *beg; /* The head of the first video control interface descriptor */ uint16_t len; /* Byte length of the descriptors */ uint16_t cur; /* offset for current video control interface */ uint8_t stm[CFG_TUD_VIDEO_STREAMING]; /* Indices of streaming interface */ @@ -108,9 +108,9 @@ static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */ * @param[in] desc interface descriptor * * @return bInterfaceNumber */ -static inline uint8_t _desc_itfnum(void const *desc) +static inline uint8_t _desc_itfnum(uint8_t const *desc) { - return ((uint8_t const*)desc)[2]; + return desc[2]; } /** Get endpoint address from the endpoint descriptor @@ -118,9 +118,9 @@ static inline uint8_t _desc_itfnum(void const *desc) * @param[in] desc endpoint descriptor * * @return bEndpointAddress */ -static inline uint8_t _desc_ep_addr(void const *desc) +static inline uint8_t _desc_ep_addr(uint8_t const *desc) { - return ((uint8_t const*)desc)[2]; + return desc[2]; } /** Get instance of streaming interface @@ -146,7 +146,7 @@ static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self) static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const *self) { if (!self->desc.cur) return NULL; - void const *desc = _videod_itf[self->index_vc].beg; + uint8_t const *desc = _videod_itf[self->index_vc].beg; return (tusb_desc_vs_itf_t const*)(desc + self->desc.cur); } @@ -158,9 +158,9 @@ static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static void const* _find_desc(void const *beg, void const *end, uint_fast8_t desc_type) +static uint8_t const* _find_desc(uint8_t const *beg, uint8_t const *end, uint_fast8_t desc_type) { - void const *cur = beg; + uint8_t const *cur = beg; while ((cur < end) && (desc_type != tu_desc_type(cur))) { cur = tu_desc_next(cur); } @@ -177,14 +177,13 @@ static void const* _find_desc(void const *beg, void const *end, uint_fast8_t des * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static void const* _find_desc_3(void const *beg, void const *end, - uint_fast8_t desc_type, - uint_fast8_t element_0, - uint_fast8_t element_1) +static uint8_t const* _find_desc_3(uint8_t const *beg, uint8_t const *end, + uint_fast8_t desc_type, + uint_fast8_t element_0, + uint_fast8_t element_1) { - for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, desc_type)) { - uint8_t const *p = (uint8_t const *)cur; - if ((p[2] == element_0) && (p[3] == element_1)) { + for (uint8_t const *cur = beg; cur < end; cur = _find_desc(cur, end, desc_type)) { + if ((cur[2] == element_0) && (cur[3] == element_1)) { return cur; } cur = tu_desc_next(cur); @@ -199,9 +198,9 @@ static void const* _find_desc_3(void const *beg, void const *end, * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static void const* _next_desc_itf(void const *beg, void const *end) +static uint8_t const* _next_desc_itf(void const *beg, uint8_t const *end) { - void const *cur = beg; + uint8_t const *cur = beg; uint_fast8_t itfnum = ((tusb_desc_interface_t const*)cur)->bInterfaceNumber; while ((cur < end) && (itfnum == ((tusb_desc_interface_t const*)cur)->bInterfaceNumber)) { @@ -219,7 +218,7 @@ static void const* _next_desc_itf(void const *beg, void const *end) * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static inline void const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t itfnum, uint_fast8_t altnum) +static inline uint8_t const* _find_desc_itf(uint8_t const *beg, uint8_t const *end, uint_fast8_t itfnum, uint_fast8_t altnum) { return _find_desc_3(beg, end, TUSB_DESC_INTERFACE, itfnum, altnum); } @@ -233,9 +232,9 @@ static inline void const* _find_desc_itf(void const *beg, void const *end, uint_ * * @return The pointer for endpoint descriptor. * @retval end did not found endpoint descriptor */ -static void const* _find_desc_ep(void const *beg, void const *end) +static uint8_t const* _find_desc_ep(uint8_t const *beg, uint8_t const *end) { - for (void const *cur = beg; cur < end; cur = tu_desc_next(cur)) { + for (uint8_t const *cur = beg; cur < end; cur = tu_desc_next(cur)) { uint_fast8_t desc_type = tu_desc_type(cur); if (TUSB_DESC_ENDPOINT == desc_type) return cur; if (TUSB_DESC_INTERFACE == desc_type) break; @@ -251,17 +250,17 @@ static void const* _find_desc_ep(void const *beg, void const *end) * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static void const* _find_desc_entity(void const *desc, uint_fast8_t entityid) +static uint8_t const* _find_desc_entity(void const *desc, uint_fast8_t entityid) { tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const*)desc; - void const *beg = vc; - void const *end = beg + vc->std.bLength + vc->ctl.wTotalLength; - for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) { + uint8_t const *beg = desc; + uint8_t const *end = beg + vc->std.bLength + vc->ctl.wTotalLength; + for (uint8_t const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) { tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur; if ((VIDEO_CS_ITF_VC_INPUT_TERMINAL <= itf->bDescriptorSubtype && itf->bDescriptorSubtype < VIDEO_CS_ITF_VC_MAX) && itf->bEntityId == entityid) { - return itf; + return cur; } cur = tu_desc_next(cur); } @@ -272,18 +271,18 @@ static void const* _find_desc_entity(void const *desc, uint_fast8_t entityid) static inline void const* _end_of_streaming_descriptor(void const *desc) { tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const *)desc; - return desc + vs->std.bLength + vs->stm.wTotalLength; + return (uint8_t const *)desc + vs->std.bLength + vs->stm.wTotalLength; } /** Find the first format descriptor with the specified format number. */ -static inline tusb_desc_cs_video_fmt_uncompressed_t const *_find_desc_format(void const *beg, void const *end, uint_fast8_t fmtnum) +static inline tusb_desc_cs_video_fmt_uncompressed_t const *_find_desc_format(uint8_t const *beg, uint8_t const *end, uint_fast8_t fmtnum) { return (tusb_desc_cs_video_fmt_uncompressed_t const*) _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED, fmtnum); } /** Find the first frame descriptor with the specified format number. */ -static inline tusb_desc_cs_video_frm_uncompressed_t const *_find_desc_frame(void const *beg, void const *end, uint_fast8_t frmnum) +static inline tusb_desc_cs_video_frm_uncompressed_t const *_find_desc_frame(uint8_t const *beg, uint8_t const *end, uint_fast8_t frmnum) { return (tusb_desc_cs_video_frm_uncompressed_t const*) _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED, frmnum); @@ -485,9 +484,9 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) { tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); /* The next descriptor after the class-specific VC interface header descriptor. */ - void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength; + uint8_t const *cur = (uint8_t const*)vc + vc->std.bLength + vc->ctl.bLength; /* The end of the video control interface descriptor. */ - void const *end = (void const*)vc + vc->std.bLength + vc->ctl.wTotalLength; + uint8_t const *end = (uint8_t const*)vc + vc->std.bLength + vc->ctl.wTotalLength; if (vc->std.bNumEndpoints) { /* Find the notification endpoint descriptor. */ cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); @@ -506,10 +505,10 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum) { TU_LOG2(" open VC %d\n", altnum); - void const *beg = self->beg; - void const *end = beg + self->len; + uint8_t const *beg = self->beg; + uint8_t const *end = beg + self->len; /* The first descriptor is a video control interface descriptor. */ - void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); + uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); TU_LOG2(" cur %d\n", cur - beg); TU_VERIFY(cur < end); @@ -534,7 +533,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t /* Open the notification endpoint */ TU_ASSERT(usbd_edpt_open(rhport, notif)); } - self->cur = (uint16_t) ((void const*)vc - beg); + self->cur = (uint16_t) ((uint8_t const*)vc - beg); return true; } @@ -546,7 +545,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint { uint_fast8_t i; TU_LOG2(" reopen VS %d\n", altnum); - void const *desc = _videod_itf[stm->index_vc].beg; + uint8_t const *desc = _videod_itf[stm->index_vc].beg; /* Close endpoints of previous settings. */ for (i = 0; i < TU_ARRAY_SIZE(stm->desc.ep); ++i) { @@ -563,9 +562,9 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint stm->offset = 0; /* Find a alternate interface */ - void const *beg = desc + stm->desc.beg; - void const *end = desc + stm->desc.end; - void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); + uint8_t const *beg = desc + stm->desc.beg; + uint8_t const *end = desc + stm->desc.end; + uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); TU_VERIFY(cur < end); uint_fast8_t numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints; TU_ASSERT(numeps <= TU_ARRAY_SIZE(stm->desc.ep)); @@ -977,7 +976,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu if (!stm || !stm->desc.ep[0] || stm->buffer) return false; /* Find EP address */ - void const *desc = _videod_itf[stm->index_vc].beg; + uint8_t const *desc = _videod_itf[stm->index_vc].beg; uint8_t ep_addr = 0; for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) { uint_fast16_t ofs_ep = stm->desc.ep[i]; @@ -1044,15 +1043,15 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin } TU_ASSERT(ctl_idx < CFG_TUD_VIDEO, 0); - void const *end = (void const*)itf_desc + max_len; - self->beg = itf_desc; + uint8_t const *end = (uint8_t const*)itf_desc + max_len; + self->beg = (uint8_t const *)itf_desc; self->len = max_len; /*------------- Video Control Interface -------------*/ TU_VERIFY(_open_vc_itf(rhport, self, 0), 0); tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); uint_fast8_t bInCollection = vc->ctl.bInCollection; /* Find the end of the video interface descriptor */ - void const *cur = _next_desc_itf(itf_desc, end); + uint8_t const *cur = _next_desc_itf(itf_desc, end); for (uint8_t stm_idx = 0; stm_idx < bInCollection; ++stm_idx) { videod_streaming_interface_t *stm = NULL; /* find free streaming interface handle */ @@ -1085,7 +1084,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ /* Identify which control interface to use */ uint_fast8_t itf; for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) { - void const *desc = _videod_itf[itf].beg; + uint8_t const *desc = _videod_itf[itf].beg; if (!desc) continue; if (itfnum == _desc_itfnum(desc)) break; } @@ -1101,7 +1100,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ for (itf = 0; itf < CFG_TUD_VIDEO_STREAMING; ++itf) { videod_streaming_interface_t *stm = &_videod_streaming_itf[itf]; if (!stm->desc.beg) continue; - void const *desc = _videod_itf[stm->index_vc].beg; + uint8_t const *desc = _videod_itf[stm->index_vc].beg; if (itfnum == _desc_itfnum(desc + stm->desc.beg)) break; } @@ -1127,7 +1126,7 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3 uint_fast16_t const ep_ofs = stm->desc.ep[0]; if (!ep_ofs) continue; ctl = &_videod_itf[stm->index_vc]; - void const *desc = ctl->beg; + uint8_t const *desc = ctl->beg; if (ep_addr == _desc_ep_addr(desc + ep_ofs)) break; } -- cgit v1.3.1 From 65ba15c37d50fa470fa24c38dbf0e30eba3147c0 Mon Sep 17 00:00:00 2001 From: Ben Avison Date: Mon, 5 Sep 2022 12:53:49 +0100 Subject: Remove unreachable code IAR generates warning Pe111 'statement is unreachable'. In a couple of cases, replace return statements with TU_ATTR_FALLTHROUGH; because some compilers apparently can't figure out that the return statements are unreachable but do whinge about an imagined fall-through without them! --- examples/device/audio_4_channel_mic/src/main.c | 3 --- examples/device/audio_test/src/main.c | 3 --- examples/device/board_test/src/main.c | 2 -- examples/device/cdc_dual_ports/src/main.c | 2 -- examples/device/cdc_msc/src/main.c | 2 -- examples/device/dfu/src/main.c | 2 -- examples/device/dfu_runtime/src/main.c | 2 -- examples/device/dynamic_configuration/src/main.c | 2 -- examples/device/hid_composite/src/main.c | 2 -- examples/device/hid_generic_inout/src/main.c | 2 -- examples/device/hid_multiple_interface/src/main.c | 2 -- examples/device/midi_test/src/main.c | 3 --- examples/device/msc_dual_lun/src/main.c | 2 -- examples/device/uac2_headset/src/main.c | 2 -- examples/device/usbtmc/src/main.c | 2 -- examples/device/usbtmc/src/usbtmc_app.c | 1 - examples/device/video_capture/src/main.c | 2 -- examples/device/webusb_serial/src/main.c | 2 -- examples/host/cdc_msc_hid/src/main.c | 2 -- examples/host/hid_controller/src/main.c | 2 -- src/class/usbtmc/usbtmc_device.c | 10 +++------- src/class/video/video_device.c | 1 - src/portable/raspberrypi/rp2040/hcd_rp2040.c | 6 ++---- 23 files changed, 5 insertions(+), 54 deletions(-) (limited to 'src') diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c index a6af5fd19..662f67df3 100644 --- a/examples/device/audio_4_channel_mic/src/main.c +++ b/examples/device/audio_4_channel_mic/src/main.c @@ -99,9 +99,6 @@ int main(void) led_blinking_task(); audio_task(); } - - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c index d0849c7ac..4b88c2883 100644 --- a/examples/device/audio_test/src/main.c +++ b/examples/device/audio_test/src/main.c @@ -100,9 +100,6 @@ int main(void) led_blinking_task(); audio_task(); } - - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c index 5e28cbb27..207ca6294 100644 --- a/examples/device/board_test/src/main.c +++ b/examples/device/board_test/src/main.c @@ -67,8 +67,6 @@ int main(void) led_state = 1 - led_state; // toggle } } - - return 0; } #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c index 0264f0566..893b0dbc5 100644 --- a/examples/device/cdc_dual_ports/src/main.c +++ b/examples/device/cdc_dual_ports/src/main.c @@ -47,8 +47,6 @@ int main(void) tud_task(); // tinyusb device task cdc_task(); } - - return 0; } // echo to either Serial0 or Serial1 diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c index c3666763b..043b4e8f5 100644 --- a/examples/device/cdc_msc/src/main.c +++ b/examples/device/cdc_msc/src/main.c @@ -65,8 +65,6 @@ int main(void) cdc_task(); } - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c index 6bb183819..5f37f25e1 100644 --- a/examples/device/dfu/src/main.c +++ b/examples/device/dfu/src/main.c @@ -82,8 +82,6 @@ int main(void) tud_task(); // tinyusb device task led_blinking_task(); } - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c index 55b380353..3c5f04e82 100644 --- a/examples/device/dfu_runtime/src/main.c +++ b/examples/device/dfu_runtime/src/main.c @@ -77,8 +77,6 @@ int main(void) tud_task(); // tinyusb device task led_blinking_task(); } - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c index 33a603343..69b3acd19 100644 --- a/examples/device/dynamic_configuration/src/main.c +++ b/examples/device/dynamic_configuration/src/main.c @@ -66,8 +66,6 @@ int main(void) cdc_task(); midi_task(); } - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c index f7d76cfc7..75a0633a3 100644 --- a/examples/device/hid_composite/src/main.c +++ b/examples/device/hid_composite/src/main.c @@ -67,8 +67,6 @@ int main(void) hid_task(); } - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c index 5b7daf118..e692d3bd3 100644 --- a/examples/device/hid_generic_inout/src/main.c +++ b/examples/device/hid_generic_inout/src/main.c @@ -88,8 +88,6 @@ int main(void) tud_task(); // tinyusb device task led_blinking_task(); } - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c index 29ba74398..72240b208 100644 --- a/examples/device/hid_multiple_interface/src/main.c +++ b/examples/device/hid_multiple_interface/src/main.c @@ -71,8 +71,6 @@ int main(void) hid_task(); } - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c index 3310348bd..ddf419fe9 100644 --- a/examples/device/midi_test/src/main.c +++ b/examples/device/midi_test/src/main.c @@ -71,9 +71,6 @@ int main(void) led_blinking_task(); midi_task(); } - - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c index 96790d20c..18038e442 100644 --- a/examples/device/msc_dual_lun/src/main.c +++ b/examples/device/msc_dual_lun/src/main.c @@ -62,8 +62,6 @@ int main(void) tud_task(); // tinyusb device task led_blinking_task(); } - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c index 003dc2a74..3256bc272 100644 --- a/examples/device/uac2_headset/src/main.c +++ b/examples/device/uac2_headset/src/main.c @@ -113,8 +113,6 @@ int main(void) audio_task(); led_blinking_task(); } - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c index 6945d8743..8fc06b56c 100644 --- a/examples/device/usbtmc/src/main.c +++ b/examples/device/usbtmc/src/main.c @@ -63,8 +63,6 @@ int main(void) led_blinking_task(); usbtmc_app_task_iter(); } - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/usbtmc/src/usbtmc_app.c b/examples/device/usbtmc/src/usbtmc_app.c index 115163c7f..e1ce115ad 100644 --- a/examples/device/usbtmc/src/usbtmc_app.c +++ b/examples/device/usbtmc/src/usbtmc_app.c @@ -254,7 +254,6 @@ void usbtmc_app_task_iter(void) { break; default: TU_ASSERT(false,); - return; } } diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index 4028352da..0f81c693a 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -66,8 +66,6 @@ int main(void) video_task(); } - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c index 604d30a83..23aa79f58 100644 --- a/examples/device/webusb_serial/src/main.c +++ b/examples/device/webusb_serial/src/main.c @@ -103,8 +103,6 @@ int main(void) webserial_task(); led_blinking_task(); } - - return 0; } // send characters to both CDC and WebUSB diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c index 664cbf035..091c002ac 100644 --- a/examples/host/cdc_msc_hid/src/main.c +++ b/examples/host/cdc_msc_hid/src/main.c @@ -62,8 +62,6 @@ int main(void) hid_app_task(); #endif } - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c index 299a3ff10..13d1d6cdb 100644 --- a/examples/host/hid_controller/src/main.c +++ b/examples/host/hid_controller/src/main.c @@ -68,8 +68,6 @@ int main(void) hid_app_task(); #endif } - - return 0; } //--------------------------------------------------------------------+ diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index af4a92732..64db85fcf 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -496,7 +496,6 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint default: usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); TU_VERIFY(false); - return false; } return true; @@ -509,8 +508,8 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint return true; case STATE_ABORTING_BULK_OUT: - TU_VERIFY(false); - return false; // Should be stalled by now, shouldn't have received a packet. + TU_VERIFY(false); // Should be stalled by now, shouldn't have received a packet. + TU_ATTR_FALLTHROUGH; // Not really - some compilers can't figure out that the above macro always returns. case STATE_TX_REQUESTED: case STATE_TX_INITIATED: @@ -567,7 +566,6 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint default: TU_ASSERT(false); - return false; } } else if (ep_addr == usbtmc_state.ep_int_in) { @@ -872,15 +870,13 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request { TU_VERIFY(request->bmRequestType == 0xA1); // in,class,interface TU_VERIFY(false); - return false; + TU_ATTR_FALLTHROUGH; // Not really - some compilers can't figure out that the above macro always returns. } #endif default: TU_VERIFY(false); - return false; } - TU_VERIFY(false); } #endif /* CFG_TUD_TSMC */ diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 1f653f5c5..a27287360 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -943,7 +943,6 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage, default: return VIDEO_ERROR_INVALID_REQUEST; } - return VIDEO_ERROR_UNKNOWN; } //--------------------------------------------------------------------+ diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 5badb261a..f65749a2f 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -432,8 +432,7 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport) case 2: return TUSB_SPEED_FULL; default: - panic("Invalid speed\n"); - return TUSB_SPEED_INVALID; + panic("Invalid speed\n"); // does not return } } @@ -599,8 +598,7 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) (void) dev_addr; (void) ep_addr; - panic("hcd_clear_stall"); - return true; + panic("hcd_clear_stall"); // does not return } #endif -- cgit v1.3.1 From 53f0d5538bd2ab171567c9ba3138522accc8145d Mon Sep 17 00:00:00 2001 From: Ben Avison Date: Thu, 1 Sep 2022 12:34:25 +0100 Subject: Don't assume ints automatically convert to enums IAR generates warning Pe188 'enumerated type mixed with another type'. --- examples/device/audio_4_channel_mic/src/main.c | 2 +- examples/device/audio_test/src/main.c | 2 +- src/class/cdc/cdc_host.c | 2 +- src/host/usbh.c | 6 +++--- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c index 662f67df3..db2e9bf95 100644 --- a/examples/device/audio_4_channel_mic/src/main.c +++ b/examples/device/audio_4_channel_mic/src/main.c @@ -287,7 +287,7 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * // Those are dummy values for now ret.bNrChannels = 1; - ret.bmChannelConfig = 0; + ret.bmChannelConfig = (audio_channel_config_t) 0; ret.iChannelNames = 0; TU_LOG2(" Get terminal connector\r\n"); diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c index 4b88c2883..a3bf767f4 100644 --- a/examples/device/audio_test/src/main.c +++ b/examples/device/audio_test/src/main.c @@ -288,7 +288,7 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * // Those are dummy values for now ret.bNrChannels = 1; - ret.bmChannelConfig = 0; + ret.bmChannelConfig = (audio_channel_config_t) 0; ret.iChannelNames = 0; TU_LOG2(" Get terminal connector\r\n"); diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index ee824cb4e..09acc0c70 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -245,7 +245,7 @@ bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num) bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) { (void) ep_addr; - tuh_cdc_xfer_isr( dev_addr, event, 0, xferred_bytes ); + tuh_cdc_xfer_isr( dev_addr, event, (cdc_pipeid_t) 0, xferred_bytes ); return true; } diff --git a/src/host/usbh.c b/src/host/usbh.c index 9d618db92..32f701248 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -449,7 +449,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { // device 0 only has control endpoint TU_ASSERT(epnum == 0, ); - usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len); + usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len); } else { @@ -461,14 +461,14 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) if ( 0 == epnum ) { - usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len); + usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len); }else { uint8_t drv_id = dev->ep2drv[epnum][ep_dir]; if(drv_id < USBH_CLASS_DRIVER_COUNT) { TU_LOG2("%s xfer callback\r\n", usbh_class_drivers[drv_id].name); - usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len); + usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len); } else { diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 89fd6b82d..ebf352d39 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -201,7 +201,7 @@ static void __tusb_irq_path_func(hw_handle_buff_status)(void) usb_hw_clear->buf_status = bit; // IN transfer for even i, OUT transfer for odd i - struct hw_endpoint *ep = hw_endpoint_get_by_num(i >> 1u, !(i & 1u)); + struct hw_endpoint *ep = hw_endpoint_get_by_num(i >> 1u, !(i & 1u) ? TUSB_DIR_IN : TUSB_DIR_OUT); // Continue xfer bool done = hw_endpoint_xfer_continue(ep); -- cgit v1.3.1 From 6a2d01bae47d2660dc2d10941e767fc0bc0e97bc Mon Sep 17 00:00:00 2001 From: Ben Avison Date: Thu, 1 Sep 2022 12:33:12 +0100 Subject: Don't assume different enum types can be combined IAR generates warning Pa089 'enumerated type mixed with another enumerated type'. --- examples/device/uac2_headset/src/usb_descriptors.h | 8 ++++---- src/class/video/video.h | 2 +- src/device/usbd.h | 8 ++++---- 3 files changed, 9 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h index 342b4fac1..7d1f60e82 100644 --- a/examples/device/uac2_headset/src/usb_descriptors.h +++ b/examples/device/uac2_headset/src/usb_descriptors.h @@ -114,7 +114,7 @@ enum /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\ /* Interface 1, Alternate 2 - alternate interface for data streaming */\ @@ -124,7 +124,7 @@ enum /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\ /* Standard AS Interface Descriptor(4.9.1) */\ @@ -138,7 +138,7 @@ enum /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\ /* Interface 2, Alternate 2 - alternate interface for data streaming */\ @@ -148,7 +148,7 @@ enum /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000) diff --git a/src/class/video/video.h b/src/class/video/video.h index 844746546..eb2f6adc9 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -470,7 +470,7 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c /* 3.10.1.1 */ #define TUD_VIDEO_DESC_EP_ISO(_ep, _epsize, _ep_interval) \ - 7, TUSB_DESC_ENDPOINT, _ep, TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS,\ + 7, TUSB_DESC_ENDPOINT, _ep, (uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS,\ U16_TO_U8S_LE(_epsize), _ep_interval /* 3.10.1.2 */ diff --git a/src/device/usbd.h b/src/device/usbd.h index 17b4d927b..64f166826 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -418,7 +418,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */ #define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN 7 #define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(_ep, _interval) \ - TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_NO_SYNC | TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval + TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_NO_SYNC | TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval // AUDIO simple descriptor (UAC2) for 1 microphone input // - 1 Input Terminal, 1 Feature Unit (Mute and Volume Control), 1 Output Terminal, 1 Clock Source @@ -465,7 +465,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000) @@ -514,7 +514,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000) @@ -562,7 +562,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\ /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\ -- cgit v1.3.1 From caff3b5c54615a0cc4e35dadffb99af543d0165f Mon Sep 17 00:00:00 2001 From: Ben Avison Date: Thu, 1 Sep 2022 14:29:30 +0100 Subject: Remove unused static data This affects struct rspMsg in usbtmc_app.c (unconditionally) and uint8_t termChar in usbtmc_device.c (when NDEBUG is defined). IAR generates warning Pe550 'variable was set but never used'. --- examples/device/usbtmc/src/usbtmc_app.c | 11 ----------- src/class/usbtmc/usbtmc_device.c | 4 ++++ 2 files changed, 4 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/examples/device/usbtmc/src/usbtmc_app.c b/examples/device/usbtmc/src/usbtmc_app.c index e1ce115ad..0057a429f 100644 --- a/examples/device/usbtmc/src/usbtmc_app.c +++ b/examples/device/usbtmc/src/usbtmc_app.c @@ -92,14 +92,6 @@ static size_t buffer_tx_ix; // for transmitting using multiple transfers static uint8_t buffer[225]; // A few packets long should be enough. -static usbtmc_msg_dev_dep_msg_in_header_t rspMsg = { - .bmTransferAttributes = - { - .EOM = 1, - .UsingTermChar = 0 - } -}; - void tud_usbtmc_open_cb(uint8_t interface_id) { (void)interface_id; @@ -188,9 +180,6 @@ static unsigned int msgReqLen; bool tud_usbtmc_msgBulkIn_request_cb(usbtmc_msg_request_dev_dep_in const * request) { - rspMsg.header.MsgID = request->header.MsgID, - rspMsg.header.bTag = request->header.bTag, - rspMsg.header.bTagInverse = request->header.bTagInverse; msgReqLen = request->TransferSize; #ifdef xDEBUG diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index 64db85fcf..e96990c49 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -154,7 +154,9 @@ TU_VERIFY_STATIC(USBTMCD_BUFFER_SIZE >= 32u,"USBTMC dev buffer size too small"); static bool handle_devMsgOutStart(uint8_t rhport, void *data, size_t len); static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t packetLen); +#ifndef NDEBUG static uint8_t termChar; +#endif static uint8_t termCharRequested = false; osal_mutex_def_t usbtmcLockBuffer; @@ -440,7 +442,9 @@ static bool handle_devMsgIn(void *data, size_t len) usbtmc_state.transfer_size_sent = 0u; termCharRequested = msg->bmTransferAttributes.TermCharEnabled; +#ifndef NDEBUG termChar = msg->TermChar; +#endif if(termCharRequested) TU_VERIFY(usbtmc_state.capabilities->bmDevCapabilities.canEndBulkInOnTermChar); -- cgit v1.3.1 From 62d90c850096277080e4044dd37ef9c18748f06c Mon Sep 17 00:00:00 2001 From: Ben Avison Date: Thu, 1 Sep 2022 14:33:04 +0100 Subject: Move variable into its own curly-brace scope IAR generates warning Pe546 'transfer of control bypasses initialization of variable "invInvTag"'. --- src/class/usbtmc/usbtmc_device.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index e96990c49..d7ba02d29 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -470,8 +470,10 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint case STATE_IDLE: TU_VERIFY(xferred_bytes >= sizeof(usbtmc_msg_generic_t)); msg = (usbtmc_msg_generic_t*)(usbtmc_state.ep_bulk_out_buf); - uint8_t invInvTag = (uint8_t)~(msg->header.bTagInverse); - TU_VERIFY(msg->header.bTag == invInvTag); + { + uint8_t invInvTag = (uint8_t)~(msg->header.bTagInverse); + TU_VERIFY(msg->header.bTag == invInvTag); + } TU_VERIFY(msg->header.bTag != 0x00); switch(msg->header.MsgID) { -- cgit v1.3.1 From 01edbb8af6b22fa213bcbbaccd92c9be5f72b376 Mon Sep 17 00:00:00 2001 From: Ben Avison Date: Thu, 1 Sep 2022 17:10:26 +0100 Subject: IAR doesn't support __attribute__((fallthrough)) IAR generates warning Pa167 'the "fallthrough" attribute is not supported'. It doesn't generate warnings when one switch case falls through to another, so simply make TU_ATTR_FALLTHROUGH expand to an empty string. Also replace one instance of __attribute__ with the macro. --- src/common/tusb_compiler.h | 2 +- src/host/usbh.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index 2c30daf6f..894d0178a 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -189,7 +189,7 @@ #define TU_ATTR_DEPRECATED(mess) __attribute__ ((deprecated(mess))) // warn if function with this attribute is used #define TU_ATTR_UNUSED __attribute__ ((unused)) // Function/Variable is meant to be possibly unused #define TU_ATTR_USED __attribute__ ((used)) // Function/Variable is meant to be used - #define TU_ATTR_FALLTHROUGH __attribute__((fallthrough)) + #define TU_ATTR_FALLTHROUGH #define TU_ATTR_PACKED_BEGIN #define TU_ATTR_PACKED_END diff --git a/src/host/usbh.c b/src/host/usbh.c index 32f701248..fb8479419 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1273,7 +1273,7 @@ static void process_enumeration(tuh_xfer_t* xfer) break; } #endif - __attribute__((fallthrough)); + TU_ATTR_FALLTHROUGH; #endif case ENUM_SET_ADDR: -- cgit v1.3.1 From 73f22e31c7a31e9b974e27407b906bbc8cb05a7a Mon Sep 17 00:00:00 2001 From: Ben Avison Date: Mon, 12 Sep 2022 14:46:26 +0100 Subject: [rp2040] Wrap GCC pragmas in #ifdef __GNUC__ IAR generates warning Pe161 'unrecognized #pragma'. --- src/portable/raspberrypi/rp2040/rp2040_usb.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index 25c013bd2..adb9151f9 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -57,15 +57,19 @@ void rp2040_usb_init(void) reset_block(RESETS_RESET_USBCTRL_BITS); unreset_block_wait(RESETS_RESET_USBCTRL_BITS); +#ifdef __GNUC__ // Clear any previous state just in case #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Warray-bounds" #if __GNUC__ > 6 #pragma GCC diagnostic ignored "-Wstringop-overflow" +#endif #endif memset(usb_hw, 0, sizeof(*usb_hw)); memset(usb_dpram, 0, sizeof(*usb_dpram)); +#ifdef __GNUC__ #pragma GCC diagnostic pop +#endif // Mux the controller to the onboard usb phy usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS; -- cgit v1.3.1 From 2a520fb921fceb2a8e6182bff073c4a98504127f Mon Sep 17 00:00:00 2001 From: gaoyichuan Date: Wed, 25 May 2022 09:51:58 +0800 Subject: hid: add fido hid descriptor templates --- src/class/hid/hid.h | 9 +++++++++ src/class/hid/hid_device.h | 23 +++++++++++++++++++++++ 2 files changed, 32 insertions(+) (limited to 'src') diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h index 44a464be1..296664f62 100644 --- a/src/class/hid/hid.h +++ b/src/class/hid/hid.h @@ -708,6 +708,7 @@ enum { HID_USAGE_PAGE_MSR = 0x8e, HID_USAGE_PAGE_CAMERA = 0x90, HID_USAGE_PAGE_ARCADE = 0x91, + HID_USAGE_PAGE_FIDO_ALLIANCE = 0xF1D0, HID_USAGE_PAGE_VENDOR = 0xFF00 // 0xFF00 - 0xFFFF }; @@ -844,6 +845,14 @@ enum HID_USAGE_CONSUMER_AC_PAN = 0x0238, }; +/// HID Usage Table: FIDO Alliance Page (0xF1D0) +enum +{ + HID_USAGE_FIDO_U2F_AUTHENTICATOR_DEVICE = 0x01, + HID_USAGE_FIDO_INPUT_REPORT_DATA = 0x20, + HID_USAGE_FIDO_OUTPUT_REPORT_DATA = 0x21 +}; + /*-------------------------------------------------------------------- * ASCII to KEYCODE Conversion * Expand to array of [128][2] (shift, keycode) diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h index 3143b1024..d6cf27bd8 100644 --- a/src/class/hid/hid_device.h +++ b/src/class/hid/hid_device.h @@ -352,6 +352,29 @@ static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y HID_INPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\ HID_COLLECTION_END \ +// FIDO U2F Authenticator Descriptor Template +#define TUD_HID_REPORT_DESC_FIDO_U2F(...) \ + HID_USAGE_PAGE_N ( HID_USAGE_PAGE_FIDO_ALLIANCE, 2 ) ,\ + HID_USAGE ( HID_USAGE_FIDO_U2F_AUTHENTICATOR_DEVICE ) ,\ + HID_COLLECTION ( HID_COLLECTION_APPLICATION ) ,\ + /* Report ID if any */ \ + __VA_ARGS__ \ + /* Usage Data In */ \ + HID_USAGE ( HID_USAGE_FIDO_INPUT_REPORT_DATA ) ,\ + HID_LOGICAL_MIN ( 0 ) ,\ + HID_LOGICAL_MAX_N ( 255, 2 ) ,\ + HID_REPORT_SIZE ( 8 ) ,\ + HID_REPORT_COUNT ( 64 ) ,\ + HID_INPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\ + /* Usage Data Out */ \ + HID_USAGE ( HID_USAGE_FIDO_OUTPUT_REPORT_DATA ) ,\ + HID_LOGICAL_MIN ( 0 ) ,\ + HID_LOGICAL_MAX_N ( 255, 2 ) ,\ + HID_REPORT_SIZE ( 8 ) ,\ + HID_REPORT_COUNT ( 64 ) ,\ + HID_OUTPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\ + HID_COLLECTION_END \ + // HID Generic Input & Output // - 1st parameter is report size (mandatory) // - 2nd parameter is report id HID_REPORT_ID(n) (optional) -- cgit v1.3.1 From 3846d5f38c465d673442db1085c69f3602e21470 Mon Sep 17 00:00:00 2001 From: gaoyichuan Date: Sat, 15 Oct 2022 19:22:21 +0800 Subject: hid: add configurable report size for fido --- src/class/hid/hid_device.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h index d6cf27bd8..a9f47d644 100644 --- a/src/class/hid/hid_device.h +++ b/src/class/hid/hid_device.h @@ -353,7 +353,9 @@ static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y HID_COLLECTION_END \ // FIDO U2F Authenticator Descriptor Template -#define TUD_HID_REPORT_DESC_FIDO_U2F(...) \ +// - 1st parameter is report size, which is 64 bytes maximum in U2F +// - 2nd parameter is HID_REPORT_ID(n) (optional) +#define TUD_HID_REPORT_DESC_FIDO_U2F(report_size, ...) \ HID_USAGE_PAGE_N ( HID_USAGE_PAGE_FIDO_ALLIANCE, 2 ) ,\ HID_USAGE ( HID_USAGE_FIDO_U2F_AUTHENTICATOR_DEVICE ) ,\ HID_COLLECTION ( HID_COLLECTION_APPLICATION ) ,\ @@ -362,16 +364,16 @@ static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y /* Usage Data In */ \ HID_USAGE ( HID_USAGE_FIDO_INPUT_REPORT_DATA ) ,\ HID_LOGICAL_MIN ( 0 ) ,\ - HID_LOGICAL_MAX_N ( 255, 2 ) ,\ + HID_LOGICAL_MAX_N ( 0xff, 2 ) ,\ HID_REPORT_SIZE ( 8 ) ,\ - HID_REPORT_COUNT ( 64 ) ,\ + HID_REPORT_COUNT ( report_size ) ,\ HID_INPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\ /* Usage Data Out */ \ HID_USAGE ( HID_USAGE_FIDO_OUTPUT_REPORT_DATA ) ,\ HID_LOGICAL_MIN ( 0 ) ,\ - HID_LOGICAL_MAX_N ( 255, 2 ) ,\ + HID_LOGICAL_MAX_N ( 0xff, 2 ) ,\ HID_REPORT_SIZE ( 8 ) ,\ - HID_REPORT_COUNT ( 64 ) ,\ + HID_REPORT_COUNT ( report_size ) ,\ HID_OUTPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\ HID_COLLECTION_END \ -- cgit v1.3.1 From d2c9b8bcfba42ebc0023154493383b8bcb892020 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 4 Nov 2022 16:14:35 +0700 Subject: fix -wconversion-int and add minor comment --- src/common/tusb_types.h | 8 ++++++-- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 18 ++++++++++-------- 2 files changed, 16 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index cfa24bd82..e11f08dd1 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -513,15 +513,19 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpo return tu_le16toh(desc_ep->wMaxPacketSize) & TU_GENMASK(10, 0); } -static inline const char *tu_edpt_dir_str(tusb_dir_t dir) { +#if CFG_TUSB_DEBUG +TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir) +{ static const char *str[] = {"out", "in"}; return str[dir]; } -static inline const char *tu_edpt_type_str(tusb_xfer_type_t t) { +TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t) +{ static const char *str[] = {"control", "isochronous", "bulk", "interrupt"}; return str[t]; } +#endif //--------------------------------------------------------------------+ // Descriptor helper diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 1125d30b6..10237d1f9 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -138,10 +138,10 @@ static void __tusb_irq_path_func(hw_handle_buff_status)(void) _handle_buff_status_bit(bit, ep); } - // Check interrupt endpoints + // Check "interrupt" (asynchronous) endpoints for both IN and OUT for (uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++) { - // EPX is bit 0 + // EPX is bit 0 & 1 // IEP1 IN is bit 2 // IEP1 OUT is bit 3 // IEP2 IN is bit 4 @@ -149,7 +149,8 @@ static void __tusb_irq_path_func(hw_handle_buff_status)(void) // IEP3 IN is bit 6 // IEP3 OUT is bit 7 // etc - for(int j = 0; j < 2; j++){ + for(uint j = 0; j < 2; j++) + { bit = 1 << (i*2+j); if (remaining_buffers & bit) { @@ -279,6 +280,8 @@ static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type) if (transfer_type != TUSB_XFER_CONTROL) { + // Note: even though datasheet name these "Interrupt" endpoints. These are actually + // "Asynchronous" endpoints and can be used for other type such as: Bulk (ISO need confirmation) ep = _next_free_interrupt_ep(); pico_info("Allocate %s ep %d\n", tu_edpt_type_str(transfer_type), ep->interrupt_num); assert(ep); @@ -344,11 +347,10 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t if (ep != &epx) { // Endpoint has its own addr_endp and interrupt bits to be setup! - // This is an interrupt endpoint - // so need to set up interrupt endpoint address control register with: - // device address - // endpoint number / direction - // preamble + // This is an interrupt/async endpoint. so need to set up ADDR_ENDP register with: + // - device address + // - endpoint number / direction + // - preamble uint32_t reg = (uint32_t) (dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB)); if (dir == TUSB_DIR_OUT) -- cgit v1.3.1 From 1eae139aa94130a63ecc4725852cb69c02566c82 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Mon, 7 Nov 2022 12:32:36 +0100 Subject: Add support for STM32L412. --- .../boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld | 184 +++++++++++++++++++++ hw/bsp/stm32l4/boards/stm32l412nucleo/board.h | 141 ++++++++++++++++ hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk | 10 ++ hw/bsp/stm32l4/family.c | 27 ++- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 9 +- .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 4 + 6 files changed, 370 insertions(+), 5 deletions(-) create mode 100644 hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld create mode 100644 hw/bsp/stm32l4/boards/stm32l412nucleo/board.h create mode 100644 hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk (limited to 'src') diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld new file mode 100644 index 000000000..28cd96131 --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld @@ -0,0 +1,184 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32L412KBTx Device with +** 128KByte FLASH, 40KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20008000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K +SRAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 8K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(8); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(8); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(8); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(8); + } >FLASH + + .ARM.extab : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } >FLASH + .ARM : { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(8); + } >FLASH + + .preinit_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } >FLASH + + .init_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } >FLASH + .fini_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(8); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(8); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h new file mode 100644 index 000000000..704d742cc --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h @@ -0,0 +1,141 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define LED_PORT GPIOB +#define LED_PIN GPIO_PIN_3 +#define LED_STATE_ON 1 + +// Not a real button +#define BUTTON_PORT GPIOB +#define BUTTON_PIN GPIO_PIN_0 +#define BUTTON_STATE_ACTIVE 1 + +#define UART_DEV LPUART1 +#define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE +#define UART_GPIO_PORT GPIOA +#define UART_GPIO_AF GPIO_AF8_LPUART1 +#define UART_TX_PIN GPIO_PIN_2 +#define UART_RX_PIN GPIO_PIN_3 + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ + +/** + * @brief System Clock Configuration + * The system Clock is configured as follow : + * System Clock source = PLL (MSI) + * SYSCLK(Hz) = 80000000 + * HCLK(Hz) = 80000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 1 + * APB2 Prescaler = 1 + * MSI Frequency(Hz) = 8000000 + * PLL_M = 1 + * PLL_N = 10 + * PLL_Q = 2 + * PLL_R = 2 + * VDD(V) = 3.3 + * @param None + * @retval None + */ + +static inline void board_clock_init(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_CRSInitTypeDef RCC_CRSInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 10; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); + + /** Enable the SYSCFG APB clock + */ + __HAL_RCC_CRS_CLK_ENABLE(); + + /** Configures CRS + */ + RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1; + RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB; + RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING; + RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000); + RCC_CRSInitStruct.ErrorLimitValue = 34; + RCC_CRSInitStruct.HSI48CalibrationValue = 32; + + HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct); + + /* Select HSI48 output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL output as UART clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk new file mode 100644 index 000000000..841ee4948 --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk @@ -0,0 +1,10 @@ +CFLAGS += \ + -DSTM32L412xx \ + +# All source paths should be relative to the top level. +LD_FILE = $(BOARD_PATH)/STM32L412KBUx_FLASH.ld + +SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l412xx.s + +# For flash-jlink target +JLINK_DEVICE = stm32l412kb diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c index c15be98e5..8b464f647 100644 --- a/hw/bsp/stm32l4/family.c +++ b/hw/bsp/stm32l4/family.c @@ -33,7 +33,11 @@ //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ +#if defined(USB_OTG_FS) void OTG_FS_IRQHandler(void) +#else +void USB_IRQHandler(void) +#endif { tud_int_handler(0); } @@ -53,9 +57,15 @@ void board_init(void) __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); +#if defined(GPIOE) __HAL_RCC_GPIOE_CLK_ENABLE(); +#endif +#if defined(GPIOF) __HAL_RCC_GPIOF_CLK_ENABLE(); +#endif +#if defined(GPIOG) __HAL_RCC_GPIOG_CLK_ENABLE(); +#endif __HAL_RCC_GPIOH_CLK_ENABLE(); UART_CLK_EN(); @@ -95,7 +105,10 @@ void board_init(void) // IOSV bit MUST be set to access GPIO port G[2:15] */ __HAL_RCC_PWR_CLK_ENABLE(); + +#if defined(PWR_CR2_IOSV) HAL_PWREx_EnableVddIO2(); +#endif // Uart GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; @@ -124,9 +137,14 @@ void board_init(void) GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; +#if defined(USB_OTG_FS) GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; +#else + GPIO_InitStruct.Alternate = GPIO_AF10_USB_FS; +#endif HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); +#if defined(USB_OTG_FS) /* Configure VBUS Pin */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; @@ -139,11 +157,16 @@ void board_init(void) GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); +#endif /* Enable USB FS Clocks */ +#if defined(USB_OTG_FS) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - board_vbus_sense_init(); +#else + __HAL_RCC_USB_CLK_ENABLE(); +#endif + } //--------------------------------------------------------------------+ @@ -187,7 +210,7 @@ uint32_t board_millis(void) void HardFault_Handler (void) { - asm("bkpt"); + asm("bkpt 0x10"); } // Required by __libc_init_array in startup code if we are compiling using diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 177a7ad2a..ec3964b4a 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -111,7 +111,8 @@ #if TUSB_OPT_DEVICE_ENABLED && \ ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32G4) || \ - (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) \ + (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) || \ + (TU_CHECK_MCU(OPT_MCU_STM32L4) && !defined(DCD_ATTR_DWC2_STM32)) \ ) // In order to reduce the dependance on HAL, we undefine this. @@ -294,7 +295,8 @@ void dcd_int_enable (uint8_t rhport) // Member here forces write to RAM before allowing ISR to execute __DSB(); __ISB(); -#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 +#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || \ + CFG_TUSB_MCU == OPT_MCU_STM32L4 NVIC_EnableIRQ(USB_IRQn); #elif CFG_TUSB_MCU == OPT_MCU_STM32L1 @@ -338,7 +340,8 @@ void dcd_int_disable(uint8_t rhport) { (void)rhport; -#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 +#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || \ + CFG_TUSB_MCU == OPT_MCU_STM32L4 NVIC_DisableIRQ(USB_IRQn); #elif CFG_TUSB_MCU == OPT_MCU_STM32L1 NVIC_DisableIRQ(USB_LP_IRQn); diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 596f7be6c..eabefa687 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -91,6 +91,10 @@ #include "stm32g4xx.h" #define PMA_LENGTH (1024u) +#elif CFG_TUSB_MCU == OPT_MCU_STM32L4 + #include "stm32l4xx.h" + #define PMA_LENGTH (1024u) + #else #error You are using an untested or unimplemented STM32 variant. Please update the driver. // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4 -- cgit v1.3.1 From f3f3739073b46bc7609e4c55f50accbfb08e1807 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Mon, 7 Nov 2022 12:58:23 +0100 Subject: Fix DCD build. --- hw/bsp/stm32l4/family.mk | 1 + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/hw/bsp/stm32l4/family.mk b/hw/bsp/stm32l4/family.mk index d6f55e5f9..1361e184c 100644 --- a/hw/bsp/stm32l4/family.mk +++ b/hw/bsp/stm32l4/family.mk @@ -22,6 +22,7 @@ CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align #src/portable/st/synopsys/dcd_synopsys.c SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index b90ab7d11..c88a8a3a2 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -109,10 +109,17 @@ #define STM32F1_FSDEV #endif +#if defined(STM32L412xx) || defined(STM32L422xx) || \ + defined(STM32L432xx) || defined(STM32L433xx) || \ + defined(STM32L442xx) || defined(STM32L443xx) || \ + defined(STM32L452xx) || defined(STM32L462xx) +#define STM32L4_FSDEV +#endif + #if CFG_TUD_ENABLED && \ ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32G4, OPT_MCU_STM32WB) || \ (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) || \ - (TU_CHECK_MCU(OPT_MCU_STM32L4) && !defined(DCD_ATTR_DWC2_STM32)) \ + (TU_CHECK_MCU(OPT_MCU_STM32L4) && defined(STM32L4_FSDEV)) \ ) // In order to reduce the dependance on HAL, we undefine this. -- cgit v1.3.1 From abfcdf2cfb2f19a20d606ca906e2d75f599b2ed8 Mon Sep 17 00:00:00 2001 From: Kay Sievers Date: Fri, 11 Nov 2022 22:47:48 +0100 Subject: MIDI: support port name strings This allows to set custom descriptive names for virtual MIDI ports/cables. A MIDI port offers different functionality on the same physical USB device. The names make it easier to distinguish one from the other. --- src/device/usbd.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/device/usbd.h b/src/device/usbd.h index 17b4d927b..731c57aad 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -308,15 +308,16 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb (uint8_t)(((_cablenum) - 1) * 4 + 4) #define TUD_MIDI_DESC_JACK_LEN (6 + 6 + 9 + 9) -#define TUD_MIDI_DESC_JACK(_cablenum) \ +#define TUD_MIDI_DESC_JACK_DESC(_cablenum, _stridx) \ /* MS In Jack (Embedded) */\ - 6, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_IN_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_IN_EMB(_cablenum), 0,\ + 6, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_IN_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_IN_EMB(_cablenum), _stridx,\ /* MS In Jack (External) */\ - 6, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_IN_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_IN_EXT(_cablenum), 0,\ + 6, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_IN_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_IN_EXT(_cablenum), _stridx,\ /* MS Out Jack (Embedded), connected to In Jack External */\ - 9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_OUT_EMB(_cablenum), 1, TUD_MIDI_JACKID_IN_EXT(_cablenum), 1, 0,\ + 9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_OUT_EMB(_cablenum), 1, TUD_MIDI_JACKID_IN_EXT(_cablenum), 1, _stridx,\ /* MS Out Jack (External), connected to In Jack Embedded */\ - 9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_OUT_EXT(_cablenum), 1, TUD_MIDI_JACKID_IN_EMB(_cablenum), 1, 0 + 9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_OUT_EXT(_cablenum), 1, TUD_MIDI_JACKID_IN_EMB(_cablenum), 1, _stridx +#define TUD_MIDI_DESC_JACK(_cablenum) TUD_MIDI_DESC_JACK_DESC(_cablenum, 0) #define TUD_MIDI_DESC_EP_LEN(_numcables) (9 + 4 + (_numcables)) #define TUD_MIDI_DESC_EP(_epout, _epsize, _numcables) \ @@ -333,7 +334,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb // - 1 Embedded Jack out connected to 1 External Jack In #define TUD_MIDI_DESCRIPTOR(_itfnum, _stridx, _epout, _epin, _epsize) \ TUD_MIDI_DESC_HEAD(_itfnum, _stridx, 1),\ - TUD_MIDI_DESC_JACK(1),\ + TUD_MIDI_DESC_JACK_DESC(1, 0),\ TUD_MIDI_DESC_EP(_epout, _epsize, 1),\ TUD_MIDI_JACKID_IN_EMB(1),\ TUD_MIDI_DESC_EP(_epin, _epsize, 1),\ -- cgit v1.3.1 From 64ecf43663dcc4f441a4b66c6b07661944ff4d97 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 21 Nov 2022 11:53:15 +0700 Subject: whitespace --- src/class/msc/msc_host.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h index 7718ad4fe..8d95980f9 100644 --- a/src/class/msc/msc_host.h +++ b/src/class/msc/msc_host.h @@ -82,7 +82,7 @@ bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_ms // Perform SCSI Read 10 command. Read n blocks starting from LBA to buffer // Complete callback is invoked when SCSI op is complete. -bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb); +bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb); // Perform SCSI Write 10 command. Write n blocks starting from LBA to device // Complete callback is invoked when SCSI op is complete. -- cgit v1.3.1 From 460bef9dbb40d1c6990c1bfd2f8da48978550932 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 21 Nov 2022 15:49:38 +0700 Subject: host msc example work well with rp2040 pio-usb --- examples/device/board_test/src/main.c | 2 +- examples/host/cdc_msc_hid/CMakeLists.txt | 14 ++++++++++++- examples/host/cdc_msc_hid/src/main.c | 8 -------- examples/host/cdc_msc_hid/src/msc_app.c | 3 --- examples/host/cdc_msc_hid/src/tusb_config.h | 6 ++++++ examples/host/hid_controller/src/hid_app.c | 1 - examples/host/msc_file_explorer/src/main.c | 2 +- examples/host/msc_file_explorer/src/msc_app.c | 5 +++-- hw/bsp/board.h | 8 ++------ hw/bsp/rp2040/family.c | 29 +++++++++++++++------------ src/host/usbh.h | 2 +- 11 files changed, 43 insertions(+), 37 deletions(-) (limited to 'src') diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c index 74beda55f..0289ca15f 100644 --- a/examples/device/board_test/src/main.c +++ b/examples/device/board_test/src/main.c @@ -69,7 +69,7 @@ int main(void) // echo uint8_t ch; - if ( board_uart_read(&ch, 1) ) + if ( board_uart_read(&ch, 1) > 0 ) { board_uart_write(&ch, 1); } diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt index c4a4d8e63..5b44ef217 100644 --- a/examples/host/cdc_msc_hid/CMakeLists.txt +++ b/examples/host/cdc_msc_hid/CMakeLists.txt @@ -29,4 +29,16 @@ target_include_directories(${PROJECT} PUBLIC family_configure_host_example(${PROJECT}) # For rp2040, un-comment to enable pico-pio-usb -# family_add_pico_pio_usb(${PROJECT}) +family_add_pico_pio_usb(${PROJECT}) + +# due to warnings from Pico-PIO-USB +target_compile_options(${PROJECT} PUBLIC + -Wno-error=shadow + -Wno-error=cast-align + -Wno-error=cast-qual + -Wno-error=redundant-decls + -Wno-error=sign-conversion + -Wno-error=conversion + -Wno-error=sign-compare + -Wno-error=unused-function + ) diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c index 664cbf035..d26e41e8d 100644 --- a/examples/host/cdc_msc_hid/src/main.c +++ b/examples/host/cdc_msc_hid/src/main.c @@ -54,13 +54,8 @@ int main(void) tuh_task(); led_blinking_task(); -#if CFG_TUH_CDC cdc_task(); -#endif - -#if CFG_TUH_HID hid_app_task(); -#endif } return 0; @@ -69,7 +64,6 @@ int main(void) //--------------------------------------------------------------------+ // USB CDC //--------------------------------------------------------------------+ -#if CFG_TUH_CDC CFG_TUSB_MEM_SECTION static char serial_in_buffer[64] = { 0 }; // invoked ISR context @@ -90,8 +84,6 @@ void cdc_task(void) } -#endif - //--------------------------------------------------------------------+ // TinyUSB Callbacks //--------------------------------------------------------------------+ diff --git a/examples/host/cdc_msc_hid/src/msc_app.c b/examples/host/cdc_msc_hid/src/msc_app.c index 77a72052d..80a5eab6f 100644 --- a/examples/host/cdc_msc_hid/src/msc_app.c +++ b/examples/host/cdc_msc_hid/src/msc_app.c @@ -25,8 +25,6 @@ #include "tusb.h" -#if CFG_TUH_MSC - //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ @@ -103,4 +101,3 @@ void tuh_msc_umount_cb(uint8_t dev_addr) // } } -#endif diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index 33f34315b..c515405cb 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -34,6 +34,12 @@ // Board Specific Configuration //--------------------------------------------------------------------+ +#if CFG_TUSB_MCU == OPT_MCU_RP2040 +// change to 1 if using pico-pio-usb as host controller for raspberry rp2040 +#define CFG_TUH_RPI_PIO_USB 0 +#define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_USB +#endif + // RHPort number used for host can be defined by board.mk, default to port 0 #ifndef BOARD_TUH_RHPORT #define BOARD_TUH_RHPORT 0 diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c index 582e01959..75c91400e 100644 --- a/examples/host/hid_controller/src/hid_app.c +++ b/examples/host/hid_controller/src/hid_app.c @@ -162,7 +162,6 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance) { printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance); - } // check if different than 2 diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c index 652986b7c..ab2cfd498 100644 --- a/examples/host/msc_file_explorer/src/main.c +++ b/examples/host/msc_file_explorer/src/main.c @@ -35,6 +35,7 @@ //--------------------------------------------------------------------+ void led_blinking_task(void); +// from msc_app.c extern bool msc_app_init(void); extern void msc_app_task(void); @@ -75,7 +76,6 @@ void tuh_umount_cb(uint8_t dev_addr) (void) dev_addr; } - //--------------------------------------------------------------------+ // Blinking Task //--------------------------------------------------------------------+ diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c index 6e5cb672a..b7c9212ee 100644 --- a/examples/host/msc_file_explorer/src/msc_app.c +++ b/examples/host/msc_file_explorer/src/msc_app.c @@ -25,6 +25,7 @@ #include #include "tusb.h" +#include "bsp/board.h" #include "ff.h" #include "diskio.h" @@ -75,13 +76,13 @@ void msc_app_task(void) { if (!_cli) return; - int ch = getchar(); + int ch = board_uart_getchar(); if ( ch > 0 ) { while( ch > 0 ) { embeddedCliReceiveChar(_cli, (char) ch); - ch = getchar(); + ch = board_uart_getchar(); } embeddedCliProcess(_cli); } diff --git a/hw/bsp/board.h b/hw/bsp/board.h index 0826d7786..52c64a1cc 100644 --- a/hw/bsp/board.h +++ b/hw/bsp/board.h @@ -132,15 +132,11 @@ static inline void board_delay(uint32_t ms) } } +// stdio getchar() is blocking, this is non-blocking version for uart static inline int board_uart_getchar(void) { uint8_t c; - return board_uart_read(&c, 1) ? (int) c : (-1); -} - -static inline int board_uart_putchar(uint8_t c) -{ - return board_uart_write(&c, 1); + return ( board_uart_read(&c, 1) > 0 ) ? (int) c : (-1); } #ifdef __cplusplus diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index ee5a73ff6..d78e2c754 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -121,16 +121,6 @@ static uart_inst_t *uart_inst; void board_init(void) { -#ifdef LED_PIN - bi_decl(bi_1pin_with_name(LED_PIN, "LED")); - gpio_init(LED_PIN); - gpio_set_dir(LED_PIN, GPIO_OUT); -#endif - - // Button -#ifndef BUTTON_BOOTSEL -#endif - #if CFG_TUH_RPI_PIO_USB || CFG_TUD_RPI_PIO_USB // Set the system clock to a multiple of 120mhz for bitbanging USB with pico-usb set_sys_clock_khz(120000, true); @@ -148,6 +138,16 @@ void board_init(void) tuh_configure(BOARD_TUH_RHPORT, TUH_CFGID_RPI_PIO_USB_CONFIGURATION, &pio_cfg); #endif +#ifdef LED_PIN + bi_decl(bi_1pin_with_name(LED_PIN, "LED")); + gpio_init(LED_PIN); + gpio_set_dir(LED_PIN, GPIO_OUT); +#endif + + // Button +#ifndef BUTTON_BOOTSEL +#endif + #if defined(UART_DEV) && defined(LIB_PICO_STDIO_UART) bi_decl(bi_2pins_with_func(UART_TX_PIN, UART_TX_PIN, GPIO_FUNC_UART)); uart_inst = uart_get_instance(UART_DEV); @@ -192,10 +192,13 @@ uint32_t board_button_read(void) int board_uart_read(uint8_t* buf, int len) { #ifdef UART_DEV - for(int i=0;i Date: Wed, 23 Nov 2022 16:01:48 +0700 Subject: rework tuh_msc_complete_cb_t signature to use new tuh_msc_complete_data_t add user arg to all scsi command API that support complete callback --- examples/host/cdc_msc_hid/src/msc_app.c | 42 ++-------------- examples/host/msc_file_explorer/src/msc_app.c | 15 +++--- src/class/msc/msc_host.c | 69 +++++++++++++++++---------- src/class/msc/msc_host.h | 23 +++++---- 4 files changed, 74 insertions(+), 75 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/msc_app.c b/examples/host/cdc_msc_hid/src/msc_app.c index 80a5eab6f..797d55f8a 100644 --- a/examples/host/cdc_msc_hid/src/msc_app.c +++ b/examples/host/cdc_msc_hid/src/msc_app.c @@ -30,8 +30,11 @@ //--------------------------------------------------------------------+ static scsi_inquiry_resp_t inquiry_resp; -bool inquiry_complete_cb(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw) +bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) { + msc_cbw_t const* cbw = cb_data->cbw; + msc_csw_t const* csw = cb_data->csw; + if (csw->status != 0) { printf("Inquiry failed\r\n"); @@ -57,47 +60,12 @@ void tuh_msc_mount_cb(uint8_t dev_addr) printf("A MassStorage device is mounted\r\n"); uint8_t const lun = 0; - tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb); -// -// //------------- file system (only 1 LUN support) -------------// -// uint8_t phy_disk = dev_addr-1; -// disk_initialize(phy_disk); -// -// if ( disk_is_ready(phy_disk) ) -// { -// if ( f_mount(phy_disk, &fatfs[phy_disk]) != FR_OK ) -// { -// puts("mount failed"); -// return; -// } -// -// f_chdrive(phy_disk); // change to newly mounted drive -// f_chdir("/"); // root as current dir -// -// cli_init(); -// } + tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb, 0); } void tuh_msc_umount_cb(uint8_t dev_addr) { (void) dev_addr; printf("A MassStorage device is unmounted\r\n"); - -// uint8_t phy_disk = dev_addr-1; -// -// f_mount(phy_disk, NULL); // unmount disk -// disk_deinitialize(phy_disk); -// -// if ( phy_disk == f_get_current_drive() ) -// { // active drive is unplugged --> change to other drive -// for(uint8_t i=0; icbw; + msc_csw_t const* csw = cb_data->csw; + if (csw->status != 0) { printf("Inquiry failed\r\n"); @@ -140,7 +143,7 @@ void tuh_msc_mount_cb(uint8_t dev_addr) printf("A MassStorage device is mounted\r\n"); uint8_t const lun = 0; - tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb); + tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb, 0); } void tuh_msc_umount_cb(uint8_t dev_addr) @@ -178,9 +181,9 @@ static void wait_for_disk_io(BYTE pdrv) } } -static bool disk_io_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw) +static bool disk_io_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) { - (void) dev_addr; (void) cbw; (void) csw; + (void) dev_addr; (void) cb_data; _disk_busy[dev_addr-1] = false; return true; } @@ -212,7 +215,7 @@ DRESULT disk_read ( uint8_t const lun = 0; _disk_busy[pdrv] = true; - tuh_msc_read10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete); + tuh_msc_read10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete, 0); wait_for_disk_io(pdrv); return RES_OK; @@ -231,7 +234,7 @@ DRESULT disk_write ( uint8_t const lun = 0; _disk_busy[pdrv] = true; - tuh_msc_write10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete); + tuh_msc_write10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete, 0); wait_for_disk_io(pdrv); return RES_OK; diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c index 934f79ff7..9e88ebc30 100644 --- a/src/class/msc/msc_host.c +++ b/src/class/msc/msc_host.c @@ -64,6 +64,7 @@ typedef struct uint8_t stage; void* buffer; tuh_msc_complete_cb_t complete_cb; + uintptr_t complete_arg; msc_cbw_t cbw; msc_csw_t csw; @@ -126,7 +127,7 @@ static inline void cbw_init(msc_cbw_t *cbw, uint8_t lun) cbw->lun = lun; } -bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb) +bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) { msch_interface_t* p_msc = get_itf(dev_addr); TU_VERIFY(p_msc->configured); @@ -137,13 +138,14 @@ bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tu p_msc->stage = MSC_STAGE_CMD; p_msc->buffer = data; p_msc->complete_cb = complete_cb; + p_msc->complete_arg = arg; TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t))); return true; } -bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb) +bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) { msch_interface_t* p_msc = get_itf(dev_addr); TU_VERIFY(p_msc->configured); @@ -156,10 +158,10 @@ bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_r cbw.cmd_len = sizeof(scsi_read_capacity10_t); cbw.command[0] = SCSI_CMD_READ_CAPACITY_10; - return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb); + return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg); } -bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb) +bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) { msch_interface_t* p_msc = get_itf(dev_addr); TU_VERIFY(p_msc->mounted); @@ -178,10 +180,10 @@ bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* respons }; memcpy(cbw.command, &cmd_inquiry, cbw.cmd_len); - return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb); + return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg); } -bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb) +bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) { msch_interface_t* p_msc = get_itf(dev_addr); TU_VERIFY(p_msc->configured); @@ -195,10 +197,10 @@ bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_ cbw.command[0] = SCSI_CMD_TEST_UNIT_READY; cbw.command[1] = lun; // according to wiki TODO need verification - return tuh_msc_scsi_command(dev_addr, &cbw, NULL, complete_cb); + return tuh_msc_scsi_command(dev_addr, &cbw, NULL, complete_cb, arg); } -bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_msc_complete_cb_t complete_cb) +bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) { msc_cbw_t cbw; cbw_init(&cbw, lun); @@ -215,10 +217,10 @@ bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_ms memcpy(cbw.command, &cmd_request_sense, cbw.cmd_len); - return tuh_msc_scsi_command(dev_addr, &cbw, resposne, complete_cb); + return tuh_msc_scsi_command(dev_addr, &cbw, resposne, complete_cb, arg); } -bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb) +bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) { msch_interface_t* p_msc = get_itf(dev_addr); TU_VERIFY(p_msc->mounted); @@ -239,10 +241,10 @@ bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, memcpy(cbw.command, &cmd_read10, cbw.cmd_len); - return tuh_msc_scsi_command(dev_addr, &cbw, buffer, complete_cb); + return tuh_msc_scsi_command(dev_addr, &cbw, buffer, complete_cb, arg); } -bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb) +bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) { msch_interface_t* p_msc = get_itf(dev_addr); TU_VERIFY(p_msc->mounted); @@ -263,7 +265,7 @@ bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_ memcpy(cbw.command, &cmd_write10, cbw.cmd_len); - return tuh_msc_scsi_command(dev_addr, &cbw, (void*)(uintptr_t) buffer, complete_cb); + return tuh_msc_scsi_command(dev_addr, &cbw, (void*)(uintptr_t) buffer, complete_cb, arg); } #if 0 @@ -344,7 +346,17 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32 // SCSI op is complete p_msc->stage = MSC_STAGE_IDLE; - if (p_msc->complete_cb) p_msc->complete_cb(dev_addr, cbw, csw); + if (p_msc->complete_cb) + { + tuh_msc_complete_data_t const cb_data = + { + .cbw = cbw, + .csw = csw, + .scsi_data = p_msc->buffer, + .user_arg = p_msc->complete_arg + }; + p_msc->complete_cb(dev_addr, &cb_data); + } break; // unknown state @@ -359,9 +371,9 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32 //--------------------------------------------------------------------+ static void config_get_maxlun_complete (tuh_xfer_t* xfer); -static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw); -static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw); -static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw); +static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data); +static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data); +static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data); bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len) { @@ -446,37 +458,46 @@ static void config_get_maxlun_complete (tuh_xfer_t* xfer) // TODO multiple LUN support TU_LOG2("SCSI Test Unit Ready\r\n"); uint8_t const lun = 0; - tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete); + tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete, 0); } -static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw) +static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) { + msc_cbw_t const* cbw = cb_data->cbw; + msc_csw_t const* csw = cb_data->csw; + if (csw->status == 0) { // Unit is ready, read its capacity TU_LOG2("SCSI Read Capacity\r\n"); - tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer), config_read_capacity_complete); + tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer), config_read_capacity_complete, 0); }else { // Note: During enumeration, some device fails Test Unit Ready and require a few retries // with Request Sense to start working !! // TODO limit number of retries TU_LOG2("SCSI Request Sense\r\n"); - TU_ASSERT(tuh_msc_request_sense(dev_addr, cbw->lun, _msch_buffer, config_request_sense_complete)); + TU_ASSERT(tuh_msc_request_sense(dev_addr, cbw->lun, _msch_buffer, config_request_sense_complete, 0)); } return true; } -static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw) +static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) { + msc_cbw_t const* cbw = cb_data->cbw; + msc_csw_t const* csw = cb_data->csw; + TU_ASSERT(csw->status == 0); - TU_ASSERT(tuh_msc_test_unit_ready(dev_addr, cbw->lun, config_test_unit_ready_complete)); + TU_ASSERT(tuh_msc_test_unit_ready(dev_addr, cbw->lun, config_test_unit_ready_complete, 0)); return true; } -static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw) +static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) { + msc_cbw_t const* cbw = cb_data->cbw; + msc_csw_t const* csw = cb_data->csw; + TU_ASSERT(csw->status == 0); msch_interface_t* p_msc = get_itf(dev_addr); diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h index 8d95980f9..416e4318b 100644 --- a/src/class/msc/msc_host.h +++ b/src/class/msc/msc_host.h @@ -41,7 +41,14 @@ #define CFG_TUH_MSC_MAXLUN 4 #endif -typedef bool (*tuh_msc_complete_cb_t)(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw); +typedef struct { + msc_cbw_t const* cbw; // SCSI command + msc_csw_t const* csw; // SCSI status + void* scsi_data; // SCSI Data + uintptr_t user_arg; // user argument +}tuh_msc_complete_data_t; + +typedef bool (*tuh_msc_complete_cb_t)(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data); //--------------------------------------------------------------------+ // Application API @@ -66,33 +73,33 @@ uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun); // Perform a full SCSI command (cbw, data, csw) in non-blocking manner. // Complete callback is invoked when SCSI op is complete. // return true if success, false if there is already pending operation. -bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb); +bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg); // Perform SCSI Inquiry command // Complete callback is invoked when SCSI op is complete. -bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb); +bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg); // Perform SCSI Test Unit Ready command // Complete callback is invoked when SCSI op is complete. -bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb); +bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb, uintptr_t arg); // Perform SCSI Request Sense 10 command // Complete callback is invoked when SCSI op is complete. -bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_msc_complete_cb_t complete_cb); +bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_msc_complete_cb_t complete_cb, uintptr_t arg); // Perform SCSI Read 10 command. Read n blocks starting from LBA to buffer // Complete callback is invoked when SCSI op is complete. -bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb); +bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg); // Perform SCSI Write 10 command. Write n blocks starting from LBA to device // Complete callback is invoked when SCSI op is complete. -bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb); +bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg); // Perform SCSI Read Capacity 10 command // Complete callback is invoked when SCSI op is complete. // Note: during enumeration, host stack already carried out this request. Application can retrieve capacity by // simply call tuh_msc_get_block_count() and tuh_msc_get_block_size() -bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb); +bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg); //------------- Application Callback -------------// -- cgit v1.3.1 From 9825fbe9ac69cea94942361ac47080b7f5a0a1cd Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Wed, 23 Nov 2022 13:12:31 -0800 Subject: Fix RP2040 Issue 1721 --- src/portable/raspberrypi/rp2040/rp2040_usb.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index 25c013bd2..d7895175e 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -155,7 +155,9 @@ static void __tusb_irq_path_func(_hw_endpoint_start_next_buffer)(struct hw_endpo // For now: skip double buffered for Device mode, OUT endpoint since // host could send < 64 bytes and cause short packet on buffer0 // NOTE this could happen to Host mode IN endpoint - bool const force_single = !(usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && !tu_edpt_dir(ep->ep_addr); + // Also, Host mode interrupt endpoint hardware is only single buffered + bool const force_single = (!(usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && !tu_edpt_dir(ep->ep_addr)) || + ((usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && tu_edpt_number(ep->ep_addr) != 0); if(ep->remaining_len && !force_single) { -- cgit v1.3.1 From b2a3f33046fe736557ad1a4bc9c0da76e47e68f3 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 28 Nov 2022 23:22:10 +0700 Subject: Retry a few times with transfers in enumeration since device can be unstable when starting up --- src/common/tusb_types.h | 2 +- src/host/usbh.c | 24 +++++++++++++++++++----- src/host/usbh.h | 12 ++++++++---- 3 files changed, 28 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index e11f08dd1..1bfa7c7d1 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -225,7 +225,7 @@ enum { typedef enum { - XFER_RESULT_SUCCESS, + XFER_RESULT_SUCCESS = 0, XFER_RESULT_FAILED, XFER_RESULT_STALLED, XFER_RESULT_TIMEOUT, diff --git a/src/host/usbh.c b/src/host/usbh.c index 9d618db92..a5abac843 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -620,9 +620,7 @@ static void _xfer_complete(uint8_t daddr, xfer_result_t result) .user_data = _ctrl_xfer.user_data }; - usbh_lock(); - _ctrl_xfer.stage = CONTROL_STAGE_IDLE; - usbh_unlock(); + _set_control_xfer_stage(CONTROL_STAGE_IDLE); if (xfer_temp.complete_cb) { @@ -1182,12 +1180,28 @@ static void enum_full_complete(void); // process device enumeration static void process_enumeration(tuh_xfer_t* xfer) { + // Retry a few times with transfers in enumeration since device can be unstable when starting up + enum { + ATTEMPT_COUNT_MAX = 3, + ATTEMPT_DELAY_MS = 10 + }; + static uint8_t failed_count = 0; + if (XFER_RESULT_SUCCESS != xfer->result) { - // stop enumeration, maybe we could retry this - enum_full_complete(); + // retry if not reaching max attempt + if ( failed_count < ATTEMPT_COUNT_MAX ) + { + failed_count++; + osal_task_delay(ATTEMPT_DELAY_MS); // delay a bit + TU_ASSERT(tuh_control_xfer(xfer), ); + }else + { + enum_full_complete(); + } return; } + failed_count = 0; uint8_t const daddr = xfer->daddr; uintptr_t const state = xfer->user_data; diff --git a/src/host/usbh.h b/src/host/usbh.h index 1a26a69b4..37de7093c 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -51,14 +51,15 @@ struct tuh_xfer_s { uint8_t daddr; uint8_t ep_addr; - + uint8_t TU_RESERVED; // reserved xfer_result_t result; + uint32_t actual_len; // excluding setup packet union { tusb_control_request_t const* setup; // setup packet pointer if control transfer - uint32_t buflen; // expected length if not control transfer (not available in callback) + uint32_t buflen; // expected length if not control transfer (not available in callback) }; uint8_t* buffer; // not available in callback if not control transfer @@ -80,10 +81,13 @@ enum //TU_ATTR_WEAK uint8_t tuh_attach_cb (tusb_desc_device_t const *desc_device); -// Invoked when device is mounted (configured) +// Invoked when a device is mounted (configured) TU_ATTR_WEAK void tuh_mount_cb (uint8_t daddr); -/// Invoked when device is unmounted (bus reset/unplugged) +// Invoked when a device failed to mount during enumeration process +// TU_ATTR_WEAK void tuh_mount_failed_cb (uint8_t daddr); + +/// Invoked when a device is unmounted (detached) TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr); //--------------------------------------------------------------------+ -- cgit v1.3.1 From be6f6f2c99dde762a70c1c3206e75f5765039bf1 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 28 Nov 2022 23:43:52 +0700 Subject: increase delay between attempts to 100ms --- src/host/usbh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index a5abac843..d97b160c9 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1183,7 +1183,7 @@ static void process_enumeration(tuh_xfer_t* xfer) // Retry a few times with transfers in enumeration since device can be unstable when starting up enum { ATTEMPT_COUNT_MAX = 3, - ATTEMPT_DELAY_MS = 10 + ATTEMPT_DELAY_MS = 100 }; static uint8_t failed_count = 0; -- cgit v1.3.1 From 1fce76ad472fe1936eedea0688960c76bd42fd40 Mon Sep 17 00:00:00 2001 From: Gordon McNab Date: Mon, 28 Nov 2022 17:41:00 +0000 Subject: Fix issue with the CDC SetLineCoding request The SetLineCoding would fail as host would send the SETUP OUT phase before tinyUSB had setup a transaction for it. ft9xx port would ignore the transfer since there was no valid transaction setup for it. One SETUP data phase packet is cached now. --- .../device/cdc_dual_ports/src/usb_descriptors.c | 2 +- hw/bsp/brtmm90x/family.c | 17 ++++- hw/bsp/brtmm90x/family.mk | 10 +-- hw/mcu/bridgetek/ft9xx/ft90x-sdk | 2 +- src/portable/bridgetek/ft9xx/dcd_ft9xx.c | 82 +++++++++++++++++----- 5 files changed, 87 insertions(+), 26 deletions(-) (limited to 'src') diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c index cda1b63b6..9f212c78f 100644 --- a/examples/device/cdc_dual_ports/src/usb_descriptors.c +++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c @@ -97,7 +97,7 @@ enum #define EPNUM_CDC_1_OUT 0x05 #define EPNUM_CDC_1_IN 0x85 -#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X +#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X || CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_CDC_0_NOTIF 0x81 diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c index 6b3c1f56c..77a03e909 100644 --- a/hw/bsp/brtmm90x/family.c +++ b/hw/bsp/brtmm90x/family.c @@ -27,8 +27,8 @@ #include "bsp/board.h" #include "board.h" -#include #include +#include #if CFG_TUD_ENABLED int8_t board_ft90x_vbus(void); // Board specific implementation of VBUS detection for USB device. @@ -213,3 +213,18 @@ uint32_t board_millis(void) return safe_ms; } + +// Restart the program +// Called in the event of a watchdog timeout +void chip_reboot(void) +{ + // SOFT reset + __asm__("call 0"); + #if 0 + // HARD reset + // Initiates data transfer from Flash Memory to Data Memory (DBG_CMDF2D3) + // followed by a system reboot + dbg_memory_copy(0xfe, 0, 0, 255); +#endif +} + diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk index 3933f15cc..a476cfc06 100644 --- a/hw/bsp/brtmm90x/family.mk +++ b/hw/bsp/brtmm90x/family.mk @@ -21,7 +21,7 @@ endif # Add include files which are within the TinyUSB directory structure. INC += \ - $(TOP)/$(BOARD_PATH) + $(TOP)/$(BOARD_PATH) # Add required C Compiler flags for FT90X. CFLAGS += \ @@ -30,14 +30,14 @@ CFLAGS += \ -fvar-tracking-assignments \ -fmessage-length=0 \ -ffunction-sections \ - -DCFG_TUSB_MCU=OPT_MCU_FT90X + -DCFG_TUSB_MCU=OPT_MCU_FT90X + +# Maximum USB device speed supported by the board +CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED # lwip/src/core/raw.c:334:43: error: declaration of 'recv' shadows a global declaration CFLAGS += -Wno-error=shadow -# Add include files outside the TinyUSB structure that are added manually. -CFLAGS += -I"$(FT9XX_SDK)/include" - # Set Linker flags. LD_FILE = hw/mcu/bridgetek/ft9xx/scripts/ldscript.ld LDFLAGS += $(addprefix -L,$(LDINC)) \ diff --git a/hw/mcu/bridgetek/ft9xx/ft90x-sdk b/hw/mcu/bridgetek/ft9xx/ft90x-sdk index c810d1312..0ea80ceaf 160000 --- a/hw/mcu/bridgetek/ft9xx/ft90x-sdk +++ b/hw/mcu/bridgetek/ft9xx/ft90x-sdk @@ -1 +1 @@ -Subproject commit c810d1312ded923c3c2ed9035c97bd0db4f35b5f +Subproject commit 0ea80ceafdf32e4e496cacc94178417e2ef4bf9c diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c index 2445593fe..080d633fa 100644 --- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c +++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c @@ -38,9 +38,6 @@ #include #include -#include "board.h" -#include "bsp/board.h" - #define USBD_USE_STREAMS #include "device/dcd.h" @@ -53,14 +50,20 @@ extern int8_t board_ft90x_vbus(void); // Static array to store an incoming SETUP request for processing by tinyusb. +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _ft90x_setup_packet[8]; +// Static array to store one SETUP DATA packet until required by dcd_edpt_xfer. +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN +static uint8_t _ft90x_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE]; +static uint8_t _ft90x_ctrl_buf_complete; + struct ft90x_xfer_state { volatile uint8_t valid; // Transfer is pending and total_size, remain_size, and buff_ptr are valid. - volatile int16_t total_size; // Total transfer size in bytes for this transfer. - volatile int16_t remain_size; // Total remaining in transfer. - volatile uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to. + int16_t total_size; // Total transfer size in bytes for this transfer. + int16_t remain_size; // Total remaining in transfer. + uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to. uint8_t type; // Endpoint type. Of type USBD_ENDPOINT_TYPE from endpoint descriptor. uint8_t dir; // Endpoint direction. TUSB_DIR_OUT or TUSB_DIR_IN. For control endpoint this is the current direction. @@ -766,13 +769,13 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) USBD_EP_CR_REG(USBD_EP_0) = (ep_reg_size << BIT_USBD_EP0_MAX_SIZE); } + CRITICAL_SECTION_BEGIN // Store the endpoint characteristics for later reference. ep_xfer[ep_number].dir = ep_dir; ep_xfer[ep_number].type = ep_type; ep_xfer[ep_number].size = ep_size; ep_xfer[ep_number].buff_size = ep_buff_size; - CRITICAL_SECTION_BEGIN // Clear register transaction continuation and signalling state. ep_xfer[ep_number].valid = 0; ep_xfer[ep_number].buff_ptr = NULL; @@ -809,12 +812,9 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to // Transfer currently in progress. if (ep_xfer[ep_number].valid == 0) { - status = true; - ep_xfer[ep_number].total_size = total_bytes; ep_xfer[ep_number].remain_size = total_bytes; ep_xfer[ep_number].buff_ptr = buffer; - ep_xfer[ep_number].valid = 1; if (ep_number == USBD_EP_0) { @@ -835,10 +835,33 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to ep_xfer[ep_number].buff_ptr += xfer_bytes; ep_xfer[ep_number].remain_size -= xfer_bytes; + + // Tell the interrupt handler to signal dcd_event_xfer_complete on completion. + ep_xfer[ep_number].valid = 1; } + else + { + // For OUT transfers on the control endpoint. + // The host may already have performed the first data transfer after the SETUP packet + // before the transfer is setup for it. + if ((ep_number == USBD_EP_0) && (_ft90x_ctrl_buf_complete)) + { + // Pull the received data packet from the packet cache and complete the transfer + // immediately. + memcpy(buffer, _ft90x_ctrl_buf, _ft90x_ctrl_buf_complete); + dcd_event_xfer_complete(BOARD_TUD_RHPORT, TUSB_DIR_OUT, _ft90x_ctrl_buf_complete, XFER_RESULT_SUCCESS, false); + } + else + { + // Tell the interrupt handler to wait for the packet to be received. + ep_xfer[ep_number].valid = 1; + } + } + status = true; } + CRITICAL_SECTION_END - + return status; } @@ -899,7 +922,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) void _ft90x_usbd_ISR(void) { - tud_int_handler(BOARD_TUD_RHPORT); // Resolves to dcd_int_handler(). + dcd_int_handler(BOARD_TUD_RHPORT); } void dcd_int_handler(uint8_t rhport) @@ -962,7 +985,6 @@ void dcd_int_handler(uint8_t rhport) { // Clear interrupt register. USBD_REG(epif) = MASK_USBD_EPIF_EP0IRQ; - // Test for an incoming SETUP request on the control endpoint. if (USBD_EP_SR_REG(USBD_EP_0) & MASK_USBD_EP0SR_SETUP) { @@ -976,7 +998,7 @@ void dcd_int_handler(uint8_t rhport) USBD_EP_SR_REG(USBD_EP_0) = MASK_USBD_EP0SR_STALL; } - // Host has sent a SETUP packet. Recieve this into the setup packet store. + // Host has sent a SETUP packet. Recieve this into the SETUP packet store. _ft90x_dusb_out(USBD_EP_0, (uint8_t *)_ft90x_setup_packet, sizeof(USB_device_request)); // Send the packet to tinyusb. @@ -985,6 +1007,9 @@ void dcd_int_handler(uint8_t rhport) // Clear the interrupt that signals a SETUP packet is received. USBD_EP_SR_REG(USBD_EP_0) = (MASK_USBD_EP0SR_SETUP); + // Invalidate cache packet. + _ft90x_ctrl_buf_complete = 0; + // Allow new transfers on the control endpoint. ep_xfer[USBD_EP_0].valid = 0; return; @@ -998,15 +1023,36 @@ void dcd_int_handler(uint8_t rhport) // Transfer incoming data from an OUT packet to the buffer supplied. if (ep_xfer[USBD_EP_0].dir == TUSB_DIR_OUT) - { - xfer_bytes = _ft90x_edpt_xfer_out(USBD_EP_0, (uint8_t *)ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes); + { + xfer_bytes = _ft90x_edpt_xfer_out(USBD_EP_0, ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes); } // Now signal completion of data packet. dcd_event_xfer_complete(BOARD_TUD_RHPORT, (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0), xfer_bytes, XFER_RESULT_SUCCESS, true); + // Invalidate cache packet. + _ft90x_ctrl_buf_complete = 0; + // Allow new transfers on the control endpoint. ep_xfer[USBD_EP_0].valid = 0; } + else + { + // We have received a data packet on the control endpoint without a transfer + // being initialised. This can be because the host has sent this packet before + // a new transfer has been initiated on the control endpoint. + // We will cache upto the maximum packet size for the control endpoint and + // use it later in dcd_edpt_xfer. + xfer_bytes = CFG_TUD_ENDPOINT0_SIZE; + + // Transfer incoming data from an OUT packet to the cache packet. + xfer_bytes = _ft90x_edpt_xfer_out(USBD_EP_0, _ft90x_ctrl_buf, xfer_bytes); + + // Set the size of the cache packet. + _ft90x_ctrl_buf_complete = xfer_bytes; + } + + // Clear the interrupt that signals a SETUP DATA packet is received. + USBD_EP_SR_REG(USBD_EP_0) = (MASK_USBD_EP0SR_OPRDY); } } else // !(epif & MASK_USBD_EPIF_EP0IRQ) @@ -1035,7 +1081,7 @@ void dcd_int_handler(uint8_t rhport) if (ep_xfer[ep_number].dir == TUSB_DIR_OUT) { xfer_bytes = _ft90x_edpt_xfer_out(ep_number, - (uint8_t *)ep_xfer[ep_number].buff_ptr, + ep_xfer[ep_number].buff_ptr, (uint16_t)ep_xfer[ep_number].remain_size); ep_xfer[ep_number].buff_ptr += xfer_bytes; @@ -1047,7 +1093,7 @@ void dcd_int_handler(uint8_t rhport) if (ep_xfer[ep_number].remain_size > 0) { xfer_bytes = _ft90x_edpt_xfer_in(ep_number, - (uint8_t *)ep_xfer[ep_number].buff_ptr, + ep_xfer[ep_number].buff_ptr, (uint16_t)ep_xfer[ep_number].remain_size); ep_xfer[ep_number].buff_ptr += xfer_bytes; -- cgit v1.3.1 From 7d8d3eca730552355b5ad442f58b5a6b070d4d03 Mon Sep 17 00:00:00 2001 From: Gordon McNab Date: Tue, 29 Nov 2022 18:49:23 +0000 Subject: Fix transfers issues with FT9xx Correct USB FIFO use for setup data phases (OUT transfers). We cannot stop traffic on the control endpoint so we set a flag and pull data from host when tinyUSB requests it from the USB FIFO. Extend this for all endpoints although currently not required. Rename all instances of ft90x which can apply to ft93x as ft9xx. Add support for the cdc_dual_ports example for ft9xx. Add LED pin definition for board LED in a simple to access place on the Bridgetek MM900EVx boards. --- .../device/cdc_dual_ports/src/usb_descriptors.c | 12 +- hw/bsp/brtmm90x/boards/mm900evxb/board.h | 18 +- hw/bsp/brtmm90x/family.c | 22 +- hw/bsp/brtmm90x/family.mk | 6 +- src/portable/bridgetek/ft9xx/dcd_ft9xx.c | 225 ++++++++++++--------- 5 files changed, 167 insertions(+), 116 deletions(-) (limited to 'src') diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c index 9f212c78f..5a8dea553 100644 --- a/examples/device/cdc_dual_ports/src/usb_descriptors.c +++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c @@ -97,7 +97,7 @@ enum #define EPNUM_CDC_1_OUT 0x05 #define EPNUM_CDC_1_IN 0x85 -#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X || CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X +#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_CDC_0_NOTIF 0x81 @@ -108,6 +108,16 @@ enum #define EPNUM_CDC_1_OUT 0x05 #define EPNUM_CDC_1_IN 0x86 +#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X + // FT9XX doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_CDC_NOTIF 0x81 + #define EPNUM_CDC_OUT 0x02 + #define EPNUM_CDC_IN 0x83 + + #define EPNUM_MSC_OUT 0x04 + #define EPNUM_MSC_IN 0x85 + #else #define EPNUM_CDC_0_NOTIF 0x81 #define EPNUM_CDC_0_OUT 0x02 diff --git a/hw/bsp/brtmm90x/boards/mm900evxb/board.h b/hw/bsp/brtmm90x/boards/mm900evxb/board.h index 57936fda5..930cb9d33 100644 --- a/hw/bsp/brtmm90x/boards/mm900evxb/board.h +++ b/hw/bsp/brtmm90x/boards/mm900evxb/board.h @@ -27,20 +27,28 @@ #ifndef BOARD_H_ #define BOARD_H_ -// Note: This definition file covers all MM900EV1B, MM900EV2B, and MM900EV3B boards. +// Note: This definition file covers all MM900EV1B, MM900EV2B, MM900EV3B, +// MM900EV-Lite boards. // Each of these boards has an FT900 device. #ifdef __cplusplus extern "C" { #endif -#define GPIO_UART0_TX 48 -#define GPIO_UART0_RX 49 -#define GPIO_ETH_LED0 61 -#define GPIO_ETH_LED1 62 +// UART is on connector CN1. +#define GPIO_UART0_TX 48 // Pin 4 of CN1. +#define GPIO_UART0_RX 49 // Pin 6 of CN1. + +// LED is connected to pins 4 (signal) and 2 (GND) of CN2. +#define GPIO_LED 36 + +// Remote wakeup is wired to pin 40 of CN1. #define GPIO_REMOTE_WAKEUP_PIN 18 + +// USB VBus signal is connected directly to the FT900. #define USBD_VBUS_DTC_PIN 3 +// Enable the Remote Wakeup signalling. #define GPIO_REMOTE_WAKEUP #ifdef __cplusplus diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c index 77a03e909..cc28cb69b 100644 --- a/hw/bsp/brtmm90x/family.c +++ b/hw/bsp/brtmm90x/family.c @@ -31,8 +31,8 @@ #include #if CFG_TUD_ENABLED -int8_t board_ft90x_vbus(void); // Board specific implementation of VBUS detection for USB device. -extern void ft90x_usbd_pm_ISR(uint16_t pmcfg); // Interrupt handler for USB device power management +int8_t board_ft9xx_vbus(void); // Board specific implementation of VBUS detection for USB device. +extern void ft9xx_usbd_pm_ISR(uint16_t pmcfg); // Interrupt handler for USB device power management #endif #ifdef GPIO_REMOTE_WAKEUP @@ -64,12 +64,10 @@ void board_init(void) // Use sizeof to avoid pulling in strlen unnecessarily. board_uart_write(WELCOME_MSG, sizeof(WELCOME_MSG)); -#if 0 - // Ethernet LEDs - gpio_function(GPIO_ETH_LED0, pad_gpio4); /* ETH LED0 */ - gpio_dir(GPIO_ETH_LED0, pad_dir_open_drain); - gpio_function(GPIO_ETH_LED1, pad_gpio5); /* ETH LED1 */ - gpio_dir(GPIO_ETH_LED1, pad_dir_output); +#ifdef GPIO_LED + gpio_function(GPIO_LED, pad_func_0); /* CN2 connector pin 4 */ + gpio_idrive(GPIO_LED, pad_drive_12mA); + gpio_dir(GPIO_LED, pad_dir_output); #endif sys_enable(sys_device_timer_wdt); @@ -153,14 +151,14 @@ void board_pm_ISR(void) ) { #if CFG_TUD_ENABLED - ft90x_usbd_pm_ISR(pmcfg); + ft9xx_usbd_pm_ISR(pmcfg); #endif } #endif } #if CFG_TUD_ENABLED -int8_t board_ft90x_vbus(void) +int8_t board_ft9xx_vbus(void) { return gpio_read(USBD_VBUS_DTC_PIN); } @@ -173,7 +171,11 @@ int8_t board_ft90x_vbus(void) // Turn LED on or off void board_led_write(bool state) { +#if 0 gpio_write(GPIO_ETH_LED0, state); +#else + gpio_write(GPIO_LED, state); +#endif } // Get the current state of button diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk index a476cfc06..f45e27cb5 100644 --- a/hw/bsp/brtmm90x/family.mk +++ b/hw/bsp/brtmm90x/family.mk @@ -3,8 +3,8 @@ CROSS_COMPILE = ft32-elf- SKIP_NANOLIB = 1 # Set to use FT90X prebuilt libraries. -FT90X_PREBUILT_LIBS = 0 -ifeq ($(FT90X_PREBUILT_LIBS),1) +FT9XX_PREBUILT_LIBS = 0 +ifeq ($(FT9XX_PREBUILT_LIBS),1) # If the FT90X toolchain is installed on Windows systems then the SDK # include files and prebuilt libraries are at: %FT90X_TOOLCHAIN%/hardware FT9XX_SDK = $(FT90X_TOOLCHAIN)/hardware @@ -48,7 +48,7 @@ LDFLAGS += $(addprefix -L,$(LDINC)) \ SRC_C += src/portable/bridgetek/ft9xx/dcd_ft9xx.c # Linker library. -ifneq ($(FT90X_PREBUILT_LIBS),1) +ifneq ($(FT9XX_PREBUILT_LIBS),1) # Optionally add in files from the Bridgetek SDK instead of the prebuilt # library. These are the minimum required. SRC_C += $(FT9XX_SDK)/src/sys.c diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c index 080d633fa..50f7018db 100644 --- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c +++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c @@ -47,20 +47,17 @@ //--------------------------------------------------------------------+ // Board code will determine the state of VBUS from USB host. -extern int8_t board_ft90x_vbus(void); +extern int8_t board_ft9xx_vbus(void); // Static array to store an incoming SETUP request for processing by tinyusb. CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN -static uint8_t _ft90x_setup_packet[8]; +static uint8_t _ft9xx_setup_packet[8]; -// Static array to store one SETUP DATA packet until required by dcd_edpt_xfer. -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN -static uint8_t _ft90x_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE]; -static uint8_t _ft90x_ctrl_buf_complete; - -struct ft90x_xfer_state +struct ft9xx_xfer_state { + volatile uint8_t ready; // OUT Transfer has been received and waiting for transfer. volatile uint8_t valid; // Transfer is pending and total_size, remain_size, and buff_ptr are valid. + int16_t total_size; // Total transfer size in bytes for this transfer. int16_t remain_size; // Total remaining in transfer. uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to. @@ -71,24 +68,24 @@ struct ft90x_xfer_state uint16_t size; // Max packet size for endpoint from endpoint descriptor. }; // Endpoint description array for each endpoint. -static struct ft90x_xfer_state ep_xfer[USBD_MAX_ENDPOINT_COUNT]; +static struct ft9xx_xfer_state ep_xfer[USBD_MAX_ENDPOINT_COUNT]; // USB speed. static tusb_speed_t _speed; // Interrupt handlers. -void _ft90x_usbd_ISR(void); // Interrupt handler for USB device. -void ft90x_usbd_pm_ISR(void); // Interrupt handler for USB device for power management (called by board). +void _ft9xx_usbd_ISR(void); // Interrupt handler for USB device. +void ft9xx_usbd_pm_ISR(void); // Interrupt handler for USB device for power management (called by board). // Internal functions forward declarations. -static uint16_t _ft90x_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes); -static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes); -static void _ft90x_reset_edpts(void); -static inline void _ft90x_phy_enable(bool en); -static void _ft90x_usb_speed(void); -static void _dcd_ft90x_attach(void); -static void _dcd_ft90x_detach(void) __attribute__((unused)); -static uint16_t _ft90x_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length); -static uint16_t _ft90x_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length); +static uint16_t _ft9xx_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes); +static uint16_t _ft9xx_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes); +static void _ft9xx_reset_edpts(void); +static inline void _ft9xx_phy_enable(bool en); +static void _ft9xx_usb_speed(void); +static void _dcd_ft9xx_attach(void); +static void _dcd_ft9xx_detach(void) __attribute__((unused)); +static uint16_t _ft9xx_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length); +static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length); // Internal functions. @@ -96,7 +93,7 @@ static uint16_t _ft90x_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len // This can be up-to the maximum packet size of the endpoint. // Continuation of a transfer beyond the maximum packet size is performed // by the interrupt handler. -static uint16_t _ft90x_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes) +static uint16_t _ft9xx_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes) { //Note: this is called from only the interrupt handler when an OUT transfer is called. uint16_t ep_size = ep_xfer[ep_number].size; @@ -111,7 +108,7 @@ static uint16_t _ft90x_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_ //; // Send the first packet of max packet size - xfer_bytes = _ft90x_dusb_out(ep_number, (uint8_t *)buffer, xfer_bytes); + xfer_bytes = _ft9xx_dusb_out(ep_number, (uint8_t *)buffer, xfer_bytes); if (ep_number == USBD_EP_0) { // Set flags to indicate data ready. @@ -129,7 +126,7 @@ static uint16_t _ft90x_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_ // This can be up-to the maximum packet size of the endpoint. // Continuation of a transfer beyond the maximum packet size is performed // by the interrupt handler. -static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes) +static uint16_t _ft9xx_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes) { //Note: this may be called from the interrupt handler or from normal code. uint8_t end = 0; @@ -167,7 +164,7 @@ static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t } - xfer_bytes = _ft90x_dusb_in(ep_number, (uint8_t *)buffer, xfer_bytes); + xfer_bytes = _ft9xx_dusb_in(ep_number, (uint8_t *)buffer, xfer_bytes); if (ep_number == USBD_EP_0) { @@ -193,13 +190,13 @@ static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t // Reset all non-control endpoints to a default state. // Control endpoint is always enabled and ready. All others disabled. -static void _ft90x_reset_edpts(void) +static void _ft9xx_reset_edpts(void) { // Disable all endpoints and remove configuration values. for (int i = 1; i < USBD_MAX_ENDPOINT_COUNT; i++) { // Clear settings. - tu_memclr(&ep_xfer[i], sizeof(struct ft90x_xfer_state)); + tu_memclr(&ep_xfer[i], sizeof(struct ft9xx_xfer_state)); // Disable hardware. USBD_EP_CR_REG(i) = 0; } @@ -209,7 +206,7 @@ static void _ft90x_reset_edpts(void) } // Enable or disable the USB PHY. -static inline void _ft90x_phy_enable(bool en) +static inline void _ft9xx_phy_enable(bool en) { if (en) SYS->PMCFG_L |= MASK_SYS_PMCFG_DEV_PHY_EN; @@ -218,7 +215,7 @@ static inline void _ft90x_phy_enable(bool en) } // Safely connect to the USB. -static void _dcd_ft90x_attach(void) +static void _dcd_ft9xx_attach(void) { uint8_t reg; @@ -274,7 +271,7 @@ static void _dcd_ft90x_attach(void) } // Gracefully disconnect from the USB. -static void _dcd_ft90x_detach(void) +static void _dcd_ft9xx_detach(void) { // Disable device connect/disconnect/host reset detection. SYS->PMCFG_L = SYS->PMCFG_L & (~MASK_SYS_PMCFG_DEV_DETECT_EN); @@ -316,7 +313,7 @@ static void _dcd_ft90x_detach(void) // Determine the speed of the USB to which we are connected. // Set the speed of the PHY accordingly. // High speed can be disabled through CFG_TUSB_RHPORT0_MODE or CFG_TUD_MAX_SPEED settings. -static void _ft90x_usb_speed(void) +static void _ft9xx_usb_speed(void) { uint8_t fctrl_val; @@ -379,7 +376,7 @@ static void _ft90x_usb_speed(void) // If streaming is disabled then it will send each byte of the buffer in turn // to the FIFO. The is no reason to not stream. // The total number of bytes sent to the FIFO is returned. -static uint16_t _ft90x_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length) +static uint16_t _ft9xx_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length) { uint16_t bytes_read = 0; uint16_t buff_size = length; @@ -436,7 +433,7 @@ static uint16_t _ft90x_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_ // If streaming is disabled then it will receive each byte from the FIFO in turn // to the buffer. The is no reason to not stream. // The total number of bytes received from the FIFO is returned. -static uint16_t _ft90x_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length) +static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length) { #ifdef USBD_USE_STREAMS volatile uint8_t *data_reg; @@ -514,11 +511,11 @@ static uint16_t _ft90x_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len // Initialize controller to device mode void dcd_init(uint8_t rhport) { - TU_LOG2("FT90x initialisation\r\n"); + TU_LOG2("FT9xx initialisation\r\n"); - _dcd_ft90x_attach(); + _dcd_ft9xx_attach(); - interrupt_attach(interrupt_usb_device, (int8_t)interrupt_usb_device, _ft90x_usbd_ISR); + interrupt_attach(interrupt_usb_device, (int8_t)interrupt_usb_device, _ft9xx_usbd_ISR); dcd_connect(rhport); } @@ -527,7 +524,7 @@ void dcd_init(uint8_t rhport) void dcd_int_enable(uint8_t rhport) { (void)rhport; - TU_LOG3("FT90x int enable\r\n"); + TU_LOG3("FT9xx int enable\r\n"); // Peripheral devices interrupt enable. interrupt_enable_globally(); @@ -537,7 +534,7 @@ void dcd_int_enable(uint8_t rhport) void dcd_int_disable(uint8_t rhport) { (void)rhport; - TU_LOG3("FT90x int disable\r\n"); + TU_LOG3("FT9xx int disable\r\n"); // Peripheral devices interrupt disable. interrupt_disable_globally(); @@ -603,18 +600,18 @@ void dcd_remote_wakeup(uint8_t rhport) void dcd_connect(uint8_t rhport) { (void)rhport; - TU_LOG2("FT90x connect\r\n"); + TU_LOG2("FT9xx connect\r\n"); CRITICAL_SECTION_BEGIN // Is device connected? - if (board_ft90x_vbus()) + if (board_ft9xx_vbus()) { // Clear/disable address register. USBD_REG(faddr) = 0; - _ft90x_phy_enable(true); + _ft9xx_phy_enable(true); // Determine bus speed and signal speed to tusb. - _ft90x_usb_speed(); + _ft9xx_usb_speed(); } // Setup the control endpoint only. @@ -639,17 +636,17 @@ void dcd_connect(uint8_t rhport) USBD_REG(epie) = (MASK_USBD_EPIE_EP0IE); // Restore default endpoint state. - _ft90x_reset_edpts(); + _ft9xx_reset_edpts(); } // Disconnect by disabling internal pull-up resistor on D+/D- void dcd_disconnect(uint8_t rhport) { (void)rhport; - TU_LOG2("FT90x disconnect\r\n"); + TU_LOG2("FT9xx disconnect\r\n"); // Disable the USB PHY. - _ft90x_phy_enable(false); + _ft9xx_phy_enable(false); } void dcd_sof_enable(uint8_t rhport, bool en) @@ -677,12 +674,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) uint8_t ep_reg_data = 0; int16_t total_ram; - TU_LOG2("FT90x endpoint open %d %c\r\n", ep_number, ep_dir?'I':'O'); + TU_LOG2("FT9xx endpoint open %d %c\r\n", ep_number, ep_dir?'I':'O'); // Check that the requested endpoint number is allowable. if (ep_number >= USBD_MAX_ENDPOINT_COUNT) { - TU_LOG1("FT90x endpoint not valid: requested %d max %d\r\n", ep_number, USBD_MAX_ENDPOINT_COUNT); + TU_LOG1("FT9xx endpoint not valid: requested %d max %d\r\n", ep_number, USBD_MAX_ENDPOINT_COUNT); return false; } @@ -694,7 +691,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) } if (ep_reg_size > USBD_EP_MAX_SIZE_1024) { - TU_LOG1("FT90x endpoint size not valid: requested %d max 1024\r\n", ep_size); + TU_LOG1("FT9xx endpoint size not valid: requested %d max 1024\r\n", ep_size); return false; } // Calculate actual amount of buffer RAM used by this endpoint. This may be more than the @@ -709,9 +706,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) if (ep_xfer[ep_number].type != USBD_EP_TYPE_DISABLED) { // This could be because an endpoint has been assigned with the same number. - // On FT90x, IN and OUT endpoints may not have the same number. e.g. There + // On FT9xx, IN and OUT endpoints may not have the same number. e.g. There // cannot been an 0x81 and 0x01 endpoint. - TU_LOG1("FT90x endpoint %d already assigned\r\n", ep_number); + TU_LOG1("FT9xx endpoint %d already assigned\r\n", ep_number); return false; } @@ -723,7 +720,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) else total_ram = USBD_RAMTOTAL_OUT; // Work out how much has been allocated to existing endpoints. - // The total RAM allocated shoudl alsyes be a positive number as this + // The total RAM allocated should always be a positive number as this // algorithm should not let it go below zero. for (int i = 1; i < USBD_MAX_ENDPOINT_COUNT; i++) { @@ -735,14 +732,19 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) } } } - // The control endpoint is taken into account as well. - total_ram -= ep_xfer[0].buff_size; + + if (sys_check_ft900_revB()) + { + // The control endpoint is taken into account as well on RevB silicon. + total_ram -= ep_xfer[0].buff_size; + } + // Make sure we have enough space. The corner case is having zero bytes // free which means that total_ram must be signed as zero bytes free is // allowable. if (total_ram < ep_buff_size) { - TU_LOG1("FT90x insufficient buffer RAM for endpoint %d\r\n", ep_number); + TU_LOG1("FT9xx insufficient buffer RAM for endpoint %d\r\n", ep_number); return false; } @@ -761,7 +763,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) //ep_reg_data |= MASK_USBD_EPxCR_DB; // Set the control endpoint for this endpoint. USBD_EP_CR_REG(ep_number) = ep_reg_data; - TU_LOG2("FT90x endpoint setting %x\r\n", ep_reg_data); + TU_LOG2("FT9xx endpoint setting %x\r\n", ep_reg_data); } else { @@ -777,6 +779,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) ep_xfer[ep_number].buff_size = ep_buff_size; // Clear register transaction continuation and signalling state. + ep_xfer[ep_number].ready = 0; ep_xfer[ep_number].valid = 0; ep_xfer[ep_number].buff_ptr = NULL; ep_xfer[ep_number].total_size = 0; @@ -791,7 +794,7 @@ void dcd_edpt_close_all(uint8_t rhport) { (void)rhport; // Reset the endpoint configurations. - _ft90x_reset_edpts(); + _ft9xx_reset_edpts(); } // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack @@ -799,7 +802,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to { (void)rhport; uint8_t ep_number = tu_edpt_number(ep_addr); - uint8_t dir = tu_edpt_dir(ep_addr); + uint8_t ep_dir = tu_edpt_dir(ep_addr); uint16_t xfer_bytes; bool status = false; @@ -809,6 +812,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to // ep_xfer is used to tell the interrupt handler what to do. // ep_xfer can be used at interrupt level to continue transfers. CRITICAL_SECTION_BEGIN + // Transfer currently in progress. if (ep_xfer[ep_number].valid == 0) { @@ -818,7 +822,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to if (ep_number == USBD_EP_0) { - ep_xfer[USBD_EP_0].dir = dir; + ep_xfer[USBD_EP_0].dir = ep_dir; } else { @@ -827,11 +831,11 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to USBD_REG(epie) = USBD_REG(epie) | (1 << ep_number); } - if (dir == TUSB_DIR_IN) + if (ep_dir == TUSB_DIR_IN) { // For IN transfers send the first packet as a starter. Interrupt handler to complete // this if it is larger than one packet. - xfer_bytes = _ft90x_edpt_xfer_in(ep_number, buffer, total_bytes); + xfer_bytes = _ft9xx_edpt_xfer_in(ep_number, buffer, total_bytes); ep_xfer[ep_number].buff_ptr += xfer_bytes; ep_xfer[ep_number].remain_size -= xfer_bytes; @@ -839,26 +843,37 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to // Tell the interrupt handler to signal dcd_event_xfer_complete on completion. ep_xfer[ep_number].valid = 1; } - else + else // (dir == TUSB_DIR_OUT) { // For OUT transfers on the control endpoint. // The host may already have performed the first data transfer after the SETUP packet // before the transfer is setup for it. - if ((ep_number == USBD_EP_0) && (_ft90x_ctrl_buf_complete)) + if (ep_xfer[ep_number].ready) { - // Pull the received data packet from the packet cache and complete the transfer - // immediately. - memcpy(buffer, _ft90x_ctrl_buf, _ft90x_ctrl_buf_complete); - dcd_event_xfer_complete(BOARD_TUD_RHPORT, TUSB_DIR_OUT, _ft90x_ctrl_buf_complete, XFER_RESULT_SUCCESS, false); + // We have received a data packet on the endpoint without a transfer + // being initialised. This can be because the host has sent this packet before + // a new transfer has been initiated on the endpoint. + // We will now stream the data from the FIFO. + ep_xfer[ep_number].ready = 0; + + // Transfer incoming data from an OUT packet to the buffer. + xfer_bytes = _ft9xx_edpt_xfer_out(ep_number, buffer, total_bytes); + // Report completion of the transfer. + dcd_event_xfer_complete(BOARD_TUD_RHPORT, ep_number /*| TUSB_DIR_OUT_MASK */, xfer_bytes, XFER_RESULT_SUCCESS, false); } else { - // Tell the interrupt handler to wait for the packet to be received. + // Tell the interrupt handler to wait for the packet to be received and + // then report the transfer complete with dcd_event_xfer_complete. ep_xfer[ep_number].valid = 1; } } status = true; } + else + { + // Note: should not arrive here. + } CRITICAL_SECTION_END @@ -912,6 +927,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) USBD_EP_SR_REG(ep_number) = MASK_USBD_EPxSR_CLR_TOGGLE; // Allow transfers to restart. + ep_xfer[ep_number].ready = 0; ep_xfer[ep_number].valid = 0; ep_xfer[ep_number].remain_size = 0; CRITICAL_SECTION_END @@ -920,7 +936,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) // Interrupt handling. -void _ft90x_usbd_ISR(void) +void _ft9xx_usbd_ISR(void) { dcd_int_handler(BOARD_TUD_RHPORT); } @@ -959,7 +975,7 @@ void dcd_int_handler(uint8_t rhport) if (cmif & MASK_USBD_CMIF_RSTIRQ) //Handle Reset interrupt { // Reset endpoints to default state. - _ft90x_reset_edpts(); + _ft9xx_reset_edpts(); dcd_event_bus_reset(BOARD_TUD_RHPORT, _speed, true); } if (cmif & MASK_USBD_CMIF_SUSIRQ) //Handle Suspend interrupt @@ -999,18 +1015,18 @@ void dcd_int_handler(uint8_t rhport) } // Host has sent a SETUP packet. Recieve this into the SETUP packet store. - _ft90x_dusb_out(USBD_EP_0, (uint8_t *)_ft90x_setup_packet, sizeof(USB_device_request)); + _ft9xx_dusb_out(USBD_EP_0, (uint8_t *)_ft9xx_setup_packet, sizeof(USB_device_request)); // Send the packet to tinyusb. - dcd_event_setup_received(BOARD_TUD_RHPORT, _ft90x_setup_packet, true); + dcd_event_setup_received(BOARD_TUD_RHPORT, _ft9xx_setup_packet, true); // Clear the interrupt that signals a SETUP packet is received. USBD_EP_SR_REG(USBD_EP_0) = (MASK_USBD_EP0SR_SETUP); - // Invalidate cache packet. - _ft90x_ctrl_buf_complete = 0; + // Any SETUP packet will clear the incoming FIFO. + ep_xfer[USBD_EP_0].ready = 0; - // Allow new transfers on the control endpoint. + // Allow new DATA and ACK transfers on the control endpoint. ep_xfer[USBD_EP_0].valid = 0; return; } @@ -1024,35 +1040,28 @@ void dcd_int_handler(uint8_t rhport) // Transfer incoming data from an OUT packet to the buffer supplied. if (ep_xfer[USBD_EP_0].dir == TUSB_DIR_OUT) { - xfer_bytes = _ft90x_edpt_xfer_out(USBD_EP_0, ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes); + xfer_bytes = _ft9xx_edpt_xfer_out(USBD_EP_0, ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes); } // Now signal completion of data packet. - dcd_event_xfer_complete(BOARD_TUD_RHPORT, (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0), xfer_bytes, XFER_RESULT_SUCCESS, true); + dcd_event_xfer_complete(BOARD_TUD_RHPORT, USBD_EP_0 | (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0), + xfer_bytes, XFER_RESULT_SUCCESS, true); - // Invalidate cache packet. - _ft90x_ctrl_buf_complete = 0; + // Incoming FIFO has been cleared. + ep_xfer[USBD_EP_0].ready = 0; // Allow new transfers on the control endpoint. ep_xfer[USBD_EP_0].valid = 0; } + // No transfer is in flight for EP0. else { // We have received a data packet on the control endpoint without a transfer // being initialised. This can be because the host has sent this packet before // a new transfer has been initiated on the control endpoint. - // We will cache upto the maximum packet size for the control endpoint and - // use it later in dcd_edpt_xfer. - xfer_bytes = CFG_TUD_ENDPOINT0_SIZE; - - // Transfer incoming data from an OUT packet to the cache packet. - xfer_bytes = _ft90x_edpt_xfer_out(USBD_EP_0, _ft90x_ctrl_buf, xfer_bytes); - - // Set the size of the cache packet. - _ft90x_ctrl_buf_complete = xfer_bytes; + // We will record that there is data in the FIFO for dcd_edpt_xfer to obtain + // once the transfer is initiated. + ep_xfer[USBD_EP_0].ready = 1; } - - // Clear the interrupt that signals a SETUP DATA packet is received. - USBD_EP_SR_REG(USBD_EP_0) = (MASK_USBD_EP0SR_OPRDY); } } else // !(epif & MASK_USBD_EPIF_EP0IRQ) @@ -1072,7 +1081,6 @@ void dcd_int_handler(uint8_t rhport) if (ep_xfer[ep_number].valid) { xfer_bytes = 0; - uint8_t ep_dirmask = (ep_xfer[ep_number].dir ? TUSB_DIR_IN_MASK : 0); // Clear interrupt register for this endpoint. USBD_REG(epif) = MASK_USBD_EPIF_IRQ(ep_number); @@ -1080,10 +1088,15 @@ void dcd_int_handler(uint8_t rhport) // Start or continue an OUT transfer. if (ep_xfer[ep_number].dir == TUSB_DIR_OUT) { - xfer_bytes = _ft90x_edpt_xfer_out(ep_number, + xfer_bytes = _ft9xx_edpt_xfer_out(ep_number, ep_xfer[ep_number].buff_ptr, (uint16_t)ep_xfer[ep_number].remain_size); + // Report each OUT packet received to the stack. + dcd_event_xfer_complete(BOARD_TUD_RHPORT, + ep_number /* | TUSB_DIR_OUT_MASK */, + xfer_bytes, XFER_RESULT_SUCCESS, true); + ep_xfer[ep_number].buff_ptr += xfer_bytes; ep_xfer[ep_number].remain_size -= xfer_bytes; } @@ -1092,27 +1105,45 @@ void dcd_int_handler(uint8_t rhport) { if (ep_xfer[ep_number].remain_size > 0) { - xfer_bytes = _ft90x_edpt_xfer_in(ep_number, + xfer_bytes = _ft9xx_edpt_xfer_in(ep_number, ep_xfer[ep_number].buff_ptr, (uint16_t)ep_xfer[ep_number].remain_size); ep_xfer[ep_number].buff_ptr += xfer_bytes; ep_xfer[ep_number].remain_size -= xfer_bytes; } + + if (ep_xfer[ep_number].remain_size == 0) + { + dcd_event_xfer_complete(BOARD_TUD_RHPORT, + ep_number | TUSB_DIR_IN_MASK, + ep_xfer[ep_number].total_size, XFER_RESULT_SUCCESS, true); + } } // When the transfer is complete... if (ep_xfer[ep_number].remain_size == 0) { - // Signal tinyUSB. - dcd_event_xfer_complete(BOARD_TUD_RHPORT, ep_number | ep_dirmask, ep_xfer[ep_number].total_size, XFER_RESULT_SUCCESS, true); - - // Allow new transfers on this endpoint. + // Finish this transfer and allow new transfers on this endpoint. ep_xfer[ep_number].valid = 0; // Disable the interrupt for this endpoint now it is complete. USBD_REG(epie) = USBD_REG(epie) & (~(1 << ep_number)); } + + ep_xfer[ep_number].ready = 0; + } + // No OUT transfer is in flight for this endpoint. + else + { + if (ep_xfer[ep_number].dir == TUSB_DIR_OUT) + { + // We will record that there is data in the FIFO for dcd_edpt_xfer to obtain + // once the transfer is initiated. + // Strictly this should not happen for a non-control endpoint. Interrupts + // are disabled when there are no transfers setup for an endpoint. + ep_xfer[ep_number].ready = 1; + } } } } @@ -1121,7 +1152,7 @@ void dcd_int_handler(uint8_t rhport) // Power management interrupt handler. // This handles USB device related power management interrupts only. -void ft90x_usbd_pm_ISR(void) +void ft9xx_usbd_pm_ISR(void) { uint16_t pmcfg = SYS->PMCFG_H; -- cgit v1.3.1 From d588167a39fd01e5cea718deb1917e74c6a801ab Mon Sep 17 00:00:00 2001 From: pete-pjb Date: Wed, 30 Nov 2022 11:33:24 +0000 Subject: Modify FreeRTOS integration to allow non-static allocation. --- src/osal/osal_freertos.h | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index 52db336f5..a2b0573f8 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -62,12 +62,20 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) //--------------------------------------------------------------------+ // Semaphore API //--------------------------------------------------------------------+ +#if configSUPPORT_STATIC_ALLOCATION == 1 typedef StaticSemaphore_t osal_semaphore_def_t; +#else +typedef SemaphoreHandle_t osal_semaphore_def_t; +#endif typedef SemaphoreHandle_t osal_semaphore_t; TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) { +#if configSUPPORT_STATIC_ALLOCATION == 1 return xSemaphoreCreateBinaryStatic(semdef); +#else + return xSemaphoreCreateBinary(); +#endif } TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) @@ -105,12 +113,21 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t c //--------------------------------------------------------------------+ // MUTEX API (priority inheritance) //--------------------------------------------------------------------+ +#if configSUPPORT_STATIC_ALLOCATION == 1 typedef StaticSemaphore_t osal_mutex_def_t; +#else +typedef SemaphoreHandle_t osal_mutex_def_t; +#endif typedef SemaphoreHandle_t osal_mutex_t; TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) { +#if configSUPPORT_STATIC_ALLOCATION == 1 return xSemaphoreCreateMutexStatic(mdef); +#else + return xSemaphoreCreateMutex(); +#endif + } TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) @@ -145,7 +162,11 @@ typedef QueueHandle_t osal_queue_t; TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) { - return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq); +#if configSUPPORT_STATIC_ALLOCATION == 1 + return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq); +#else + return xQueueCreate(qdef->depth, qdef->item_sz); +#endif } TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) -- cgit v1.3.1 From fe63e30a4408dacc714ad9fcf39cf6fcf7c7d865 Mon Sep 17 00:00:00 2001 From: Gordon McNab Date: Wed, 30 Nov 2022 11:46:13 +0000 Subject: Add FT9xx for cdc_dual_ports Fix handling of interrupt endpoints. i.e. no ZLPs. Fix the assignation of endpoint types. Add button support for MM900evx boards. On board support do not block for UART input. --- .../device/cdc_dual_ports/src/usb_descriptors.c | 11 ++++---- hw/bsp/brtmm90x/boards/mm900evxb/board.h | 2 ++ hw/bsp/brtmm90x/family.c | 31 +++++++++++++++++----- src/portable/bridgetek/ft9xx/dcd_ft9xx.c | 29 +++++++++++++------- 4 files changed, 52 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c index 5a8dea553..4eb8c7c27 100644 --- a/examples/device/cdc_dual_ports/src/usb_descriptors.c +++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c @@ -111,12 +111,13 @@ enum #elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X // FT9XX doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together - #define EPNUM_CDC_NOTIF 0x81 - #define EPNUM_CDC_OUT 0x02 - #define EPNUM_CDC_IN 0x83 + #define EPNUM_CDC_0_NOTIF 0x81 + #define EPNUM_CDC_0_OUT 0x02 + #define EPNUM_CDC_0_IN 0x83 - #define EPNUM_MSC_OUT 0x04 - #define EPNUM_MSC_IN 0x85 + #define EPNUM_CDC_1_NOTIF 0x84 + #define EPNUM_CDC_1_OUT 0x05 + #define EPNUM_CDC_1_IN 0x86 #else #define EPNUM_CDC_0_NOTIF 0x81 diff --git a/hw/bsp/brtmm90x/boards/mm900evxb/board.h b/hw/bsp/brtmm90x/boards/mm900evxb/board.h index 930cb9d33..76813b116 100644 --- a/hw/bsp/brtmm90x/boards/mm900evxb/board.h +++ b/hw/bsp/brtmm90x/boards/mm900evxb/board.h @@ -41,6 +41,8 @@ // LED is connected to pins 4 (signal) and 2 (GND) of CN2. #define GPIO_LED 36 +// Button is connected to pins 6 (signal) and 2 (GND) of CN2. +#define GPIO_BUTTON 37 // Remote wakeup is wired to pin 40 of CN1. #define GPIO_REMOTE_WAKEUP_PIN 18 diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c index cc28cb69b..8155c0afc 100644 --- a/hw/bsp/brtmm90x/family.c +++ b/hw/bsp/brtmm90x/family.c @@ -49,11 +49,16 @@ void board_pm_ISR(void); void board_init(void) { sys_reset_all(); + // Enable the UART Device. sys_enable(sys_device_uart0); // Set UART0 GPIO functions to UART0_TXD and UART0_RXD. +#ifdef GPIO_UART0_TX gpio_function(GPIO_UART0_TX, pad_uart0_txd); /* UART0 TXD */ +#endif +#ifdef GPIO_UART0_RX gpio_function(GPIO_UART0_RX, pad_uart0_rxd); /* UART0 RXD */ +#endif uart_open(UART0, /* Device */ 1, /* Prescaler = 1 */ UART_DIVIDER_19200_BAUD, /* Divider = 1302 */ @@ -65,11 +70,17 @@ void board_init(void) board_uart_write(WELCOME_MSG, sizeof(WELCOME_MSG)); #ifdef GPIO_LED - gpio_function(GPIO_LED, pad_func_0); /* CN2 connector pin 4 */ + gpio_function(GPIO_LED, pad_func_0); gpio_idrive(GPIO_LED, pad_drive_12mA); gpio_dir(GPIO_LED, pad_dir_output); #endif +#ifdef GPIO_BUTTON + gpio_function(GPIO_BUTTON, pad_func_0); + gpio_pull(GPIO_BUTTON, pad_pull_pullup); + gpio_dir(GPIO_BUTTON, pad_dir_input); +#endif + sys_enable(sys_device_timer_wdt); /* Timer A = 1ms */ timer_prescaler(timer_select_a, 1000); @@ -171,9 +182,7 @@ int8_t board_ft9xx_vbus(void) // Turn LED on or off void board_led_write(bool state) { -#if 0 - gpio_write(GPIO_ETH_LED0, state); -#else +#ifdef GPIO_LED gpio_write(GPIO_LED, state); #endif } @@ -182,13 +191,23 @@ void board_led_write(bool state) // a '1' means active (pressed), a '0' means inactive. uint32_t board_button_read(void) { - return 0; + uint32_t state = 0; +#ifdef GPIO_BUTTON + state = gpio_read(GPIO_BUTTON); + state = !state; +#endif + return state; } // Get characters from UART int board_uart_read(uint8_t *buf, int len) { - int r = uart_readn(UART0, (uint8_t *)buf, len); + int r = 0; + + if (uart_rx_has_data(UART0)) + { + r = uart_readn(UART0, (uint8_t *)buf, len); + } return r; } diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c index 50f7018db..fabe7910b 100644 --- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c +++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c @@ -48,6 +48,7 @@ // Board code will determine the state of VBUS from USB host. extern int8_t board_ft9xx_vbus(void); +extern int board_uart_write(void const *buf, int len); // Static array to store an incoming SETUP request for processing by tinyusb. CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN @@ -154,17 +155,24 @@ static uint16_t _ft9xx_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t } else { - uint8_t sr_reg; // If there is data to transmit then wait until the IN buffer // for the endpoint is empty. - do + // This does not apply to interrupt endpoints. + if (ep_xfer[ep_number].type != TUSB_XFER_INTERRUPT) { - sr_reg = USBD_EP_SR_REG(ep_number); - } while (sr_reg & MASK_USBD_EPxSR_INPRDY); - + uint8_t sr_reg; + do + { + sr_reg = USBD_EP_SR_REG(ep_number); + } while (sr_reg & MASK_USBD_EPxSR_INPRDY); + } } - xfer_bytes = _ft9xx_dusb_in(ep_number, (uint8_t *)buffer, xfer_bytes); + // Do not send a ZLP for interrupt endpoints. + if ((ep_xfer[ep_number].type != TUSB_XFER_INTERRUPT) || (xfer_bytes > 0)) + { + xfer_bytes = _ft9xx_dusb_in(ep_number, (uint8_t *)buffer, xfer_bytes); + } if (ep_number == USBD_EP_0) { @@ -749,11 +757,11 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) } // Set the type of this endpoint in the control register. - if (ep_type == USBD_EP_BULK) + if (ep_type == TUSB_XFER_BULK) ep_reg_data |= (USBD_EP_DIS_BULK << BIT_USBD_EP_CONTROL_DIS); - else if (ep_type == USBD_EP_INT) + else if (ep_type == TUSB_XFER_INTERRUPT) ep_reg_data |= (USBD_EP_DIS_INT << BIT_USBD_EP_CONTROL_DIS); - else if (ep_type == USBD_EP_ISOC) + else if (ep_type == TUSB_XFER_ISOCHRONOUS) ep_reg_data |= (USBD_EP_DIS_ISO << BIT_USBD_EP_CONTROL_DIS); // Set the direction of this endpoint in the control register. if (ep_dir == USBD_DIR_IN) @@ -761,7 +769,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) // Do not perform double buffering. //if ( != USBD_DB_OFF) //ep_reg_data |= MASK_USBD_EPxCR_DB; - // Set the control endpoint for this endpoint. + // Set the control register for this endpoint. USBD_EP_CR_REG(ep_number) = ep_reg_data; TU_LOG2("FT9xx endpoint setting %x\r\n", ep_reg_data); } @@ -858,6 +866,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to // Transfer incoming data from an OUT packet to the buffer. xfer_bytes = _ft9xx_edpt_xfer_out(ep_number, buffer, total_bytes); + // Report completion of the transfer. dcd_event_xfer_complete(BOARD_TUD_RHPORT, ep_number /*| TUSB_DIR_OUT_MASK */, xfer_bytes, XFER_RESULT_SUCCESS, false); } -- cgit v1.3.1 From 069215c538cc1b615f18a6af055026267d56581c Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 30 Nov 2022 18:36:01 +0700 Subject: white spaces --- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 587 ++++++++++++++------------- src/portable/raspberrypi/rp2040/rp2040_usb.c | 54 ++- 2 files changed, 330 insertions(+), 311 deletions(-) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 10237d1f9..9e6bdad44 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -81,89 +81,90 @@ static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr) TU_ATTR_ALWAYS_INLINE static inline uint8_t dev_speed(void) { - return (usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS) >> USB_SIE_STATUS_SPEED_LSB; + return (usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS) >> USB_SIE_STATUS_SPEED_LSB; } -static bool need_pre(uint8_t dev_addr) +TU_ATTR_ALWAYS_INLINE static inline bool need_pre(uint8_t dev_addr) { - // If this device is different to the speed of the root device - // (i.e. is a low speed device on a full speed hub) then need pre - return hcd_port_speed_get(0) != tuh_speed_get(dev_addr); + // If this device is different to the speed of the root device + // (i.e. is a low speed device on a full speed hub) then need pre + return hcd_port_speed_get(0) != tuh_speed_get(dev_addr); } static void __tusb_irq_path_func(hw_xfer_complete)(struct hw_endpoint *ep, xfer_result_t xfer_result) { - // Mark transfer as done before we tell the tinyusb stack - uint8_t dev_addr = ep->dev_addr; - uint8_t ep_addr = ep->ep_addr; - uint xferred_len = ep->xferred_len; - hw_endpoint_reset_transfer(ep); - hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, xfer_result, true); + // Mark transfer as done before we tell the tinyusb stack + uint8_t dev_addr = ep->dev_addr; + uint8_t ep_addr = ep->ep_addr; + uint xferred_len = ep->xferred_len; + hw_endpoint_reset_transfer(ep); + hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, xfer_result, true); } static void __tusb_irq_path_func(_handle_buff_status_bit)(uint bit, struct hw_endpoint *ep) { - usb_hw_clear->buf_status = bit; - // EP may have been stalled? - assert(ep->active); - bool done = hw_endpoint_xfer_continue(ep); - if (done) - { - hw_xfer_complete(ep, XFER_RESULT_SUCCESS); - } + usb_hw_clear->buf_status = bit; + // EP may have been stalled? + assert(ep->active); + bool done = hw_endpoint_xfer_continue(ep); + if ( done ) + { + hw_xfer_complete(ep, XFER_RESULT_SUCCESS); + } } static void __tusb_irq_path_func(hw_handle_buff_status)(void) { - uint32_t remaining_buffers = usb_hw->buf_status; - pico_trace("buf_status 0x%08x\n", remaining_buffers); + uint32_t remaining_buffers = usb_hw->buf_status; + pico_trace("buf_status 0x%08x\n", remaining_buffers); - // Check EPX first - uint bit = 0b1; - if (remaining_buffers & bit) + // Check EPX first + uint bit = 0b1; + if ( remaining_buffers & bit ) + { + remaining_buffers &= ~bit; + struct hw_endpoint * ep = &epx; + + uint32_t ep_ctrl = *ep->endpoint_control; + if ( ep_ctrl & EP_CTRL_DOUBLE_BUFFERED_BITS ) { - remaining_buffers &= ~bit; - struct hw_endpoint *ep = &epx; - - uint32_t ep_ctrl = *ep->endpoint_control; - if (ep_ctrl & EP_CTRL_DOUBLE_BUFFERED_BITS) - { - TU_LOG(3, "Double Buffered: "); - }else - { - TU_LOG(3, "Single Buffered: "); - } - TU_LOG_HEX(3, ep_ctrl); - - _handle_buff_status_bit(bit, ep); + TU_LOG(3, "Double Buffered: "); } - - // Check "interrupt" (asynchronous) endpoints for both IN and OUT - for (uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++) + else { - // EPX is bit 0 & 1 - // IEP1 IN is bit 2 - // IEP1 OUT is bit 3 - // IEP2 IN is bit 4 - // IEP2 OUT is bit 5 - // IEP3 IN is bit 6 - // IEP3 OUT is bit 7 - // etc - for(uint j = 0; j < 2; j++) - { - bit = 1 << (i*2+j); - if (remaining_buffers & bit) - { - remaining_buffers &= ~bit; - _handle_buff_status_bit(bit, &ep_pool[i]); - } - } + TU_LOG(3, "Single Buffered: "); } + TU_LOG_HEX(3, ep_ctrl); - if (remaining_buffers) + _handle_buff_status_bit(bit, ep); + } + + // Check "interrupt" (asynchronous) endpoints for both IN and OUT + for ( uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++ ) + { + // EPX is bit 0 & 1 + // IEP1 IN is bit 2 + // IEP1 OUT is bit 3 + // IEP2 IN is bit 4 + // IEP2 OUT is bit 5 + // IEP3 IN is bit 6 + // IEP3 OUT is bit 7 + // etc + for ( uint j = 0; j < 2; j++ ) { - panic("Unhandled buffer %d\n", remaining_buffers); + bit = 1 << (i * 2 + j); + if ( remaining_buffers & bit ) + { + remaining_buffers &= ~bit; + _handle_buff_status_bit(bit, &ep_pool[i]); + } } + } + + if ( remaining_buffers ) + { + panic("Unhandled buffer %d\n", remaining_buffers); + } } static void __tusb_irq_path_func(hw_trans_complete)(void) @@ -186,70 +187,72 @@ static void __tusb_irq_path_func(hw_trans_complete)(void) static void __tusb_irq_path_func(hcd_rp2040_irq)(void) { - uint32_t status = usb_hw->ints; - uint32_t handled = 0; + uint32_t status = usb_hw->ints; + uint32_t handled = 0; - if (status & USB_INTS_HOST_CONN_DIS_BITS) - { - handled |= USB_INTS_HOST_CONN_DIS_BITS; - - if (dev_speed()) - { - hcd_event_device_attach(RHPORT_NATIVE, true); - } - else - { - hcd_event_device_remove(RHPORT_NATIVE, true); - } - - // Clear speed change interrupt - usb_hw_clear->sie_status = USB_SIE_STATUS_SPEED_BITS; - } + if ( status & USB_INTS_HOST_CONN_DIS_BITS ) + { + handled |= USB_INTS_HOST_CONN_DIS_BITS; - if (status & USB_INTS_STALL_BITS) + if ( dev_speed() ) { - // We have rx'd a stall from the device - // NOTE THIS SHOULD HAVE PRIORITY OVER BUFF_STATUS - // AND TRANS_COMPLETE as the stall is an alternative response - // to one of those events - pico_trace("Stall REC\n"); - handled |= USB_INTS_STALL_BITS; - usb_hw_clear->sie_status = USB_SIE_STATUS_STALL_REC_BITS; - hw_xfer_complete(&epx, XFER_RESULT_STALLED); + hcd_event_device_attach(RHPORT_NATIVE, true); } - - if (status & USB_INTS_BUFF_STATUS_BITS) + else { - handled |= USB_INTS_BUFF_STATUS_BITS; - TU_LOG(2, "Buffer complete\n"); - hw_handle_buff_status(); + hcd_event_device_remove(RHPORT_NATIVE, true); } - if (status & USB_INTS_TRANS_COMPLETE_BITS) - { - handled |= USB_INTS_TRANS_COMPLETE_BITS; - usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS; - TU_LOG(2, "Transfer complete\n"); - hw_trans_complete(); - } + // Clear speed change interrupt + usb_hw_clear->sie_status = USB_SIE_STATUS_SPEED_BITS; + } - if (status & USB_INTS_ERROR_RX_TIMEOUT_BITS) - { - handled |= USB_INTS_ERROR_RX_TIMEOUT_BITS; - usb_hw_clear->sie_status = USB_SIE_STATUS_RX_TIMEOUT_BITS; - } + if ( status & USB_INTS_STALL_BITS ) + { + // We have rx'd a stall from the device + // NOTE THIS SHOULD HAVE PRIORITY OVER BUFF_STATUS + // AND TRANS_COMPLETE as the stall is an alternative response + // to one of those events + pico_trace("Stall REC\n"); + handled |= USB_INTS_STALL_BITS; + usb_hw_clear->sie_status = USB_SIE_STATUS_STALL_REC_BITS; + hw_xfer_complete(&epx, XFER_RESULT_STALLED); + } - if (status & USB_INTS_ERROR_DATA_SEQ_BITS) - { - usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS; - TU_LOG(3, " Seq Error: [0] = 0x%04u [1] = 0x%04x\r\n", tu_u32_low16(*epx.buffer_control), tu_u32_high16(*epx.buffer_control)); - panic("Data Seq Error \n"); - } + if ( status & USB_INTS_BUFF_STATUS_BITS ) + { + handled |= USB_INTS_BUFF_STATUS_BITS; + TU_LOG(2, "Buffer complete\n"); + hw_handle_buff_status(); + } - if (status ^ handled) - { - panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled)); - } + if ( status & USB_INTS_TRANS_COMPLETE_BITS ) + { + handled |= USB_INTS_TRANS_COMPLETE_BITS; + usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS; + TU_LOG(2, "Transfer complete\n"); + hw_trans_complete(); + } + + if ( status & USB_INTS_ERROR_RX_TIMEOUT_BITS ) + { + handled |= USB_INTS_ERROR_RX_TIMEOUT_BITS; + usb_hw_clear->sie_status = USB_SIE_STATUS_RX_TIMEOUT_BITS; + } + + if ( status & USB_INTS_ERROR_DATA_SEQ_BITS ) + { + usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS; + TU_LOG(3, " Seq Error: [0] = 0x%04u [1] = 0x%04x\r\n", + tu_u32_low16(*epx.buffer_control), + tu_u32_high16(*epx.buffer_control)); + panic("Data Seq Error \n"); + } + + if ( status ^ handled ) + { + panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled)); + } } void __tusb_irq_path_func(hcd_int_handler)(uint8_t rhport) @@ -260,116 +263,118 @@ void __tusb_irq_path_func(hcd_int_handler)(uint8_t rhport) static struct hw_endpoint *_next_free_interrupt_ep(void) { - struct hw_endpoint *ep = NULL; - for (uint i = 1; i < TU_ARRAY_SIZE(ep_pool); i++) + struct hw_endpoint * ep = NULL; + for ( uint i = 1; i < TU_ARRAY_SIZE(ep_pool); i++ ) + { + ep = &ep_pool[i]; + if ( !ep->configured ) { - ep = &ep_pool[i]; - if (!ep->configured) - { - // Will be configured by _hw_endpoint_init / _hw_endpoint_allocate - ep->interrupt_num = (uint8_t) (i - 1); - return ep; - } + // Will be configured by _hw_endpoint_init / _hw_endpoint_allocate + ep->interrupt_num = (uint8_t) (i - 1); + return ep; } - return ep; + } + return ep; } static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type) { - struct hw_endpoint *ep = NULL; + struct hw_endpoint * ep = NULL; - if (transfer_type != TUSB_XFER_CONTROL) - { - // Note: even though datasheet name these "Interrupt" endpoints. These are actually - // "Asynchronous" endpoints and can be used for other type such as: Bulk (ISO need confirmation) - ep = _next_free_interrupt_ep(); - pico_info("Allocate %s ep %d\n", tu_edpt_type_str(transfer_type), ep->interrupt_num); - assert(ep); - ep->buffer_control = &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl; - ep->endpoint_control = &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl; - // 0 for epx (double buffered): TODO increase to 1024 for ISO - // 2x64 for intep0 - // 3x64 for intep1 - // etc - ep->hw_data_buf = &usbh_dpram->epx_data[64 * (ep->interrupt_num + 2)]; - } - else - { - ep = &epx; - ep->buffer_control = &usbh_dpram->epx_buf_ctrl; - ep->endpoint_control = &usbh_dpram->epx_ctrl; - ep->hw_data_buf = &usbh_dpram->epx_data[0]; - } + if ( transfer_type != TUSB_XFER_CONTROL ) + { + // Note: even though datasheet name these "Interrupt" endpoints. These are actually + // "Asynchronous" endpoints and can be used for other type such as: Bulk (ISO need confirmation) + ep = _next_free_interrupt_ep(); + pico_info("Allocate %s ep %d\n", tu_edpt_type_str(transfer_type), ep->interrupt_num); + assert(ep); + ep->buffer_control = &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl; + ep->endpoint_control = &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl; + // 0 for epx (double buffered): TODO increase to 1024 for ISO + // 2x64 for intep0 + // 3x64 for intep1 + // etc + ep->hw_data_buf = &usbh_dpram->epx_data[64 * (ep->interrupt_num + 2)]; + } + else + { + ep = &epx; + ep->buffer_control = &usbh_dpram->epx_buf_ctrl; + ep->endpoint_control = &usbh_dpram->epx_ctrl; + ep->hw_data_buf = &usbh_dpram->epx_data[0]; + } - return ep; + return ep; } static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type, uint8_t bmInterval) { - // Already has data buffer, endpoint control, and buffer control allocated at this point - assert(ep->endpoint_control); - assert(ep->buffer_control); - assert(ep->hw_data_buf); - - uint8_t const num = tu_edpt_number(ep_addr); - tusb_dir_t const dir = tu_edpt_dir(ep_addr); - - ep->ep_addr = ep_addr; - ep->dev_addr = dev_addr; - - // For host, IN to host == RX, anything else rx == false - ep->rx = (dir == TUSB_DIR_IN); - - // Response to a setup packet on EP0 starts with pid of 1 - ep->next_pid = (num == 0 ? 1u : 0u); - ep->wMaxPacketSize = wMaxPacketSize; - ep->transfer_type = transfer_type; - - pico_trace("hw_endpoint_init dev %d ep %d %s xfer %d\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->transfer_type); - pico_trace("dev %d ep %d %s setup buffer @ 0x%p\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->hw_data_buf); - uint dpram_offset = hw_data_offset(ep->hw_data_buf); - // Bits 0-5 should be 0 - assert(!(dpram_offset & 0b111111)); - - // Fill in endpoint control register with buffer offset - uint32_t ep_reg = EP_CTRL_ENABLE_BITS - | EP_CTRL_INTERRUPT_PER_BUFFER - | (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB) - | dpram_offset; - if (bmInterval) + // Already has data buffer, endpoint control, and buffer control allocated at this point + assert(ep->endpoint_control); + assert(ep->buffer_control); + assert(ep->hw_data_buf); + + uint8_t const num = tu_edpt_number(ep_addr); + tusb_dir_t const dir = tu_edpt_dir(ep_addr); + + ep->ep_addr = ep_addr; + ep->dev_addr = dev_addr; + + // For host, IN to host == RX, anything else rx == false + ep->rx = (dir == TUSB_DIR_IN); + + // Response to a setup packet on EP0 starts with pid of 1 + ep->next_pid = (num == 0 ? 1u : 0u); + ep->wMaxPacketSize = wMaxPacketSize; + ep->transfer_type = transfer_type; + + pico_trace("hw_endpoint_init dev %d ep %d %s xfer %d\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), + ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->transfer_type); + pico_trace("dev %d ep %d %s setup buffer @ 0x%p\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), + ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->hw_data_buf); + uint dpram_offset = hw_data_offset(ep->hw_data_buf); + // Bits 0-5 should be 0 + assert(!(dpram_offset & 0b111111)); + + // Fill in endpoint control register with buffer offset + uint32_t ep_reg = EP_CTRL_ENABLE_BITS + | EP_CTRL_INTERRUPT_PER_BUFFER + | (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB) + | dpram_offset; + if ( bmInterval ) + { + ep_reg |= (uint32_t) ((bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB); + } + *ep->endpoint_control = ep_reg; + pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg); + ep->configured = true; + + if ( ep != &epx ) + { + // Endpoint has its own addr_endp and interrupt bits to be setup! + // This is an interrupt/async endpoint. so need to set up ADDR_ENDP register with: + // - device address + // - endpoint number / direction + // - preamble + uint32_t reg = (uint32_t) (dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB)); + + if ( dir == TUSB_DIR_OUT ) { - ep_reg |= (uint32_t) ((bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB); + reg |= USB_ADDR_ENDP1_INTEP_DIR_BITS; } - *ep->endpoint_control = ep_reg; - pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg); - ep->configured = true; - if (ep != &epx) + if ( need_pre(dev_addr) ) { - // Endpoint has its own addr_endp and interrupt bits to be setup! - // This is an interrupt/async endpoint. so need to set up ADDR_ENDP register with: - // - device address - // - endpoint number / direction - // - preamble - uint32_t reg = (uint32_t) (dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB)); - - if (dir == TUSB_DIR_OUT) - { - reg |= USB_ADDR_ENDP1_INTEP_DIR_BITS; - } - - if (need_pre(dev_addr)) - { - reg |= USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS; - } - usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = reg; - - // Finally, enable interrupt that endpoint - usb_hw_set->int_ep_ctrl = 1 << (ep->interrupt_num + 1); - - // If it's an interrupt endpoint we need to set up the buffer control - // register + reg |= USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS; } + usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = reg; + + // Finally, enable interrupt that endpoint + usb_hw_set->int_ep_ctrl = 1 << (ep->interrupt_num + 1); + + // If it's an interrupt endpoint we need to set up the buffer control + // register + } } //--------------------------------------------------------------------+ @@ -434,16 +439,17 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport) { (void) rhport; assert(rhport == 0); + // TODO: Should enumval this register - switch (dev_speed()) + switch ( dev_speed() ) { - case 1: - return TUSB_SPEED_LOW; - case 2: - return TUSB_SPEED_FULL; - default: - panic("Invalid speed\n"); - return TUSB_SPEED_INVALID; + case 1: + return TUSB_SPEED_LOW; + case 2: + return TUSB_SPEED_FULL; + default: + panic("Invalid speed\n"); + return TUSB_SPEED_INVALID; } } @@ -476,8 +482,8 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) uint32_t hcd_frame_number(uint8_t rhport) { - (void) rhport; - return usb_hw->sof_rd; + (void) rhport; + return usb_hw->sof_rd; } void hcd_int_enable(uint8_t rhport) @@ -501,117 +507,116 @@ void hcd_int_disable(uint8_t rhport) bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { - (void) rhport; + (void) rhport; - pico_trace("hcd_edpt_open dev_addr %d, ep_addr %d\n", dev_addr, ep_desc->bEndpointAddress); + pico_trace("hcd_edpt_open dev_addr %d, ep_addr %d\n", dev_addr, ep_desc->bEndpointAddress); - // Allocated differently based on if it's an interrupt endpoint or not - struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer); - TU_ASSERT(ep); + // Allocated differently based on if it's an interrupt endpoint or not + struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer); + TU_ASSERT(ep); - _hw_endpoint_init(ep, - dev_addr, - ep_desc->bEndpointAddress, - tu_edpt_packet_size(ep_desc), - ep_desc->bmAttributes.xfer, - ep_desc->bInterval); + _hw_endpoint_init(ep, + dev_addr, + ep_desc->bEndpointAddress, + tu_edpt_packet_size(ep_desc), + ep_desc->bmAttributes.xfer, + ep_desc->bInterval); - return true; + return true; } bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { - (void) rhport; + (void) rhport; - pico_trace("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen); - - uint8_t const ep_num = tu_edpt_number(ep_addr); - tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr); + pico_trace("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen); - // Get appropriate ep. Either EPX or interrupt endpoint - struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr); + uint8_t const ep_num = tu_edpt_number(ep_addr); + tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr); - TU_ASSERT(ep); + // Get appropriate ep. Either EPX or interrupt endpoint + struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr); - // EP should be inactive - assert(!ep->active); + TU_ASSERT(ep); - // Control endpoint can change direction 0x00 <-> 0x80 - if ( ep_addr != ep->ep_addr ) - { - assert(ep_num == 0); + // EP should be inactive + assert(!ep->active); - // Direction has flipped on endpoint control so re init it but with same properties - _hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0); - } + // Control endpoint can change direction 0x00 <-> 0x80 + if ( ep_addr != ep->ep_addr ) + { + assert(ep_num == 0); - // If a normal transfer (non-interrupt) then initiate using - // sie ctrl registers. Otherwise interrupt ep registers should - // already be configured - if (ep == &epx) { - hw_endpoint_xfer_start(ep, buffer, buflen); + // Direction has flipped on endpoint control so re init it but with same properties + _hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0); + } - // That has set up buffer control, endpoint control etc - // for host we have to initiate the transfer - usb_hw->dev_addr_ctrl = (uint32_t) (dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB)); + // If a normal transfer (non-interrupt) then initiate using + // sie ctrl registers. Otherwise interrupt ep registers should + // already be configured + if ( ep == &epx ) + { + hw_endpoint_xfer_start(ep, buffer, buflen); - uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | SIE_CTRL_BASE | - (ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS); - // Set pre if we are a low speed device on full speed hub - flags |= need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0; + // That has set up buffer control, endpoint control etc + // for host we have to initiate the transfer + usb_hw->dev_addr_ctrl = (uint32_t) (dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB)); - usb_hw->sie_ctrl = flags; - }else - { - hw_endpoint_xfer_start(ep, buffer, buflen); - } + uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | SIE_CTRL_BASE | + (ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS) | + (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0); + usb_hw->sie_ctrl = flags; + }else + { + hw_endpoint_xfer_start(ep, buffer, buflen); + } - return true; + return true; } bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { - (void) rhport; + (void) rhport; - // Copy data into setup packet buffer - for(uint8_t i=0; i<8; i++) - { - usbh_dpram->setup_packet[i] = setup_packet[i]; - } + // Copy data into setup packet buffer + for ( uint8_t i = 0; i < 8; i++ ) + { + usbh_dpram->setup_packet[i] = setup_packet[i]; + } - // Configure EP0 struct with setup info for the trans complete - struct hw_endpoint *ep = _hw_endpoint_allocate(0); - TU_ASSERT(ep); + // Configure EP0 struct with setup info for the trans complete + struct hw_endpoint * ep = _hw_endpoint_allocate(0); + TU_ASSERT(ep); - // EPX should be inactive - assert(!ep->active); + // EPX should be inactive + assert(!ep->active); - // EP0 out - _hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0); - assert(ep->configured); + // EP0 out + _hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0); + assert(ep->configured); - ep->remaining_len = 8; - ep->active = true; + ep->remaining_len = 8; + ep->active = true; - // Set device address - usb_hw->dev_addr_ctrl = dev_addr; + // Set device address + usb_hw->dev_addr_ctrl = dev_addr; - // Set pre if we are a low speed device on full speed hub - uint32_t const flags = SIE_CTRL_BASE | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS | - (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0); + // Set pre if we are a low speed device on full speed hub + uint32_t const flags = SIE_CTRL_BASE | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS | + (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0); - usb_hw->sie_ctrl = flags; + usb_hw->sie_ctrl = flags; - return true; + return true; } bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) { - (void) dev_addr; - (void) ep_addr; + (void) dev_addr; + (void) ep_addr; - panic("hcd_clear_stall"); - return true; + panic("hcd_clear_stall"); + return true; } #endif diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index d7895175e..5c7645902 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -47,6 +47,12 @@ TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_lock_update(__unused struc static void _hw_endpoint_xfer_sync(struct hw_endpoint *ep); static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep); +// if usb hardware is in host mode +TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void) +{ + return (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) ? true : false; +} + //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ @@ -69,6 +75,8 @@ void rp2040_usb_init(void) // Mux the controller to the onboard usb phy usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS; + + TU_LOG2_INT(sizeof(hw_endpoint_t)); } void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep) @@ -80,19 +88,23 @@ void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep) } void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask) { - uint32_t value = 0; - if (and_mask) { - value = *ep->buffer_control & and_mask; - } - if (or_mask) { - value |= or_mask; - if (or_mask & USB_BUF_CTRL_AVAIL) { - if (*ep->buffer_control & USB_BUF_CTRL_AVAIL) { - panic("ep %d %s was already available", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]); - } - *ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL; - // 12 cycle delay.. (should be good for 48*12Mhz = 576Mhz) - // Don't need delay in host mode as host is in charge + uint32_t value = 0; + if ( and_mask ) + { + value = *ep->buffer_control & and_mask; + } + if ( or_mask ) + { + value |= or_mask; + if ( or_mask & USB_BUF_CTRL_AVAIL ) + { + if ( *ep->buffer_control & USB_BUF_CTRL_AVAIL ) + { + panic("ep %d %s was already available", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]); + } + *ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL; + // 12 cycle delay.. (should be good for 48*12Mhz = 576Mhz) + // Don't need delay in host mode as host is in charge #if !CFG_TUH_ENABLED __asm volatile ( "b 1f\n" @@ -104,9 +116,9 @@ void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoi "1:\n" : : : "memory"); #endif - } } - *ep->buffer_control = value; + } + *ep->buffer_control = value; } // prepare buffer, return buffer control @@ -152,12 +164,14 @@ static void __tusb_irq_path_func(_hw_endpoint_start_next_buffer)(struct hw_endpo // always compute and start with buffer 0 uint32_t buf_ctrl = prepare_ep_buffer(ep, 0) | USB_BUF_CTRL_SEL; - // For now: skip double buffered for Device mode, OUT endpoint since + // For now: skip double buffered for OUT endpoint in Device mode, since // host could send < 64 bytes and cause short packet on buffer0 - // NOTE this could happen to Host mode IN endpoint - // Also, Host mode interrupt endpoint hardware is only single buffered - bool const force_single = (!(usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && !tu_edpt_dir(ep->ep_addr)) || - ((usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && tu_edpt_number(ep->ep_addr) != 0); + // NOTE: this could happen to Host mode IN endpoint + // Also, Host mode "interrupt" endpoint hardware is only single buffered, + // NOTE2: Currently Host bulk is implemented using "interrupt" endpoint + bool const is_host = is_host_mode(); + bool const force_single = (!is_host && !tu_edpt_dir(ep->ep_addr)) || + (is_host && tu_edpt_number(ep->ep_addr) != 0); if(ep->remaining_len && !force_single) { -- cgit v1.3.1 From c9c7dfa868ea78afd6b3bb490542e65660c39149 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 30 Nov 2022 18:59:58 +0700 Subject: more clean up --- src/portable/raspberrypi/rp2040/rp2040_usb.h | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h index c72dae64c..b65d32fd4 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.h +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h @@ -82,26 +82,30 @@ void hw_endpoint_reset_transfer(struct hw_endpoint *ep); void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask); -TU_ATTR_ALWAYS_INLINE static inline uint32_t _hw_endpoint_buffer_control_get_value32(struct hw_endpoint *ep) { - return *ep->buffer_control; +TU_ATTR_ALWAYS_INLINE static inline uint32_t _hw_endpoint_buffer_control_get_value32 (struct hw_endpoint *ep) +{ + return *ep->buffer_control; } -TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_value32(struct hw_endpoint *ep, uint32_t value) { - return _hw_endpoint_buffer_control_update32(ep, 0, value); +TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_value32 (struct hw_endpoint *ep, uint32_t value) +{ + return _hw_endpoint_buffer_control_update32(ep, 0, value); } -TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_mask32(struct hw_endpoint *ep, uint32_t value) { - return _hw_endpoint_buffer_control_update32(ep, ~value, value); +TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_mask32 (struct hw_endpoint *ep, uint32_t value) +{ + return _hw_endpoint_buffer_control_update32(ep, ~value, value); } -TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_clear_mask32(struct hw_endpoint *ep, uint32_t value) { - return _hw_endpoint_buffer_control_update32(ep, ~value, 0); +TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_clear_mask32 (struct hw_endpoint *ep, uint32_t value) +{ + return _hw_endpoint_buffer_control_update32(ep, ~value, 0); } -static inline uintptr_t hw_data_offset(uint8_t *buf) +static inline uintptr_t hw_data_offset (uint8_t *buf) { - // Remove usb base from buffer pointer - return (uintptr_t)buf ^ (uintptr_t)usb_dpram; + // Remove usb base from buffer pointer + return (uintptr_t) buf ^ (uintptr_t) usb_dpram; } extern const char *ep_dir_string[]; -- cgit v1.3.1 From 25abb10de17ed868b2189ae5038a7c47aab19ae5 Mon Sep 17 00:00:00 2001 From: pete-pjb Date: Wed, 30 Nov 2022 13:26:59 +0000 Subject: Fix white space issue. --- src/osal/osal_freertos.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index a2b0573f8..fed70400e 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -62,7 +62,7 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) //--------------------------------------------------------------------+ // Semaphore API //--------------------------------------------------------------------+ -#if configSUPPORT_STATIC_ALLOCATION == 1 +#if configSUPPORT_STATIC_ALLOCATION == 1 typedef StaticSemaphore_t osal_semaphore_def_t; #else typedef SemaphoreHandle_t osal_semaphore_def_t; @@ -71,7 +71,7 @@ typedef SemaphoreHandle_t osal_semaphore_t; TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) { -#if configSUPPORT_STATIC_ALLOCATION == 1 +#if configSUPPORT_STATIC_ALLOCATION == 1 return xSemaphoreCreateBinaryStatic(semdef); #else return xSemaphoreCreateBinary(); @@ -113,7 +113,7 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t c //--------------------------------------------------------------------+ // MUTEX API (priority inheritance) //--------------------------------------------------------------------+ -#if configSUPPORT_STATIC_ALLOCATION == 1 +#if configSUPPORT_STATIC_ALLOCATION == 1 typedef StaticSemaphore_t osal_mutex_def_t; #else typedef SemaphoreHandle_t osal_mutex_def_t; @@ -122,7 +122,7 @@ typedef SemaphoreHandle_t osal_mutex_t; TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) { -#if configSUPPORT_STATIC_ALLOCATION == 1 +#if configSUPPORT_STATIC_ALLOCATION == 1 return xSemaphoreCreateMutexStatic(mdef); #else return xSemaphoreCreateMutex(); @@ -162,7 +162,7 @@ typedef QueueHandle_t osal_queue_t; TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) { -#if configSUPPORT_STATIC_ALLOCATION == 1 +#if configSUPPORT_STATIC_ALLOCATION == 1 return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq); #else return xQueueCreate(qdef->depth, qdef->item_sz); -- cgit v1.3.1 From ae588d796e1b035c7efd582a4e4f3fc28b3a5ac0 Mon Sep 17 00:00:00 2001 From: PeterB Date: Thu, 1 Dec 2022 16:06:15 +0000 Subject: Alter tuh_task_ext() function so no need to return when using FreeRTOS --- src/host/usbh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index d97b160c9..a90b54924 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -509,7 +509,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) default: break; } -#if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO +#if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO && CFG_TUSB_OS != OPT_OS_FREERTOS // return if there is no more events, for application to run other background if (osal_queue_empty(_usbh_q)) return; #endif -- cgit v1.3.1 From c31b95c91652f58b8b991a5481c9f7c37be7f09a Mon Sep 17 00:00:00 2001 From: pete-pjb Date: Thu, 1 Dec 2022 17:53:35 +0000 Subject: Added CFG_TUSB_MEM_SECTION define to struct _ctrl_xfer in usbh.c --- src/host/usbh.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index a90b54924..f28554b81 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -246,8 +246,8 @@ static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE]; // Control transfer: since most controller does not support multiple control transfer // on multiple devices concurrently. And control transfer is not used much except enumeration -// We will only execute control transfer one at a time. -struct +// We will only execute control transfer one at a time.CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4096) +CFG_TUSB_MEM_SECTION struct { tusb_control_request_t request TU_ATTR_ALIGNED(4); uint8_t* buffer; -- cgit v1.3.1 From 3816869fce15509fd43eb5a6d14de76478f86cf1 Mon Sep 17 00:00:00 2001 From: pete-pjb Date: Fri, 2 Dec 2022 10:00:19 +0000 Subject: Some reverts and changes after discussion. --- src/host/usbh.c | 6 +++--- src/osal/osal_freertos.h | 5 ++++- src/portable/ehci/ehci.c | 3 ++- 3 files changed, 9 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index f28554b81..d97b160c9 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -246,8 +246,8 @@ static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE]; // Control transfer: since most controller does not support multiple control transfer // on multiple devices concurrently. And control transfer is not used much except enumeration -// We will only execute control transfer one at a time.CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4096) -CFG_TUSB_MEM_SECTION struct +// We will only execute control transfer one at a time. +struct { tusb_control_request_t request TU_ATTR_ALIGNED(4); uint8_t* buffer; @@ -509,7 +509,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) default: break; } -#if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO && CFG_TUSB_OS != OPT_OS_FREERTOS +#if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO // return if there is no more events, for application to run other background if (osal_queue_empty(_usbh_q)) return; #endif diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index fed70400e..ccb98cc99 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -74,6 +74,7 @@ TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_ #if configSUPPORT_STATIC_ALLOCATION == 1 return xSemaphoreCreateBinaryStatic(semdef); #else + (void)(semdef); return xSemaphoreCreateBinary(); #endif } @@ -125,6 +126,7 @@ TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_de #if configSUPPORT_STATIC_ALLOCATION == 1 return xSemaphoreCreateMutexStatic(mdef); #else + (void)(mdef); return xSemaphoreCreateMutex(); #endif @@ -154,8 +156,9 @@ typedef struct uint16_t depth; uint16_t item_sz; void* buf; - +#if configSUPPORT_STATIC_ALLOCATION == 1 StaticQueue_t sq; +#endif }osal_queue_def_t; typedef QueueHandle_t osal_queue_t; diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 76ba2a921..0af8c3b2d 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -193,7 +193,8 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr) { // TODO check type for ISO iTD and siTD // TODO Suppress cast-align warning - #pragma GCC diagnostic push + if( prev == NULL ) break; + #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wcast-align" ehci_qhd_t* qhd = (ehci_qhd_t*) list_next(prev); #pragma GCC diagnostic pop -- cgit v1.3.1 From 52261ac02dfbe58f35f959be852f0949cc0744cd Mon Sep 17 00:00:00 2001 From: pete-pjb Date: Fri, 2 Dec 2022 10:13:35 +0000 Subject: Back out another of my changes I am still investigating. --- src/portable/ehci/ehci.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 0af8c3b2d..361015964 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -193,7 +193,6 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr) { // TODO check type for ISO iTD and siTD // TODO Suppress cast-align warning - if( prev == NULL ) break; #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wcast-align" ehci_qhd_t* qhd = (ehci_qhd_t*) list_next(prev); -- cgit v1.3.1 From 6a2cf6728906aa61b44ecfe43b4ceef287b29bf8 Mon Sep 17 00:00:00 2001 From: Bastien Nocera Date: Sun, 4 Dec 2022 13:58:47 +0700 Subject: Fix typos --- .github/ISSUE_TEMPLATE/bug_report.yml | 2 +- docs/contributing/porting.rst | 4 ++-- docs/info/changelog.rst | 22 +++++++++++----------- examples/device/cdc_msc/src/main.c | 2 +- examples/device/cdc_msc_freertos/CMakeLists.txt | 2 +- examples/device/dfu_runtime/src/main.c | 2 +- examples/device/hid_boot_interface/src/main.c | 6 +++--- examples/host/cdc_msc_hid/src/hid_app.c | 2 +- hw/bsp/ansi_escape.h | 2 +- .../led_strip/src/led_strip_rmt_ws2812.c | 2 +- .../led_strip/src/led_strip_rmt_ws2812.c | 2 +- hw/bsp/family_support.cmake | 4 ++-- hw/bsp/gd32vf103/family.c | 2 +- hw/bsp/gd32vf103/system_gd32vf103.c | 2 +- .../evkmimxrt1010_flexspi_nor_config.h | 10 +++++----- .../evkmimxrt1015_flexspi_nor_config.h | 10 +++++----- .../evkmimxrt1020_flexspi_nor_config.h | 10 +++++----- .../evkbimxrt1050_flexspi_nor_config.h | 10 +++++----- .../evkmimxrt1060_flexspi_nor_config.h | 10 +++++----- .../evkmimxrt1064_flexspi_nor_config.h | 10 +++++----- .../boards/teensy_40/teensy40_flexspi_nor_config.h | 10 +++++----- .../boards/teensy_41/teensy41_flexspi_nor_config.h | 10 +++++----- hw/bsp/imxrt/family.mk | 2 +- hw/bsp/lpc54/family.c | 4 ++-- hw/bsp/lpc55/family.c | 4 ++-- hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld | 2 +- hw/bsp/rp2040/family.c | 2 +- .../stm32f070rbnucleo/stm32F070rbtx_flash.ld | 2 +- .../boards/stm32f072disco/STM32F072RBTx_FLASH.ld | 2 +- .../boards/stm32f103_bluepill/STM32F103X8_FLASH.ld | 2 +- .../boards/stm32f103_mini_2/STM32F103XC_FLASH.ld | 2 +- hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld | 2 +- hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld | 2 +- .../feather_stm32f405/STM32F405RGTx_FLASH.ld | 2 +- .../boards/pyboardv11/STM32F405RGTx_FLASH.ld | 2 +- .../stm32f401blackpill/STM32F401VCTx_FLASH.ld | 2 +- hw/bsp/stm32f4/boards/stm32f401blackpill/board.h | 2 +- .../boards/stm32f407disco/STM32F407VGTx_FLASH.ld | 2 +- .../stm32f411blackpill/STM32F411CEUx_FLASH.ld | 2 +- hw/bsp/stm32f4/boards/stm32f411blackpill/board.h | 2 +- .../boards/stm32f411disco/STM32F411VETx_FLASH.ld | 2 +- .../boards/stm32f412disco/STM32F412ZGTx_FLASH.ld | 2 +- .../boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld | 2 +- .../boards/stlinkv3mini/STM32F723xE_FLASH.ld | 2 +- .../boards/stm32f723disco/STM32F723xE_FLASH.ld | 2 +- .../boards/stm32f746disco/STM32F746ZGTx_FLASH.ld | 2 +- .../boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld | 2 +- .../boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld | 2 +- .../boards/stm32f769disco/STM32F769ZITx_FLASH.ld | 2 +- hw/bsp/stm32g4/boards/stm32g474nucleo/board.h | 4 ++-- .../boards/stm32h743eval/stm32h743xx_flash.ld | 2 +- .../boards/stm32h743nucleo/stm32h743xx_flash.ld | 2 +- .../waveshare_openh743i/STM32H743IITX_FLASH.ld | 2 +- hw/bsp/stm32h7/boards/waveshare_openh743i/board.h | 2 +- .../boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld | 2 +- hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld | 2 +- .../boards/stm32l476disco/STM32L476VGTx_FLASH.ld | 2 +- .../boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld | 2 +- hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h | 4 ++-- hw/bsp/tm4c123/family.c | 2 +- lib/SEGGER_RTT/RTT/SEGGER_RTT.c | 2 +- lib/networking/dnserver.c | 8 ++++---- lib/networking/ndis.h | 2 +- lib/networking/rndis_reports.c | 2 +- src/class/cdc/cdc.h | 2 +- src/class/cdc/cdc_rndis_host.c | 2 +- src/class/hid/hid_host.h | 2 +- src/class/msc/msc_host.c | 4 ++-- src/class/msc/msc_host.h | 2 +- src/class/net/ecm_rndis_device.c | 2 +- src/class/usbtmc/usbtmc.h | 2 +- src/class/usbtmc/usbtmc_device.h | 2 +- src/common/tusb_fifo.c | 8 ++++---- src/common/tusb_fifo.h | 4 ++-- src/device/usbd.h | 2 +- src/host/usbh.c | 4 ++-- src/portable/bridgetek/ft9xx/dcd_ft9xx.c | 6 +++--- src/portable/ehci/ehci.c | 4 ++-- src/portable/ehci/ehci.h | 10 +++++----- src/portable/espressif/esp32sx/dcd_esp32sx.c | 2 +- src/portable/microchip/pic32mz/usbhs_registers.h | 6 +++--- src/portable/microchip/samx7x/dcd_samx7x.c | 6 +++--- src/portable/nuvoton/nuc505/dcd_nuc505.c | 2 +- src/portable/ohci/ohci.c | 2 +- src/portable/ohci/ohci.h | 2 +- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 2 +- src/portable/sunxi/dcd_sunxi_musb.c | 2 +- src/portable/sunxi/musb_def.h | 2 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 2 +- src/portable/synopsys/dwc2/dwc2_stm32.h | 2 +- 90 files changed, 160 insertions(+), 160 deletions(-) (limited to 'src') diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml index 2958d3b12..8c39b95e1 100644 --- a/.github/ISSUE_TEMPLATE/bug_report.yml +++ b/.github/ISSUE_TEMPLATE/bug_report.yml @@ -64,7 +64,7 @@ body: placeholder: | Attach your debug log txt file here, where the issue occurred, best with comments to explain the actual events. - Note1: Please DO NOT paste your lengthy log contents here since it hurts the readibility. + Note1: Please DO NOT paste your lengthy log contents here since it hurts the readability. Note2: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h. More information can be found at [example's readme](https://github.com/hathach/tinyusb/blob/master/docs/getting_started.md) validations: diff --git a/docs/contributing/porting.rst b/docs/contributing/porting.rst index 7e9e462f0..710af51c3 100644 --- a/docs/contributing/porting.rst +++ b/docs/contributing/porting.rst @@ -195,7 +195,7 @@ Others (like the nRF52) may need each USB packet queued individually. To make th some state for yourself and queue up an intermediate USB packet from the interrupt handler. Once the transaction is going, the interrupt handler will notify TinyUSB of transfer completion. -During transmission, the IN data buffer is guarenteed to remain unchanged in memory until the ``dcd_xfer_complete`` function is called. +During transmission, the IN data buffer is guaranteed to remain unchanged in memory until the ``dcd_xfer_complete`` function is called. The dcd_edpt_xfer function must never add zero-length-packets (ZLP) on its own to a transfer. If a ZLP is required, then it must be explicitly sent by the stack calling dcd_edpt_xfer(), by calling dcd_edpt_xfer() a second time with len=0. @@ -238,4 +238,4 @@ Use `WireShark `_ or `a Beagle PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK; CLOCK_DisableClock(kCLOCK_Usbhsl0); /* disable usb0 host clock */ @@ -182,7 +182,7 @@ void board_init(void) // Port1 is High Speed POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); - /*According to reference mannual, device mode setting has to be set by access usb host register */ + /*According to reference manual, device mode setting has to be set by access usb host register */ CLOCK_EnableClock(kCLOCK_Usbh1); /* enable usb1 host clock */ USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; CLOCK_DisableClock(kCLOCK_Usbh1); /* enable usb1 host clock */ diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c index e7aed5759..5b6c56dd3 100644 --- a/hw/bsp/lpc55/family.c +++ b/hw/bsp/lpc55/family.c @@ -192,7 +192,7 @@ void board_init(void) CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); - /*According to reference mannual, device mode setting has to be set by access usb host register */ + /*According to reference manual, device mode setting has to be set by access usb host register */ CLOCK_EnableClock(kCLOCK_Usbhsl0); // enable usb0 host clock USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK; CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock @@ -213,7 +213,7 @@ void board_init(void) RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn); RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn); - /* According to reference mannual, device mode setting has to be set by access usb host register */ + /* According to reference manual, device mode setting has to be set by access usb host register */ CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld index d96d6e43d..0b45ee7bd 100644 --- a/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld +++ b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld @@ -126,7 +126,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index 26008168d..f7ee56990 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -226,6 +226,6 @@ int board_getchar(void) //--------------------------------------------------------------------+ // USB Interrupt Handler -// rp2040 implementation will install approriate handler when initializing +// rp2040 implementation will install appropriate handler when initializing // tinyusb. There is no need to forward IRQ from application //--------------------------------------------------------------------+ diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld index 59e18f375..4a6491510 100644 --- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld +++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld @@ -165,7 +165,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld b/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld index 8d31f6a00..f0879e929 100644 --- a/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld +++ b/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld b/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld index ca1804905..c434ca038 100644 --- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld +++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld b/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld index da40d1eb2..da637d1b0 100644 --- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld +++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld b/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld index 29e387f28..5010435ae 100644 --- a/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld +++ b/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld b/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld index ca9046d29..7f46c71b2 100644 --- a/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld +++ b/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld @@ -150,7 +150,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld b/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld index 57ef61e26..9eb53bcc0 100644 --- a/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld @@ -150,7 +150,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld b/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld index 57ef61e26..9eb53bcc0 100644 --- a/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld @@ -150,7 +150,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld index f51f1ab41..2bc5f6c14 100644 --- a/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h index 0f820512c..e1fef7277 100644 --- a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h +++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h @@ -93,7 +93,7 @@ static inline void board_clock_init(void) static inline void board_vbus_sense_init(void) { - // Blackpill doens't use VBUS sense (B device) explicitly disable it + // Blackpill doesn't use VBUS sense (B device) explicitly disable it USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld index c41602720..aac6577ea 100644 --- a/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld @@ -150,7 +150,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld index efea1e067..56dcea605 100644 --- a/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h index 0f820512c..e1fef7277 100644 --- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h +++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h @@ -93,7 +93,7 @@ static inline void board_clock_init(void) static inline void board_vbus_sense_init(void) { - // Blackpill doens't use VBUS sense (B device) explicitly disable it + // Blackpill doesn't use VBUS sense (B device) explicitly disable it USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld index 3a0ce526f..4477229ea 100644 --- a/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld index b00b5dbe0..2372cc1d9 100644 --- a/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld index b00b5dbe0..2372cc1d9 100644 --- a/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld b/hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld index 8645ce5c5..f4be85703 100644 --- a/hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld +++ b/hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/STM32F723xE_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f723disco/STM32F723xE_FLASH.ld index 8645ce5c5..f4be85703 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/STM32F723xE_FLASH.ld +++ b/hw/bsp/stm32f7/boards/stm32f723disco/STM32F723xE_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/STM32F746ZGTx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f746disco/STM32F746ZGTx_FLASH.ld index 045ec76f9..eeb0e29f3 100644 --- a/hw/bsp/stm32f7/boards/stm32f746disco/STM32F746ZGTx_FLASH.ld +++ b/hw/bsp/stm32f7/boards/stm32f746disco/STM32F746ZGTx_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld index b434a01b7..e1e60bc78 100644 --- a/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld +++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld index 0b6d5a494..3785f9cbf 100644 --- a/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld +++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/STM32F769ZITx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f769disco/STM32F769ZITx_FLASH.ld index 378ed80dd..520a75539 100644 --- a/hw/bsp/stm32f7/boards/stm32f769disco/STM32F769ZITx_FLASH.ld +++ b/hw/bsp/stm32f7/boards/stm32f769disco/STM32F769ZITx_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h index eab0bd5f0..aa2bf20bb 100644 --- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h +++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h @@ -66,7 +66,7 @@ static inline void board_clock_init(void) // Configure the main internal regulator output voltage HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); - // Initializes the CPU, AHB and APB busses clocks + // Initializes the CPU, AHB and APB buses clocks RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; @@ -79,7 +79,7 @@ static inline void board_clock_init(void) RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; HAL_RCC_OscConfig(&RCC_OscInitStruct); - // Initializes the CPU, AHB and APB busses clocks + // Initializes the CPU, AHB and APB buses clocks RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld b/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld index 59b9ff4df..7ee40671c 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld +++ b/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld @@ -134,7 +134,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld b/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld index 59b9ff4df..7ee40671c 100644 --- a/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld +++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld @@ -134,7 +134,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld b/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld index 73d2dedb2..e99bb977b 100644 --- a/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld +++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld @@ -138,7 +138,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h index 09442c233..2b072e07c 100644 --- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h +++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h @@ -186,7 +186,7 @@ static inline void timer_board_delay(TIM_HandleTypeDef* tim_hdl, uint32_t ms) static inline void board_stm32h7_post_init(void) { - // walkaround for reseting the ULPI PHY using Timer since systick is not + // walkaround for resetting the ULPI PHY using Timer since systick is not // available when RTOS is used. // Init timer diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld b/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld index 1bc16cc7b..dfefe59f1 100644 --- a/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld +++ b/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld b/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld index 787418e09..79427d80b 100644 --- a/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld +++ b/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld index 98f468ac0..d6865f49d 100644 --- a/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld +++ b/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld @@ -144,7 +144,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld index f93a16041..f77c72d1b 100644 --- a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld +++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld @@ -130,7 +130,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h index f42c7d6dd..ea975df03 100644 --- a/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h +++ b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h @@ -59,7 +59,7 @@ static inline void board_clock_init(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - // Initializes the CPU, AHB and APB busses clocks + // Initializes the CPU, AHB and APB buses clocks RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; @@ -72,7 +72,7 @@ static inline void board_clock_init(void) RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV3; HAL_RCC_OscConfig(&RCC_OscInitStruct); - // Initializes the CPU, AHB and APB busses clocks + // Initializes the CPU, AHB and APB buses clocks RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c123/family.c index b0947d6c4..87b94289b 100644 --- a/hw/bsp/tm4c123/family.c +++ b/hw/bsp/tm4c123/family.c @@ -39,7 +39,7 @@ static void board_uart_init (void) UART0->LCRH = (0x3 << 5); // 8-bit, no parity, 1 stop bit UART0->CC = 0x0; // Configure the UART clock source as system clock - UART0->CTL = (1 << 0) | (1 << 8) | (1 << 9); // UART0 Enable, Transmit Enable, Recieve Enable + UART0->CTL = (1 << 0) | (1 << 8) | (1 << 9); // UART0 Enable, Transmit Enable, Receive Enable } static void initialize_board_led (GPIOA_Type *port, uint8_t PinMsk, uint8_t dirmsk) diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c index 3ad2b1a12..a7ae013dd 100644 --- a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c +++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c @@ -1404,7 +1404,7 @@ int SEGGER_RTT_GetKey(void) { * SEGGER_RTT_WaitKey * * Function description -* Waits until at least one character is avaible in the SEGGER RTT buffer. +* Waits until at least one character is available in the SEGGER RTT buffer. * Once a character is available, it is read and this function returns. * * Return value diff --git a/lib/networking/dnserver.c b/lib/networking/dnserver.c index e4e7c3492..539cc2cea 100644 --- a/lib/networking/dnserver.c +++ b/lib/networking/dnserver.c @@ -93,11 +93,11 @@ static uint16_t get_uint16(const uint8_t *pnt) static int parse_next_query(void *data, int size, dns_query_t *query) { int len; - int lables; + int labels; uint8_t *ptr; len = 0; - lables = 0; + labels = 0; ptr = (uint8_t *)data; while (true) @@ -107,7 +107,7 @@ static int parse_next_query(void *data, int size, dns_query_t *query) lable_len = *ptr++; size--; if (lable_len == 0) break; - if (lables > 0) + if (labels > 0) { if (len == DNS_MAX_HOST_NAME_LEN) return -2; query->name[len++] = '.'; @@ -118,7 +118,7 @@ static int parse_next_query(void *data, int size, dns_query_t *query) len += lable_len; ptr += lable_len; size -= lable_len; - lables++; + labels++; } if (size < 4) return -1; diff --git a/lib/networking/ndis.h b/lib/networking/ndis.h index 1c737574c..06258e6bb 100644 --- a/lib/networking/ndis.h +++ b/lib/networking/ndis.h @@ -22,7 +22,7 @@ * ntddndis.h modified by Benedikt Spranger * * Thanks to the cygwin development team, - * espacially to Casper S. Hornstrup + * especially to Casper S. Hornstrup * * THIS SOFTWARE IS NOT COPYRIGHTED * diff --git a/lib/networking/rndis_reports.c b/lib/networking/rndis_reports.c index ee611c883..d129466c8 100644 --- a/lib/networking/rndis_reports.c +++ b/lib/networking/rndis_reports.c @@ -220,7 +220,7 @@ static void rndis_handle_set_msg(void) case OID_802_3_MULTICAST_LIST: break; - /* Power Managment: fails for now */ + /* Power Management: fails for now */ case OID_PNP_ADD_WAKE_UP_PATTERN: case OID_PNP_REMOVE_WAKE_UP_PATTERN: case OID_PNP_ENABLE_WAKE_UP: diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index e345139ea..c428af865 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -193,7 +193,7 @@ typedef enum }cdc_management_request_t; //--------------------------------------------------------------------+ -// Management Elemenent Notification (Notification Endpoint) +// Management Element Notification (Notification Endpoint) //--------------------------------------------------------------------+ /// 6.3 Notification Codes diff --git a/src/class/cdc/cdc_rndis_host.c b/src/class/cdc/cdc_rndis_host.c index 8f28f51ac..44de85b45 100644 --- a/src/class/cdc/cdc_rndis_host.c +++ b/src/class/cdc/cdc_rndis_host.c @@ -117,7 +117,7 @@ void rndish_init(void) //------------- Task creation -------------// - //------------- semaphore creation for notificaiton pipe -------------// + //------------- semaphore creation for notification pipe -------------// for(uint8_t i=0; iMSC0CFG = SYS->MSC0CFG | MASK_SYS_MSC0CFG_DEV_RMWAKEUP; - // Atleast 2 ms of delay needed for RESUME Data K state. + // At least 2 ms of delay needed for RESUME Data K state. delayms(2); SYS->MSC0CFG &= ~MASK_SYS_MSC0CFG_DEV_RMWAKEUP; @@ -720,7 +720,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) else total_ram = USBD_RAMTOTAL_OUT; // Work out how much has been allocated to existing endpoints. - // The total RAM allocated shoudl alsyes be a positive number as this + // The total RAM allocated should always be a positive number as this // algorithm should not let it go below zero. for (int i = 1; i < USBD_MAX_ENDPOINT_COUNT; i++) { @@ -976,7 +976,7 @@ void dcd_int_handler(uint8_t rhport) USBD_EP_SR_REG(USBD_EP_0) = MASK_USBD_EP0SR_STALL; } - // Host has sent a SETUP packet. Recieve this into the setup packet store. + // Host has sent a SETUP packet. Receive this into the setup packet store. _ft90x_dusb_out(USBD_EP_0, (uint8_t *)_ft90x_setup_packet, sizeof(USB_device_request)); // Send the packet to tinyusb. diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 76ba2a921..80f616478 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -199,7 +199,7 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr) #pragma GCC diagnostic pop if ( qhd->dev_addr == dev_addr ) { - // TODO deactive all TD, wait for QHD to inactive before removal + // TODO deactivate all TD, wait for QHD to inactive before removal prev->address = qhd->next.address; // EHCI 4.8.2 link the removed qhd to async head (which always reachable by Host Controller) @@ -839,7 +839,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c if (TUSB_SPEED_HIGH == p_qhd->ep_speed) { TU_ASSERT( interval <= 16, ); - if ( interval < 4) // sub milisecond interval + if ( interval < 4) // sub millisecond interval { p_qhd->interval_ms = 0; p_qhd->int_smask = (interval == 1) ? TU_BIN8(11111111) : diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h index ff9ae12e7..36f8649be 100644 --- a/src/portable/ehci/ehci.h +++ b/src/portable/ehci/ehci.h @@ -114,7 +114,7 @@ typedef struct volatile uint32_t current_page : 3 ; ///< Index into the qTD buffer pointer list uint32_t int_on_complete : 1 ; ///< Interrupt on complete volatile uint32_t total_bytes : 15 ; ///< Transfer bytes, decreased during transaction - volatile uint32_t data_toggle : 1 ; ///< Data Toogle bit + volatile uint32_t data_toggle : 1 ; ///< Data Toggle bit /// Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page @@ -160,7 +160,7 @@ typedef struct TU_ATTR_ALIGNED(32) uint8_t used; uint8_t removing; // removed from asyn list, waiting for async advance uint8_t pid; - uint8_t interval_ms; // polling interval in frames (or milisecond) + uint8_t interval_ms; // polling interval in frames (or millisecond) uint16_t total_xferred_bytes; // number of bytes xferred until a qtd with ioc bit set uint8_t reserved2[2]; @@ -225,7 +225,7 @@ typedef struct TU_ATTR_ALIGNED(32) uint16_t reserved ; ///< reserved // Word 3: siTD Transfer Status and Control - // Status [7:0] TODO indentical to qTD Token'status --> refractor later + // Status [7:0] TODO identical to qTD Token'status --> refactor later volatile uint32_t : 1 ; // reserved volatile uint32_t split_state : 1 ; volatile uint32_t missed_uframe : 1 ; @@ -350,8 +350,8 @@ typedef volatile struct uint32_t periodic_status : 1 ; ///< Periodic schedule status uint32_t async_status : 1 ; ///< Async schedule status uint32_t : 2 ; - uint32_t nxp_int_async : 1 ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected andthe packet is on the asynchronous schedule. - uint32_t nxp_int_period : 1 ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the periodic schedule. + uint32_t nxp_int_async : 1 ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. + uint32_t nxp_int_period : 1 ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. uint32_t : 12 ; }status_bm; }; diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c index 0b75af627..41240f737 100644 --- a/src/portable/espressif/esp32sx/dcd_esp32sx.c +++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c @@ -741,7 +741,7 @@ static void handle_epin_ints(void) // XFER Timeout if (USB0.in_ep_reg[n].diepint & USB_D_TIMEOUT0_M) { - // Clear interrupt or enpoint will hang. + // Clear interrupt or endpoint will hang. USB0.in_ep_reg[n].diepint = USB_D_TIMEOUT0_M; // Maybe retry? } diff --git a/src/portable/microchip/pic32mz/usbhs_registers.h b/src/portable/microchip/pic32mz/usbhs_registers.h index 757e3f083..93b552322 100644 --- a/src/portable/microchip/pic32mz/usbhs_registers.h +++ b/src/portable/microchip/pic32mz/usbhs_registers.h @@ -21,16 +21,16 @@ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. *******************************************************************************/ /******************************************************************************* - USBHS Peripheral Library Register Defintions + USBHS Peripheral Library Register Definitions File Name: usbhs_registers.h Summary: - USBHS PLIB Register Defintions + USBHS PLIB Register Definitions Description: - This file contains the constants and defintions which are required by the + This file contains the constants and definitions which are required by the the USBHS library. *******************************************************************************/ diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c index 7507c0f69..24657872b 100644 --- a/src/portable/microchip/samx7x/dcd_samx7x.c +++ b/src/portable/microchip/samx7x/dcd_samx7x.c @@ -42,7 +42,7 @@ # define USE_SOF 0 #endif -// Dual bank can imporve performance, but need 2 times bigger packet buffer +// Dual bank can improve performance, but need 2 times bigger packet buffer // As SAM7x has only 4KB packet buffer, use with caution ! // Enable in FS mode as packets are smaller #ifndef USE_DUAL_BANK @@ -644,7 +644,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t } __set_PRIMASK(irq_state); - // Here a ZLP has been recieved + // Here a ZLP has been received // and the DMA transfer must be not started. // It is the end of transfer return false; @@ -734,7 +734,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 } __set_PRIMASK(irq_state); - // Here a ZLP has been recieved + // Here a ZLP has been received // and the DMA transfer must be not started. // It is the end of transfer return false; diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c index 886720e33..3fa7c1ec1 100644 --- a/src/portable/nuvoton/nuc505/dcd_nuc505.c +++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c @@ -181,7 +181,7 @@ static void dcd_userEP_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep) ep->EPINTEN = USBD_EPINTEN_TXPKIEN_Msk; } - /* provided buffers are thankfully 32-bit aligned, allowing most data to be transfered as 32-bit */ + /* provided buffers are thankfully 32-bit aligned, allowing most data to be transferred as 32-bit */ #if 0 // TODO support dcd_edpt_xfer_fifo API if (xfer->ff) { diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 3e523ebc2..228da6ae0 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -165,7 +165,7 @@ bool hcd_init(uint8_t rhport) //------------- Data Structure init -------------// tu_memclr(&ohci_data, sizeof(ohci_data_t)); for(uint8_t i=0; i<32; i++) - { // assign all interrupt pointes to period head ed + { // assign all interrupt pointers to period head ed ohci_data.hcca.interrupt_table[i] = (uint32_t) &ohci_data.period_head_ed; } diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h index 9fc954c8f..f40ae24cc 100644 --- a/src/portable/ohci/ohci.h +++ b/src/portable/ohci/ohci.h @@ -34,7 +34,7 @@ //--------------------------------------------------------------------+ // OHCI CONFIGURATION & CONSTANTS //--------------------------------------------------------------------+ -#define HOST_HCD_XFER_INTERRUPT // TODO interrupt is used widely, should always be enalbed +#define HOST_HCD_XFER_INTERRUPT // TODO interrupt is used widely, should always be enabled #define OHCI_PERIODIC_LIST (defined HOST_HCD_XFER_INTERRUPT || defined HOST_HCD_XFER_ISOCHRONOUS) // TODO merge OHCI with EHCI diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index c88a8a3a2..54c3c95e7 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -122,7 +122,7 @@ (TU_CHECK_MCU(OPT_MCU_STM32L4) && defined(STM32L4_FSDEV)) \ ) -// In order to reduce the dependance on HAL, we undefine this. +// In order to reduce the dependence on HAL, we undefine this. // Some definitions are copied to our private include file. #undef USE_HAL_DRIVER diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c index a0be846a5..2d0e379ad 100644 --- a/src/portable/sunxi/dcd_sunxi_musb.c +++ b/src/portable/sunxi/dcd_sunxi_musb.c @@ -243,7 +243,7 @@ static void USBC_Dev_SetAddress(u8 address) static void __USBC_Dev_Tx_SendStall(void) { - //send stall, and fifo is flushed automaticly + //send stall, and fifo is flushed automatically USBC_REG_set_bit_w(USBC_BP_TXCSR_D_SEND_STALL, USBC_REG_TXCSR(USBC0_BASE)); } static u32 __USBC_Dev_Tx_IsEpStall(void) diff --git a/src/portable/sunxi/musb_def.h b/src/portable/sunxi/musb_def.h index 602b4f113..53da5ded2 100644 --- a/src/portable/sunxi/musb_def.h +++ b/src/portable/sunxi/musb_def.h @@ -93,7 +93,7 @@ #define USBC1_BASE 0x01c14000 #define USBC2_BASE 0x01c1E000 -//Some reg whithin musb +//Some reg within musb #define USBPHY_CLK_REG 0x01c200CC #define USBPHY_CLK_RST_BIT 0 #define USBPHY_CLK_GAT_BIT 1 diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index f5ecdfe4f..b53735a5e 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -1003,7 +1003,7 @@ static void handle_rxflvl_irq(uint8_t rhport) switch ( pktsts ) { - // Global OUT NAK: do nothign + // Global OUT NAK: do nothing case GRXSTS_PKTSTS_GLOBALOUTNAK: break; case GRXSTS_PKTSTS_SETUPRX: diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index ea786362e..b63d1fcd0 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -116,7 +116,7 @@ static const dwc2_controller_t _dwc2_controller[] = // //--------------------------------------------------------------------+ -// SystemCoreClock is alrady included by family header +// SystemCoreClock is already included by family header // extern uint32_t SystemCoreClock; TU_ATTR_ALWAYS_INLINE -- cgit v1.3.1 From 43b255f413e08b9e567a23b24701efbdaebcb824 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 4 Dec 2022 18:51:52 +0700 Subject: more typos --- docs/contributing/index.rst | 2 +- examples/device/hid_generic_inout/hid_test.py | 4 ++-- hw/bsp/gd32vf103/family.c | 2 +- hw/bsp/sltb009a/sltb009a.c | 2 +- hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld | 4 ++-- hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld | 2 +- hw/bsp/stm32u5/boards/stm32u575eval/board.h | 4 ++-- src/class/hid/hid_device.h | 2 +- src/class/usbtmc/usbtmc_device.c | 2 +- src/portable/dialog/da146xx/dcd_da146xx.c | 2 +- src/portable/nordic/nrf5x/dcd_nrf5x.c | 2 +- src/portable/renesas/usba/hcd_usba.c | 2 +- src/portable/valentyusb/eptri/dcd_eptri.c | 2 +- 13 files changed, 16 insertions(+), 16 deletions(-) (limited to 'src') diff --git a/docs/contributing/index.rst b/docs/contributing/index.rst index c572894ad..7ff79cb32 100644 --- a/docs/contributing/index.rst +++ b/docs/contributing/index.rst @@ -6,7 +6,7 @@ Contributing can be highly rewarding, but it can also be frustrating at times. It takes time to review patches, and as this is an open source project, that sometimes can take a while. The reviewing process depends on the availability of the maintainers, who may not be always available. Please try to be -understanding throught the process. +understanding through the process. There a few guidelines you need to keep in mind when contributing. Please have a look at them as that will make the contribution process easier for all diff --git a/examples/device/hid_generic_inout/hid_test.py b/examples/device/hid_generic_inout/hid_test.py index 21fd3f421..5bdba9db0 100644 --- a/examples/device/hid_generic_inout/hid_test.py +++ b/examples/device/hid_generic_inout/hid_test.py @@ -13,8 +13,8 @@ for vid in USB_VID: if dev: while True: # Get input from console and encode to UTF8 for array of chars. - # hid generic inout is single report therefore by HIDAPI requirement - # it must be preceeded with 0x00 as dummy reportID + # hid generic in/out is single report therefore by HIDAPI requirement + # it must be preceded, with 0x00 as dummy reportID str_out = b'\x00' str_out += input("Send text to HID Device : ").encode('utf-8') dev.write(str_out) diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c index 5427c8dd0..60a326d27 100644 --- a/hw/bsp/gd32vf103/family.c +++ b/hw/bsp/gd32vf103/family.c @@ -112,7 +112,7 @@ void board_init(void) { otg_core_regs->GCCFG &= ~GCCFG_VBUSIG; #endif - /* Enable interrupts globaly */ + /* Enable interrupts globally */ __enable_irq(); } diff --git a/hw/bsp/sltb009a/sltb009a.c b/hw/bsp/sltb009a/sltb009a.c index b929adb13..b5eb5ed5d 100644 --- a/hw/bsp/sltb009a/sltb009a.c +++ b/hw/bsp/sltb009a/sltb009a.c @@ -397,7 +397,7 @@ void cmu_init(void) CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO; while((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) != CMU_HFCLKSTATUS_SELECTED_HFXO); - // Calibrate HFRCO for 72MHz and enable tunning by PLL + // Calibrate HFRCO for 72MHz and enable tuning by PLL cmu_hfrco_calib((DEVINFO->HFRCOCAL16) | CMU_HFRCOCTRL_FINETUNINGEN); // Setup the PLL diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld index 935d97c87..9c327483b 100644 --- a/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld +++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld @@ -16,7 +16,7 @@ ** ** Target : STMicroelectronics STM32 ** -** Distribution: The file is distributed as is, without any warranty +** Distribution: The file is distributed �as is,� without any warranty ** of any kind. ** ***************************************************************************** @@ -151,7 +151,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld index 28cd96131..d4b86b3e3 100644 --- a/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld +++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld @@ -145,7 +145,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.h b/hw/bsp/stm32u5/boards/stm32u575eval/board.h index 5c348b812..5562b95a8 100644 --- a/hw/bsp/stm32u5/boards/stm32u575eval/board.h +++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.h @@ -69,7 +69,7 @@ static inline void board_clock_init(void) */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB buses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -92,7 +92,7 @@ static inline void board_clock_init(void) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h index 3143b1024..fa41ebf8a 100644 --- a/src/class/hid/hid_device.h +++ b/src/class/hid/hid_device.h @@ -182,7 +182,7 @@ static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y HID_COLLECTION ( HID_COLLECTION_APPLICATION ) ,\ /* Report ID if any */\ __VA_ARGS__ \ - /* 8 bits Modifier Keys (Shfit, Control, Alt) */ \ + /* 8 bits Modifier Keys (Shift, Control, Alt) */ \ HID_USAGE_PAGE ( HID_USAGE_PAGE_KEYBOARD ) ,\ HID_USAGE_MIN ( 224 ) ,\ HID_USAGE_MAX ( 231 ) ,\ diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index af4a92732..0f6d3f60d 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -599,7 +599,7 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request // At this point, a transfer MAY be in progress. Based on USB spec, when clearing bulk EP HALT, // the EP transfer buffer needs to be cleared and DTOG needs to be reset, even if - // the EP is not halted. The only USBD API interface to do this is to stall and then unstall the EP. + // the EP is not halted. The only USBD API interface to do this is to stall and then un-stall the EP. if(ep_addr == usbtmc_state.ep_bulk_out) { criticalEnter(); diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index 0bb8b6e41..961da81d6 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -243,7 +243,7 @@ static struct // Converts xfer pointer to epnum (0,1,2,3) regardless of xfer direction #define XFER_EPNUM(xfer) ((xfer - &_dcd.xfer_status[0][0]) >> 1) -// Converts xfer pinter to EPx_REGS pointer (returns same pointer for IN and OUT with same endpoint number) +// Converts xfer pointer to EPx_REGS pointer (returns same pointer for IN and OUT with same endpoint number) #define XFER_REGS(xfer) ep_regs[XFER_EPNUM(xfer)] // Converts epnum (0,1,2,3) to EPx_REGS pointer #define EPNUM_REGS(epnum) ep_regs[epnum] diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index ca37d799f..afc14b010 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -170,7 +170,7 @@ static void xact_out_dma(uint8_t epnum) uint32_t xact_len; // DMA can't be active during read of SIZE.EPOUT or SIZE.ISOOUT, so try to lock, - // If already running deffer call regardless if it was called from ISR or task, + // If already running defer call regardless if it was called from ISR or task, if ( atomic_flag_test_and_set(&_dcd.dma_running) ) { usbd_defer_func((osal_task_func_t)xact_out_dma_wrapper, (void *)(uint32_t)epnum, is_in_isr()); diff --git a/src/portable/renesas/usba/hcd_usba.c b/src/portable/renesas/usba/hcd_usba.c index 5246ecb94..18cd5f148 100644 --- a/src/portable/renesas/usba/hcd_usba.c +++ b/src/portable/renesas/usba/hcd_usba.c @@ -600,7 +600,7 @@ uint32_t hcd_frame_number(uint8_t rhport) bool hcd_port_connect_status(uint8_t rhport) { (void)rhport; - return USB0.INTSTS1.BIT.ATTCH ? true: false; + return USB0.INTSTS1.BIT.ATTCH ? true : false; } void hcd_port_reset(uint8_t rhport) diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c index e368b5f39..a3f228dd9 100644 --- a/src/portable/valentyusb/eptri/dcd_eptri.c +++ b/src/portable/valentyusb/eptri/dcd_eptri.c @@ -465,7 +465,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) enable = 1; usb_out_ctrl_write((0 << CSR_USB_OUT_CTRL_STALL_OFFSET) | (enable << CSR_USB_OUT_CTRL_ENABLE_OFFSET) | tu_edpt_number(ep_addr)); } - // IN endpoints will get unstalled when more data is written. + // IN endpoints will get un-stalled when more data is written. } bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) -- cgit v1.3.1 From de5a67bf3b8737a580539c5fbc6a054c90e4a084 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 5 Dec 2022 12:09:41 +0700 Subject: clean osal_freertos, update freertos examples to work with configSUPPORT_DYNAMIC_ALLOCATION only note: for example to build with configSUPPORT_STATIC_ALLOCATION = 0, one of heap_n.c must be included in makefile/cmake --- examples/device/cdc_msc_freertos/Makefile | 11 ++- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- examples/device/cdc_msc_freertos/src/main.c | 24 ++++--- examples/device/hid_composite_freertos/Makefile | 11 ++- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 7 +- examples/device/hid_composite_freertos/src/main.c | 24 ++++--- src/osal/osal_freertos.h | 84 +++++++++++----------- src/portable/ehci/ehci.c | 2 +- 8 files changed, 100 insertions(+), 65 deletions(-) (limited to 'src') diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile index 3352dd37d..ff4b41108 100644 --- a/examples/device/cdc_msc_freertos/Makefile +++ b/examples/device/cdc_msc_freertos/Makefile @@ -29,8 +29,15 @@ SRC_C += \ $(FREERTOS_SRC)/timers.c \ $(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c)) -# Suppress FreeRTOS warnings -CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls +# include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1 +# SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c +# CFLAGS += -Wno-error=sign-compare + +# Suppress FreeRTOSConfig.h warnings +CFLAGS += -Wno-error=redundant-decls + +# Suppress FreeRTOS source warnings +CFLAGS += -Wno-error=cast-qual # FreeRTOS (lto + Os) linker issue LDFLAGS += -Wl,--undefined=vTaskSwitchContext diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index 6a3630dbc..968c59749 100644 --- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -69,7 +69,7 @@ #define configTICK_RATE_HZ ( 1000 ) #define configMAX_PRIORITIES ( 5 ) #define configMINIMAL_STACK_SIZE ( 128 ) -#define configTOTAL_HEAP_SIZE ( 0*1024 ) // dynamic is not used +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) #define configMAX_TASK_NAME_LEN 16 #define configUSE_16_BIT_TICKS 0 #define configIDLE_SHOULD_YIELD 1 diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index 755220c13..cfb14aa2b 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -51,6 +51,8 @@ #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1) #endif +#define CDC_STACK_SZIE configMINIMAL_STACK_SIZE + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ @@ -66,19 +68,18 @@ enum { BLINK_SUSPENDED = 2500, }; -// static timer +// static timer & task +#if configSUPPORT_STATIC_ALLOCATION StaticTimer_t blinky_tmdef; -TimerHandle_t blinky_tm; -// static task StackType_t usb_device_stack[USBD_STACK_SIZE]; StaticTask_t usb_device_taskdef; -// static task for cdc -#define CDC_STACK_SZIE configMINIMAL_STACK_SIZE StackType_t cdc_stack[CDC_STACK_SZIE]; StaticTask_t cdc_taskdef; +#endif +TimerHandle_t blinky_tm; void led_blinky_cb(TimerHandle_t xTimer); void usb_device_task(void* param); @@ -92,15 +93,22 @@ int main(void) { board_init(); +#if configSUPPORT_STATIC_ALLOCATION // soft timer for blinky blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef); - xTimerStart(blinky_tm, 0); // Create a task for tinyusb device stack - (void) xTaskCreateStatic( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef); + xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef); // Create CDC task - (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef); + xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef); +#else + blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb); + xTaskCreate( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL); + xTaskCreate( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL); +#endif + + xTimerStart(blinky_tm, 0); // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile index 6c8c43ddd..9c66b896d 100644 --- a/examples/device/hid_composite_freertos/Makefile +++ b/examples/device/hid_composite_freertos/Makefile @@ -28,8 +28,15 @@ SRC_C += \ $(FREERTOS_SRC)/timers.c \ $(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c)) -# Suppress FreeRTOS warnings -CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls +# include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1 +# SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c +# CFLAGS += -Wno-error=sign-compare + +# Suppress FreeRTOSConfig.h warnings +CFLAGS += -Wno-error=redundant-decls + +# Suppress FreeRTOS source warnings +CFLAGS += -Wno-error=cast-qual # FreeRTOS (lto + Os) linker issue LDFLAGS += -Wl,--undefined=vTaskSwitchContext diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index bfdf1e926..968c59749 100644 --- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -46,13 +46,14 @@ #include "bsp/board_mcu.h" #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 -#error "ESP32-Sx should use IDF's FreeRTOSConfig.h" + #error "ESP32-Sx should use IDF's FreeRTOSConfig.h" #endif +// TODO fix later #if CFG_TUSB_MCU == OPT_MCU_MM32F327X - // TODO fix/remove later extern u32 SystemCoreClock; #else + // FIXME cause redundant-decls warnings extern uint32_t SystemCoreClock; #endif @@ -68,7 +69,7 @@ #define configTICK_RATE_HZ ( 1000 ) #define configMAX_PRIORITIES ( 5 ) #define configMINIMAL_STACK_SIZE ( 128 ) -#define configTOTAL_HEAP_SIZE ( 0*1024 ) // dynamic is not used +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) #define configMAX_TASK_NAME_LEN 16 #define configUSE_16_BIT_TICKS 0 #define configIDLE_SHOULD_YIELD 1 diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c index b67c10937..fb0d69258 100644 --- a/examples/device/hid_composite_freertos/src/main.c +++ b/examples/device/hid_composite_freertos/src/main.c @@ -53,6 +53,8 @@ #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1) #endif +#define HID_STACK_SZIE configMINIMAL_STACK_SIZE + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ @@ -68,19 +70,18 @@ enum { BLINK_SUSPENDED = 2500, }; -// static timer +// static timer & task +#if configSUPPORT_STATIC_ALLOCATION StaticTimer_t blinky_tmdef; -TimerHandle_t blinky_tm; -// static task StackType_t usb_device_stack[USBD_STACK_SIZE]; StaticTask_t usb_device_taskdef; -// static task for hid -#define HID_STACK_SZIE configMINIMAL_STACK_SIZE StackType_t hid_stack[HID_STACK_SZIE]; StaticTask_t hid_taskdef; +#endif +TimerHandle_t blinky_tm; void led_blinky_cb(TimerHandle_t xTimer); void usb_device_task(void* param); @@ -94,15 +95,22 @@ int main(void) { board_init(); +#if configSUPPORT_STATIC_ALLOCATION // soft timer for blinky blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef); - xTimerStart(blinky_tm, 0); // Create a task for tinyusb device stack - (void) xTaskCreateStatic( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef); + xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef); // Create HID task - (void) xTaskCreateStatic( hid_task, "hid", HID_STACK_SZIE, NULL, configMAX_PRIORITIES-2, hid_stack, &hid_taskdef); + xTaskCreateStatic(hid_task, "hid", HID_STACK_SZIE, NULL, configMAX_PRIORITIES-2, hid_stack, &hid_taskdef); +#else + blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb); + xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL); + xTaskCreate(hid_task, "hid", HID_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL); +#endif + + xTimerStart(blinky_tm, 0); // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index ccb98cc99..327aa9970 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -37,6 +37,43 @@ extern "C" { #endif +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF PROTYPES +//--------------------------------------------------------------------+ + +#if configSUPPORT_STATIC_ALLOCATION + typedef StaticSemaphore_t osal_semaphore_def_t; + typedef StaticSemaphore_t osal_mutex_def_t; +#else + // not used therefore defined to smallest possible type to save space + typedef uint8_t osal_semaphore_def_t; + typedef uint8_t osal_mutex_def_t; +#endif + +typedef SemaphoreHandle_t osal_semaphore_t; +typedef SemaphoreHandle_t osal_mutex_t; + +// _int_set is not used with an RTOS +#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \ + static _type _name##_##buf[_depth];\ + osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf }; + +typedef struct +{ + uint16_t depth; + uint16_t item_sz; + void* buf; +#if configSUPPORT_STATIC_ALLOCATION + StaticQueue_t sq; +#endif +}osal_queue_def_t; + +typedef QueueHandle_t osal_queue_t; + +//--------------------------------------------------------------------+ +// TASK API +//--------------------------------------------------------------------+ + TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec) { if (msec == OSAL_TIMEOUT_WAIT_FOREVER) return portMAX_DELAY; @@ -51,9 +88,6 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec) return ticks; } -//--------------------------------------------------------------------+ -// TASK API -//--------------------------------------------------------------------+ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { vTaskDelay( pdMS_TO_TICKS(msec) ); @@ -62,19 +96,13 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) //--------------------------------------------------------------------+ // Semaphore API //--------------------------------------------------------------------+ -#if configSUPPORT_STATIC_ALLOCATION == 1 -typedef StaticSemaphore_t osal_semaphore_def_t; -#else -typedef SemaphoreHandle_t osal_semaphore_def_t; -#endif -typedef SemaphoreHandle_t osal_semaphore_t; TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) { -#if configSUPPORT_STATIC_ALLOCATION == 1 +#if configSUPPORT_STATIC_ALLOCATION return xSemaphoreCreateBinaryStatic(semdef); #else - (void)(semdef); + (void) semdef; return xSemaphoreCreateBinary(); #endif } @@ -101,7 +129,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t se } } -TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec) +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) { return xSemaphoreTake(sem_hdl, _osal_ms2tick(msec)); } @@ -114,25 +142,18 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t c //--------------------------------------------------------------------+ // MUTEX API (priority inheritance) //--------------------------------------------------------------------+ -#if configSUPPORT_STATIC_ALLOCATION == 1 -typedef StaticSemaphore_t osal_mutex_def_t; -#else -typedef SemaphoreHandle_t osal_mutex_def_t; -#endif -typedef SemaphoreHandle_t osal_mutex_t; TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) { -#if configSUPPORT_STATIC_ALLOCATION == 1 +#if configSUPPORT_STATIC_ALLOCATION return xSemaphoreCreateMutexStatic(mdef); #else - (void)(mdef); + (void) mdef; return xSemaphoreCreateMutex(); #endif - } -TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) { return osal_semaphore_wait(mutex_hdl, msec); } @@ -146,26 +167,9 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd // QUEUE API //--------------------------------------------------------------------+ -// _int_set is not used with an RTOS -#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \ - static _type _name##_##buf[_depth];\ - osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf }; - -typedef struct -{ - uint16_t depth; - uint16_t item_sz; - void* buf; -#if configSUPPORT_STATIC_ALLOCATION == 1 - StaticQueue_t sq; -#endif -}osal_queue_def_t; - -typedef QueueHandle_t osal_queue_t; - TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) { -#if configSUPPORT_STATIC_ALLOCATION == 1 +#if configSUPPORT_STATIC_ALLOCATION return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq); #else return xQueueCreate(qdef->depth, qdef->item_sz); diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 361015964..76ba2a921 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -193,7 +193,7 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr) { // TODO check type for ISO iTD and siTD // TODO Suppress cast-align warning - #pragma GCC diagnostic push + #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wcast-align" ehci_qhd_t* qhd = (ehci_qhd_t*) list_next(prev); #pragma GCC diagnostic pop -- cgit v1.3.1 From d58120647aef366de7a57e40b2572da03efdb415 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 5 Dec 2022 13:18:05 +0700 Subject: rename to match fido sample uf2_hid..h --- src/class/hid/hid.h | 8 ++++---- src/class/hid/hid_device.h | 10 +++++----- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h index 296664f62..d9b0ead10 100644 --- a/src/class/hid/hid.h +++ b/src/class/hid/hid.h @@ -708,7 +708,7 @@ enum { HID_USAGE_PAGE_MSR = 0x8e, HID_USAGE_PAGE_CAMERA = 0x90, HID_USAGE_PAGE_ARCADE = 0x91, - HID_USAGE_PAGE_FIDO_ALLIANCE = 0xF1D0, + HID_USAGE_PAGE_FIDO = 0xF1D0, // FIDO alliance HID usage page HID_USAGE_PAGE_VENDOR = 0xFF00 // 0xFF00 - 0xFFFF }; @@ -848,9 +848,9 @@ enum /// HID Usage Table: FIDO Alliance Page (0xF1D0) enum { - HID_USAGE_FIDO_U2F_AUTHENTICATOR_DEVICE = 0x01, - HID_USAGE_FIDO_INPUT_REPORT_DATA = 0x20, - HID_USAGE_FIDO_OUTPUT_REPORT_DATA = 0x21 + HID_USAGE_FIDO_U2FHID = 0x01, // U2FHID usage for top-level collection + HID_USAGE_FIDO_DATA_IN = 0x20, // Raw IN data report + HID_USAGE_FIDO_DATA_OUT = 0x21 // Raw OUT data report }; /*-------------------------------------------------------------------- diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h index a9f47d644..025394126 100644 --- a/src/class/hid/hid_device.h +++ b/src/class/hid/hid_device.h @@ -356,20 +356,20 @@ static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y // - 1st parameter is report size, which is 64 bytes maximum in U2F // - 2nd parameter is HID_REPORT_ID(n) (optional) #define TUD_HID_REPORT_DESC_FIDO_U2F(report_size, ...) \ - HID_USAGE_PAGE_N ( HID_USAGE_PAGE_FIDO_ALLIANCE, 2 ) ,\ - HID_USAGE ( HID_USAGE_FIDO_U2F_AUTHENTICATOR_DEVICE ) ,\ - HID_COLLECTION ( HID_COLLECTION_APPLICATION ) ,\ + HID_USAGE_PAGE_N ( HID_USAGE_PAGE_FIDO, 2 ) ,\ + HID_USAGE ( HID_USAGE_FIDO_U2FHID ) ,\ + HID_COLLECTION ( HID_COLLECTION_APPLICATION ) ,\ /* Report ID if any */ \ __VA_ARGS__ \ /* Usage Data In */ \ - HID_USAGE ( HID_USAGE_FIDO_INPUT_REPORT_DATA ) ,\ + HID_USAGE ( HID_USAGE_FIDO_DATA_IN ) ,\ HID_LOGICAL_MIN ( 0 ) ,\ HID_LOGICAL_MAX_N ( 0xff, 2 ) ,\ HID_REPORT_SIZE ( 8 ) ,\ HID_REPORT_COUNT ( report_size ) ,\ HID_INPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\ /* Usage Data Out */ \ - HID_USAGE ( HID_USAGE_FIDO_OUTPUT_REPORT_DATA ) ,\ + HID_USAGE ( HID_USAGE_FIDO_DATA_OUT ) ,\ HID_LOGICAL_MIN ( 0 ) ,\ HID_LOGICAL_MAX_N ( 0xff, 2 ) ,\ HID_REPORT_SIZE ( 8 ) ,\ -- cgit v1.3.1 From 603effbb77ab587bae9800993a53599a9dbff97e Mon Sep 17 00:00:00 2001 From: Tomas Rezucha Date: Thu, 2 Jun 2022 13:22:53 +0200 Subject: cdc: Fix autoflush for FIFO < MPS --- src/class/cdc/cdc_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index fab6f0035..77c73030a 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -171,7 +171,7 @@ uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize) uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) bufsize); // flush if queue more than packet size - if ( tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE ) + if ( (tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE) || ((CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE) && tu_fifo_full(&p_cdc->tx_ff)) ) { tud_cdc_n_write_flush(itf); } -- cgit v1.3.1 From 19400c8556ce4bf5e40653d0c87a9f07db0870a3 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 8 Dec 2022 10:30:22 +0700 Subject: fix typo, add -Wno-error=unreachable-code for fuzz due to latest cdc changes --- fuzz/device/net/src/fuzz.cc | 4 ++-- fuzz/make.mk | 1 + src/class/cdc/cdc_device.c | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/fuzz/device/net/src/fuzz.cc b/fuzz/device/net/src/fuzz.cc index 1013cf7f7..ea4943665 100644 --- a/fuzz/device/net/src/fuzz.cc +++ b/fuzz/device/net/src/fuzz.cc @@ -88,7 +88,7 @@ void net_task(FuzzedDataProvider *provider) { case kNetworkCanXmit: (void)tud_network_can_xmit(provider->ConsumeIntegral()); case kNetworkXmit: - // TODO: Actuall pass real values here later. + // TODO: Actually pass real values here later. tud_network_xmit(NULL, 0); case kMaxValue: @@ -96,4 +96,4 @@ void net_task(FuzzedDataProvider *provider) { break; } } -} \ No newline at end of file +} diff --git a/fuzz/make.mk b/fuzz/make.mk index 299d2c843..796ddc443 100644 --- a/fuzz/make.mk +++ b/fuzz/make.mk @@ -72,6 +72,7 @@ CFLAGS += \ -O1 CFLAGS += \ + -Wno-error=unreachable-code \ -DOPT_MCU_FUZZ=1 \ -DCFG_TUSB_MCU=OPT_MCU_FUZZ diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index 77c73030a..7b1e08d5d 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -171,6 +171,7 @@ uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize) uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) bufsize); // flush if queue more than packet size + // may need to suppress -Wunreachable-code since most of the time CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE if ( (tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE) || ((CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE) && tu_fifo_full(&p_cdc->tx_ff)) ) { tud_cdc_n_write_flush(itf); -- cgit v1.3.1 From 3e32fa36b86c502a35341f7f1aba62b89dae8fcb Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 8 Dec 2022 16:39:24 +0700 Subject: enhance tu fifo - rename wr/rd absolute to index, and rel to pointer. - fix crash with _tu_fifo_remaining() - change get_relative_pointer() to idx2ptr() and merge with _ff_mod() --- src/common/tusb_fifo.c | 205 +++++++++++++++++++++++++++++-------------------- src/common/tusb_fifo.h | 6 +- 2 files changed, 124 insertions(+), 87 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index b857c6444..853614d28 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -34,6 +34,8 @@ #pragma diag_suppress = Pa082 #endif +#define TU_FIFO_DBG 0 + // implement mutex lock and unlock #if CFG_FIFO_MUTEX @@ -90,12 +92,9 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si return true; } -// Static functions are intended to work on local variables -static inline uint16_t _ff_mod(uint16_t idx, uint16_t depth) -{ - while ( idx >= depth) idx -= depth; - return idx; -} +//--------------------------------------------------------------------+ +// Pull & Push +//--------------------------------------------------------------------+ // Intended to be used to read from hardware USB FIFO in e.g. STM32 where all data is read from a constant address // Code adapted from dcd_synopsys.c @@ -179,7 +178,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t // Write data to linear part of buffer memcpy(ff_buf, app_buf, nLin_bytes); - // Write data wrapped around + TU_ASSERT(nWrap_bytes <= f->depth, ); memcpy(f->buffer, ((uint8_t const*) app_buf) + nLin_bytes, nWrap_bytes); } break; @@ -317,21 +316,24 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu } } +//--------------------------------------------------------------------+ +// Index (free-running and real buffer pointer) +//--------------------------------------------------------------------+ + // Advance an absolute pointer +// "absolute" index is only in the range of [0..2*depth) static uint16_t advance_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset) { // We limit the index space of p such that a correct wrap around happens // Check for a wrap around or if we are in unused index space - This has to be checked first!! // We are exploiting the wrap around to the correct index - if ((p > (uint16_t)(p + offset)) || ((uint16_t)(p + offset) > f->max_pointer_idx)) - { - p = (uint16_t) ((p + offset) + f->non_used_index_space); - } - else + uint16_t next_p = (uint16_t) (p + offset); + if ( (p > next_p) || (next_p > f->max_pointer_idx) ) { - p += offset; + next_p = (uint16_t) (next_p + f->non_used_index_space); } - return p; + + return next_p; } // Backward an absolute pointer @@ -340,30 +342,33 @@ static uint16_t backward_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset) // We limit the index space of p such that a correct wrap around happens // Check for a wrap around or if we are in unused index space - This has to be checked first!! // We are exploiting the wrap around to the correct index - if ((p < (uint16_t)(p - offset)) || ((uint16_t)(p - offset) > f->max_pointer_idx)) - { - p = (uint16_t) ((p - offset) - f->non_used_index_space); - } - else + uint16_t new_p = (uint16_t) (p - offset); + if ( (p < new_p) || (new_p > f->max_pointer_idx) ) { - p -= offset; + new_p = (uint16_t) (new_p - f->non_used_index_space); } - return p; + + return new_p; } -// get relative from absolute pointer -static uint16_t get_relative_pointer(tu_fifo_t* f, uint16_t p) +// index to pointer, simply an modulo with minus +static inline uint16_t idx2ptr(uint16_t idx, uint16_t depth) { - return _ff_mod(p, f->depth); + while ( idx >= depth ) idx -= depth; + return idx; } // Works on local copies of w and r - return only the difference and as such can be used to determine an overflow -static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs) +static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx) { - uint16_t cnt = wAbs-rAbs; + uint16_t cnt = (uint16_t) (wr_idx-rd_idx); // In case we have non-power of two depth we need a further modification - if (rAbs > wAbs) cnt -= f->non_used_index_space; + if (rd_idx > wr_idx) + { + // 2*f->depth - (rd_idx - wr_idx); + cnt = (uint16_t) (cnt - f->non_used_index_space); + } return cnt; } @@ -400,39 +405,39 @@ static inline void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wAbs) // Works on local copies of w and r // Must be protected by mutexes since in case of an overflow read pointer gets modified -static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wAbs, uint16_t rAbs) +static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16_t rd_idx) { - uint16_t cnt = _tu_fifo_count(f, wAbs, rAbs); + uint16_t cnt = _tu_fifo_count(f, wr_idx, rd_idx); // Check overflow and correct if required if (cnt > f->depth) { - _tu_fifo_correct_read_pointer(f, wAbs); + _tu_fifo_correct_read_pointer(f, wr_idx); cnt = f->depth; } // Skip beginning of buffer if (cnt == 0) return false; - uint16_t rRel = get_relative_pointer(f, rAbs); + uint16_t rd_ptr = idx2ptr(rd_idx, f->depth); // Peek data - _ff_pull(f, p_buffer, rRel); + _ff_pull(f, p_buffer, rd_ptr); return true; } // Works on local copies of w and r // Must be protected by mutexes since in case of an overflow read pointer gets modified -static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint16_t wAbs, uint16_t rAbs, tu_fifo_copy_mode_t copy_mode) +static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint16_t wr_idx, uint16_t rd_idx, tu_fifo_copy_mode_t copy_mode) { - uint16_t cnt = _tu_fifo_count(f, wAbs, rAbs); + uint16_t cnt = _tu_fifo_count(f, wr_idx, rd_idx); // Check overflow and correct if required if (cnt > f->depth) { - _tu_fifo_correct_read_pointer(f, wAbs); - rAbs = f->rd_idx; + _tu_fifo_correct_read_pointer(f, wr_idx); + rd_idx = f->rd_idx; cnt = f->depth; } @@ -442,53 +447,80 @@ static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint1 // Check if we can read something at and after offset - if too less is available we read what remains if (cnt < n) n = cnt; - uint16_t rRel = get_relative_pointer(f, rAbs); + uint16_t rd_ptr = idx2ptr(rd_idx, f->depth); // Peek data - _ff_pull_n(f, p_buffer, n, rRel, copy_mode); + _ff_pull_n(f, p_buffer, n, rd_ptr, copy_mode); return n; } // Works on local copies of w and r -static inline uint16_t _tu_fifo_remaining(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs) +static inline uint16_t _tu_fifo_remaining(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx) { - return f->depth - _tu_fifo_count(f, wAbs, rAbs); + uint16_t const count = _tu_fifo_count(f, wr_idx, rd_idx); + return (f->depth > count) ? (f->depth - count) : 0; } static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu_fifo_copy_mode_t copy_mode) { if ( n == 0 ) return 0; + TU_LOG(TU_FIFO_DBG, "rd = %u, wr = %02u, n = %u: ", f->rd_idx, f->wr_idx, n); + _ff_lock(f->mutex_wr); - uint16_t w = f->wr_idx, r = f->rd_idx; + uint16_t wr_idx = f->wr_idx; + uint16_t rd_idx = f->rd_idx; + uint8_t const* buf8 = (uint8_t const*) data; + uint16_t const remain = _tu_fifo_remaining(f, wr_idx, rd_idx); - if (!f->overwritable) + if ( n > remain) { - // Not overwritable limit up to full - n = tu_min16(n, _tu_fifo_remaining(f, w, r)); + if ( !f->overwritable ) + { + // limit up to full + n = remain; + } + else + { + // oldest data in fifo i.e read pointer data will be overwritten + // Note: we modify read data but we do not want to modify the read pointer within a write function! + // since it would end up in a race condition with read functions! + // Note2: race condition could still occur if tu_fifo_read() is called while we modify its buffer (corrupted data) + + if ( n >= f->depth ) + { + // Only copy last part + buf8 = buf8 + (n - f->depth) * f->item_size; + n = f->depth; + + // We start writing at the read pointer's position since we fill the complete + // buffer and we do not want to modify the read pointer within a write function! + // This would end up in a race condition with read functions! + wr_idx = rd_idx; + }else + { + // TODO shift out oldest data from read pointer !!! + } + } } - else if (n >= f->depth) + + if (n) { - // Only copy last part - buf8 = buf8 + (n - f->depth) * f->item_size; - n = f->depth; - - // We start writing at the read pointer's position since we fill the complete - // buffer and we do not want to modify the read pointer within a write function! - // This would end up in a race condition with read functions! - w = r; - } + uint16_t wr_ptr = idx2ptr(wr_idx, f->depth); - uint16_t wRel = get_relative_pointer(f, w); + TU_LOG(TU_FIFO_DBG, "actual_n = %u, wr_rel = %u", n, wr_ptr); - // Write data - _ff_push_n(f, buf8, n, wRel, copy_mode); + // Write data + _ff_push_n(f, buf8, n, wr_ptr, copy_mode); - // Advance pointer - f->wr_idx = advance_pointer(f, w, n); + // Advance pointer + f->wr_idx = advance_pointer(f, wr_idx, n); + + TU_LOG(TU_FIFO_DBG, "\tnew_wr = %u\n", f->wr_idx); + } _ff_unlock(f->mutex_wr); @@ -742,20 +774,20 @@ bool tu_fifo_write(tu_fifo_t* f, const void * data) _ff_lock(f->mutex_wr); bool ret; - uint16_t const w = f->wr_idx; + uint16_t const wr_idx = f->wr_idx; - if ( _tu_fifo_full(f, w, f->rd_idx) && !f->overwritable ) + if ( _tu_fifo_full(f, wr_idx, f->rd_idx) && !f->overwritable ) { ret = false; }else { - uint16_t wRel = get_relative_pointer(f, w); + uint16_t wr_ptr = idx2ptr(wr_idx, f->depth); // Write data - _ff_push(f, data, wRel); + _ff_push(f, data, wr_ptr); // Advance pointer - f->wr_idx = advance_pointer(f, w, 1); + f->wr_idx = advance_pointer(f, wr_idx, 1); ret = true; } @@ -909,17 +941,19 @@ void tu_fifo_advance_read_pointer(tu_fifo_t *f, uint16_t n) void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) { // Operate on temporary values in case they change in between - uint16_t w = f->wr_idx, r = f->rd_idx; + uint16_t wr_idx = f->wr_idx; + uint16_t rd_idx = f->rd_idx; - uint16_t cnt = _tu_fifo_count(f, w, r); + uint16_t cnt = _tu_fifo_count(f, wr_idx, rd_idx); // Check overflow and correct if required - may happen in case a DMA wrote too fast if (cnt > f->depth) { _ff_lock(f->mutex_rd); - _tu_fifo_correct_read_pointer(f, w); + _tu_fifo_correct_read_pointer(f, wr_idx); _ff_unlock(f->mutex_rd); - r = f->rd_idx; + + rd_idx = f->rd_idx; cnt = f->depth; } @@ -934,22 +968,24 @@ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) } // Get relative pointers - w = get_relative_pointer(f, w); - r = get_relative_pointer(f, r); + uint16_t wr_ptr = idx2ptr(wr_idx, f->depth); + uint16_t rd_ptr = idx2ptr(rd_idx, f->depth); // Copy pointer to buffer to start reading from - info->ptr_lin = &f->buffer[r]; + info->ptr_lin = &f->buffer[rd_ptr]; // Check if there is a wrap around necessary - if (w > r) { + if (wr_ptr > rd_ptr) { // Non wrapping case info->len_lin = cnt; + info->len_wrap = 0; info->ptr_wrap = NULL; } else { - info->len_lin = f->depth - r; // Also the case if FIFO was full + info->len_lin = f->depth - rd_ptr; // Also the case if FIFO was full + info->len_wrap = cnt - info->len_lin; info->ptr_wrap = f->buffer; } @@ -972,10 +1008,11 @@ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) /******************************************************************************/ void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) { - uint16_t w = f->wr_idx, r = f->rd_idx; - uint16_t free = _tu_fifo_remaining(f, w, r); + uint16_t wr_idx = f->wr_idx; + uint16_t rd_idx = f->rd_idx; + uint16_t remain = _tu_fifo_remaining(f, wr_idx, rd_idx); - if (free == 0) + if (remain == 0) { info->len_lin = 0; info->len_wrap = 0; @@ -985,23 +1022,23 @@ void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) } // Get relative pointers - w = get_relative_pointer(f, w); - r = get_relative_pointer(f, r); + uint16_t wr_ptr = idx2ptr(wr_idx, f->depth); + uint16_t rd_ptr = idx2ptr(rd_idx, f->depth); // Copy pointer to buffer to start writing to - info->ptr_lin = &f->buffer[w]; + info->ptr_lin = &f->buffer[wr_ptr]; - if (w < r) + if (wr_ptr < rd_ptr) { // Non wrapping case - info->len_lin = r-w; + info->len_lin = rd_ptr-wr_ptr; info->len_wrap = 0; info->ptr_wrap = NULL; } else { - info->len_lin = f->depth - w; - info->len_wrap = free - info->len_lin; // Remaining length - n already was limited to free or FIFO depth - info->ptr_wrap = f->buffer; // Always start of buffer + info->len_lin = f->depth - wr_ptr; + info->len_wrap = remain - info->len_lin; // Remaining length - n already was limited to remain or FIFO depth + info->ptr_wrap = f->buffer; // Always start of buffer } } diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h index e64ab4b6d..204d53081 100644 --- a/src/common/tusb_fifo.h +++ b/src/common/tusb_fifo.h @@ -101,10 +101,10 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si #if CFG_FIFO_MUTEX TU_ATTR_ALWAYS_INLINE static inline -void tu_fifo_config_mutex(tu_fifo_t *f, tu_fifo_mutex_t write_mutex_hdl, tu_fifo_mutex_t read_mutex_hdl) +void tu_fifo_config_mutex(tu_fifo_t *f, tu_fifo_mutex_t wr_mutex, tu_fifo_mutex_t rd_mutex) { - f->mutex_wr = write_mutex_hdl; - f->mutex_rd = read_mutex_hdl; + f->mutex_wr = wr_mutex; + f->mutex_rd = rd_mutex; } #endif -- cgit v1.3.1 From 15ab35d9b82590e49937457efd2654adb2dd8b65 Mon Sep 17 00:00:00 2001 From: Sebastien COUDREAU Date: Thu, 8 Dec 2022 11:18:28 +0100 Subject: usbtmc: correct packet size bug Code was only reading the first 64 bytes of a 512 bytes packet. --- src/class/usbtmc/usbtmc_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index 0f6d3f60d..0b7c28b6e 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -364,7 +364,7 @@ bool tud_usbtmc_start_bus_read() default: TU_VERIFY(false); } - TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_out, usbtmc_state.ep_bulk_out_buf, 64)); + TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_out, usbtmc_state.ep_bulk_out_buf, usbtmc_state.ep_bulk_out_wMaxPacketSize)); return true; } -- cgit v1.3.1 From 071da47944a4345b41328dc514d8a73a537072a9 Mon Sep 17 00:00:00 2001 From: Sebastien COUDREAU Date: Thu, 8 Dec 2022 11:36:48 +0100 Subject: Correct interrupt polling interval in descriptor Use macro argument instead of 0x16 constant value. At least Linux kernel was complaining about this value: "config 1 interface 0 altsetting 0 endpoint 0x82 has an invalid bInterval 22, changing to 8" (warning obtained using usbtmc device config) --- src/device/usbd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/device/usbd.h b/src/device/usbd.h index dc5b35ffd..118e53ce4 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -603,7 +603,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* optional interrupt endpoint */ \ // _int_pollingInterval : for LS/FS, expressed in frames (1ms each). 16 may be a good number? #define TUD_USBTMC_INT_DESCRIPTOR(_ep_interrupt, _ep_interrupt_size, _int_pollingInterval ) \ - 7, TUSB_DESC_ENDPOINT, _ep_interrupt, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_interrupt_size), 0x16 + 7, TUSB_DESC_ENDPOINT, _ep_interrupt, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_interrupt_size), _int_pollingInterval #define TUD_USBTMC_INT_DESCRIPTOR_LEN (7u) -- cgit v1.3.1 From 007ed1f0fe84c13567c7a4ccda79d71a05d79aec Mon Sep 17 00:00:00 2001 From: scoudreau <95369154+scoudreau@users.noreply.github.com> Date: Thu, 8 Dec 2022 14:50:34 +0100 Subject: Added missing typecast to pass build checks --- src/class/usbtmc/usbtmc_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index 0b7c28b6e..122b3f3cf 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -364,7 +364,7 @@ bool tud_usbtmc_start_bus_read() default: TU_VERIFY(false); } - TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_out, usbtmc_state.ep_bulk_out_buf, usbtmc_state.ep_bulk_out_wMaxPacketSize)); + TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_out, usbtmc_state.ep_bulk_out_buf, (uint16_t)usbtmc_state.ep_bulk_out_wMaxPacketSize)); return true; } -- cgit v1.3.1 From 82852774a74631e0916254022339c9713c44cb57 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 9 Dec 2022 18:20:09 +0700 Subject: add fifo implementation note - handle/fix double overflowed with write() - other minor clean upp --- src/common/tusb_fifo.c | 94 +++++++++++++++++++++++++++++--------------------- src/common/tusb_fifo.h | 63 ++++++++++++++++++++++++++++++--- 2 files changed, 113 insertions(+), 44 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index 853614d28..df07a990c 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -81,8 +81,8 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si // Limit index space to 2*depth - this allows for a fast "modulo" calculation // but limits the maximum depth to 2^16/2 = 2^15 and buffer overflows are detectable // only if overflow happens once (important for unsupervised DMA applications) - f->max_pointer_idx = (uint16_t) (2*depth - 1); - f->non_used_index_space = UINT16_MAX - f->max_pointer_idx; + //f->max_pointer_idx = (uint16_t) (2*depth - 1); + f->non_used_index_space = UINT16_MAX - (2*f->depth-1); f->rd_idx = f->wr_idx = 0; @@ -320,15 +320,15 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu // Index (free-running and real buffer pointer) //--------------------------------------------------------------------+ -// Advance an absolute pointer +// Advance an absolute index // "absolute" index is only in the range of [0..2*depth) -static uint16_t advance_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset) +static uint16_t advance_pointer(tu_fifo_t* f, uint16_t idx, uint16_t offset) { // We limit the index space of p such that a correct wrap around happens // Check for a wrap around or if we are in unused index space - This has to be checked first!! // We are exploiting the wrap around to the correct index - uint16_t next_p = (uint16_t) (p + offset); - if ( (p > next_p) || (next_p > f->max_pointer_idx) ) + uint16_t next_p = (uint16_t) (idx + offset); + if ( (idx > next_p) || (next_p >= 2*f->depth) ) { next_p = (uint16_t) (next_p + f->non_used_index_space); } @@ -343,7 +343,7 @@ static uint16_t backward_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset) // Check for a wrap around or if we are in unused index space - This has to be checked first!! // We are exploiting the wrap around to the correct index uint16_t new_p = (uint16_t) (p - offset); - if ( (p < new_p) || (new_p > f->max_pointer_idx) ) + if ( (p < new_p) || (new_p >= 2*f->depth) ) { new_p = (uint16_t) (new_p - f->non_used_index_space); } @@ -374,15 +374,15 @@ static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd } // Works on local copies of w and r -static inline bool _tu_fifo_empty(uint16_t wAbs, uint16_t rAbs) +static inline bool _tu_fifo_empty(uint16_t wr_idx, uint16_t rd_idx) { - return wAbs == rAbs; + return wr_idx == rd_idx; } // Works on local copies of w and r static inline bool _tu_fifo_full(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs) { - return (_tu_fifo_count(f, wAbs, rAbs) == f->depth); + return _tu_fifo_count(f, wAbs, rAbs) == f->depth; } // Works on local copies of w and r @@ -391,9 +391,9 @@ static inline bool _tu_fifo_full(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs) // write more than 2*depth-1 items in one rush without updating write pointer. Otherwise // write pointer wraps and you pointer states are messed up. This can only happen if you // use DMAs, write functions do not allow such an error. -static inline bool _tu_fifo_overflowed(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs) +static inline bool _tu_fifo_overflowed(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx) { - return (_tu_fifo_count(f, wAbs, rAbs) > f->depth); + return (_tu_fifo_count(f, wr_idx, rd_idx) > f->depth); } // Works on local copies of w @@ -466,44 +466,58 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu { if ( n == 0 ) return 0; - TU_LOG(TU_FIFO_DBG, "rd = %u, wr = %02u, n = %u: ", f->rd_idx, f->wr_idx, n); - _ff_lock(f->mutex_wr); uint16_t wr_idx = f->wr_idx; uint16_t rd_idx = f->rd_idx; uint8_t const* buf8 = (uint8_t const*) data; + uint16_t overflowable_count = _tu_fifo_count(f, wr_idx, rd_idx); uint16_t const remain = _tu_fifo_remaining(f, wr_idx, rd_idx); - if ( n > remain) + TU_LOG(TU_FIFO_DBG, "rd = %3u, wr = %3u, count = %3u, remain = %3u, n = %3u: ", rd_idx, wr_idx, _tu_fifo_count(f, wr_idx, rd_idx), remain, n); + + if ( !f->overwritable ) { - if ( !f->overwritable ) - { - // limit up to full - n = remain; - } - else + // limit up to full + n = tu_min16(n, remain); + } + else + { + // In over-writable mode, fifo_write() is allowed even when fifo is full. In such case, + // oldest data in fifo i.e at read pointer data will be overwritten + // Note: we can modify read buffer contents but we must not modify the read index itself within a write function! + // Since it would end up in a race condition with read functions! + if ( n >= f->depth ) { - // oldest data in fifo i.e read pointer data will be overwritten - // Note: we modify read data but we do not want to modify the read pointer within a write function! - // since it would end up in a race condition with read functions! - // Note2: race condition could still occur if tu_fifo_read() is called while we modify its buffer (corrupted data) - - if ( n >= f->depth ) + // Only copy last part + if ( copy_mode == TU_FIFO_COPY_INC ) { - // Only copy last part - buf8 = buf8 + (n - f->depth) * f->item_size; - n = f->depth; - - // We start writing at the read pointer's position since we fill the complete - // buffer and we do not want to modify the read pointer within a write function! - // This would end up in a race condition with read functions! - wr_idx = rd_idx; + buf8 += (n - f->depth) * f->item_size; }else { - // TODO shift out oldest data from read pointer !!! + // TODO should read from hw fifo to discard data, however reading an odd number could + // accidentally discard data. } + + n = f->depth; + + // We start writing at the read pointer's position since we fill the whole buffer + wr_idx = rd_idx; + }else if (overflowable_count + n >= 2*f->depth) + { + // Double overflowed + // re-position write index to have a full fifo after pushed + wr_idx = advance_pointer(f, rd_idx, f->depth - n); + + // TODO we should also shift out n bytes from read index since we avoid changing rd index !! + // However memmove() is expensive due to actual copying + wrapping consideration. + // Also race condition could happen anyway if read() is invoke while moving result in corrupted memory + // currently deliberately not implemented --> result in incorrect data read back + }else + { + // normal + single overflowed: just increase write index + // we will correct (re-position) read index later on in fifo_read() function } } @@ -511,12 +525,12 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu { uint16_t wr_ptr = idx2ptr(wr_idx, f->depth); - TU_LOG(TU_FIFO_DBG, "actual_n = %u, wr_rel = %u", n, wr_ptr); + TU_LOG(TU_FIFO_DBG, "actual_n = %u, wr_ptr = %u", n, wr_ptr); // Write data _ff_push_n(f, buf8, n, wr_ptr, copy_mode); - // Advance pointer + // Advance index f->wr_idx = advance_pointer(f, wr_idx, n); TU_LOG(TU_FIFO_DBG, "\tnew_wr = %u\n", f->wr_idx); @@ -850,8 +864,8 @@ bool tu_fifo_clear(tu_fifo_t *f) _ff_lock(f->mutex_rd); f->rd_idx = f->wr_idx = 0; - f->max_pointer_idx = (uint16_t) (2*f->depth-1); - f->non_used_index_space = UINT16_MAX - f->max_pointer_idx; + //f->max_pointer_idx = (uint16_t) (2*f->depth-1); + f->non_used_index_space = UINT16_MAX - (2*f->depth-1); _ff_unlock(f->mutex_wr); _ff_unlock(f->mutex_rd); diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h index 204d53081..fd149b75c 100644 --- a/src/common/tusb_fifo.h +++ b/src/common/tusb_fifo.h @@ -52,18 +52,74 @@ extern "C" { #define tu_fifo_mutex_t osal_mutex_t #endif +/* Write/Read index is always in the range of: + * 0 .. 2*depth-1 + * The extra window allow us to determine the fifo state of empty or full with only 2 indexes + * Following are examples with depth = 3 + * + * - empty: W = R + * | + * ------------------------- + * | 0 | RW| 2 | 3 | 4 | 5 | + * + * - full 1: W > R + * | + * ------------------------- + * | 0 | R | 2 | 3 | W | 5 | + * + * - full 2: W < R + * | + * ------------------------- + * | 0 | 1 | W | 3 | 4 | R | + * + * - Number of items in the fifo can be determined in either cases: + * - case W > R: Count = W - R + * - case W < R: Count = 2*depth - (R - W) + * + * In non-overwritable mode, computed Count (in above 2 cases) is at most equal to depth. + * However, in over-writable mode, write index can be repeatedly increased and count can be + * temporarily larger than depth (overflowed condition) e.g + * + * - Overflowed 1: write(3), write(1) + * In this case we will adjust Read index when read()/peek() is called so that count = depth. + * | + * ------------------------- + * | R | 1 | 2 | 3 | W | 5 | + * + * - Double Overflowed: write(3), write(1), write(2) + * Continue to write after overflowed to 2nd overflowed. + * We must prevent 2nd overflowed since it will cause incorrect computed of count, in above example + * if not handled the fifo will be empty instead of continue-to-be full. Since we must not modify + * read index in write() function, which cause race condition. We will re-position write index so that + * after data is written it is a full fifo i.e W = depth - R + * + * re-position W = 1 before write(2) + * Note: we should also move data from mem[4] to read index as well, but deliberately skipped here + * since it is an expensive operation !!! + * | + * ------------------------- + * | R | W | 2 | 3 | 4 | 5 | + * + * perform write(2), result is still a full fifo. + * + * | + * ------------------------- + * | R | 1 | 2 | W | 4 | 5 | + + */ typedef struct { uint8_t* buffer ; ///< buffer pointer uint16_t depth ; ///< max items uint16_t item_size ; ///< size of each item + bool overwritable ; uint16_t non_used_index_space ; ///< required for non-power-of-two buffer length - uint16_t max_pointer_idx ; ///< maximum absolute pointer index + //uint16_t max_pointer_idx ; ///< maximum absolute pointer index - volatile uint16_t wr_idx ; ///< write pointer - volatile uint16_t rd_idx ; ///< read pointer + volatile uint16_t wr_idx ; ///< write index + volatile uint16_t rd_idx ; ///< read index #if CFG_FIFO_MUTEX tu_fifo_mutex_t mutex_wr; @@ -87,7 +143,6 @@ typedef struct .item_size = sizeof(_type), \ .overwritable = _overwritable, \ .non_used_index_space = UINT16_MAX - (2*(_depth)-1), \ - .max_pointer_idx = 2*(_depth)-1, \ } #define TU_FIFO_DEF(_name, _depth, _type, _overwritable) \ -- cgit v1.3.1 From ce064de6fd4416bb5368a2aaff4283f8e4b9fc36 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 10 Dec 2022 00:18:11 +0700 Subject: clean up --- src/common/tusb_fifo.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index df07a990c..a3933416c 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -178,7 +178,8 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t // Write data to linear part of buffer memcpy(ff_buf, app_buf, nLin_bytes); - TU_ASSERT(nWrap_bytes <= f->depth, ); + // Write data wrapped around + // TU_ASSERT(nWrap_bytes <= f->depth, ); memcpy(f->buffer, ((uint8_t const*) app_buf) + nLin_bytes, nWrap_bytes); } break; @@ -504,7 +505,8 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu // We start writing at the read pointer's position since we fill the whole buffer wr_idx = rd_idx; - }else if (overflowable_count + n >= 2*f->depth) + } + else if (overflowable_count + n >= 2*f->depth) { // Double overflowed // re-position write index to have a full fifo after pushed -- cgit v1.3.1 From 04a5c03ea8ea70510c332f0fafb44daf0ec7c7fb Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 12 Dec 2022 11:54:33 +0700 Subject: fix int conversion warnings --- src/common/tusb_fifo.c | 4 ++-- src/common/tusb_fifo.h | 14 +++++++------- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index a3933416c..70f514df2 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -82,7 +82,7 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si // but limits the maximum depth to 2^16/2 = 2^15 and buffer overflows are detectable // only if overflow happens once (important for unsupervised DMA applications) //f->max_pointer_idx = (uint16_t) (2*depth - 1); - f->non_used_index_space = UINT16_MAX - (2*f->depth-1); + f->non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1)); f->rd_idx = f->wr_idx = 0; @@ -867,7 +867,7 @@ bool tu_fifo_clear(tu_fifo_t *f) f->rd_idx = f->wr_idx = 0; //f->max_pointer_idx = (uint16_t) (2*f->depth-1); - f->non_used_index_space = UINT16_MAX - (2*f->depth-1); + f->non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1)); _ff_unlock(f->mutex_wr); _ff_unlock(f->mutex_rd); diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h index fd149b75c..932214c81 100644 --- a/src/common/tusb_fifo.h +++ b/src/common/tusb_fifo.h @@ -136,13 +136,13 @@ typedef struct void * ptr_wrap ; ///< wrapped part start pointer } tu_fifo_buffer_info_t; -#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable) \ -{ \ - .buffer = _buffer, \ - .depth = _depth, \ - .item_size = sizeof(_type), \ - .overwritable = _overwritable, \ - .non_used_index_space = UINT16_MAX - (2*(_depth)-1), \ +#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable) \ +{ \ + .buffer = _buffer, \ + .depth = _depth, \ + .item_size = sizeof(_type), \ + .overwritable = _overwritable, \ + .non_used_index_space = (uint16_t)(UINT16_MAX - (2*(_depth)-1)), \ } #define TU_FIFO_DEF(_name, _depth, _type, _overwritable) \ -- cgit v1.3.1 From a05adfce86104c8ad217993db2707e1112918be3 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 14 Dec 2022 14:38:40 +0700 Subject: fix midi MS Header wTotalLength computation --- src/device/usbd.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/device/usbd.h b/src/device/usbd.h index 118e53ce4..ad19d1045 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -293,7 +293,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* MIDI Streaming (MS) Interface */\ 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum) + 1), 0, 2, TUSB_CLASS_AUDIO, AUDIO_SUBCLASS_MIDI_STREAMING, AUDIO_FUNC_PROTOCOL_CODE_UNDEF, 0,\ /* MS Header */\ - 7, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_HEADER, U16_TO_U8S_LE(0x0100), U16_TO_U8S_LE(7 + (_numcables) * TUD_MIDI_DESC_JACK_LEN) + 7, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_HEADER, U16_TO_U8S_LE(0x0100), U16_TO_U8S_LE(7 + (_numcables) * TUD_MIDI_DESC_JACK_LEN + 2 * TUD_MIDI_DESC_EP_LEN(_numcables)) #define TUD_MIDI_JACKID_IN_EMB(_cablenum) \ (uint8_t)(((_cablenum) - 1) * 4 + 1) @@ -317,6 +317,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb 9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_OUT_EMB(_cablenum), 1, TUD_MIDI_JACKID_IN_EXT(_cablenum), 1, _stridx,\ /* MS Out Jack (External), connected to In Jack Embedded */\ 9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_OUT_EXT(_cablenum), 1, TUD_MIDI_JACKID_IN_EMB(_cablenum), 1, _stridx + #define TUD_MIDI_DESC_JACK(_cablenum) TUD_MIDI_DESC_JACK_DESC(_cablenum, 0) #define TUD_MIDI_DESC_EP_LEN(_numcables) (9 + 4 + (_numcables)) -- cgit v1.3.1 From 88e6da727370114b427287e74c3ade176c483b17 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 15 Dec 2022 18:03:01 +0700 Subject: use OSAL_MUTEX_REQUIRED to replace CFG_FIFO_MUTEX/TUSB_OPT_MUTEX add macro to swallow mutex API in order to simplify code with mutex --- src/class/cdc/cdc_device.c | 8 ++------ src/common/tusb_fifo.h | 19 +++++++++++-------- src/common/tusb_mcu.h | 4 ++++ src/device/usbd.c | 20 +++++++------------- src/host/usbh.c | 41 +++++++++++------------------------------ src/osal/osal.h | 21 ++++++++++++++------- src/osal/osal_none.h | 12 ++++++++++++ src/tusb.c | 16 ++++------------ src/tusb_option.h | 3 --- 9 files changed, 65 insertions(+), 79 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index 7b1e08d5d..0bbbaaa83 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -62,10 +62,8 @@ typedef struct uint8_t rx_ff_buf[CFG_TUD_CDC_RX_BUFSIZE]; uint8_t tx_ff_buf[CFG_TUD_CDC_TX_BUFSIZE]; -#if CFG_FIFO_MUTEX - osal_mutex_def_t rx_ff_mutex; - osal_mutex_def_t tx_ff_mutex; -#endif + OSAL_MUTEX_DEF(rx_ff_mutex); + OSAL_MUTEX_DEF(tx_ff_mutex); // Endpoint Transfer buffer CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE]; @@ -248,10 +246,8 @@ void cdcd_init(void) // In this way, the most current data is prioritized. tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, true); -#if CFG_FIFO_MUTEX tu_fifo_config_mutex(&p_cdc->rx_ff, NULL, osal_mutex_create(&p_cdc->rx_ff_mutex)); tu_fifo_config_mutex(&p_cdc->tx_ff, osal_mutex_create(&p_cdc->tx_ff_mutex), NULL); -#endif } } diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h index e64ab4b6d..e36e3a7f3 100644 --- a/src/common/tusb_fifo.h +++ b/src/common/tusb_fifo.h @@ -42,15 +42,13 @@ extern "C" { // within a certain number (see tu_fifo_overflow()). #include "common/tusb_common.h" +#include "osal/osal.h" + +#define tu_fifo_mutex_t osal_mutex_t // mutex is only needed for RTOS // for OS None, we don't get preempted -#define CFG_FIFO_MUTEX (CFG_TUSB_OS != OPT_OS_NONE) - -#if CFG_FIFO_MUTEX -#include "osal/osal.h" -#define tu_fifo_mutex_t osal_mutex_t -#endif +#define CFG_FIFO_MUTEX OSAL_MUTEX_REQUIRED typedef struct { @@ -65,7 +63,7 @@ typedef struct volatile uint16_t wr_idx ; ///< write pointer volatile uint16_t rd_idx ; ///< read pointer -#if CFG_FIFO_MUTEX +#if OSAL_MUTEX_REQUIRED tu_fifo_mutex_t mutex_wr; tu_fifo_mutex_t mutex_rd; #endif @@ -99,13 +97,18 @@ bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable); bool tu_fifo_clear(tu_fifo_t *f); bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable); -#if CFG_FIFO_MUTEX +#if OSAL_MUTEX_REQUIRED TU_ATTR_ALWAYS_INLINE static inline void tu_fifo_config_mutex(tu_fifo_t *f, tu_fifo_mutex_t write_mutex_hdl, tu_fifo_mutex_t read_mutex_hdl) { f->mutex_wr = write_mutex_hdl; f->mutex_rd = read_mutex_hdl; } + +#else + +#define tu_fifo_config_mutex(_f, _wr_mutex, _rd_mutex) + #endif bool tu_fifo_write (tu_fifo_t* f, void const * p_data); diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 86c68baf8..bb4225ad5 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -281,6 +281,10 @@ // Default Values //--------------------------------------------------------------------+ +#ifndef TUP_MCU_MULTIPLE_CORE +#define TUP_MCU_MULTIPLE_CORE 0 +#endif + #ifndef TUP_DCD_ENDPOINT_MAX #warning "TUP_DCD_ENDPOINT_MAX is not defined for this MCU, default to 8" #define TUP_DCD_ENDPOINT_MAX 8 diff --git a/src/device/usbd.c b/src/device/usbd.c index c199e647e..f9a7af21b 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -272,10 +272,12 @@ static uint8_t _usbd_rhport = RHPORT_INVALID; OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t); static osal_queue_t _usbd_q; -// Mutex for claiming endpoint, only needed when using with preempted RTOS -#if CFG_TUSB_OS != OPT_OS_NONE -static osal_mutex_def_t _ubsd_mutexdef; -static osal_mutex_t _usbd_mutex; +// Mutex for claiming endpoint +#if OSAL_MUTEX_REQUIRED + static osal_mutex_def_t _ubsd_mutexdef; + static osal_mutex_t _usbd_mutex; +#else + #define _usbd_mutex NULL #endif @@ -389,7 +391,7 @@ bool tud_init (uint8_t rhport) tu_varclr(&_usbd_dev); -#if CFG_TUSB_OS != OPT_OS_NONE +#if OSAL_MUTEX_REQUIRED // Init device mutex _usbd_mutex = osal_mutex_create(&_ubsd_mutexdef); TU_ASSERT(_usbd_mutex); @@ -1209,11 +1211,7 @@ bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr) uint8_t const dir = tu_edpt_dir(ep_addr); tu_edpt_state_t* ep_state = &_usbd_dev.ep_status[epnum][dir]; -#if TUSB_OPT_MUTEX return tu_edpt_claim(ep_state, _usbd_mutex); -#else - return tu_edpt_claim(ep_state, NULL); -#endif } bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr) @@ -1224,11 +1222,7 @@ bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr) uint8_t const dir = tu_edpt_dir(ep_addr); tu_edpt_state_t* ep_state = &_usbd_dev.ep_status[epnum][dir]; -#if TUSB_OPT_MUTEX return tu_edpt_release(ep_state, _usbd_mutex); -#else - return tu_edpt_release(ep_state, NULL); -#endif } bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) diff --git a/src/host/usbh.c b/src/host/usbh.c index 9065e5241..ff8fbaef3 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -212,28 +212,12 @@ static usbh_dev0_t _dev0; // TODO: hub can has its own simpler struct to save memory CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[TOTAL_DEVICES]; -// Mutex for claiming endpoint, only needed when using with preempted RTOS -#if TUSB_OPT_MUTEX -static osal_mutex_def_t _usbh_mutexdef; -static osal_mutex_t _usbh_mutex; - -TU_ATTR_ALWAYS_INLINE static inline void usbh_lock(void) -{ - osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); -} - -TU_ATTR_ALWAYS_INLINE static inline void usbh_unlock(void) -{ - osal_mutex_unlock(_usbh_mutex); -} - +// Mutex for claiming endpoint +#if OSAL_MUTEX_REQUIRED + static osal_mutex_def_t _usbh_mutexdef; + static osal_mutex_t _usbh_mutex; #else - -#define _usbh_mutex NULL - -#define usbh_lock() -#define usbh_unlock() - + #define _usbh_mutex NULL #endif // Event queue @@ -277,8 +261,6 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t // TODO rework time-related function later void osal_task_delay(uint32_t msec) { - (void) msec; - const uint32_t start = hcd_frame_number(_usbh_controller); while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {} } @@ -352,8 +334,8 @@ bool tuh_init(uint8_t controller_id) _usbh_q = osal_queue_create( &_usbh_qdef ); TU_ASSERT(_usbh_q != NULL); -#if TUSB_OPT_MUTEX - // Mutex +#if OSAL_MUTEX_REQUIRED + // Init mutex _usbh_mutex = osal_mutex_create(&_usbh_mutexdef); TU_ASSERT(_usbh_mutex); #endif @@ -537,8 +519,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) uint8_t const daddr = xfer->daddr; - // TODO probably better to use semaphore as resource management than mutex - usbh_lock(); + (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); bool const is_idle = (_ctrl_xfer.stage == CONTROL_STAGE_IDLE); if (is_idle) @@ -553,7 +534,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) _ctrl_xfer.user_data = xfer->user_data; } - usbh_unlock(); + (void) osal_mutex_unlock(_usbh_mutex); TU_VERIFY(is_idle); const uint8_t rhport = usbh_get_rhport(daddr); @@ -597,9 +578,9 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage) { - usbh_lock(); + osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); _ctrl_xfer.stage = stage; - usbh_unlock(); + osal_mutex_unlock(_usbh_mutex); } static void _xfer_complete(uint8_t daddr, xfer_result_t result) diff --git a/src/osal/osal.h b/src/osal/osal.h index 9d11866df..9cdab2882 100644 --- a/src/osal/osal.h +++ b/src/osal/osal.h @@ -33,17 +33,24 @@ #include "common/tusb_common.h" -// Return immediately -#define OSAL_TIMEOUT_NOTIMEOUT (0) -// Default timeout -#define OSAL_TIMEOUT_NORMAL (10) -// Wait forever -#define OSAL_TIMEOUT_WAIT_FOREVER (UINT32_MAX) +typedef void (*osal_task_func_t)( void * ); +// Timeout +#define OSAL_TIMEOUT_NOTIMEOUT (0) // Return immediately +#define OSAL_TIMEOUT_NORMAL (10) // Default timeout +#define OSAL_TIMEOUT_WAIT_FOREVER (UINT32_MAX) // Wait forever #define OSAL_TIMEOUT_CONTROL_XFER OSAL_TIMEOUT_WAIT_FOREVER -typedef void (*osal_task_func_t)( void * ); +// Mutex is required when using a preempted RTOS or MCU has multiple cores +#if (CFG_TUSB_OS == OPT_OS_NONE) && !TUP_MCU_MULTIPLE_CORE + #define OSAL_MUTEX_REQUIRED 0 + #define OSAL_MUTEX_DEF(_name) +#else + #define OSAL_MUTEX_REQUIRED 1 + #define OSAL_MUTEX_DEF(_name) osal_mutex_def_t _name +#endif +// OS thin implementation #if CFG_TUSB_OS == OPT_OS_NONE #include "osal_none.h" #elif CFG_TUSB_OS == OPT_OS_FREERTOS diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h index 9c80e4548..1ad130557 100644 --- a/src/osal/osal_none.h +++ b/src/osal/osal_none.h @@ -82,6 +82,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t s typedef osal_semaphore_def_t osal_mutex_def_t; typedef osal_semaphore_t osal_mutex_t; +#if OSAL_MUTEX_REQUIRED +// Note: multiple cores MCUs usually do provide IPC API for mutex +// or we can use std atomic function + TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) { mdef->count = 1; @@ -98,6 +102,14 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd return osal_semaphore_post(mutex_hdl, false); } +#else + +#define osal_mutex_create(_mdef) (NULL) +#define osal_mutex_lock(_mutex_hdl, _ms) (true) +#define osal_mutex_unlock(_mutex_hdl) (true) + +#endif + //--------------------------------------------------------------------+ // QUEUE API //--------------------------------------------------------------------+ diff --git a/src/tusb.c b/src/tusb.c index c3787ff8f..f4380f89c 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -74,11 +74,9 @@ bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex) { (void) mutex; -#if TUSB_OPT_MUTEX // pre-check to help reducing mutex lock TU_VERIFY((ep_state->busy == 0) && (ep_state->claimed == 0)); - osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER); -#endif + (void) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER); // can only claim the endpoint if it is not busy and not claimed yet. bool const available = (ep_state->busy == 0) && (ep_state->claimed == 0); @@ -87,9 +85,7 @@ bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex) ep_state->claimed = 1; } -#if TUSB_OPT_MUTEX - osal_mutex_unlock(mutex); -#endif + (void) osal_mutex_unlock(mutex); return available; } @@ -98,9 +94,7 @@ bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex) { (void) mutex; -#if TUSB_OPT_MUTEX - osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER); -#endif + (void) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER); // can only release the endpoint if it is claimed and not busy bool const ret = (ep_state->claimed == 1) && (ep_state->busy == 0); @@ -109,9 +103,7 @@ bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex) ep_state->claimed = 0; } -#if TUSB_OPT_MUTEX - osal_mutex_unlock(mutex); -#endif + (void) osal_mutex_unlock(mutex); return ret; } diff --git a/src/tusb_option.h b/src/tusb_option.h index f95ae6273..9ca6c794b 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -299,9 +299,6 @@ typedef int make_iso_compilers_happy; #define CFG_TUSB_OS_INC_PATH #endif -// mutex is only needed for RTOS TODO also required with multiple core MCUs -#define TUSB_OPT_MUTEX (CFG_TUSB_OS != OPT_OS_NONE) - //-------------------------------------------------------------------- // Device Options (Default) //-------------------------------------------------------------------- -- cgit v1.3.1 From 96d2be905ba331419a34a64bba6baaaf006ae26f Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 15 Dec 2022 18:47:54 +0700 Subject: fix build with usbtmc --- src/class/usbtmc/usbtmc_device.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index 122b3f3cf..07c7c28a6 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -157,12 +157,12 @@ static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t pack static uint8_t termChar; static uint8_t termCharRequested = false; -osal_mutex_def_t usbtmcLockBuffer; +OSAL_MUTEX_DEF(usbtmcLockBuffer); static osal_mutex_t usbtmcLock; // Our own private lock, mostly for the state variable. -#define criticalEnter() do {osal_mutex_lock(usbtmcLock,OSAL_TIMEOUT_WAIT_FOREVER); } while (0) -#define criticalLeave() do {osal_mutex_unlock(usbtmcLock); } while (0) +#define criticalEnter() do { (void) osal_mutex_lock(usbtmcLock,OSAL_TIMEOUT_WAIT_FOREVER); } while (0) +#define criticalLeave() do { (void) osal_mutex_unlock(usbtmcLock); } while (0) bool atomicChangeState(usbtmcd_state_enum expectedState, usbtmcd_state_enum newState) { -- cgit v1.3.1 From 1e99480ad28808a29938673d5b05d9461da5d1c1 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 16 Dec 2022 15:19:40 +0700 Subject: fix ci with usbh and unit test --- src/host/usbh.c | 4 ++-- test/unit-test/test/device/msc/test_msc_device.c | 1 + test/unit-test/test/device/usbd/test_usbd.c | 1 + test/unit-test/test/test_fifo.c | 4 +++- 4 files changed, 7 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index ff8fbaef3..ca42a523c 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -578,9 +578,9 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage) { - osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); + (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); _ctrl_xfer.stage = stage; - osal_mutex_unlock(_usbh_mutex); + (void) osal_mutex_unlock(_usbh_mutex); } static void _xfer_complete(uint8_t daddr, xfer_result_t result) diff --git a/test/unit-test/test/device/msc/test_msc_device.c b/test/unit-test/test/device/msc/test_msc_device.c index 00bb86ccf..63684e76a 100644 --- a/test/unit-test/test/device/msc/test_msc_device.c +++ b/test/unit-test/test/device/msc/test_msc_device.c @@ -28,6 +28,7 @@ #include "unity.h" // Files to test +#include "osal/osal.h" #include "tusb_fifo.h" #include "tusb.h" #include "usbd.h" diff --git a/test/unit-test/test/device/usbd/test_usbd.c b/test/unit-test/test/device/usbd/test_usbd.c index c90383b57..ad95eb47a 100644 --- a/test/unit-test/test/device/usbd/test_usbd.c +++ b/test/unit-test/test/device/usbd/test_usbd.c @@ -25,6 +25,7 @@ #include "unity.h" // Files to test +#include "osal/osal.h" #include "tusb_fifo.h" #include "tusb.h" #include "usbd.h" diff --git a/test/unit-test/test/test_fifo.c b/test/unit-test/test/test_fifo.c index 0a5f4d3b9..1d87081bb 100644 --- a/test/unit-test/test/test_fifo.c +++ b/test/unit-test/test/test_fifo.c @@ -26,6 +26,8 @@ #include #include "unity.h" + +#include "osal/osal.h" #include "tusb_fifo.h" #define FIFO_SIZE 10 @@ -315,4 +317,4 @@ void test_rd_idx_wrap() n = tu_fifo_read_n(&ff10, dst, 4); TEST_ASSERT_EQUAL(n, 2); TEST_ASSERT_EQUAL(ff10.rd_idx, 6); -} \ No newline at end of file +} -- cgit v1.3.1 From 660343d2001c0ee943bf3e24cab6f235d3930b33 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 16 Dec 2022 16:55:25 +0700 Subject: update fifo per PanRe review --- src/common/tusb_fifo.c | 8 ++++++-- src/common/tusb_fifo.h | 7 ++++--- 2 files changed, 10 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index 70f514df2..bbdd82982 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -352,9 +352,10 @@ static uint16_t backward_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset) return new_p; } -// index to pointer, simply an modulo with minus +// index to pointer, simply an modulo with minus. static inline uint16_t idx2ptr(uint16_t idx, uint16_t depth) { + // Only run at most 3 times since index is limit in the range of [0..2*depth) while ( idx >= depth ) idx -= depth; return idx; } @@ -509,6 +510,7 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu else if (overflowable_count + n >= 2*f->depth) { // Double overflowed + // Index is bigger than the allowed range [0,2*depth) // re-position write index to have a full fifo after pushed wr_idx = advance_pointer(f, rd_idx, f->depth - n); @@ -518,7 +520,9 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu // currently deliberately not implemented --> result in incorrect data read back }else { - // normal + single overflowed: just increase write index + // normal + single overflowed: + // Index is in the range of [0,2*depth) and thus detect and recoverable. Recovering is handled in read() + // Therefore we just increase write index // we will correct (re-position) read index later on in fifo_read() function } } diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h index 932214c81..972d29d50 100644 --- a/src/common/tusb_fifo.h +++ b/src/common/tusb_fifo.h @@ -54,7 +54,7 @@ extern "C" { /* Write/Read index is always in the range of: * 0 .. 2*depth-1 - * The extra window allow us to determine the fifo state of empty or full with only 2 indexes + * The extra window allow us to determine the fifo state of empty or full with only 2 indices * Following are examples with depth = 3 * * - empty: W = R @@ -86,7 +86,8 @@ extern "C" { * ------------------------- * | R | 1 | 2 | 3 | W | 5 | * - * - Double Overflowed: write(3), write(1), write(2) + * - Double Overflowed i.e index is out of allowed range [0,2*depth) e.g: + * write(3), write(1), write(2) * Continue to write after overflowed to 2nd overflowed. * We must prevent 2nd overflowed since it will cause incorrect computed of count, in above example * if not handled the fifo will be empty instead of continue-to-be full. Since we must not modify @@ -94,7 +95,7 @@ extern "C" { * after data is written it is a full fifo i.e W = depth - R * * re-position W = 1 before write(2) - * Note: we should also move data from mem[4] to read index as well, but deliberately skipped here + * Note: we should also move data from mem[3] to read index as well, but deliberately skipped here * since it is an expensive operation !!! * | * ------------------------- -- cgit v1.3.1 From 4f0369508450883504e377b40aaec8860c8cb256 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 14 Dec 2022 16:52:28 +0700 Subject: adding tuh_cdc_mount_cb/tuh_cdc_umount_cb start adding cdc_app.c to example --- examples/host/cdc_msc_hid/CMakeLists.txt | 3 +- examples/host/cdc_msc_hid/Makefile | 3 +- examples/host/cdc_msc_hid/src/cdc_app.c | 51 ++++++++++++++++++++++++++++++++ examples/host/cdc_msc_hid/src/main.c | 11 ++----- src/class/cdc/cdc_host.c | 12 ++++++++ src/class/cdc/cdc_host.h | 17 +++++++---- 6 files changed, 81 insertions(+), 16 deletions(-) create mode 100644 examples/host/cdc_msc_hid/src/cdc_app.c (limited to 'src') diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt index d84457bc9..2e89817a5 100644 --- a/examples/host/cdc_msc_hid/CMakeLists.txt +++ b/examples/host/cdc_msc_hid/CMakeLists.txt @@ -14,8 +14,9 @@ add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c ) diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile index ad28076a0..9adccfa3a 100644 --- a/examples/host/cdc_msc_hid/Makefile +++ b/examples/host/cdc_msc_hid/Makefile @@ -7,7 +7,8 @@ INC += \ # Example source EXAMPLE_SOURCE = \ - src/hid_app.c \ + src/cdc_app.c \ + src/hid_app.c \ src/main.c \ src/msc_app.c \ diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c new file mode 100644 index 000000000..29da02abc --- /dev/null +++ b/examples/host/cdc_msc_hid/src/cdc_app.c @@ -0,0 +1,51 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2022, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb.h" + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ + + +//------------- IMPLEMENTATION -------------// + +void cdc_app_task(void) +{ + +} + +void tuh_cdc_mount_cb(uint8_t dev_addr) +{ + (void) dev_addr; + printf("A CDC device is mounted\r\n"); +} + +void tuh_cdc_umount_cb(uint8_t dev_addr) +{ + (void) dev_addr; + printf("A CDC device is unmounted\r\n"); +} diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c index d26e41e8d..465e457f7 100644 --- a/examples/host/cdc_msc_hid/src/main.c +++ b/examples/host/cdc_msc_hid/src/main.c @@ -35,7 +35,7 @@ //--------------------------------------------------------------------+ void led_blinking_task(void); -extern void cdc_task(void); +extern void cdc_app_task(void); extern void hid_app_task(void); /*------------- MAIN -------------*/ @@ -52,9 +52,9 @@ int main(void) { // tinyusb host task tuh_task(); - led_blinking_task(); - cdc_task(); + led_blinking_task(); + cdc_app_task(); hid_app_task(); } @@ -79,11 +79,6 @@ void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_i tuh_cdc_receive(dev_addr, serial_in_buffer, sizeof(serial_in_buffer), true); // waiting for next data } -void cdc_task(void) -{ - -} - //--------------------------------------------------------------------+ // TinyUSB Callbacks //--------------------------------------------------------------------+ diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index ee824cb4e..aa3a7e1e5 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -239,6 +239,8 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num) { (void) dev_addr; (void) itf_num; + + if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(dev_addr); return true; } @@ -254,6 +256,16 @@ void cdch_close(uint8_t dev_addr) TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, ); cdch_data_t * p_cdc = get_itf(dev_addr); + + // Invoke application callback + if (tuh_cdc_umount_cb) + { + if (p_cdc->ep_out || p_cdc->ep_in || p_cdc->ep_notif) + { + tuh_cdc_umount_cb(dev_addr); + } + } + tu_memclr(p_cdc, sizeof(cdch_data_t)); } diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 33dbd2efb..c3b601b34 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -34,13 +34,18 @@ #endif //--------------------------------------------------------------------+ -// CDC APPLICATION PUBLIC API +// Application API //--------------------------------------------------------------------+ -/** \ingroup ClassDriver_CDC Communication Device Class (CDC) - * \addtogroup CDC_Serial Serial - * @{ - * \defgroup CDC_Serial_Host Host - * @{ */ + + +//------------- Application Callback -------------// + +// Invoked when a device with CDC interface is mounted +TU_ATTR_WEAK void tuh_cdc_mount_cb(uint8_t dev_addr); + +// Invoked when a device with CDC interface is unmounted +TU_ATTR_WEAK void tuh_cdc_umount_cb(uint8_t dev_addr); + bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb); -- cgit v1.3.1 From f0c51eae44e4cd8f38fdba6469e49b1d98100d7c Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 14 Dec 2022 17:35:01 +0700 Subject: cdc check for bNumEndpoints before checking for endpoint descriptor --- src/class/cdc/cdc_host.c | 64 ++++++++++++++++++++++++++---------------------- src/host/usbh.c | 3 +-- 2 files changed, 36 insertions(+), 31 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index aa3a7e1e5..83fa1bf5e 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -152,13 +152,43 @@ bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xf } //--------------------------------------------------------------------+ -// USBH-CLASS DRIVER API +// CLASS-USBH API //--------------------------------------------------------------------+ + void cdch_init(void) { tu_memclr(cdch_data, sizeof(cdch_data)); } +void cdch_close(uint8_t dev_addr) +{ + TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, ); + + cdch_data_t * p_cdc = get_itf(dev_addr); + + // Invoke application callback + if (tuh_cdc_umount_cb) + { + if (p_cdc->ep_out || p_cdc->ep_in || p_cdc->ep_notif) + { + tuh_cdc_umount_cb(dev_addr); + } + } + + tu_memclr(p_cdc, sizeof(cdch_data_t)); +} + +bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) +{ + (void) ep_addr; + tuh_cdc_xfer_isr( dev_addr, event, 0, xferred_bytes ); + return true; +} + +//--------------------------------------------------------------------+ +// Enumeration +//--------------------------------------------------------------------+ + bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { (void) rhport; @@ -175,7 +205,7 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it p_cdc->itf_num = itf_desc->bInterfaceNumber; p_cdc->itf_protocol = itf_desc->bInterfaceProtocol; - //------------- Communication Interface -------------// + //------------- Control Interface -------------// uint16_t drv_len = tu_desc_len(itf_desc); uint8_t const * p_desc = tu_desc_next(itf_desc); @@ -192,9 +222,10 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it p_desc = tu_desc_next(p_desc); } - if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) ) + // Open notification endpoint of control interface if any + if (itf_desc->bNumEndpoints == 1) { - // notification endpoint + TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)); tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc; TU_ASSERT( tuh_edpt_open(dev_addr, desc_ep) ); @@ -244,29 +275,4 @@ bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num) return true; } -bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) -{ - (void) ep_addr; - tuh_cdc_xfer_isr( dev_addr, event, 0, xferred_bytes ); - return true; -} - -void cdch_close(uint8_t dev_addr) -{ - TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, ); - - cdch_data_t * p_cdc = get_itf(dev_addr); - - // Invoke application callback - if (tuh_cdc_umount_cb) - { - if (p_cdc->ep_out || p_cdc->ep_in || p_cdc->ep_notif) - { - tuh_cdc_umount_cb(dev_addr); - } - } - - tu_memclr(p_cdc, sizeof(cdch_data_t)); -} - #endif diff --git a/src/host/usbh.c b/src/host/usbh.c index ca42a523c..b0cd62bac 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1524,8 +1524,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t)); // Find driver for this interface - uint8_t drv_id; - for (drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) + for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) { usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id]; -- cgit v1.3.1 From f62f97395626f316f1670f1777a0a75877e8e773 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 14 Dec 2022 23:19:47 +0700 Subject: minor rename --- src/class/cdc/cdc_host.c | 51 +++++++++++++++++++++++++++++++++++++++--------- src/class/cdc/cdc_host.h | 26 ++++++++++++++++++------ src/class/hid/hid_host.c | 1 + src/tusb_option.h | 4 ++++ 4 files changed, 67 insertions(+), 15 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 83fa1bf5e..9678b756c 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -37,6 +37,7 @@ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ typedef struct { + // uint8_t daddr; uint8_t itf_num; uint8_t itf_protocol; @@ -46,21 +47,42 @@ typedef struct { cdc_acm_capability_t acm_capability; -} cdch_data_t; + // Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send) + // uint8_t line_state; +#if 0 + + // FIFO + tu_fifo_t rx_ff; + tu_fifo_t tx_ff; + + uint8_t rx_ff_buf[CFG_TUH_CDC_RX_BUFSIZE]; + uint8_t tx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; + +#if CFG_FIFO_MUTEX + osal_mutex_def_t rx_ff_mutex; + osal_mutex_def_t tx_ff_mutex; +#endif + + // Endpoint Transfer buffer + CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUH_CDC_EP_BUFSIZE]; + CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUH_CDC_EP_BUFSIZE]; +#endif + +} cdch_interface_t; //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -static cdch_data_t cdch_data[CFG_TUH_DEVICE_MAX]; +static cdch_interface_t cdch_data[CFG_TUH_DEVICE_MAX]; -static inline cdch_data_t* get_itf(uint8_t dev_addr) +static inline cdch_interface_t* get_itf(uint8_t dev_addr) { return &cdch_data[dev_addr-1]; } bool tuh_cdc_mounted(uint8_t dev_addr) { - cdch_data_t* cdc = get_itf(dev_addr); + cdch_interface_t* cdc = get_itf(dev_addr); return cdc->ep_in && cdc->ep_out; } @@ -68,7 +90,7 @@ bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid) { if ( !tuh_cdc_mounted(dev_addr) ) return false; - cdch_data_t const * p_cdc = get_itf(dev_addr); + cdch_interface_t const * p_cdc = get_itf(dev_addr); switch (pipeid) { @@ -89,6 +111,17 @@ bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid) //--------------------------------------------------------------------+ // APPLICATION API (parameter validation needed) //--------------------------------------------------------------------+ + +uint32_t tuh_cdc_write(uint8_t dev_addr, void const* buffer, uint32_t bufsize) +{ + (void) dev_addr; + (void) buffer; + (void) bufsize; + + return 0; +} + + bool tuh_cdc_serial_is_mounted(uint8_t dev_addr) { // TODO consider all AT Command as serial candidate @@ -122,7 +155,7 @@ bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb) { - cdch_data_t const * p_cdc = get_itf(dev_addr); + cdch_interface_t const * p_cdc = get_itf(dev_addr); tusb_control_request_t const request = { @@ -164,7 +197,7 @@ void cdch_close(uint8_t dev_addr) { TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, ); - cdch_data_t * p_cdc = get_itf(dev_addr); + cdch_interface_t * p_cdc = get_itf(dev_addr); // Invoke application callback if (tuh_cdc_umount_cb) @@ -175,7 +208,7 @@ void cdch_close(uint8_t dev_addr) } } - tu_memclr(p_cdc, sizeof(cdch_data_t)); + tu_memclr(p_cdc, sizeof(cdch_interface_t)); } bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) @@ -200,7 +233,7 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass && 0xFF != itf_desc->bInterfaceProtocol); - cdch_data_t * p_cdc = get_itf(dev_addr); + cdch_interface_t * p_cdc = get_itf(dev_addr); p_cdc->itf_num = itf_desc->bInterfaceNumber; p_cdc->itf_protocol = itf_desc->bInterfaceProtocol; diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index c3b601b34..ce1f0f309 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -34,19 +34,24 @@ #endif //--------------------------------------------------------------------+ -// Application API +// Class Driver Configuration //--------------------------------------------------------------------+ -//------------- Application Callback -------------// +//--------------------------------------------------------------------+ +// Application API +//--------------------------------------------------------------------+ -// Invoked when a device with CDC interface is mounted -TU_ATTR_WEAK void tuh_cdc_mount_cb(uint8_t dev_addr); +bool tuh_cdc_mounted(uint8_t dev_addr); -// Invoked when a device with CDC interface is unmounted -TU_ATTR_WEAK void tuh_cdc_umount_cb(uint8_t dev_addr); +uint32_t tuh_cdc_write(uint8_t dev_addr, void const* buffer, uint32_t bufsize); +//uint32_t tuh_cdc_read(uint8_t dev_addr, void* buffer, uint32_t bufsize); +//--------------------------------------------------------------------+ +// Control Endpoint (Request) API +//--------------------------------------------------------------------+ +// Set Control Line State (DTR, RTS) bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb); static inline bool tuh_cdc_connect(uint8_t dev_addr, tuh_xfer_cb_t complete_cb) @@ -59,6 +64,15 @@ static inline bool tuh_cdc_disconnect(uint8_t dev_addr, tuh_xfer_cb_t complete_c return tuh_cdc_set_control_line_state(dev_addr, false, false, complete_cb); } +//------------- Application Callback -------------// + +// Invoked when a device with CDC interface is mounted +TU_ATTR_WEAK void tuh_cdc_mount_cb(uint8_t dev_addr); + +// Invoked when a device with CDC interface is unmounted +TU_ATTR_WEAK void tuh_cdc_umount_cb(uint8_t dev_addr); + + /** \brief Check if device support CDC Serial interface or not * \param[in] dev_addr device address * \retval true if device supports diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index ca745464c..504ddca1e 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -62,6 +62,7 @@ typedef struct hidh_interface_t instances[CFG_TUH_HID]; } hidh_device_t; +CFG_TUSB_MEM_SECTION static hidh_device_t _hidh_dev[CFG_TUH_DEVICE_MAX]; //------------- Internal prototypes -------------// diff --git a/src/tusb_option.h b/src/tusb_option.h index 9ca6c794b..69972c630 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -256,6 +256,10 @@ typedef int make_iso_compilers_happy; // For backward compatible #define TUSB_OPT_HOST_ENABLED CFG_TUH_ENABLED +// highspeed support indicator +#define TUH_OPT_HIGH_SPEED (CFG_TUH_MAX_SPEED ? (CFG_TUH_MAX_SPEED & OPT_MODE_HIGH_SPEED) : TUP_RHPORT_HIGHSPEED) + + //--------------------------------------------------------------------+ // TODO move later //--------------------------------------------------------------------+ -- cgit v1.3.1 From bd1f7f86ce1b6e82c3942d545e984b74b050004e Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 15 Dec 2022 15:27:39 +0700 Subject: add common EPSIZE for bulk/iso in full and highspeed adding cdc host fifo tx/rx --- src/class/cdc/cdc_device.h | 1 - src/class/cdc/cdc_host.c | 71 ++++++++++++++++++++------------------------- src/class/cdc/cdc_host.h | 19 ++++++++++++ src/common/tusb_types.h | 10 ++++++- src/host/usbh_classdriver.h | 4 +++ 5 files changed, 64 insertions(+), 41 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h index fbc7162a3..f625a7554 100644 --- a/src/class/cdc/cdc_device.h +++ b/src/class/cdc/cdc_device.h @@ -27,7 +27,6 @@ #ifndef _TUSB_CDC_DEVICE_H_ #define _TUSB_CDC_DEVICE_H_ -#include "common/tusb_common.h" #include "cdc.h" //--------------------------------------------------------------------+ diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 9678b756c..da8ad726b 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -37,7 +37,7 @@ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ typedef struct { - // uint8_t daddr; + uint8_t daddr; uint8_t itf_num; uint8_t itf_protocol; @@ -49,7 +49,6 @@ typedef struct { // Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send) // uint8_t line_state; -#if 0 // FIFO tu_fifo_t rx_ff; @@ -64,54 +63,48 @@ typedef struct { #endif // Endpoint Transfer buffer - CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUH_CDC_EP_BUFSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUH_CDC_EP_BUFSIZE]; -#endif + CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUH_CDC_RX_EPSIZE]; + CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUH_CDC_TX_EPSIZE]; } cdch_interface_t; //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -static cdch_interface_t cdch_data[CFG_TUH_DEVICE_MAX]; + +CFG_TUSB_MEM_SECTION +static cdch_interface_t cdch_data[CFG_TUH_CDC]; static inline cdch_interface_t* get_itf(uint8_t dev_addr) { - return &cdch_data[dev_addr-1]; -} + for(size_t i=0; iep_in && cdc->ep_out; + return NULL; } -bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid) +static cdch_interface_t* find_new_itf(void) { - if ( !tuh_cdc_mounted(dev_addr) ) return false; - - cdch_interface_t const * p_cdc = get_itf(dev_addr); - - switch (pipeid) + for(size_t i=0; iep_notif ); - - case CDC_PIPE_DATA_IN: - return usbh_edpt_busy(dev_addr, p_cdc->ep_in ); - - case CDC_PIPE_DATA_OUT: - return usbh_edpt_busy(dev_addr, p_cdc->ep_out ); - - default: - return false; + if (cdch_data[i].daddr == 0) return &cdch_data[i]; } + + return NULL; } //--------------------------------------------------------------------+ // APPLICATION API (parameter validation needed) //--------------------------------------------------------------------+ +bool tuh_cdc_mounted(uint8_t dev_addr) +{ + cdch_interface_t* p_cdc = get_itf(dev_addr); + return p_cdc != NULL; +} + uint32_t tuh_cdc_write(uint8_t dev_addr, void const* buffer, uint32_t bufsize) { (void) dev_addr; @@ -121,7 +114,6 @@ uint32_t tuh_cdc_write(uint8_t dev_addr, void const* buffer, uint32_t bufsize) return 0; } - bool tuh_cdc_serial_is_mounted(uint8_t dev_addr) { // TODO consider all AT Command as serial candidate @@ -156,6 +148,7 @@ bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb) { cdch_interface_t const * p_cdc = get_itf(dev_addr); + TU_VERIFY(p_cdc && p_cdc->acm_capability.support_line_request); tusb_control_request_t const request = { @@ -195,17 +188,13 @@ void cdch_init(void) void cdch_close(uint8_t dev_addr) { - TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, ); - cdch_interface_t * p_cdc = get_itf(dev_addr); + TU_VERIFY(p_cdc, ); // Invoke application callback if (tuh_cdc_umount_cb) { - if (p_cdc->ep_out || p_cdc->ep_in || p_cdc->ep_notif) - { - tuh_cdc_umount_cb(dev_addr); - } + tuh_cdc_umount_cb(dev_addr); } tu_memclr(p_cdc, sizeof(cdch_interface_t)); @@ -233,8 +222,10 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass && 0xFF != itf_desc->bInterfaceProtocol); - cdch_interface_t * p_cdc = get_itf(dev_addr); + cdch_interface_t * p_cdc = find_new_itf(); + TU_VERIFY(p_cdc); + p_cdc->daddr = dev_addr; p_cdc->itf_num = itf_desc->bInterfaceNumber; p_cdc->itf_protocol = itf_desc->bInterfaceProtocol; @@ -302,9 +293,11 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num) { - (void) dev_addr; (void) itf_num; - if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(dev_addr); + + // notify usbh that driver enumeration is complete + usbh_driver_set_config_complete(dev_addr, itf_num); + return true; } diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index ce1f0f309..b2e75902d 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -37,6 +37,25 @@ // Class Driver Configuration //--------------------------------------------------------------------+ +// RX FIFO size +#ifndef CFG_TUH_CDC_RX_BUFSIZE +#define CFG_TUH_CDC_RX_BUFSIZE USBH_EPSIZE_BULK_MAX +#endif + +// RX Endpoint size +#ifndef CFG_TUH_CDC_RX_EPSIZE +#define CFG_TUH_CDC_RX_EPSIZE USBH_EPSIZE_BULK_MAX +#endif + +// TX FIFO size +#ifndef CFG_TUH_CDC_TX_BUFSIZE +#define CFG_TUH_CDC_TX_BUFSIZE USBH_EPSIZE_BULK_MAX +#endif + +// TX Endpoint size +#ifndef CFG_TUH_CDC_TX_EPSIZE +#define CFG_TUH_CDC_TX_EPSIZE USBH_EPSIZE_BULK_MAX +#endif //--------------------------------------------------------------------+ // Application API diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 1bfa7c7d1..c4c9d4133 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -69,6 +69,15 @@ typedef enum TUSB_DIR_IN_MASK = 0x80 }tusb_dir_t; +enum +{ + TUSB_EPSIZE_BULK_FS = 64, + TUSB_EPSIZE_BULK_HS= 512, + + TUSB_EPSIZE_ISO_FS_MAX = 1023, + TUSB_EPSIZE_ISO_HS_MAX = 1024, +}; + /// Isochronous End Point Attributes typedef enum { @@ -243,7 +252,6 @@ enum INTERFACE_INVALID_NUMBER = 0xff }; - typedef enum { MS_OS_20_SET_HEADER_DESCRIPTOR = 0x00, diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h index c156afea0..7f72560c3 100644 --- a/src/host/usbh_classdriver.h +++ b/src/host/usbh_classdriver.h @@ -34,6 +34,10 @@ extern "C" { #endif +enum { + USBH_EPSIZE_BULK_MAX = (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS) +}; + //--------------------------------------------------------------------+ // Class Driver API //--------------------------------------------------------------------+ -- cgit v1.3.1 From 4811b3463ff20fb6eee551b42d66a6e74b411746 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 15 Dec 2022 17:16:19 +0700 Subject: stub --- src/class/cdc/cdc_host.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index da8ad726b..cb0794fa3 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -36,6 +36,14 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ + +//typedef struct { +// tu_fifo_t fifo; +// OSAL_MUTEX_DEF(ff_mutex); +// +// +//}usbh_edpt_stream_t; + typedef struct { uint8_t daddr; uint8_t itf_num; @@ -184,6 +192,13 @@ bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xf void cdch_init(void) { tu_memclr(cdch_data, sizeof(cdch_data)); + +// for(size_t i=0; i Date: Fri, 16 Dec 2022 23:54:21 +0700 Subject: correct cdc usbh_driver_set_config_complete() --- src/class/cdc/cdc_host.c | 32 +++++++++++++++++++++----------- src/host/usbh.c | 3 ++- 2 files changed, 23 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index cb0794fa3..482ccf4be 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -36,13 +36,24 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ +#if 0 +typedef struct { + tu_fifo_t ff; + OSAL_MUTEX_DEF(ff_mutex); +}tu_edpt_stream_t; -//typedef struct { -// tu_fifo_t fifo; -// OSAL_MUTEX_DEF(ff_mutex); -// -// -//}usbh_edpt_stream_t; +uint32_t tud_cdc_read_available (void); +uint32_t tud_cdc_read (void *buffer, uint32_t bufsize); +void tud_cdc_read_flush (void); +bool tud_cdc_peek (uint8_t *ui8); + +uint32_t tud_cdc_write (void const *buffer, uint32_t bufsize); +uint32_t tud_cdc_write_flush (void); +uint32_t tud_cdc_write_available (void); + +//-------------------------------------------------------- +tu_edpt_stream_write() +#endif typedef struct { uint8_t daddr; @@ -65,10 +76,8 @@ typedef struct { uint8_t rx_ff_buf[CFG_TUH_CDC_RX_BUFSIZE]; uint8_t tx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; -#if CFG_FIFO_MUTEX - osal_mutex_def_t rx_ff_mutex; - osal_mutex_def_t tx_ff_mutex; -#endif + OSAL_MUTEX_DEF(rx_ff_mutex); + OSAL_MUTEX_DEF(tx_ff_mutex); // Endpoint Transfer buffer CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUH_CDC_RX_EPSIZE]; @@ -311,7 +320,8 @@ bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num) if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(dev_addr); // notify usbh that driver enumeration is complete - usbh_driver_set_config_complete(dev_addr, itf_num); + // itf_num+1 to account for data interface as well + usbh_driver_set_config_complete(dev_addr, itf_num+1); return true; } diff --git a/src/host/usbh.c b/src/host/usbh.c index b0cd62bac..4b278f2da 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1570,7 +1570,8 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) for(itf_num++; itf_num < CFG_TUH_INTERFACE_MAX; itf_num++) { // continue with next valid interface - // TODO skip IAD binding interface such as CDCs + // IAD binding interface such as CDCs should return itf_num + 1 when complete + // with usbh_driver_set_config_complete() uint8_t const drv_id = dev->itf2drv[itf_num]; if (drv_id != DRVID_INVALID) { -- cgit v1.3.1 From 7d76c172db2f45846c9db45ceed4d879be96296d Mon Sep 17 00:00:00 2001 From: tyustli <43946994+tyustli@users.noreply.github.com> Date: Mon, 19 Dec 2022 17:18:47 +0800 Subject: [add] semaphore reset support for rt-thread add semaphore reset support for rt-thread --- src/osal/osal_rtthread.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h index f8452bfb2..c0d6e91a1 100644 --- a/src/osal/osal_rtthread.h +++ b/src/osal/osal_rtthread.h @@ -63,7 +63,8 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t se } TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) { - // TODO: implement + rt_ubase_t value = 0; + rt_sem_control(sem_hdl, RT_IPC_CMD_RESET, &value); } //--------------------------------------------------------------------+ -- cgit v1.3.1 From e992ff46d24984a8e1143d6d6c1c5aba8c93266f Mon Sep 17 00:00:00 2001 From: tyustli <43946994+tyustli@users.noreply.github.com> Date: Mon, 19 Dec 2022 17:25:35 +0800 Subject: Update osal_rtthread.h --- src/osal/osal_rtthread.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src') diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h index c0d6e91a1..18eb9c693 100644 --- a/src/osal/osal_rtthread.h +++ b/src/osal/osal_rtthread.h @@ -63,8 +63,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t se } TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) { - rt_ubase_t value = 0; - rt_sem_control(sem_hdl, RT_IPC_CMD_RESET, &value); + rt_sem_control(sem_hdl, RT_IPC_CMD_RESET, 0); } //--------------------------------------------------------------------+ -- cgit v1.3.1 From a46ad8fcdfef8c742933843b9c237778fc5ea0a0 Mon Sep 17 00:00:00 2001 From: jbruneaux31 <96246761+jbruneaux31@users.noreply.github.com> Date: Mon, 19 Dec 2022 13:58:54 +0100 Subject: Update osal_freertos.h Fix FreeRTOS task switch even if not required (unitialized variable usage) --- src/osal/osal_freertos.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index 327aa9970..9393d1f26 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -115,7 +115,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t se } else { - BaseType_t xHigherPriorityTaskWoken; + BaseType_t xHigherPriorityTaskWoken = pdFALSE; BaseType_t res = xSemaphoreGiveFromISR(sem_hdl, &xHigherPriorityTaskWoken); #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 @@ -189,7 +189,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void } else { - BaseType_t xHigherPriorityTaskWoken; + BaseType_t xHigherPriorityTaskWoken = pdFALSE; BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &xHigherPriorityTaskWoken); #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 -- cgit v1.3.1 From 7004914d8c6c7d88908776eb153661b6b987e513 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 20 Dec 2022 12:06:59 +0700 Subject: fix hid host incorrect edpt release if failed to transmit add CDC_CONTROL_LINE_STATE_DTR/RTS, TUSB_INDEX_INVALID enum --- src/class/cdc/cdc.h | 10 ++++++++-- src/class/hid/hid_host.c | 2 +- src/common/tusb_types.h | 5 +++++ 3 files changed, 14 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index c428af865..6a9669cf2 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -192,6 +192,12 @@ typedef enum CDC_REQUEST_MDLM_SEMANTIC_MODEL = 0x60, }cdc_management_request_t; +enum +{ + CDC_CONTROL_LINE_STATE_DTR = 0x01, + CDC_CONTROL_LINE_STATE_RTS = 0x02, +}; + //--------------------------------------------------------------------+ // Management Element Notification (Notification Endpoint) //--------------------------------------------------------------------+ @@ -390,8 +396,8 @@ TU_VERIFY_STATIC(sizeof(cdc_line_coding_t) == 7, "size is not correct"); typedef struct TU_ATTR_PACKED { - uint16_t dte_is_present : 1; ///< Indicates to DCE if DTE is presentor not. This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR. - uint16_t half_duplex_carrier_control : 1; + uint16_t dtr : 1; + uint16_t rts : 1; uint16_t : 14; } cdc_line_control_state_t; diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 504ddca1e..42b5e2f4e 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -259,7 +259,7 @@ bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance) if ( !usbh_edpt_xfer(dev_addr, hid_itf->ep_in, hid_itf->epin_buf, hid_itf->epin_size) ) { - usbh_edpt_claim(dev_addr, hid_itf->ep_in); + usbh_edpt_release(dev_addr, hid_itf->ep_in); return false; } diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index c4c9d4133..32cdba450 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -273,6 +273,11 @@ enum CONTROL_STAGE_ACK }; +enum +{ + TUSB_INDEX_INVALID = 0xff +}; + //--------------------------------------------------------------------+ // USB Descriptors //--------------------------------------------------------------------+ -- cgit v1.3.1 From 854e5222aea570a2be2201d8c460f54b87c9108a Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 Dec 2022 00:26:46 +0700 Subject: finalizing cdc host, has a working read/write TODO: first character seems not to get echoed. set control line state seems to failed with LOG < 2 --- examples/host/cdc_msc_hid/src/main.c | 18 -- src/class/cdc/cdc_host.c | 458 +++++++++++++++++++++++++++-------- src/class/cdc/cdc_host.h | 84 +++++-- 3 files changed, 419 insertions(+), 141 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c index 465e457f7..b34810252 100644 --- a/examples/host/cdc_msc_hid/src/main.c +++ b/examples/host/cdc_msc_hid/src/main.c @@ -61,24 +61,6 @@ int main(void) return 0; } -//--------------------------------------------------------------------+ -// USB CDC -//--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION static char serial_in_buffer[64] = { 0 }; - -// invoked ISR context -void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_id, uint32_t xferred_bytes) -{ - (void) event; - (void) pipe_id; - (void) xferred_bytes; - - printf(serial_in_buffer); - tu_memclr(serial_in_buffer, sizeof(serial_in_buffer)); - - tuh_cdc_receive(dev_addr, serial_in_buffer, sizeof(serial_in_buffer), true); // waiting for next data -} - //--------------------------------------------------------------------+ // TinyUSB Callbacks //--------------------------------------------------------------------+ diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 482ccf4be..bdfbe3e74 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -36,52 +36,157 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -#if 0 typedef struct { tu_fifo_t ff; + + // mutex: read if ep rx, write if e tx OSAL_MUTEX_DEF(ff_mutex); + + // TODO xfer_fifo can skip this buffer + uint8_t* ep_buf; + uint16_t ep_bufsize; + uint8_t ep_addr; }tu_edpt_stream_t; -uint32_t tud_cdc_read_available (void); -uint32_t tud_cdc_read (void *buffer, uint32_t bufsize); -void tud_cdc_read_flush (void); -bool tud_cdc_peek (uint8_t *ui8); +bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool use_wr_mutex, bool overwritable, + void* ff_buf, uint16_t ff_bufsize, + uint8_t* ep_buf, uint16_t ep_bufsize) +{ + osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutex); + (void) new_mutex; -uint32_t tud_cdc_write (void const *buffer, uint32_t bufsize); -uint32_t tud_cdc_write_flush (void); -uint32_t tud_cdc_write_available (void); + tu_fifo_config(&s->ff, ff_buf, ff_bufsize, 1, overwritable); + tu_fifo_config_mutex(&s->ff, use_wr_mutex ? new_mutex : NULL, use_wr_mutex ? NULL : new_mutex); -//-------------------------------------------------------- -tu_edpt_stream_write() -#endif + s->ep_buf = ep_buf; + s->ep_bufsize = ep_bufsize; + + return true; +} + +bool tu_edpt_stream_clear(tu_edpt_stream_t* s) +{ + return tu_fifo_clear(&s->ff); +} + +uint32_t tud_edpt_stream_write_flush(uint8_t dev_addr, tu_edpt_stream_t* s) +{ + // No data to send + if ( !tu_fifo_count(&s->ff) ) return 0; + + // Claim the endpoint + // uint8_t const rhport = 0; + // TU_VERIFY( usbd_edpt_claim(rhport, p_cdc->ep_in), 0 ); + TU_VERIFY( usbh_edpt_claim(dev_addr, s->ep_addr) ); + + // Pull data from FIFO -> EP buf + uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize); + + if ( count ) + { + //TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 ); + TU_ASSERT( usbh_edpt_xfer(dev_addr, s->ep_addr, s->ep_buf, count), 0 ); + return count; + }else + { + // Release endpoint since we don't make any transfer + // Note: data is dropped if terminal is not connected + //usbd_edpt_release(rhport, p_cdc->ep_in); + + usbh_edpt_release(dev_addr, s->ep_addr); + return 0; + } +} + +uint32_t tu_edpt_stream_write(uint8_t daddr, tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize) +{ + uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize); + + // flush if queue more than packet size + uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS; + if ( (tu_fifo_count(&s->ff) >= bulk_packet_size) + /* || ((CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE) && tu_fifo_full(&p_cdc->tx_ff)) */ ) + { + tud_edpt_stream_write_flush(daddr, s); + } + + return ret; +} + +void tu_edpt_stream_read_xfer_complete(tu_edpt_stream_t* s, uint32_t xferred_bytes) +{ + tu_fifo_write_n(&s->ff, s->ep_buf, (uint16_t) xferred_bytes); +} + +uint32_t tu_edpt_stream_read_xfer(uint8_t daddr, tu_edpt_stream_t* s) +{ + uint16_t available = tu_fifo_remaining(&s->ff); + + // Prepare for incoming data but only allow what we can store in the ring buffer. + // TODO Actually we can still carry out the transfer, keeping count of received bytes + // and slowly move it to the FIFO when read(). + // This pre-check reduces endpoint claiming + uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS; + TU_VERIFY(available >= bulk_packet_size); + + // claim endpoint + TU_VERIFY(usbh_edpt_claim(daddr, s->ep_addr), 0); + + // fifo can be changed before endpoint is claimed + available = tu_fifo_remaining(&s->ff); + + if ( available >= bulk_packet_size ) + { + // multiple of packet size limit by ep bufsize + uint16_t count = (uint16_t) (available & (bulk_packet_size -1)); + count = tu_min16(count, s->ep_bufsize); + + TU_ASSERT( usbh_edpt_xfer(daddr, s->ep_addr, s->ep_buf, count), 0 ); + return count; + }else + { + // Release endpoint since we don't make any transfer + usbh_edpt_release(daddr, s->ep_addr); + return 0; + } +} + +uint32_t tu_edpt_stream_read(uint8_t daddr, tu_edpt_stream_t* s, void* buffer, uint32_t bufsize) +{ + uint32_t num_read = tu_fifo_read_n(&s->ff, buffer, (uint16_t) bufsize); + tu_edpt_stream_read_xfer(daddr, s); + return num_read; +} + +uint32_t tu_edpt_stream_read_available(tu_edpt_stream_t* s) +{ + return (uint32_t) tu_fifo_count(&s->ff); +} typedef struct { uint8_t daddr; - uint8_t itf_num; - uint8_t itf_protocol; - - uint8_t ep_notif; - uint8_t ep_in; - uint8_t ep_out; + uint8_t bInterfaceNumber; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; cdc_acm_capability_t acm_capability; + uint8_t ep_notif; // Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send) - // uint8_t line_state; + uint8_t line_state; - // FIFO - tu_fifo_t rx_ff; - tu_fifo_t tx_ff; + tuh_xfer_cb_t user_control_cb; - uint8_t rx_ff_buf[CFG_TUH_CDC_RX_BUFSIZE]; - uint8_t tx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; + struct { + tu_edpt_stream_t tx; + tu_edpt_stream_t rx; - OSAL_MUTEX_DEF(rx_ff_mutex); - OSAL_MUTEX_DEF(tx_ff_mutex); + uint8_t tx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; + CFG_TUSB_MEM_ALIGN uint8_t tx_ep_buf[CFG_TUH_CDC_TX_EPSIZE]; - // Endpoint Transfer buffer - CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUH_CDC_RX_EPSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUH_CDC_TX_EPSIZE]; + uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; + CFG_TUSB_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE]; + } stream; } cdch_interface_t; @@ -92,19 +197,33 @@ typedef struct { CFG_TUSB_MEM_SECTION static cdch_interface_t cdch_data[CFG_TUH_CDC]; -static inline cdch_interface_t* get_itf(uint8_t dev_addr) +static inline cdch_interface_t* get_itf(uint8_t idx) { - for(size_t i=0; idaddr != 0) ? p_cdc : NULL; +} + +static inline cdch_interface_t* get_itf_by_ep_addr(uint8_t daddr, uint8_t ep_addr) +{ + for(uint8_t i=0; idaddr == daddr) && + (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr)) + { + return p_cdc; + } } return NULL; } + static cdch_interface_t* find_new_itf(void) { - for(size_t i=0; idaddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i; + } + + return TUSB_INDEX_INVALID; +} + +bool tuh_cdc_itf_get_info(uint8_t idx, tuh_cdc_itf_info_t* info) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc && info); + + info->daddr = p_cdc->daddr; + info->bInterfaceNumber = p_cdc->bInterfaceNumber; + info->bInterfaceSubClass = p_cdc->bInterfaceSubClass; + info->bInterfaceProtocol = p_cdc->bInterfaceProtocol; + + return true; +} + +bool tuh_cdc_mounted(uint8_t idx) +{ + cdch_interface_t* p_cdc = get_itf(idx); return p_cdc != NULL; } -uint32_t tuh_cdc_write(uint8_t dev_addr, void const* buffer, uint32_t bufsize) +bool tuh_cdc_get_dtr(uint8_t idx) { - (void) dev_addr; - (void) buffer; - (void) bufsize; + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); - return 0; + return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR) ? true : false; } -bool tuh_cdc_serial_is_mounted(uint8_t dev_addr) +bool tuh_cdc_get_rts(uint8_t idx) { - // TODO consider all AT Command as serial candidate - return tuh_cdc_mounted(dev_addr) && - (cdch_data[dev_addr-1].itf_protocol <= CDC_COMM_PROTOCOL_ATCOMMAND_CDMA); + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); + + return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false; } -bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify) +uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize) { - (void) is_notify; - TU_VERIFY( tuh_cdc_mounted(dev_addr) ); - TU_VERIFY( p_data != NULL && length); + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); + + return tu_edpt_stream_write(p_cdc->daddr, &p_cdc->stream.tx, buffer, bufsize); +} - uint8_t const ep_out = cdch_data[dev_addr-1].ep_out; - if ( usbh_edpt_busy(dev_addr, ep_out) ) return false; +uint32_t tuh_cdc_write_flush(uint8_t idx) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); - return usbh_edpt_xfer(dev_addr, ep_out, (void*)(uintptr_t) p_data, (uint16_t) length); + return tud_edpt_stream_write_flush(p_cdc->daddr, &p_cdc->stream.tx); } -bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify) +uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) { - (void) is_notify; - TU_VERIFY( tuh_cdc_mounted(dev_addr) ); - TU_VERIFY( p_buffer != NULL && length ); + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); - uint8_t const ep_in = cdch_data[dev_addr-1].ep_in; - if ( usbh_edpt_busy(dev_addr, ep_in) ) return false; + return tu_edpt_stream_read(p_cdc->daddr, &p_cdc->stream.rx, buffer, bufsize); +} - return usbh_edpt_xfer(dev_addr, ep_in, p_buffer, (uint16_t) length); +uint32_t tuh_cdc_read_available(uint8_t idx) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); + + return tu_edpt_stream_read_available(&p_cdc->stream.rx); } -bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb) +//--------------------------------------------------------------------+ +// Control Endpoint API +//--------------------------------------------------------------------+ + +// internal control complete to update state such as line state, encoding +static void cdch_internal_control_complete(tuh_xfer_t* xfer) { - cdch_interface_t const * p_cdc = get_itf(dev_addr); + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t* p_cdc = get_itf(idx); + TU_ASSERT(p_cdc, ); + + if (xfer->result == XFER_RESULT_SUCCESS) + { + switch(xfer->setup->bRequest) + { + case CDC_REQUEST_SET_CONTROL_LINE_STATE: + p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue); + break; + + default: break; + } + } + + xfer->complete_cb = p_cdc->user_control_cb; + xfer->complete_cb(xfer); +} + +bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->acm_capability.support_line_request); tusb_control_request_t const request = @@ -176,19 +356,20 @@ bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xf .direction = TUSB_DIR_OUT }, .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE, - .wValue = tu_htole16((uint16_t) ((dtr ? 1u : 0u) | (rts ? 2u : 0u))), - .wIndex = tu_htole16(p_cdc->itf_num), + .wValue = tu_htole16(line_state), + .wIndex = tu_htole16(p_cdc->bInterfaceNumber), .wLength = 0 }; + p_cdc->user_control_cb = complete_cb; tuh_xfer_t xfer = { - .daddr = dev_addr, + .daddr = p_cdc->daddr, .ep_addr = 0, .setup = &request, .buffer = NULL, - .complete_cb = complete_cb, - .user_data = 0 + .complete_cb = cdch_internal_control_complete, + .user_data = user_data }; return tuh_control_xfer(&xfer); @@ -202,32 +383,79 @@ void cdch_init(void) { tu_memclr(cdch_data, sizeof(cdch_data)); -// for(size_t i=0; istream.tx, true, false, + p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE, + p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE); + + tu_edpt_stream_init(&p_cdc->stream.rx, false, false, + p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE, + p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE); + } } -void cdch_close(uint8_t dev_addr) +void cdch_close(uint8_t daddr) { - cdch_interface_t * p_cdc = get_itf(dev_addr); - TU_VERIFY(p_cdc, ); - - // Invoke application callback - if (tuh_cdc_umount_cb) + for(uint8_t idx=0; idxdaddr == daddr) + { + // Invoke application callback + if (tuh_cdc_umount_cb) tuh_cdc_umount_cb(idx); + + //tu_memclr(p_cdc, sizeof(cdch_interface_t)); + p_cdc->daddr = 0; + p_cdc->bInterfaceNumber = 0; + tu_edpt_stream_clear(&p_cdc->stream.tx); + tu_edpt_stream_clear(&p_cdc->stream.rx); + } } - - tu_memclr(p_cdc, sizeof(cdch_interface_t)); } -bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) +bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) { - (void) ep_addr; - tuh_cdc_xfer_isr( dev_addr, event, 0, xferred_bytes ); + // TODO handle stall response, retry failed transfer ... + TU_ASSERT(event == XFER_RESULT_SUCCESS); + + cdch_interface_t * p_cdc = get_itf_by_ep_addr(daddr, ep_addr); + TU_ASSERT(p_cdc); + + if ( ep_addr == p_cdc->stream.tx.ep_addr ) + { + if ( 0 == tud_edpt_stream_write_flush(daddr, &p_cdc->stream.tx) ) + { + // If there is no data left, a ZLP should be sent if + // xferred_bytes is multiple of EP Packet size and not zero + uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS; + if ( !tu_fifo_count(&p_cdc->stream.tx.ff) && xferred_bytes && (0 == (xferred_bytes & (bulk_packet_size-1))) ) + { + if ( usbh_edpt_claim(daddr, p_cdc->stream.tx.ep_addr) ) + { + usbh_edpt_xfer(daddr, p_cdc->stream.tx.ep_addr, NULL, 0); + } + } + } + } + else if ( ep_addr == p_cdc->stream.rx.ep_addr ) + { + tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes); + + // invoke receive callback + + // prepare for next transfer if needed + tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx); + }else if ( ep_addr == p_cdc->ep_notif ) + { + // TODO handle notification endpoint + }else + { + TU_ASSERT(false); + } + return true; } @@ -238,7 +466,6 @@ bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32 bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { (void) rhport; - (void) max_len; // Only support ACM subclass // Protocol 0xFF can be RNDIS device for windows XP @@ -246,19 +473,22 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass && 0xFF != itf_desc->bInterfaceProtocol); + uint8_t const * p_desc_end = ((uint8_t const*) itf_desc) + max_len; + cdch_interface_t * p_cdc = find_new_itf(); TU_VERIFY(p_cdc); - p_cdc->daddr = dev_addr; - p_cdc->itf_num = itf_desc->bInterfaceNumber; - p_cdc->itf_protocol = itf_desc->bInterfaceProtocol; + p_cdc->daddr = dev_addr; + p_cdc->bInterfaceNumber = itf_desc->bInterfaceNumber; + p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass; + p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol; + p_cdc->line_state = 0; //------------- Control Interface -------------// - uint16_t drv_len = tu_desc_len(itf_desc); uint8_t const * p_desc = tu_desc_next(itf_desc); // Communication Functional Descriptors - while( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len ) + while( (p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc)) ) { if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) ) { @@ -266,7 +496,6 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities; } - drv_len += tu_desc_len(p_desc); p_desc = tu_desc_next(p_desc); } @@ -279,7 +508,6 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it TU_ASSERT( tuh_edpt_open(dev_addr, desc_ep) ); p_cdc->ep_notif = desc_ep->bEndpointAddress; - drv_len += tu_desc_len(p_desc); p_desc = tu_desc_next(p_desc); } @@ -288,42 +516,72 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) ) { // next to endpoint descriptor - drv_len += tu_desc_len(p_desc); p_desc = tu_desc_next(p_desc); // data endpoints expected to be in pairs for(uint32_t i=0; i<2; i++) { tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc; - TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_BULK == desc_ep->bmAttributes.xfer); + TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && + TUSB_XFER_BULK == desc_ep->bmAttributes.xfer); TU_ASSERT(tuh_edpt_open(dev_addr, desc_ep)); if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN ) { - p_cdc->ep_in = desc_ep->bEndpointAddress; + p_cdc->stream.rx.ep_addr = desc_ep->bEndpointAddress; }else { - p_cdc->ep_out = desc_ep->bEndpointAddress; + p_cdc->stream.tx.ep_addr = desc_ep->bEndpointAddress; } - drv_len += tu_desc_len(p_desc); - p_desc = tu_desc_next( p_desc ); + p_desc = tu_desc_next(p_desc); } } return true; } -bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num) +static void config_cdc_complete(uint8_t daddr, uint8_t itf_num) { - if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(dev_addr); + uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num); + + if (idx != TUSB_INDEX_INVALID) + { + if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx); + + // Prepare for incoming data + cdch_interface_t* p_cdc = get_itf(idx); + tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx); + } // notify usbh that driver enumeration is complete // itf_num+1 to account for data interface as well - usbh_driver_set_config_complete(dev_addr, itf_num+1); + usbh_driver_set_config_complete(daddr, itf_num+1); +} + +#if CFG_TUH_CDC_SET_DTRRTS_ON_ENUM +static void config_set_dtr_rts_complete (tuh_xfer_t* xfer) +{ + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + config_cdc_complete(xfer->daddr, itf_num); +} + +bool cdch_set_config(uint8_t daddr, uint8_t itf_num) +{ + uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num); + return tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_SET_DTRRTS_ON_ENUM, config_set_dtr_rts_complete, 0); +} + +#else + +bool cdch_set_config(uint8_t daddr, uint8_t itf_num) +{ + config_cdc_complete(daddr, itf_num); return true; } #endif + +#endif diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index b2e75902d..54e082e7d 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -37,6 +37,11 @@ // Class Driver Configuration //--------------------------------------------------------------------+ +// Set DTR ( bit 0), RTS (bit 1) on enumeration/mounted +#ifndef CFG_TUH_CDC_SET_DTRRTS_ON_ENUM +#define CFG_TUH_CDC_SET_DTRRTS_ON_ENUM 0 +#endif + // RX FIFO size #ifndef CFG_TUH_CDC_RX_BUFSIZE #define CFG_TUH_CDC_RX_BUFSIZE USBH_EPSIZE_BULK_MAX @@ -61,43 +66,76 @@ // Application API //--------------------------------------------------------------------+ -bool tuh_cdc_mounted(uint8_t dev_addr); +typedef struct +{ + uint8_t daddr; + uint8_t bInterfaceNumber; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; +} tuh_cdc_itf_info_t; + +// Get Interface index from device address + interface number +// return TUSB_INDEX_INVALID (0xFF) if not found +uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num); + +// Get Interface information +// return true if index is correct and interface is currently mounted +bool tuh_cdc_itf_get_info(uint8_t idx, tuh_cdc_itf_info_t* info); + +// Check if a interface is mounted +bool tuh_cdc_mounted(uint8_t idx); + +// Get current DTR status +bool tuh_cdc_get_dtr(uint8_t idx); + +// Get current RTS status +bool tuh_cdc_get_rts(uint8_t idx); + +// Check if interface is connected (DTR active) +TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_connected(uint8_t idx) +{ + return tuh_cdc_get_dtr(idx); +} + +// Write to cdc interface +uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize); + +// Force sending data if possible, return number of forced bytes +uint32_t tuh_cdc_write_flush(uint8_t idx); + +// Read from cdc interface +uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize); -uint32_t tuh_cdc_write(uint8_t dev_addr, void const* buffer, uint32_t bufsize); -//uint32_t tuh_cdc_read(uint8_t dev_addr, void* buffer, uint32_t bufsize); +// Get the number of bytes available for reading +uint32_t tuh_cdc_read_available(uint8_t idx); //--------------------------------------------------------------------+ // Control Endpoint (Request) API //--------------------------------------------------------------------+ -// Set Control Line State (DTR, RTS) -bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb); +// Send control request to Set Control Line State: DTR (bit 0), RTS (bit 1) +bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static inline bool tuh_cdc_connect(uint8_t dev_addr, tuh_xfer_cb_t complete_cb) +// Connect by set both DTR, RTS +static inline bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - return tuh_cdc_set_control_line_state(dev_addr, true, true, complete_cb); + return tuh_cdc_set_control_line_state(idx, CDC_CONTROL_LINE_STATE_DTR | CDC_CONTROL_LINE_STATE_RTS, complete_cb, user_data); } -static inline bool tuh_cdc_disconnect(uint8_t dev_addr, tuh_xfer_cb_t complete_cb) +// Disconnect by clear both DTR, RTS +static inline bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - return tuh_cdc_set_control_line_state(dev_addr, false, false, complete_cb); + return tuh_cdc_set_control_line_state(idx, 0x00, complete_cb, user_data); } //------------- Application Callback -------------// // Invoked when a device with CDC interface is mounted -TU_ATTR_WEAK void tuh_cdc_mount_cb(uint8_t dev_addr); +// idx is index of cdc interface in the internal pool. +TU_ATTR_WEAK void tuh_cdc_mount_cb(uint8_t idx); // Invoked when a device with CDC interface is unmounted -TU_ATTR_WEAK void tuh_cdc_umount_cb(uint8_t dev_addr); - - -/** \brief Check if device support CDC Serial interface or not - * \param[in] dev_addr device address - * \retval true if device supports - * \retval false if device does not support or is not mounted - */ -bool tuh_cdc_serial_is_mounted(uint8_t dev_addr); +TU_ATTR_WEAK void tuh_cdc_umount_cb(uint8_t idx); /** \brief Check if the interface is currently busy or not * \param[in] dev_addr device address @@ -108,7 +146,7 @@ bool tuh_cdc_serial_is_mounted(uint8_t dev_addr); * can be scheduled. User needs to make sure the corresponding interface is mounted * (by \ref tuh_cdc_serial_is_mounted) before calling this function. */ -bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid); +// bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid); /** \brief Perform USB OUT transfer to device * \param[in] dev_addr device address @@ -121,7 +159,7 @@ bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid); * \note This function is non-blocking and returns immediately. The result of USB transfer will be reported by the * interface's callback function. \a p_data must be declared with \ref CFG_TUSB_MEM_SECTION. */ -bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify); +// bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify); /** \brief Perform USB IN transfer to get data from device * \param[in] dev_addr device address @@ -134,7 +172,7 @@ bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool i * \note This function is non-blocking and returns immediately. The result of USB transfer will be reported by the * interface's callback function. \a p_data must be declared with \ref CFG_TUSB_MEM_SECTION. */ -bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify); +// bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify); //--------------------------------------------------------------------+ // CDC APPLICATION CALLBACKS @@ -151,7 +189,7 @@ bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is * - XFER_RESULT_STALLED : previously scheduled transfer is stalled by device. * \note */ -void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_id, uint32_t xferred_bytes); +// void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_id, uint32_t xferred_bytes); /// @} // group CDC_Serial_Host /// @} -- cgit v1.3.1 From 37529c41da3884c235ac4f582b7202331877142c Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 Dec 2022 10:46:47 +0700 Subject: fix ci --- src/class/cdc/cdc_host.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index bdfbe3e74..5aec41cbc 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -54,6 +54,7 @@ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool use_wr_mutex, bool overwritab { osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutex); (void) new_mutex; + (void) use_wr_mutex; tu_fifo_config(&s->ff, ff_buf, ff_bufsize, 1, overwritable); tu_fifo_config_mutex(&s->ff, use_wr_mutex ? new_mutex : NULL, use_wr_mutex ? NULL : new_mutex); -- cgit v1.3.1 From d1ea3844f70a5add6e073aa8fa6b562413db4929 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 Dec 2022 11:04:57 +0700 Subject: rename TU_LOG_VAR to TU_LOG_PTR, print out setup of failed control transfer when LOG=1 --- src/common/tusb_debug.h | 18 +++++++++--------- src/host/usbh.c | 8 ++++++-- 2 files changed, 15 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h index ac5bee6ec..65fd1920d 100644 --- a/src/common/tusb_debug.h +++ b/src/common/tusb_debug.h @@ -66,7 +66,7 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize) #define TU_LOG(n, ...) TU_XSTRCAT(TU_LOG, n)(__VA_ARGS__) #define TU_LOG_MEM(n, ...) TU_XSTRCAT3(TU_LOG, n, _MEM)(__VA_ARGS__) #define TU_LOG_ARR(n, ...) TU_XSTRCAT3(TU_LOG, n, _ARR)(__VA_ARGS__) -#define TU_LOG_VAR(n, ...) TU_XSTRCAT3(TU_LOG, n, _VAR)(__VA_ARGS__) +#define TU_LOG_PTR(n, ...) TU_XSTRCAT3(TU_LOG, n, _PTR)(__VA_ARGS__) #define TU_LOG_INT(n, ...) TU_XSTRCAT3(TU_LOG, n, _INT)(__VA_ARGS__) #define TU_LOG_HEX(n, ...) TU_XSTRCAT3(TU_LOG, n, _HEX)(__VA_ARGS__) #define TU_LOG_LOCATION() tu_printf("%s: %d:\r\n", __PRETTY_FUNCTION__, __LINE__) @@ -76,7 +76,7 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize) #define TU_LOG1 tu_printf #define TU_LOG1_MEM tu_print_mem #define TU_LOG1_ARR(_x, _n) tu_print_arr((uint8_t const*)(_x), _n) -#define TU_LOG1_VAR(_x) tu_print_arr((uint8_t const*)(_x), sizeof(*(_x))) +#define TU_LOG1_PTR(_x) tu_print_arr((uint8_t const*)(_x), sizeof(*(_x))) #define TU_LOG1_INT(_x) tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) ) #define TU_LOG1_HEX(_x) tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) ) @@ -85,7 +85,7 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize) #define TU_LOG2 TU_LOG1 #define TU_LOG2_MEM TU_LOG1_MEM #define TU_LOG2_ARR TU_LOG1_ARR - #define TU_LOG2_VAR TU_LOG1_VAR + #define TU_LOG2_PTR TU_LOG1_PTR #define TU_LOG2_INT TU_LOG1_INT #define TU_LOG2_HEX TU_LOG1_HEX #endif @@ -95,7 +95,7 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize) #define TU_LOG3 TU_LOG1 #define TU_LOG3_MEM TU_LOG1_MEM #define TU_LOG3_ARR TU_LOG1_ARR - #define TU_LOG3_VAR TU_LOG1_VAR + #define TU_LOG3_PTR TU_LOG1_PTR #define TU_LOG3_INT TU_LOG1_INT #define TU_LOG3_HEX TU_LOG1_HEX #endif @@ -132,7 +132,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3 #ifndef TU_LOG #define TU_LOG(n, ...) #define TU_LOG_MEM(n, ...) - #define TU_LOG_VAR(n, ...) + #define TU_LOG_PTR(n, ...) #define TU_LOG_INT(n, ...) #define TU_LOG_HEX(n, ...) #define TU_LOG_LOCATION() @@ -143,14 +143,14 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3 #define TU_LOG0(...) #define TU_LOG0_MEM(...) -#define TU_LOG0_VAR(...) +#define TU_LOG0_PTR(...) #define TU_LOG0_INT(...) #define TU_LOG0_HEX(...) #ifndef TU_LOG1 #define TU_LOG1(...) #define TU_LOG1_MEM(...) - #define TU_LOG1_VAR(...) + #define TU_LOG1_PTR(...) #define TU_LOG1_INT(...) #define TU_LOG1_HEX(...) #endif @@ -158,7 +158,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3 #ifndef TU_LOG2 #define TU_LOG2(...) #define TU_LOG2_MEM(...) - #define TU_LOG2_VAR(...) + #define TU_LOG2_PTR(...) #define TU_LOG2_INT(...) #define TU_LOG2_HEX(...) #endif @@ -166,7 +166,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3 #ifndef TU_LOG3 #define TU_LOG3(...) #define TU_LOG3_MEM(...) - #define TU_LOG3_VAR(...) + #define TU_LOG3_PTR(...) #define TU_LOG3_INT(...) #define TU_LOG3_HEX(...) #endif diff --git a/src/host/usbh.c b/src/host/usbh.c index 4b278f2da..59b1c3280 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -540,7 +540,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) const uint8_t rhport = usbh_get_rhport(daddr); TU_LOG2("[%u:%u] %s: ", rhport, daddr, xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[xfer->setup->bRequest] : "Unknown Request"); - TU_LOG2_VAR(xfer->setup); + TU_LOG2_PTR(xfer->setup); TU_LOG2("\r\n"); if (xfer->complete_cb) @@ -618,7 +618,11 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result if (XFER_RESULT_SUCCESS != result) { - TU_LOG1("[%u:%u] Control %s\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED"); + TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes); + #if CFG_TUSB_DEBUG == 1 + TU_LOG1_PTR(request); + TU_LOG1("\r\n"); + #endif // terminate transfer if any stage failed _xfer_complete(dev_addr, result); -- cgit v1.3.1 From cb2af4c0bc096e57c3486945eda43dbc26b3829a Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 Dec 2022 11:46:58 +0700 Subject: minor debug log --- src/class/cdc/cdc_host.c | 8 +++++ src/class/msc/msc_host.c | 13 +++++--- src/host/usbh.c | 85 ++++++++++++++++++++++++++---------------------- 3 files changed, 63 insertions(+), 43 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 5aec41cbc..83c623884 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -33,6 +33,12 @@ #include "cdc_host.h" + +// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message +#define CDCH_DEBUG 2 + +#define TU_LOG_CDCH(...) TU_LOG(CDCH_DEBUG, __VA_ARGS__) + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ @@ -348,6 +354,8 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->acm_capability.support_line_request); + TU_LOG_CDCH("CDC Set Control Line State\r\n"); + tusb_control_request_t const request = { .bmRequestType_bit = diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c index 32f75a84b..6724e486c 100644 --- a/src/class/msc/msc_host.c +++ b/src/class/msc/msc_host.c @@ -33,6 +33,11 @@ #include "msc_host.h" +// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message +#define MSCH_DEBUG 2 + +#define TU_LOG_MSCH(...) TU_LOG(MSCH_DEBUG, __VA_ARGS__) + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ @@ -417,7 +422,7 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num) p_msc->configured = true; //------------- Get Max Lun -------------// - TU_LOG2("MSC Get Max Lun\r\n"); + TU_LOG_MSCH("MSC Get Max Lun\r\n"); tusb_control_request_t const request = { .bmRequestType_bit = @@ -456,7 +461,7 @@ static void config_get_maxlun_complete (tuh_xfer_t* xfer) p_msc->max_lun++; // MAX LUN is minus 1 by specs // TODO multiple LUN support - TU_LOG2("SCSI Test Unit Ready\r\n"); + TU_LOG_MSCH("SCSI Test Unit Ready\r\n"); uint8_t const lun = 0; tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete, 0); } @@ -469,14 +474,14 @@ static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_d if (csw->status == 0) { // Unit is ready, read its capacity - TU_LOG2("SCSI Read Capacity\r\n"); + TU_LOG_MSCH("SCSI Read Capacity\r\n"); tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer), config_read_capacity_complete, 0); }else { // Note: During enumeration, some device fails Test Unit Ready and require a few retries // with Request Sense to start working !! // TODO limit number of retries - TU_LOG2("SCSI Request Sense\r\n"); + TU_LOG_MSCH("SCSI Request Sense\r\n"); TU_ASSERT(tuh_msc_request_sense(dev_addr, cbw->lun, _msch_buffer, config_request_sense_complete, 0)); } diff --git a/src/host/usbh.c b/src/host/usbh.c index 59b1c3280..36fc5fded 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -46,8 +46,10 @@ #define CFG_TUH_INTERFACE_MAX 8 #endif -// Debug level of USBD -#define USBH_DBG_LVL 2 +// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message +#define USBH_DEBUG 2 + +#define TU_LOG_USBH(...) TU_LOG(USBH_DEBUG, __VA_ARGS__) //--------------------------------------------------------------------+ // USBH-HCD common data structure @@ -324,11 +326,11 @@ bool tuh_init(uint8_t controller_id) // skip if already initialized if ( tuh_inited() ) return true; - TU_LOG2("USBH init on controller %u\r\n", controller_id); - TU_LOG2_INT(sizeof(usbh_device_t)); - TU_LOG2_INT(sizeof(hcd_event_t)); - TU_LOG2_INT(sizeof(_ctrl_xfer)); - TU_LOG2_INT(sizeof(tuh_xfer_t)); + TU_LOG_USBH("USBH init on controller %u\r\n", controller_id); + TU_LOG_INT(USBH_DEBUG, sizeof(usbh_device_t)); + TU_LOG_INT(USBH_DEBUG, sizeof(hcd_event_t)); + TU_LOG_INT(USBH_DEBUG, sizeof(_ctrl_xfer)); + TU_LOG_INT(USBH_DEBUG, sizeof(tuh_xfer_t)); // Event queue _usbh_q = osal_queue_create( &_usbh_qdef ); @@ -353,7 +355,7 @@ bool tuh_init(uint8_t controller_id) // Class drivers for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) { - TU_LOG2("%s init\r\n", usbh_class_drivers[drv_id].name); + TU_LOG_USBH("%s init\r\n", usbh_class_drivers[drv_id].name); usbh_class_drivers[drv_id].init(); } @@ -401,12 +403,12 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) case HCD_EVENT_DEVICE_ATTACH: // TODO due to the shared _usbh_ctrl_buf, we must complete enumerating // one device before enumerating another one. - TU_LOG2("[%u:] USBH DEVICE ATTACH\r\n", event.rhport); + TU_LOG_USBH("[%u:] USBH DEVICE ATTACH\r\n", event.rhport); enum_new_device(&event); break; case HCD_EVENT_DEVICE_REMOVE: - TU_LOG2("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port); + TU_LOG_USBH("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port); process_device_unplugged(event.rhport, event.connection.hub_addr, event.connection.hub_port); #if CFG_TUH_HUB @@ -425,7 +427,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const ep_dir = tu_edpt_dir(ep_addr); - TU_LOG2("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len); + TU_LOG_USBH("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len); if (event.dev_addr == 0) { @@ -449,7 +451,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) uint8_t drv_id = dev->ep2drv[epnum][ep_dir]; if(drv_id < USBH_CLASS_DRIVER_COUNT) { - TU_LOG2("%s xfer callback\r\n", usbh_class_drivers[drv_id].name); + TU_LOG_USBH("%s xfer callback\r\n", usbh_class_drivers[drv_id].name); usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len); } else @@ -539,9 +541,11 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) TU_VERIFY(is_idle); const uint8_t rhport = usbh_get_rhport(daddr); - TU_LOG2("[%u:%u] %s: ", rhport, daddr, xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[xfer->setup->bRequest] : "Unknown Request"); - TU_LOG2_PTR(xfer->setup); - TU_LOG2("\r\n"); + TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr, + (xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ? + tu_str_std_request[xfer->setup->bRequest] : "Class Request"); + TU_LOG_PTR(USBH_DEBUG, xfer->setup); + TU_LOG_USBH("\r\n"); if (xfer->complete_cb) { @@ -585,7 +589,7 @@ TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage) static void _xfer_complete(uint8_t daddr, xfer_result_t result) { - TU_LOG2("\r\n"); + TU_LOG_USBH("\r\n"); // duplicate xfer since user can execute control transfer within callback tusb_control_request_t const request = _ctrl_xfer.request; @@ -643,8 +647,8 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result case CONTROL_STAGE_DATA: if (request->wLength) { - TU_LOG2("[%u:%u] Control data:\r\n", rhport, dev_addr); - TU_LOG2_MEM(_ctrl_xfer.buffer, xferred_bytes, 2); + TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, dev_addr); + TU_LOG_MEM(USBH_DEBUG, _ctrl_xfer.buffer, xferred_bytes, 2); } _ctrl_xfer.actual_len = (uint16_t) xferred_bytes; @@ -760,7 +764,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b uint8_t const dir = tu_edpt_dir(ep_addr); tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir]; - TU_LOG2(" Queue EP %02X with %u bytes ... ", ep_addr, total_bytes); + TU_LOG_USBH(" Queue EP %02X with %u bytes ... ", ep_addr, total_bytes); // Attempt to transfer on a busy endpoint, sound like an race condition ! TU_ASSERT(ep_state->busy == 0); @@ -776,7 +780,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b if ( hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes) ) { - TU_LOG2("OK\r\n"); + TU_LOG_USBH("OK\r\n"); return true; }else { @@ -791,7 +795,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size) { - TU_LOG2("[%u:%u] Open EP0 with Size = %u\r\n", usbh_get_rhport(dev_addr), dev_addr, max_packet_size); + TU_LOG_USBH("[%u:%u] Open EP0 with Size = %u\r\n", usbh_get_rhport(dev_addr), dev_addr, max_packet_size); tusb_desc_endpoint_t ep0_desc = { @@ -960,7 +964,7 @@ bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG2("HID Get Report Descriptor\r\n"); + TU_LOG_USBH("HID Get Report Descriptor\r\n"); tusb_control_request_t const request = { .bmRequestType_bit = @@ -999,7 +1003,7 @@ bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG2("Set Configuration = %d\r\n", config_num); + TU_LOG_USBH("Set Configuration = %d\r\n", config_num); tusb_control_request_t const request = { @@ -1103,11 +1107,11 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h (hub_port == 0 || dev->hub_port == hub_port) && // hub_port = 0 means all devices of downstream hub dev->connected) { - TU_LOG2(" Address = %u\r\n", dev_addr); + TU_LOG_USBH(" Address = %u\r\n", dev_addr); if (is_hub_addr(dev_addr)) { - TU_LOG(USBH_DBG_LVL, "HUB address = %u is unmounted\r\n", dev_addr); + TU_LOG(USBH_DEBUG, "HUB address = %u is unmounted\r\n", dev_addr); // If the device itself is a usb hub, unplug downstream devices. // FIXME un-roll recursive calls to prevent potential stack overflow process_device_unplugged(rhport, dev_addr, 0); @@ -1120,7 +1124,7 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h // Close class driver for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) { - TU_LOG2("%s close\r\n", usbh_class_drivers[drv_id].name); + TU_LOG_USBH("%s close\r\n", usbh_class_drivers[drv_id].name); usbh_class_drivers[drv_id].close(dev_addr); } @@ -1245,7 +1249,7 @@ static void process_enumeration(tuh_xfer_t* xfer) TU_ASSERT( usbh_edpt_control_open(addr0, 8), ); // Get first 8 bytes of device descriptor for Control Endpoint size - TU_LOG2("Get 8 byte of Device Descriptor\r\n"); + TU_LOG_USBH("Get 8 byte of Device Descriptor\r\n"); TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, process_enumeration, ENUM_SET_ADDR), ); } break; @@ -1254,7 +1258,7 @@ static void process_enumeration(tuh_xfer_t* xfer) case ENUM_RESET_2: // TODO not used by now, but may be needed for some devices !? // Reset device again before Set Address - TU_LOG2("Port reset2 \r\n"); + TU_LOG_USBH("Port reset2 \r\n"); if (_dev0.hub_addr == 0) { // connected directly to roothub @@ -1294,7 +1298,7 @@ static void process_enumeration(tuh_xfer_t* xfer) TU_ASSERT( usbh_edpt_control_open(new_addr, new_dev->ep0_size), ); // Get full device descriptor - TU_LOG2("Get Device Descriptor\r\n"); + TU_LOG_USBH("Get Device Descriptor\r\n"); TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC), ); } break; @@ -1315,7 +1319,7 @@ static void process_enumeration(tuh_xfer_t* xfer) // Get 9-byte for total length uint8_t const config_idx = CONFIG_NUM - 1; - TU_LOG2("Get Configuration[0] Descriptor (9 bytes)\r\n"); + TU_LOG_USBH("Get Configuration[0] Descriptor (9 bytes)\r\n"); TU_ASSERT( tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, 9, process_enumeration, ENUM_GET_FULL_CONFIG_DESC), ); } break; @@ -1332,7 +1336,7 @@ static void process_enumeration(tuh_xfer_t* xfer) // Get full configuration descriptor uint8_t const config_idx = CONFIG_NUM - 1; - TU_LOG2("Get Configuration[0] Descriptor\r\n"); + TU_LOG_USBH("Get Configuration[0] Descriptor\r\n"); TU_ASSERT( tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, total_len, process_enumeration, ENUM_SET_CONFIG), ); } break; @@ -1347,7 +1351,7 @@ static void process_enumeration(tuh_xfer_t* xfer) case ENUM_CONFIG_DRIVER: { - TU_LOG2("Device configured\r\n"); + TU_LOG_USBH("Device configured\r\n"); usbh_device_t* dev = get_device(daddr); TU_ASSERT(dev, ); @@ -1387,7 +1391,7 @@ static bool enum_new_device(hcd_event_t* event) if ( !hcd_port_connect_status(_dev0.rhport) ) return true; _dev0.speed = hcd_port_speed_get(_dev0.rhport ); - TU_LOG2("%s Speed\r\n", tu_str_speed[_dev0.speed]); + TU_LOG_USBH("%s Speed\r\n", tu_str_speed[_dev0.speed]); // fake transfer to kick-off the enumeration process tuh_xfer_t xfer; @@ -1444,7 +1448,7 @@ static bool enum_request_set_addr(void) uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB); TU_ASSERT(new_addr != 0); - TU_LOG2("Set Address = %d\r\n", new_addr); + TU_LOG_USBH("Set Address = %d\r\n", new_addr); usbh_device_t* new_dev = get_device(new_addr); @@ -1488,9 +1492,12 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur { usbh_device_t* dev = get_device(dev_addr); - uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength); + uint16_t const total_len = tu_le16toh(desc_cfg->wTotalLength); + uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + total_len; uint8_t const* p_desc = tu_desc_next(desc_cfg); + TU_LOG_USBH("Parsing Configuration descriptor (wTotalLength = %u)\r\n", total_len); + // parse each interfaces while( p_desc < desc_end ) { @@ -1535,7 +1542,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur if ( driver->open(dev->rhport, dev_addr, desc_itf, drv_len) ) { // open successfully - TU_LOG2(" %s opened\r\n", driver->name); + TU_LOG_USBH(" %s opened\r\n", driver->name); // bind (associated) interfaces to found driver for(uint8_t i=0; i= USBH_CLASS_DRIVER_COUNT ) { - TU_LOG(USBH_DBG_LVL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n", + TU_LOG(USBH_DEBUG, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n", desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol); } } @@ -1580,7 +1587,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) if (drv_id != DRVID_INVALID) { usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id]; - TU_LOG2("%s set config: itf = %u\r\n", driver->name, itf_num); + TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num); driver->set_config(dev_addr, itf_num); break; } @@ -1593,7 +1600,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) if (is_hub_addr(dev_addr)) { - TU_LOG(USBH_DBG_LVL, "HUB address = %u is mounted\r\n", dev_addr); + TU_LOG(USBH_DEBUG, "HUB address = %u is mounted\r\n", dev_addr); }else { // Invoke callback if available -- cgit v1.3.1 From 76021c7359fd330f547a1c22c5c00a23aa5c2bf0 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 Dec 2022 11:49:28 +0700 Subject: rename tud_edpt_stream_write_xfer --- src/class/cdc/cdc_host.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 83c623884..79e29796c 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -76,7 +76,7 @@ bool tu_edpt_stream_clear(tu_edpt_stream_t* s) return tu_fifo_clear(&s->ff); } -uint32_t tud_edpt_stream_write_flush(uint8_t dev_addr, tu_edpt_stream_t* s) +uint32_t tud_edpt_stream_write_xfer(uint8_t dev_addr, tu_edpt_stream_t* s) { // No data to send if ( !tu_fifo_count(&s->ff) ) return 0; @@ -114,7 +114,7 @@ uint32_t tu_edpt_stream_write(uint8_t daddr, tu_edpt_stream_t* s, void const *bu if ( (tu_fifo_count(&s->ff) >= bulk_packet_size) /* || ((CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE) && tu_fifo_full(&p_cdc->tx_ff)) */ ) { - tud_edpt_stream_write_flush(daddr, s); + tud_edpt_stream_write_xfer(daddr, s); } return ret; @@ -302,7 +302,7 @@ uint32_t tuh_cdc_write_flush(uint8_t idx) cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return tud_edpt_stream_write_flush(p_cdc->daddr, &p_cdc->stream.tx); + return tud_edpt_stream_write_xfer(p_cdc->daddr, &p_cdc->stream.tx); } uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) @@ -435,7 +435,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t if ( ep_addr == p_cdc->stream.tx.ep_addr ) { - if ( 0 == tud_edpt_stream_write_flush(daddr, &p_cdc->stream.tx) ) + if ( 0 == tud_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx) ) { // If there is no data left, a ZLP should be sent if // xferred_bytes is multiple of EP Packet size and not zero -- cgit v1.3.1 From 22b62f871263ae170965a037e4f677a8a8e49709 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 Dec 2022 12:07:12 +0700 Subject: add tu_edpt_stream_write_zlp_if_needed() --- src/class/cdc/cdc_host.c | 44 ++++++++++++++++++++++++++------------------ 1 file changed, 26 insertions(+), 18 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 79e29796c..f8d996e17 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -76,15 +76,30 @@ bool tu_edpt_stream_clear(tu_edpt_stream_t* s) return tu_fifo_clear(&s->ff); } -uint32_t tud_edpt_stream_write_xfer(uint8_t dev_addr, tu_edpt_stream_t* s) +bool tu_edpt_stream_write_zlp_if_needed(uint8_t daddr, tu_edpt_stream_t* s, uint32_t last_xferred_bytes) { - // No data to send - if ( !tu_fifo_count(&s->ff) ) return 0; + uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS; + + // ZLP condition: no pending data, last transferred bytes is multiple of packet size + TU_VERIFY( !tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (bulk_packet_size-1))) ); + + if ( usbh_edpt_claim(daddr, s->ep_addr) ) + { + TU_ASSERT( usbh_edpt_xfer(daddr, s->ep_addr, NULL, 0) ); + } + + return true; +} + +uint32_t tu_edpt_stream_write_xfer(uint8_t daddr, tu_edpt_stream_t* s) +{ + // skip if no data + TU_VERIFY( tu_fifo_count(&s->ff), 0 ); // Claim the endpoint // uint8_t const rhport = 0; // TU_VERIFY( usbd_edpt_claim(rhport, p_cdc->ep_in), 0 ); - TU_VERIFY( usbh_edpt_claim(dev_addr, s->ep_addr) ); + TU_VERIFY( usbh_edpt_claim(daddr, s->ep_addr) ); // Pull data from FIFO -> EP buf uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize); @@ -92,7 +107,7 @@ uint32_t tud_edpt_stream_write_xfer(uint8_t dev_addr, tu_edpt_stream_t* s) if ( count ) { //TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 ); - TU_ASSERT( usbh_edpt_xfer(dev_addr, s->ep_addr, s->ep_buf, count), 0 ); + TU_ASSERT( usbh_edpt_xfer(daddr, s->ep_addr, s->ep_buf, count), 0 ); return count; }else { @@ -100,7 +115,7 @@ uint32_t tud_edpt_stream_write_xfer(uint8_t dev_addr, tu_edpt_stream_t* s) // Note: data is dropped if terminal is not connected //usbd_edpt_release(rhport, p_cdc->ep_in); - usbh_edpt_release(dev_addr, s->ep_addr); + usbh_edpt_release(daddr, s->ep_addr); return 0; } } @@ -114,7 +129,7 @@ uint32_t tu_edpt_stream_write(uint8_t daddr, tu_edpt_stream_t* s, void const *bu if ( (tu_fifo_count(&s->ff) >= bulk_packet_size) /* || ((CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE) && tu_fifo_full(&p_cdc->tx_ff)) */ ) { - tud_edpt_stream_write_xfer(daddr, s); + tu_edpt_stream_write_xfer(daddr, s); } return ret; @@ -302,7 +317,7 @@ uint32_t tuh_cdc_write_flush(uint8_t idx) cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return tud_edpt_stream_write_xfer(p_cdc->daddr, &p_cdc->stream.tx); + return tu_edpt_stream_write_xfer(p_cdc->daddr, &p_cdc->stream.tx); } uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) @@ -435,18 +450,11 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t if ( ep_addr == p_cdc->stream.tx.ep_addr ) { - if ( 0 == tud_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx) ) + if ( 0 == tu_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx) ) { - // If there is no data left, a ZLP should be sent if + // If there is no data left, a ZLP should be sent if needed // xferred_bytes is multiple of EP Packet size and not zero - uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS; - if ( !tu_fifo_count(&p_cdc->stream.tx.ff) && xferred_bytes && (0 == (xferred_bytes & (bulk_packet_size-1))) ) - { - if ( usbh_edpt_claim(daddr, p_cdc->stream.tx.ep_addr) ) - { - usbh_edpt_xfer(daddr, p_cdc->stream.tx.ep_addr, NULL, 0); - } - } + tu_edpt_stream_write_zlp_if_needed(daddr, &p_cdc->stream.tx, xferred_bytes); } } else if ( ep_addr == p_cdc->stream.rx.ep_addr ) -- cgit v1.3.1 From badb30a6c3d0748b52d7c9db5a48b7bef21b4c1a Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 Dec 2022 12:25:13 +0700 Subject: correct cdc host app --- examples/host/cdc_msc_hid/src/cdc_app.c | 17 +++++++++++------ src/class/cdc/cdc_host.c | 3 ++- 2 files changed, 13 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c index 123cb33f0..db652efde 100644 --- a/examples/host/cdc_msc_hid/src/cdc_app.c +++ b/examples/host/cdc_msc_hid/src/cdc_app.c @@ -52,26 +52,31 @@ size_t get_console_inputs(uint8_t* buf, size_t bufsize) void cdc_app_task(void) { uint8_t buf[64+1]; // +1 for extra null character - memset(buf, 0, sizeof(buf)); + uint32_t const bufsize = sizeof(buf)-1; - size_t count = get_console_inputs(buf, sizeof(buf)-1); + uint32_t console_count = get_console_inputs(buf, bufsize); + buf[console_count] = 0; // loop over all mounted interfaces - for(size_t idx=0; idx cdc interfaces - if (count) + if (console_count) { - tuh_cdc_write(idx, buf, count); + tuh_cdc_write(idx, buf, console_count); tuh_cdc_write_flush(idx); } // cdc interfaces -> console if ( tuh_cdc_read_available(idx) ) { - printf((char*) buf); + uint8_t buf_cdc[64+1]; + uint32_t cdc_count = tuh_cdc_read(idx, buf_cdc, sizeof(buf_cdc)-1); + buf_cdc[cdc_count] = 0; + + printf((char*) buf_cdc); } } } diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index f8d996e17..326567689 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -459,7 +459,8 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t } else if ( ep_addr == p_cdc->stream.rx.ep_addr ) { - tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes); + // skip if ZLP + if (xferred_bytes) tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes); // invoke receive callback -- cgit v1.3.1 From edc559cb4d9c0c940387b514f2e66c4a2f3a9c1c Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 Dec 2022 12:29:51 +0700 Subject: fix ci --- src/device/usbd.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index f9a7af21b..f652a878e 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -39,13 +39,13 @@ // USBD Configuration //--------------------------------------------------------------------+ -// Debug level of USBD -#define USBD_DBG 2 - #ifndef CFG_TUD_TASK_QUEUE_SZ #define CFG_TUD_TASK_QUEUE_SZ 16 #endif +// Debug level of USBD +#define USBD_DBG 2 + //--------------------------------------------------------------------+ // Device Data //--------------------------------------------------------------------+ @@ -506,7 +506,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) break; case DCD_EVENT_SETUP_RECEIVED: - TU_LOG_VAR(USBD_DBG, &event.setup_received); + TU_LOG_PTR(USBD_DBG, &event.setup_received); TU_LOG(USBD_DBG, "\r\n"); // Mark as connected after receiving 1st setup packet. -- cgit v1.3.1 From 84a483f5ea7446a5cc1a9fe957379dd1f0a6fd4c Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 Dec 2022 12:47:00 +0700 Subject: add more host cdc API tuh_cdc_write_available(), tuh_cdc_read_flush(), tuh_cdc_rx_cb() callback --- examples/host/cdc_msc_hid/src/cdc_app.c | 31 +++++++++-------- src/class/cdc/cdc_host.c | 34 ++++++++++++++++++ src/class/cdc/cdc_host.h | 62 +++++++++++---------------------- 3 files changed, 72 insertions(+), 55 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c index db652efde..23ea05b2b 100644 --- a/examples/host/cdc_msc_hid/src/cdc_app.c +++ b/examples/host/cdc_msc_hid/src/cdc_app.c @@ -54,8 +54,8 @@ void cdc_app_task(void) uint8_t buf[64+1]; // +1 for extra null character uint32_t const bufsize = sizeof(buf)-1; - uint32_t console_count = get_console_inputs(buf, bufsize); - buf[console_count] = 0; + uint32_t count = get_console_inputs(buf, bufsize); + buf[count] = 0; // loop over all mounted interfaces for(uint8_t idx=0; idx cdc interfaces - if (console_count) + if (count) { - tuh_cdc_write(idx, buf, console_count); + tuh_cdc_write(idx, buf, count); tuh_cdc_write_flush(idx); } - - // cdc interfaces -> console - if ( tuh_cdc_read_available(idx) ) - { - uint8_t buf_cdc[64+1]; - uint32_t cdc_count = tuh_cdc_read(idx, buf_cdc, sizeof(buf_cdc)-1); - buf_cdc[cdc_count] = 0; - - printf((char*) buf_cdc); - } } } } +// Invoked when received new data +void tuh_cdc_rx_cb(uint8_t idx) +{ + uint8_t buf[64+1]; // +1 for extra null character + uint32_t const bufsize = sizeof(buf)-1; + + // forward cdc interfaces -> console + uint32_t count = tuh_cdc_read(idx, buf, bufsize); + buf[count] = 0; + + printf((char*) buf); +} + void tuh_cdc_mount_cb(uint8_t idx) { tuh_cdc_itf_info_t itf_info; diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 326567689..ba2e9e1b7 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -185,6 +185,17 @@ uint32_t tu_edpt_stream_read_available(tu_edpt_stream_t* s) return (uint32_t) tu_fifo_count(&s->ff); } +uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s) +{ + return (uint32_t) tu_fifo_remaining(&s->ff); +} + +void tu_edpt_stream_read_clear(uint8_t daddr, tu_edpt_stream_t* s) +{ + tu_fifo_clear(&s->ff); + tu_edpt_stream_read_xfer(daddr, s); +} + typedef struct { uint8_t daddr; uint8_t bInterfaceNumber; @@ -227,6 +238,12 @@ static inline cdch_interface_t* get_itf(uint8_t idx) return (p_cdc->daddr != 0) ? p_cdc : NULL; } +TU_ATTR_ALWAYS_INLINE +static inline uint8_t itf2idx(cdch_interface_t* p_cdc) +{ + return (uint8_t) (p_cdc - cdch_data); +} + static inline cdch_interface_t* get_itf_by_ep_addr(uint8_t daddr, uint8_t ep_addr) { for(uint8_t i=0; idaddr, &p_cdc->stream.tx); } +uint32_t tuh_cdc_write_available(uint8_t idx) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); + + return tu_edpt_stream_write_available(&p_cdc->stream.tx); +} + uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) { cdch_interface_t* p_cdc = get_itf(idx); @@ -336,6 +361,14 @@ uint32_t tuh_cdc_read_available(uint8_t idx) return tu_edpt_stream_read_available(&p_cdc->stream.rx); } +void tuh_cdc_read_flush (uint8_t idx) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc, ); + + tu_edpt_stream_read_clear(p_cdc->daddr, &p_cdc->stream.rx); +} + //--------------------------------------------------------------------+ // Control Endpoint API //--------------------------------------------------------------------+ @@ -463,6 +496,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t if (xferred_bytes) tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes); // invoke receive callback + if (tuh_cdc_rx_cb) tuh_cdc_rx_cb(itf2idx(p_cdc)); // prepare for next transfer if needed tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx); diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 54e082e7d..dd8ae80ce 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -97,18 +97,32 @@ TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_connected(uint8_t idx) return tuh_cdc_get_dtr(idx); } +//--------------------------------------------------------------------+ +// Write API +//--------------------------------------------------------------------+ + +// Get the number of bytes available for writing +uint32_t tuh_cdc_write_available(uint8_t idx); + // Write to cdc interface uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize); // Force sending data if possible, return number of forced bytes uint32_t tuh_cdc_write_flush(uint8_t idx); -// Read from cdc interface -uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize); +//--------------------------------------------------------------------+ +// Read API +//--------------------------------------------------------------------+ // Get the number of bytes available for reading uint32_t tuh_cdc_read_available(uint8_t idx); +// Read from cdc interface +uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize); + +// Clear the received FIFO +void tuh_cdc_read_flush (uint8_t idx); + //--------------------------------------------------------------------+ // Control Endpoint (Request) API //--------------------------------------------------------------------+ @@ -132,47 +146,13 @@ static inline bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, ui // Invoked when a device with CDC interface is mounted // idx is index of cdc interface in the internal pool. -TU_ATTR_WEAK void tuh_cdc_mount_cb(uint8_t idx); +TU_ATTR_WEAK extern void tuh_cdc_mount_cb(uint8_t idx); // Invoked when a device with CDC interface is unmounted -TU_ATTR_WEAK void tuh_cdc_umount_cb(uint8_t idx); - -/** \brief Check if the interface is currently busy or not - * \param[in] dev_addr device address - * \param[in] pipeid value from \ref cdc_pipeid_t to indicate target pipe. - * \retval true if the interface is busy, meaning the stack is still transferring/waiting data from/to device - * \retval false if the interface is not busy, meaning the stack successfully transferred data from/to device - * \note This function is used to check if previous transfer is complete (success or error), so that the next transfer - * can be scheduled. User needs to make sure the corresponding interface is mounted - * (by \ref tuh_cdc_serial_is_mounted) before calling this function. - */ -// bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid); - -/** \brief Perform USB OUT transfer to device - * \param[in] dev_addr device address - * \param[in] p_data Buffer containing data. Must be accessible by USB controller (see \ref CFG_TUSB_MEM_SECTION) - * \param[in] length Number of bytes to be transferred via USB bus - * \retval TUSB_ERROR_NONE on success - * \retval TUSB_ERROR_INTERFACE_IS_BUSY if the interface is already transferring data with device - * \retval TUSB_ERROR_DEVICE_NOT_READY if device is not yet configured (by SET CONFIGURED request) - * \retval TUSB_ERROR_INVALID_PARA if input parameters are not correct - * \note This function is non-blocking and returns immediately. The result of USB transfer will be reported by the - * interface's callback function. \a p_data must be declared with \ref CFG_TUSB_MEM_SECTION. - */ -// bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify); - -/** \brief Perform USB IN transfer to get data from device - * \param[in] dev_addr device address - * \param[in] p_buffer Buffer containing received data. Must be accessible by USB controller (see \ref CFG_TUSB_MEM_SECTION) - * \param[in] length Number of bytes to be transferred via USB bus - * \retval TUSB_ERROR_NONE on success - * \retval TUSB_ERROR_INTERFACE_IS_BUSY if the interface is already transferring data with device - * \retval TUSB_ERROR_DEVICE_NOT_READY if device is not yet configured (by SET CONFIGURED request) - * \retval TUSB_ERROR_INVALID_PARA if input parameters are not correct - * \note This function is non-blocking and returns immediately. The result of USB transfer will be reported by the - * interface's callback function. \a p_data must be declared with \ref CFG_TUSB_MEM_SECTION. - */ -// bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify); +TU_ATTR_WEAK extern void tuh_cdc_umount_cb(uint8_t idx); + +// Invoked when received new data +TU_ATTR_WEAK extern void tuh_cdc_rx_cb(uint8_t idx); //--------------------------------------------------------------------+ // CDC APPLICATION CALLBACKS -- cgit v1.3.1 From cd9008e5a9c8da81d9736f7e0bf72c5ba409a7f1 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 Dec 2022 13:05:45 +0700 Subject: add tuh_cdc_tx_complete_cb() callback --- examples/host/cdc_msc_hid/src/cdc_app.c | 4 ++-- src/class/cdc/cdc_host.c | 20 +++++++++----------- src/class/cdc/cdc_host.h | 3 +++ 3 files changed, 14 insertions(+), 13 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c index 23ea05b2b..dd3196146 100644 --- a/examples/host/cdc_msc_hid/src/cdc_app.c +++ b/examples/host/cdc_msc_hid/src/cdc_app.c @@ -87,7 +87,7 @@ void tuh_cdc_rx_cb(uint8_t idx) void tuh_cdc_mount_cb(uint8_t idx) { - tuh_cdc_itf_info_t itf_info; + tuh_cdc_itf_info_t itf_info = { 0 }; tuh_cdc_itf_get_info(idx, &itf_info); printf("CDC Interface is mounted: device address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber); @@ -95,7 +95,7 @@ void tuh_cdc_mount_cb(uint8_t idx) void tuh_cdc_umount_cb(uint8_t idx) { - tuh_cdc_itf_info_t itf_info; + tuh_cdc_itf_info_t itf_info = { 0 }; tuh_cdc_itf_get_info(idx, &itf_info); printf("CDC Interface is unmounted: device address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber); diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index ba2e9e1b7..ce0efe6e3 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -238,13 +238,7 @@ static inline cdch_interface_t* get_itf(uint8_t idx) return (p_cdc->daddr != 0) ? p_cdc : NULL; } -TU_ATTR_ALWAYS_INLINE -static inline uint8_t itf2idx(cdch_interface_t* p_cdc) -{ - return (uint8_t) (p_cdc - cdch_data); -} - -static inline cdch_interface_t* get_itf_by_ep_addr(uint8_t daddr, uint8_t ep_addr) +static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr) { for(uint8_t i=0; idaddr == daddr) && (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr)) { - return p_cdc; + return i; } } - return NULL; + return TUSB_INDEX_INVALID; } @@ -478,11 +472,15 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t // TODO handle stall response, retry failed transfer ... TU_ASSERT(event == XFER_RESULT_SUCCESS); - cdch_interface_t * p_cdc = get_itf_by_ep_addr(daddr, ep_addr); + uint8_t const idx = get_idx_by_ep_addr(daddr, ep_addr); + cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc); if ( ep_addr == p_cdc->stream.tx.ep_addr ) { + // invoke tx complete callback to possibly refill tx fifo + if (tuh_cdc_tx_complete_cb) tuh_cdc_tx_complete_cb(idx); + if ( 0 == tu_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx) ) { // If there is no data left, a ZLP should be sent if needed @@ -496,7 +494,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t if (xferred_bytes) tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes); // invoke receive callback - if (tuh_cdc_rx_cb) tuh_cdc_rx_cb(itf2idx(p_cdc)); + if (tuh_cdc_rx_cb) tuh_cdc_rx_cb(idx); // prepare for next transfer if needed tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx); diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index dd8ae80ce..476431cc5 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -154,6 +154,9 @@ TU_ATTR_WEAK extern void tuh_cdc_umount_cb(uint8_t idx); // Invoked when received new data TU_ATTR_WEAK extern void tuh_cdc_rx_cb(uint8_t idx); +// Invoked when a TX is complete and therefore space becomes available in TX buffer +TU_ATTR_WEAK extern void tuh_cdc_tx_complete_cb(uint8_t idx); + //--------------------------------------------------------------------+ // CDC APPLICATION CALLBACKS //--------------------------------------------------------------------+ -- cgit v1.3.1 From 9e8ea44925e80abd7189ed7a673762527ee3adfd Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 Dec 2022 17:46:11 +0700 Subject: add tuh_cdc_write_clear, rename read_flush() to read_clear() --- src/class/cdc/cdc_host.c | 24 +++++++++++++++++++----- src/class/cdc/cdc_host.h | 5 ++++- 2 files changed, 23 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index ce0efe6e3..2f3406378 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -190,10 +190,16 @@ uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s) return (uint32_t) tu_fifo_remaining(&s->ff); } -void tu_edpt_stream_read_clear(uint8_t daddr, tu_edpt_stream_t* s) +bool tu_edpt_stream_read_clear(uint8_t daddr, tu_edpt_stream_t* s) { - tu_fifo_clear(&s->ff); + bool ret = tu_fifo_clear(&s->ff); tu_edpt_stream_read_xfer(daddr, s); + return ret; +} + +bool tu_edpt_stream_write_clear(tu_edpt_stream_t* s) +{ + return tu_fifo_clear(&s->ff); } typedef struct { @@ -331,6 +337,14 @@ uint32_t tuh_cdc_write_flush(uint8_t idx) return tu_edpt_stream_write_xfer(p_cdc->daddr, &p_cdc->stream.tx); } +bool tuh_cdc_write_clear(uint8_t idx) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); + + return tu_edpt_stream_write_clear(&p_cdc->stream.tx); +} + uint32_t tuh_cdc_write_available(uint8_t idx) { cdch_interface_t* p_cdc = get_itf(idx); @@ -355,12 +369,12 @@ uint32_t tuh_cdc_read_available(uint8_t idx) return tu_edpt_stream_read_available(&p_cdc->stream.rx); } -void tuh_cdc_read_flush (uint8_t idx) +bool tuh_cdc_read_clear (uint8_t idx) { cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc, ); + TU_VERIFY(p_cdc); - tu_edpt_stream_read_clear(p_cdc->daddr, &p_cdc->stream.rx); + return tu_edpt_stream_read_clear(p_cdc->daddr, &p_cdc->stream.rx); } //--------------------------------------------------------------------+ diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 476431cc5..02ae69111 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -110,6 +110,9 @@ uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize); // Force sending data if possible, return number of forced bytes uint32_t tuh_cdc_write_flush(uint8_t idx); +// Clear the transmit FIFO +bool tuh_cdc_write_clear(uint8_t idx); + //--------------------------------------------------------------------+ // Read API //--------------------------------------------------------------------+ @@ -121,7 +124,7 @@ uint32_t tuh_cdc_read_available(uint8_t idx); uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize); // Clear the received FIFO -void tuh_cdc_read_flush (uint8_t idx); +bool tuh_cdc_read_clear (uint8_t idx); //--------------------------------------------------------------------+ // Control Endpoint (Request) API -- cgit v1.3.1 From 8323e4b79a2052aee814ca8811e841bceb6a7a7d Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 22 Dec 2022 00:34:35 +0700 Subject: moving edpt_stream API into common tusb.c --- src/class/cdc/cdc_host.c | 179 ++++++++++---------------------------------- src/common/tusb_private.h | 92 ++++++++++++++++++++++- src/host/usbh.c | 1 - src/host/usbh_classdriver.h | 1 + src/tusb.c | 112 +++++++++++++++++++++++++-- 5 files changed, 239 insertions(+), 146 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 2f3406378..54d81dc0d 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -42,56 +42,23 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -typedef struct { - tu_fifo_t ff; - - // mutex: read if ep rx, write if e tx - OSAL_MUTEX_DEF(ff_mutex); - - // TODO xfer_fifo can skip this buffer - uint8_t* ep_buf; - uint16_t ep_bufsize; - uint8_t ep_addr; -}tu_edpt_stream_t; - -bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool use_wr_mutex, bool overwritable, - void* ff_buf, uint16_t ff_bufsize, - uint8_t* ep_buf, uint16_t ep_bufsize) -{ - osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutex); - (void) new_mutex; - (void) use_wr_mutex; - - tu_fifo_config(&s->ff, ff_buf, ff_bufsize, 1, overwritable); - tu_fifo_config_mutex(&s->ff, use_wr_mutex ? new_mutex : NULL, use_wr_mutex ? NULL : new_mutex); - - s->ep_buf = ep_buf; - s->ep_bufsize = ep_bufsize; - - return true; -} - -bool tu_edpt_stream_clear(tu_edpt_stream_t* s) -{ - return tu_fifo_clear(&s->ff); -} -bool tu_edpt_stream_write_zlp_if_needed(uint8_t daddr, tu_edpt_stream_t* s, uint32_t last_xferred_bytes) +bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes) { - uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS; + uint16_t const bulk_packet_size = (s->ep_speed == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS; // ZLP condition: no pending data, last transferred bytes is multiple of packet size TU_VERIFY( !tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (bulk_packet_size-1))) ); - if ( usbh_edpt_claim(daddr, s->ep_addr) ) + if ( usbh_edpt_claim(s->daddr, s->ep_addr) ) { - TU_ASSERT( usbh_edpt_xfer(daddr, s->ep_addr, NULL, 0) ); + TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, NULL, 0) ); } return true; } -uint32_t tu_edpt_stream_write_xfer(uint8_t daddr, tu_edpt_stream_t* s) +uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s) { // skip if no data TU_VERIFY( tu_fifo_count(&s->ff), 0 ); @@ -99,7 +66,7 @@ uint32_t tu_edpt_stream_write_xfer(uint8_t daddr, tu_edpt_stream_t* s) // Claim the endpoint // uint8_t const rhport = 0; // TU_VERIFY( usbd_edpt_claim(rhport, p_cdc->ep_in), 0 ); - TU_VERIFY( usbh_edpt_claim(daddr, s->ep_addr) ); + TU_VERIFY( usbh_edpt_claim(s->daddr, s->ep_addr) ); // Pull data from FIFO -> EP buf uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize); @@ -107,7 +74,7 @@ uint32_t tu_edpt_stream_write_xfer(uint8_t daddr, tu_edpt_stream_t* s) if ( count ) { //TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 ); - TU_ASSERT( usbh_edpt_xfer(daddr, s->ep_addr, s->ep_buf, count), 0 ); + TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, s->ep_buf, count), 0 ); return count; }else { @@ -115,93 +82,28 @@ uint32_t tu_edpt_stream_write_xfer(uint8_t daddr, tu_edpt_stream_t* s) // Note: data is dropped if terminal is not connected //usbd_edpt_release(rhport, p_cdc->ep_in); - usbh_edpt_release(daddr, s->ep_addr); + usbh_edpt_release(s->daddr, s->ep_addr); return 0; } } -uint32_t tu_edpt_stream_write(uint8_t daddr, tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize) -{ - uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize); - - // flush if queue more than packet size - uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS; - if ( (tu_fifo_count(&s->ff) >= bulk_packet_size) - /* || ((CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE) && tu_fifo_full(&p_cdc->tx_ff)) */ ) - { - tu_edpt_stream_write_xfer(daddr, s); - } - - return ret; -} - -void tu_edpt_stream_read_xfer_complete(tu_edpt_stream_t* s, uint32_t xferred_bytes) -{ - tu_fifo_write_n(&s->ff, s->ep_buf, (uint16_t) xferred_bytes); -} - -uint32_t tu_edpt_stream_read_xfer(uint8_t daddr, tu_edpt_stream_t* s) +uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize) { - uint16_t available = tu_fifo_remaining(&s->ff); + TU_VERIFY(bufsize); // TODO support ZLP - // Prepare for incoming data but only allow what we can store in the ring buffer. - // TODO Actually we can still carry out the transfer, keeping count of received bytes - // and slowly move it to the FIFO when read(). - // This pre-check reduces endpoint claiming - uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS; - TU_VERIFY(available >= bulk_packet_size); - - // claim endpoint - TU_VERIFY(usbh_edpt_claim(daddr, s->ep_addr), 0); - - // fifo can be changed before endpoint is claimed - available = tu_fifo_remaining(&s->ff); - - if ( available >= bulk_packet_size ) - { - // multiple of packet size limit by ep bufsize - uint16_t count = (uint16_t) (available & (bulk_packet_size -1)); - count = tu_min16(count, s->ep_bufsize); + uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize); - TU_ASSERT( usbh_edpt_xfer(daddr, s->ep_addr, s->ep_buf, count), 0 ); - return count; - }else + // flush if fifo has more than packet size or + // in rare case: fifo depth is configured too small (which never reach packet size) + uint16_t const bulk_packet_size = (s->ep_speed == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS; + if ( (tu_fifo_count(&s->ff) >= bulk_packet_size) || ( tu_fifo_depth(&s->ff) < bulk_packet_size) ) { - // Release endpoint since we don't make any transfer - usbh_edpt_release(daddr, s->ep_addr); - return 0; + tu_edpt_stream_write_xfer(s); } -} - -uint32_t tu_edpt_stream_read(uint8_t daddr, tu_edpt_stream_t* s, void* buffer, uint32_t bufsize) -{ - uint32_t num_read = tu_fifo_read_n(&s->ff, buffer, (uint16_t) bufsize); - tu_edpt_stream_read_xfer(daddr, s); - return num_read; -} - -uint32_t tu_edpt_stream_read_available(tu_edpt_stream_t* s) -{ - return (uint32_t) tu_fifo_count(&s->ff); -} - -uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s) -{ - return (uint32_t) tu_fifo_remaining(&s->ff); -} -bool tu_edpt_stream_read_clear(uint8_t daddr, tu_edpt_stream_t* s) -{ - bool ret = tu_fifo_clear(&s->ff); - tu_edpt_stream_read_xfer(daddr, s); return ret; } -bool tu_edpt_stream_write_clear(tu_edpt_stream_t* s) -{ - return tu_fifo_clear(&s->ff); -} - typedef struct { uint8_t daddr; uint8_t bInterfaceNumber; @@ -326,7 +228,7 @@ uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize) cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return tu_edpt_stream_write(p_cdc->daddr, &p_cdc->stream.tx, buffer, bufsize); + return tu_edpt_stream_write(&p_cdc->stream.tx, buffer, bufsize); } uint32_t tuh_cdc_write_flush(uint8_t idx) @@ -334,7 +236,7 @@ uint32_t tuh_cdc_write_flush(uint8_t idx) cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return tu_edpt_stream_write_xfer(p_cdc->daddr, &p_cdc->stream.tx); + return tu_edpt_stream_write_xfer(&p_cdc->stream.tx); } bool tuh_cdc_write_clear(uint8_t idx) @@ -342,7 +244,7 @@ bool tuh_cdc_write_clear(uint8_t idx) cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return tu_edpt_stream_write_clear(&p_cdc->stream.tx); + return tu_edpt_stream_clear(&p_cdc->stream.tx); } uint32_t tuh_cdc_write_available(uint8_t idx) @@ -358,7 +260,7 @@ uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return tu_edpt_stream_read(p_cdc->daddr, &p_cdc->stream.rx, buffer, bufsize); + return tu_edpt_stream_read(&p_cdc->stream.rx, buffer, bufsize); } uint32_t tuh_cdc_read_available(uint8_t idx) @@ -374,7 +276,9 @@ bool tuh_cdc_read_clear (uint8_t idx) cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return tu_edpt_stream_read_clear(p_cdc->daddr, &p_cdc->stream.rx); + bool ret = tu_edpt_stream_clear(&p_cdc->stream.rx); + tu_edpt_stream_read_xfer(&p_cdc->stream.rx); + return ret; } //--------------------------------------------------------------------+ @@ -452,13 +356,13 @@ void cdch_init(void) { cdch_interface_t* p_cdc = &cdch_data[i]; - tu_edpt_stream_init(&p_cdc->stream.tx, true, false, - p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE, - p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE); + tu_edpt_stream_init(&p_cdc->stream.tx, true, true, false, + p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE, + p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE); - tu_edpt_stream_init(&p_cdc->stream.rx, false, false, - p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE, - p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE); + tu_edpt_stream_init(&p_cdc->stream.rx, true, false, false, + p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE, + p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE); } } @@ -475,8 +379,6 @@ void cdch_close(uint8_t daddr) //tu_memclr(p_cdc, sizeof(cdch_interface_t)); p_cdc->daddr = 0; p_cdc->bInterfaceNumber = 0; - tu_edpt_stream_clear(&p_cdc->stream.tx); - tu_edpt_stream_clear(&p_cdc->stream.rx); } } } @@ -495,23 +397,22 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t // invoke tx complete callback to possibly refill tx fifo if (tuh_cdc_tx_complete_cb) tuh_cdc_tx_complete_cb(idx); - if ( 0 == tu_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx) ) + if ( 0 == tu_edpt_stream_write_xfer(&p_cdc->stream.tx) ) { // If there is no data left, a ZLP should be sent if needed // xferred_bytes is multiple of EP Packet size and not zero - tu_edpt_stream_write_zlp_if_needed(daddr, &p_cdc->stream.tx, xferred_bytes); + tu_edpt_stream_write_zlp_if_needed(&p_cdc->stream.tx, xferred_bytes); } } else if ( ep_addr == p_cdc->stream.rx.ep_addr ) { - // skip if ZLP - if (xferred_bytes) tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes); + tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes); // invoke receive callback if (tuh_cdc_rx_cb) tuh_cdc_rx_cb(idx); // prepare for next transfer if needed - tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx); + tu_edpt_stream_read_xfer(&p_cdc->stream.rx); }else if ( ep_addr == p_cdc->ep_notif ) { // TODO handle notification endpoint @@ -527,7 +428,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t // Enumeration //--------------------------------------------------------------------+ -bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) +bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { (void) rhport; @@ -542,7 +443,7 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it cdch_interface_t * p_cdc = find_new_itf(); TU_VERIFY(p_cdc); - p_cdc->daddr = dev_addr; + p_cdc->daddr = daddr; p_cdc->bInterfaceNumber = itf_desc->bInterfaceNumber; p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass; p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol; @@ -569,7 +470,7 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)); tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc; - TU_ASSERT( tuh_edpt_open(dev_addr, desc_ep) ); + TU_ASSERT( tuh_edpt_open(daddr, desc_ep) ); p_cdc->ep_notif = desc_ep->bEndpointAddress; p_desc = tu_desc_next(p_desc); @@ -589,14 +490,14 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_BULK == desc_ep->bmAttributes.xfer); - TU_ASSERT(tuh_edpt_open(dev_addr, desc_ep)); + TU_ASSERT(tuh_edpt_open(daddr, desc_ep)); if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN ) { - p_cdc->stream.rx.ep_addr = desc_ep->bEndpointAddress; + tu_edpt_stream_open(&p_cdc->stream.rx, daddr, desc_ep); }else { - p_cdc->stream.tx.ep_addr = desc_ep->bEndpointAddress; + tu_edpt_stream_open(&p_cdc->stream.tx, daddr, desc_ep); } p_desc = tu_desc_next(p_desc); @@ -616,7 +517,7 @@ static void config_cdc_complete(uint8_t daddr, uint8_t itf_num) // Prepare for incoming data cdch_interface_t* p_cdc = get_itf(idx); - tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx); + tu_edpt_stream_read_xfer(&p_cdc->stream.rx); } // notify usbh that driver enumeration is complete diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h index b34506f65..01078eed3 100644 --- a/src/common/tusb_private.h +++ b/src/common/tusb_private.h @@ -28,6 +28,8 @@ #ifndef _TUSB_PRIVATE_H_ #define _TUSB_PRIVATE_H_ +// Internal Helper used by Host and Device Stack + #ifdef __cplusplus extern "C" { #endif @@ -39,8 +41,31 @@ typedef struct TU_ATTR_PACKED volatile uint8_t claimed : 1; }tu_edpt_state_t; +typedef struct { + bool is_host; // host or device most + union { + uint8_t daddr; + uint8_t rhport; + uint8_t hwid; + }; + uint8_t ep_addr; + uint8_t ep_speed; + + uint16_t ep_packetsize; + uint16_t ep_bufsize; + + // TODO xfer_fifo can skip this buffer + uint8_t* ep_buf; + + tu_fifo_t ff; + + // mutex: read if ep rx, write if e tx + OSAL_MUTEX_DEF(ff_mutex); + +}tu_edpt_stream_t; + //--------------------------------------------------------------------+ -// Internal Helper used by Host and Device Stack +// Endpoint //--------------------------------------------------------------------+ // Check if endpoint descriptor is valid per USB specs @@ -58,6 +83,71 @@ bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex); // Release an endpoint with provided mutex bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex); +//--------------------------------------------------------------------+ +// Endpoint Stream +//--------------------------------------------------------------------+ + +// Init an stream, should only called once +bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable, + void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize); + +// Open an stream for an endpoint +// hwid is either device address (host mode) or rhport (device mode) +TU_ATTR_ALWAYS_INLINE static inline +void tu_edpt_stream_open(tu_edpt_stream_t* s, uint8_t hwid, tusb_desc_endpoint_t const *desc_ep) +{ + tu_fifo_clear(&s->ff); + s->hwid = hwid; + s->ep_addr = desc_ep->bEndpointAddress; + s->ep_packetsize = tu_edpt_packet_size(desc_ep); +} + +// Clear fifo +TU_ATTR_ALWAYS_INLINE static inline +bool tu_edpt_stream_clear(tu_edpt_stream_t* s) +{ + return tu_fifo_clear(&s->ff); +} + +//------------- Write -------------// + +// Write to stream +uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize); + +// Start an usb transfer if endpoint is not busy +uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s); + +// Get the number of bytes available for writing +TU_ATTR_ALWAYS_INLINE static inline +uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s) +{ + return (uint32_t) tu_fifo_remaining(&s->ff); +} + + +//------------- Read -------------// + +// Read from stream +uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize); + +// Start an usb transfer if endpoint is not busy +uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s); + +// Must be called in the transfer complete callback +TU_ATTR_ALWAYS_INLINE static inline +void tu_edpt_stream_read_xfer_complete(tu_edpt_stream_t* s, uint32_t xferred_bytes) +{ + tu_fifo_write_n(&s->ff, s->ep_buf, (uint16_t) xferred_bytes); +} + +// Get the number of bytes available for reading +TU_ATTR_ALWAYS_INLINE static inline +uint32_t tu_edpt_stream_read_available(tu_edpt_stream_t* s) +{ + return (uint32_t) tu_fifo_count(&s->ff); +} + + #ifdef __cplusplus } #endif diff --git a/src/host/usbh.c b/src/host/usbh.c index 36fc5fded..f0ca7be2e 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -30,7 +30,6 @@ #include "host/hcd.h" #include "tusb.h" -#include "common/tusb_private.h" #include "host/usbh_classdriver.h" #include "hub.h" diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h index 7f72560c3..be9811641 100644 --- a/src/host/usbh_classdriver.h +++ b/src/host/usbh_classdriver.h @@ -29,6 +29,7 @@ #include "osal/osal.h" #include "common/tusb_fifo.h" +#include "common/tusb_private.h" #ifdef __cplusplus extern "C" { diff --git a/src/tusb.c b/src/tusb.c index f4380f89c..05e0d4c1f 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -31,11 +31,18 @@ #include "tusb.h" #include "common/tusb_private.h" -// TODO clean up #if CFG_TUD_ENABLED #include "device/usbd_pvt.h" #endif +#if CFG_TUH_ENABLED +#include "host/usbh_classdriver.h" +#endif + +//--------------------------------------------------------------------+ +// Public API +//--------------------------------------------------------------------+ + bool tusb_init(void) { #if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT) @@ -67,7 +74,7 @@ bool tusb_inited(void) } //--------------------------------------------------------------------+ -// Internal Helper for both Host and Device stack +// Endpoint Helper for both Host and Device stack //--------------------------------------------------------------------+ bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex) @@ -196,9 +203,104 @@ uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, return len; } -/*------------------------------------------------------------------*/ -/* Debug - *------------------------------------------------------------------*/ +//--------------------------------------------------------------------+ +// Endpoint Stream Helper for both Host and Device stack +//--------------------------------------------------------------------+ + +bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable, + void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize) +{ + osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutex); + (void) new_mutex; + (void) is_tx; + + s->is_host = is_host; + tu_fifo_config(&s->ff, ff_buf, ff_bufsize, 1, overwritable); + tu_fifo_config_mutex(&s->ff, is_tx ? new_mutex : NULL, is_tx ? NULL : new_mutex); + + s->ep_buf = ep_buf; + s->ep_bufsize = ep_bufsize; + + return true; +} + +//------------- Stream Write -------------// + +//------------- Stream Read -------------// + +uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s) +{ + uint16_t available = tu_fifo_remaining(&s->ff); + + // Prepare for incoming data but only allow what we can store in the ring buffer. + // TODO Actually we can still carry out the transfer, keeping count of received bytes + // and slowly move it to the FIFO when read(). + // This pre-check reduces endpoint claiming + TU_VERIFY(available >= s->ep_packetsize); + + // claim endpoint + if (s->is_host) + { + #if CFG_TUH_ENABLED + TU_VERIFY(usbh_edpt_claim(s->daddr, s->ep_addr), 0); + #endif + }else + { + #if CFG_TUD_ENABLED + TU_VERIFY(usbd_edpt_claim(s->rhport, s->ep_addr), 0); + #endif + } + + // get available again since fifo can be changed before endpoint is claimed + available = tu_fifo_remaining(&s->ff); + + if ( available >= s->ep_packetsize ) + { + // multiple of packet size limit by ep bufsize + uint16_t count = (uint16_t) (available & (s->ep_packetsize -1)); + count = tu_min16(count, s->ep_bufsize); + + if (s->is_host) + { + #if CFG_TUH_ENABLED + TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, s->ep_buf, count), 0 ); + #endif + }else + { + #if CFG_TUD_ENABLED + TU_ASSERT( usbd_edpt_xfer(s->rhport, s->ep_addr, s->ep_buf, count), 0 ); + #endif + } + return count; + }else + { + // Release endpoint since we don't make any transfer + if (s->is_host) + { + #if CFG_TUH_ENABLED + usbh_edpt_release(s->daddr, s->ep_addr); + #endif + }else + { + #if CFG_TUD_ENABLED + usbd_edpt_release(s->rhport, s->ep_addr); + #endif + } + + return 0; + } +} + +uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize) +{ + uint32_t num_read = tu_fifo_read_n(&s->ff, buffer, (uint16_t) bufsize); + tu_edpt_stream_read_xfer(s); + return num_read; +} + +//--------------------------------------------------------------------+ +// Debug +//--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG #include -- cgit v1.3.1 From e3c9d9450009f757b9ddf5f94a00f14e7cfb0471 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 22 Dec 2022 11:16:39 +0700 Subject: fix stream read count computation --- src/class/cdc/cdc_host.c | 63 +------------------------------ src/common/tusb_private.h | 21 +++++++++-- src/tusb.c | 96 ++++++++++++++++++++++++++++++++++++++++------- 3 files changed, 101 insertions(+), 79 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 54d81dc0d..469725e72 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -43,67 +43,6 @@ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes) -{ - uint16_t const bulk_packet_size = (s->ep_speed == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS; - - // ZLP condition: no pending data, last transferred bytes is multiple of packet size - TU_VERIFY( !tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (bulk_packet_size-1))) ); - - if ( usbh_edpt_claim(s->daddr, s->ep_addr) ) - { - TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, NULL, 0) ); - } - - return true; -} - -uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s) -{ - // skip if no data - TU_VERIFY( tu_fifo_count(&s->ff), 0 ); - - // Claim the endpoint - // uint8_t const rhport = 0; - // TU_VERIFY( usbd_edpt_claim(rhport, p_cdc->ep_in), 0 ); - TU_VERIFY( usbh_edpt_claim(s->daddr, s->ep_addr) ); - - // Pull data from FIFO -> EP buf - uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize); - - if ( count ) - { - //TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 ); - TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, s->ep_buf, count), 0 ); - return count; - }else - { - // Release endpoint since we don't make any transfer - // Note: data is dropped if terminal is not connected - //usbd_edpt_release(rhport, p_cdc->ep_in); - - usbh_edpt_release(s->daddr, s->ep_addr); - return 0; - } -} - -uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize) -{ - TU_VERIFY(bufsize); // TODO support ZLP - - uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize); - - // flush if fifo has more than packet size or - // in rare case: fifo depth is configured too small (which never reach packet size) - uint16_t const bulk_packet_size = (s->ep_speed == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS; - if ( (tu_fifo_count(&s->ff) >= bulk_packet_size) || ( tu_fifo_depth(&s->ff) < bulk_packet_size) ) - { - tu_edpt_stream_write_xfer(s); - } - - return ret; -} - typedef struct { uint8_t daddr; uint8_t bInterfaceNumber; @@ -379,6 +318,8 @@ void cdch_close(uint8_t daddr) //tu_memclr(p_cdc, sizeof(cdch_interface_t)); p_cdc->daddr = 0; p_cdc->bInterfaceNumber = 0; + tu_edpt_stream_close(&p_cdc->stream.tx); + tu_edpt_stream_close(&p_cdc->stream.rx); } } } diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h index 01078eed3..d0c7a84fb 100644 --- a/src/common/tusb_private.h +++ b/src/common/tusb_private.h @@ -87,7 +87,7 @@ bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex); // Endpoint Stream //--------------------------------------------------------------------+ -// Init an stream, should only called once +// Init an stream, should only be called once bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable, void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize); @@ -102,6 +102,13 @@ void tu_edpt_stream_open(tu_edpt_stream_t* s, uint8_t hwid, tusb_desc_endpoint_t s->ep_packetsize = tu_edpt_packet_size(desc_ep); } +TU_ATTR_ALWAYS_INLINE static inline +void tu_edpt_stream_close(tu_edpt_stream_t* s) +{ + s->hwid = 0; + s->ep_addr = 0; +} + // Clear fifo TU_ATTR_ALWAYS_INLINE static inline bool tu_edpt_stream_clear(tu_edpt_stream_t* s) @@ -109,7 +116,9 @@ bool tu_edpt_stream_clear(tu_edpt_stream_t* s) return tu_fifo_clear(&s->ff); } -//------------- Write -------------// +//--------------------------------------------------------------------+ +// Stream Write +//--------------------------------------------------------------------+ // Write to stream uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize); @@ -117,6 +126,9 @@ uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t // Start an usb transfer if endpoint is not busy uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s); +// Start an zero-length packet if needed +bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes); + // Get the number of bytes available for writing TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s) @@ -124,8 +136,9 @@ uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s) return (uint32_t) tu_fifo_remaining(&s->ff); } - -//------------- Read -------------// +//--------------------------------------------------------------------+ +// Stream Read +//--------------------------------------------------------------------+ // Read from stream uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize); diff --git a/src/tusb.c b/src/tusb.c index 05e0d4c1f..0d0e84a49 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -224,9 +224,86 @@ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool ove return true; } -//------------- Stream Write -------------// +TU_ATTR_ALWAYS_INLINE static inline +bool stream_claim(tu_edpt_stream_t* s) +{ + if (s->is_host) + { + #if CFG_TUH_ENABLED + return usbh_edpt_claim(s->daddr, s->ep_addr); + #endif + }else + { + #if CFG_TUD_ENABLED + return usbd_edpt_claim(s->rhport, s->ep_addr); + #endif + } + + return false; +} -//------------- Stream Read -------------// + +//--------------------------------------------------------------------+ +// Stream Write +//--------------------------------------------------------------------+ + +bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes) +{ + // ZLP condition: no pending data, last transferred bytes is multiple of packet size + TU_VERIFY( !tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (s->ep_packetsize-1))) ); + + TU_VERIFY( stream_claim(s) ); + TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, NULL, 0) ); + + return true; +} + +uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s) +{ + // skip if no data + TU_VERIFY( tu_fifo_count(&s->ff), 0 ); + + // Claim the endpoint + TU_VERIFY( stream_claim(s), 0 ); + + // Pull data from FIFO -> EP buf + uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize); + + if ( count ) + { + //TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 ); + TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, s->ep_buf, count), 0 ); + return count; + }else + { + // Release endpoint since we don't make any transfer + // Note: data is dropped if terminal is not connected + //usbd_edpt_release(rhport, p_cdc->ep_in); + + usbh_edpt_release(s->daddr, s->ep_addr); + return 0; + } +} + +uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize) +{ + TU_VERIFY(bufsize); // TODO support ZLP + + uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize); + + // flush if fifo has more than packet size or + // in rare case: fifo depth is configured too small (which never reach packet size) + if ( (tu_fifo_count(&s->ff) >= s->ep_packetsize) || (tu_fifo_depth(&s->ff) < s->ep_packetsize) ) + { + tu_edpt_stream_write_xfer(s); + } + + return ret; +} + +//--------------------------------------------------------------------+ +// Stream Read +//--------------------------------------------------------------------+ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s) { @@ -239,17 +316,7 @@ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s) TU_VERIFY(available >= s->ep_packetsize); // claim endpoint - if (s->is_host) - { - #if CFG_TUH_ENABLED - TU_VERIFY(usbh_edpt_claim(s->daddr, s->ep_addr), 0); - #endif - }else - { - #if CFG_TUD_ENABLED - TU_VERIFY(usbd_edpt_claim(s->rhport, s->ep_addr), 0); - #endif - } + TU_VERIFY(stream_claim(s), 0); // get available again since fifo can be changed before endpoint is claimed available = tu_fifo_remaining(&s->ff); @@ -257,7 +324,7 @@ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s) if ( available >= s->ep_packetsize ) { // multiple of packet size limit by ep bufsize - uint16_t count = (uint16_t) (available & (s->ep_packetsize -1)); + uint16_t count = (uint16_t) (available & ~(s->ep_packetsize -1)); count = tu_min16(count, s->ep_bufsize); if (s->is_host) @@ -301,6 +368,7 @@ uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize //--------------------------------------------------------------------+ // Debug //--------------------------------------------------------------------+ + #if CFG_TUSB_DEBUG #include -- cgit v1.3.1 From 2d536123c8ff8dd233656f0a9d7c16aff606302d Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 22 Dec 2022 11:31:37 +0700 Subject: finish moving edpt stream to tusb.c --- src/class/cdc/cdc_host.c | 4 +-- src/tusb.c | 69 ++++++++++++++++++++++++++++-------------------- 2 files changed, 43 insertions(+), 30 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 469725e72..de1466cb1 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -340,8 +340,8 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t if ( 0 == tu_edpt_stream_write_xfer(&p_cdc->stream.tx) ) { - // If there is no data left, a ZLP should be sent if needed - // xferred_bytes is multiple of EP Packet size and not zero + // If there is no data left, a ZLP should be sent if: + // - xferred_bytes is multiple of EP Packet size and not zero tu_edpt_stream_write_zlp_if_needed(&p_cdc->stream.tx, xferred_bytes); } } diff --git a/src/tusb.c b/src/tusb.c index 0d0e84a49..8f64f4acf 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -242,6 +242,41 @@ bool stream_claim(tu_edpt_stream_t* s) return false; } +TU_ATTR_ALWAYS_INLINE static inline +bool stream_xfer(tu_edpt_stream_t* s, uint16_t count) +{ + if (s->is_host) + { + #if CFG_TUH_ENABLED + return usbh_edpt_xfer(s->daddr, s->ep_addr, count ? s->ep_buf : NULL, count); + #endif + }else + { + #if CFG_TUD_ENABLED + return usbd_edpt_xfer(s->rhport, s->ep_addr, cont ? s->ep_buf : NULL, count); + #endif + } + + return false; +} + +TU_ATTR_ALWAYS_INLINE static inline +bool stream_release(tu_edpt_stream_t* s) +{ + if (s->is_host) + { + #if CFG_TUH_ENABLED + return usbh_edpt_release(s->daddr, s->ep_addr); + #endif + }else + { + #if CFG_TUD_ENABLED + return usbd_edpt_release(s->rhport, s->ep_addr); + #endif + } + + return false; +} //--------------------------------------------------------------------+ // Stream Write @@ -253,7 +288,7 @@ bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferr TU_VERIFY( !tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (s->ep_packetsize-1))) ); TU_VERIFY( stream_claim(s) ); - TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, NULL, 0) ); + TU_ASSERT( stream_xfer(s, 0) ); return true; } @@ -271,16 +306,13 @@ uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s) if ( count ) { - //TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 ); - TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, s->ep_buf, count), 0 ); + TU_ASSERT( stream_xfer(s, count), 0 ); return count; }else { // Release endpoint since we don't make any transfer // Note: data is dropped if terminal is not connected - //usbd_edpt_release(rhport, p_cdc->ep_in); - - usbh_edpt_release(s->daddr, s->ep_addr); + stream_release(s); return 0; } } @@ -327,32 +359,13 @@ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s) uint16_t count = (uint16_t) (available & ~(s->ep_packetsize -1)); count = tu_min16(count, s->ep_bufsize); - if (s->is_host) - { - #if CFG_TUH_ENABLED - TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, s->ep_buf, count), 0 ); - #endif - }else - { - #if CFG_TUD_ENABLED - TU_ASSERT( usbd_edpt_xfer(s->rhport, s->ep_addr, s->ep_buf, count), 0 ); - #endif - } + TU_ASSERT( stream_xfer(s, count), 0 ); + return count; }else { // Release endpoint since we don't make any transfer - if (s->is_host) - { - #if CFG_TUH_ENABLED - usbh_edpt_release(s->daddr, s->ep_addr); - #endif - }else - { - #if CFG_TUD_ENABLED - usbd_edpt_release(s->rhport, s->ep_addr); - #endif - } + stream_release(s); return 0; } -- cgit v1.3.1 From c99af908f10103c0829c4adc1ef74832c3ca4482 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 22 Dec 2022 11:41:27 +0700 Subject: fix typo --- src/tusb.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src') diff --git a/src/tusb.c b/src/tusb.c index 8f64f4acf..a5c820b8d 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -253,7 +253,7 @@ bool stream_xfer(tu_edpt_stream_t* s, uint16_t count) }else { #if CFG_TUD_ENABLED - return usbd_edpt_xfer(s->rhport, s->ep_addr, cont ? s->ep_buf : NULL, count); + return usbd_edpt_xfer(s->rhport, s->ep_addr, count ? s->ep_buf : NULL, count); #endif } @@ -366,7 +366,6 @@ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s) { // Release endpoint since we don't make any transfer stream_release(s); - return 0; } } -- cgit v1.3.1 From 11233e4d3e04ceab1ad6e33d37a166aa48c436de Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 22 Dec 2022 11:43:57 +0700 Subject: minor clean up --- examples/host/cdc_msc_hid/src/tusb_config.h | 4 ++++ src/class/cdc/cdc_host.h | 28 +++++----------------------- 2 files changed, 9 insertions(+), 23 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index c515405cb..e3d9356f6 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -108,6 +108,10 @@ #define CFG_TUH_HID_EPIN_BUFSIZE 64 #define CFG_TUH_HID_EPOUT_BUFSIZE 64 +//------------- CDC -------------// +// Set both DTR ( bit 0), RTS (bit 1) on enumeration/mounted +#define CFG_TUH_CDC_SET_DTRRTS_ON_ENUM 0x03 + #ifdef __cplusplus } #endif diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 02ae69111..5407c646d 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -49,7 +49,7 @@ // RX Endpoint size #ifndef CFG_TUH_CDC_RX_EPSIZE -#define CFG_TUH_CDC_RX_EPSIZE USBH_EPSIZE_BULK_MAX +#define CFG_TUH_CDC_RX_EPSIZE USBH_EPSIZE_BULK_MAX #endif // TX FIFO size @@ -59,7 +59,7 @@ // TX Endpoint size #ifndef CFG_TUH_CDC_TX_EPSIZE -#define CFG_TUH_CDC_TX_EPSIZE USBH_EPSIZE_BULK_MAX +#define CFG_TUH_CDC_TX_EPSIZE USBH_EPSIZE_BULK_MAX #endif //--------------------------------------------------------------------+ @@ -145,7 +145,9 @@ static inline bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, ui return tuh_cdc_set_control_line_state(idx, 0x00, complete_cb, user_data); } -//------------- Application Callback -------------// +//--------------------------------------------------------------------+ +// CDC APPLICATION CALLBACKS +//--------------------------------------------------------------------+ // Invoked when a device with CDC interface is mounted // idx is index of cdc interface in the internal pool. @@ -160,26 +162,6 @@ TU_ATTR_WEAK extern void tuh_cdc_rx_cb(uint8_t idx); // Invoked when a TX is complete and therefore space becomes available in TX buffer TU_ATTR_WEAK extern void tuh_cdc_tx_complete_cb(uint8_t idx); -//--------------------------------------------------------------------+ -// CDC APPLICATION CALLBACKS -//--------------------------------------------------------------------+ - -/** \brief Callback function that is invoked when an transferring event occurred - * \param[in] dev_addr Address of device - * \param[in] event an value from \ref xfer_result_t - * \param[in] pipe_id value from \ref cdc_pipeid_t indicate the pipe - * \param[in] xferred_bytes Number of bytes transferred via USB bus - * \note event can be one of following - * - XFER_RESULT_SUCCESS : previously scheduled transfer completes successfully. - * - XFER_RESULT_FAILED : previously scheduled transfer encountered a transaction error. - * - XFER_RESULT_STALLED : previously scheduled transfer is stalled by device. - * \note - */ -// void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_id, uint32_t xferred_bytes); - -/// @} // group CDC_Serial_Host -/// @} - //--------------------------------------------------------------------+ // Internal Class Driver API //--------------------------------------------------------------------+ -- cgit v1.3.1 From 05c119ce975668eff814c78d5306589fc2d24530 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 22 Dec 2022 18:28:06 +0700 Subject: cdc host, add set line coding API --- examples/host/cdc_msc_hid/src/tusb_config.h | 11 ++- src/class/cdc/cdc.h | 28 ++++-- src/class/cdc/cdc_host.c | 129 +++++++++++++++++++++------- src/class/cdc/cdc_host.h | 16 +++- 4 files changed, 143 insertions(+), 41 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index e3d9356f6..139a921d1 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -109,8 +109,15 @@ #define CFG_TUH_HID_EPOUT_BUFSIZE 64 //------------- CDC -------------// -// Set both DTR ( bit 0), RTS (bit 1) on enumeration/mounted -#define CFG_TUH_CDC_SET_DTRRTS_ON_ENUM 0x03 + +// Set Line Control state on enumeration/mounted: +// DTR ( bit 0), RTS (bit 1) +#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM 0x03 + +// Set Line Coding on enumeration/mounted, value for cdc_line_coding_t +// bit rate = 115200, 1 stop bit, no parity, 8 bit data width +#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } + #ifdef __cplusplus } diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index 6a9669cf2..9a3fc21ee 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -198,6 +198,22 @@ enum CDC_CONTROL_LINE_STATE_RTS = 0x02, }; +enum +{ + CDC_LINE_CONDING_STOP_BITS_1 = 0, // 1 bit + CDC_LINE_CONDING_STOP_BITS_1_5 = 1, // 1.5 bits + CDC_LINE_CONDING_STOP_BITS_2 = 2, // 2 bits +}; + +enum +{ + CDC_LINE_CODING_PARITY_NONE = 0, + CDC_LINE_CODING_PARITY_ODD = 1, + CDC_LINE_CODING_PARITY_EVEN = 2, + CDC_LINE_CODING_PARITY_MARK = 3, + CDC_LINE_CODING_PARITY_SPACE = 4, +}; + //--------------------------------------------------------------------+ // Management Element Notification (Notification Endpoint) //--------------------------------------------------------------------+ @@ -207,13 +223,13 @@ typedef enum { CDC_NOTIF_NETWORK_CONNECTION = 0x00, ///< This notification allows the device to notify the host about network connection status. CDC_NOTIF_RESPONSE_AVAILABLE = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request. - CDC_NOTIF_AUX_JACK_HOOK_STATE = 0x08, - CDC_NOTIF_RING_DETECT = 0x09, - CDC_NOTIF_SERIAL_STATE = 0x20, - CDC_NOTIF_CALL_STATE_CHANGE = 0x28, - CDC_NOTIF_LINE_STATE_CHANGE = 0x29, + CDC_NOTIF_AUX_JACK_HOOK_STATE = 0x08,///< CDC_NOTIF_AUX_JACK_HOOK_STATE + CDC_NOTIF_RING_DETECT = 0x09,///< CDC_NOTIF_RING_DETECT + CDC_NOTIF_SERIAL_STATE = 0x20,///< CDC_NOTIF_SERIAL_STATE + CDC_NOTIF_CALL_STATE_CHANGE = 0x28,///< CDC_NOTIF_CALL_STATE_CHANGE + CDC_NOTIF_LINE_STATE_CHANGE = 0x29,///< CDC_NOTIF_LINE_STATE_CHANGE CDC_NOTIF_CONNECTION_SPEED_CHANGE = 0x2A, ///< This notification allows the device to inform the host-networking driver that a change in either the upstream or the downstream bit rate of the connection has occurred - CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40, + CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40,///< CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION }cdc_notification_request_t; //--------------------------------------------------------------------+ diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index de1466cb1..fcabb922a 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -52,8 +52,8 @@ typedef struct { cdc_acm_capability_t acm_capability; uint8_t ep_notif; - // Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send) - uint8_t line_state; + cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width + uint8_t line_state; // DTR (bit0), RTS (bit1) tuh_xfer_cb_t user_control_cb; @@ -240,6 +240,13 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue); break; + case CDC_REQUEST_SET_LINE_CODING: + { + uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength)); + memcpy(&p_cdc->line_coding, xfer->buffer, len); + } + break; + default: break; } } @@ -265,7 +272,7 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c }, .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE, .wValue = tu_htole16(line_state), - .wIndex = tu_htole16(p_cdc->bInterfaceNumber), + .wIndex = tu_htole16((uint16_t) p_cdc->bInterfaceNumber), .wLength = 0 }; @@ -283,6 +290,46 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c return tuh_control_xfer(&xfer); } +bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc && p_cdc->acm_capability.support_line_request); + + TU_LOG_CDCH("CDC Set Line Conding\r\n"); + + tusb_control_request_t const request = + { + .bmRequestType_bit = + { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_CLASS, + .direction = TUSB_DIR_OUT + }, + .bRequest = CDC_REQUEST_SET_LINE_CODING, + .wValue = 0, + .wIndex = tu_htole16(p_cdc->bInterfaceNumber), + .wLength = tu_htole16(sizeof(cdc_line_coding_t)) + }; + + // use usbh enum buf to hold line coding since user line_coding variable may not live long enough + // for the transfer to complete + uint8_t* enum_buf = usbh_get_enum_buf(); + memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t)); + + p_cdc->user_control_cb = complete_cb; + tuh_xfer_t xfer = + { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request, + .buffer = enum_buf, + .complete_cb = cdch_internal_control_complete, + .user_data = user_data + }; + + return tuh_control_xfer(&xfer); +} + //--------------------------------------------------------------------+ // CLASS-USBH API //--------------------------------------------------------------------+ @@ -448,46 +495,70 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d return true; } -static void config_cdc_complete(uint8_t daddr, uint8_t itf_num) +enum { - uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num); + CONFIG_SET_CONTROL_LINE_STATE, + CONFIG_SET_LINE_CODING, + CONFIG_COMPLETE +}; - if (idx != TUSB_INDEX_INVALID) +static void process_cdc_config(tuh_xfer_t* xfer) +{ + uintptr_t const state = xfer->user_data; + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + TU_ASSERT(idx != TUSB_INDEX_INVALID, ); + + switch(state) { - if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx); + case CONFIG_SET_CONTROL_LINE_STATE: + #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + TU_ASSERT( tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cdc_config, CONFIG_SET_LINE_CODING), ); + break; + #endif + TU_ATTR_FALLTHROUGH; - // Prepare for incoming data - cdch_interface_t* p_cdc = get_itf(idx); - tu_edpt_stream_read_xfer(&p_cdc->stream.rx); - } + case CONFIG_SET_LINE_CODING: + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + { + cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, 0), ); + break; + } + #endif + TU_ATTR_FALLTHROUGH; - // notify usbh that driver enumeration is complete - // itf_num+1 to account for data interface as well - usbh_driver_set_config_complete(daddr, itf_num+1); -} + case CONFIG_COMPLETE: + if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx); -#if CFG_TUH_CDC_SET_DTRRTS_ON_ENUM + // Prepare for incoming data + cdch_interface_t* p_cdc = get_itf(idx); + tu_edpt_stream_read_xfer(&p_cdc->stream.rx); -static void config_set_dtr_rts_complete (tuh_xfer_t* xfer) -{ - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - config_cdc_complete(xfer->daddr, itf_num); + // notify usbh that driver enumeration is complete + // itf_num+1 to account for data interface as well + usbh_driver_set_config_complete(xfer->daddr, itf_num+1); + break; + + default: break; + } } bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { - uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num); - return tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_SET_DTRRTS_ON_ENUM, config_set_dtr_rts_complete, 0); -} + // fake transfer to kick-off process + tusb_control_request_t request; + request.wIndex = tu_htole16((uint16_t) itf_num); -#else + tuh_xfer_t xfer; + xfer.daddr = daddr; + xfer.result = XFER_RESULT_SUCCESS; + xfer.setup = &request; + xfer.user_data = CONFIG_SET_CONTROL_LINE_STATE; + + process_cdc_config(&xfer); -bool cdch_set_config(uint8_t daddr, uint8_t itf_num) -{ - config_cdc_complete(daddr, itf_num); return true; } #endif - -#endif diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 5407c646d..9bf5af46c 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -37,11 +37,16 @@ // Class Driver Configuration //--------------------------------------------------------------------+ -// Set DTR ( bit 0), RTS (bit 1) on enumeration/mounted -#ifndef CFG_TUH_CDC_SET_DTRRTS_ON_ENUM -#define CFG_TUH_CDC_SET_DTRRTS_ON_ENUM 0 +// Set Line Control state on enumeration/mounted: DTR ( bit 0), RTS (bit 1) +#ifndef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM +#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM 0 #endif +// Set Line Coding on enumeration/mounted, value for cdc_line_coding_t +//#ifndef CFG_TUH_CDC_LINE_CODING_ON_ENUM +//#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } +//#endif + // RX FIFO size #ifndef CFG_TUH_CDC_RX_BUFSIZE #define CFG_TUH_CDC_RX_BUFSIZE USBH_EPSIZE_BULK_MAX @@ -130,9 +135,12 @@ bool tuh_cdc_read_clear (uint8_t idx); // Control Endpoint (Request) API //--------------------------------------------------------------------+ -// Send control request to Set Control Line State: DTR (bit 0), RTS (bit 1) +// Request to Set Control Line State: DTR (bit 0), RTS (bit 1) bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +// Request to Set Line Coding +bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + // Connect by set both DTR, RTS static inline bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { -- cgit v1.3.1 From 14d45b580e0cd82e77e36ecb152f7c001d860ce7 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 22 Dec 2022 19:17:09 +0700 Subject: correct host cdc enum --- src/class/cdc/cdc_host.c | 2 +- src/host/usbh.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index fcabb922a..05e0bdfc7 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -522,7 +522,7 @@ static void process_cdc_config(tuh_xfer_t* xfer) #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM { cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, 0), ); + TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, CONFIG_COMPLETE), ); break; } #endif diff --git a/src/host/usbh.c b/src/host/usbh.c index f0ca7be2e..af1e67d4d 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -330,6 +330,8 @@ bool tuh_init(uint8_t controller_id) TU_LOG_INT(USBH_DEBUG, sizeof(hcd_event_t)); TU_LOG_INT(USBH_DEBUG, sizeof(_ctrl_xfer)); TU_LOG_INT(USBH_DEBUG, sizeof(tuh_xfer_t)); + TU_LOG_INT(USBH_DEBUG, sizeof(tu_fifo_t)); + TU_LOG_INT(USBH_DEBUG, sizeof(tu_edpt_stream_t)); // Event queue _usbh_q = osal_queue_create( &_usbh_qdef ); @@ -1275,7 +1277,7 @@ static void process_enumeration(tuh_xfer_t* xfer) break; } #endif - __attribute__((fallthrough)); + TU_ATTR_FALLTHROUGH; #endif case ENUM_SET_ADDR: -- cgit v1.3.1 From f33883c308959aa2ca08ef55282c82c54f929226 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 22 Dec 2022 19:41:39 +0700 Subject: add tuh_cdc_get_local_line_coding() --- examples/host/cdc_msc_hid/src/cdc_app.c | 15 +++++++++++++-- src/class/cdc/cdc_host.c | 22 ++++++++++++++++++++-- src/class/cdc/cdc_host.h | 12 ++++++++++++ 3 files changed, 45 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c index dd3196146..b1b137e0e 100644 --- a/examples/host/cdc_msc_hid/src/cdc_app.c +++ b/examples/host/cdc_msc_hid/src/cdc_app.c @@ -90,7 +90,18 @@ void tuh_cdc_mount_cb(uint8_t idx) tuh_cdc_itf_info_t itf_info = { 0 }; tuh_cdc_itf_get_info(idx, &itf_info); - printf("CDC Interface is mounted: device address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber); + printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber); + +#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration + // otherwise you need to call tuh_cdc_set_line_coding() first + cdc_line_coding_t line_coding = { 0 }; + if ( tuh_cdc_get_local_line_coding(idx, &line_coding) ) + { + printf(" Baudrate: %lu, Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits); + printf(" Parity : %u, Data Width: %u\r\n", line_coding.parity , line_coding.data_bits); + } +#endif } void tuh_cdc_umount_cb(uint8_t idx) @@ -98,5 +109,5 @@ void tuh_cdc_umount_cb(uint8_t idx) tuh_cdc_itf_info_t itf_info = { 0 }; tuh_cdc_itf_get_info(idx, &itf_info); - printf("CDC Interface is unmounted: device address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber); + printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber); } diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 05e0bdfc7..17dc877f8 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -52,8 +52,8 @@ typedef struct { cdc_acm_capability_t acm_capability; uint8_t ep_notif; - cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width - uint8_t line_state; // DTR (bit0), RTS (bit1) + cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width + uint8_t line_state; // DTR (bit0), RTS (bit1) tuh_xfer_cb_t user_control_cb; @@ -162,6 +162,20 @@ bool tuh_cdc_get_rts(uint8_t idx) return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false; } +bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); + + *line_coding = p_cdc->line_coding; + + return true; +} + +//--------------------------------------------------------------------+ +// Write +//--------------------------------------------------------------------+ + uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize) { cdch_interface_t* p_cdc = get_itf(idx); @@ -194,6 +208,10 @@ uint32_t tuh_cdc_write_available(uint8_t idx) return tu_edpt_stream_write_available(&p_cdc->stream.tx); } +//--------------------------------------------------------------------+ +// Read +//--------------------------------------------------------------------+ + uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) { cdch_interface_t* p_cdc = get_itf(idx); diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 9bf5af46c..502ad430d 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -102,6 +102,12 @@ TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_connected(uint8_t idx) return tuh_cdc_get_dtr(idx); } +// Get local (saved/cached) version of line coding. +// This function should return correct values if tuh_cdc_set_line_coding() / tuh_cdc_get_line_coding() +// are invoked previously or CFG_TUH_CDC_LINE_CODING_ON_ENUM is defined. +// NOTE: This function does not make any USB transfer request to device. +bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding); + //--------------------------------------------------------------------+ // Write API //--------------------------------------------------------------------+ @@ -133,6 +139,7 @@ bool tuh_cdc_read_clear (uint8_t idx); //--------------------------------------------------------------------+ // Control Endpoint (Request) API +// Each Function will make a USB transfer request to/from device //--------------------------------------------------------------------+ // Request to Set Control Line State: DTR (bit 0), RTS (bit 1) @@ -141,6 +148,11 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c // Request to Set Line Coding bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +// Request to Get Line Coding +// Should only use if tuh_cdc_set_line_coding() / tuh_cdc_get_line_coding() never got invoked and +// CFG_TUH_CDC_LINE_CODING_ON_ENUM is not defined +// bool tuh_cdc_get_line_coding(uint8_t idx, cdc_line_coding_t* coding); + // Connect by set both DTR, RTS static inline bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { -- cgit v1.3.1 From 396716cc2c29b151556d554c560307afcadd7252 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 22 Dec 2022 20:26:32 +0700 Subject: clean up --- examples/host/cdc_msc_hid/CMakeLists.txt | 2 +- src/class/cdc/cdc.h | 22 ++++++---------------- 2 files changed, 7 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt index 2e89817a5..7af6b738e 100644 --- a/examples/host/cdc_msc_hid/CMakeLists.txt +++ b/examples/host/cdc_msc_hid/CMakeLists.txt @@ -15,8 +15,8 @@ add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c ) diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index 9a3fc21ee..2fecde3ca 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -41,16 +41,6 @@ /** \defgroup ClassDriver_CDC_Common Common Definitions * @{ */ -// TODO remove -/// CDC Pipe ID, used to indicate which pipe the API is addressing to (Notification, Out, In) -typedef enum -{ - CDC_PIPE_NOTIFICATION , ///< Notification pipe - CDC_PIPE_DATA_IN , ///< Data in pipe - CDC_PIPE_DATA_OUT , ///< Data out pipe - CDC_PIPE_ERROR , ///< Invalid Pipe ID -}cdc_pipeid_t; - //--------------------------------------------------------------------+ // CDC Communication Interface Class //--------------------------------------------------------------------+ @@ -223,13 +213,13 @@ typedef enum { CDC_NOTIF_NETWORK_CONNECTION = 0x00, ///< This notification allows the device to notify the host about network connection status. CDC_NOTIF_RESPONSE_AVAILABLE = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request. - CDC_NOTIF_AUX_JACK_HOOK_STATE = 0x08,///< CDC_NOTIF_AUX_JACK_HOOK_STATE - CDC_NOTIF_RING_DETECT = 0x09,///< CDC_NOTIF_RING_DETECT - CDC_NOTIF_SERIAL_STATE = 0x20,///< CDC_NOTIF_SERIAL_STATE - CDC_NOTIF_CALL_STATE_CHANGE = 0x28,///< CDC_NOTIF_CALL_STATE_CHANGE - CDC_NOTIF_LINE_STATE_CHANGE = 0x29,///< CDC_NOTIF_LINE_STATE_CHANGE + CDC_NOTIF_AUX_JACK_HOOK_STATE = 0x08, + CDC_NOTIF_RING_DETECT = 0x09, + CDC_NOTIF_SERIAL_STATE = 0x20, + CDC_NOTIF_CALL_STATE_CHANGE = 0x28, + CDC_NOTIF_LINE_STATE_CHANGE = 0x29, CDC_NOTIF_CONNECTION_SPEED_CHANGE = 0x2A, ///< This notification allows the device to inform the host-networking driver that a change in either the upstream or the downstream bit rate of the connection has occurred - CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40,///< CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION + CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40, }cdc_notification_request_t; //--------------------------------------------------------------------+ -- cgit v1.3.1 From 15a02d04df33afdeddc751453bbaefd4bc895939 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 22 Dec 2022 21:35:55 +0700 Subject: fix incorrect rx buf in cdc --- src/class/cdc/cdc_device.c | 2 +- src/class/cdc/cdc_device.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index 0bbbaaa83..8d10a416c 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -432,7 +432,7 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_ // Received new data if ( ep_addr == p_cdc->ep_out ) { - tu_fifo_write_n(&p_cdc->rx_ff, &p_cdc->epout_buf, (uint16_t) xferred_bytes); + tu_fifo_write_n(&p_cdc->rx_ff, p_cdc->epout_buf, (uint16_t) xferred_bytes); // Check for wanted char and invoke callback if needed if ( tud_cdc_rx_wanted_cb && (((signed char) p_cdc->wanted_char) != -1) ) diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h index f625a7554..a7d25bd32 100644 --- a/src/class/cdc/cdc_device.h +++ b/src/class/cdc/cdc_device.h @@ -134,7 +134,7 @@ TU_ATTR_WEAK void tud_cdc_rx_cb(uint8_t itf); // Invoked when received `wanted_char` TU_ATTR_WEAK void tud_cdc_rx_wanted_cb(uint8_t itf, char wanted_char); -// Invoked when space becomes available in TX buffer +// Invoked when a TX is complete and therefore space becomes available in TX buffer TU_ATTR_WEAK void tud_cdc_tx_complete_cb(uint8_t itf); // Invoked when line state DTR & RTS are changed via SET_CONTROL_LINE_STATE -- cgit v1.3.1 From 48d4a67ec5468f9fd7c073acd599a1271b9e877f Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 24 Dec 2022 01:11:13 +0700 Subject: add tuh_cdc_peek() --- src/class/cdc/cdc_device.h | 2 +- src/class/cdc/cdc_host.c | 8 ++++++++ src/class/cdc/cdc_host.h | 3 +++ src/common/tusb_fifo.c | 2 -- src/common/tusb_private.h | 5 +++++ 5 files changed, 17 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h index a7d25bd32..f8a004df4 100644 --- a/src/class/cdc/cdc_device.h +++ b/src/class/cdc/cdc_device.h @@ -80,7 +80,7 @@ int32_t tud_cdc_n_read_char (uint8_t itf); // Clear the received FIFO void tud_cdc_n_read_flush (uint8_t itf); -// Get a byte from FIFO at the specified position without removing it +// Get a byte from FIFO without removing it bool tud_cdc_n_peek (uint8_t itf, uint8_t* ui8); // Write bytes to TX FIFO, data may remain in the FIFO for a while diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 17dc877f8..e9c3d34cb 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -228,6 +228,14 @@ uint32_t tuh_cdc_read_available(uint8_t idx) return tu_edpt_stream_read_available(&p_cdc->stream.rx); } +bool tuh_cdc_peek(uint8_t idx, uint8_t* ch) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); + + return tu_edpt_stream_peek(&p_cdc->stream.rx, ch); +} + bool tuh_cdc_read_clear (uint8_t idx) { cdch_interface_t* p_cdc = get_itf(idx); diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 502ad430d..c759527e6 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -134,6 +134,9 @@ uint32_t tuh_cdc_read_available(uint8_t idx); // Read from cdc interface uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize); +// Get a byte from RX FIFO without removing it +bool tuh_cdc_peek(uint8_t idx, uint8_t* ch); + // Clear the received FIFO bool tuh_cdc_read_clear (uint8_t idx); diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index b857c6444..d45ca09ed 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -682,8 +682,6 @@ uint16_t tu_fifo_read_n_const_addr_full_words(tu_fifo_t* f, void * buffer, uint1 @param[in] f Pointer to the FIFO buffer to manipulate - @param[in] offset - Position to read from in the FIFO buffer with respect to read pointer @param[in] p_buffer Pointer to the place holder for data read from the buffer diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h index d0c7a84fb..d5541856c 100644 --- a/src/common/tusb_private.h +++ b/src/common/tusb_private.h @@ -160,6 +160,11 @@ uint32_t tu_edpt_stream_read_available(tu_edpt_stream_t* s) return (uint32_t) tu_fifo_count(&s->ff); } +TU_ATTR_ALWAYS_INLINE static inline +bool tu_edpt_stream_peek(tu_edpt_stream_t* s, uint8_t* ch) +{ + return tu_fifo_peek(&s->ff, ch); +} #ifdef __cplusplus } -- cgit v1.3.1 From d0ca6ca8f728fadcc12053c24ada23e328f2180a Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 27 Dec 2022 18:21:56 +0700 Subject: fix ncm warning --- src/class/net/ncm_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c index 00892b49c..1cbc0ce01 100644 --- a/src/class/net/ncm_device.c +++ b/src/class/net/ncm_device.c @@ -392,7 +392,7 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t if (NCM_GET_NTB_PARAMETERS == request->bRequest) { - tud_control_xfer(rhport, request, (void*)&ntb_parameters, sizeof(ntb_parameters)); + tud_control_xfer(rhport, request, (void*)(uintptr_t) &ntb_parameters, sizeof(ntb_parameters)); } break; -- cgit v1.3.1 From 95ba158a1070635551b01d921cb4c5eeb7734989 Mon Sep 17 00:00:00 2001 From: Staacks Date: Tue, 27 Dec 2022 23:02:33 +0100 Subject: Fix UVC probe and commit on MacOS --- src/class/video/video_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index a6d2724c1..e17d0a90f 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -917,7 +917,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: if (stage == CONTROL_STAGE_SETUP) { - TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN); + TU_VERIFY(sizeof(video_probe_and_commit_control_t) >= request->wLength, VIDEO_ERROR_UNKNOWN); TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); } else if (stage == CONTROL_STAGE_DATA) { @@ -973,7 +973,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: if (stage == CONTROL_STAGE_SETUP) { - TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN); + TU_VERIFY(sizeof(video_probe_and_commit_control_t) >= request->wLength, VIDEO_ERROR_UNKNOWN); TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); } else if (stage == CONTROL_STAGE_DATA) { TU_VERIFY(_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); -- cgit v1.3.1 From 6d65eaf7a18a498ef686a21e3d3ccb98dd42ec03 Mon Sep 17 00:00:00 2001 From: Simon Kueppers Date: Mon, 24 Oct 2022 19:59:59 +0200 Subject: Implemented very rudimentary support for isochronous transfer buffer handling --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 134 +++++++++++---------- .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 2 + 2 files changed, 75 insertions(+), 61 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 0e78c796e..17b5c7068 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -163,7 +163,7 @@ TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligne typedef struct { uint8_t * buffer; - // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API + tu_fifo_t * ff; uint16_t total_len; uint16_t queued_len; uint16_t pma_ptr; @@ -196,8 +196,8 @@ static void dcd_pma_free(uint8_t ep_addr); static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes); static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes); -//static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wNBytes); -//static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNBytes); +static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wNBytes); +static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNBytes); // Using a function due to better type checks // This seems better than having to do type casts everywhere else @@ -222,7 +222,7 @@ void dcd_init (uint8_t rhport) { asm("NOP"); } - // Perform USB peripheral reset + // Perform USB peripheral reset USB->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN; for(uint32_t i = 0; i<200; i++) // should be a few us { @@ -526,15 +526,15 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) if (count != 0U) { -#if 0 // TODO support dcd_edpt_xfer_fifo API + uint16_t addr = *pcd_ep_rx_address_ptr(USB, EPindex); + if (xfer->ff) { - dcd_read_packet_memory_ff(xfer->ff, *pcd_ep_rx_address_ptr(USB,EPindex), count); + dcd_read_packet_memory_ff(xfer->ff, addr, count); } else -#endif { - dcd_read_packet_memory(&(xfer->buffer[xfer->queued_len]), *pcd_ep_rx_address_ptr(USB,EPindex), count); + dcd_read_packet_memory(&(xfer->buffer[xfer->queued_len]), addr, count); } xfer->queued_len = (uint16_t)(xfer->queued_len + count); @@ -683,6 +683,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re static void dcd_pma_alloc_reset(void) { + open_ep_count = 0; ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8*MAX_EP_COUNT; // 8 bytes per endpoint (two TX and two RX words, each) //TU_LOG2("dcd_pma_alloc_reset()\r\n"); for(uint32_t i=0; ipma_alloc_size != 0U) { //TU_LOG2("dcd_pma_alloc(%x,%x)=%x (cached)\r\n",ep_addr,length,epXferCtl->pma_ptr); @@ -771,9 +773,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc const uint16_t epMaxPktSize = tu_edpt_packet_size(p_endpoint_desc); uint16_t pma_addr; uint32_t wType; - + // Isochronous not supported (yet), and some other driver assumptions. - TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS); TU_ASSERT(epnum < MAX_EP_COUNT); // Set type @@ -781,12 +782,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc case TUSB_XFER_CONTROL: wType = USB_EP_CONTROL; break; -#if (0) - case TUSB_XFER_ISOCHRONOUS: // FIXME: Not yet supported + case TUSB_XFER_ISOCHRONOUS: wType = USB_EP_ISOCHRONOUS; break; -#endif - case TUSB_XFER_BULK: wType = USB_EP_CONTROL; break; @@ -805,21 +803,41 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc // or being double-buffered (bulk endpoints) pcd_clear_ep_kind(USB,0); + /* Create a packet memory buffer area. For isochronous endpoints, + * use the same buffer as the double buffer, essentially disabling double buffering */ pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, epMaxPktSize); +#if defined(ISOCHRONOUS_DOUBLEBUFFER) + if( (dir == TUSB_DIR_IN) || (wType == USB_EP_ISOCHRONOUS) ) +#else if(dir == TUSB_DIR_IN) +#endif { *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr; pcd_set_ep_tx_cnt(USB, epnum, epMaxPktSize); pcd_clear_tx_dtog(USB, epnum); - pcd_set_ep_tx_status(USB,epnum,USB_EP_TX_NAK); + + if(wType == USB_EP_ISOCHRONOUS) { + pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS); + } else { + pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_NAK); + } } +#if defined(ISOCHRONOUS_DOUBLEBUFFER) + if( (dir == TUSB_DIR_OUT) || (wType == USB_EP_ISOCHRONOUS) ) +#else else +#endif { *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr; pcd_set_ep_rx_cnt(USB, epnum, epMaxPktSize); pcd_clear_rx_dtog(USB, epnum); - pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK); + + if(wType == USB_EP_ISOCHRONOUS) { + pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS); + } else { + pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK); + } } xfer_ctl_ptr(epnum, dir)->max_packet_size = epMaxPktSize; @@ -845,10 +863,10 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) (void)rhport; uint32_t const epnum = tu_edpt_number(ep_addr); uint32_t const dir = tu_edpt_dir(ep_addr); - + if(dir == TUSB_DIR_IN) { - pcd_set_ep_tx_status(USB,epnum,USB_EP_TX_DIS); + pcd_set_ep_tx_status(USB,epnum, USB_EP_TX_DIS); } else { @@ -868,15 +886,14 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix) { len = xfer->max_packet_size; } + uint16_t oldAddr = *pcd_ep_tx_address_ptr(USB,ep_ix); -#if 0 // TODO support dcd_edpt_xfer_fifo API if (xfer->ff) { dcd_write_packet_memory_ff(xfer->ff, oldAddr, len); } else -#endif { dcd_write_packet_memory(oldAddr, &(xfer->buffer[xfer->queued_len]), len); } @@ -896,7 +913,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir); xfer->buffer = buffer; - // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API + xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API xfer->total_len = total_bytes; xfer->queued_len = 0; @@ -908,6 +925,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t { xfer->buffer = (uint8_t*)_setup_packet; } + if(total_bytes > xfer->max_packet_size) { pcd_set_ep_rx_cnt(USB,epnum,xfer->max_packet_size); @@ -923,7 +941,6 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t return true; } -#if 0 // TODO support dcd_edpt_xfer_fifo API bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) { (void) rhport; @@ -934,7 +951,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir); xfer->buffer = NULL; - // xfer->ff = ff; // TODO support dcd_edpt_xfer_fifo API + xfer->ff = ff; // TODO support dcd_edpt_xfer_fifo API xfer->total_len = total_bytes; xfer->queued_len = 0; @@ -954,7 +971,6 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 } return true; } -#endif void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) { @@ -978,7 +994,10 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) { // IN ep_addr &= 0x7F; - pcd_set_ep_tx_status(USB,ep_addr, USB_EP_TX_NAK); + uint8_t const epnum = tu_edpt_number(ep_addr); + if (pcd_get_eptype(USB, epnum) != USB_EP_ISOCHRONOUS) { + pcd_set_ep_tx_status(USB,ep_addr, USB_EP_TX_NAK); + } /* Reset to DATA0 if clearing stall condition. */ pcd_clear_tx_dtog(USB,ep_addr); @@ -1029,7 +1048,6 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si return true; } -#if 0 // TODO support dcd_edpt_xfer_fifo API /** * @brief Copy from FIFO to packet memory area (PMA). * Uses byte-access of system memory and 16-bit access of packet memory @@ -1043,38 +1061,36 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN { // Since we copy from a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies // Check for first linear part - void * src; - uint16_t len = tu_fifo_get_linear_read_info(ff, 0, &src, wNBytes); // We want to read from the FIFO - THIS FUNCTION CHANGED!!! - TU_VERIFY(len && dcd_write_packet_memory(dst, src, len)); // and write it into the PMA - tu_fifo_advance_read_pointer(ff, len); + tu_fifo_buffer_info_t info; + tu_fifo_get_read_info(ff, &info); // We want to read from the FIFO + TU_VERIFY(info.len_lin && dcd_write_packet_memory(dst, info.ptr_lin, info.len_lin)); // and write it into the PMA + tu_fifo_advance_read_pointer(ff, info.len_lin); // Check for wrapped part - if (len < wNBytes) + if (info.len_wrap) { - // Get remaining wrapped length - uint16_t len2 = tu_fifo_get_linear_read_info(ff, 0, &src, wNBytes - len); - TU_VERIFY(len2); - // Update destination pointer - dst += len; + dst += info.len_lin; + uint8_t* src = (uint8_t*)info.ptr_wrap; + uint16_t len2 = info.len_wrap; // Since PMA is accessed 16-bit wise we need to handle the case when a 16 bit value was split - if (len % 2) // If len is uneven there is a byte left to copy + if (info.len_lin % 2) // If len is uneven there is a byte left to copy { - // Since PMA can accessed only 16 bit-wise we copy the last byte again - tu_fifo_backward_read_pointer(ff, 1); // Move one byte back and copy two bytes for the PMA - tu_fifo_read_n(ff, (void *) &pma[PMA_STRIDE*(dst>>1)], 2); // Since EP FIFOs must be of item size 1 this is safe to do - dst++; + TU_ASSERT(false); // TODO: Step through and check -> untested + + uint16_t temp = ((uint8_t *)info.ptr_lin)[info.len_lin-1] | src[0] << 16; // CHECK endianess + pma[PMA_STRIDE*(dst>>1)] = temp; + src++; len2--; } TU_VERIFY(dcd_write_packet_memory(dst, src, len2)); - tu_fifo_advance_write_pointer(ff, len2); + tu_fifo_advance_write_pointer(ff, info.len_wrap); } return true; } -#endif /** * @brief Copy a buffer from packet memory area (PMA) to user memory area. @@ -1111,7 +1127,6 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN return true; } -#if 0 // TODO support dcd_edpt_xfer_fifo API /** * @brief Copy a buffer from user packet memory area (PMA) to FIFO. * Uses byte-access of system memory and 16-bit access of packet memory @@ -1125,32 +1140,31 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB { // Since we copy into a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies // Check for first linear part - void * dst; - uint16_t len = tu_fifo_get_linear_write_info(ff, 0, &dst, wNBytes); // THIS FUNCTION CHANGED!!!! - TU_VERIFY(len && dcd_read_packet_memory(dst, src, len)); - tu_fifo_advance_write_pointer(ff, len); + tu_fifo_buffer_info_t info; + tu_fifo_get_write_info(ff, &info); // We want to read from the FIFO + + TU_VERIFY(info.len_lin && dcd_read_packet_memory(info.ptr_lin, src, info.len_lin)); + tu_fifo_advance_write_pointer(ff, info.len_lin); // Check for wrapped part - if (len < wNBytes) + if (info.len_wrap) { - // Get remaining wrapped length - uint16_t len2 = tu_fifo_get_linear_write_info(ff, 0, &dst, wNBytes - len); - TU_VERIFY(len2); - // Update source pointer - src += len; + src += info.len_lin; // Since PMA is accessed 16-bit wise we need to handle the case when a 16 bit value was split - if (len % 2) // If len is uneven there is a byte left to copy + if (info.len_lin % 2) // If len is uneven there is a byte left to copy { + TU_ASSERT(false); //TODO: step through -> untested uint32_t temp = pma[PMA_STRIDE*(src>>1)]; - *((uint8_t *)dst++) = ((temp >> 8) & 0xFF); + *((uint8_t *)info.ptr_wrap++) = ((temp >> 8) & 0xFF); src++; - len2--; + tu_fifo_advance_write_pointer(ff, 1); + info.len_wrap--; } - TU_VERIFY(dcd_read_packet_memory(dst, src, len2)); - tu_fifo_advance_write_pointer(ff, len2); + TU_VERIFY(dcd_read_packet_memory(info.ptr_wrap, src, info.len_wrap)); + tu_fifo_advance_write_pointer(ff, info.len_wrap); } return true; @@ -1158,5 +1172,3 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB #endif -#endif - diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index bffae4500..40c4003c5 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -66,6 +66,7 @@ defined(STM32F373xC) #include "stm32f3xx.h" #define PMA_LENGTH (512u) + #define ISOCHRONOUS_DOUBLEBUFFER // NO internal Pull-ups // *B, and *C: 1 x 16 bits/word // PMA dedicated to USB (no sharing with CAN) @@ -75,6 +76,7 @@ defined(STM32F303xD) || defined(STM32F303xE) #include "stm32f3xx.h" #define PMA_LENGTH (1024u) + #define ISOCHRONOUS_DOUBLEBUFFER // NO internal Pull-ups // *6, *8, *D, and *E: 2 x 16 bits/word LPM Support // When CAN clock is enabled, USB can use first 768 bytes ONLY. -- cgit v1.3.1 From d9b2c9934a5a7051e6f6c19fa4047109c3e056fb Mon Sep 17 00:00:00 2001 From: Simon Kueppers Date: Mon, 24 Oct 2022 22:07:45 +0200 Subject: Implemented an optional callback function that is used instead of tu_edpt_number in the stm32 device driver as a crude tool to control mapping of the endpoint address to actual endpoint register --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 48 ++++++++++++---------- .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 9 ++++ 2 files changed, 35 insertions(+), 22 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 17b5c7068..73fecb750 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -400,7 +400,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) (void) dev_addr; // Respond with status - dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); + dcd_edpt_xfer(rhport, TUSB_DIR_IN_MASK | 0x00, NULL, 0); // DCD can only set address after status for this request is complete. // do it at dcd_edpt0_status_complete() @@ -479,7 +479,8 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr) } else /* TX Complete */ { - dcd_event_xfer_complete(0, (uint8_t)(0x80 + EPindex), xfer->total_len, XFER_RESULT_SUCCESS, true); + uint8_t ep_addr = wEPRegVal & USB_EPADDR_FIELD; + dcd_event_xfer_complete(0, (uint8_t)(TUSB_DIR_IN_MASK | ep_addr), xfer->total_len, XFER_RESULT_SUCCESS, true); } } @@ -543,7 +544,8 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) { /* RX COMPLETE */ - dcd_event_xfer_complete(0, EPindex, xfer->queued_len, XFER_RESULT_SUCCESS, true); + uint8_t ep_addr = wEPRegVal & USB_EPADDR_FIELD; + dcd_event_xfer_complete(0, ep_addr, xfer->queued_len, XFER_RESULT_SUCCESS, true); // Though the host could still send, we don't know. // Does the bulk pipe need to be reset to valid to allow for a ZLP? } @@ -706,7 +708,7 @@ static void dcd_pma_alloc_reset(void) */ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length) { - uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); xfer_ctl_t* epXferCtl = xfer_ctl_ptr(epnum,dir); @@ -737,7 +739,7 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length) */ static void dcd_pma_free(uint8_t ep_addr) { - uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); // Presently, this should never be called for EP0 IN/OUT @@ -768,7 +770,7 @@ static void dcd_pma_free(uint8_t ep_addr) bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { (void)rhport; - uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); + uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(p_endpoint_desc->bEndpointAddress) : tu_edpt_number(p_endpoint_desc->bEndpointAddress); uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); const uint16_t epMaxPktSize = tu_edpt_packet_size(p_endpoint_desc); uint16_t pma_addr; @@ -798,7 +800,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc } pcd_set_eptype(USB, epnum, wType); - pcd_set_ep_address(USB, epnum, epnum); + pcd_set_ep_address(USB, epnum, tu_edpt_number(p_endpoint_desc->bEndpointAddress)); // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint) // or being double-buffered (bulk endpoints) pcd_clear_ep_kind(USB,0); @@ -861,7 +863,7 @@ void dcd_edpt_close_all (uint8_t rhport) void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) { (void)rhport; - uint32_t const epnum = tu_edpt_number(ep_addr); + uint32_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr); uint32_t const dir = tu_edpt_dir(ep_addr); if(dir == TUSB_DIR_IN) @@ -907,7 +909,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t { (void) rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir); @@ -945,7 +947,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 { (void) rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir); @@ -976,13 +978,16 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) { (void)rhport; - if (ep_addr & 0x80) + uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if (dir == TUSB_DIR_IN) { // IN - pcd_set_ep_tx_status(USB, ep_addr & 0x7F, USB_EP_TX_STALL); + pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_STALL); } else { // OUT - pcd_set_ep_rx_status(USB, ep_addr, USB_EP_RX_STALL); + pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_STALL); } } @@ -990,24 +995,23 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) { (void)rhport; - if (ep_addr & 0x80) - { // IN - ep_addr &= 0x7F; + uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); - uint8_t const epnum = tu_edpt_number(ep_addr); + if (dir == TUSB_DIR_IN) + { // IN if (pcd_get_eptype(USB, epnum) != USB_EP_ISOCHRONOUS) { - pcd_set_ep_tx_status(USB,ep_addr, USB_EP_TX_NAK); + pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_NAK); } /* Reset to DATA0 if clearing stall condition. */ - pcd_clear_tx_dtog(USB,ep_addr); + pcd_clear_tx_dtog(USB, epnum); } else { // OUT /* Reset to DATA0 if clearing stall condition. */ - pcd_clear_rx_dtog(USB,ep_addr); - - pcd_set_ep_rx_status(USB,ep_addr, USB_EP_RX_NAK); + pcd_clear_rx_dtog(USB, epnum); + pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK); } } diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 40c4003c5..5d26d3525 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -117,6 +117,15 @@ // Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden) static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR; +// This array maps the endpoint address to a endpoint register in hardware +// By default the tinyusb stack chooses the endpoint register using the endpoint number +// However when using ISOCHRONOUS endpoints, the entire endpoint register (RX _and_ TX) +// are used for a double buffer in a single direction. If you now want to use the same endpoint number with +// different directions (e.g. 0x02 and 0x82), they would be mapped to the same register +// In this case, this serves as a crude helper to overcome this limitation by implementing +// this callback and defining a custom mapping in your application +TU_ATTR_WEAK uint8_t tu_stm32_edpt_number_cb(uint8_t addr); + // prototypes static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum); static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum); -- cgit v1.3.1 From 8c0388f477839810260f578922f17a5197294cc1 Mon Sep 17 00:00:00 2001 From: Simon Kueppers Date: Mon, 24 Oct 2022 22:39:38 +0200 Subject: Fixed wrongly enabling RX and TX status simultaneously on ISOCHRONOUS endpoints --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 73fecb750..d2fefde82 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -818,12 +818,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr; pcd_set_ep_tx_cnt(USB, epnum, epMaxPktSize); pcd_clear_tx_dtog(USB, epnum); - - if(wType == USB_EP_ISOCHRONOUS) { - pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS); - } else { - pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_NAK); - } } #if defined(ISOCHRONOUS_DOUBLEBUFFER) if( (dir == TUSB_DIR_OUT) || (wType == USB_EP_ISOCHRONOUS) ) @@ -834,7 +828,18 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr; pcd_set_ep_rx_cnt(USB, epnum, epMaxPktSize); pcd_clear_rx_dtog(USB, epnum); + } + /* Enable endpoint */ + if (dir == TUSB_DIR_IN) + { + if(wType == USB_EP_ISOCHRONOUS) { + pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS); + } else { + pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_NAK); + } + } else + { if(wType == USB_EP_ISOCHRONOUS) { pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS); } else { -- cgit v1.3.1 From abf53f927067f84d057d54e31d44d5fc40c76cf7 Mon Sep 17 00:00:00 2001 From: Simon Kueppers Date: Tue, 25 Oct 2022 17:45:04 +0200 Subject: Changed indirection from actual endpoint address to hardware endpoint through lookup table. Allocation of endpoint is now only performed in dcd_edpt_open --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 71 ++++++++++++++------------- 1 file changed, 38 insertions(+), 33 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index d2fefde82..7ebaa826c 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -169,12 +169,17 @@ typedef struct uint16_t pma_ptr; uint8_t max_packet_size; uint8_t pma_alloc_size; + uint8_t epnum; } xfer_ctl_t; static xfer_ctl_t xfer_status[MAX_EP_COUNT][2]; -static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t epnum, uint32_t dir) +static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr) { + uint8_t epnum = tu_edpt_number(ep_addr); + uint8_t dir = tu_edpt_dir(ep_addr); + TU_ASSERT(epnum < MAX_EP_COUNT); + return &xfer_status[epnum][dir]; } @@ -461,6 +466,7 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr) { uint32_t EPindex = wIstr & USB_ISTR_EP_ID; uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex); + uint8_t ep_addr = (wEPRegVal & USB_EPADDR_FIELD) | TUSB_DIR_IN_MASK; // Verify the CTR_TX bit is set. This was in the ST Micro code, // but I'm not sure it's actually necessary? @@ -472,15 +478,14 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr) /* clear int flag */ pcd_clear_tx_ep_ctr(USB, EPindex); - xfer_ctl_t * xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_IN); + xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr); if((xfer->total_len != xfer->queued_len)) /* TX not complete */ { dcd_transmit_packet(xfer, EPindex); } else /* TX Complete */ { - uint8_t ep_addr = wEPRegVal & USB_EPADDR_FIELD; - dcd_event_xfer_complete(0, (uint8_t)(TUSB_DIR_IN_MASK | ep_addr), xfer->total_len, XFER_RESULT_SUCCESS, true); + dcd_event_xfer_complete(0, ep_addr, xfer->total_len, XFER_RESULT_SUCCESS, true); } } @@ -492,8 +497,9 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) uint32_t EPindex = wIstr & USB_ISTR_EP_ID; uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex); uint32_t count = pcd_get_ep_rx_cnt(USB,EPindex); + uint8_t ep_addr = wEPRegVal & USB_EPADDR_FIELD; - xfer_ctl_t *xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_OUT); + xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr); // Verify the CTR_RX bit is set. This was in the ST Micro code, // but I'm not sure it's actually necessary? @@ -544,7 +550,6 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) { /* RX COMPLETE */ - uint8_t ep_addr = wEPRegVal & USB_EPADDR_FIELD; dcd_event_xfer_complete(0, ep_addr, xfer->queued_len, XFER_RESULT_SUCCESS, true); // Though the host could still send, we don't know. // Does the bulk pipe need to be reset to valid to allow for a ZLP? @@ -690,10 +695,10 @@ static void dcd_pma_alloc_reset(void) //TU_LOG2("dcd_pma_alloc_reset()\r\n"); for(uint32_t i=0; ipma_alloc_size = 0U; - xfer_ctl_ptr(i,TUSB_DIR_IN)->pma_alloc_size = 0U; - xfer_ctl_ptr(i,TUSB_DIR_OUT)->pma_ptr = 0U; - xfer_ctl_ptr(i,TUSB_DIR_IN)->pma_ptr = 0U; + xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_OUT))->pma_alloc_size = 0U; + xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_IN))->pma_alloc_size = 0U; + xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_OUT))->pma_ptr = 0U; + xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_IN))->pma_ptr = 0U; } } @@ -708,11 +713,8 @@ static void dcd_pma_alloc_reset(void) */ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length) { - uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - xfer_ctl_t* epXferCtl = xfer_ctl_ptr(epnum,dir); + xfer_ctl_t* epXferCtl = xfer_ctl_ptr(ep_addr); - open_ep_count++; if(epXferCtl->pma_alloc_size != 0U) { //TU_LOG2("dcd_pma_alloc(%x,%x)=%x (cached)\r\n",ep_addr,length,epXferCtl->pma_ptr); @@ -739,12 +741,9 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length) */ static void dcd_pma_free(uint8_t ep_addr) { - uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - // Presently, this should never be called for EP0 IN/OUT TU_ASSERT(open_ep_count > 2, /**/); - TU_ASSERT(xfer_ctl_ptr(epnum,dir)->max_packet_size != 0, /**/); + TU_ASSERT(xfer_ctl_ptr(ep_addr)->max_packet_size != 0, /**/); open_ep_count--; // If count is 2, only EP0 should be open, so allocations can be mostly reset. @@ -756,10 +755,10 @@ static void dcd_pma_free(uint8_t ep_addr) // Skip EP0 for(uint32_t i=1; ipma_alloc_size = 0U; - xfer_ctl_ptr(i,TUSB_DIR_IN)->pma_alloc_size = 0U; - xfer_ctl_ptr(i,TUSB_DIR_OUT)->pma_ptr = 0U; - xfer_ctl_ptr(i,TUSB_DIR_IN)->pma_ptr = 0U; + xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_OUT))->pma_alloc_size = 0U; + xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_IN))->pma_alloc_size = 0U; + xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_OUT))->pma_ptr = 0U; + xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_IN))->pma_ptr = 0U; } } } @@ -770,6 +769,7 @@ static void dcd_pma_free(uint8_t ep_addr) bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { (void)rhport; + /* TODO: This hardware endpoint allocation could be more sensible. For now, simple allocation or manual allocation using callback */ uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(p_endpoint_desc->bEndpointAddress) : tu_edpt_number(p_endpoint_desc->bEndpointAddress); uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); const uint16_t epMaxPktSize = tu_edpt_packet_size(p_endpoint_desc); @@ -799,6 +799,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc TU_ASSERT(false); } + open_ep_count++; + pcd_set_eptype(USB, epnum, wType); pcd_set_ep_address(USB, epnum, tu_edpt_number(p_endpoint_desc->bEndpointAddress)); // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint) @@ -847,7 +849,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc } } - xfer_ctl_ptr(epnum, dir)->max_packet_size = epMaxPktSize; + xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = epMaxPktSize; + xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum = epnum; return true; } @@ -868,8 +871,10 @@ void dcd_edpt_close_all (uint8_t rhport) void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) { (void)rhport; - uint32_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr); - uint32_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr); + uint8_t const epnum = xfer->epnum; + uint8_t const dir = tu_edpt_dir(ep_addr); if(dir == TUSB_DIR_IN) { @@ -914,11 +919,10 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t { (void) rhport; - uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr); + xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr); + uint8_t const epnum = xfer->epnum; uint8_t const dir = tu_edpt_dir(ep_addr); - xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir); - xfer->buffer = buffer; xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API xfer->total_len = total_bytes; @@ -952,11 +956,10 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 { (void) rhport; - uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr); + xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr); + uint8_t const epnum = xfer->epnum; uint8_t const dir = tu_edpt_dir(ep_addr); - xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir); - xfer->buffer = NULL; xfer->ff = ff; // TODO support dcd_edpt_xfer_fifo API xfer->total_len = total_bytes; @@ -983,7 +986,8 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) { (void)rhport; - uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr); + xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr); + uint8_t const epnum = xfer->epnum; uint8_t const dir = tu_edpt_dir(ep_addr); if (dir == TUSB_DIR_IN) @@ -1000,7 +1004,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) { (void)rhport; - uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr); + xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr); + uint8_t const epnum = xfer->epnum; uint8_t const dir = tu_edpt_dir(ep_addr); if (dir == TUSB_DIR_IN) -- cgit v1.3.1 From ec826732fccf070b4de1369d0ee50d653689bb9c Mon Sep 17 00:00:00 2001 From: Simon Kueppers Date: Tue, 25 Oct 2022 18:32:10 +0200 Subject: Fixed non-aligned allocated memory sizes --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 11 +++--- .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 44 +++++++++++----------- 2 files changed, 26 insertions(+), 29 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 7ebaa826c..cb2b5a029 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -723,7 +723,7 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length) return epXferCtl->pma_ptr; } - uint16_t addr = ep_buf_ptr; + uint16_t addr = ep_buf_ptr; ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer // Verify no overflow @@ -772,7 +772,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc /* TODO: This hardware endpoint allocation could be more sensible. For now, simple allocation or manual allocation using callback */ uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(p_endpoint_desc->bEndpointAddress) : tu_edpt_number(p_endpoint_desc->bEndpointAddress); uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); - const uint16_t epMaxPktSize = tu_edpt_packet_size(p_endpoint_desc); + const uint16_t buffer_size = pcd_aligned_buffer_size(tu_edpt_packet_size(p_endpoint_desc)); uint16_t pma_addr; uint32_t wType; @@ -809,7 +809,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc /* Create a packet memory buffer area. For isochronous endpoints, * use the same buffer as the double buffer, essentially disabling double buffering */ - pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, epMaxPktSize); + pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, buffer_size); #if defined(ISOCHRONOUS_DOUBLEBUFFER) if( (dir == TUSB_DIR_IN) || (wType == USB_EP_ISOCHRONOUS) ) @@ -818,7 +818,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc #endif { *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr; - pcd_set_ep_tx_cnt(USB, epnum, epMaxPktSize); pcd_clear_tx_dtog(USB, epnum); } #if defined(ISOCHRONOUS_DOUBLEBUFFER) @@ -828,7 +827,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc #endif { *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr; - pcd_set_ep_rx_cnt(USB, epnum, epMaxPktSize); + pcd_set_ep_rx_cnt(USB, epnum, buffer_size); pcd_clear_rx_dtog(USB, epnum); } @@ -849,7 +848,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc } } - xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = epMaxPktSize; + xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = buffer_size; xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum = epnum; return true; diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 5d26d3525..17726e521 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -131,6 +131,18 @@ static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpN static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum); static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue); +/* Aligned buffer size according to hardware */ +static inline uint16_t pcd_aligned_buffer_size(uint16_t size) +{ + /* The STM32 full speed USB peripheral supports only a limited set of + * buffer sizes given by the RX buffer entry format in the USB_BTABLE. */ + uint16_t blocksize = (size > 62) ? 32 : 2; + + // Round up while dividing requested size by blocksize + uint16_t numblocks = (size + blocksize - 1) / blocksize ; + + return numblocks * blocksize; +} /* SetENDPOINT */ static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue) @@ -207,31 +219,17 @@ static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum) * @param wNBlocks no. of Blocks. * @retval None */ +static inline void pcd_set_ep_cnt_rx_reg(__O uint16_t * pdwReg, size_t wCount) +{ + /* We assume that the buffer size is already aligned to hardware requirements. */ + uint16_t blocksize = (wCount > 62) ? 1 : 0; + uint16_t numblocks = wCount / (blocksize ? 32 : 2); -static inline void pcd_set_ep_cnt_rx_reg(__O uint16_t * pdwReg, size_t wCount) { - uint32_t wNBlocks; - if(wCount > 62u) - { - wNBlocks = wCount >> 5u; - if((wCount & 0x1fU) == 0u) - { - wNBlocks--; - } - wNBlocks = wNBlocks << 10u; - wNBlocks |= 0x8000u; // Mark block size as 32byte - *pdwReg = (uint16_t)wNBlocks; - } - else - { - wNBlocks = wCount >> 1u; - if((wCount & 0x1U) != 0u) - { - wNBlocks++; - } - *pdwReg = (uint16_t)((wNBlocks) << 10u); - } -} + /* There should be no remainder in the above calculation */ + TU_VERIFY((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/); + *pdwReg = (blocksize << 15) | (numblocks << 10); +} /** * @brief Sets address in an endpoint register. -- cgit v1.3.1 From 9a8439087864e2c1e19412fb5ce329cf720f5005 Mon Sep 17 00:00:00 2001 From: Simon Kueppers Date: Tue, 25 Oct 2022 18:39:09 +0200 Subject: Changed comments, added define to fail if ISOCHRONOUS endpoint is not available but requested --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index cb2b5a029..736150fcd 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -64,10 +64,9 @@ * - STALL handled, but not tested. * - Does it work? No clue. * - All EP BTABLE buffers are created based on max packet size of first EP opened with that address. - * - No isochronous endpoints * - Endpoint index is the ID of the endpoint * - This means that priority is given to endpoints with lower ID numbers - * - Code is mixing up EP IX with EP ID. Everywhere. + * - Manual override of this mapping is possible through callback * - Packet buffer memory is copied in the interrupt. * - This is better for performance, but means interrupts are disabled for longer * - DMA may be the best choice, but it could also be pushed to the USBD task. @@ -776,17 +775,19 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc uint16_t pma_addr; uint32_t wType; - // Isochronous not supported (yet), and some other driver assumptions. TU_ASSERT(epnum < MAX_EP_COUNT); + TU_ASSERT(buffer_size <= 1024); // Set type switch(p_endpoint_desc->bmAttributes.xfer) { case TUSB_XFER_CONTROL: wType = USB_EP_CONTROL; break; +#if defined(ISOCHRONOUS_DOUBLEBUFFER) case TUSB_XFER_ISOCHRONOUS: wType = USB_EP_ISOCHRONOUS; break; +#endif case TUSB_XFER_BULK: wType = USB_EP_CONTROL; break; -- cgit v1.3.1 From 510720b396eaa610e6ae688d5f46198de4aaee29 Mon Sep 17 00:00:00 2001 From: Simon Kueppers Date: Thu, 27 Oct 2022 18:51:16 +0200 Subject: Renamed pcd_set_ep_rx_cnt because it actually sets the maximum buffer size --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 16 ++++++++-------- src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 10 +++++++++- 2 files changed, 17 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 736150fcd..9ec8ef592 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -557,9 +557,9 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) { uint32_t remaining = (uint32_t)xfer->total_len - (uint32_t)xfer->queued_len; if(remaining >= xfer->max_packet_size) { - pcd_set_ep_rx_cnt(USB, EPindex,xfer->max_packet_size); + pcd_set_ep_rx_bufsize(USB, EPindex,xfer->max_packet_size); } else { - pcd_set_ep_rx_cnt(USB, EPindex,remaining); + pcd_set_ep_rx_bufsize(USB, EPindex,remaining); } pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID); } @@ -571,7 +571,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) if(EPindex == 0u) { // Always be prepared for a status packet... - pcd_set_ep_rx_cnt(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE); + pcd_set_ep_rx_bufsize(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE); pcd_clear_rx_ep_ctr(USB, EPindex); } } @@ -828,7 +828,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc #endif { *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr; - pcd_set_ep_rx_cnt(USB, epnum, buffer_size); + pcd_set_ep_rx_bufsize(USB, epnum, buffer_size); pcd_clear_rx_dtog(USB, epnum); } @@ -939,9 +939,9 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t if(total_bytes > xfer->max_packet_size) { - pcd_set_ep_rx_cnt(USB,epnum,xfer->max_packet_size); + pcd_set_ep_rx_bufsize(USB,epnum,xfer->max_packet_size); } else { - pcd_set_ep_rx_cnt(USB,epnum,total_bytes); + pcd_set_ep_rx_bufsize(USB,epnum,total_bytes); } pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_VALID); } @@ -969,9 +969,9 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 { if(total_bytes > xfer->max_packet_size) { - pcd_set_ep_rx_cnt(USB,epnum,xfer->max_packet_size); + pcd_set_ep_rx_bufsize(USB,epnum,xfer->max_packet_size); } else { - pcd_set_ep_rx_cnt(USB,epnum,total_bytes); + pcd_set_ep_rx_bufsize(USB,epnum,total_bytes); } pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_VALID); } diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 17726e521..3130953b4 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -276,12 +276,20 @@ static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpN static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) { - *pcd_ep_tx_cnt_ptr(USBx, bEpNum) = (uint16_t)wCount; + __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpNum); + *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU); } static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) +{ + __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpNum); + *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU); +} + +static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) { __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpNum)); + wCount = pcd_aligned_buffer_size(wCount); pcd_set_ep_cnt_rx_reg(pdwReg, wCount); } -- cgit v1.3.1 From d584b07e2c8068a51c89421be2ddc116f4fc9d3e Mon Sep 17 00:00:00 2001 From: Simon Kueppers Date: Thu, 27 Oct 2022 19:09:48 +0200 Subject: Fixed problem where the transmit byte count was written into the wrong register on ISOCHRONOUS endpoints --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 9ec8ef592..36548975e 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -899,19 +899,26 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix) len = xfer->max_packet_size; } - uint16_t oldAddr = *pcd_ep_tx_address_ptr(USB,ep_ix); + uint16_t ep_reg = pcd_get_endpoint(USB, ep_ix); + uint16_t addr_ptr = *pcd_ep_tx_address_ptr(USB,ep_ix); if (xfer->ff) { - dcd_write_packet_memory_ff(xfer->ff, oldAddr, len); + dcd_write_packet_memory_ff(xfer->ff, addr_ptr, len); } else { - dcd_write_packet_memory(oldAddr, &(xfer->buffer[xfer->queued_len]), len); + dcd_write_packet_memory(addr_ptr, &(xfer->buffer[xfer->queued_len]), len); } xfer->queued_len = (uint16_t)(xfer->queued_len + len); - pcd_set_ep_tx_cnt(USB,ep_ix,len); + /* Write into correct register when ISOCHRONOUS (double buffered) */ + if ( (ep_reg & USB_EP_DTOG_TX) && ( (ep_reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) ) { + pcd_set_ep_rx_cnt(USB, ep_ix, len); + } else { + pcd_set_ep_tx_cnt(USB, ep_ix, len); + } + pcd_set_ep_tx_status(USB, ep_ix, USB_EP_TX_VALID); } -- cgit v1.3.1 From b4b619abd6badd664149604c77a0bb05ea579f86 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Thu, 29 Dec 2022 12:29:28 +0100 Subject: SHA-1: 5cb3ed518301e2237ee4e468e97e51ece0ba3838 * Correct handling of SOF interrupt --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index ee188b65c..ae22bb455 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -149,12 +149,6 @@ # define DCD_STM32_BTABLE_LENGTH (PMA_LENGTH - DCD_STM32_BTABLE_BASE) #endif -// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) -// We disable SOF for now until needed later on -#ifndef USE_SOF -# define USE_SOF 0 -#endif - /*************************************************** * Checks, structs, defines, function definitions, etc. */ @@ -259,7 +253,7 @@ void dcd_init (uint8_t rhport) pcd_set_endpoint(USB,i,0u); } - USB->CNTR |= USB_CNTR_RESETM | (USE_SOF ? USB_CNTR_SOFM : 0) | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM; + USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM; dcd_handle_bus_reset(); // Enable pull-up if supported @@ -304,7 +298,14 @@ void dcd_sof_enable(uint8_t rhport, bool en) (void) rhport; (void) en; - // TODO implement later + if (en) + { + USB->CNTR |= USB_CNTR_SOFM; + } + else + { + USB->CNTR &= (uint16_t) ~USB_CNTR_SOFM; + } } // Enable device interrupt @@ -655,12 +656,10 @@ void dcd_int_handler(uint8_t rhport) { dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); } -#if USE_SOF if(int_status & USB_ISTR_SOF) { clear_istr_bits(USB_ISTR_SOF); - dcd_event_bus_signal(0, DCD_EVENT_SOF, true); + dcd_event_sof(0, USB->FNR & USB_FNR_FN, true); } -#endif if(int_status & USB_ISTR_ESOF) { if(remoteWakeCountdown == 1u) -- cgit v1.3.1 From 9ec21248d7f11e14f5011ea015c5ecfba8e0632b Mon Sep 17 00:00:00 2001 From: Simon Kueppers Date: Mon, 31 Oct 2022 13:42:52 +0100 Subject: Fixed various small problems and inaccuracies regarding ISOCHRONOUS endpoint --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 16 ++++++++++++---- src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 9 +++++---- 2 files changed, 17 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index ae22bb455..8e8ffec76 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -506,7 +506,6 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) { uint32_t EPindex = wIstr & USB_ISTR_EP_ID; uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex); - uint32_t count = pcd_get_ep_rx_cnt(USB,EPindex); uint8_t ep_addr = wEPRegVal & USB_EPADDR_FIELD; xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr); @@ -518,11 +517,12 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) return; } - if((EPindex == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) /* Setup packet */ + if((ep_addr == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) /* Setup packet */ { // The setup_received function uses memcpy, so this must first copy the setup data into // user memory, to allow for the 32-bit access that memcpy performs. uint8_t userMemBuf[8]; + uint32_t count = pcd_get_ep_rx_cnt(USB, EPindex); /* Get SETUP Packet*/ if(count == 8) // Setup packet should always be 8 bytes. If not, ignore it, and try again. { @@ -535,8 +535,16 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) } else { + uint32_t count; + /* Read from correct register when ISOCHRONOUS (double buffered) */ + if ( (wEPRegVal & USB_EP_DTOG_RX) && ( (wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) ) { + count = pcd_get_ep_tx_cnt(USB, EPindex); + } else { + count = pcd_get_ep_rx_cnt(USB, EPindex); + } + // Clear RX CTR interrupt flag - if(EPindex != 0u) + if(ep_addr != 0u) { pcd_clear_rx_ep_ctr(USB, EPindex); } @@ -579,7 +587,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) // For EP0, prepare to receive another SETUP packet. // Clear CTR last so that a new packet does not overwrite the packing being read. // (Based on the docs, it seems SETUP will always be accepted after CTR is cleared) - if(EPindex == 0u) + if(ep_addr == 0u) { // Always be prepared for a status packet... pcd_set_ep_rx_bufsize(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE); diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 8acce3c71..8ea659124 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -223,16 +223,17 @@ static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum) * @param wNBlocks no. of Blocks. * @retval None */ -static inline void pcd_set_ep_cnt_rx_reg(__O uint16_t * pdwReg, size_t wCount) +static inline void pcd_set_ep_cnt_reg(__O uint16_t * pdwReg, size_t wCount) { /* We assume that the buffer size is already aligned to hardware requirements. */ uint16_t blocksize = (wCount > 62) ? 1 : 0; uint16_t numblocks = wCount / (blocksize ? 32 : 2); /* There should be no remainder in the above calculation */ - TU_VERIFY((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/); + TU_ASSERT((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/); - *pdwReg = (blocksize << 15) | (numblocks << 10); + /* Encode into register. When BLSIZE==1, we need to substract 1 block count */ + *pdwReg = (blocksize << 15) | ((numblocks - blocksize) << 10); } /** @@ -294,7 +295,7 @@ static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpNum, u { __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpNum)); wCount = pcd_aligned_buffer_size(wCount); - pcd_set_ep_cnt_rx_reg(pdwReg, wCount); + pcd_set_ep_cnt_reg(pdwReg, wCount); } /** -- cgit v1.3.1 From 76413a95d4463d11232810e42d4f1a64a30aed2b Mon Sep 17 00:00:00 2001 From: Simon Kueppers Date: Mon, 31 Oct 2022 13:47:24 +0100 Subject: Added TU_ATTR_ALWAYS_INLINE to all static inline functions --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 6 +-- .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 63 +++++++++++----------- 2 files changed, 35 insertions(+), 34 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 8e8ffec76..fefa7a330 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -175,7 +175,7 @@ typedef struct static xfer_ctl_t xfer_status[MAX_EP_COUNT][2]; -static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr) +TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr) { uint8_t epnum = tu_edpt_number(ep_addr); uint8_t dir = tu_edpt_dir(ep_addr); @@ -207,12 +207,12 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB // Using a function due to better type checks // This seems better than having to do type casts everywhere else -static inline void reg16_clear_bits(__IO uint16_t *reg, uint16_t mask) { +TU_ATTR_ALWAYS_INLINE static inline void reg16_clear_bits(__IO uint16_t *reg, uint16_t mask) { *reg = (uint16_t)(*reg & ~mask); } // Bits in ISTR are cleared upon writing 0 -static inline void clear_istr_bits(uint16_t mask) { +TU_ATTR_ALWAYS_INLINE static inline void clear_istr_bits(uint16_t mask) { USB->ISTR = ~mask; } diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 8ea659124..d6f10c5a9 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -131,12 +131,12 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR; TU_ATTR_WEAK uint8_t tu_stm32_edpt_number_cb(uint8_t addr); // prototypes -static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum); -static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum); -static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue); +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum); +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum); +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue); /* Aligned buffer size according to hardware */ -static inline uint16_t pcd_aligned_buffer_size(uint16_t size) +TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size) { /* The STM32 full speed USB peripheral supports only a limited set of * buffer sizes given by the RX buffer entry format in the USB_BTABLE. */ @@ -149,19 +149,19 @@ static inline uint16_t pcd_aligned_buffer_size(uint16_t size) } /* SetENDPOINT */ -static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue) { __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpNum*2u); *reg = (uint16_t)wRegValue; } /* GetENDPOINT */ -static inline uint16_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpNum) { +TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpNum) { __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpNum*2u); return *reg; } -static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wType) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wType) { uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); regVal &= (uint32_t)USB_EP_T_MASK; @@ -170,7 +170,7 @@ static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t pcd_set_endpoint(USBx, bEpNum, regVal); } -static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpNum) { uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); regVal &= USB_EP_T_FIELD; @@ -182,7 +182,7 @@ static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpNum) * @param bEpNum Endpoint Number. * @retval None */ -static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum) { uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); regVal &= USB_EPREG_MASK; @@ -190,7 +190,8 @@ static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum) regVal |= USB_EP_CTR_TX; // preserve CTR_TX (clears on writing 0) pcd_set_endpoint(USBx, bEpNum, regVal); } -static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum) + +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum) { uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); regVal &= USB_EPREG_MASK; @@ -204,13 +205,13 @@ static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum) * @param bEpNum Endpoint Number. * @retval Counter value */ -static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum) { __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpNum); return *regPtr & 0x3ffU; } -static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum) { __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpNum); return *regPtr & 0x3ffU; @@ -223,7 +224,7 @@ static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum) * @param wNBlocks no. of Blocks. * @retval None */ -static inline void pcd_set_ep_cnt_reg(__O uint16_t * pdwReg, size_t wCount) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_cnt_reg(__O uint16_t * pdwReg, size_t wCount) { /* We assume that the buffer size is already aligned to hardware requirements. */ uint16_t blocksize = (wCount > 62) ? 1 : 0; @@ -243,7 +244,7 @@ static inline void pcd_set_ep_cnt_reg(__O uint16_t * pdwReg, size_t wCount) * @param bAddr Address. * @retval None */ -static inline void pcd_set_ep_address(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t bAddr) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t bAddr) { uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); regVal &= USB_EPREG_MASK; @@ -252,7 +253,7 @@ static inline void pcd_set_ep_address(USB_TypeDef * USBx, uint32_t bEpNum, uint pcd_set_endpoint(USBx, bEpNum,regVal); } -static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) { size_t total_word_offset = (((USBx)->BTABLE)>>1) + x; total_word_offset *= PMA_STRIDE; @@ -260,38 +261,38 @@ static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) } // Pointers to the PMA table entries (using the ARM address space) -static inline __IO uint16_t* pcd_ep_tx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum) { return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 0u); } -static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum) { return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 1u); } -static inline __IO uint16_t* pcd_ep_rx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum) { return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 2u); } -static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum) { return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 3u); } -static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) { __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpNum); *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU); } -static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) { __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpNum); *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU); } -static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) { __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpNum)); wCount = pcd_aligned_buffer_size(wCount); @@ -305,7 +306,7 @@ static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpNum, u * @param wState new state * @retval None */ -static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wState) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wState) { uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); regVal &= USB_EPTX_DTOGMASK; @@ -332,7 +333,7 @@ static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpNum, ui * @retval None */ -static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wState) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wState) { uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); regVal &= USB_EPRX_DTOGMASK; @@ -351,7 +352,7 @@ static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpNum, ui pcd_set_endpoint(USBx, bEpNum, regVal); } /* pcd_set_ep_rx_status */ -static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpNum) { uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); return (regVal & USB_EPRX_STAT) >> (12u); @@ -364,7 +365,7 @@ static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpNum * @param bEpNum Endpoint Number. * @retval None */ -static inline void pcd_rx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) { uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); regVal &= USB_EPREG_MASK; @@ -372,7 +373,7 @@ static inline void pcd_rx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) pcd_set_endpoint(USBx, bEpNum, regVal); } -static inline void pcd_tx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) { uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); regVal &= USB_EPREG_MASK; @@ -387,7 +388,7 @@ static inline void pcd_tx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) * @retval None */ -static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) { uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); if((regVal & USB_EP_DTOG_RX) != 0) @@ -396,7 +397,7 @@ static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) } } -static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) { uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); if((regVal & USB_EP_DTOG_TX) != 0) @@ -412,7 +413,7 @@ static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) * @retval None */ -static inline void pcd_set_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum) { uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); regVal |= USB_EP_KIND; @@ -420,7 +421,7 @@ static inline void pcd_set_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum) regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; pcd_set_endpoint(USBx, bEpNum, regVal); } -static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum) { uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); regVal &= USB_EPKIND_MASK; -- cgit v1.3.1 From 1d37f5ef9b94d53d8a90b73934913aa4252011e5 Mon Sep 17 00:00:00 2001 From: Simon Kueppers Date: Sun, 6 Nov 2022 12:40:14 +0100 Subject: Added improvements with regards to SOF timing jitter --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 12 +++++++----- src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 3 +++ 2 files changed, 10 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index fefa7a330..d6ca59756 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -627,6 +627,13 @@ void dcd_int_handler(uint8_t rhport) { // dcd_ep_ctr_handler(), so less need to loop here. The other interrupts shouldn't // be triggered repeatedly. + /* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */ + if(int_status & USB_ISTR_SOF) { + clear_istr_bits(USB_ISTR_SOF); + if (tu_stm32_sof_cb) tu_stm32_sof_cb(); + dcd_event_sof(0, USB->FNR & USB_FNR_FN, true); + } + if(int_status & USB_ISTR_RESET) { // USBRST is start of reset. clear_istr_bits(USB_ISTR_RESET); @@ -664,11 +671,6 @@ void dcd_int_handler(uint8_t rhport) { dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); } - if(int_status & USB_ISTR_SOF) { - clear_istr_bits(USB_ISTR_SOF); - dcd_event_sof(0, USB->FNR & USB_FNR_FN, true); - } - if(int_status & USB_ISTR_ESOF) { if(remoteWakeCountdown == 1u) { diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index d6f10c5a9..40af9b3a5 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -130,6 +130,9 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR; // this callback and defining a custom mapping in your application TU_ATTR_WEAK uint8_t tu_stm32_edpt_number_cb(uint8_t addr); +// This callback is called on SOF and can be used to e.g. capture a timer value for timing purposes +TU_ATTR_WEAK void tu_stm32_sof_cb(void); + // prototypes TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum); TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum); -- cgit v1.3.1 From 17990025bbe9017eb5a8b636cbf5345a58812587 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Wed, 28 Dec 2022 17:14:23 +0100 Subject: dcd_stm32_fsdev : Fix index out of bound in dcd_write_packet_memory() If src is odd then src[wNBytes] is accessed. --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index d6ca59756..e5006809d 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -1064,8 +1064,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) */ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes) { - uint32_t n = ((uint32_t)wNBytes + 1U) >> 1U; - uint32_t i; + uint32_t n = (uint32_t)wNBytes >> 1U; uint16_t temp1, temp2; const uint8_t * srcVal; @@ -1076,15 +1075,22 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si srcVal = src; pdwVal = &pma[PMA_STRIDE*(dst>>1)]; - for (i = n; i != 0; i--) + while (n--) { - temp1 = (uint16_t) *srcVal; + temp1 = (uint16_t)*srcVal; srcVal++; - temp2 = temp1 | ((uint16_t)((uint16_t) ((*srcVal) << 8U))) ; + temp2 = temp1 | ((uint16_t)(((uint16_t)(*srcVal)) << 8U)) ; *pdwVal = temp2; pdwVal += PMA_STRIDE; srcVal++; } + + if (wNBytes & 0x01) + { + temp1 = *srcVal; + *pdwVal = temp2; + } + return true; } @@ -1141,7 +1147,6 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes) { uint32_t n = (uint32_t)wNBytes >> 1U; - uint32_t i; // The GCC optimizer will combine access to 32-bit sizes if we let it. Force // it volatile so that it won't do that. __IO const uint16_t *pdwVal; @@ -1150,7 +1155,7 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN pdwVal = &pma[PMA_STRIDE*(src>>1)]; uint8_t *dstVal = (uint8_t*)dst; - for (i = n; i != 0U; i--) + while (n--) { temp = *pdwVal; pdwVal += PMA_STRIDE; -- cgit v1.3.1 From b156a8b78c5ede08849bd30a05c4e43ac211b068 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Wed, 28 Dec 2022 17:16:49 +0100 Subject: dcd_stm32_fsdev : Implement FIFO transfer correctly. --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 109 +++++++++++++++----------- 1 file changed, 64 insertions(+), 45 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index e5006809d..e259991ae 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -6,6 +6,8 @@ * Portions: * Copyright (c) 2016 STMicroelectronics * Copyright (c) 2019 Ha Thach (tinyusb.org) + * Copyright (c) 2022 Simon Kppers (skuep) + * Copyright (c) 2022 HiFiPhile * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -987,7 +989,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 uint8_t const dir = tu_edpt_dir(ep_addr); xfer->buffer = NULL; - xfer->ff = ff; // TODO support dcd_edpt_xfer_fifo API + xfer->ff = ff; xfer->total_len = total_bytes; xfer->queued_len = 0; @@ -1088,7 +1090,7 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si if (wNBytes & 0x01) { temp1 = *srcVal; - *pdwVal = temp2; + *pdwVal = temp1; } return true; @@ -1100,41 +1102,47 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si * @param wNBytes no. of bytes to be copied. * @retval None */ - -// THIS FUNCTION IS UNTESTED - static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wNBytes) { // Since we copy from a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies - // Check for first linear part tu_fifo_buffer_info_t info; - tu_fifo_get_read_info(ff, &info); // We want to read from the FIFO - TU_VERIFY(info.len_lin && dcd_write_packet_memory(dst, info.ptr_lin, info.len_lin)); // and write it into the PMA - tu_fifo_advance_read_pointer(ff, info.len_lin); + tu_fifo_get_read_info(ff, &info); + + uint16_t cnt_lin = TU_MIN(wNBytes, info.len_lin); + uint16_t cnt_wrap = TU_MIN(wNBytes - cnt_lin, info.len_wrap); + + // We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part, + // last lin byte will be combined with wrapped part + // To ensure PMA is always access 16bit aligned (dst aligned to 16 bit) + if((cnt_lin & 0x01) && cnt_wrap) + { + // Copy first linear part + dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin &~0x01); + dst += cnt_lin &~0x01; + + // Copy last linear byte & first wrapped byte + uint16_t tmp = ((uint8_t*)info.ptr_lin)[cnt_lin - 1] | ((uint16_t)(((uint8_t*)info.ptr_wrap)[0]) << 8U); + dcd_write_packet_memory(dst, &tmp, 2); + dst += 2; - // Check for wrapped part - if (info.len_wrap) + // Copy rest of wrapped byte + dcd_write_packet_memory(dst, ((uint8_t*)info.ptr_wrap) + 1, cnt_wrap - 1); + } + else { - // Update destination pointer + // Copy linear part + dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin); dst += info.len_lin; - uint8_t* src = (uint8_t*)info.ptr_wrap; - uint16_t len2 = info.len_wrap; - // Since PMA is accessed 16-bit wise we need to handle the case when a 16 bit value was split - if (info.len_lin % 2) // If len is uneven there is a byte left to copy + if(info.len_wrap) { - TU_ASSERT(false); // TODO: Step through and check -> untested - - uint16_t temp = ((uint8_t *)info.ptr_lin)[info.len_lin-1] | src[0] << 16; // CHECK endianess - pma[PMA_STRIDE*(dst>>1)] = temp; - src++; - len2--; + // Copy wrapped byte + dcd_write_packet_memory(dst, info.ptr_wrap, cnt_wrap); } - - TU_VERIFY(dcd_write_packet_memory(dst, src, len2)); - tu_fifo_advance_write_pointer(ff, info.len_wrap); } + tu_fifo_advance_read_pointer(ff, cnt_lin + cnt_wrap); + return true; } @@ -1178,9 +1186,6 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN * @param wNBytes no. of bytes to be copied. * @retval None */ - -// THIS FUNCTION IS UNTESTED - static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNBytes) { // Since we copy into a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies @@ -1188,30 +1193,44 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB tu_fifo_buffer_info_t info; tu_fifo_get_write_info(ff, &info); // We want to read from the FIFO - TU_VERIFY(info.len_lin && dcd_read_packet_memory(info.ptr_lin, src, info.len_lin)); - tu_fifo_advance_write_pointer(ff, info.len_lin); + uint16_t cnt_lin = TU_MIN(wNBytes, info.len_lin); + uint16_t cnt_wrap = TU_MIN(wNBytes - cnt_lin, info.len_wrap); - // Check for wrapped part - if (info.len_wrap) + // We want to read from PMA and write it into the FIFO, if LIN part is ODD and has WRAPPED part, + // last lin byte will be combined with wrapped part + // To ensure PMA is always access 16bit aligned (src aligned to 16 bit) + if((cnt_lin & 0x01) && cnt_wrap) { - // Update source pointer - src += info.len_lin; + // Copy first linear part + dcd_read_packet_memory(info.ptr_lin, src, cnt_lin &~0x01); + src += cnt_lin &~0x01; + + // Copy last linear byte & first wrapped byte + uint16_t tmp; + dcd_read_packet_memory(&tmp, src, 2); + + ((uint8_t*)info.ptr_lin)[cnt_lin - 1] = (uint8_t)tmp; + ((uint8_t*)info.ptr_wrap)[0] = (uint8_t)(tmp >> 8U); + src += 2; + + // Copy rest of wrapped byte + dcd_read_packet_memory(((uint8_t*)info.ptr_wrap) + 1, src, cnt_wrap - 1); + } + else + { + // Copy linear part + dcd_read_packet_memory(info.ptr_lin, src, cnt_lin); + src += cnt_lin; - // Since PMA is accessed 16-bit wise we need to handle the case when a 16 bit value was split - if (info.len_lin % 2) // If len is uneven there is a byte left to copy + if(info.len_wrap) { - TU_ASSERT(false); //TODO: step through -> untested - uint32_t temp = pma[PMA_STRIDE*(src>>1)]; - *((uint8_t *)info.ptr_wrap++) = ((temp >> 8) & 0xFF); - src++; - tu_fifo_advance_write_pointer(ff, 1); - info.len_wrap--; + // Copy wrapped byte + dcd_read_packet_memory(info.ptr_wrap, src, cnt_wrap); } - - TU_VERIFY(dcd_read_packet_memory(info.ptr_wrap, src, info.len_wrap)); - tu_fifo_advance_write_pointer(ff, info.len_wrap); } + tu_fifo_advance_write_pointer(ff, cnt_lin + cnt_wrap); + return true; } -- cgit v1.3.1 From ef2f17a514fb0967261c3a8308af017b5d911e15 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Wed, 28 Dec 2022 23:45:10 +0100 Subject: Add hardware endpoint allocator. --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 97 +++++++++++++++++++++++++-- 1 file changed, 90 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index e259991ae..0d566da12 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -66,9 +66,6 @@ * - STALL handled, but not tested. * - Does it work? No clue. * - All EP BTABLE buffers are created based on max packet size of first EP opened with that address. - * - Endpoint index is the ID of the endpoint - * - This means that priority is given to endpoints with lower ID numbers - * - Manual override of this mapping is possible through callback * - Packet buffer memory is copied in the interrupt. * - This is better for performance, but means interrupts are disabled for longer * - DMA may be the best choice, but it could also be pushed to the USBD task. @@ -186,6 +183,16 @@ TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr) return &xfer_status[epnum][dir]; } +// EP allocator +typedef struct +{ + uint8_t ep_num; + uint8_t ep_type; + bool allocated[2]; +} ep_alloc_t; + +static ep_alloc_t ep_alloc_status[STFSDEV_EP_COUNT]; + static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6]; static uint8_t remoteWakeCountdown; // When wake is requested @@ -201,6 +208,8 @@ static uint16_t ep_buf_ptr; ///< Points to first free memory location static void dcd_pma_alloc_reset(void); static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length); static void dcd_pma_free(uint8_t ep_addr); +static void dcd_ep_free(uint8_t ep_addr); +static uint8_t dcd_ep_alloc(tusb_desc_endpoint_t const * p_endpoint_desc); static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes); static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes); @@ -458,10 +467,17 @@ static void dcd_handle_bus_reset(void) //__IO uint16_t * const epreg = &(EPREG(0)); USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag - // Clear all EPREG (or maybe this is automatic? I'm not sure) + for(uint32_t i=0; ibEndpointAddress); + uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); + uint8_t const eptype = p_endpoint_desc->bmAttributes.xfer; + + for(uint8_t i = 0; i < STFSDEV_EP_COUNT; i++) + { + // If EP of current direction is not allocated + // Except for ISO endpoint, both direction should be free + if(!ep_alloc_status[i].allocated[dir] && + (eptype != TUSB_XFER_ISOCHRONOUS || !ep_alloc_status[i].allocated[dir ^ 1])) + { + // Check if EP number is the same + if(ep_alloc_status[i].ep_num == 0xFF || + ep_alloc_status[i].ep_num == epnum) + { + // One EP pair has to be the same type + if(ep_alloc_status[i].ep_type == 0xFF || + ep_alloc_status[i].ep_type == eptype) + { + ep_alloc_status[i].ep_num = epnum; + ep_alloc_status[i].ep_type = eptype; + ep_alloc_status[i].allocated[dir] = true; + + return i; + } + } + } + } + + // Allocation failed + TU_ASSERT(0); +} + +/*** + * Free hardware endpoint + */ +static void dcd_ep_free(uint8_t ep_addr) +{ + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + for(uint8_t i = 0; i < STFSDEV_EP_COUNT; i++) + { + // Check if EP number & dir are the same + if(ep_alloc_status[i].ep_num == epnum && + ep_alloc_status[i].allocated[dir] == dir) + { + ep_alloc_status[i].allocated[dir] = false; + // Reset entry if ISO endpoint or both direction are free + if(ep_alloc_status[i].ep_type == TUSB_XFER_ISOCHRONOUS || + !ep_alloc_status[i].allocated[dir ^ 1]) + { + ep_alloc_status[i].ep_num = 0xFF; + ep_alloc_status[i].ep_type = 0xFF; + + return; + } + } + } +} + // The STM32F0 doesn't seem to like |= or &= to manipulate the EP#R registers, // so I'm using the #define from HAL here, instead. bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { (void)rhport; - /* TODO: This hardware endpoint allocation could be more sensible. For now, simple allocation or manual allocation using callback */ - uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(p_endpoint_desc->bEndpointAddress) : tu_edpt_number(p_endpoint_desc->bEndpointAddress); + uint8_t const epnum = dcd_ep_alloc(p_endpoint_desc); uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); const uint16_t buffer_size = pcd_aligned_buffer_size(tu_edpt_packet_size(p_endpoint_desc)); uint16_t pma_addr; uint32_t wType; - TU_ASSERT(epnum < MAX_EP_COUNT); + TU_ASSERT(epnum < STFSDEV_EP_COUNT); TU_ASSERT(buffer_size <= 1024); // Set type @@ -906,6 +987,8 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS); } + dcd_ep_free(ep_addr); + dcd_pma_free(ep_addr); } -- cgit v1.3.1 From cece59df22cdd6d07f49676ff356a781d4536245 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Thu, 29 Dec 2022 11:44:10 +0100 Subject: Generally enable ISO xfer. --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 13 ++----------- src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 2 -- 2 files changed, 2 insertions(+), 13 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 0d566da12..de8802d15 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -885,11 +885,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc case TUSB_XFER_CONTROL: wType = USB_EP_CONTROL; break; -#if defined(ISOCHRONOUS_DOUBLEBUFFER) case TUSB_XFER_ISOCHRONOUS: wType = USB_EP_ISOCHRONOUS; break; -#endif case TUSB_XFER_BULK: wType = USB_EP_CONTROL; break; @@ -914,20 +912,13 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc * use the same buffer as the double buffer, essentially disabling double buffering */ pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, buffer_size); -#if defined(ISOCHRONOUS_DOUBLEBUFFER) if( (dir == TUSB_DIR_IN) || (wType == USB_EP_ISOCHRONOUS) ) -#else - if(dir == TUSB_DIR_IN) -#endif { *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr; pcd_clear_tx_dtog(USB, epnum); } -#if defined(ISOCHRONOUS_DOUBLEBUFFER) + if( (dir == TUSB_DIR_OUT) || (wType == USB_EP_ISOCHRONOUS) ) -#else - else -#endif { *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr; pcd_set_ep_rx_bufsize(USB, epnum, buffer_size); @@ -1035,7 +1026,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t uint8_t const dir = tu_edpt_dir(ep_addr); xfer->buffer = buffer; - xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API + xfer->ff = NULL; xfer->total_len = total_bytes; xfer->queued_len = 0; diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 40af9b3a5..b64776fc9 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -66,7 +66,6 @@ defined(STM32F373xC) #include "stm32f3xx.h" #define PMA_LENGTH (512u) - #define ISOCHRONOUS_DOUBLEBUFFER // NO internal Pull-ups // *B, and *C: 1 x 16 bits/word // PMA dedicated to USB (no sharing with CAN) @@ -76,7 +75,6 @@ defined(STM32F303xD) || defined(STM32F303xE) #include "stm32f3xx.h" #define PMA_LENGTH (1024u) - #define ISOCHRONOUS_DOUBLEBUFFER // NO internal Pull-ups // *6, *8, *D, and *E: 2 x 16 bits/word LPM Support // When CAN clock is enabled, USB can use first 768 bytes ONLY. -- cgit v1.3.1 From fe8c170c98c40a2fb517cbeaa49336b5af572c0f Mon Sep 17 00:00:00 2001 From: Mengsk Date: Thu, 29 Dec 2022 19:19:27 +0100 Subject: Add dcd_edpt_iso_alloc() / dcd_edpt_iso_activate() for ISO EP buffer management. --- src/device/dcd.h | 6 +++ src/device/usbd.c | 19 +++++++ src/device/usbd_pvt.h | 6 +++ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 77 ++++++++++++++++++++++----- 4 files changed, 94 insertions(+), 14 deletions(-) (limited to 'src') diff --git a/src/device/dcd.h b/src/device/dcd.h index c1780f656..ef92d71d0 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -167,6 +167,12 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr); // This API never calls with control endpoints, since it is auto cleared when receiving setup packet void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr); +// Allocate packet buffer used by ISO endpoints +// Some MCU need manual packet buffer allocation, we allocation largest size to avoid clustering +bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size); + +// Configure and enable an ISO endpoint according to descriptor +bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc); //--------------------------------------------------------------------+ // Event API (implemented by stack) //--------------------------------------------------------------------+ diff --git a/src/device/usbd.c b/src/device/usbd.c index f652a878e..8b5e4d745 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1380,4 +1380,23 @@ void usbd_sof_enable(uint8_t rhport, bool en) dcd_sof_enable(rhport, en); } +bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) +{ + rhport = _usbd_rhport; + + TU_ASSERT(tu_edpt_number(ep_addr) < CFG_TUD_ENDPPOINT_MAX); + + return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size); +} + +bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) +{ + rhport = _usbd_rhport; + + TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < CFG_TUD_ENDPPOINT_MAX); + TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed)); + + return dcd_edpt_iso_activate(rhport, desc_ep); +} + #endif diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h index 6fad46db3..f860ab0a1 100644 --- a/src/device/usbd_pvt.h +++ b/src/device/usbd_pvt.h @@ -96,6 +96,12 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr); // Check if endpoint is stalled bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr); +// Allocate packet buffer used by ISO endpoints +bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size); + +// Configure and enable an ISO endpoint according to descriptor +bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc); + // Check if endpoint is ready (not busy and not stalled) TU_ATTR_ALWAYS_INLINE static inline bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr) diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index de8802d15..59f155111 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -209,7 +209,7 @@ static void dcd_pma_alloc_reset(void); static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length); static void dcd_pma_free(uint8_t ep_addr); static void dcd_ep_free(uint8_t ep_addr); -static uint8_t dcd_ep_alloc(tusb_desc_endpoint_t const * p_endpoint_desc); +static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type); static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes); static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes); @@ -758,13 +758,15 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length) TU_ASSERT(length <= epXferCtl->pma_alloc_size, 0xFFFF); // Verify no larger than previous alloc return epXferCtl->pma_ptr; } - + + open_ep_count++; + uint16_t addr = ep_buf_ptr; ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer - + // Verify no overflow TU_ASSERT(ep_buf_ptr <= PMA_LENGTH, 0xFFFF); - + epXferCtl->pma_ptr = addr; epXferCtl->pma_alloc_size = length; //TU_LOG2("dcd_pma_alloc(%x,%x)=%x\r\n",ep_addr,length,addr); @@ -802,18 +804,17 @@ static void dcd_pma_free(uint8_t ep_addr) /*** * Allocate hardware endpoint */ -static uint8_t dcd_ep_alloc(tusb_desc_endpoint_t const * p_endpoint_desc) +static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type) { - uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); - uint8_t const eptype = p_endpoint_desc->bmAttributes.xfer; + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); for(uint8_t i = 0; i < STFSDEV_EP_COUNT; i++) { // If EP of current direction is not allocated // Except for ISO endpoint, both direction should be free if(!ep_alloc_status[i].allocated[dir] && - (eptype != TUSB_XFER_ISOCHRONOUS || !ep_alloc_status[i].allocated[dir ^ 1])) + (ep_type != TUSB_XFER_ISOCHRONOUS || !ep_alloc_status[i].allocated[dir ^ 1])) { // Check if EP number is the same if(ep_alloc_status[i].ep_num == 0xFF || @@ -821,10 +822,10 @@ static uint8_t dcd_ep_alloc(tusb_desc_endpoint_t const * p_endpoint_desc) { // One EP pair has to be the same type if(ep_alloc_status[i].ep_type == 0xFF || - ep_alloc_status[i].ep_type == eptype) + ep_alloc_status[i].ep_type == ep_type) { ep_alloc_status[i].ep_num = epnum; - ep_alloc_status[i].ep_type = eptype; + ep_alloc_status[i].ep_type = ep_type; ep_alloc_status[i].allocated[dir] = true; return i; @@ -871,7 +872,7 @@ static void dcd_ep_free(uint8_t ep_addr) bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { (void)rhport; - uint8_t const epnum = dcd_ep_alloc(p_endpoint_desc); + uint8_t const epnum = dcd_ep_alloc(p_endpoint_desc->bEndpointAddress, p_endpoint_desc->bmAttributes.xfer); uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); const uint16_t buffer_size = pcd_aligned_buffer_size(tu_edpt_packet_size(p_endpoint_desc)); uint16_t pma_addr; @@ -900,8 +901,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc TU_ASSERT(false); } - open_ep_count++; - pcd_set_eptype(USB, epnum, wType); pcd_set_ep_address(USB, epnum, tu_edpt_number(p_endpoint_desc->bEndpointAddress)); // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint) @@ -983,6 +982,56 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) dcd_pma_free(ep_addr); } +bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) +{ + (void)rhport; + + TU_ASSERT(largest_packet_size <= 1024); + + uint8_t const epnum = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS); + const uint16_t buffer_size = pcd_aligned_buffer_size(largest_packet_size); + + /* Create a packet memory buffer area. For isochronous endpoints, + * use the same buffer as the double buffer, essentially disabling double buffering */ + dcd_pma_alloc(ep_addr, buffer_size); + + xfer_ctl_ptr(ep_addr)->epnum = epnum; + + return true; +} + +bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) +{ + (void)rhport; + uint8_t const epnum = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum; + uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); + const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc); + uint16_t pma_addr; + + /* Disable endpoint */ + pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS); + pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS); + + pcd_set_eptype(USB, epnum, USB_EP_ISOCHRONOUS); + pcd_set_ep_address(USB, epnum, tu_edpt_number(p_endpoint_desc->bEndpointAddress)); + // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint) + // or being double-buffered (bulk endpoints) + pcd_clear_ep_kind(USB,0); + + pma_addr = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->pma_ptr; + + *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr; + pcd_clear_tx_dtog(USB, epnum); + + *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr; + pcd_set_ep_rx_bufsize(USB, epnum, packet_size); + pcd_clear_rx_dtog(USB, epnum); + + xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = packet_size; + + return true; +} + // Currently, single-buffered, and only 64 bytes at a time (max) static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix) -- cgit v1.3.1 From e4f07206f8cbb177f3515f1fdbd5ed1f8cc9f668 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Thu, 29 Dec 2022 19:34:12 +0100 Subject: UAC : Enable fifo based transfer on stm32_fsdev --- src/class/audio/audio_device.c | 25 +++++++++---------------- src/device/dcd.h | 4 ++-- 2 files changed, 11 insertions(+), 18 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 698fba566..82682f162 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -76,26 +76,19 @@ // Linear buffer in case target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer // is available or driver is would need to be changed dramatically -// Only STM32 synopsys and dcd_transdimension use non-linear buffer for now -// Synopsys detection copied from dcd_synopsys.c (refactor later on) -#if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \ - defined (STM32F107xB) || defined (STM32F107xC) -#define STM32F1_SYNOPSYS -#endif - -#if defined (STM32L475xx) || defined (STM32L476xx) || \ - defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \ - defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define STM32L4_SYNOPSYS -#endif - -#if (CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_SYNOPSYS)) || \ +// Only STM32 and dcd_transdimension use non-linear buffer for now +#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || \ + CFG_TUSB_MCU == OPT_MCU_STM32F1 || \ CFG_TUSB_MCU == OPT_MCU_STM32F2 || \ + CFG_TUSB_MCU == OPT_MCU_STM32F3 || \ CFG_TUSB_MCU == OPT_MCU_STM32F4 || \ CFG_TUSB_MCU == OPT_MCU_STM32F7 || \ CFG_TUSB_MCU == OPT_MCU_STM32H7 || \ - (CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)) || \ + CFG_TUSB_MCU == OPT_MCU_STM32L0 || \ + CFG_TUSB_MCU == OPT_MCU_STM32L1 || \ + CFG_TUSB_MCU == OPT_MCU_STM32L4 || \ + CFG_TUSB_MCU == OPT_MCU_STM32G4 || \ + CFG_TUSB_MCU == OPT_MCU_STM32WB || \ CFG_TUSB_MCU == OPT_MCU_RX63X || \ CFG_TUSB_MCU == OPT_MCU_RX65X || \ CFG_TUSB_MCU == OPT_MCU_RX72N || \ diff --git a/src/device/dcd.h b/src/device/dcd.h index ef92d71d0..2980cc4e6 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -169,10 +169,10 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr); // Allocate packet buffer used by ISO endpoints // Some MCU need manual packet buffer allocation, we allocation largest size to avoid clustering -bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size); +TU_ATTR_WEAK bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size); // Configure and enable an ISO endpoint according to descriptor -bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc); +TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc); //--------------------------------------------------------------------+ // Event API (implemented by stack) //--------------------------------------------------------------------+ -- cgit v1.3.1 From 0bd41d53549183576553ec2fb84f00926c25e44c Mon Sep 17 00:00:00 2001 From: Mengsk Date: Thu, 29 Dec 2022 21:02:10 +0100 Subject: Fix CI. --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 4 ++-- src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 59f155111..f3b55cd75 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -178,7 +178,8 @@ TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr) { uint8_t epnum = tu_edpt_number(ep_addr); uint8_t dir = tu_edpt_dir(ep_addr); - TU_ASSERT(epnum < MAX_EP_COUNT); + // Fix -Werror=null-dereference + TU_ASSERT(epnum < MAX_EP_COUNT, &xfer_status[0][0]); return &xfer_status[epnum][dir]; } @@ -1004,7 +1005,6 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpo { (void)rhport; uint8_t const epnum = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum; - uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc); uint16_t pma_addr; diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index b64776fc9..382374614 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -234,7 +234,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_cnt_reg(__O uint16_t * pdwRe /* There should be no remainder in the above calculation */ TU_ASSERT((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/); - /* Encode into register. When BLSIZE==1, we need to substract 1 block count */ + /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */ *pdwReg = (blocksize << 15) | ((numblocks - blocksize) << 10); } -- cgit v1.3.1 From db65759b1eb24c8dc20dfd77f2ff0ea07914e9d2 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Thu, 29 Dec 2022 23:29:50 +0100 Subject: Use weak for dcd_edpt_iso_alloc/dcd_edpt_iso_activate --- src/device/usbd.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index 8b5e4d745..ea9ab91b6 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1386,7 +1386,10 @@ bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packe TU_ASSERT(tu_edpt_number(ep_addr) < CFG_TUD_ENDPPOINT_MAX); - return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size); + if (dcd_edpt_iso_alloc) + return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size); + else + return false; } bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) @@ -1396,7 +1399,10 @@ bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < CFG_TUD_ENDPPOINT_MAX); TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed)); - return dcd_edpt_iso_activate(rhport, desc_ep); + if (dcd_edpt_iso_activate) + return dcd_edpt_iso_activate(rhport, desc_ep); + else + return false; } #endif -- cgit v1.3.1 From 07ad64adfe192a3cdc6dc20088d98dbb6beb0f58 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Thu, 29 Dec 2022 23:30:24 +0100 Subject: Do not set USB_EP_RX_NAK for ISO EP. --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index f3b55cd75..d462fc649 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -1170,9 +1170,11 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) } else { // OUT + if (pcd_get_eptype(USB, epnum) != USB_EP_ISOCHRONOUS) { + pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK); + } /* Reset to DATA0 if clearing stall condition. */ pcd_clear_rx_dtog(USB, epnum); - pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK); } } -- cgit v1.3.1 From 21bdafcfef4cfdbd77277da1717c8a33544b8721 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Fri, 30 Dec 2022 01:05:12 +0100 Subject: Add ISO buffer allocation. --- src/class/audio/audio_device.c | 123 +++++++++++++++++++++++++- src/device/usbd.c | 12 ++- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 37 +++++--- 3 files changed, 155 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 82682f162..a8a2439bc 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -106,6 +106,18 @@ #define USE_LINEAR_BUFFER 1 #endif +// Temporarily put the check here for stm32_fsdev +#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || \ + CFG_TUSB_MCU == OPT_MCU_STM32F3 || \ + CFG_TUSB_MCU == OPT_MCU_STM32L0 || \ + CFG_TUSB_MCU == OPT_MCU_STM32L1 || \ + CFG_TUSB_MCU == OPT_MCU_STM32G4 || \ + CFG_TUSB_MCU == OPT_MCU_STM32WB +#define USE_ISO_EP_ALLOCATION 1 +#else +#define USE_ISO_EP_ALLOCATION 0 +#endif + // Declaration of buffers // Check for maximum supported numbers @@ -1467,6 +1479,104 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin #endif } +#if USE_ISO_EP_ALLOCATION +#if CFG_TUD_AUDIO_ENABLE_EP_IN + uint8_t ep_in = 0; + uint16_t ep_in_size = 0; +#endif +#if CFG_TUD_AUDIO_ENABLE_EP_OUT + uint8_t ep_out = 0; + uint16_t ep_out_size = 0; +#endif +#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP + uint8_t ep_fb = 0; +#endif + + // First find EP addr + uint8_t const *p_desc = _audiod_fct[i].p_desc; + uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN; + while (p_desc < p_desc_end) + { + if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) + { + tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc; + if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) + { +#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP + // Explicit feedback EP + if (desc_ep->bmAttributes.usage == 1) + { + ep_fb = desc_ep->bEndpointAddress; + } +#endif + // Data EP + if (desc_ep->bmAttributes.usage == 0) + { + if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) + { +#if CFG_TUD_AUDIO_ENABLE_EP_IN + ep_in = desc_ep->bEndpointAddress; +#endif + } else + { +#if CFG_TUD_AUDIO_ENABLE_EP_OUT + ep_out = desc_ep->bEndpointAddress; +#endif + } + } + + } + } + p_desc = tu_desc_next(p_desc); + } + + // Then find EP max size + p_desc = _audiod_fct[i].p_desc; + while (p_desc < p_desc_end) + { + if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) + { + tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc; + if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) + { +#if CFG_TUD_AUDIO_ENABLE_EP_IN + if (desc_ep->bEndpointAddress == ep_in) + { + ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size); + } +#endif +#if CFG_TUD_AUDIO_ENABLE_EP_OUT + if (desc_ep->bEndpointAddress == ep_out) + { + ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size); + } +#endif + } + } + p_desc = tu_desc_next(p_desc); + } + +#if CFG_TUD_AUDIO_ENABLE_EP_IN + if (ep_in) + { + usbd_edpt_iso_alloc(rhport, ep_in, ep_in_size); + } +#endif +#if CFG_TUD_AUDIO_ENABLE_EP_OUT + if (ep_out) + { + usbd_edpt_iso_alloc(rhport, ep_out, ep_out_size); + } +#endif +#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP + if (ep_fb) + { + usbd_edpt_iso_alloc(rhport, ep_fb, 4); + } +#endif + +#endif + break; } } @@ -1528,8 +1638,9 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * if (audio->ep_in_as_intf_num == itf) { audio->ep_in_as_intf_num = 0; +#if !USE_ISO_EP_ALLOCATION usbd_edpt_close(rhport, audio->ep_in); - +#endif // Clear FIFOs, since data is no longer valid #if !CFG_TUD_AUDIO_ENABLE_ENCODING tu_fifo_clear(&audio->ep_in_ff); @@ -1552,8 +1663,9 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * if (audio->ep_out_as_intf_num == itf) { audio->ep_out_as_intf_num = 0; +#if !USE_ISO_EP_ALLOCATION usbd_edpt_close(rhport, audio->ep_out); - +#endif // Clear FIFOs, since data is no longer valid #if !CFG_TUD_AUDIO_ENABLE_DECODING tu_fifo_clear(&audio->ep_out_ff); @@ -1571,7 +1683,9 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * // Close corresponding feedback EP #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP +#if !USE_ISO_EP_ALLOCATION usbd_edpt_close(rhport, audio->ep_fb); +#endif audio->ep_fb = 0; tu_memclr(&audio->feedback, sizeof(audio->feedback)); #endif @@ -1601,8 +1715,11 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) { tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const *) p_desc; +#if USE_ISO_EP_ALLOCATION + TU_ASSERT(usbd_edpt_iso_activate(rhport, desc_ep)); +#else TU_ASSERT(usbd_edpt_open(rhport, desc_ep)); - +#endif uint8_t const ep_addr = desc_ep->bEndpointAddress; //TODO: We need to set EP non busy since this is not taken care of right now in ep_close() - THIS IS A WORKAROUND! diff --git a/src/device/usbd.c b/src/device/usbd.c index ea9ab91b6..fd4414559 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1396,11 +1396,19 @@ bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep { rhport = _usbd_rhport; - TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < CFG_TUD_ENDPPOINT_MAX); + uint8_t const epnum = tu_edpt_number(desc_ep->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(desc_ep->bEndpointAddress); + + TU_ASSERT(epnum < CFG_TUD_ENDPPOINT_MAX); TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed)); - + if (dcd_edpt_iso_activate) + { + _usbd_dev.ep_status[epnum][dir].stalled = false; + _usbd_dev.ep_status[epnum][dir].busy = false; + _usbd_dev.ep_status[epnum][dir].claimed = false; return dcd_edpt_iso_activate(rhport, desc_ep); + } else return false; } diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index d462fc649..a428d546d 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -812,6 +812,13 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type) for(uint8_t i = 0; i < STFSDEV_EP_COUNT; i++) { + // Check if already allocated + if(ep_alloc_status[i].allocated[dir] && + ep_alloc_status[i].ep_type == ep_type && + ep_alloc_status[i].ep_num == epnum) + { + return i; + } // If EP of current direction is not allocated // Except for ISO endpoint, both direction should be free if(!ep_alloc_status[i].allocated[dir] && @@ -971,7 +978,7 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) if(dir == TUSB_DIR_IN) { - pcd_set_ep_tx_status(USB,epnum, USB_EP_TX_DIS); + pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS); } else { @@ -994,10 +1001,15 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet /* Create a packet memory buffer area. For isochronous endpoints, * use the same buffer as the double buffer, essentially disabling double buffering */ - dcd_pma_alloc(ep_addr, buffer_size); + uint16_t pma_addr = dcd_pma_alloc(ep_addr, buffer_size); xfer_ctl_ptr(ep_addr)->epnum = epnum; + pcd_set_eptype(USB, epnum, USB_EP_ISOCHRONOUS); + + *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr; + *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr; + return true; } @@ -1005,25 +1017,26 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpo { (void)rhport; uint8_t const epnum = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum; - const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc); - uint16_t pma_addr; + uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); + const uint16_t packet_size = pcd_aligned_buffer_size(tu_edpt_packet_size(p_endpoint_desc)); /* Disable endpoint */ - pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS); - pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS); - - pcd_set_eptype(USB, epnum, USB_EP_ISOCHRONOUS); + if(dir == TUSB_DIR_IN) + { + pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS); + } + else + { + pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS); + } + pcd_set_ep_address(USB, epnum, tu_edpt_number(p_endpoint_desc->bEndpointAddress)); // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint) // or being double-buffered (bulk endpoints) pcd_clear_ep_kind(USB,0); - pma_addr = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->pma_ptr; - - *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr; pcd_clear_tx_dtog(USB, epnum); - *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr; pcd_set_ep_rx_bufsize(USB, epnum, packet_size); pcd_clear_rx_dtog(USB, epnum); -- cgit v1.3.1 From fc32280f42e03ef78e8d43bb9e8382ad4c9b19c0 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Fri, 30 Dec 2022 15:10:00 +0100 Subject: Fix buffer allocation overflow. --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index a428d546d..702b32f9c 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -167,8 +167,8 @@ typedef struct uint16_t total_len; uint16_t queued_len; uint16_t pma_ptr; - uint8_t max_packet_size; - uint8_t pma_alloc_size; + uint16_t max_packet_size; + uint16_t pma_alloc_size; uint8_t epnum; } xfer_ctl_t; -- cgit v1.3.1 From 51bb27a131ca57f8f7c7c971024f90e77b81d11a Mon Sep 17 00:00:00 2001 From: Mengsk Date: Sat, 31 Dec 2022 13:37:22 +0100 Subject: Optimize descriptor looping. --- src/class/audio/audio_device.c | 50 +++++++++++++++++------------------------- 1 file changed, 20 insertions(+), 30 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index a8a2439bc..31c4783eb 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -106,13 +106,28 @@ #define USE_LINEAR_BUFFER 1 #endif +#if defined(STM32F102x6) || defined(STM32F102xB) || \ + defined(STM32F103x6) || defined(STM32F103xB) || \ + defined(STM32F103xE) || defined(STM32F103xG) +#define STM32F1_FSDEV +#endif + +#if defined(STM32L412xx) || defined(STM32L422xx) || \ + defined(STM32L432xx) || defined(STM32L433xx) || \ + defined(STM32L442xx) || defined(STM32L443xx) || \ + defined(STM32L452xx) || defined(STM32L462xx) +#define STM32L4_FSDEV +#endif + // Temporarily put the check here for stm32_fsdev #if CFG_TUSB_MCU == OPT_MCU_STM32F0 || \ CFG_TUSB_MCU == OPT_MCU_STM32F3 || \ CFG_TUSB_MCU == OPT_MCU_STM32L0 || \ CFG_TUSB_MCU == OPT_MCU_STM32L1 || \ CFG_TUSB_MCU == OPT_MCU_STM32G4 || \ - CFG_TUSB_MCU == OPT_MCU_STM32WB + CFG_TUSB_MCU == OPT_MCU_STM32WB || \ + (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) || \ + (TU_CHECK_MCU(OPT_MCU_STM32L4) && defined(STM32L4_FSDEV)) #define USE_ISO_EP_ALLOCATION 1 #else #define USE_ISO_EP_ALLOCATION 0 @@ -1481,18 +1496,17 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin #if USE_ISO_EP_ALLOCATION #if CFG_TUD_AUDIO_ENABLE_EP_IN - uint8_t ep_in = 0; + uint8_t ep_in = 0; uint16_t ep_in_size = 0; #endif #if CFG_TUD_AUDIO_ENABLE_EP_OUT - uint8_t ep_out = 0; + uint8_t ep_out = 0; uint16_t ep_out_size = 0; #endif #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP uint8_t ep_fb = 0; #endif - // First find EP addr uint8_t const *p_desc = _audiod_fct[i].p_desc; uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN; while (p_desc < p_desc_end) @@ -1516,11 +1530,13 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin { #if CFG_TUD_AUDIO_ENABLE_EP_IN ep_in = desc_ep->bEndpointAddress; + ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size); #endif } else { #if CFG_TUD_AUDIO_ENABLE_EP_OUT ep_out = desc_ep->bEndpointAddress; + ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size); #endif } } @@ -1530,32 +1546,6 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin p_desc = tu_desc_next(p_desc); } - // Then find EP max size - p_desc = _audiod_fct[i].p_desc; - while (p_desc < p_desc_end) - { - if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) - { - tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc; - if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) - { -#if CFG_TUD_AUDIO_ENABLE_EP_IN - if (desc_ep->bEndpointAddress == ep_in) - { - ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size); - } -#endif -#if CFG_TUD_AUDIO_ENABLE_EP_OUT - if (desc_ep->bEndpointAddress == ep_out) - { - ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size); - } -#endif - } - } - p_desc = tu_desc_next(p_desc); - } - #if CFG_TUD_AUDIO_ENABLE_EP_IN if (ep_in) { -- cgit v1.3.1 From 7228239eb94f16281fe98ca3a612ba89995f7b47 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Mon, 2 Jan 2023 09:43:48 +0100 Subject: Clean up. --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 9 --------- 1 file changed, 9 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 382374614..ded13ae14 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -119,15 +119,6 @@ // Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden) static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR; -// This array maps the endpoint address to a endpoint register in hardware -// By default the tinyusb stack chooses the endpoint register using the endpoint number -// However when using ISOCHRONOUS endpoints, the entire endpoint register (RX _and_ TX) -// are used for a double buffer in a single direction. If you now want to use the same endpoint number with -// different directions (e.g. 0x02 and 0x82), they would be mapped to the same register -// In this case, this serves as a crude helper to overcome this limitation by implementing -// this callback and defining a custom mapping in your application -TU_ATTR_WEAK uint8_t tu_stm32_edpt_number_cb(uint8_t addr); - // This callback is called on SOF and can be used to e.g. capture a timer value for timing purposes TU_ATTR_WEAK void tu_stm32_sof_cb(void); -- cgit v1.3.1 From 69475cd1bf6c4937bd2bc6570f611a700022cdac Mon Sep 17 00:00:00 2001 From: Mengsk Date: Mon, 2 Jan 2023 12:06:26 +0100 Subject: Remove tu_stm32_sof_cb --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 1 - src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 3 --- 2 files changed, 4 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 702b32f9c..648e8f8d0 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -649,7 +649,6 @@ void dcd_int_handler(uint8_t rhport) { /* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */ if(int_status & USB_ISTR_SOF) { clear_istr_bits(USB_ISTR_SOF); - if (tu_stm32_sof_cb) tu_stm32_sof_cb(); dcd_event_sof(0, USB->FNR & USB_FNR_FN, true); } diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index ded13ae14..98cf008d4 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -119,9 +119,6 @@ // Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden) static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR; -// This callback is called on SOF and can be used to e.g. capture a timer value for timing purposes -TU_ATTR_WEAK void tu_stm32_sof_cb(void); - // prototypes TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum); TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum); -- cgit v1.3.1 From 82f105e32b3b299509daa1dc24d6aa94f5ce63fb Mon Sep 17 00:00:00 2001 From: Mengsk Date: Mon, 2 Jan 2023 17:12:03 +0100 Subject: Fix IAR warning: Warning[Pe381]: extra ";" ignored --- src/class/usbtmc/usbtmc_device.c | 6 ++++-- src/osal/osal.h | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index 07c7c28a6..ba38bfca8 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -157,8 +157,10 @@ static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t pack static uint8_t termChar; static uint8_t termCharRequested = false; -OSAL_MUTEX_DEF(usbtmcLockBuffer); -static osal_mutex_t usbtmcLock; +#if OSAL_MUTEX_REQUIRED +static OSAL_MUTEX_DEF(usbtmcLockBuffer); +#endif +osal_mutex_t usbtmcLock; // Our own private lock, mostly for the state variable. #define criticalEnter() do { (void) osal_mutex_lock(usbtmcLock,OSAL_TIMEOUT_WAIT_FOREVER); } while (0) diff --git a/src/osal/osal.h b/src/osal/osal.h index 9cdab2882..afa3826fc 100644 --- a/src/osal/osal.h +++ b/src/osal/osal.h @@ -44,7 +44,7 @@ typedef void (*osal_task_func_t)( void * ); // Mutex is required when using a preempted RTOS or MCU has multiple cores #if (CFG_TUSB_OS == OPT_OS_NONE) && !TUP_MCU_MULTIPLE_CORE #define OSAL_MUTEX_REQUIRED 0 - #define OSAL_MUTEX_DEF(_name) + #define OSAL_MUTEX_DEF(_name) uint8_t :0 #else #define OSAL_MUTEX_REQUIRED 1 #define OSAL_MUTEX_DEF(_name) osal_mutex_def_t _name -- cgit v1.3.1 From f5cffeedec863c1efd59688fa79a8455046e8377 Mon Sep 17 00:00:00 2001 From: pete-pjb Date: Tue, 3 Jan 2023 10:33:36 +0000 Subject: Fix typo in audio.h. Specifiy _ctrl_xfer struct in CFG_TUSB_MEM_SECTION Add NULL check to loop in list_remove_qhd_by_addr() function in ehci.c --- src/class/audio/audio.h | 2 ++ src/host/usbh.c | 8 ++++---- src/portable/ehci/ehci.c | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio.h b/src/class/audio/audio.h index 6f9c1a6b5..ba497906b 100644 --- a/src/class/audio/audio.h +++ b/src/class/audio/audio.h @@ -721,11 +721,13 @@ typedef struct TU_ATTR_PACKED uint8_t bLength ; ///< Size of this descriptor, in bytes: 17. uint8_t bDescriptorType ; ///< Descriptor Type. Value: TUSB_DESC_CS_INTERFACE. uint8_t bDescriptorSubType ; ///< Descriptor SubType. Value: AUDIO_CS_AC_INTERFACE_INPUT_TERMINAL. + uint8_t bTerminalID ; ///< Constant uniquely identifying the Terminal within the audio function. This value is used in all requests to address this terminal. uint16_t wTerminalType ; ///< Constant characterizing the type of Terminal. See: audio_terminal_type_t for USB streaming and audio_terminal_input_type_t for other input types. uint8_t bAssocTerminal ; ///< ID of the Output Terminal to which this Input Terminal is associated. uint8_t bCSourceID ; ///< ID of the Clock Entity to which this Input Terminal is connected. uint8_t bNrChannels ; ///< Number of logical output channels in the Terminal’s output audio channel cluster. uint32_t bmChannelConfig ; ///< Describes the spatial location of the logical channels. See:audio_channel_config_t. + uint8_t iChannelNames ; ///< Index of a string descriptor, describing the name of the first logical channel. uint16_t bmControls ; ///< See: audio_terminal_input_control_pos_t. uint8_t iTerminal ; ///< Index of a string descriptor, describing the Input Terminal. } audio_desc_input_terminal_t; diff --git a/src/host/usbh.c b/src/host/usbh.c index af1e67d4d..5ac9e9cca 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -229,10 +229,10 @@ static osal_queue_t _usbh_q; CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE]; -// Control transfer: since most controller does not support multiple control transfer -// on multiple devices concurrently. And control transfer is not used much except enumeration -// We will only execute control transfer one at a time. -struct +// Control transfers: since most controllers do not support multiple control transfers +// on multiple devices concurrently and control transfers are not used much except for +// enumeration, we will only execute control transfers one at a time. +CFG_TUSB_MEM_SECTION struct { tusb_control_request_t request TU_ATTR_ALIGNED(4); uint8_t* buffer; diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 80f616478..7140897a1 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -188,7 +188,7 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport) static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr) { for(ehci_link_t* prev = list_head; - !prev->terminate && (tu_align32(prev->address) != (uint32_t) list_head); + !prev->terminate && (tu_align32(prev->address) != (uint32_t) list_head) && prev != NULL; prev = list_next(prev) ) { // TODO check type for ISO iTD and siTD -- cgit v1.3.1 From 8c591e2c45f80f41d2704ae3b3ce5bde8550ecb9 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Wed, 4 Jan 2023 10:19:34 +0100 Subject: More warning fixes --- src/class/usbtmc/usbtmc_device.c | 73 +++++++++++++++++++--------------------- 1 file changed, 34 insertions(+), 39 deletions(-) (limited to 'src') diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index ba38bfca8..0cf0743a7 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -364,7 +364,7 @@ bool tud_usbtmc_start_bus_read() case STATE_RCV: break; default: - TU_VERIFY(false); + return false; } TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_out, usbtmc_state.ep_bulk_out_buf, (uint16_t)usbtmc_state.ep_bulk_out_wMaxPacketSize)); return true; @@ -466,53 +466,52 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint switch(usbtmc_state.state) { case STATE_IDLE: - TU_VERIFY(xferred_bytes >= sizeof(usbtmc_msg_generic_t)); - msg = (usbtmc_msg_generic_t*)(usbtmc_state.ep_bulk_out_buf); - uint8_t invInvTag = (uint8_t)~(msg->header.bTagInverse); - TU_VERIFY(msg->header.bTag == invInvTag); - TU_VERIFY(msg->header.bTag != 0x00); - - switch(msg->header.MsgID) { - case USBTMC_MSGID_DEV_DEP_MSG_OUT: - if(!handle_devMsgOutStart(rhport, msg, xferred_bytes)) - { - usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); - TU_VERIFY(false); - } - break; + { + TU_VERIFY(xferred_bytes >= sizeof(usbtmc_msg_generic_t)); + msg = (usbtmc_msg_generic_t*)(usbtmc_state.ep_bulk_out_buf); + uint8_t invInvTag = (uint8_t)~(msg->header.bTagInverse); + TU_VERIFY(msg->header.bTag == invInvTag); + TU_VERIFY(msg->header.bTag != 0x00); + + switch(msg->header.MsgID) { + case USBTMC_MSGID_DEV_DEP_MSG_OUT: + if(!handle_devMsgOutStart(rhport, msg, xferred_bytes)) + { + usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); + return false; + } + break; - case USBTMC_MSGID_DEV_DEP_MSG_IN: - TU_VERIFY(handle_devMsgIn(msg, xferred_bytes)); - break; + case USBTMC_MSGID_DEV_DEP_MSG_IN: + TU_VERIFY(handle_devMsgIn(msg, xferred_bytes)); + break; #if (CFG_TUD_USBTMC_ENABLE_488) - case USBTMC_MSGID_USB488_TRIGGER: - // Spec says we halt the EP if we didn't declare we support it. - TU_VERIFY(usbtmc_state.capabilities->bmIntfcCapabilities488.supportsTrigger); - TU_VERIFY(tud_usbtmc_msg_trigger_cb(msg)); + case USBTMC_MSGID_USB488_TRIGGER: + // Spec says we halt the EP if we didn't declare we support it. + TU_VERIFY(usbtmc_state.capabilities->bmIntfcCapabilities488.supportsTrigger); + TU_VERIFY(tud_usbtmc_msg_trigger_cb(msg)); - break; + break; #endif - case USBTMC_MSGID_VENDOR_SPECIFIC_MSG_OUT: - case USBTMC_MSGID_VENDOR_SPECIFIC_IN: - default: - usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); - TU_VERIFY(false); - return false; + case USBTMC_MSGID_VENDOR_SPECIFIC_MSG_OUT: + case USBTMC_MSGID_VENDOR_SPECIFIC_IN: + default: + usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); + return false; + } + return true; } - return true; - case STATE_RCV: if(!handle_devMsgOut(rhport, usbtmc_state.ep_bulk_out_buf, xferred_bytes, xferred_bytes)) { usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); - TU_VERIFY(false); + return false; } return true; case STATE_ABORTING_BULK_OUT: - TU_VERIFY(false); - return false; // Should be stalled by now, shouldn't have received a packet. + return false; case STATE_TX_REQUESTED: case STATE_TX_INITIATED: @@ -520,7 +519,7 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint case STATE_ABORTING_BULK_IN_SHORTED: case STATE_ABORTING_BULK_IN_ABORTED: default: - TU_VERIFY(false); + return false; } } else if(ep_addr == usbtmc_state.ep_bulk_in) @@ -569,7 +568,6 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint default: TU_ASSERT(false); - return false; } } else if (ep_addr == usbtmc_state.ep_int_in) { @@ -873,16 +871,13 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request case USB488_bREQUEST_LOCAL_LOCKOUT: { TU_VERIFY(request->bmRequestType == 0xA1); // in,class,interface - TU_VERIFY(false); return false; } #endif default: - TU_VERIFY(false); return false; } - TU_VERIFY(false); } #endif /* CFG_TUD_TSMC */ -- cgit v1.3.1 From d6b612257ed1026cccd18c620d3d6cb51d5b2cb2 Mon Sep 17 00:00:00 2001 From: Simon Kueppers Date: Thu, 5 Jan 2023 14:39:23 +0100 Subject: Fixed bug where with some devices, the TU_ASSERT inserted with this commit gets triggered for ISOCHRONOUS endpoints. It is necessary for those endpoints to set the NUM_BLOCK and BLSIZE for the receiving buffer in both, USB_COUNTn_TX and USB_COUNTn_RX. Despite the datasheet showing those fields only for the USB_COUNTn_RX register --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 15 ++++++++++++--- src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 9 +++++++++ 2 files changed, 21 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 648e8f8d0..fdcb2c48d 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -562,6 +562,8 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) count = pcd_get_ep_rx_cnt(USB, EPindex); } + TU_ASSERT(count <= xfer->max_packet_size, /**/); + // Clear RX CTR interrupt flag if(ep_addr != 0u) { @@ -599,7 +601,12 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) } else { pcd_set_ep_rx_bufsize(USB, EPindex,remaining); } - pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID); + + if (!((wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS)) { + /* Set endpoint active again for receiving more data. + * Note that isochronous endpoints stay active always */ + pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID); + } } } @@ -881,7 +888,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc (void)rhport; uint8_t const epnum = dcd_ep_alloc(p_endpoint_desc->bEndpointAddress, p_endpoint_desc->bmAttributes.xfer); uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); - const uint16_t buffer_size = pcd_aligned_buffer_size(tu_edpt_packet_size(p_endpoint_desc)); + const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc); + const uint16_t buffer_size = pcd_aligned_buffer_size(packet_size); uint16_t pma_addr; uint32_t wType; @@ -921,6 +929,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc if( (dir == TUSB_DIR_IN) || (wType == USB_EP_ISOCHRONOUS) ) { *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr; + pcd_set_ep_tx_bufsize(USB, epnum, buffer_size); pcd_clear_tx_dtog(USB, epnum); } @@ -948,7 +957,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc } } - xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = buffer_size; + xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = packet_size; xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum = epnum; return true; diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 98cf008d4..f4966907a 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -281,6 +281,13 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU); } +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) +{ + __IO uint16_t *pdwReg = pcd_ep_tx_cnt_ptr((USBx),(bEpNum)); + wCount = pcd_aligned_buffer_size(wCount); + pcd_set_ep_cnt_reg(pdwReg, wCount); +} + TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) { __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpNum)); @@ -310,6 +317,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx { regVal ^= USB_EPTX_DTOG2; } + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; pcd_set_endpoint(USBx, bEpNum, regVal); } /* pcd_set_ep_tx_status */ @@ -337,6 +345,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx { regVal ^= USB_EPRX_DTOG2; } + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; pcd_set_endpoint(USBx, bEpNum, regVal); } /* pcd_set_ep_rx_status */ -- cgit v1.3.1 From 8db462bf6e2cd6d244ab9b3a69471ad085478bf6 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Thu, 5 Jan 2023 16:54:42 +0100 Subject: Add fix to dcd_edpt_iso_activate() --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index fdcb2c48d..c9b244c8c 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -1026,7 +1026,8 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpo (void)rhport; uint8_t const epnum = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum; uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); - const uint16_t packet_size = pcd_aligned_buffer_size(tu_edpt_packet_size(p_endpoint_desc)); + const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc); + const uint16_t buffer_size = pcd_aligned_buffer_size(packet_size); /* Disable endpoint */ if(dir == TUSB_DIR_IN) @@ -1043,9 +1044,9 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpo // or being double-buffered (bulk endpoints) pcd_clear_ep_kind(USB,0); + pcd_set_ep_tx_bufsize(USB, epnum, buffer_size); + pcd_set_ep_rx_bufsize(USB, epnum, buffer_size); pcd_clear_tx_dtog(USB, epnum); - - pcd_set_ep_rx_bufsize(USB, epnum, packet_size); pcd_clear_rx_dtog(USB, epnum); xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = packet_size; -- cgit v1.3.1 From 9c73c1a532649630de5e55400632bcca90ebea06 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 6 Jan 2023 10:56:19 +0700 Subject: minor clean up --- src/common/tusb_fifo.c | 4 ++-- src/common/tusb_fifo.h | 8 +++----- 2 files changed, 5 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index 6862a6f43..d3875a7d4 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -39,12 +39,12 @@ // implement mutex lock and unlock #if CFG_FIFO_MUTEX -static inline void _ff_lock(tu_fifo_mutex_t mutex) +static inline void _ff_lock(osal_mutex_t mutex) { if (mutex) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER); } -static inline void _ff_unlock(tu_fifo_mutex_t mutex) +static inline void _ff_unlock(osal_mutex_t mutex) { if (mutex) osal_mutex_unlock(mutex); } diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h index f1810e39c..f72ff295b 100644 --- a/src/common/tusb_fifo.h +++ b/src/common/tusb_fifo.h @@ -44,8 +44,6 @@ extern "C" { #include "common/tusb_common.h" #include "osal/osal.h" -#define tu_fifo_mutex_t osal_mutex_t - // mutex is only needed for RTOS // for OS None, we don't get preempted #define CFG_FIFO_MUTEX OSAL_MUTEX_REQUIRED @@ -121,8 +119,8 @@ typedef struct volatile uint16_t rd_idx ; ///< read index #if OSAL_MUTEX_REQUIRED - tu_fifo_mutex_t mutex_wr; - tu_fifo_mutex_t mutex_rd; + osal_mutex_t mutex_wr; + osal_mutex_t mutex_rd; #endif } tu_fifo_t; @@ -155,7 +153,7 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si #if OSAL_MUTEX_REQUIRED TU_ATTR_ALWAYS_INLINE static inline -void tu_fifo_config_mutex(tu_fifo_t *f, tu_fifo_mutex_t wr_mutex, tu_fifo_mutex_t rd_mutex) +void tu_fifo_config_mutex(tu_fifo_t *f, osal_mutex_t wr_mutex, osal_mutex_t rd_mutex) { f->mutex_wr = wr_mutex; f->mutex_rd = rd_mutex; -- cgit v1.3.1 From 2a1b81e3c50f5e37530c8318b7fb7767ba771979 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 6 Jan 2023 11:51:17 +0700 Subject: minimize tu_fifo size to 16 - remove non_used_index_space - packed overwritable with item_size --- src/common/tusb_fifo.c | 37 ++++++++++++++++++------------------- src/common/tusb_fifo.h | 40 +++++++++++++++++++--------------------- src/device/usbd.c | 2 ++ 3 files changed, 39 insertions(+), 40 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index d3875a7d4..4dfe7bd81 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -68,22 +68,19 @@ typedef enum bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable) { - if (depth > 0x8000) return false; // Maximum depth is 2^15 items + // Limit index space to 2*depth - this allows for a fast "modulo" calculation + // but limits the maximum depth to 2^16/2 = 2^15 and buffer overflows are detectable + // only if overflow happens once (important for unsupervised DMA applications) + if (depth > 0x8000) return false; _ff_lock(f->mutex_wr); _ff_lock(f->mutex_rd); - f->buffer = (uint8_t*) buffer; - f->depth = depth; - f->item_size = item_size; + f->buffer = (uint8_t*) buffer; + f->depth = depth; + f->item_size = (uint16_t) (item_size & 0x7FFF); f->overwritable = overwritable; - // Limit index space to 2*depth - this allows for a fast "modulo" calculation - // but limits the maximum depth to 2^16/2 = 2^15 and buffer overflows are detectable - // only if overflow happens once (important for unsupervised DMA applications) - //f->max_pointer_idx = (uint16_t) (2*depth - 1); - f->non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1)); - f->rd_idx = f->wr_idx = 0; _ff_unlock(f->mutex_wr); @@ -331,7 +328,8 @@ static uint16_t advance_pointer(tu_fifo_t* f, uint16_t idx, uint16_t offset) uint16_t next_p = (uint16_t) (idx + offset); if ( (idx > next_p) || (next_p >= 2*f->depth) ) { - next_p = (uint16_t) (next_p + f->non_used_index_space); + uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1)); + next_p = (uint16_t) (next_p + non_used_index_space); } return next_p; @@ -346,7 +344,8 @@ static uint16_t backward_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset) uint16_t new_p = (uint16_t) (p - offset); if ( (p < new_p) || (new_p >= 2*f->depth) ) { - new_p = (uint16_t) (new_p - f->non_used_index_space); + uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1)); + new_p = (uint16_t) (new_p - non_used_index_space); } return new_p; @@ -363,13 +362,15 @@ static inline uint16_t idx2ptr(uint16_t idx, uint16_t depth) // Works on local copies of w and r - return only the difference and as such can be used to determine an overflow static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx) { - uint16_t cnt = (uint16_t) (wr_idx-rd_idx); + uint16_t cnt; // In case we have non-power of two depth we need a further modification - if (rd_idx > wr_idx) + if (wr_idx >= rd_idx) + { + cnt = (uint16_t) (wr_idx - rd_idx); + } else { - // 2*f->depth - (rd_idx - wr_idx); - cnt = (uint16_t) (cnt - f->non_used_index_space); + cnt = (uint16_t) (2*f->depth - (rd_idx - wr_idx)); } return cnt; @@ -395,7 +396,7 @@ static inline bool _tu_fifo_full(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs) // use DMAs, write functions do not allow such an error. static inline bool _tu_fifo_overflowed(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx) { - return (_tu_fifo_count(f, wr_idx, rd_idx) > f->depth); + return _tu_fifo_count(f, wr_idx, rd_idx) > f->depth; } // Works on local copies of w @@ -868,8 +869,6 @@ bool tu_fifo_clear(tu_fifo_t *f) _ff_lock(f->mutex_rd); f->rd_idx = f->wr_idx = 0; - //f->max_pointer_idx = (uint16_t) (2*f->depth-1); - f->non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1)); _ff_unlock(f->mutex_wr); _ff_unlock(f->mutex_rd); diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h index f72ff295b..2f60ec2f4 100644 --- a/src/common/tusb_fifo.h +++ b/src/common/tusb_fifo.h @@ -69,8 +69,8 @@ extern "C" { * | 0 | 1 | W | 3 | 4 | R | * * - Number of items in the fifo can be determined in either cases: - * - case W > R: Count = W - R - * - case W < R: Count = 2*depth - (R - W) + * - case W >= R: Count = W - R + * - case W < R: Count = 2*depth - (R - W) * * In non-overwritable mode, computed Count (in above 2 cases) is at most equal to depth. * However, in over-writable mode, write index can be repeatedly increased and count can be @@ -82,10 +82,10 @@ extern "C" { * ------------------------- * | R | 1 | 2 | 3 | W | 5 | * - * - Double Overflowed i.e index is out of allowed range [0,2*depth) e.g: + * - Double Overflowed i.e index is out of allowed range [0,2*depth) + * This occurs when we continue to write after 1st overflowed to 2nd overflowed. e.g: * write(3), write(1), write(2) - * Continue to write after overflowed to 2nd overflowed. - * We must prevent 2nd overflowed since it will cause incorrect computed of count, in above example + * This must be prevented since it will cause unrecoverable state, in above example * if not handled the fifo will be empty instead of continue-to-be full. Since we must not modify * read index in write() function, which cause race condition. We will re-position write index so that * after data is written it is a full fifo i.e W = depth - R @@ -106,17 +106,16 @@ extern "C" { */ typedef struct { - uint8_t* buffer ; ///< buffer pointer - uint16_t depth ; ///< max items - uint16_t item_size ; ///< size of each item + uint8_t* buffer ; // buffer pointer + uint16_t depth ; // max items - bool overwritable ; + struct TU_ATTR_PACKED { + uint16_t item_size : 15; // size of each item + bool overwritable : 1 ; // ovwerwritable when full + }; - uint16_t non_used_index_space ; ///< required for non-power-of-two buffer length - //uint16_t max_pointer_idx ; ///< maximum absolute pointer index - - volatile uint16_t wr_idx ; ///< write index - volatile uint16_t rd_idx ; ///< read index + volatile uint16_t wr_idx ; // write index + volatile uint16_t rd_idx ; // read index #if OSAL_MUTEX_REQUIRED osal_mutex_t mutex_wr; @@ -133,13 +132,12 @@ typedef struct void * ptr_wrap ; ///< wrapped part start pointer } tu_fifo_buffer_info_t; -#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable) \ -{ \ - .buffer = _buffer, \ - .depth = _depth, \ - .item_size = sizeof(_type), \ - .overwritable = _overwritable, \ - .non_used_index_space = (uint16_t)(UINT16_MAX - (2*(_depth)-1)), \ +#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable) \ +{ \ + .buffer = _buffer, \ + .depth = _depth, \ + .item_size = sizeof(_type), \ + .overwritable = _overwritable, \ } #define TU_FIFO_DEF(_name, _depth, _type, _overwritable) \ diff --git a/src/device/usbd.c b/src/device/usbd.c index f652a878e..6e0c6710d 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -388,6 +388,8 @@ bool tud_init (uint8_t rhport) TU_LOG(USBD_DBG, "USBD init on controller %u\r\n", rhport); TU_LOG_INT(USBD_DBG, sizeof(usbd_device_t)); + TU_LOG_INT(USBD_DBG, sizeof(tu_fifo_t)); + TU_LOG_INT(USBD_DBG, sizeof(tu_edpt_stream_t)); tu_varclr(&_usbd_dev); -- cgit v1.3.1 From 82457519fa050b2efd1b462ba88f7f258047c715 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 6 Jan 2023 12:11:55 +0700 Subject: minor clean up --- src/common/tusb_fifo.c | 68 ++++++++++++++++++++++++++------------------------ 1 file changed, 36 insertions(+), 32 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index 4dfe7bd81..f72c8a12f 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -28,16 +28,15 @@ #include "osal/osal.h" #include "tusb_fifo.h" +#define TU_FIFO_DBG 0 + // Suppress IAR warning // Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined in this statement #if defined(__ICCARM__) #pragma diag_suppress = Pa082 #endif -#define TU_FIFO_DBG 0 - -// implement mutex lock and unlock -#if CFG_FIFO_MUTEX +#if OSAL_MUTEX_REQUIRED static inline void _ff_lock(osal_mutex_t mutex) { @@ -80,8 +79,8 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si f->depth = depth; f->item_size = (uint16_t) (item_size & 0x7FFF); f->overwritable = overwritable; - - f->rd_idx = f->wr_idx = 0; + f->rd_idx = 0; + f->wr_idx = 0; _ff_unlock(f->mutex_wr); _ff_unlock(f->mutex_rd); @@ -142,13 +141,13 @@ static void _ff_pull_const_addr(void * app_buf, const uint8_t * ff_buf, uint16_t } } -// send one item to FIFO WITHOUT updating write pointer +// send one item to fifo WITHOUT updating write pointer static inline void _ff_push(tu_fifo_t* f, void const * app_buf, uint16_t rel) { memcpy(f->buffer + (rel * f->item_size), app_buf, f->item_size); } -// send n items to FIFO WITHOUT updating write pointer +// send n items to fifo WITHOUT updating write pointer static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode) { uint16_t const nLin = f->depth - rel; @@ -227,13 +226,13 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t } } -// get one item from FIFO WITHOUT updating read pointer +// get one item from fifo WITHOUT updating read pointer static inline void _ff_pull(tu_fifo_t* f, void * app_buf, uint16_t rel) { memcpy(app_buf, f->buffer + (rel * f->item_size), f->item_size); } -// get n items from FIFO WITHOUT updating read pointer +// get n items from fifo WITHOUT updating read pointer static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode) { uint16_t const nLin = f->depth - rel; @@ -475,14 +474,14 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu uint16_t rd_idx = f->rd_idx; uint8_t const* buf8 = (uint8_t const*) data; - uint16_t overflowable_count = _tu_fifo_count(f, wr_idx, rd_idx); - uint16_t const remain = _tu_fifo_remaining(f, wr_idx, rd_idx); - TU_LOG(TU_FIFO_DBG, "rd = %3u, wr = %3u, count = %3u, remain = %3u, n = %3u: ", rd_idx, wr_idx, _tu_fifo_count(f, wr_idx, rd_idx), remain, n); + TU_LOG(TU_FIFO_DBG, "rd = %3u, wr = %3u, count = %3u, remain = %3u, n = %3u: ", + rd_idx, wr_idx, _tu_fifo_count(f, wr_idx, rd_idx), _tu_fifo_remaining(f, wr_idx, rd_idx), n); if ( !f->overwritable ) { // limit up to full + uint16_t const remain = _tu_fifo_remaining(f, wr_idx, rd_idx); n = tu_min16(n, remain); } else @@ -508,23 +507,27 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu // We start writing at the read pointer's position since we fill the whole buffer wr_idx = rd_idx; } - else if (overflowable_count + n >= 2*f->depth) - { - // Double overflowed - // Index is bigger than the allowed range [0,2*depth) - // re-position write index to have a full fifo after pushed - wr_idx = advance_pointer(f, rd_idx, f->depth - n); - - // TODO we should also shift out n bytes from read index since we avoid changing rd index !! - // However memmove() is expensive due to actual copying + wrapping consideration. - // Also race condition could happen anyway if read() is invoke while moving result in corrupted memory - // currently deliberately not implemented --> result in incorrect data read back - }else + else { - // normal + single overflowed: - // Index is in the range of [0,2*depth) and thus detect and recoverable. Recovering is handled in read() - // Therefore we just increase write index - // we will correct (re-position) read index later on in fifo_read() function + uint16_t const overflowable_count = _tu_fifo_count(f, wr_idx, rd_idx); + if (overflowable_count + n >= 2*f->depth) + { + // Double overflowed + // Index is bigger than the allowed range [0,2*depth) + // re-position write index to have a full fifo after pushed + wr_idx = advance_pointer(f, rd_idx, f->depth - n); + + // TODO we should also shift out n bytes from read index since we avoid changing rd index !! + // However memmove() is expensive due to actual copying + wrapping consideration. + // Also race condition could happen anyway if read() is invoke while moving result in corrupted memory + // currently deliberately not implemented --> result in incorrect data read back + }else + { + // normal + single overflowed: + // Index is in the range of [0,2*depth) and thus detect and recoverable. Recovering is handled in read() + // Therefore we just increase write index + // we will correct (re-position) read index later on in fifo_read() function + } } } @@ -868,7 +871,8 @@ bool tu_fifo_clear(tu_fifo_t *f) _ff_lock(f->mutex_wr); _ff_lock(f->mutex_rd); - f->rd_idx = f->wr_idx = 0; + f->rd_idx = 0; + f->wr_idx = 0; _ff_unlock(f->mutex_wr); _ff_unlock(f->mutex_rd); @@ -1031,9 +1035,9 @@ void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) if (remain == 0) { - info->len_lin = 0; + info->len_lin = 0; info->len_wrap = 0; - info->ptr_lin = NULL; + info->ptr_lin = NULL; info->ptr_wrap = NULL; return; } -- cgit v1.3.1 From a804a1ac09c34a4f69c0d2873a552a2a505d0492 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 7 Jan 2023 16:48:07 +0700 Subject: simplify and remove _tu_fifo_empty, _tu_fifo_full. Also correct full condition check --- src/common/tusb_fifo.c | 30 +++++++----------------------- 1 file changed, 7 insertions(+), 23 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index f72c8a12f..4b27bc589 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -38,12 +38,12 @@ #if OSAL_MUTEX_REQUIRED -static inline void _ff_lock(osal_mutex_t mutex) +TU_ATTR_ALWAYS_INLINE static inline void _ff_lock(osal_mutex_t mutex) { if (mutex) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER); } -static inline void _ff_unlock(osal_mutex_t mutex) +TU_ATTR_ALWAYS_INLINE static inline void _ff_unlock(osal_mutex_t mutex) { if (mutex) osal_mutex_unlock(mutex); } @@ -361,30 +361,14 @@ static inline uint16_t idx2ptr(uint16_t idx, uint16_t depth) // Works on local copies of w and r - return only the difference and as such can be used to determine an overflow static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx) { - uint16_t cnt; - // In case we have non-power of two depth we need a further modification if (wr_idx >= rd_idx) { - cnt = (uint16_t) (wr_idx - rd_idx); + return (uint16_t) (wr_idx - rd_idx); } else { - cnt = (uint16_t) (2*f->depth - (rd_idx - wr_idx)); + return (uint16_t) (2*f->depth - (rd_idx - wr_idx)); } - - return cnt; -} - -// Works on local copies of w and r -static inline bool _tu_fifo_empty(uint16_t wr_idx, uint16_t rd_idx) -{ - return wr_idx == rd_idx; -} - -// Works on local copies of w and r -static inline bool _tu_fifo_full(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs) -{ - return _tu_fifo_count(f, wAbs, rAbs) == f->depth; } // Works on local copies of w and r @@ -601,7 +585,7 @@ uint16_t tu_fifo_count(tu_fifo_t* f) /******************************************************************************/ bool tu_fifo_empty(tu_fifo_t* f) { - return _tu_fifo_empty(f->wr_idx, f->rd_idx); + return f->wr_idx == f->rd_idx; } /******************************************************************************/ @@ -619,7 +603,7 @@ bool tu_fifo_empty(tu_fifo_t* f) /******************************************************************************/ bool tu_fifo_full(tu_fifo_t* f) { - return _tu_fifo_full(f, f->wr_idx, f->rd_idx); + return _tu_fifo_count(f, f->wr_idx, f->rd_idx) >= f->depth; } /******************************************************************************/ @@ -798,7 +782,7 @@ bool tu_fifo_write(tu_fifo_t* f, const void * data) bool ret; uint16_t const wr_idx = f->wr_idx; - if ( _tu_fifo_full(f, wr_idx, f->rd_idx) && !f->overwritable ) + if ( tu_fifo_full(f) && !f->overwritable ) { ret = false; }else -- cgit v1.3.1 From 507d5b10b049d865e5bb24f99038eed07d092e8f Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 7 Jan 2023 17:14:17 +0700 Subject: simplify _tu_fifo_count() and _tu_fifo_remaining(), also rename to _ff_count() and _ff_remaining() --- src/common/tusb_fifo.c | 57 ++++++++++++++++++++++++++++---------------------- 1 file changed, 32 insertions(+), 25 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index 4b27bc589..cdb0df73f 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -358,8 +358,9 @@ static inline uint16_t idx2ptr(uint16_t idx, uint16_t depth) return idx; } -// Works on local copies of w and r - return only the difference and as such can be used to determine an overflow -static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx) +// return only the index difference and as such can be used to determine an overflow i.e overflowable count +TU_ATTR_ALWAYS_INLINE static inline +uint16_t _ff_count(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx) { // In case we have non-power of two depth we need a further modification if (wr_idx >= rd_idx) @@ -367,24 +368,33 @@ static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd return (uint16_t) (wr_idx - rd_idx); } else { - return (uint16_t) (2*f->depth - (rd_idx - wr_idx)); + return (uint16_t) (2*depth - (rd_idx - wr_idx)); } } -// Works on local copies of w and r // BE AWARE - THIS FUNCTION MIGHT NOT GIVE A CORRECT ANSWERE IN CASE WRITE POINTER "OVERFLOWS" // Only one overflow is allowed for this function to work e.g. if depth = 100, you must not // write more than 2*depth-1 items in one rush without updating write pointer. Otherwise // write pointer wraps and you pointer states are messed up. This can only happen if you // use DMAs, write functions do not allow such an error. -static inline bool _tu_fifo_overflowed(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx) +TU_ATTR_ALWAYS_INLINE static inline +bool _ff_overflowed(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx) +{ + return _ff_count(depth, wr_idx, rd_idx) > depth; +} + +// return remaining slot in fifo +TU_ATTR_ALWAYS_INLINE static inline +uint16_t _ff_remaining(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx) { - return _tu_fifo_count(f, wr_idx, rd_idx) > f->depth; + uint16_t const count = _ff_count(depth, wr_idx, rd_idx); + return (depth > count) ? (depth - count) : 0; } // Works on local copies of w // For more details see _tu_fifo_overflow()! -static inline void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wAbs) +TU_ATTR_ALWAYS_INLINE static inline +void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wAbs) { f->rd_idx = backward_pointer(f, wAbs, f->depth); } @@ -393,7 +403,7 @@ static inline void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wAbs) // Must be protected by mutexes since in case of an overflow read pointer gets modified static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16_t rd_idx) { - uint16_t cnt = _tu_fifo_count(f, wr_idx, rd_idx); + uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx); // Check overflow and correct if required if (cnt > f->depth) @@ -417,7 +427,7 @@ static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16 // Must be protected by mutexes since in case of an overflow read pointer gets modified static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint16_t wr_idx, uint16_t rd_idx, tu_fifo_copy_mode_t copy_mode) { - uint16_t cnt = _tu_fifo_count(f, wr_idx, rd_idx); + uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx); // Check overflow and correct if required if (cnt > f->depth) @@ -441,13 +451,6 @@ static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint1 return n; } -// Works on local copies of w and r -static inline uint16_t _tu_fifo_remaining(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx) -{ - uint16_t const count = _tu_fifo_count(f, wr_idx, rd_idx); - return (f->depth > count) ? (f->depth - count) : 0; -} - static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu_fifo_copy_mode_t copy_mode) { if ( n == 0 ) return 0; @@ -460,12 +463,12 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu uint8_t const* buf8 = (uint8_t const*) data; TU_LOG(TU_FIFO_DBG, "rd = %3u, wr = %3u, count = %3u, remain = %3u, n = %3u: ", - rd_idx, wr_idx, _tu_fifo_count(f, wr_idx, rd_idx), _tu_fifo_remaining(f, wr_idx, rd_idx), n); + rd_idx, wr_idx, _ff_count(f->depth, wr_idx, rd_idx), _ff_remaining(f->depth, wr_idx, rd_idx), n); if ( !f->overwritable ) { // limit up to full - uint16_t const remain = _tu_fifo_remaining(f, wr_idx, rd_idx); + uint16_t const remain = _ff_remaining(f->depth, wr_idx, rd_idx); n = tu_min16(n, remain); } else @@ -493,7 +496,7 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu } else { - uint16_t const overflowable_count = _tu_fifo_count(f, wr_idx, rd_idx); + uint16_t const overflowable_count = _ff_count(f->depth, wr_idx, rd_idx); if (overflowable_count + n >= 2*f->depth) { // Double overflowed @@ -550,6 +553,10 @@ static uint16_t _tu_fifo_read_n(tu_fifo_t* f, void * buffer, uint16_t n, tu_fifo return n; } +//--------------------------------------------------------------------+ +// Application API +//--------------------------------------------------------------------+ + /******************************************************************************/ /*! @brief Get number of items in FIFO. @@ -567,7 +574,7 @@ static uint16_t _tu_fifo_read_n(tu_fifo_t* f, void * buffer, uint16_t n, tu_fifo /******************************************************************************/ uint16_t tu_fifo_count(tu_fifo_t* f) { - return tu_min16(_tu_fifo_count(f, f->wr_idx, f->rd_idx), f->depth); + return tu_min16(_ff_count(f->depth, f->wr_idx, f->rd_idx), f->depth); } /******************************************************************************/ @@ -603,7 +610,7 @@ bool tu_fifo_empty(tu_fifo_t* f) /******************************************************************************/ bool tu_fifo_full(tu_fifo_t* f) { - return _tu_fifo_count(f, f->wr_idx, f->rd_idx) >= f->depth; + return _ff_count(f->depth, f->wr_idx, f->rd_idx) >= f->depth; } /******************************************************************************/ @@ -621,7 +628,7 @@ bool tu_fifo_full(tu_fifo_t* f) /******************************************************************************/ uint16_t tu_fifo_remaining(tu_fifo_t* f) { - return _tu_fifo_remaining(f, f->wr_idx, f->rd_idx); + return _ff_remaining(f->depth, f->wr_idx, f->rd_idx); } /******************************************************************************/ @@ -647,7 +654,7 @@ uint16_t tu_fifo_remaining(tu_fifo_t* f) /******************************************************************************/ bool tu_fifo_overflowed(tu_fifo_t* f) { - return _tu_fifo_overflowed(f, f->wr_idx, f->rd_idx); + return _ff_overflowed(f->depth, f->wr_idx, f->rd_idx); } // Only use in case tu_fifo_overflow() returned true! @@ -949,7 +956,7 @@ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) uint16_t wr_idx = f->wr_idx; uint16_t rd_idx = f->rd_idx; - uint16_t cnt = _tu_fifo_count(f, wr_idx, rd_idx); + uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx); // Check overflow and correct if required - may happen in case a DMA wrote too fast if (cnt > f->depth) @@ -1015,7 +1022,7 @@ void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) { uint16_t wr_idx = f->wr_idx; uint16_t rd_idx = f->rd_idx; - uint16_t remain = _tu_fifo_remaining(f, wr_idx, rd_idx); + uint16_t remain = _ff_remaining(f->depth, wr_idx, rd_idx); if (remain == 0) { -- cgit v1.3.1 From 24bd1c95623377a81286f9d516da57c34451c515 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 7 Jan 2023 17:27:26 +0700 Subject: update advance_pointer/backward_pointer to use depth instead of fifo, also rename to advance/backward_index --- src/common/tusb_fifo.c | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index cdb0df73f..8de58c4a4 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -319,35 +319,35 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu // Advance an absolute index // "absolute" index is only in the range of [0..2*depth) -static uint16_t advance_pointer(tu_fifo_t* f, uint16_t idx, uint16_t offset) +static uint16_t advance_index(uint16_t depth, uint16_t idx, uint16_t offset) { // We limit the index space of p such that a correct wrap around happens // Check for a wrap around or if we are in unused index space - This has to be checked first!! // We are exploiting the wrap around to the correct index - uint16_t next_p = (uint16_t) (idx + offset); - if ( (idx > next_p) || (next_p >= 2*f->depth) ) + uint16_t new_idx = (uint16_t) (idx + offset); + if ( (idx > new_idx) || (new_idx >= 2*depth) ) { - uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1)); - next_p = (uint16_t) (next_p + non_used_index_space); + uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*depth-1)); + new_idx = (uint16_t) (new_idx + non_used_index_space); } - return next_p; + return new_idx; } -// Backward an absolute pointer -static uint16_t backward_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset) +// Backward an absolute index +static uint16_t backward_index(uint16_t depth, uint16_t idx, uint16_t offset) { // We limit the index space of p such that a correct wrap around happens // Check for a wrap around or if we are in unused index space - This has to be checked first!! // We are exploiting the wrap around to the correct index - uint16_t new_p = (uint16_t) (p - offset); - if ( (p < new_p) || (new_p >= 2*f->depth) ) + uint16_t new_idx = (uint16_t) (idx - offset); + if ( (idx < new_idx) || (new_idx >= 2*depth) ) { - uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1)); - new_p = (uint16_t) (new_p - non_used_index_space); + uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*depth-1)); + new_idx = (uint16_t) (new_idx - non_used_index_space); } - return new_p; + return new_idx; } // index to pointer, simply an modulo with minus. @@ -394,9 +394,9 @@ uint16_t _ff_remaining(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx) // Works on local copies of w // For more details see _tu_fifo_overflow()! TU_ATTR_ALWAYS_INLINE static inline -void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wAbs) +void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wr_idx) { - f->rd_idx = backward_pointer(f, wAbs, f->depth); + f->rd_idx = backward_index(f->depth, wr_idx, f->depth); } // Works on local copies of w and r @@ -502,7 +502,7 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu // Double overflowed // Index is bigger than the allowed range [0,2*depth) // re-position write index to have a full fifo after pushed - wr_idx = advance_pointer(f, rd_idx, f->depth - n); + wr_idx = advance_index(f->depth, rd_idx, f->depth - n); // TODO we should also shift out n bytes from read index since we avoid changing rd index !! // However memmove() is expensive due to actual copying + wrapping consideration. @@ -528,7 +528,7 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu _ff_push_n(f, buf8, n, wr_ptr, copy_mode); // Advance index - f->wr_idx = advance_pointer(f, wr_idx, n); + f->wr_idx = advance_index(f->depth, wr_idx, n); TU_LOG(TU_FIFO_DBG, "\tnew_wr = %u\n", f->wr_idx); } @@ -547,7 +547,7 @@ static uint16_t _tu_fifo_read_n(tu_fifo_t* f, void * buffer, uint16_t n, tu_fifo n = _tu_fifo_peek_n(f, buffer, n, f->wr_idx, f->rd_idx, copy_mode); // Advance read pointer - f->rd_idx = advance_pointer(f, f->rd_idx, n); + f->rd_idx = advance_index(f->depth, f->rd_idx, n); _ff_unlock(f->mutex_rd); return n; @@ -690,7 +690,7 @@ bool tu_fifo_read(tu_fifo_t* f, void * buffer) bool ret = _tu_fifo_peek(f, buffer, f->wr_idx, f->rd_idx); // Advance pointer - f->rd_idx = advance_pointer(f, f->rd_idx, ret); + f->rd_idx = advance_index(f->depth, f->rd_idx, ret); _ff_unlock(f->mutex_rd); return ret; @@ -800,7 +800,7 @@ bool tu_fifo_write(tu_fifo_t* f, const void * data) _ff_push(f, data, wr_ptr); // Advance pointer - f->wr_idx = advance_pointer(f, wr_idx, 1); + f->wr_idx = advance_index(f->depth, wr_idx, 1); ret = true; } @@ -911,7 +911,7 @@ bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable) /******************************************************************************/ void tu_fifo_advance_write_pointer(tu_fifo_t *f, uint16_t n) { - f->wr_idx = advance_pointer(f, f->wr_idx, n); + f->wr_idx = advance_index(f->depth, f->wr_idx, n); } /******************************************************************************/ @@ -932,7 +932,7 @@ void tu_fifo_advance_write_pointer(tu_fifo_t *f, uint16_t n) /******************************************************************************/ void tu_fifo_advance_read_pointer(tu_fifo_t *f, uint16_t n) { - f->rd_idx = advance_pointer(f, f->rd_idx, n); + f->rd_idx = advance_index(f->depth, f->rd_idx, n); } /******************************************************************************/ -- cgit v1.3.1 From 248025bb6cdf361e93603204d89cbf58e9e3b0af Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 7 Jan 2023 17:29:43 +0700 Subject: reverse idx2ptr() arguments to be consistent --- src/common/tusb_fifo.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index 8de58c4a4..a0ce73ba0 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -351,7 +351,8 @@ static uint16_t backward_index(uint16_t depth, uint16_t idx, uint16_t offset) } // index to pointer, simply an modulo with minus. -static inline uint16_t idx2ptr(uint16_t idx, uint16_t depth) +TU_ATTR_ALWAYS_INLINE static inline +uint16_t idx2ptr(uint16_t depth, uint16_t idx) { // Only run at most 3 times since index is limit in the range of [0..2*depth) while ( idx >= depth ) idx -= depth; @@ -415,7 +416,7 @@ static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16 // Skip beginning of buffer if (cnt == 0) return false; - uint16_t rd_ptr = idx2ptr(rd_idx, f->depth); + uint16_t rd_ptr = idx2ptr(f->depth, rd_idx); // Peek data _ff_pull(f, p_buffer, rd_ptr); @@ -443,7 +444,7 @@ static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint1 // Check if we can read something at and after offset - if too less is available we read what remains if (cnt < n) n = cnt; - uint16_t rd_ptr = idx2ptr(rd_idx, f->depth); + uint16_t rd_ptr = idx2ptr(f->depth, rd_idx); // Peek data _ff_pull_n(f, p_buffer, n, rd_ptr, copy_mode); @@ -520,7 +521,7 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu if (n) { - uint16_t wr_ptr = idx2ptr(wr_idx, f->depth); + uint16_t wr_ptr = idx2ptr(f->depth, wr_idx); TU_LOG(TU_FIFO_DBG, "actual_n = %u, wr_ptr = %u", n, wr_ptr); @@ -794,7 +795,7 @@ bool tu_fifo_write(tu_fifo_t* f, const void * data) ret = false; }else { - uint16_t wr_ptr = idx2ptr(wr_idx, f->depth); + uint16_t wr_ptr = idx2ptr(f->depth, wr_idx); // Write data _ff_push(f, data, wr_ptr); @@ -980,8 +981,8 @@ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) } // Get relative pointers - uint16_t wr_ptr = idx2ptr(wr_idx, f->depth); - uint16_t rd_ptr = idx2ptr(rd_idx, f->depth); + uint16_t wr_ptr = idx2ptr(f->depth, wr_idx); + uint16_t rd_ptr = idx2ptr(f->depth, rd_idx); // Copy pointer to buffer to start reading from info->ptr_lin = &f->buffer[rd_ptr]; @@ -1034,8 +1035,8 @@ void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) } // Get relative pointers - uint16_t wr_ptr = idx2ptr(wr_idx, f->depth); - uint16_t rd_ptr = idx2ptr(rd_idx, f->depth); + uint16_t wr_ptr = idx2ptr(f->depth, wr_idx); + uint16_t rd_ptr = idx2ptr(f->depth, rd_idx); // Copy pointer to buffer to start writing to info->ptr_lin = &f->buffer[wr_ptr]; -- cgit v1.3.1 From c29b7643a59f4baa266d13ef0a7bed864ad83eb2 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 7 Jan 2023 18:50:19 +0700 Subject: simplify _ff_correct_read_index() --- src/common/tusb_fifo.c | 107 ++++++++++++++++++++++++++++--------------------- 1 file changed, 62 insertions(+), 45 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index a0ce73ba0..22d6e8e55 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -314,7 +314,44 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu } //--------------------------------------------------------------------+ -// Index (free-running and real buffer pointer) +// Helper +//--------------------------------------------------------------------+ + +// return only the index difference and as such can be used to determine an overflow i.e overflowable count +TU_ATTR_ALWAYS_INLINE static inline +uint16_t _ff_count(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx) +{ + // In case we have non-power of two depth we need a further modification + if (wr_idx >= rd_idx) + { + return (uint16_t) (wr_idx - rd_idx); + } else + { + return (uint16_t) (2*depth - (rd_idx - wr_idx)); + } +} + +// BE AWARE - THIS FUNCTION MIGHT NOT GIVE A CORRECT ANSWERE IN CASE WRITE POINTER "OVERFLOWS" +// Only one overflow is allowed for this function to work e.g. if depth = 100, you must not +// write more than 2*depth-1 items in one rush without updating write pointer. Otherwise +// write pointer wraps and you pointer states are messed up. This can only happen if you +// use DMAs, write functions do not allow such an error. +TU_ATTR_ALWAYS_INLINE static inline +bool _ff_overflowed(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx) +{ + return _ff_count(depth, wr_idx, rd_idx) > depth; +} + +// return remaining slot in fifo +TU_ATTR_ALWAYS_INLINE static inline +uint16_t _ff_remaining(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx) +{ + uint16_t const count = _ff_count(depth, wr_idx, rd_idx); + return (depth > count) ? (depth - count) : 0; +} + +//--------------------------------------------------------------------+ +// Index Helper //--------------------------------------------------------------------+ // Advance an absolute index @@ -334,6 +371,7 @@ static uint16_t advance_index(uint16_t depth, uint16_t idx, uint16_t offset) return new_idx; } +#if 0 // not used but // Backward an absolute index static uint16_t backward_index(uint16_t depth, uint16_t idx, uint16_t offset) { @@ -349,6 +387,7 @@ static uint16_t backward_index(uint16_t depth, uint16_t idx, uint16_t offset) return new_idx; } +#endif // index to pointer, simply an modulo with minus. TU_ATTR_ALWAYS_INLINE static inline @@ -359,45 +398,24 @@ uint16_t idx2ptr(uint16_t depth, uint16_t idx) return idx; } -// return only the index difference and as such can be used to determine an overflow i.e overflowable count +// Works on local copies of w +// When an overwritable fifo is overflowed, rd_idx will be re-index so that it forms +// an full fifo i.e _ff_count() = depth TU_ATTR_ALWAYS_INLINE static inline -uint16_t _ff_count(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx) +uint16_t _ff_correct_read_index(tu_fifo_t* f, uint16_t wr_idx) { - // In case we have non-power of two depth we need a further modification - if (wr_idx >= rd_idx) + uint16_t rd_idx; + if ( wr_idx >= f->depth ) { - return (uint16_t) (wr_idx - rd_idx); - } else + rd_idx = wr_idx - f->depth; + }else { - return (uint16_t) (2*depth - (rd_idx - wr_idx)); + rd_idx = wr_idx + f->depth; } -} -// BE AWARE - THIS FUNCTION MIGHT NOT GIVE A CORRECT ANSWERE IN CASE WRITE POINTER "OVERFLOWS" -// Only one overflow is allowed for this function to work e.g. if depth = 100, you must not -// write more than 2*depth-1 items in one rush without updating write pointer. Otherwise -// write pointer wraps and you pointer states are messed up. This can only happen if you -// use DMAs, write functions do not allow such an error. -TU_ATTR_ALWAYS_INLINE static inline -bool _ff_overflowed(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx) -{ - return _ff_count(depth, wr_idx, rd_idx) > depth; -} + f->rd_idx = rd_idx; -// return remaining slot in fifo -TU_ATTR_ALWAYS_INLINE static inline -uint16_t _ff_remaining(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx) -{ - uint16_t const count = _ff_count(depth, wr_idx, rd_idx); - return (depth > count) ? (depth - count) : 0; -} - -// Works on local copies of w -// For more details see _tu_fifo_overflow()! -TU_ATTR_ALWAYS_INLINE static inline -void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wr_idx) -{ - f->rd_idx = backward_index(f->depth, wr_idx, f->depth); + return rd_idx; } // Works on local copies of w and r @@ -407,14 +425,14 @@ static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16 uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx); // Check overflow and correct if required - if (cnt > f->depth) + if ( cnt > f->depth ) { - _tu_fifo_correct_read_pointer(f, wr_idx); + rd_idx = _ff_correct_read_index(f, wr_idx); cnt = f->depth; } // Skip beginning of buffer - if (cnt == 0) return false; + if ( cnt == 0 ) return false; uint16_t rd_ptr = idx2ptr(f->depth, rd_idx); @@ -431,18 +449,17 @@ static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint1 uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx); // Check overflow and correct if required - if (cnt > f->depth) + if ( cnt > f->depth ) { - _tu_fifo_correct_read_pointer(f, wr_idx); - rd_idx = f->rd_idx; + rd_idx = _ff_correct_read_index(f, wr_idx); cnt = f->depth; } // Skip beginning of buffer - if (cnt == 0) return 0; + if ( cnt == 0 ) return 0; // Check if we can read something at and after offset - if too less is available we read what remains - if (cnt < n) n = cnt; + if ( cnt < n ) n = cnt; uint16_t rd_ptr = idx2ptr(f->depth, rd_idx); @@ -662,7 +679,7 @@ bool tu_fifo_overflowed(tu_fifo_t* f) void tu_fifo_correct_read_pointer(tu_fifo_t* f) { _ff_lock(f->mutex_rd); - _tu_fifo_correct_read_pointer(f, f->wr_idx); + _ff_correct_read_index(f, f->wr_idx); _ff_unlock(f->mutex_rd); } @@ -963,10 +980,9 @@ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) if (cnt > f->depth) { _ff_lock(f->mutex_rd); - _tu_fifo_correct_read_pointer(f, wr_idx); + rd_idx = _ff_correct_read_index(f, wr_idx); _ff_unlock(f->mutex_rd); - rd_idx = f->rd_idx; cnt = f->depth; } @@ -988,7 +1004,8 @@ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) info->ptr_lin = &f->buffer[rd_ptr]; // Check if there is a wrap around necessary - if (wr_ptr > rd_ptr) { + if (wr_ptr > rd_ptr) + { // Non wrapping case info->len_lin = cnt; -- cgit v1.3.1 From 9e551c9f5cda2bd2bb1f53e34c5010babc534eb9 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 7 Jan 2023 19:00:04 +0700 Subject: remove _ff_overflowed() due to lack of use --- src/common/tusb_fifo.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index 22d6e8e55..d5eea83f7 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -331,17 +331,6 @@ uint16_t _ff_count(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx) } } -// BE AWARE - THIS FUNCTION MIGHT NOT GIVE A CORRECT ANSWERE IN CASE WRITE POINTER "OVERFLOWS" -// Only one overflow is allowed for this function to work e.g. if depth = 100, you must not -// write more than 2*depth-1 items in one rush without updating write pointer. Otherwise -// write pointer wraps and you pointer states are messed up. This can only happen if you -// use DMAs, write functions do not allow such an error. -TU_ATTR_ALWAYS_INLINE static inline -bool _ff_overflowed(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx) -{ - return _ff_count(depth, wr_idx, rd_idx) > depth; -} - // return remaining slot in fifo TU_ATTR_ALWAYS_INLINE static inline uint16_t _ff_remaining(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx) @@ -672,7 +661,7 @@ uint16_t tu_fifo_remaining(tu_fifo_t* f) /******************************************************************************/ bool tu_fifo_overflowed(tu_fifo_t* f) { - return _ff_overflowed(f->depth, f->wr_idx, f->rd_idx); + return _ff_count(f->depth, f->wr_idx, f->rd_idx) > f->depth; } // Only use in case tu_fifo_overflow() returned true! -- cgit v1.3.1 From c84de8f06bb42de78fec22dec8026f3a0c0899cc Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 7 Jan 2023 19:40:06 +0700 Subject: minor clean up --- src/common/tusb_fifo.c | 100 +++++++++++++++++++++++++------------------------ 1 file changed, 51 insertions(+), 49 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index d5eea83f7..a52c92267 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -97,13 +97,13 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si // TODO generalize with configurable 1 byte or 4 byte each read static void _ff_push_const_addr(uint8_t * ff_buf, const void * app_buf, uint16_t len) { - volatile const uint32_t * rx_fifo = (volatile const uint32_t *) app_buf; + volatile const uint32_t * reg_rx = (volatile const uint32_t *) app_buf; // Reading full available 32 bit words from const app address uint16_t full_words = len >> 2; while(full_words--) { - tu_unaligned_write32(ff_buf, *rx_fifo); + tu_unaligned_write32(ff_buf, *reg_rx); ff_buf += 4; } @@ -111,7 +111,7 @@ static void _ff_push_const_addr(uint8_t * ff_buf, const void * app_buf, uint16_t uint8_t const bytes_rem = len & 0x03; if ( bytes_rem ) { - uint32_t tmp32 = *rx_fifo; + uint32_t tmp32 = *reg_rx; memcpy(ff_buf, &tmp32, bytes_rem); } } @@ -120,24 +120,24 @@ static void _ff_push_const_addr(uint8_t * ff_buf, const void * app_buf, uint16_t // where all data is written to a constant address in full word copies static void _ff_pull_const_addr(void * app_buf, const uint8_t * ff_buf, uint16_t len) { - volatile uint32_t * tx_fifo = (volatile uint32_t *) app_buf; + volatile uint32_t * reg_tx = (volatile uint32_t *) app_buf; - // Pushing full available 32 bit words to const app address + // Write full available 32 bit words to const address uint16_t full_words = len >> 2; while(full_words--) { - *tx_fifo = tu_unaligned_read32(ff_buf); + *reg_tx = tu_unaligned_read32(ff_buf); ff_buf += 4; } - // Write the remaining 1-3 bytes into const app address + // Write the remaining 1-3 bytes into const address uint8_t const bytes_rem = len & 0x03; if ( bytes_rem ) { uint32_t tmp32 = 0; memcpy(&tmp32, ff_buf, bytes_rem); - *tx_fifo = tmp32; + *reg_tx = tmp32; } } @@ -148,21 +148,21 @@ static inline void _ff_push(tu_fifo_t* f, void const * app_buf, uint16_t rel) } // send n items to fifo WITHOUT updating write pointer -static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode) +static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t wr_ptr, tu_fifo_copy_mode_t copy_mode) { - uint16_t const nLin = f->depth - rel; - uint16_t const nWrap = n - nLin; + uint16_t const lin_count = f->depth - wr_ptr; + uint16_t const wrap_count = n - lin_count; - uint16_t nLin_bytes = nLin * f->item_size; - uint16_t nWrap_bytes = nWrap * f->item_size; + uint16_t lin_bytes = lin_count * f->item_size; + uint16_t wrap_bytes = wrap_count * f->item_size; // current buffer of fifo - uint8_t* ff_buf = f->buffer + (rel * f->item_size); + uint8_t* ff_buf = f->buffer + (wr_ptr * f->item_size); switch (copy_mode) { case TU_FIFO_COPY_INC: - if(n <= nLin) + if(n <= lin_count) { // Linear only memcpy(ff_buf, app_buf, n*f->item_size); @@ -172,17 +172,17 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t // Wrap around // Write data to linear part of buffer - memcpy(ff_buf, app_buf, nLin_bytes); + memcpy(ff_buf, app_buf, lin_bytes); // Write data wrapped around // TU_ASSERT(nWrap_bytes <= f->depth, ); - memcpy(f->buffer, ((uint8_t const*) app_buf) + nLin_bytes, nWrap_bytes); + memcpy(f->buffer, ((uint8_t const*) app_buf) + lin_bytes, wrap_bytes); } break; case TU_FIFO_COPY_CST_FULL_WORDS: // Intended for hardware buffers from which it can be read word by word only - if(n <= nLin) + if(n <= lin_count) { // Linear only _ff_push_const_addr(ff_buf, app_buf, n*f->item_size); @@ -192,17 +192,18 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t // Wrap around case // Write full words to linear part of buffer - uint16_t nLin_4n_bytes = nLin_bytes & 0xFFFC; + uint16_t nLin_4n_bytes = lin_bytes & 0xFFFC; _ff_push_const_addr(ff_buf, app_buf, nLin_4n_bytes); ff_buf += nLin_4n_bytes; // There could be odd 1-3 bytes before the wrap-around boundary - volatile const uint32_t * rx_fifo = (volatile const uint32_t *) app_buf; - uint8_t rem = nLin_bytes & 0x03; + uint8_t rem = lin_bytes & 0x03; if (rem > 0) { - uint8_t remrem = (uint8_t) tu_min16(nWrap_bytes, 4-rem); - nWrap_bytes -= remrem; + volatile const uint32_t * rx_fifo = (volatile const uint32_t *) app_buf; + + uint8_t remrem = (uint8_t) tu_min16(wrap_bytes, 4-rem); + wrap_bytes -= remrem; uint32_t tmp32 = *rx_fifo; uint8_t * src_u8 = ((uint8_t *) &tmp32); @@ -220,7 +221,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t } // Write data wrapped part - if (nWrap_bytes > 0) _ff_push_const_addr(ff_buf, app_buf, nWrap_bytes); + if (wrap_bytes > 0) _ff_push_const_addr(ff_buf, app_buf, wrap_bytes); } break; } @@ -233,21 +234,21 @@ static inline void _ff_pull(tu_fifo_t* f, void * app_buf, uint16_t rel) } // get n items from fifo WITHOUT updating read pointer -static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode) +static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rd_ptr, tu_fifo_copy_mode_t copy_mode) { - uint16_t const nLin = f->depth - rel; - uint16_t const nWrap = n - nLin; // only used if wrapped + uint16_t const lin_count = f->depth - rd_ptr; + uint16_t const wrap_count = n - lin_count; // only used if wrapped - uint16_t nLin_bytes = nLin * f->item_size; - uint16_t nWrap_bytes = nWrap * f->item_size; + uint16_t lin_bytes = lin_count * f->item_size; + uint16_t wrap_bytes = wrap_count * f->item_size; // current buffer of fifo - uint8_t* ff_buf = f->buffer + (rel * f->item_size); + uint8_t* ff_buf = f->buffer + (rd_ptr * f->item_size); switch (copy_mode) { case TU_FIFO_COPY_INC: - if ( n <= nLin ) + if ( n <= lin_count ) { // Linear only memcpy(app_buf, ff_buf, n*f->item_size); @@ -257,15 +258,15 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu // Wrap around // Read data from linear part of buffer - memcpy(app_buf, ff_buf, nLin_bytes); + memcpy(app_buf, ff_buf, lin_bytes); // Read data wrapped part - memcpy((uint8_t*) app_buf + nLin_bytes, f->buffer, nWrap_bytes); + memcpy((uint8_t*) app_buf + lin_bytes, f->buffer, wrap_bytes); } break; case TU_FIFO_COPY_CST_FULL_WORDS: - if ( n <= nLin ) + if ( n <= lin_count ) { // Linear only _ff_pull_const_addr(app_buf, ff_buf, n*f->item_size); @@ -275,17 +276,18 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu // Wrap around case // Read full words from linear part of buffer - uint16_t nLin_4n_bytes = nLin_bytes & 0xFFFC; - _ff_pull_const_addr(app_buf, ff_buf, nLin_4n_bytes); - ff_buf += nLin_4n_bytes; + uint16_t lin_4n_bytes = lin_bytes & 0xFFFC; + _ff_pull_const_addr(app_buf, ff_buf, lin_4n_bytes); + ff_buf += lin_4n_bytes; // There could be odd 1-3 bytes before the wrap-around boundary - volatile uint32_t * tx_fifo = (volatile uint32_t *) app_buf; - uint8_t rem = nLin_bytes & 0x03; + uint8_t rem = lin_bytes & 0x03; if (rem > 0) { - uint8_t remrem = (uint8_t) tu_min16(nWrap_bytes, 4-rem); - nWrap_bytes -= remrem; + volatile uint32_t * reg_tx = (volatile uint32_t *) app_buf; + + uint8_t remrem = (uint8_t) tu_min16(wrap_bytes, 4-rem); + wrap_bytes -= remrem; uint32_t tmp32=0; uint8_t * dst_u8 = (uint8_t *)&tmp32; @@ -297,7 +299,7 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu ff_buf = f->buffer; while(remrem--) *dst_u8++ = *ff_buf++; - *tx_fifo = tmp32; + *reg_tx = tmp32; } else { @@ -305,7 +307,7 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu } // Read data wrapped part - if (nWrap_bytes > 0) _ff_pull_const_addr(app_buf, ff_buf, nWrap_bytes); + if (wrap_bytes > 0) _ff_pull_const_addr(app_buf, ff_buf, wrap_bytes); } break; @@ -413,6 +415,9 @@ static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16 { uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx); + // nothing to peek + if ( cnt == 0 ) return false; + // Check overflow and correct if required if ( cnt > f->depth ) { @@ -420,9 +425,6 @@ static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16 cnt = f->depth; } - // Skip beginning of buffer - if ( cnt == 0 ) return false; - uint16_t rd_ptr = idx2ptr(f->depth, rd_idx); // Peek data @@ -437,6 +439,9 @@ static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint1 { uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx); + // nothing to peek + if ( cnt == 0 ) return 0; + // Check overflow and correct if required if ( cnt > f->depth ) { @@ -444,9 +449,6 @@ static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint1 cnt = f->depth; } - // Skip beginning of buffer - if ( cnt == 0 ) return 0; - // Check if we can read something at and after offset - if too less is available we read what remains if ( cnt < n ) n = cnt; -- cgit v1.3.1 From 57de6016f9470904228f7b8d6dbe467251922757 Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Sun, 8 Jan 2023 11:20:15 +0100 Subject: ip3511 : Fix IAR build. --- src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 34 ++++++++++++++-------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c index 9b490c48c..124656307 100644 --- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c +++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c @@ -139,7 +139,7 @@ typedef union TU_ATTR_PACKED uint32_t stall : 1 ; uint32_t disable : 1 ; uint32_t active : 1 ; - }; + } cmd_sts; }ep_cmd_sts_t; TU_VERIFY_STATIC( sizeof(ep_cmd_sts_t) == 4, "size is not correct" ); @@ -329,7 +329,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) // TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around uint8_t const ep_id = ep_addr2id(ep_addr); - _dcd.ep[ep_id][0].stall = 1; + _dcd.ep[ep_id][0].cmd_sts.stall = 1; } void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) @@ -338,9 +338,9 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) uint8_t const ep_id = ep_addr2id(ep_addr); - _dcd.ep[ep_id][0].stall = 0; - _dcd.ep[ep_id][0].toggle_reset = 1; - _dcd.ep[ep_id][0].toggle_mode = 0; + _dcd.ep[ep_id][0].cmd_sts.stall = 0; + _dcd.ep[ep_id][0].cmd_sts.toggle_reset = 1; + _dcd.ep[ep_id][0].cmd_sts.toggle_mode = 0; } bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) @@ -349,10 +349,10 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) uint8_t ep_id = ep_addr2id(p_endpoint_desc->bEndpointAddress); // Check if endpoint is available - TU_ASSERT( _dcd.ep[ep_id][0].disable && _dcd.ep[ep_id][1].disable ); + TU_ASSERT( _dcd.ep[ep_id][0].cmd_sts.disable && _dcd.ep[ep_id][1].cmd_sts.disable ); edpt_reset(rhport, ep_id); - _dcd.ep[ep_id][0].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS); + _dcd.ep[ep_id][0].cmd_sts.is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS); // Enable EP interrupt dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; @@ -365,8 +365,8 @@ void dcd_edpt_close_all (uint8_t rhport) { for (uint8_t ep_id = 0; ep_id < 2*_dcd_controller[rhport].ep_pairs; ++ep_id) { - _dcd.ep[ep_id][0].active = _dcd.ep[ep_id][0].active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual) - _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1; + _dcd.ep[ep_id][0].cmd_sts.active = _dcd.ep[ep_id][0].cmd_sts.active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual) + _dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1; } } @@ -375,8 +375,8 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) (void) rhport; uint8_t ep_id = ep_addr2id(ep_addr); - _dcd.ep[ep_id][0].active = _dcd.ep[ep_id][0].active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual) - _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1; + _dcd.ep[ep_id][0].cmd_sts.active = _dcd.ep[ep_id][0].cmd_sts.active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual) + _dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1; } static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes) @@ -385,7 +385,7 @@ static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL ) { - nbytes = tu_min16(total_bytes, _dcd.ep[ep_id][0].is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX); + nbytes = tu_min16(total_bytes, _dcd.ep[ep_id][0].cmd_sts.is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX); _dcd.ep[ep_id][0].buffer_fs.offset = buf_offset; _dcd.ep[ep_id][0].buffer_fs.nbytes = nbytes; }else @@ -397,7 +397,7 @@ static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, _dcd.dma[ep_id].nbytes = nbytes; - _dcd.ep[ep_id][0].active = 1; + _dcd.ep[ep_id][0].cmd_sts.active = 1; } bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) @@ -431,7 +431,7 @@ static void bus_reset(uint8_t rhport) // disable all endpoints as specified by LPC55S69 UM Table 778 for(uint8_t ep_id = 0; ep_id < 2*MAX_EP_PAIRS; ep_id++) { - _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1; + _dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1; } dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; @@ -459,7 +459,7 @@ static void process_xfer_isr(uint8_t rhport, uint32_t int_status) if ( ep_id == 0 || ep_id == 1) { // For control endpoint, we need to manually clear Active bit - ep_cs->active = 0; + ep_cs->cmd_sts.active = 0; } uint16_t buf_offset; @@ -556,8 +556,8 @@ void dcd_int_handler(uint8_t rhport) if ( tu_bit_test(int_status, 0) && (cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) ) { // Follow UM flowchart to clear Active & Stall on both Control IN/OUT endpoints - _dcd.ep[0][0].active = _dcd.ep[1][0].active = 0; - _dcd.ep[0][0].stall = _dcd.ep[1][0].stall = 0; + _dcd.ep[0][0].cmd_sts.active = _dcd.ep[1][0].cmd_sts.active = 0; + _dcd.ep[0][0].cmd_sts.stall = _dcd.ep[1][0].cmd_sts.stall = 0; dcd_reg->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK; -- cgit v1.3.1 From 9d19ed940e303ea01a685ebba986b24713f5febd Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Wed, 11 Jan 2023 18:49:15 +0100 Subject: dwc2: fix IAR warnings. --- src/portable/synopsys/dwc2/dcd_dwc2.c | 9 ++++++--- src/portable/synopsys/dwc2/dwc2_stm32.h | 4 ++-- 2 files changed, 8 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index b53735a5e..c6132a1f5 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -529,8 +529,10 @@ void dcd_init (uint8_t rhport) dwc2->dcfg |= DCFG_NZLSOHSK; // Clear all interrupts - dwc2->gintsts |= dwc2->gintsts; - dwc2->gotgint |= dwc2->gotgint; + uint32_t int_mask = dwc2->gintsts; + dwc2->gintsts |= int_mask; + int_mask = dwc2->gotgint; + dwc2->gotgint |= int_mask; // Required as part of core initialization. // TODO: How should mode mismatch be handled? It will cause @@ -1219,7 +1221,8 @@ void dcd_int_handler(uint8_t rhport) { dwc2_regs_t *dwc2 = DWC2_REG(rhport); - uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk; + uint32_t const int_mask = dwc2->gintmsk; + uint32_t const int_status = dwc2->gintsts & int_mask; if(int_status & GINTSTS_USBRST) { diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index b63d1fcd0..cb455bd90 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -122,13 +122,13 @@ static const dwc2_controller_t _dwc2_controller[] = TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { - NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum); + NVIC_EnableIRQ((IRQn_Type)_dwc2_controller[rhport].irqnum); } TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable (uint8_t rhport) { - NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum); + NVIC_DisableIRQ((IRQn_Type)_dwc2_controller[rhport].irqnum); } TU_ATTR_ALWAYS_INLINE -- cgit v1.3.1 From 3cc6cece0783e893d9fadc868f7fb58c81625fe0 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 12 Jan 2023 10:25:48 +0700 Subject: add note for openocd with wch, also add wch-riscv.cfg --- hw/bsp/ch32v307/family.mk | 18 +++++++++++++++--- hw/bsp/ch32v307/wch-riscv.cfg | 15 +++++++++++++++ src/portable/wch/ch32v307/usb_dc_usbhs.c | 4 ++-- 3 files changed, 32 insertions(+), 5 deletions(-) create mode 100644 hw/bsp/ch32v307/wch-riscv.cfg (limited to 'src') diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk index 12565016d..58542041f 100644 --- a/hw/bsp/ch32v307/family.mk +++ b/hw/bsp/ch32v307/family.mk @@ -30,7 +30,7 @@ CFLAGS += \ -nostdlib -nostartfiles \ -DCFG_TUSB_MCU=OPT_MCU_CH32V307 \ -Xlinker --gc-sections \ - -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED + -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED # caused by extra void USART_Printf_Init() in debug_uart.h and EVT/EXAME/SRC/DEBUG/debug.h CFLAGS += -Wno-error=redundant-decls @@ -51,7 +51,6 @@ SRC_S += \ INC += \ src/portable/wch/ch32v307 \ - $(TOP)/$(BOARD_PATH)/.. \ $(TOP)/$(BOARD_PATH) \ $(CH32V307_SDK_SRC_TOP)/Peripheral/inc \ $(CH32V307_SDK_SRC_TOP)/Debug \ @@ -60,6 +59,19 @@ INC += \ # For freeRTOS port source FREERTOS_PORT = RISC-V +# wch-link is not supported yet in official openOCD yet. We need to either use +# 1. download openocd as part of mounriver studio http://www.mounriver.com/download or +# 2. compiled from modified source https://github.com/kprasadvnsi/riscv-openocd-wch +# +# Note: For Linux, somehow openocd in mounriver studio does not seem to have wch-link enable, +# therefore we need to compile it from source as follows: +# git clone https://github.com/kprasadvnsi/riscv-openocd-wch +# cd riscv-openocd-wch +# ./bootstrap +# ./configure CFLAGS="-Wno-error" --enable-wlink +# make +# openocd binaries will be generated in riscv-openocd-wch/src + # flash target ROM bootloader flash: $(BUILD)/$(PROJECT).elf - openocd -f wch-riscv.cfg -c init -c halt -c "program $< 0x08000000" -c reset -c exit + openocd -f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg -c init -c halt -c "program $<" -c reset -c exit diff --git a/hw/bsp/ch32v307/wch-riscv.cfg b/hw/bsp/ch32v307/wch-riscv.cfg new file mode 100644 index 000000000..0d24d16ca --- /dev/null +++ b/hw/bsp/ch32v307/wch-riscv.cfg @@ -0,0 +1,15 @@ +#interface wlink +adapter driver wlink +wlink_set +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 +set _FLASHNAME $_CHIPNAME.flash + +flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0 + +echo "Ready for Remote Connections" diff --git a/src/portable/wch/ch32v307/usb_dc_usbhs.c b/src/portable/wch/ch32v307/usb_dc_usbhs.c index e647389ee..39fd41392 100644 --- a/src/portable/wch/ch32v307/usb_dc_usbhs.c +++ b/src/portable/wch/ch32v307/usb_dc_usbhs.c @@ -70,7 +70,7 @@ void dcd_init(uint8_t rhport) { USBHSD->CONTROL = 0; -#if (BOARD_DEVICE_RHPORT_SPEED == OPT_MODE_HIGH_SPEED) +#if TUD_OPT_HIGH_SPEED USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED; #else #error OPT_MODE_FULL_SPEED not currently supported on CH32V307 @@ -383,4 +383,4 @@ void dcd_int_handler(uint8_t rhport) { } } -#endif \ No newline at end of file +#endif -- cgit v1.3.1 From e61d4aefe6b9fbab862e7c440ff9ff25ebb5092c Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 12 Jan 2023 12:08:56 +0700 Subject: rename driver with dcd_ to be consitent with other ports --- hw/bsp/ch32v307/family.mk | 22 +- src/portable/wch/ch32v307/ch32_usbhs_reg.h | 345 ++++++++++++++++++++++ src/portable/wch/ch32v307/dcd_usbhs.c | 386 +++++++++++++++++++++++++ src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h | 345 ---------------------- src/portable/wch/ch32v307/usb_dc_usbhs.c | 386 ------------------------- 5 files changed, 740 insertions(+), 744 deletions(-) create mode 100644 src/portable/wch/ch32v307/ch32_usbhs_reg.h create mode 100644 src/portable/wch/ch32v307/dcd_usbhs.c delete mode 100644 src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h delete mode 100644 src/portable/wch/ch32v307/usb_dc_usbhs.c (limited to 'src') diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk index 58542041f..ffc992f21 100644 --- a/hw/bsp/ch32v307/family.mk +++ b/hw/bsp/ch32v307/family.mk @@ -10,8 +10,6 @@ DEPS_SUBMODULES += $(CH32V307_SDK) # WCH-SDK paths CH32V307_SDK_SRC = $(CH32V307_SDK)/EVT/EXAM/SRC -CH32V307_SDK_SRC_TOP = $(TOP)/$(CH32V307_SDK_SRC) -CH32V307_STARTUP_ASM = $(CH32V307_SDK_SRC)/Startup include $(TOP)/$(BOARD_PATH)/board.mk @@ -39,22 +37,20 @@ LDFLAGS += \ -Xlinker --gc-sections --specs=nano.specs --specs=nosys.specs SRC_C += \ - src/portable/wch/ch32v307/usb_dc_usbhs.c \ - $(CH32V307_SDK_SRC_TOP)/Core/core_riscv.c \ - $(CH32V307_SDK_SRC_TOP)/Peripheral/src/ch32v30x_gpio.c \ - $(CH32V307_SDK_SRC_TOP)/Peripheral/src/ch32v30x_misc.c \ - $(CH32V307_SDK_SRC_TOP)/Peripheral/src/ch32v30x_rcc.c \ - $(CH32V307_SDK_SRC_TOP)/Peripheral/src/ch32v30x_usart.c + src/portable/wch/ch32v307/dcd_usbhs.c \ + $(CH32V307_SDK_SRC)/Core/core_riscv.c \ + $(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_gpio.c \ + $(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_misc.c \ + $(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_rcc.c \ + $(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_usart.c SRC_S += \ - $(CH32V307_STARTUP_ASM)/startup_ch32v30x_D8C.S + $(CH32V307_SDK_SRC)/Startup/startup_ch32v30x_D8C.S INC += \ - src/portable/wch/ch32v307 \ $(TOP)/$(BOARD_PATH) \ - $(CH32V307_SDK_SRC_TOP)/Peripheral/inc \ - $(CH32V307_SDK_SRC_TOP)/Debug \ - $(CH32V307_SDK_SRC_TOP) + $(TOP)/$(CH32V307_SDK_SRC)/Peripheral/inc \ + $(TOP)/$(CH32V307_SDK_SRC)/Debug # For freeRTOS port source FREERTOS_PORT = RISC-V diff --git a/src/portable/wch/ch32v307/ch32_usbhs_reg.h b/src/portable/wch/ch32v307/ch32_usbhs_reg.h new file mode 100644 index 000000000..5a2c1fbc9 --- /dev/null +++ b/src/portable/wch/ch32v307/ch32_usbhs_reg.h @@ -0,0 +1,345 @@ +#ifndef _USB_CH32_USBHS_REG_H +#define _USB_CH32_USBHS_REG_H + +#include + +/******************* GLOBAL ******************/ + +// USB CONTROL +#define USBHS_CONTROL_OFFSET 0x00 +#define USBHS_DMA_EN (1 << 0) +#define USBHS_ALL_CLR (1 << 1) +#define USBHS_FORCE_RST (1 << 2) +#define USBHS_INT_BUSY_EN (1 << 3) +#define USBHS_DEV_PU_EN (1 << 4) +#define USBHS_SPEED_MASK (3 << 5) +#define USBHS_FULL_SPEED (0 << 5) +#define USBHS_HIGH_SPEED (1 << 5) +#define USBHS_LOW_SPEED (2 << 5) +#define USBHS_HOST_MODE (1 << 7) + +// USB_INT_EN +#define USBHS_INT_EN_OFFSET 0x02 +#define USBHS_BUS_RST_EN (1 << 0) +#define USBHS_DETECT_EN (1 << 0) +#define USBHS_TRANSFER_EN (1 << 1) +#define USBHS_SUSPEND_EN (1 << 2) +#define USBHS_SOF_ACT_EN (1 << 3) +#define USBHS_FIFO_OV_EN (1 << 4) +#define USBHS_SETUP_ACT_EN (1 << 5) +#define USBHS_ISO_ACT_EN (1 << 6) +#define USBHS_DEV_NAK_EN (1 << 7) + +// USB DEV AD +#define USBHS_DEV_AD_OFFSET 0x03 +// USB FRAME_NO +#define USBHS_FRAME_NO_OFFSET 0x04 +// USB SUSPEND +#define USBHS_SUSPEND_OFFSET 0x06 +#define USBHS_DEV_REMOTE_WAKEUP (1 << 2) +#define USBHS_LINESTATE_MASK (2 << 4) /* Read Only */ + +// RESERVED0 + +// USB SPEED TYPE +#define USBHS_SPEED_TYPE_OFFSET 0x08 +#define USBSPEED_MASK (0x03) + +// USB_MIS_ST +#define USBHS_MIS_ST_OFFSET 0x09 +#define USBHS_SPLIT_CAN (1 << 0) +#define USBHS_ATTACH (1 << 1) +#define USBHS_SUSPEND (1 << 2) +#define USBHS_BUS_RESET (1 << 3) +#define USBHS_R_FIFO_RDY (1 << 4) +#define USBHS_SIE_FREE (1 << 5) +#define USBHS_SOF_ACT (1 << 6) +#define USBHS_SOF_PRES (1 << 7) + +// INT_FLAG +#define USBHS_INT_FLAG_OFFSET 0x0A +#define USBHS_BUS_RST_FLAG (1 << 0) +#define USBHS_DETECT_FLAG (1 << 0) +#define USBHS_TRANSFER_FLAG (1 << 1) +#define USBHS_SUSPEND_FLAG (1 << 2) +#define USBHS_HST_SOF_FLAG (1 << 3) +#define USBHS_FIFO_OV_FLAG (1 << 4) +#define USBHS_SETUP_FLAG (1 << 5) +#define USBHS_ISO_ACT_FLAG (1 << 6) + +// INT_ST +#define USBHS_INT_ST_OFFSET 0x0B +#define USBHS_DEV_UIS_IS_NAK (1 << 7) +#define USBHS_DEV_UIS_TOG_OK (1 << 6) +#define MASK_UIS_TOKEN (3 << 4) +#define MASK_UIS_ENDP (0x0F) +#define MASK_UIS_H_RES (0x0F) + +#define USBHS_TOGGLE_OK (0x40) +#define USBHS_HOST_RES (0x0f) + +//USB_RX_LEN +#define USBHS_RX_LEN_OFFSET 0x0C +/******************* DEVICE ******************/ + +//UEP_CONFIG +#define USBHS_UEP_CONFIG_OFFSET 0x10 +#define USBHS_EP0_T_EN (1 << 0) +#define USBHS_EP0_R_EN (1 << 16) + +#define USBHS_EP1_T_EN (1 << 1) +#define USBHS_EP1_R_EN (1 << 17) + +#define USBHS_EP2_T_EN (1 << 2) +#define USBHS_EP2_R_EN (1 << 18) + +#define USBHS_EP3_T_EN (1 << 3) +#define USBHS_EP3_R_EN (1 << 19) + +#define USBHS_EP4_T_EN (1 << 4) +#define USBHS_EP4_R_EN (1 << 20) + +#define USBHS_EP5_T_EN (1 << 5) +#define USBHS_EP5_R_EN (1 << 21) + +#define USBHS_EP6_T_EN (1 << 6) +#define USBHS_EP6_R_EN (1 << 22) + +#define USBHS_EP7_T_EN (1 << 7) +#define USBHS_EP7_R_EN (1 << 23) + +#define USBHS_EP8_T_EN (1 << 8) +#define USBHS_EP8_R_EN (1 << 24) + +#define USBHS_EP9_T_EN (1 << 9) +#define USBHS_EP9_R_EN (1 << 25) + +#define USBHS_EP10_T_EN (1 << 10) +#define USBHS_EP10_R_EN (1 << 26) + +#define USBHS_EP11_T_EN (1 << 11) +#define USBHS_EP11_R_EN (1 << 27) + +#define USBHS_EP12_T_EN (1 << 12) +#define USBHS_EP12_R_EN (1 << 28) + +#define USBHS_EP13_T_EN (1 << 13) +#define USBHS_EP13_R_EN (1 << 29) + +#define USBHS_EP14_T_EN (1 << 14) +#define USBHS_EP14_R_EN (1 << 30) + +#define USBHS_EP15_T_EN (1 << 15) +#define USBHS_EP15_R_EN (1 << 31) + +//UEP_TYPE +#define USBHS_UEP_TYPE_OFFSET 0x14 +#define USBHS_EP0_T_TYP (1 << 0) +#define USBHS_EP0_R_TYP (1 << 16) + +#define USBHS_EP1_T_TYP (1 << 1) +#define USBHS_EP1_R_TYP (1 << 17) + +#define USBHS_EP2_T_TYP (1 << 2) +#define USBHS_EP2_R_TYP (1 << 18) + +#define USBHS_EP3_T_TYP (1 << 3) +#define USBHS_EP3_R_TYP (1 << 19) + +#define USBHS_EP4_T_TYP (1 << 4) +#define USBHS_EP4_R_TYP (1 << 20) + +#define USBHS_EP5_T_TYP (1 << 5) +#define USBHS_EP5_R_TYP (1 << 21) + +#define USBHS_EP6_T_TYP (1 << 6) +#define USBHS_EP6_R_TYP (1 << 22) + +#define USBHS_EP7_T_TYP (1 << 7) +#define USBHS_EP7_R_TYP (1 << 23) + +#define USBHS_EP8_T_TYP (1 << 8) +#define USBHS_EP8_R_TYP (1 << 24) + +#define USBHS_EP9_T_TYP (1 << 8) +#define USBHS_EP9_R_TYP (1 << 25) + +#define USBHS_EP10_T_TYP (1 << 10) +#define USBHS_EP10_R_TYP (1 << 26) + +#define USBHS_EP11_T_TYP (1 << 11) +#define USBHS_EP11_R_TYP (1 << 27) + +#define USBHS_EP12_T_TYP (1 << 12) +#define USBHS_EP12_R_TYP (1 << 28) + +#define USBHS_EP13_T_TYP (1 << 13) +#define USBHS_EP13_R_TYP (1 << 29) + +#define USBHS_EP14_T_TYP (1 << 14) +#define USBHS_EP14_R_TYP (1 << 30) + +#define USBHS_EP15_T_TYP (1 << 15) +#define USBHS_EP15_R_TYP (1 << 31) + +/* BUF_MOD UEP1~15 */ +#define USBHS_BUF_MOD_OFFSET 0x18 +#define USBHS_EP0_BUF_MOD (1 << 0) +#define USBHS_EP0_ISO_BUF_MOD (1 << 16) + +#define USBHS_EP1_BUF_MOD (1 << 1) +#define USBHS_EP1_ISO_BUF_MOD (1 << 17) + +#define USBHS_EP2_BUF_MOD (1 << 2) +#define USBHS_EP2_ISO_BUF_MOD (1 << 18) + +#define USBHS_EP3_BUF_MOD (1 << 3) +#define USBHS_EP3_ISO_BUF_MOD (1 << 19) + +#define USBHS_EP4_BUF_MOD (1 << 4) +#define USBHS_EP4_ISO_BUF_MOD (1 << 20) + +#define USBHS_EP5_BUF_MOD (1 << 5) +#define USBHS_EP5_ISO_BUF_MOD (1 << 21) + +#define USBHS_EP6_BUF_MOD (1 << 6) +#define USBHS_EP6_ISO_BUF_MOD (1 << 22) + +#define USBHS_EP7_BUF_MOD (1 << 7) +#define USBHS_EP7_ISO_BUF_MOD (1 << 23) + +#define USBHS_EP8_BUF_MOD (1 << 8) +#define USBHS_EP8_ISO_BUF_MOD (1 << 24) + +#define USBHS_EP9_BUF_MOD (1 << 9) +#define USBHS_EP9_ISO_BUF_MOD (1 << 25) + +#define USBHS_EP10_BUF_MOD (1 << 10) +#define USBHS_EP10_ISO_BUF_MOD (1 << 26) + +#define USBHS_EP11_BUF_MOD (1 << 11) +#define USBHS_EP11_ISO_BUF_MOD (1 << 27) + +#define USBHS_EP12_BUF_MOD (1 << 12) +#define USBHS_EP12_ISO_BUF_MOD (1 << 28) + +#define USBHS_EP13_BUF_MOD (1 << 13) +#define USBHS_EP13_ISO_BUF_MOD (1 << 29) + +#define USBHS_EP14_BUF_MOD (1 << 14) +#define USBHS_EP14_ISO_BUF_MOD (1 << 30) + +#define USBHS_EP15_BUF_MOD (1 << 15) +#define USBHS_EP15_ISO_BUF_MOD (1 << 31) +//USBHS_EPn_T_EN USBHS_EPn_R_EN USBHS_EPn_BUF_MOD Description: Arrange from low to high with UEPn_DMA as the starting address +// 0 0 x The endpoint is disabled and the UEPn_*_DMA buffers are not used. +// 1 0 0 The first address of the receive (OUT) buffer is UEPn_RX_DMA +// 1 0 1 RB_UEPn_RX_TOG[0]=0, use buffer UEPn_RX_DMA RB_UEPn_RX_TOG[0]=1, use buffer UEPn_TX_DMA +// 0 1 0 The first address of the transmit (IN) buffer is UEPn_TX_DMA. +// 0 1 1 RB_UEPn_TX_TOG[0]=0, use buffer UEPn_TX_DMA RB_UEPn_TX_TOG[0]=1, use buffer UEPn_RX_DMA + +/* USB0_DMA */ +#define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address + +/* USBX_RX_DMA */ +#define USBHS_UEPx_RX_DMA_OFFSET(n) (0x1C + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_TX_DMA_OFFSET(n) (0x58 + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_MAX_LEN_OFFSET(n) (0x98 + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_T_LEN_OFFSET(n) (0xD8 + 4 * (n)) // endpoint x DMA buffer address +#define USBHS_UEPx_TX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 2) // endpoint x DMA buffer address +#define USBHS_UEPx_RX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 3) // endpoint x DMA buffer address + +// UEPn_T_LEN +#define USBHS_EP_T_LEN_MASK (0x7FF) + +//UEPn_TX_CTRL +#define USBHS_EP_T_RES_MASK (3 << 0) +#define USBHS_EP_T_RES_ACK (0 << 0) +#define USBHS_EP_T_RES_NYET (1 << 0) +#define USBHS_EP_T_RES_NAK (2 << 0) +#define USBHS_EP_T_RES_STALL (3 << 0) + +#define USBHS_EP_T_TOG_MASK (3 << 3) +#define USBHS_EP_T_TOG_0 (0 << 3) +#define USBHS_EP_T_TOG_1 (1 << 3) +#define USBHS_EP_T_TOG_2 (2 << 3) +#define USBHS_EP_T_TOG_M (3 << 3) + +#define USBHS_EP_T_AUTOTOG (1 << 5) + +//UEPn_RX_CTRL +#define USBHS_EP_R_RES_MASK (3 << 0) +#define USBHS_EP_R_RES_ACK (0 << 0) +#define USBHS_EP_R_RES_NYET (1 << 0) +#define USBHS_EP_R_RES_NAK (2 << 0) +#define USBHS_EP_R_RES_STALL (3 << 0) + +#define USBHS_EP_R_TOG_MASK (3 << 3) +#define USBHS_EP_R_TOG_0 (0 << 3) +#define USBHS_EP_R_TOG_1 (1 << 3) +#define USBHS_EP_R_TOG_2 (2 << 3) +#define USBHS_EP_R_TOG_M (3 << 3) + +#define USBHS_EP_R_AUTOTOG (1 << 5) + +#define USBHS_TOG_MATCH (1 << 6) + +/******************* HOST ******************/ +// USB HOST_CTRL +#define USBHS_SEND_BUS_RESET (1 << 0) +#define USBHS_SEND_BUS_SUSPEND (1 << 1) +#define USBHS_SEND_BUS_RESUME (1 << 2) +#define USBHS_REMOTE_WAKE (1 << 3) +#define USBHS_PHY_SUSPENDM (1 << 4) +#define USBHS_UH_SOFT_FREE (1 << 6) +#define USBHS_SEND_SOF_EN (1 << 7) + +//UH_CONFIG +#define USBHS_HOST_TX_EN (1 << 3) +#define USBHS_HOST_RX_EN (1 << 18) + +// HOST_EP_TYPE +#define USBHS_ENDP_TX_ISO (1 << 3) +#define USBHS_ENDP_RX_ISO (1 << (16 + 2)) + +// R32_UH_EP_PID +#define USBHS_HOST_MASK_TOKEN (0x0f) +#define USBHS_HOST_MASK_ENDP (0x0f << 4) + +//R8_UH_RX_CTRL +#define USBHS_EP_R_RES_MASK (3 << 0) +#define USBHS_EP_R_RES_ACK (0 << 0) +#define USBHS_EP_R_RES_NYET (1 << 0) +#define USBHS_EP_R_RES_NAK (2 << 0) +#define USBHS_EP_R_RES_STALL (3 << 0) + +#define USBHS_UH_R_RES_NO (1 << 2) +#define USBHS_UH_R_TOG_1 (1 << 3) +#define USBHS_UH_R_TOG_2 (2 << 3) +#define USBHS_UH_R_TOG_3 (3 << 3) +#define USBHS_UH_R_TOG_AUTO (1 << 5) +#define USBHS_UH_R_DATA_NO (1 << 6) +//R8_UH_TX_CTRL +#define USBHS_UH_T_RES_MASK (3 << 0) +#define USBHS_UH_T_RES_ACK (0 << 0) +#define USBHS_UH_T_RES_NYET (1 << 0) +#define USBHS_UH_T_RES_NAK (2 << 0) +#define USBHS_UH_T_RES_STALL (3 << 0) + +#define USBHS_UH_T_RES_NO (1 << 2) +#define USBHS_UH_T_TOG_1 (1 << 3) +#define USBHS_UH_T_TOG_2 (2 << 3) +#define USBHS_UH_T_TOG_3 (3 << 3) +#define USBHS_UH_T_TOG_AUTO (1 << 5) +#define USBHS_UH_T_DATA_NO (1 << 6) + +// 00: OUT, 01:SOF, 10:IN, 11:SETUP +#define PID_OUT 0 +#define PID_SOF 1 +#define PID_IN 2 +#define PID_SETUP 3 + +#endif diff --git a/src/portable/wch/ch32v307/dcd_usbhs.c b/src/portable/wch/ch32v307/dcd_usbhs.c new file mode 100644 index 000000000..7a0dcfc23 --- /dev/null +++ b/src/portable/wch/ch32v307/dcd_usbhs.c @@ -0,0 +1,386 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2022 Greg Davill + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_CH32V307) +#include "device/dcd.h" + +#include "ch32_usbhs_reg.h" +#include "core_riscv.h" + +// Max number of bi-directional endpoints including EP0 +#define EP_MAX 16 + +typedef struct { + uint8_t *buffer; + // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API + uint16_t total_len; + uint16_t queued_len; + uint16_t max_size; + bool short_packet; +} xfer_ctl_t; + +#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] +static xfer_ctl_t xfer_status[EP_MAX][2]; + +#define EP_TX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_TX_LEN) + (ep)*2) +#define EP_TX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_TX_CTRL) + (ep)*4) +#define EP_RX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_RX_CTRL) + (ep)*4) +#define EP_RX_MAX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_MAX_LEN) + (ep)*2) + +#define EP_TX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_TX_DMA) + (ep - 1)) +#define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1)) + +/* Endpoint Buffer */ +TU_ATTR_ALIGNED(4) uint8_t EP0_DatabufHD[64]; // ep0(64) + +volatile uint8_t USBHS_Dev_Endp0_Tog = 0x01; + +void dcd_init(uint8_t rhport) { + (void)rhport; + + memset(&xfer_status, 0, sizeof(xfer_status)); + + USBHSD->HOST_CTRL = 0x00; + USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM; + + USBHSD->CONTROL = 0; + +#if TUD_OPT_HIGH_SPEED + USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED; +#else + #error OPT_MODE_FULL_SPEED not currently supported on CH32V307 + USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED; +#endif + + USBHSD->INT_EN = 0; + USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN | USBHS_SUSPEND_EN; + + /* ALL endpoint enable */ + USBHSD->ENDP_CONFIG = 0xffffffff; + + USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN; + USBHSD->ENDP_TYPE = 0x00; + USBHSD->BUF_MODE = 0x00; + + USBHSD->UEP0_MAX_LEN = 64; + + USBHSD->UEP0_DMA = (uint32_t)EP0_DatabufHD; + + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_NAK; + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + + for (int ep = 1; ep < EP_MAX; ep++) { + EP_TX_LEN(ep) = 0; + EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK; + EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK; + + EP_RX_MAX_LEN(ep) = 512; + } + + USBHSD->DEV_AD = 0; + USBHSD->CONTROL |= USBHS_DEV_PU_EN; +} + +void dcd_int_enable(uint8_t rhport) { + (void)rhport; + + NVIC_EnableIRQ(USBHS_IRQn); +} + +void dcd_int_disable(uint8_t rhport) { + (void)rhport; + + NVIC_DisableIRQ(USBHS_IRQn); +} + +void dcd_edpt_close_all(uint8_t rhport) { + (void)rhport; +} + +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { + (void)dev_addr; + + // Response with zlp status + dcd_edpt_xfer(rhport, 0x80, NULL, 0); +} + +void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) { + (void)rhport; + + if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && + request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && + request->bRequest == TUSB_REQ_SET_ADDRESS) { + USBHSD->DEV_AD = (uint8_t)request->wValue; + } + + EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK; + EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK; +} + +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) { + (void)rhport; + + uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); + + TU_ASSERT(epnum < EP_MAX); + + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->max_size = tu_edpt_packet_size(desc_edpt); + + if (epnum != 0) { + if (tu_edpt_dir(desc_edpt->bEndpointAddress) == TUSB_DIR_OUT) { + EP_RX_CTRL(epnum) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_ACK; + } else { + EP_TX_LEN(epnum) = 0; + EP_TX_CTRL(epnum) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0; + } + } + + return true; +} + +int usbd_ep_close(const uint8_t ep) { + (void)ep; + + return 0; +} +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { + (void)rhport; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if (epnum == 0) { + if (dir == TUSB_DIR_OUT) { + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_STALL; + } else { + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_STALL; + } + } else { + if (dir == TUSB_DIR_OUT) { + EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_STALL; + + } else { + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~USBHS_EP_T_RES_MASK) | USBHS_EP_T_RES_STALL; + } + } +} + +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { + (void)rhport; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if (epnum == 0) { + if (dir == TUSB_DIR_OUT) { + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + } else { + } + } else { + if (dir == TUSB_DIR_OUT) { + EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~(USBHS_EP_R_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_ACK; + + } else { + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_NAK; + } + } +} + +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { + (void)rhport; + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = buffer; + // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API + xfer->total_len = total_bytes; + xfer->queued_len = 0; + xfer->short_packet = false; + + // uint16_t num_packets = (total_bytes / xfer->max_size); + uint16_t short_packet_size = total_bytes % (xfer->max_size + 1); + + // Zero-size packet is special case. + if (short_packet_size == 0 || (total_bytes == 0)) { + xfer->short_packet = true; + } + + if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) { + if (!total_bytes) { + xfer->short_packet = true; + if (epnum == 0) { + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); + USBHS_Dev_Endp0_Tog ^= 1; + } else { + EP_TX_LEN(epnum) = 0; + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK; + } + } else { + if (epnum == 0) { + xfer->queued_len += short_packet_size; + memcpy(&EP0_DatabufHD[0], buffer, short_packet_size); + + USBHSD->UEP0_TX_LEN = short_packet_size; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); + USBHS_Dev_Endp0_Tog ^= 1; + } else { + xfer->queued_len += short_packet_size; + + EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer; + USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum); + EP_TX_LEN(epnum) = short_packet_size; + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK; + } + } + } else { /* TUSB_DIR_OUT */ + if (epnum == 0) { + uint32_t read_count = USBHSD->RX_LEN; + read_count = TU_MIN(read_count, total_bytes); + + if ((total_bytes == 8)) { + read_count = 8; + memcpy(buffer, &EP0_DatabufHD[0], 8); + } else { + memcpy(buffer, &EP0_DatabufHD[0], read_count); + } + } else { + EP_RX_DMA_ADDR(epnum) = (uint32_t)xfer->buffer; + USBHSD->ENDP_CONFIG |= (USBHS_EP0_R_EN << epnum); + } + + // usbd_ep_read(ep_addr, buffer, total_bytes, &ret_bytes); + } + return true; +} + + +static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size) { + // xfer->queued_len = xfer->total_len - remaining; + + uint16_t remaining = xfer->total_len - xfer->queued_len; + uint16_t to_recv_size; + + if (remaining <= xfer->max_size) { + // Avoid buffer overflow. + to_recv_size = (xfer_size > remaining) ? remaining : xfer_size; + } else { + // Room for full packet, choose recv_size based on what the microcontroller + // claims. + to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size; + } + + if (to_recv_size) { + } + + xfer->queued_len += xfer_size; + + // Per USB spec, a short OUT packet (including length 0) is always + // indicative of the end of a transfer (at least for ctl, bulk, int). + xfer->short_packet = (xfer_size < xfer->max_size); +} + +void dcd_int_handler(uint8_t rhport) { + (void)rhport; + + uint32_t end_num, rx_token; + uint8_t intflag = 0; + + intflag = USBHSD->INT_FG; + + if (intflag & USBHS_TRANSFER_FLAG) { + + end_num = (USBHSD->INT_ST) & MASK_UIS_ENDP; + rx_token = (((USBHSD->INT_ST) & MASK_UIS_TOKEN) >> 4) & 0x03; + + uint8_t endp = end_num | (rx_token == PID_IN ? TUSB_DIR_IN_MASK : 0); + + xfer_ctl_t *xfer = XFER_CTL_BASE(end_num, tu_edpt_dir(endp)); + + if (rx_token == PID_OUT) { + uint16_t rx_len = USBHSD->RX_LEN; + + receive_packet(xfer, rx_len); + + if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { + xfer->short_packet = false; + + dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true); + } + + if (end_num == 0) { + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0; + } + + } else if (rx_token == PID_IN) { + if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { + xfer->short_packet = false; + xfer->total_len = 0; + dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true); + + EP_TX_CTRL(end_num) = (EP_TX_CTRL(end_num) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_NAK; + + if (end_num == 0) { + } + } else { + dcd_edpt_xfer(0, endp, xfer->buffer + xfer->queued_len, xfer->total_len - xfer->queued_len); + } + } + + USBHSD->INT_FG = USBHS_TRANSFER_FLAG; /* Clear flag */ + } else if (intflag & USBHS_SETUP_FLAG) { + USBHS_Dev_Endp0_Tog = 1; + dcd_event_setup_received(0, EP0_DatabufHD, true); + + USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */ + } else if (intflag & USBHS_DETECT_FLAG) { + USBHS_Dev_Endp0_Tog = 1; + + xfer_status[0][TUSB_DIR_OUT].max_size = 64; + xfer_status[0][TUSB_DIR_IN].max_size = 64; + + dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true); + + USBHSD->DEV_AD = 0; + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0; + + USBHSD->INT_FG = USBHS_DETECT_FLAG; /* Clear flag */ + } else if (intflag & USBHS_SUSPEND_FLAG) { + dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SUSPEND }; + dcd_event_handler(&event, true); + + USBHSD->INT_FG = USBHS_SUSPEND_FLAG; /* Clear flag */ + } +} + +#endif diff --git a/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h b/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h deleted file mode 100644 index 5a2c1fbc9..000000000 --- a/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h +++ /dev/null @@ -1,345 +0,0 @@ -#ifndef _USB_CH32_USBHS_REG_H -#define _USB_CH32_USBHS_REG_H - -#include - -/******************* GLOBAL ******************/ - -// USB CONTROL -#define USBHS_CONTROL_OFFSET 0x00 -#define USBHS_DMA_EN (1 << 0) -#define USBHS_ALL_CLR (1 << 1) -#define USBHS_FORCE_RST (1 << 2) -#define USBHS_INT_BUSY_EN (1 << 3) -#define USBHS_DEV_PU_EN (1 << 4) -#define USBHS_SPEED_MASK (3 << 5) -#define USBHS_FULL_SPEED (0 << 5) -#define USBHS_HIGH_SPEED (1 << 5) -#define USBHS_LOW_SPEED (2 << 5) -#define USBHS_HOST_MODE (1 << 7) - -// USB_INT_EN -#define USBHS_INT_EN_OFFSET 0x02 -#define USBHS_BUS_RST_EN (1 << 0) -#define USBHS_DETECT_EN (1 << 0) -#define USBHS_TRANSFER_EN (1 << 1) -#define USBHS_SUSPEND_EN (1 << 2) -#define USBHS_SOF_ACT_EN (1 << 3) -#define USBHS_FIFO_OV_EN (1 << 4) -#define USBHS_SETUP_ACT_EN (1 << 5) -#define USBHS_ISO_ACT_EN (1 << 6) -#define USBHS_DEV_NAK_EN (1 << 7) - -// USB DEV AD -#define USBHS_DEV_AD_OFFSET 0x03 -// USB FRAME_NO -#define USBHS_FRAME_NO_OFFSET 0x04 -// USB SUSPEND -#define USBHS_SUSPEND_OFFSET 0x06 -#define USBHS_DEV_REMOTE_WAKEUP (1 << 2) -#define USBHS_LINESTATE_MASK (2 << 4) /* Read Only */ - -// RESERVED0 - -// USB SPEED TYPE -#define USBHS_SPEED_TYPE_OFFSET 0x08 -#define USBSPEED_MASK (0x03) - -// USB_MIS_ST -#define USBHS_MIS_ST_OFFSET 0x09 -#define USBHS_SPLIT_CAN (1 << 0) -#define USBHS_ATTACH (1 << 1) -#define USBHS_SUSPEND (1 << 2) -#define USBHS_BUS_RESET (1 << 3) -#define USBHS_R_FIFO_RDY (1 << 4) -#define USBHS_SIE_FREE (1 << 5) -#define USBHS_SOF_ACT (1 << 6) -#define USBHS_SOF_PRES (1 << 7) - -// INT_FLAG -#define USBHS_INT_FLAG_OFFSET 0x0A -#define USBHS_BUS_RST_FLAG (1 << 0) -#define USBHS_DETECT_FLAG (1 << 0) -#define USBHS_TRANSFER_FLAG (1 << 1) -#define USBHS_SUSPEND_FLAG (1 << 2) -#define USBHS_HST_SOF_FLAG (1 << 3) -#define USBHS_FIFO_OV_FLAG (1 << 4) -#define USBHS_SETUP_FLAG (1 << 5) -#define USBHS_ISO_ACT_FLAG (1 << 6) - -// INT_ST -#define USBHS_INT_ST_OFFSET 0x0B -#define USBHS_DEV_UIS_IS_NAK (1 << 7) -#define USBHS_DEV_UIS_TOG_OK (1 << 6) -#define MASK_UIS_TOKEN (3 << 4) -#define MASK_UIS_ENDP (0x0F) -#define MASK_UIS_H_RES (0x0F) - -#define USBHS_TOGGLE_OK (0x40) -#define USBHS_HOST_RES (0x0f) - -//USB_RX_LEN -#define USBHS_RX_LEN_OFFSET 0x0C -/******************* DEVICE ******************/ - -//UEP_CONFIG -#define USBHS_UEP_CONFIG_OFFSET 0x10 -#define USBHS_EP0_T_EN (1 << 0) -#define USBHS_EP0_R_EN (1 << 16) - -#define USBHS_EP1_T_EN (1 << 1) -#define USBHS_EP1_R_EN (1 << 17) - -#define USBHS_EP2_T_EN (1 << 2) -#define USBHS_EP2_R_EN (1 << 18) - -#define USBHS_EP3_T_EN (1 << 3) -#define USBHS_EP3_R_EN (1 << 19) - -#define USBHS_EP4_T_EN (1 << 4) -#define USBHS_EP4_R_EN (1 << 20) - -#define USBHS_EP5_T_EN (1 << 5) -#define USBHS_EP5_R_EN (1 << 21) - -#define USBHS_EP6_T_EN (1 << 6) -#define USBHS_EP6_R_EN (1 << 22) - -#define USBHS_EP7_T_EN (1 << 7) -#define USBHS_EP7_R_EN (1 << 23) - -#define USBHS_EP8_T_EN (1 << 8) -#define USBHS_EP8_R_EN (1 << 24) - -#define USBHS_EP9_T_EN (1 << 9) -#define USBHS_EP9_R_EN (1 << 25) - -#define USBHS_EP10_T_EN (1 << 10) -#define USBHS_EP10_R_EN (1 << 26) - -#define USBHS_EP11_T_EN (1 << 11) -#define USBHS_EP11_R_EN (1 << 27) - -#define USBHS_EP12_T_EN (1 << 12) -#define USBHS_EP12_R_EN (1 << 28) - -#define USBHS_EP13_T_EN (1 << 13) -#define USBHS_EP13_R_EN (1 << 29) - -#define USBHS_EP14_T_EN (1 << 14) -#define USBHS_EP14_R_EN (1 << 30) - -#define USBHS_EP15_T_EN (1 << 15) -#define USBHS_EP15_R_EN (1 << 31) - -//UEP_TYPE -#define USBHS_UEP_TYPE_OFFSET 0x14 -#define USBHS_EP0_T_TYP (1 << 0) -#define USBHS_EP0_R_TYP (1 << 16) - -#define USBHS_EP1_T_TYP (1 << 1) -#define USBHS_EP1_R_TYP (1 << 17) - -#define USBHS_EP2_T_TYP (1 << 2) -#define USBHS_EP2_R_TYP (1 << 18) - -#define USBHS_EP3_T_TYP (1 << 3) -#define USBHS_EP3_R_TYP (1 << 19) - -#define USBHS_EP4_T_TYP (1 << 4) -#define USBHS_EP4_R_TYP (1 << 20) - -#define USBHS_EP5_T_TYP (1 << 5) -#define USBHS_EP5_R_TYP (1 << 21) - -#define USBHS_EP6_T_TYP (1 << 6) -#define USBHS_EP6_R_TYP (1 << 22) - -#define USBHS_EP7_T_TYP (1 << 7) -#define USBHS_EP7_R_TYP (1 << 23) - -#define USBHS_EP8_T_TYP (1 << 8) -#define USBHS_EP8_R_TYP (1 << 24) - -#define USBHS_EP9_T_TYP (1 << 8) -#define USBHS_EP9_R_TYP (1 << 25) - -#define USBHS_EP10_T_TYP (1 << 10) -#define USBHS_EP10_R_TYP (1 << 26) - -#define USBHS_EP11_T_TYP (1 << 11) -#define USBHS_EP11_R_TYP (1 << 27) - -#define USBHS_EP12_T_TYP (1 << 12) -#define USBHS_EP12_R_TYP (1 << 28) - -#define USBHS_EP13_T_TYP (1 << 13) -#define USBHS_EP13_R_TYP (1 << 29) - -#define USBHS_EP14_T_TYP (1 << 14) -#define USBHS_EP14_R_TYP (1 << 30) - -#define USBHS_EP15_T_TYP (1 << 15) -#define USBHS_EP15_R_TYP (1 << 31) - -/* BUF_MOD UEP1~15 */ -#define USBHS_BUF_MOD_OFFSET 0x18 -#define USBHS_EP0_BUF_MOD (1 << 0) -#define USBHS_EP0_ISO_BUF_MOD (1 << 16) - -#define USBHS_EP1_BUF_MOD (1 << 1) -#define USBHS_EP1_ISO_BUF_MOD (1 << 17) - -#define USBHS_EP2_BUF_MOD (1 << 2) -#define USBHS_EP2_ISO_BUF_MOD (1 << 18) - -#define USBHS_EP3_BUF_MOD (1 << 3) -#define USBHS_EP3_ISO_BUF_MOD (1 << 19) - -#define USBHS_EP4_BUF_MOD (1 << 4) -#define USBHS_EP4_ISO_BUF_MOD (1 << 20) - -#define USBHS_EP5_BUF_MOD (1 << 5) -#define USBHS_EP5_ISO_BUF_MOD (1 << 21) - -#define USBHS_EP6_BUF_MOD (1 << 6) -#define USBHS_EP6_ISO_BUF_MOD (1 << 22) - -#define USBHS_EP7_BUF_MOD (1 << 7) -#define USBHS_EP7_ISO_BUF_MOD (1 << 23) - -#define USBHS_EP8_BUF_MOD (1 << 8) -#define USBHS_EP8_ISO_BUF_MOD (1 << 24) - -#define USBHS_EP9_BUF_MOD (1 << 9) -#define USBHS_EP9_ISO_BUF_MOD (1 << 25) - -#define USBHS_EP10_BUF_MOD (1 << 10) -#define USBHS_EP10_ISO_BUF_MOD (1 << 26) - -#define USBHS_EP11_BUF_MOD (1 << 11) -#define USBHS_EP11_ISO_BUF_MOD (1 << 27) - -#define USBHS_EP12_BUF_MOD (1 << 12) -#define USBHS_EP12_ISO_BUF_MOD (1 << 28) - -#define USBHS_EP13_BUF_MOD (1 << 13) -#define USBHS_EP13_ISO_BUF_MOD (1 << 29) - -#define USBHS_EP14_BUF_MOD (1 << 14) -#define USBHS_EP14_ISO_BUF_MOD (1 << 30) - -#define USBHS_EP15_BUF_MOD (1 << 15) -#define USBHS_EP15_ISO_BUF_MOD (1 << 31) -//USBHS_EPn_T_EN USBHS_EPn_R_EN USBHS_EPn_BUF_MOD Description: Arrange from low to high with UEPn_DMA as the starting address -// 0 0 x The endpoint is disabled and the UEPn_*_DMA buffers are not used. -// 1 0 0 The first address of the receive (OUT) buffer is UEPn_RX_DMA -// 1 0 1 RB_UEPn_RX_TOG[0]=0, use buffer UEPn_RX_DMA RB_UEPn_RX_TOG[0]=1, use buffer UEPn_TX_DMA -// 0 1 0 The first address of the transmit (IN) buffer is UEPn_TX_DMA. -// 0 1 1 RB_UEPn_TX_TOG[0]=0, use buffer UEPn_TX_DMA RB_UEPn_TX_TOG[0]=1, use buffer UEPn_RX_DMA - -/* USB0_DMA */ -#define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address - -/* USBX_RX_DMA */ -#define USBHS_UEPx_RX_DMA_OFFSET(n) (0x1C + 4 * (n)) // endpoint x DMA buffer address - -#define USBHS_UEPx_TX_DMA_OFFSET(n) (0x58 + 4 * (n)) // endpoint x DMA buffer address - -#define USBHS_UEPx_MAX_LEN_OFFSET(n) (0x98 + 4 * (n)) // endpoint x DMA buffer address - -#define USBHS_UEPx_T_LEN_OFFSET(n) (0xD8 + 4 * (n)) // endpoint x DMA buffer address -#define USBHS_UEPx_TX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 2) // endpoint x DMA buffer address -#define USBHS_UEPx_RX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 3) // endpoint x DMA buffer address - -// UEPn_T_LEN -#define USBHS_EP_T_LEN_MASK (0x7FF) - -//UEPn_TX_CTRL -#define USBHS_EP_T_RES_MASK (3 << 0) -#define USBHS_EP_T_RES_ACK (0 << 0) -#define USBHS_EP_T_RES_NYET (1 << 0) -#define USBHS_EP_T_RES_NAK (2 << 0) -#define USBHS_EP_T_RES_STALL (3 << 0) - -#define USBHS_EP_T_TOG_MASK (3 << 3) -#define USBHS_EP_T_TOG_0 (0 << 3) -#define USBHS_EP_T_TOG_1 (1 << 3) -#define USBHS_EP_T_TOG_2 (2 << 3) -#define USBHS_EP_T_TOG_M (3 << 3) - -#define USBHS_EP_T_AUTOTOG (1 << 5) - -//UEPn_RX_CTRL -#define USBHS_EP_R_RES_MASK (3 << 0) -#define USBHS_EP_R_RES_ACK (0 << 0) -#define USBHS_EP_R_RES_NYET (1 << 0) -#define USBHS_EP_R_RES_NAK (2 << 0) -#define USBHS_EP_R_RES_STALL (3 << 0) - -#define USBHS_EP_R_TOG_MASK (3 << 3) -#define USBHS_EP_R_TOG_0 (0 << 3) -#define USBHS_EP_R_TOG_1 (1 << 3) -#define USBHS_EP_R_TOG_2 (2 << 3) -#define USBHS_EP_R_TOG_M (3 << 3) - -#define USBHS_EP_R_AUTOTOG (1 << 5) - -#define USBHS_TOG_MATCH (1 << 6) - -/******************* HOST ******************/ -// USB HOST_CTRL -#define USBHS_SEND_BUS_RESET (1 << 0) -#define USBHS_SEND_BUS_SUSPEND (1 << 1) -#define USBHS_SEND_BUS_RESUME (1 << 2) -#define USBHS_REMOTE_WAKE (1 << 3) -#define USBHS_PHY_SUSPENDM (1 << 4) -#define USBHS_UH_SOFT_FREE (1 << 6) -#define USBHS_SEND_SOF_EN (1 << 7) - -//UH_CONFIG -#define USBHS_HOST_TX_EN (1 << 3) -#define USBHS_HOST_RX_EN (1 << 18) - -// HOST_EP_TYPE -#define USBHS_ENDP_TX_ISO (1 << 3) -#define USBHS_ENDP_RX_ISO (1 << (16 + 2)) - -// R32_UH_EP_PID -#define USBHS_HOST_MASK_TOKEN (0x0f) -#define USBHS_HOST_MASK_ENDP (0x0f << 4) - -//R8_UH_RX_CTRL -#define USBHS_EP_R_RES_MASK (3 << 0) -#define USBHS_EP_R_RES_ACK (0 << 0) -#define USBHS_EP_R_RES_NYET (1 << 0) -#define USBHS_EP_R_RES_NAK (2 << 0) -#define USBHS_EP_R_RES_STALL (3 << 0) - -#define USBHS_UH_R_RES_NO (1 << 2) -#define USBHS_UH_R_TOG_1 (1 << 3) -#define USBHS_UH_R_TOG_2 (2 << 3) -#define USBHS_UH_R_TOG_3 (3 << 3) -#define USBHS_UH_R_TOG_AUTO (1 << 5) -#define USBHS_UH_R_DATA_NO (1 << 6) -//R8_UH_TX_CTRL -#define USBHS_UH_T_RES_MASK (3 << 0) -#define USBHS_UH_T_RES_ACK (0 << 0) -#define USBHS_UH_T_RES_NYET (1 << 0) -#define USBHS_UH_T_RES_NAK (2 << 0) -#define USBHS_UH_T_RES_STALL (3 << 0) - -#define USBHS_UH_T_RES_NO (1 << 2) -#define USBHS_UH_T_TOG_1 (1 << 3) -#define USBHS_UH_T_TOG_2 (2 << 3) -#define USBHS_UH_T_TOG_3 (3 << 3) -#define USBHS_UH_T_TOG_AUTO (1 << 5) -#define USBHS_UH_T_DATA_NO (1 << 6) - -// 00: OUT, 01:SOF, 10:IN, 11:SETUP -#define PID_OUT 0 -#define PID_SOF 1 -#define PID_IN 2 -#define PID_SETUP 3 - -#endif diff --git a/src/portable/wch/ch32v307/usb_dc_usbhs.c b/src/portable/wch/ch32v307/usb_dc_usbhs.c deleted file mode 100644 index 39fd41392..000000000 --- a/src/portable/wch/ch32v307/usb_dc_usbhs.c +++ /dev/null @@ -1,386 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2022 Greg Davill - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_CH32V307) -#include "device/dcd.h" - -#include "usb_ch32_usbhs_reg.h" -#include "core_riscv.h" - -// Max number of bi-directional endpoints including EP0 -#define EP_MAX 16 - -typedef struct { - uint8_t *buffer; - // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API - uint16_t total_len; - uint16_t queued_len; - uint16_t max_size; - bool short_packet; -} xfer_ctl_t; - -#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] -static xfer_ctl_t xfer_status[EP_MAX][2]; - -#define EP_TX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_TX_LEN) + (ep)*2) -#define EP_TX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_TX_CTRL) + (ep)*4) -#define EP_RX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_RX_CTRL) + (ep)*4) -#define EP_RX_MAX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_MAX_LEN) + (ep)*2) - -#define EP_TX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_TX_DMA) + (ep - 1)) -#define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1)) - -/* Endpoint Buffer */ -TU_ATTR_ALIGNED(4) uint8_t EP0_DatabufHD[64]; // ep0(64) - -volatile uint8_t USBHS_Dev_Endp0_Tog = 0x01; - -void dcd_init(uint8_t rhport) { - (void)rhport; - - memset(&xfer_status, 0, sizeof(xfer_status)); - - USBHSD->HOST_CTRL = 0x00; - USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM; - - USBHSD->CONTROL = 0; - -#if TUD_OPT_HIGH_SPEED - USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED; -#else - #error OPT_MODE_FULL_SPEED not currently supported on CH32V307 - USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED; -#endif - - USBHSD->INT_EN = 0; - USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN | USBHS_SUSPEND_EN; - - /* ALL endpoint enable */ - USBHSD->ENDP_CONFIG = 0xffffffff; - - USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN; - USBHSD->ENDP_TYPE = 0x00; - USBHSD->BUF_MODE = 0x00; - - USBHSD->UEP0_MAX_LEN = 64; - - USBHSD->UEP0_DMA = (uint32_t)EP0_DatabufHD; - - USBHSD->UEP0_TX_LEN = 0; - USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_NAK; - USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; - - for (int ep = 1; ep < EP_MAX; ep++) { - EP_TX_LEN(ep) = 0; - EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK; - EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK; - - EP_RX_MAX_LEN(ep) = 512; - } - - USBHSD->DEV_AD = 0; - USBHSD->CONTROL |= USBHS_DEV_PU_EN; -} - -void dcd_int_enable(uint8_t rhport) { - (void)rhport; - - NVIC_EnableIRQ(USBHS_IRQn); -} - -void dcd_int_disable(uint8_t rhport) { - (void)rhport; - - NVIC_DisableIRQ(USBHS_IRQn); -} - -void dcd_edpt_close_all(uint8_t rhport) { - (void)rhport; -} - -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { - (void)dev_addr; - - // Response with zlp status - dcd_edpt_xfer(rhport, 0x80, NULL, 0); -} - -void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) { - (void)rhport; - - if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && - request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && - request->bRequest == TUSB_REQ_SET_ADDRESS) { - USBHSD->DEV_AD = (uint8_t)request->wValue; - } - - EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK; - EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK; -} - -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) { - (void)rhport; - - uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); - - TU_ASSERT(epnum < EP_MAX); - - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->max_size = tu_edpt_packet_size(desc_edpt); - - if (epnum != 0) { - if (tu_edpt_dir(desc_edpt->bEndpointAddress) == TUSB_DIR_OUT) { - EP_RX_CTRL(epnum) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_ACK; - } else { - EP_TX_LEN(epnum) = 0; - EP_TX_CTRL(epnum) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0; - } - } - - return true; -} - -int usbd_ep_close(const uint8_t ep) { - (void)ep; - - return 0; -} -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - if (epnum == 0) { - if (dir == TUSB_DIR_OUT) { - USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_STALL; - } else { - USBHSD->UEP0_TX_LEN = 0; - USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_STALL; - } - } else { - if (dir == TUSB_DIR_OUT) { - EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_STALL; - - } else { - EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~USBHS_EP_T_RES_MASK) | USBHS_EP_T_RES_STALL; - } - } -} - -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - if (epnum == 0) { - if (dir == TUSB_DIR_OUT) { - USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; - } else { - } - } else { - if (dir == TUSB_DIR_OUT) { - EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~(USBHS_EP_R_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_ACK; - - } else { - EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_NAK; - } - } -} - -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void)rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->buffer = buffer; - // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API - xfer->total_len = total_bytes; - xfer->queued_len = 0; - xfer->short_packet = false; - - // uint16_t num_packets = (total_bytes / xfer->max_size); - uint16_t short_packet_size = total_bytes % (xfer->max_size + 1); - - // Zero-size packet is special case. - if (short_packet_size == 0 || (total_bytes == 0)) { - xfer->short_packet = true; - } - - if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) { - if (!total_bytes) { - xfer->short_packet = true; - if (epnum == 0) { - USBHSD->UEP0_TX_LEN = 0; - USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); - USBHS_Dev_Endp0_Tog ^= 1; - } else { - EP_TX_LEN(epnum) = 0; - EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK; - } - } else { - if (epnum == 0) { - xfer->queued_len += short_packet_size; - memcpy(&EP0_DatabufHD[0], buffer, short_packet_size); - - USBHSD->UEP0_TX_LEN = short_packet_size; - USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); - USBHS_Dev_Endp0_Tog ^= 1; - } else { - xfer->queued_len += short_packet_size; - - EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer; - USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum); - EP_TX_LEN(epnum) = short_packet_size; - EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK; - } - } - } else { /* TUSB_DIR_OUT */ - if (epnum == 0) { - uint32_t read_count = USBHSD->RX_LEN; - read_count = TU_MIN(read_count, total_bytes); - - if ((total_bytes == 8)) { - read_count = 8; - memcpy(buffer, &EP0_DatabufHD[0], 8); - } else { - memcpy(buffer, &EP0_DatabufHD[0], read_count); - } - } else { - EP_RX_DMA_ADDR(epnum) = (uint32_t)xfer->buffer; - USBHSD->ENDP_CONFIG |= (USBHS_EP0_R_EN << epnum); - } - - // usbd_ep_read(ep_addr, buffer, total_bytes, &ret_bytes); - } - return true; -} - - -static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size) { - // xfer->queued_len = xfer->total_len - remaining; - - uint16_t remaining = xfer->total_len - xfer->queued_len; - uint16_t to_recv_size; - - if (remaining <= xfer->max_size) { - // Avoid buffer overflow. - to_recv_size = (xfer_size > remaining) ? remaining : xfer_size; - } else { - // Room for full packet, choose recv_size based on what the microcontroller - // claims. - to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size; - } - - if (to_recv_size) { - } - - xfer->queued_len += xfer_size; - - // Per USB spec, a short OUT packet (including length 0) is always - // indicative of the end of a transfer (at least for ctl, bulk, int). - xfer->short_packet = (xfer_size < xfer->max_size); -} - -void dcd_int_handler(uint8_t rhport) { - (void)rhport; - - uint32_t end_num, rx_token; - uint8_t intflag = 0; - - intflag = USBHSD->INT_FG; - - if (intflag & USBHS_TRANSFER_FLAG) { - - end_num = (USBHSD->INT_ST) & MASK_UIS_ENDP; - rx_token = (((USBHSD->INT_ST) & MASK_UIS_TOKEN) >> 4) & 0x03; - - uint8_t endp = end_num | (rx_token == PID_IN ? TUSB_DIR_IN_MASK : 0); - - xfer_ctl_t *xfer = XFER_CTL_BASE(end_num, tu_edpt_dir(endp)); - - if (rx_token == PID_OUT) { - uint16_t rx_len = USBHSD->RX_LEN; - - receive_packet(xfer, rx_len); - - if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { - xfer->short_packet = false; - - dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true); - } - - if (end_num == 0) { - USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0; - } - - } else if (rx_token == PID_IN) { - if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { - xfer->short_packet = false; - xfer->total_len = 0; - dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true); - - EP_TX_CTRL(end_num) = (EP_TX_CTRL(end_num) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_NAK; - - if (end_num == 0) { - } - } else { - dcd_edpt_xfer(0, endp, xfer->buffer + xfer->queued_len, xfer->total_len - xfer->queued_len); - } - } - - USBHSD->INT_FG = USBHS_TRANSFER_FLAG; /* Clear flag */ - } else if (intflag & USBHS_SETUP_FLAG) { - USBHS_Dev_Endp0_Tog = 1; - dcd_event_setup_received(0, EP0_DatabufHD, true); - - USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */ - } else if (intflag & USBHS_DETECT_FLAG) { - USBHS_Dev_Endp0_Tog = 1; - - xfer_status[0][TUSB_DIR_OUT].max_size = 64; - xfer_status[0][TUSB_DIR_IN].max_size = 64; - - dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true); - - USBHSD->DEV_AD = 0; - USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0; - - USBHSD->INT_FG = USBHS_DETECT_FLAG; /* Clear flag */ - } else if (intflag & USBHS_SUSPEND_FLAG) { - dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SUSPEND }; - dcd_event_handler(&event, true); - - USBHSD->INT_FG = USBHS_SUSPEND_FLAG; /* Clear flag */ - } -} - -#endif -- cgit v1.3.1 From 3cf21c66b6ef19c6dd648f952e8679a654b15803 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 12 Jan 2023 15:26:48 +0700 Subject: add dcd_remote_wakeup() stub --- src/portable/wch/ch32v307/dcd_usbhs.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src') diff --git a/src/portable/wch/ch32v307/dcd_usbhs.c b/src/portable/wch/ch32v307/dcd_usbhs.c index 7a0dcfc23..b7a79e166 100644 --- a/src/portable/wch/ch32v307/dcd_usbhs.c +++ b/src/portable/wch/ch32v307/dcd_usbhs.c @@ -130,6 +130,11 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { dcd_edpt_xfer(rhport, 0x80, NULL, 0); } +void dcd_remote_wakeup(uint8_t rhport) +{ + (void) rhport; +} + void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) { (void)rhport; -- cgit v1.3.1 From b1021d53f3617491656c50f6a1cb2c21da029f6a Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 12 Jan 2023 15:38:18 +0700 Subject: add TUP_RHPORT_HIGHSPEED for ch32v307 --- src/common/tusb_mcu.h | 2 +- src/tusb_option.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index b37ce9a34..0b10c5118 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -278,7 +278,7 @@ //------------- WCH -------------// #elif TU_CHECK_MCU(OPT_MCU_CH32V307) #define TUP_DCD_ENDPOINT_MAX 16 - + #define TUP_RHPORT_HIGHSPEED 1 #endif //--------------------------------------------------------------------+ diff --git a/src/tusb_option.h b/src/tusb_option.h index 92fbbd33f..67377b7ec 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -161,7 +161,7 @@ typedef int make_iso_compilers_happy; #define OPT_MCU_F1C100S 2100 ///< Allwinner F1C100s family // WCH -#define OPT_MCU_CH32V307 2200 ///< WCH CH32V307 config +#define OPT_MCU_CH32V307 2200 ///< WCH CH32V307 // Helper to check if configured MCU is one of listed // Apply _TU_CHECK_MCU with || as separator to list of input -- cgit v1.3.1 From 2e47210c1af88b88b6f2d92fe2b6d08117041363 Mon Sep 17 00:00:00 2001 From: Nathaniel Brough Date: Fri, 13 Jan 2023 13:37:55 -0800 Subject: fix: Replace device calls to memcpy with tu_memcpy_s Introduces a new function tu_memcpy_s, which is effectively a backport of memcpy_s. The change also refactors calls to memcpy over to the more secure tu_memcpy_s. --- src/class/audio/audio_device.c | 7 ++----- src/class/dfu/dfu_rt_device.c | 2 +- src/class/hid/hid_device.c | 18 +++++++----------- src/class/midi/midi_device.c | 2 +- src/class/msc/msc_device.c | 10 +++++----- src/common/tusb_common.h | 8 ++++++++ src/device/dcd.h | 2 +- src/device/usbd_control.c | 4 +++- src/tusb.c | 23 ++++++++++++++++++++++- 9 files changed, 50 insertions(+), 26 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 698fba566..81df95139 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -823,10 +823,7 @@ uint16_t tud_audio_int_ctr_n_write(uint8_t func_id, uint8_t const* buffer, uint1 // We write directly into the EP's buffer - abort if previous transfer not complete TU_VERIFY(!usbd_edpt_busy(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int_ctr)); - // Check length - TU_VERIFY(len <= CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE); - - memcpy(_audiod_fct[func_id].ep_int_ctr_buf, buffer, len); + TU_VERIFY(tu_memcpy_s(_audiod_fct[func_id].ep_int_ctr_buf, CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE, buffer, len)==0); // Schedule transmit TU_VERIFY(usbd_edpt_xfer(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int_ctr, _audiod_fct[func_id].ep_int_ctr_buf, len)); @@ -2202,7 +2199,7 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req if (len > _audiod_fct[func_id].ctrl_buf_sz) len = _audiod_fct[func_id].ctrl_buf_sz; // Copy into buffer - memcpy((void *)_audiod_fct[func_id].ctrl_buf, data, (size_t)len); + TU_VERIFY(tu_memcpy_s(_audiod_fct[func_id].ctrl_buf, sizeof(_audiod_fct[func_id].ctrl_buf), data, (size_t)len)==0); // Schedule transmit return tud_control_xfer(rhport, p_request, (void*)_audiod_fct[func_id].ctrl_buf, len); diff --git a/src/class/dfu/dfu_rt_device.c b/src/class/dfu/dfu_rt_device.c index b9cd6096b..7b77b3f8f 100644 --- a/src/class/dfu/dfu_rt_device.c +++ b/src/class/dfu/dfu_rt_device.c @@ -110,7 +110,7 @@ bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request TU_LOG2(" DFU RT Request: GETSTATUS\r\n"); dfu_status_response_t resp; // Status = OK, Poll timeout is ignored during RT, State = APP_IDLE, IString = 0 - memset(&resp, 0x00, sizeof(dfu_status_response_t)); + TU_VERIFY(tu_memset_s(&resp, sizeof(resp), 0x00, sizeof(resp))==0); tud_control_xfer(rhport, request, &resp, sizeof(dfu_status_response_t)); } break; diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c index 8077e4deb..40654eef9 100644 --- a/src/class/hid/hid_device.c +++ b/src/class/hid/hid_device.c @@ -92,16 +92,12 @@ bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, u // prepare data if (report_id) { - len = tu_min16(len, CFG_TUD_HID_EP_BUFSIZE-1); - p_hid->epin_buf[0] = report_id; - memcpy(p_hid->epin_buf+1, report, len); + TU_VERIFY(tu_memcpy_s(p_hid->epin_buf+1, CFG_TUD_HID_EP_BUFSIZE-1, report, len)==0); len++; }else { - // If report id = 0, skip ID field - len = tu_min16(len, CFG_TUD_HID_EP_BUFSIZE); - memcpy(p_hid->epin_buf, report, len); + TU_VERIFY(tu_memcpy_s(p_hid->epin_buf, CFG_TUD_HID_EP_BUFSIZE, report, len)==0); } return usbd_edpt_xfer(rhport, p_hid->ep_in, p_hid->epin_buf, len); @@ -126,7 +122,7 @@ bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modi if ( keycode ) { - memcpy(report.keycode, keycode, 6); + TU_VERIFY(tu_memcpy_s(report.keycode, sizeof(report.keycode), keycode, sizeof(report.keycode))==0); }else { tu_memclr(report.keycode, 6); @@ -151,8 +147,7 @@ bool tud_hid_n_mouse_report(uint8_t instance, uint8_t report_id, } bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id, - int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons) -{ + int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons) { hid_gamepad_report_t report = { .x = x, @@ -183,11 +178,12 @@ void hidd_reset(uint8_t rhport) } uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint16_t max_len) -{ + { TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass, 0); // len = interface + hid + n*endpoints - uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + + uint16_t const drv_len = + (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t)); TU_ASSERT(max_len >= drv_len, 0); diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c index de41706e8..0b52be181 100644 --- a/src/class/midi/midi_device.c +++ b/src/class/midi/midi_device.c @@ -182,7 +182,7 @@ uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void* buffer, ui uint8_t const count = (uint8_t) tu_min32(stream->total - stream->index, bufsize); // Skip the header (1st byte) in the buffer - memcpy(buf8, stream->buffer + 1 + stream->index, count); + TU_VERIFY(tu_memcpy_s(buf8, bufsize, stream->buffer + 1 + stream->index, count)==0); total_read += count; stream->index += count; diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 00b0a1d06..ed4a3e86c 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -707,7 +707,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ read_capa10.block_size = tu_htonl(block_size); resplen = sizeof(read_capa10); - memcpy(buffer, &read_capa10, (size_t) resplen); + TU_VERIFY(tu_memcpy_s(buffer, bufsize, &read_capa10, (size_t) resplen)); } } break; @@ -741,7 +741,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ read_fmt_capa.block_size_u16 = tu_htons(block_size); resplen = sizeof(read_fmt_capa); - memcpy(buffer, &read_fmt_capa, (size_t) resplen); + TU_VERIFY(tu_memcpy_s(buffer, bufsize, &read_fmt_capa, (size_t) resplen)==0); } } break; @@ -764,7 +764,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ tud_msc_inquiry_cb(lun, inquiry_rsp.vendor_id, inquiry_rsp.product_id, inquiry_rsp.product_rev); resplen = sizeof(inquiry_rsp); - memcpy(buffer, &inquiry_rsp, (size_t) resplen); + TU_VERIFY(tu_memcpy_s(buffer, bufsize, &inquiry_rsp, (size_t) resplen)==0); } break; @@ -788,7 +788,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ mode_resp.write_protected = !writable; resplen = sizeof(mode_resp); - memcpy(buffer, &mode_resp, (size_t) resplen); + TU_VERIFY(tu_memcpy_s(buffer, bufsize, &mode_resp, (size_t) resplen)==0); } break; @@ -806,7 +806,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ sense_rsp.add_sense_qualifier = p_msc->add_sense_qualifier; resplen = sizeof(sense_rsp); - memcpy(buffer, &sense_rsp, (size_t) resplen); + TU_VERIFY(tu_memcpy_s(buffer, bufsize, &sense_rsp, (size_t) resplen)==0); // request sense callback could overwrite the sense data if (tud_msc_request_sense_cb) diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index b1ee40a1a..78fdcfe36 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -83,6 +83,14 @@ #define tu_memclr(buffer, size) memset((buffer), 0, (size)) #define tu_varclr(_var) tu_memclr(_var, sizeof(*(_var))) +// This is a backport of memset_s from c11 +int32_t tu_memset_s(void *dest, size_t destsz, int ch, size_t count); + +// This is a backport of memcpy_s from c11 +int32_t tu_memcpy_s(void *dest, size_t destsz, + const void * src, size_t count ); + + //------------- Bytes -------------// TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0) { diff --git a/src/device/dcd.h b/src/device/dcd.h index c1780f656..3a7e6c5df 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -193,7 +193,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_reset (uint8_t rhport, t TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr) { dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SETUP_RECEIVED }; - memcpy(&event.setup_received, setup, 8); + memcpy(&event.setup_received, setup, sizeof(tusb_control_request_t)); dcd_event_handler(&event, in_isr); } diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index 0995ef669..ce4ddab66 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -93,7 +93,9 @@ static bool _data_stage_xact(uint8_t rhport) if ( _ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN ) { ep_addr = EDPT_CTRL_IN; - if ( xact_len ) memcpy(_usbd_ctrl_buf, _ctrl_xfer.buffer, xact_len); + if ( xact_len ) { + TU_VERIFY(tu_memcpy_s(_usbd_ctrl_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)==0); + } } return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _usbd_ctrl_buf : NULL, xact_len); diff --git a/src/tusb.c b/src/tusb.c index a5c820b8d..c918b0248 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -24,6 +24,7 @@ * This file is part of the TinyUSB stack. */ +#include "common/tusb_common.h" #include "tusb_option.h" #if CFG_TUH_ENABLED || CFG_TUD_ENABLED @@ -460,7 +461,7 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent) tu_printf("%04X: ", 16*i/item_per_line); } - memcpy(&value, buf8, size); + tu_memcpy_s(&value, sizeof(value), buf8, size); buf8 += size; tu_printf(" "); @@ -486,3 +487,23 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent) #endif #endif // host or device enabled + +//--------------------------------------------------------------------+ +// Common +//--------------------------------------------------------------------+ + +int32_t tu_memset_s(void *dest, size_t destsz, int ch, size_t count) { + if (count > destsz) { + return -1; + } + memset(dest, ch, count); + return 0; +} + +int32_t tu_memcpy_s(void *dest, size_t destsz, const void *src, size_t count) { + if (count > destsz) { + return -1; + } + memcpy(dest, src, count); + return 0; +} \ No newline at end of file -- cgit v1.3.1 From 074289caa31297b7261d9484f529f481d0fc9f06 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 20 Jan 2023 15:30:24 +0700 Subject: add helper tu_desc_find/find2/find3 --- src/common/tusb_types.h | 13 +++++++++++++ src/tusb.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) (limited to 'src') diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 32cdba450..82798a484 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -543,22 +543,35 @@ TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_ //--------------------------------------------------------------------+ // Descriptor helper //--------------------------------------------------------------------+ + +// return next descriptor TU_ATTR_ALWAYS_INLINE static inline uint8_t const * tu_desc_next(void const* desc) { uint8_t const* desc8 = (uint8_t const*) desc; return desc8 + desc8[DESC_OFFSET_LEN]; } +// get descriptor type TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_type(void const* desc) { return ((uint8_t const*) desc)[DESC_OFFSET_TYPE]; } +// get descriptor length TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_len(void const* desc) { return ((uint8_t const*) desc)[DESC_OFFSET_LEN]; } +// find descriptor that match byte1 (type) +uint8_t const * tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1); + +// find descriptor that match byte1 (type) and byte2 +uint8_t const * tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2); + +// find descriptor that match byte1 (type) and byte2 +uint8_t const * tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3); + #ifdef __cplusplus } #endif diff --git a/src/tusb.c b/src/tusb.c index a5c820b8d..44b34b0e6 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -73,6 +73,41 @@ bool tusb_inited(void) return ret; } +//--------------------------------------------------------------------+ +// Descriptor helper +//--------------------------------------------------------------------+ + +uint8_t const * tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1) +{ + while(desc+1 < end) + { + if ( desc[1] == byte1 ) return desc; + desc += desc[DESC_OFFSET_LEN]; + } + return NULL; +} + +uint8_t const * tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2) +{ + while(desc+2 < end) + { + if ( desc[1] == byte1 && desc[2] == byte2) return desc; + desc += desc[DESC_OFFSET_LEN]; + } + return NULL; +} + +uint8_t const * tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3) +{ + while(desc+3 < end) + { + if (desc[1] == byte1 && desc[2] == byte2 && desc[3] == byte3) return desc; + desc += desc[DESC_OFFSET_LEN]; + } + return NULL; +} + + //--------------------------------------------------------------------+ // Endpoint Helper for both Host and Device stack //--------------------------------------------------------------------+ -- cgit v1.3.1 From daec3c24d86682946aea5d9c38623b466851836e Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 20 Jan 2023 15:30:45 +0700 Subject: fix warnings with arithmetic on void* pointer --- src/class/video/video_device.c | 51 ++++++++++++++++++++++++------------------ 1 file changed, 29 insertions(+), 22 deletions(-) (limited to 'src') diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index e17d0a90f..257285126 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -108,7 +108,7 @@ typedef struct TU_ATTR_PACKED { /* video control interface */ typedef struct TU_ATTR_PACKED { - void const *beg; /* The head of the first video control interface descriptor */ + uint8_t const *beg; /* The head of the first video control interface descriptor */ uint16_t len; /* Byte length of the descriptors */ uint16_t cur; /* offset for current video control interface */ uint8_t stm[CFG_TUD_VIDEO_STREAMING]; /* Indices of streaming interface */ @@ -174,7 +174,7 @@ static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self) static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const *self) { if (!self->desc.cur) return NULL; - void const *desc = _videod_itf[self->index_vc].beg; + uint8_t const *desc = _videod_itf[self->index_vc].beg; return (tusb_desc_vs_itf_t const*)(desc + self->desc.cur); } @@ -247,9 +247,9 @@ static void const* _next_desc_itf(void const *beg, void const *end) * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static inline void const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t itfnum, uint_fast8_t altnum) +static inline uint8_t const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t itfnum, uint_fast8_t altnum) { - return _find_desc_3(beg, end, TUSB_DESC_INTERFACE, itfnum, altnum); + return (uint8_t const*) _find_desc_3(beg, end, TUSB_DESC_INTERFACE, itfnum, altnum); } /** Find the first endpoint descriptor belonging to the current interface descriptor. @@ -275,7 +275,7 @@ static void const* _find_desc_ep(void const *beg, void const *end) static inline void const* _end_of_control_descriptor(void const *desc) { tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)desc; - return desc + vc->std.bLength + vc->ctl.wTotalLength; + return ((uint8_t const*) desc) + vc->std.bLength + tu_le16toh(vc->ctl.wTotalLength); } /** Find the first entity descriptor with the entity ID @@ -305,7 +305,7 @@ static void const* _find_desc_entity(void const *desc, uint_fast8_t entityid) static inline void const* _end_of_streaming_descriptor(void const *desc) { tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const *)desc; - return desc + vs->std.bLength + vs->stm.wTotalLength; + return ((uint8_t const*) desc) + vs->std.bLength + tu_le16toh(vs->stm.wTotalLength); } /** Find the first format descriptor with the specified format number. */ @@ -581,8 +581,10 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const * static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) { tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); + /* The next descriptor after the class-specific VC interface header descriptor. */ - void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength; + void const *cur = (uint8_t const*)vc + vc->std.bLength + vc->ctl.bLength; + /* The end of the video control interface descriptor. */ void const *end = _end_of_control_descriptor(vc); if (vc->std.bNumEndpoints) { @@ -603,10 +605,11 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum) { TU_LOG2(" open VC %d\n", altnum); - void const *beg = self->beg; - void const *end = beg + self->len; + uint8_t const *beg = self->beg; + uint8_t const *end = beg + self->len; + /* The first descriptor is a video control interface descriptor. */ - void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); + uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); TU_LOG2(" cur %d\n", cur - beg); TU_VERIFY(cur < end); @@ -616,7 +619,8 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t TU_ASSERT(vc->ctl.bInCollection <= CFG_TUD_VIDEO_STREAMING); /* Update to point the end of the video control interface descriptor. */ - end = _end_of_control_descriptor(cur); + end = _end_of_control_descriptor(cur); + /* Advance to the next descriptor after the class-specific VC interface header descriptor. */ cur += vc->std.bLength + vc->ctl.bLength; TU_LOG2(" bNumEndpoints %d\n", vc->std.bNumEndpoints); @@ -631,7 +635,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t /* Open the notification endpoint */ TU_ASSERT(usbd_edpt_open(rhport, notif)); } - self->cur = (uint16_t) ((void const*)vc - beg); + self->cur = (uint16_t) ((uint8_t const*)vc - beg); return true; } @@ -643,7 +647,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint { uint_fast8_t i; TU_LOG2(" reopen VS %d\n", altnum); - void const *desc = _videod_itf[stm->index_vc].beg; + uint8_t const *desc = _videod_itf[stm->index_vc].beg; /* Close endpoints of previous settings. */ for (i = 0; i < TU_ARRAY_SIZE(stm->desc.ep); ++i) { @@ -654,16 +658,18 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint stm->desc.ep[i] = 0; TU_LOG2(" close EP%02x\n", ep_adr); } + /* clear transfer management information */ stm->buffer = NULL; stm->bufsize = 0; stm->offset = 0; /* Find a alternate interface */ - void const *beg = desc + stm->desc.beg; - void const *end = desc + stm->desc.end; - void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); + uint8_t const *beg = desc + stm->desc.beg; + uint8_t const *end = desc + stm->desc.end; + uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); TU_VERIFY(cur < end); + uint_fast8_t numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints; TU_ASSERT(numeps <= TU_ARRAY_SIZE(stm->desc.ep)); stm->desc.cur = (uint16_t) (cur - desc); /* Save the offset of the new settings */ @@ -1043,7 +1049,6 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage, default: return VIDEO_ERROR_INVALID_REQUEST; } - return VIDEO_ERROR_UNKNOWN; } //--------------------------------------------------------------------+ @@ -1076,7 +1081,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu if (!stm || !stm->desc.ep[0] || stm->buffer) return false; /* Find EP address */ - void const *desc = _videod_itf[stm->index_vc].beg; + uint8_t const *desc = _videod_itf[stm->index_vc].beg; uint8_t ep_addr = 0; for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) { uint_fast16_t ofs_ep = stm->desc.ep[i]; @@ -1143,13 +1148,15 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin } TU_ASSERT(ctl_idx < CFG_TUD_VIDEO, 0); - void const *end = (void const*)itf_desc + max_len; - self->beg = itf_desc; + uint8_t const *end = (uint8_t const*)itf_desc + max_len; + self->beg = (uint8_t const*) itf_desc; self->len = max_len; + /*------------- Video Control Interface -------------*/ TU_VERIFY(_open_vc_itf(rhport, self, 0), 0); tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); uint_fast8_t bInCollection = vc->ctl.bInCollection; + /* Find the end of the video interface descriptor */ void const *cur = _next_desc_itf(itf_desc, end); for (uint8_t stm_idx = 0; stm_idx < bInCollection; ++stm_idx) { @@ -1200,7 +1207,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ for (itf = 0; itf < CFG_TUD_VIDEO_STREAMING; ++itf) { videod_streaming_interface_t *stm = &_videod_streaming_itf[itf]; if (!stm->desc.beg) continue; - void const *desc = _videod_itf[stm->index_vc].beg; + uint8_t const *desc = _videod_itf[stm->index_vc].beg; if (itfnum == _desc_itfnum(desc + stm->desc.beg)) break; } @@ -1226,7 +1233,7 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3 uint_fast16_t const ep_ofs = stm->desc.ep[0]; if (!ep_ofs) continue; ctl = &_videod_itf[stm->index_vc]; - void const *desc = ctl->beg; + uint8_t const *desc = ctl->beg; if (ep_addr == _desc_ep_addr(desc + ep_ofs)) break; } -- cgit v1.3.1 From 18c3095346159a4f5c3db9775b4f7c6aebca77c2 Mon Sep 17 00:00:00 2001 From: Nathaniel Brough Date: Fri, 20 Jan 2023 15:40:32 -0800 Subject: fix: Change all static variables to thread when fuzzing --- .vscode/settings.json | 3 +++ src/class/cdc/cdc_device.c | 2 +- src/class/dfu/dfu_device.c | 14 +++++++------- src/class/hid/hid_device.c | 2 +- src/class/msc/msc_device.c | 8 ++++---- src/class/net/ecm_rndis_device.c | 14 +++++++------- src/class/net/ncm_device.c | 12 ++++++------ src/class/usbtmc/usbtmc_device.c | 8 ++++---- src/class/vendor/vendor_device.c | 2 +- src/class/vendor/vendor_device.h | 2 +- src/class/video/video_device.c | 8 ++++---- src/common/tusb_compiler.h | 7 +++++++ src/common/tusb_debug.h | 2 +- src/common/tusb_types.h | 4 ++-- src/device/usbd.c | 18 +++++++++--------- src/device/usbd_control.c | 4 ++-- test/fuzz/dcd_fuzz.cc | 2 +- test/fuzz/device/msc/src/usb_descriptors.cc | 4 ++-- test/fuzz/device/net/src/usb_descriptors.cc | 4 ++-- test/fuzz/make.mk | 3 ++- 20 files changed, 67 insertions(+), 56 deletions(-) create mode 100644 .vscode/settings.json (limited to 'src') diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 000000000..97924983a --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,3 @@ +{ + "editor.formatOnSave": false +} \ No newline at end of file diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index 8d10a416c..b943c1caf 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -76,7 +76,7 @@ typedef struct //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC]; +CFG_TUSB_MEM_SECTION TU_STATIC cdcd_interface_t _cdcd_itf[CFG_TUD_CDC]; static bool _prep_out_transaction (cdcd_interface_t* p_cdc) { diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c index aa5891ca9..a318603d3 100644 --- a/src/class/dfu/dfu_device.c +++ b/src/class/dfu/dfu_device.c @@ -56,7 +56,7 @@ typedef struct } dfu_state_ctx_t; // Only a single dfu state is allowed -CFG_TUSB_MEM_SECTION static dfu_state_ctx_t _dfu_ctx; +CFG_TUSB_MEM_SECTION TU_STATIC dfu_state_ctx_t _dfu_ctx; static void reset_state(void) { @@ -74,7 +74,7 @@ static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, tusb_cont //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= 2 -static tu_lookup_entry_t const _dfu_request_lookup[] = +TU_STATIC tu_lookup_entry_t const _dfu_request_lookup[] = { { .key = DFU_REQUEST_DETACH , .data = "DETACH" }, { .key = DFU_REQUEST_DNLOAD , .data = "DNLOAD" }, @@ -85,13 +85,13 @@ static tu_lookup_entry_t const _dfu_request_lookup[] = { .key = DFU_REQUEST_ABORT , .data = "ABORT" }, }; -static tu_lookup_table_t const _dfu_request_table = +TU_STATIC tu_lookup_table_t const _dfu_request_table = { .count = TU_ARRAY_SIZE(_dfu_request_lookup), .items = _dfu_request_lookup }; -static tu_lookup_entry_t const _dfu_state_lookup[] = +TU_STATIC tu_lookup_entry_t const _dfu_state_lookup[] = { { .key = APP_IDLE , .data = "APP_IDLE" }, { .key = APP_DETACH , .data = "APP_DETACH" }, @@ -106,13 +106,13 @@ static tu_lookup_entry_t const _dfu_state_lookup[] = { .key = DFU_ERROR , .data = "ERROR" }, }; -static tu_lookup_table_t const _dfu_state_table = +TU_STATIC tu_lookup_table_t const _dfu_state_table = { .count = TU_ARRAY_SIZE(_dfu_state_lookup), .items = _dfu_state_lookup }; -static tu_lookup_entry_t const _dfu_status_lookup[] = +TU_STATIC tu_lookup_entry_t const _dfu_status_lookup[] = { { .key = DFU_STATUS_OK , .data = "OK" }, { .key = DFU_STATUS_ERR_TARGET , .data = "errTARGET" }, @@ -132,7 +132,7 @@ static tu_lookup_entry_t const _dfu_status_lookup[] = { .key = DFU_STATUS_ERR_STALLEDPKT , .data = "errSTALLEDPKT" }, }; -static tu_lookup_table_t const _dfu_status_table = +TU_STATIC tu_lookup_table_t const _dfu_status_table = { .count = TU_ARRAY_SIZE(_dfu_status_lookup), .items = _dfu_status_lookup diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c index 8077e4deb..c42d1b6de 100644 --- a/src/class/hid/hid_device.c +++ b/src/class/hid/hid_device.c @@ -58,7 +58,7 @@ typedef struct tusb_hid_descriptor_hid_t const * hid_descriptor; } hidd_interface_t; -CFG_TUSB_MEM_SECTION static hidd_interface_t _hidd_itf[CFG_TUD_HID]; +CFG_TUSB_MEM_SECTION TU_STATIC hidd_interface_t _hidd_itf[CFG_TUD_HID]; /*------------- Helpers -------------*/ static inline uint8_t get_index_by_itfnum(uint8_t itf_num) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 00b0a1d06..bf56ed9bf 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -71,8 +71,8 @@ typedef struct uint8_t add_sense_qualifier; }mscd_interface_t; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static mscd_interface_t _mscd_itf; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE]; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC mscd_interface_t _mscd_itf; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE]; //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION @@ -202,7 +202,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= 2 -TU_ATTR_UNUSED static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = +TU_ATTR_UNUSED TU_STATIC tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = { { .key = SCSI_CMD_TEST_UNIT_READY , .data = "Test Unit Ready" }, { .key = SCSI_CMD_INQUIRY , .data = "Inquiry" }, @@ -217,7 +217,7 @@ TU_ATTR_UNUSED static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = { .key = SCSI_CMD_WRITE_10 , .data = "Write10" } }; -TU_ATTR_UNUSED static tu_lookup_table_t const _msc_scsi_cmd_table = +TU_ATTR_UNUSED TU_STATIC tu_lookup_table_t const _msc_scsi_cmd_table = { .count = TU_ARRAY_SIZE(_msc_scsi_cmd_lookup), .items = _msc_scsi_cmd_lookup diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c index c7428bcda..560e1768d 100644 --- a/src/class/net/ecm_rndis_device.c +++ b/src/class/net/ecm_rndis_device.c @@ -61,8 +61,8 @@ typedef struct #define CFG_TUD_NET_PACKET_PREFIX_LEN sizeof(rndis_data_packet_t) #define CFG_TUD_NET_PACKET_SUFFIX_LEN 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; struct ecm_notify_struct { @@ -70,7 +70,7 @@ struct ecm_notify_struct uint32_t downlink, uplink; }; -static const struct ecm_notify_struct ecm_notify_nc = +TU_STATIC const struct ecm_notify_struct ecm_notify_nc = { .header = { .bmRequestType = 0xA1, @@ -80,7 +80,7 @@ static const struct ecm_notify_struct ecm_notify_nc = }, }; -static const struct ecm_notify_struct ecm_notify_csc = +TU_STATIC const struct ecm_notify_struct ecm_notify_csc = { .header = { .bmRequestType = 0xA1, @@ -92,7 +92,7 @@ static const struct ecm_notify_struct ecm_notify_csc = }; // TODO remove CFG_TUSB_MEM_SECTION, control internal buffer is already in this special section -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static union +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC union { uint8_t rndis_buf[120]; struct ecm_notify_struct ecm_buf; @@ -102,9 +102,9 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static union // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ // TODO remove CFG_TUSB_MEM_SECTION -CFG_TUSB_MEM_SECTION static netd_interface_t _netd_itf; +CFG_TUSB_MEM_SECTION TU_STATIC netd_interface_t _netd_itf; -static bool can_xmit; +TU_STATIC bool can_xmit; void tud_network_recv_renew(void) { diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c index 1cbc0ce01..236232191 100644 --- a/src/class/net/ncm_device.c +++ b/src/class/net/ncm_device.c @@ -130,7 +130,7 @@ typedef struct // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static const ntb_parameters_t ntb_parameters = { +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC const ntb_parameters_t ntb_parameters = { .wLength = sizeof(ntb_parameters_t), .bmNtbFormatsSupported = 0x01, .dwNtbInMaxSize = CFG_TUD_NCM_IN_NTB_MAX_SIZE, @@ -145,11 +145,11 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static const ntb_parameters_t ntb_parame .wNtbOutMaxDatagrams = 0 }; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static transmit_ntb_t transmit_ntb[2]; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC transmit_ntb_t transmit_ntb[2]; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE]; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE]; -static ncm_interface_t ncm_interface; +TU_STATIC ncm_interface_t ncm_interface; /* * Set up the NTB state in ncm_interface to be ready to add datagrams. @@ -196,7 +196,7 @@ static void ncm_start_tx(void) { ncm_prepare_for_tx(); } -static struct ecm_notify_struct ncm_notify_connected = +TU_STATIC struct ecm_notify_struct ncm_notify_connected = { .header = { .bmRequestType_bit = { @@ -210,7 +210,7 @@ static struct ecm_notify_struct ncm_notify_connected = }, }; -static struct ecm_notify_struct ncm_notify_speed_change = +TU_STATIC struct ecm_notify_struct ncm_notify_speed_change = { .header = { .bmRequestType_bit = { diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index 0cf0743a7..fd8220c1f 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -78,7 +78,7 @@ #ifdef xDEBUG #include "uart_util.h" -static char logMsg[150]; +TU_STATIC char logMsg[150]; #endif // Buffer size must be an exact multiple of the max packet size for both @@ -143,7 +143,7 @@ typedef struct usbtmc_capabilities_specific_t const * capabilities; } usbtmc_interface_state_t; -CFG_TUSB_MEM_SECTION static usbtmc_interface_state_t usbtmc_state = +CFG_TUSB_MEM_SECTION TU_STATIC usbtmc_interface_state_t usbtmc_state = { .itf_id = 0xFF, }; @@ -154,8 +154,8 @@ TU_VERIFY_STATIC(USBTMCD_BUFFER_SIZE >= 32u,"USBTMC dev buffer size too small"); static bool handle_devMsgOutStart(uint8_t rhport, void *data, size_t len); static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t packetLen); -static uint8_t termChar; -static uint8_t termCharRequested = false; +TU_STATIC uint8_t termChar; +TU_STATIC uint8_t termCharRequested = false; #if OSAL_MUTEX_REQUIRED static OSAL_MUTEX_DEF(usbtmcLockBuffer); diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index 3b81a108f..b33cbcf13 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -59,7 +59,7 @@ typedef struct CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_VENDOR_EPSIZE]; } vendord_interface_t; -CFG_TUSB_MEM_SECTION static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR]; +CFG_TUSB_MEM_SECTION TU_STATIC vendord_interface_t _vendord_itf[CFG_TUD_VENDOR]; #define ITF_MEM_RESET_SIZE offsetof(vendord_interface_t, rx_ff) diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h index 4a873e5fc..543500f0c 100644 --- a/src/class/vendor/vendor_device.h +++ b/src/class/vendor/vendor_device.h @@ -50,7 +50,7 @@ void tud_vendor_n_read_flush (uint8_t itf); uint32_t tud_vendor_n_write (uint8_t itf, void const* buffer, uint32_t bufsize); uint32_t tud_vendor_n_write_available (uint8_t itf); -static inline +TU_STATIC inline uint32_t tud_vendor_n_write_str (uint8_t itf, char const* str); uint32_t tud_vendor_n_flush (uint8_t itf); diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index e17d0a90f..14518deac 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -125,11 +125,11 @@ typedef struct TU_ATTR_PACKED { //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION static videod_interface_t _videod_itf[CFG_TUD_VIDEO]; -CFG_TUSB_MEM_SECTION static videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING]; +CFG_TUSB_MEM_SECTION TU_STATIC videod_interface_t _videod_itf[CFG_TUD_VIDEO]; +CFG_TUSB_MEM_SECTION TU_STATIC videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING]; -static uint8_t const _cap_get = 0x1u; /* support for GET */ -static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */ +TU_STATIC uint8_t const _cap_get = 0x1u; /* support for GET */ +TU_STATIC uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */ /** Get interface number from the interface descriptor * diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index 2c30daf6f..6a02959ca 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -61,6 +61,13 @@ #define TU_VERIFY_STATIC(const_expr, _mess) enum { TU_XSTRCAT(_verify_static_, _TU_COUNTER_) = 1/(!!(const_expr)) } #endif +/* --------------------- Fuzzing types -------------------------------------- */ +#ifdef FUZZ + #define TU_STATIC __thread static +#else + #define TU_STATIC static +#endif + // for declaration of reserved field, make use of _TU_COUNTER_ #define TU_RESERVED TU_XSTRCAT(reserved, _TU_COUNTER_) diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h index 65fd1920d..8587b6771 100644 --- a/src/common/tusb_debug.h +++ b/src/common/tusb_debug.h @@ -114,7 +114,7 @@ typedef struct static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key) { - static char not_found[11]; + TU_STATIC char not_found[11]; for(uint16_t i=0; icount; i++) { diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 32cdba450..56f782ca3 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -529,13 +529,13 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpo #if CFG_TUSB_DEBUG TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir) { - static const char *str[] = {"out", "in"}; + TU_STATIC const char *str[] = {"out", "in"}; return str[dir]; } TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t) { - static const char *str[] = {"control", "isochronous", "bulk", "interrupt"}; + TU_STATIC const char *str[] = {"control", "isochronous", "bulk", "interrupt"}; return str[t]; } #endif diff --git a/src/device/usbd.c b/src/device/usbd.c index 6e0c6710d..72fa2bd4c 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -76,7 +76,7 @@ typedef struct }usbd_device_t; -static usbd_device_t _usbd_dev; +TU_STATIC usbd_device_t _usbd_dev; //--------------------------------------------------------------------+ // Class Driver @@ -88,7 +88,7 @@ static usbd_device_t _usbd_dev; #endif // Built-in class drivers -static usbd_class_driver_t const _usbd_driver[] = +TU_STATIC usbd_class_driver_t const _usbd_driver[] = { #if CFG_TUD_CDC { @@ -238,8 +238,8 @@ static usbd_class_driver_t const _usbd_driver[] = enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) }; // Additional class drivers implemented by application -static usbd_class_driver_t const * _app_driver = NULL; -static uint8_t _app_driver_count = 0; +TU_STATIC usbd_class_driver_t const * _app_driver = NULL; +TU_STATIC uint8_t _app_driver_count = 0; // virtually joins built-in and application drivers together. // Application is positioned first to allow overwriting built-in ones. @@ -265,17 +265,17 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid) //--------------------------------------------------------------------+ enum { RHPORT_INVALID = 0xFFu }; -static uint8_t _usbd_rhport = RHPORT_INVALID; +TU_STATIC uint8_t _usbd_rhport = RHPORT_INVALID; // Event queue // usbd_int_set() is used as mutex in OS NONE config OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t); -static osal_queue_t _usbd_q; +TU_STATIC osal_queue_t _usbd_q; // Mutex for claiming endpoint #if OSAL_MUTEX_REQUIRED - static osal_mutex_def_t _ubsd_mutexdef; - static osal_mutex_t _usbd_mutex; + TU_STATIC osal_mutex_def_t _ubsd_mutexdef; + TU_STATIC osal_mutex_t _usbd_mutex; #else #define _usbd_mutex NULL #endif @@ -299,7 +299,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, // Debug //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= 2 -static char const* const _usbd_event_str[DCD_EVENT_COUNT] = +TU_STATIC char const* const _usbd_event_str[DCD_EVENT_COUNT] = { "Invalid" , "Bus Reset" , diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index 0995ef669..c3ff7459d 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -53,10 +53,10 @@ typedef struct usbd_control_xfer_cb_t complete_cb; } usbd_control_xfer_t; -static usbd_control_xfer_t _ctrl_xfer; +TU_STATIC usbd_control_xfer_t _ctrl_xfer; CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN -static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE]; +TU_STATIC uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE]; //--------------------------------------------------------------------+ // Application API diff --git a/test/fuzz/dcd_fuzz.cc b/test/fuzz/dcd_fuzz.cc index 7153e20f0..04b5ce6d7 100644 --- a/test/fuzz/dcd_fuzz.cc +++ b/test/fuzz/dcd_fuzz.cc @@ -39,7 +39,7 @@ struct State { uint8_t address; }; -static State state = {false, 0, 0}; +TU_STATIC State state = {false, 0, 0}; //--------------------------------------------------------------------+ // Controller API diff --git a/test/fuzz/device/msc/src/usb_descriptors.cc b/test/fuzz/device/msc/src/usb_descriptors.cc index ded401fc9..91db232ac 100644 --- a/test/fuzz/device/msc/src/usb_descriptors.cc +++ b/test/fuzz/device/msc/src/usb_descriptors.cc @@ -44,7 +44,7 @@ // Invoked when received GET DEVICE DESCRIPTOR // Application return pointer to descriptor uint8_t const *tud_descriptor_device_cb(void) { - static tusb_desc_device_t const desc_device = { + TU_STATIC tusb_desc_device_t const desc_device = { .bLength = sizeof(tusb_desc_device_t), .bDescriptorType = TUSB_DESC_DEVICE, .bcdUSB = USB_BCD, @@ -184,7 +184,7 @@ char const *string_desc_arr[] = { }; -static uint16_t _desc_str[32]; +TU_STATIC uint16_t _desc_str[32]; // Invoked when received GET STRING DESCRIPTOR request // Application return pointer to descriptor, whose contents must exist long diff --git a/test/fuzz/device/net/src/usb_descriptors.cc b/test/fuzz/device/net/src/usb_descriptors.cc index c600bd801..0223ed298 100644 --- a/test/fuzz/device/net/src/usb_descriptors.cc +++ b/test/fuzz/device/net/src/usb_descriptors.cc @@ -45,7 +45,7 @@ // Invoked when received GET DEVICE DESCRIPTOR // Application return pointer to descriptor uint8_t const *tud_descriptor_device_cb(void) { - static tusb_desc_device_t const desc_device = { + TU_STATIC tusb_desc_device_t const desc_device = { .bLength = sizeof(tusb_desc_device_t), .bDescriptorType = TUSB_DESC_DEVICE, .bcdUSB = USB_BCD, @@ -189,7 +189,7 @@ char const *string_desc_arr[] = { "TinyUSB CDC", // 4: CDC Interface }; -static uint16_t _desc_str[32]; +TU_STATIC uint16_t _desc_str[32]; // Invoked when received GET STRING DESCRIPTOR request // Application return pointer to descriptor, whose contents must exist long diff --git a/test/fuzz/make.mk b/test/fuzz/make.mk index 6717ebc80..5e8658ad0 100644 --- a/test/fuzz/make.mk +++ b/test/fuzz/make.mk @@ -78,7 +78,8 @@ CFLAGS += \ CFLAGS += \ -Wno-error=unreachable-code \ -DOPT_MCU_FUZZ=1 \ - -DCFG_TUSB_MCU=OPT_MCU_FUZZ + -DCFG_TUSB_MCU=OPT_MCU_FUZZ \ + -DFUZZ CXXFLAGS += \ -xc++ \ -- cgit v1.3.1 From 1bbeb6ad79fa1e76c109592773e0834e1ec00a0c Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 21 Jan 2023 11:32:37 +0700 Subject: update stm32f1 to support iar build --- .github/workflows/build_iar.yml | 1 + examples/rules.mk | 4 +++ hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk | 4 ++- hw/bsp/stm32f0/boards/stm32f072disco/board.mk | 2 +- hw/bsp/stm32f0/boards/stm32f072eval/board.mk | 2 +- hw/bsp/stm32f0/family.mk | 11 +++++--- hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk | 10 ++++--- .../stm32f103_bluepill/stm32f103x8_flash.icf | 31 ++++++++++++++++++++++ hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk | 10 ++++--- hw/bsp/stm32f1/family.c | 5 ++-- hw/bsp/stm32f1/family.mk | 15 ++++++++--- src/common/tusb_compiler.h | 4 +-- 12 files changed, 79 insertions(+), 20 deletions(-) create mode 100644 hw/bsp/stm32f1/boards/stm32f103_bluepill/stm32f103x8_flash.icf (limited to 'src') diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml index 4c43400ab..40c7d7f26 100644 --- a/.github/workflows/build_iar.yml +++ b/.github/workflows/build_iar.yml @@ -28,6 +28,7 @@ jobs: family: # Alphabetical order - 'stm32f0' + - 'stm32f1' steps: - name: Clean workspace run: | diff --git a/examples/rules.mk b/examples/rules.mk index 19ecbc9e1..6a62288ce 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -72,6 +72,10 @@ ifdef LD_FILE LDFLAGS += -Wl,-T,$(TOP)/$(LD_FILE) endif +ifdef GCC_LD_FILE +LDFLAGS += -Wl,-T,$(TOP)/$(GCC_LD_FILE) +endif + ifneq ($(SKIP_NANOLIB), 1) LDFLAGS += -specs=nosys.specs -specs=nano.specs endif diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk index f470b80f0..cf787a103 100644 --- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk +++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk @@ -1,8 +1,10 @@ CFLAGS += -DSTM32F070xB -DCFG_EXAMPLE_VIDEO_READONLY +# GCC GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f070xb.s -LD_FILE = $(BOARD_PATH)/stm32F070rbtx_flash.ld +GCC_LD_FILE = $(BOARD_PATH)/stm32F070rbtx_flash.ld +# IAR IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f070xb.s IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f070xb_flash.icf diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk index edee9b0e8..4216ba186 100644 --- a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk +++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk @@ -1,7 +1,7 @@ CFLAGS += -DSTM32F072xB -DCFG_EXAMPLE_VIDEO_READONLY GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s -LD_FILE = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld +GCC_LD_FILE = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f072xb.s IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f072xb_flash.icf diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk index 6503d3273..bb9cba22a 100644 --- a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk +++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk @@ -1,7 +1,7 @@ CFLAGS += -DSTM32F072xB -DLSI_VALUE=40000 -DCFG_EXAMPLE_VIDEO_READONLY GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s -LD_FILE = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld +GCC_LD_FILE = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f072xb.s IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f072xb_flash.icf diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk index a81ab426f..2983af49e 100644 --- a/hw/bsp/stm32f0/family.mk +++ b/hw/bsp/stm32f0/family.mk @@ -7,13 +7,14 @@ ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver include $(TOP)/$(BOARD_PATH)/board.mk +# -------------- +# Compiler Flags +# -------------- CFLAGS += \ -DCFG_EXAMPLE_MSC_READONLY \ -DCFG_TUSB_MCU=OPT_MCU_STM32F0 -# -------------- # GCC Flags -# -------------- GCC_CFLAGS += \ -flto \ -mthumb \ @@ -25,12 +26,14 @@ GCC_CFLAGS += \ # suppress warning caused by vendor mcu driver GCC_CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual -# -------------- # IAR Flags -# -------------- IAR_CFLAGS += --cpu cortex-m0 IAR_ASFLAGS += --cpu cortex-m0 +# ------------------------ +# All source paths should be relative to the top level. +# ------------------------ + SRC_C += \ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk index db64b3a3f..159b3ecb6 100644 --- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk +++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk @@ -1,8 +1,12 @@ CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U -DCFG_EXAMPLE_VIDEO_READONLY -# All source paths should be relative to the top level. -LD_FILE = $(BOARD_PATH)/STM32F103X8_FLASH.ld -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s +# GCC +GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s +GCC_LD_FILE = $(BOARD_PATH)/STM32F103X8_FLASH.ld + +# IAR +IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f103xb.s +IAR_LD_FILE = $(BOARD_PATH)/stm32f103x8_flash.icf # For flash-jlink target JLINK_DEVICE = stm32f103c8 diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/stm32f103x8_flash.icf b/hw/bsp/stm32f1/boards/stm32f103_bluepill/stm32f103x8_flash.icf new file mode 100644 index 000000000..07601c2e8 --- /dev/null +++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/stm32f103x8_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk index eeda87080..efea75be7 100644 --- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk +++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk @@ -1,8 +1,12 @@ CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U -# All source paths should be relative to the top level. -LD_FILE = $(BOARD_PATH)/STM32F103XC_FLASH.ld -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s +# GCC +GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s +GCC_LD_FILE = $(BOARD_PATH)/STM32F103XC_FLASH.ld + +# IAR +IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f103xb.s +IAR_LD_FILE = $(BOARD_PATH)/stm32f103xc_flash.icf # For flash-jlink target JLINK_DEVICE = stm32f103rc diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c index 8fcf9ebd6..246d496c8 100644 --- a/hw/bsp/stm32f1/family.c +++ b/hw/bsp/stm32f1/family.c @@ -104,7 +104,8 @@ void board_init(void) void board_led_write(bool state) { - HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); + GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON)); + HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state); } uint32_t board_button_read(void) @@ -139,7 +140,7 @@ uint32_t board_millis(void) void HardFault_Handler (void) { - asm("bkpt"); + __asm("BKPT #0\n"); } #ifdef USE_FULL_ASSERT diff --git a/hw/bsp/stm32f1/family.mk b/hw/bsp/stm32f1/family.mk index 3fb2e6e70..4327f1cf8 100644 --- a/hw/bsp/stm32f1/family.mk +++ b/hw/bsp/stm32f1/family.mk @@ -6,19 +6,28 @@ ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver include $(TOP)/$(BOARD_PATH)/board.mk +# -------------- +# Compiler Flags +# -------------- CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_STM32F1 + +# GCC Flags +GCC_CFLAGS += \ -flto \ -mthumb \ -mabi=aapcs \ -mcpu=cortex-m3 \ -mfloat-abi=soft \ -nostdlib -nostartfiles \ - -DCFG_TUSB_MCU=OPT_MCU_STM32F1 -# mcu driver cause following warnings -#CFLAGS += -Wno-error=unused-parameter +# IAR Flags +IAR_CFLAGS += --cpu cortex-m3 +IAR_ASFLAGS += --cpu cortex-m3 +# ------------------------ # All source paths should be relative to the top level. +# ------------------------ SRC_C += \ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index 2c30daf6f..a0a49d7ec 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -76,9 +76,9 @@ * - ##__VA_ARGS__ is used to deal with 0 paramerter (swallows comma) *------------------------------------------------------------------*/ #if !defined(__CCRX__) -#define TU_ARGS_NUM(...) _TU_NARG(_0, ##__VA_ARGS__,_RSEQ_N()) +#define TU_ARGS_NUM(...) _TU_NARG(_0, ##__VA_ARGS__, _RSEQ_N()) #else -#define TU_ARGS_NUM(...) _TU_NARG(_0, __VA_ARGS__,_RSEQ_N()) +#define TU_ARGS_NUM(...) _TU_NARG(_0, __VA_ARGS__, _RSEQ_N()) #endif #define _TU_NARG(...) _GET_NTH_ARG(__VA_ARGS__) -- cgit v1.3.1 From c3e47c31ccd42b144a8a770ed56b8cdc4c2932cc Mon Sep 17 00:00:00 2001 From: Jonathan Bell Date: Mon, 5 Dec 2022 11:56:42 +0000 Subject: rp2040: export hw_endpoint_start_next_buffer() and hw_endpoint_lock_update() The next change to the driver requires the export of these functions. Leave the lock unimplemented for now. Also move hw_set and hw_clear aliases into the top-level header file. --- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 3 --- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 3 --- src/portable/raspberrypi/rp2040/rp2040_usb.c | 25 +++++++++++-------------- src/portable/raspberrypi/rp2040/rp2040_usb.h | 10 ++++++++++ 4 files changed, 21 insertions(+), 20 deletions(-) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 4952d29b1..33edf0f1e 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -46,9 +46,6 @@ /* Low level controller *------------------------------------------------------------------*/ -#define usb_hw_set hw_set_alias(usb_hw) -#define usb_hw_clear hw_clear_alias(usb_hw) - // Init these in dcd_init static uint8_t *next_buffer_ptr; diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 9e6bdad44..28abd7939 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -56,9 +56,6 @@ static_assert(PICO_USB_HOST_INTERRUPT_ENDPOINTS <= USB_MAX_ENDPOINTS, ""); static struct hw_endpoint ep_pool[1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS]; #define epx (ep_pool[0]) -#define usb_hw_set hw_set_alias(usb_hw) -#define usb_hw_clear hw_clear_alias(usb_hw) - // Flags we set by default in sie_ctrl (we add other bits on top) enum { SIE_CTRL_BASE = USB_SIE_CTRL_SOF_EN_BITS | USB_SIE_CTRL_KEEP_ALIVE_EN_BITS | diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index 5c7645902..77d5f2f8f 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -38,14 +38,11 @@ const char *ep_dir_string[] = { "in", }; -TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_lock_update(__unused struct hw_endpoint * ep, __unused int delta) { - // todo add critsec as necessary to prevent issues between worker and IRQ... - // note that this is perhaps as simple as disabling IRQs because it would make - // sense to have worker and IRQ on same core, however I think using critsec is about equivalent. -} +#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX +volatile uint32_t last_sof = 0; +#endif static void _hw_endpoint_xfer_sync(struct hw_endpoint *ep); -static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep); // if usb hardware is in host mode TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void) @@ -157,7 +154,7 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep, } // Prepare buffer control register value -static void __tusb_irq_path_func(_hw_endpoint_start_next_buffer)(struct hw_endpoint *ep) +void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint *ep) { uint32_t ep_ctrl = *ep->endpoint_control; @@ -201,7 +198,7 @@ static void __tusb_irq_path_func(_hw_endpoint_start_next_buffer)(struct hw_endpo void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len) { - _hw_endpoint_lock_update(ep, 1); + hw_endpoint_lock_update(ep, 1); if ( ep->active ) { @@ -218,8 +215,8 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to ep->active = true; ep->user_buf = buffer; - _hw_endpoint_start_next_buffer(ep); - _hw_endpoint_lock_update(ep, -1); + hw_endpoint_start_next_buffer(ep); + hw_endpoint_lock_update(ep, -1); } // sync endpoint buffer and return transferred bytes @@ -312,7 +309,7 @@ static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep // Returns true if transfer is complete bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep) { - _hw_endpoint_lock_update(ep, 1); + hw_endpoint_lock_update(ep, 1); // Part way through a transfer if (!ep->active) { @@ -329,15 +326,15 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep) pico_trace("Completed transfer of %d bytes on ep %d %s\n", ep->xferred_len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]); // Notify caller we are done so it can notify the tinyusb stack - _hw_endpoint_lock_update(ep, -1); + hw_endpoint_lock_update(ep, -1); return true; } else { - _hw_endpoint_start_next_buffer(ep); + hw_endpoint_start_next_buffer(ep); } - _hw_endpoint_lock_update(ep, -1); + hw_endpoint_lock_update(ep, -1); // More work to do return false; } diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h index b65d32fd4..be1f1e5ec 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.h +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h @@ -26,6 +26,9 @@ #define __tusb_irq_path_func(x) x #endif +#define usb_hw_set hw_set_alias(usb_hw) +#define usb_hw_clear hw_clear_alias(usb_hw) + #define pico_info(...) TU_LOG(2, __VA_ARGS__) #define pico_trace(...) TU_LOG(3, __VA_ARGS__) @@ -79,6 +82,13 @@ void rp2040_usb_init(void); void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len); bool hw_endpoint_xfer_continue(struct hw_endpoint *ep); void hw_endpoint_reset_transfer(struct hw_endpoint *ep); +void hw_endpoint_start_next_buffer(struct hw_endpoint *ep); + +TU_ATTR_ALWAYS_INLINE static inline void hw_endpoint_lock_update(__unused struct hw_endpoint * ep, __unused int delta) { + // todo add critsec as necessary to prevent issues between worker and IRQ... + // note that this is perhaps as simple as disabling IRQs because it would make + // sense to have worker and IRQ on same core, however I think using critsec is about equivalent. +} void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask); -- cgit v1.3.1 From 73b0047efc4cc657a92b356dd9b5046a44277b33 Mon Sep 17 00:00:00 2001 From: Jonathan Bell Date: Thu, 5 Jan 2023 13:36:51 +0000 Subject: rp2040: avoid device-mode state machine hang Don't mark IN buffers as available during the last 200us of a full-speed frame. This avoids a situation seen with the USB2.0 hub on a Raspberry Pi 4 where a late IN token before the next full-speed SOF can cause port babble and a corrupt ACK packet. The nature of the data corruption has a chance to cause device lockup. Use the next SOF to mark delayed buffers as available. This reduces available Bulk IN bandwidth by approximately 20%, and requires that the SOF interrupt is enabled while these transfers are ongoing. Inherit the top-level enable from the corresponding Pico-SDK flag. Applications that will not use the device in a situation where it could be plugged into a Pi 4 or Pi 400 (for example, when directly connected to a commodity hub or other host) can turn off the flag in the SDK. v2: use a field in hw_endpoint to mark pending. v3: Partial rewrite following review comments - Stub functions out if the workaround is not required - Only force-enable SOF while any vulnerable endpoints are active - Respect dcd_sof_enable() functionality - Get rid of all but necessary ifdef hackery - Fix a bug where the "endpoint lock" was used with an uninitialised pointer. --- hw/bsp/rp2040/family.cmake | 1 + src/portable/raspberrypi/rp2040/dcd_rp2040.c | 25 ++++++++++++- src/portable/raspberrypi/rp2040/rp2040_usb.c | 54 ++++++++++++++++++++++++---- src/portable/raspberrypi/rp2040/rp2040_usb.h | 24 ++++++++++++- 4 files changed, 96 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index 5dba9dc39..f83120567 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -116,6 +116,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker) target_compile_definitions(tinyusb_additions INTERFACE PICO_RP2040_USB_DEVICE_ENUMERATION_FIX=1 + PICO_RP2040_USB_DEVICE_UFRAME_FIX=1 ) if(DEFINED LOG) diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 33edf0f1e..35faba628 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -246,13 +246,32 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) { uint32_t const status = usb_hw->ints; uint32_t handled = 0; + bool keep_sof_alive = false; if (status & USB_INTF_DEV_SOF_BITS) { handled |= USB_INTF_DEV_SOF_BITS; +#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX + last_sof = time_us_32(); + + for (uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++) { + struct hw_endpoint *ep = hw_endpoint_get_by_num(i, TUSB_DIR_IN); + hw_endpoint_lock_update(ep, 1); + // Bulk IN endpoint in a transfer? + if (rp2040_ep_needs_sof(ep) && ep->active) + keep_sof_alive = true; + // Deferred enable? + if (ep->pending) { + hw_endpoint_start_next_buffer(ep); + ep->pending = 0; + } + hw_endpoint_lock_update(ep, -1); + } +#endif // disable SOF interrupt if it is used for RESUME in remote wakeup - if (!_sof_enable) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS; + if (!keep_sof_alive && !_sof_enable) + usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS; dcd_event_sof(0, usb_hw->sof_rd & USB_SOF_RD_BITS, true); } @@ -449,7 +468,11 @@ void dcd_sof_enable(uint8_t rhport, bool en) usb_hw_set->inte = USB_INTS_DEV_SOF_BITS; }else { + // Don't clear immediately if the SOF workaround is in use. + // The SOF handler will conditionally disable the interrupt. +#if !TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS; +#endif } } diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index 77d5f2f8f..6a9f162a5 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -38,10 +38,6 @@ const char *ep_dir_string[] = { "in", }; -#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX -volatile uint32_t last_sof = 0; -#endif - static void _hw_endpoint_xfer_sync(struct hw_endpoint *ep); // if usb hardware is in host mode @@ -54,6 +50,41 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void) // //--------------------------------------------------------------------+ +#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX +volatile uint32_t last_sof = 0; + +bool rp2040_critical_frame_period(struct hw_endpoint *ep) +{ + uint32_t delta; + + if (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) + return false; + + if (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_OUT || + ep->transfer_type == TUSB_XFER_INTERRUPT || + ep->transfer_type == TUSB_XFER_ISOCHRONOUS) + return false; + + /* Avoid the last 200us (uframe 6.5-7) of a frame, up to the EOF2 point. + * The device state machine cannot recover from receiving an incorrect PID + * when it is expecting an ACK. + */ + delta = time_us_32() - last_sof; + if (delta < 800 || delta > 998) { + return false; + } + TU_LOG(3, "Avoiding sof %u now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, now, last_sof); + return true; +} + +bool rp2040_ep_needs_sof(struct hw_endpoint *ep) { + if (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN && + ep->transfer_type == TUSB_XFER_BULK) + return true; + return false; +} +#endif + void rp2040_usb_init(void) { // Reset usb controller @@ -215,7 +246,14 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to ep->active = true; ep->user_buf = buffer; - hw_endpoint_start_next_buffer(ep); + if (rp2040_ep_needs_sof(ep)) + usb_hw_set->inte = USB_INTS_DEV_SOF_BITS; + + if(!rp2040_critical_frame_period(ep)) { + hw_endpoint_start_next_buffer(ep); + } else { + ep->pending = 1; + } hw_endpoint_lock_update(ep, -1); } @@ -331,7 +369,11 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep) } else { - hw_endpoint_start_next_buffer(ep); + if(!rp2040_critical_frame_period(ep)) { + hw_endpoint_start_next_buffer(ep); + } else { + ep->pending = 1; + } } hw_endpoint_lock_update(ep, -1); diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h index be1f1e5ec..717ec3514 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.h +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h @@ -11,11 +11,21 @@ #include "hardware/structs/usb.h" #include "hardware/irq.h" #include "hardware/resets.h" +#include "hardware/timer.h" #if defined(PICO_RP2040_USB_DEVICE_ENUMERATION_FIX) && !defined(TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX) #define TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX PICO_RP2040_USB_DEVICE_ENUMERATION_FIX #endif +#if defined(PICO_RP2040_USB_DEVICE_UFRAME_FIX) && !defined(TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX) +#define TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX PICO_RP2040_USB_DEVICE_UFRAME_FIX +#endif + +#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX +#undef PICO_RP2040_USB_FAST_IRQ +#define PICO_RP2040_USB_FAST_IRQ 1 +#endif + #ifndef PICO_RP2040_USB_FAST_IRQ #define PICO_RP2040_USB_FAST_IRQ 0 #endif @@ -67,7 +77,9 @@ typedef struct hw_endpoint // Interrupt, bulk, etc uint8_t transfer_type; - + + // Transfer scheduled but not active + uint8_t pending; #if CFG_TUH_ENABLED // Only needed for host uint8_t dev_addr; @@ -77,6 +89,16 @@ typedef struct hw_endpoint #endif } hw_endpoint_t; +#if !TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX +#define rp2040_critical_frame_period(x) false +#define rp2040_ep_needs_sof(x) false +#else +extern volatile uint32_t last_sof; + +bool rp2040_critical_frame_period(struct hw_endpoint *ep); +bool rp2040_ep_needs_sof(struct hw_endpoint *ep); +#endif + void rp2040_usb_init(void); void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len); -- cgit v1.3.1 From 0d2078d295667ef985675c398db7fd6a893be895 Mon Sep 17 00:00:00 2001 From: Jonathan Bell Date: Tue, 24 Jan 2023 12:02:32 +0000 Subject: rp2040: shuffle hw_endpoint members Ordering by element size prevents alignment holes, and as a consequence the host mode version of the struct is the same size as device, as pad bytes at the end are used instead. --- src/portable/raspberrypi/rp2040/rp2040_usb.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h index 717ec3514..e7fee3e3a 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.h +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h @@ -51,7 +51,7 @@ typedef struct hw_endpoint // Transfer direction (i.e. IN is rx for host but tx for device) // allows us to common up transfer functions bool rx; - + uint8_t ep_addr; uint8_t next_pid; @@ -64,17 +64,19 @@ typedef struct hw_endpoint // Buffer pointer in usb dpram uint8_t *hw_data_buf; + // User buffer in main memory + uint8_t *user_buf; + // Current transfer information - bool active; uint16_t remaining_len; uint16_t xferred_len; - // User buffer in main memory - uint8_t *user_buf; - // Data needed from EP descriptor uint16_t wMaxPacketSize; + // Endpoint is in use + bool active; + // Interrupt, bulk, etc uint8_t transfer_type; -- cgit v1.3.1 From 6dd40603f92a04d695b78a3ee6c0276525960aef Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 30 Jan 2023 11:46:52 +0700 Subject: fix typo --- src/portable/bridgetek/ft9xx/dcd_ft9xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c index f4c9b2b27..efca5bdcb 100644 --- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c +++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c @@ -1023,7 +1023,7 @@ void dcd_int_handler(uint8_t rhport) USBD_EP_SR_REG(USBD_EP_0) = MASK_USBD_EP0SR_STALL; } - // Host has sent a SETUP packet. Recieve this into the SETUP packet store. + // Host has sent a SETUP packet. Receive this into the SETUP packet store. _ft9xx_dusb_out(USBD_EP_0, (uint8_t *)_ft9xx_setup_packet, sizeof(USB_device_request)); // Send the packet to tinyusb. -- cgit v1.3.1 From cc1878447990aa01a99351cafe8bd899bd37b4e0 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 30 Jan 2023 16:42:56 +0700 Subject: hardcoded configPRIO_BITS for IAR build to pass CI --- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 23 +++++++++++++++------- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 23 +++++++++++++++------- src/tusb_option.h | 6 +++--- 3 files changed, 35 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index efd527ed2..9bef9bbbf 100644 --- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -42,8 +42,8 @@ * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ -// skip if is compiled with assembler -#if !defined(__ASSEMBLER__) && !defined(__IASMARM__) +// skip if included from IAR assembler +#ifndef __IASMARM__ // Include MCU header #include "bsp/board_mcu.h" @@ -149,10 +149,10 @@ #ifdef __RX__ /* Renesas RX series */ -#define vSoftwareInterruptISR INT_Excep_ICU_SWINT -#define vTickISR INT_Excep_CMT0_CMI0 -#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) -#define configKERNEL_INTERRUPT_PRIORITY 1 +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 #define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 #else @@ -168,10 +168,19 @@ #if defined(__NVIC_PRIO_BITS) // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h #define configPRIO_BITS __NVIC_PRIO_BITS + #elif defined(__ECLIC_INTCTLBITS) // RISC-V Bumblebee core from nuclei #define configPRIO_BITS __ECLIC_INTCTLBITS -#elif !defined(__ASSEMBLER__) && !defined(__IASMARM__) + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else #error "FreeRTOS configPRIO_BITS to be defined" #endif diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index efd527ed2..9bef9bbbf 100644 --- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -42,8 +42,8 @@ * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ -// skip if is compiled with assembler -#if !defined(__ASSEMBLER__) && !defined(__IASMARM__) +// skip if included from IAR assembler +#ifndef __IASMARM__ // Include MCU header #include "bsp/board_mcu.h" @@ -149,10 +149,10 @@ #ifdef __RX__ /* Renesas RX series */ -#define vSoftwareInterruptISR INT_Excep_ICU_SWINT -#define vTickISR INT_Excep_CMT0_CMI0 -#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) -#define configKERNEL_INTERRUPT_PRIORITY 1 +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 #define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 #else @@ -168,10 +168,19 @@ #if defined(__NVIC_PRIO_BITS) // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h #define configPRIO_BITS __NVIC_PRIO_BITS + #elif defined(__ECLIC_INTCTLBITS) // RISC-V Bumblebee core from nuclei #define configPRIO_BITS __ECLIC_INTCTLBITS -#elif !defined(__ASSEMBLER__) && !defined(__IASMARM__) + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else #error "FreeRTOS configPRIO_BITS to be defined" #endif diff --git a/src/tusb_option.h b/src/tusb_option.h index 67377b7ec..cf5b21c9c 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -27,9 +27,6 @@ #ifndef _TUSB_OPTION_H_ #define _TUSB_OPTION_H_ -// To avoid GCC compiler warnings when -pedantic option is used (strict ISO C) -typedef int make_iso_compilers_happy; - #include "common/tusb_compiler.h" #define TUSB_VERSION_MAJOR 0 @@ -435,6 +432,9 @@ typedef int make_iso_compilers_happy; #error Control Endpoint Max Packet Size cannot be larger than 64 #endif +// To avoid GCC compiler warnings when -pedantic option is used (strict ISO C) +typedef int make_iso_compilers_happy; + #endif /* _TUSB_OPTION_H_ */ /** @} */ -- cgit v1.3.1 From 0cce42fcc672cb3e0d2fe16c20b46aab9d8f94d5 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 31 Jan 2023 11:38:15 +0700 Subject: minor clean up --- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 19 ++++++++++++------- src/portable/raspberrypi/rp2040/rp2040_usb.c | 26 +++++++++++++++++--------- src/portable/raspberrypi/rp2040/rp2040_usb.h | 2 ++ 3 files changed, 31 insertions(+), 16 deletions(-) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 35faba628..d5a105a29 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -246,32 +246,37 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) { uint32_t const status = usb_hw->ints; uint32_t handled = 0; - bool keep_sof_alive = false; if (status & USB_INTF_DEV_SOF_BITS) { + bool keep_sof_alive = false; + handled |= USB_INTF_DEV_SOF_BITS; #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX last_sof = time_us_32(); - for (uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++) { + for (uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++) + { struct hw_endpoint *ep = hw_endpoint_get_by_num(i, TUSB_DIR_IN); hw_endpoint_lock_update(ep, 1); + // Bulk IN endpoint in a transfer? - if (rp2040_ep_needs_sof(ep) && ep->active) - keep_sof_alive = true; + if (rp2040_ep_needs_sof(ep) && ep->active) keep_sof_alive = true; + // Deferred enable? - if (ep->pending) { + if (ep->pending) + { hw_endpoint_start_next_buffer(ep); ep->pending = 0; } + hw_endpoint_lock_update(ep, -1); } #endif + // disable SOF interrupt if it is used for RESUME in remote wakeup - if (!keep_sof_alive && !_sof_enable) - usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS; + if (!keep_sof_alive && !_sof_enable) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS; dcd_event_sof(0, usb_hw->sof_rd & USB_SOF_RD_BITS, true); } diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index 6a9f162a5..b7790e0c1 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -57,13 +57,14 @@ bool rp2040_critical_frame_period(struct hw_endpoint *ep) { uint32_t delta; - if (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) - return false; + if (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) return false; if (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_OUT || ep->transfer_type == TUSB_XFER_INTERRUPT || ep->transfer_type == TUSB_XFER_ISOCHRONOUS) + { return false; + } /* Avoid the last 200us (uframe 6.5-7) of a frame, up to the EOF2 point. * The device state machine cannot recover from receiving an incorrect PID @@ -78,10 +79,8 @@ bool rp2040_critical_frame_period(struct hw_endpoint *ep) } bool rp2040_ep_needs_sof(struct hw_endpoint *ep) { - if (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN && - ep->transfer_type == TUSB_XFER_BULK) - return true; - return false; + return (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN && + ep->transfer_type == TUSB_XFER_BULK); } #endif @@ -115,12 +114,15 @@ void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep) ep->user_buf = 0; } -void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask) { +void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask) +{ uint32_t value = 0; + if ( and_mask ) { value = *ep->buffer_control & and_mask; } + if ( or_mask ) { value |= or_mask; @@ -146,6 +148,7 @@ void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoi #endif } } + *ep->buffer_control = value; } @@ -247,13 +250,18 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to ep->user_buf = buffer; if (rp2040_ep_needs_sof(ep)) + { usb_hw_set->inte = USB_INTS_DEV_SOF_BITS; + } - if(!rp2040_critical_frame_period(ep)) { + if(!rp2040_critical_frame_period(ep)) + { hw_endpoint_start_next_buffer(ep); - } else { + } else + { ep->pending = 1; } + hw_endpoint_lock_update(ep, -1); } diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h index e7fee3e3a..d41abfee0 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.h +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h @@ -82,6 +82,7 @@ typedef struct hw_endpoint // Transfer scheduled but not active uint8_t pending; + #if CFG_TUH_ENABLED // Only needed for host uint8_t dev_addr; @@ -89,6 +90,7 @@ typedef struct hw_endpoint // If interrupt endpoint uint8_t interrupt_num; #endif + } hw_endpoint_t; #if !TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX -- cgit v1.3.1 From 19b6cbc616e65dcb2ecdcac66f873ce416a4bf25 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 31 Jan 2023 14:48:11 +0700 Subject: add e15 prefix or walkaround related functions, also minor refactor --- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 177 ++++++++++++++------------- src/portable/raspberrypi/rp2040/rp2040_usb.c | 55 +++++---- src/portable/raspberrypi/rp2040/rp2040_usb.h | 10 +- 3 files changed, 124 insertions(+), 118 deletions(-) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index d5a105a29..ab1185102 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -244,128 +244,133 @@ static void __tusb_irq_path_func(reset_non_control_endpoints)(void) static void __tusb_irq_path_func(dcd_rp2040_irq)(void) { - uint32_t const status = usb_hw->ints; - uint32_t handled = 0; + uint32_t const status = usb_hw->ints; + uint32_t handled = 0; - if (status & USB_INTF_DEV_SOF_BITS) - { - bool keep_sof_alive = false; + if ( status & USB_INTF_DEV_SOF_BITS ) + { + bool keep_sof_alive = false; - handled |= USB_INTF_DEV_SOF_BITS; + handled |= USB_INTF_DEV_SOF_BITS; #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX - last_sof = time_us_32(); + // Errata 15 Walkaround for Device Bulk-In endpoint + e15_last_sof = time_us_32(); + + for ( uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++ ) + { + struct hw_endpoint * ep = hw_endpoint_get_by_num(i, TUSB_DIR_IN); - for (uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++) + // Active Bulk IN endpoint requires SOF + if ( (ep->transfer_type == TUSB_XFER_BULK) && ep->active ) { - struct hw_endpoint *ep = hw_endpoint_get_by_num(i, TUSB_DIR_IN); - hw_endpoint_lock_update(ep, 1); + keep_sof_alive = true; - // Bulk IN endpoint in a transfer? - if (rp2040_ep_needs_sof(ep) && ep->active) keep_sof_alive = true; + hw_endpoint_lock_update(ep, 1); // Deferred enable? - if (ep->pending) + if ( ep->pending ) { - hw_endpoint_start_next_buffer(ep); ep->pending = 0; + hw_endpoint_start_next_buffer(ep); } hw_endpoint_lock_update(ep, -1); } + } #endif - // disable SOF interrupt if it is used for RESUME in remote wakeup - if (!keep_sof_alive && !_sof_enable) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS; + // disable SOF interrupt if it is used for RESUME in remote wakeup + if ( !keep_sof_alive && !_sof_enable ) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS; - dcd_event_sof(0, usb_hw->sof_rd & USB_SOF_RD_BITS, true); - } + dcd_event_sof(0, usb_hw->sof_rd & USB_SOF_RD_BITS, true); + } - // xfer events are handled before setup req. So if a transfer completes immediately - // before closing the EP, the events will be delivered in same order. - if (status & USB_INTS_BUFF_STATUS_BITS) - { - handled |= USB_INTS_BUFF_STATUS_BITS; - hw_handle_buff_status(); - } + // xfer events are handled before setup req. So if a transfer completes immediately + // before closing the EP, the events will be delivered in same order. + if ( status & USB_INTS_BUFF_STATUS_BITS ) + { + handled |= USB_INTS_BUFF_STATUS_BITS; + hw_handle_buff_status(); + } - if (status & USB_INTS_SETUP_REQ_BITS) - { - handled |= USB_INTS_SETUP_REQ_BITS; - uint8_t const *setup = (uint8_t const *)&usb_dpram->setup_packet; + if ( status & USB_INTS_SETUP_REQ_BITS ) + { + handled |= USB_INTS_SETUP_REQ_BITS; + uint8_t const * setup = (uint8_t const*) &usb_dpram->setup_packet; - // reset pid to both 1 (data and ack) - reset_ep0_pid(); + // reset pid to both 1 (data and ack) + reset_ep0_pid(); - // Pass setup packet to tiny usb - dcd_event_setup_received(0, setup, true); - usb_hw_clear->sie_status = USB_SIE_STATUS_SETUP_REC_BITS; - } + // Pass setup packet to tiny usb + dcd_event_setup_received(0, setup, true); + usb_hw_clear->sie_status = USB_SIE_STATUS_SETUP_REC_BITS; + } #if FORCE_VBUS_DETECT == 0 - // Since we force VBUS detect On, device will always think it is connected and - // couldn't distinguish between disconnect and suspend - if (status & USB_INTS_DEV_CONN_DIS_BITS) - { - handled |= USB_INTS_DEV_CONN_DIS_BITS; - - if ( usb_hw->sie_status & USB_SIE_STATUS_CONNECTED_BITS ) - { - // Connected: nothing to do - }else - { - // Disconnected - dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true); - } + // Since we force VBUS detect On, device will always think it is connected and + // couldn't distinguish between disconnect and suspend + if (status & USB_INTS_DEV_CONN_DIS_BITS) + { + handled |= USB_INTS_DEV_CONN_DIS_BITS; - usb_hw_clear->sie_status = USB_SIE_STATUS_CONNECTED_BITS; + if ( usb_hw->sie_status & USB_SIE_STATUS_CONNECTED_BITS ) + { + // Connected: nothing to do + }else + { + // Disconnected + dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true); } + + usb_hw_clear->sie_status = USB_SIE_STATUS_CONNECTED_BITS; + } #endif - // SE0 for 2.5 us or more (will last at least 10ms) - if (status & USB_INTS_BUS_RESET_BITS) - { - pico_trace("BUS RESET\n"); + // SE0 for 2.5 us or more (will last at least 10ms) + if ( status & USB_INTS_BUS_RESET_BITS ) + { + pico_trace("BUS RESET\n"); - handled |= USB_INTS_BUS_RESET_BITS; + handled |= USB_INTS_BUS_RESET_BITS; - usb_hw->dev_addr_ctrl = 0; - reset_non_control_endpoints(); - dcd_event_bus_reset(0, TUSB_SPEED_FULL, true); - usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS; + usb_hw->dev_addr_ctrl = 0; + reset_non_control_endpoints(); + dcd_event_bus_reset(0, TUSB_SPEED_FULL, true); + usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS; #if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX - // Only run enumeration walk-around if pull up is enabled - if ( usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS ) rp2040_usb_device_enumeration_fix(); + // Only run enumeration walk-around if pull up is enabled + if ( usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS ) rp2040_usb_device_enumeration_fix(); #endif - } + } - /* Note from pico datasheet 4.1.2.6.4 (v1.2) - * If you enable the suspend interrupt, it is likely you will see a suspend interrupt when - * the device is first connected but the bus is idle. The bus can be idle for a few ms before - * the host begins sending start of frame packets. You will also see a suspend interrupt - * when the device is disconnected if you do not have a VBUS detect circuit connected. This is - * because without VBUS detection, it is impossible to tell the difference between - * being disconnected and suspended. - */ - if (status & USB_INTS_DEV_SUSPEND_BITS) - { - handled |= USB_INTS_DEV_SUSPEND_BITS; - dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); - usb_hw_clear->sie_status = USB_SIE_STATUS_SUSPENDED_BITS; - } + /* Note from pico datasheet 4.1.2.6.4 (v1.2) + * If you enable the suspend interrupt, it is likely you will see a suspend interrupt when + * the device is first connected but the bus is idle. The bus can be idle for a few ms before + * the host begins sending start of frame packets. You will also see a suspend interrupt + * when the device is disconnected if you do not have a VBUS detect circuit connected. This is + * because without VBUS detection, it is impossible to tell the difference between + * being disconnected and suspended. + */ + if ( status & USB_INTS_DEV_SUSPEND_BITS ) + { + handled |= USB_INTS_DEV_SUSPEND_BITS; + dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); + usb_hw_clear->sie_status = USB_SIE_STATUS_SUSPENDED_BITS; + } - if (status & USB_INTS_DEV_RESUME_FROM_HOST_BITS) - { - handled |= USB_INTS_DEV_RESUME_FROM_HOST_BITS; - dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); - usb_hw_clear->sie_status = USB_SIE_STATUS_RESUME_BITS; - } + if ( status & USB_INTS_DEV_RESUME_FROM_HOST_BITS ) + { + handled |= USB_INTS_DEV_RESUME_FROM_HOST_BITS; + dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); + usb_hw_clear->sie_status = USB_SIE_STATUS_RESUME_BITS; + } - if (status ^ handled) - { - panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled)); - } + if ( status ^ handled ) + { + panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled)); + } } #define USB_INTS_ERROR_BITS ( \ diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index b7790e0c1..d25e6c8fb 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -51,37 +51,41 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void) //--------------------------------------------------------------------+ #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX -volatile uint32_t last_sof = 0; +// Errata 15 Walkaround for Device Bulk-In endpoint to avoid schedule an transfer +// within last 20% of an USB frame. -bool rp2040_critical_frame_period(struct hw_endpoint *ep) -{ - uint32_t delta; +volatile uint32_t e15_last_sof = 0; - if (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) return false; +// check if Errata 15 walkround is needed for this endpoint +static bool __tusb_irq_path_func(e15_is_bulkin_ep) (struct hw_endpoint *ep) +{ + return (!is_host_mode() && tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN && + ep->transfer_type == TUSB_XFER_BULK); +} - if (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_OUT || - ep->transfer_type == TUSB_XFER_INTERRUPT || - ep->transfer_type == TUSB_XFER_ISOCHRONOUS) - { - return false; - } +// check if we need to apply Errata 15 workaround: ie.g +// Enpoint is BULK IN and is currently in critical frame period i.e 20% of last usb frame +static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoint *ep) +{ + TU_VERIFY(e15_is_bulkin_ep(ep)); /* Avoid the last 200us (uframe 6.5-7) of a frame, up to the EOF2 point. * The device state machine cannot recover from receiving an incorrect PID * when it is expecting an ACK. */ - delta = time_us_32() - last_sof; + uint32_t delta = time_us_32() - e15_last_sof; if (delta < 800 || delta > 998) { return false; } - TU_LOG(3, "Avoiding sof %u now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, now, last_sof); + TU_LOG(3, "Avoiding sof %u now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof); return true; } -bool rp2040_ep_needs_sof(struct hw_endpoint *ep) { - return (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN && - ep->transfer_type == TUSB_XFER_BULK); -} +#else + +#define e15_is_bulkin_ep(x) false +#define e15_is_critical_frame_period(x) false + #endif void rp2040_usb_init(void) @@ -249,17 +253,17 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to ep->active = true; ep->user_buf = buffer; - if (rp2040_ep_needs_sof(ep)) + if ( e15_is_bulkin_ep(ep) ) { usb_hw_set->inte = USB_INTS_DEV_SOF_BITS; } - if(!rp2040_critical_frame_period(ep)) + if ( e15_is_critical_frame_period(ep) ) { - hw_endpoint_start_next_buffer(ep); + ep->pending = 1; } else { - ep->pending = 1; + hw_endpoint_start_next_buffer(ep); } hw_endpoint_lock_update(ep, -1); @@ -356,6 +360,7 @@ static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep) { hw_endpoint_lock_update(ep, 1); + // Part way through a transfer if (!ep->active) { @@ -377,10 +382,12 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep) } else { - if(!rp2040_critical_frame_period(ep)) { - hw_endpoint_start_next_buffer(ep); - } else { + if ( e15_is_critical_frame_period(ep) ) + { ep->pending = 1; + } else + { + hw_endpoint_start_next_buffer(ep); } } diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h index d41abfee0..a06407f23 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.h +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h @@ -93,14 +93,8 @@ typedef struct hw_endpoint } hw_endpoint_t; -#if !TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX -#define rp2040_critical_frame_period(x) false -#define rp2040_ep_needs_sof(x) false -#else -extern volatile uint32_t last_sof; - -bool rp2040_critical_frame_period(struct hw_endpoint *ep); -bool rp2040_ep_needs_sof(struct hw_endpoint *ep); +#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX +extern volatile uint32_t e15_last_sof; #endif void rp2040_usb_init(void); -- cgit v1.3.1 From 6759721e9aceb52f176f3068438c103739c29768 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 31 Jan 2023 17:37:14 +0700 Subject: move errata to end of c file --- src/portable/raspberrypi/rp2040/rp2040_usb.c | 104 +++++++++++++++++---------- 1 file changed, 65 insertions(+), 39 deletions(-) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index d25e6c8fb..6f9cf34be 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -32,6 +32,10 @@ #include #include "rp2040_usb.h" +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF PROTOTYPE +//--------------------------------------------------------------------+ + // Direction strings for debug const char *ep_dir_string[] = { "out", @@ -40,6 +44,14 @@ const char *ep_dir_string[] = { static void _hw_endpoint_xfer_sync(struct hw_endpoint *ep); +#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX + static bool e15_is_bulkin_ep(struct hw_endpoint *ep); + static bool e15_is_critical_frame_period(struct hw_endpoint *ep); +#else + #define e15_is_bulkin_ep(x) (false) + #define e15_is_critical_frame_period(x) (false) +#endif + // if usb hardware is in host mode TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void) { @@ -47,47 +59,9 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void) } //--------------------------------------------------------------------+ -// +// Implementation //--------------------------------------------------------------------+ -#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX -// Errata 15 Walkaround for Device Bulk-In endpoint to avoid schedule an transfer -// within last 20% of an USB frame. - -volatile uint32_t e15_last_sof = 0; - -// check if Errata 15 walkround is needed for this endpoint -static bool __tusb_irq_path_func(e15_is_bulkin_ep) (struct hw_endpoint *ep) -{ - return (!is_host_mode() && tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN && - ep->transfer_type == TUSB_XFER_BULK); -} - -// check if we need to apply Errata 15 workaround: ie.g -// Enpoint is BULK IN and is currently in critical frame period i.e 20% of last usb frame -static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoint *ep) -{ - TU_VERIFY(e15_is_bulkin_ep(ep)); - - /* Avoid the last 200us (uframe 6.5-7) of a frame, up to the EOF2 point. - * The device state machine cannot recover from receiving an incorrect PID - * when it is expecting an ACK. - */ - uint32_t delta = time_us_32() - e15_last_sof; - if (delta < 800 || delta > 998) { - return false; - } - TU_LOG(3, "Avoiding sof %u now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof); - return true; -} - -#else - -#define e15_is_bulkin_ep(x) false -#define e15_is_critical_frame_period(x) false - -#endif - void rp2040_usb_init(void) { // Reset usb controller @@ -396,4 +370,56 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep) return false; } +//--------------------------------------------------------------------+ +// Errata 15 +//--------------------------------------------------------------------+ + +#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX + +/* Don't mark IN buffers as available during the last 200us of a full-speed + frame. This avoids a situation seen with the USB2.0 hub on a Raspberry + Pi 4 where a late IN token before the next full-speed SOF can cause port + babble and a corrupt ACK packet. The nature of the data corruption has a + chance to cause device lockup. + + Use the next SOF to mark delayed buffers as available. This reduces + available Bulk IN bandwidth by approximately 20%, and requires that the + SOF interrupt is enabled while these transfers are ongoing. + + Inherit the top-level enable from the corresponding Pico-SDK flag. + Applications that will not use the device in a situation where it could + be plugged into a Pi 4 or Pi 400 (for example, when directly connected + to a commodity hub or other host) can turn off the flag in the SDK. +*/ + +volatile uint32_t e15_last_sof = 0; + +// check if Errata 15 is needed for this endpoint i.e device bulk-in +static bool __tusb_irq_path_func(e15_is_bulkin_ep) (struct hw_endpoint *ep) +{ + return (!is_host_mode() && tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN && + ep->transfer_type == TUSB_XFER_BULK); +} + +// check if we need to apply Errata 15 walk-around : i.e +// Endpoint is BULK IN and is currently in critical frame period i.e 20% of last usb frame +static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoint *ep) +{ + TU_VERIFY(e15_is_bulkin_ep(ep)); + + /* Avoid the last 200us (uframe 6.5-7) of a frame, up to the EOF2 point. + * The device state machine cannot recover from receiving an incorrect PID + * when it is expecting an ACK. + */ + uint32_t delta = time_us_32() - e15_last_sof; + if (delta < 800 || delta > 998) { + return false; + } + TU_LOG(3, "Avoiding sof %u now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof); + return true; +} + +#endif + + #endif -- cgit v1.3.1 From 95403ed9ac88077062c03525d44818b10be1cf6f Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 31 Jan 2023 18:40:07 +0700 Subject: fix host issue when mounting an CDC device without IAD --- src/host/usbh.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 5ac9e9cca..12b0ed203 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1522,7 +1522,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur #if CFG_TUH_MIDI // MIDI has 2 interfaces (Audio Control v1 + MIDIStreaming) but does not have IAD - // manually increase the associated count + // manually force associated count = 2 if (1 == assoc_itf_count && TUSB_CLASS_AUDIO == desc_itf->bInterfaceClass && AUDIO_SUBCLASS_CONTROL == desc_itf->bInterfaceSubClass && @@ -1532,6 +1532,17 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur } #endif +#if CFG_TUH_CDC + // Some legacy CDC device does not use IAD but rather use device class as hint to combine 2 interfaces + // manually force associated count = 2 + if (1 == assoc_itf_count && + TUSB_CLASS_CDC == desc_itf->bInterfaceClass && + CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == desc_itf->bInterfaceSubClass) + { + assoc_itf_count = 2; + } +#endif + uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, (uint16_t) (desc_end-p_desc)); TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t)); -- cgit v1.3.1 From ddb061f639956781ac5644e5c9ec2371c534ea57 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 31 Jan 2023 19:03:31 +0700 Subject: fix typos --- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 4 ++-- src/portable/raspberrypi/rp2040/rp2040_usb.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index ab1185102..b5fa90c92 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -254,7 +254,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) handled |= USB_INTF_DEV_SOF_BITS; #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX - // Errata 15 Walkaround for Device Bulk-In endpoint + // Errata 15 workaround for Device Bulk-In endpoint e15_last_sof = time_us_32(); for ( uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++ ) @@ -340,7 +340,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS; #if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX - // Only run enumeration walk-around if pull up is enabled + // Only run enumeration workaround if pull up is enabled if ( usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS ) rp2040_usb_device_enumeration_fix(); #endif } diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index 6f9cf34be..df05697fe 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -401,7 +401,7 @@ static bool __tusb_irq_path_func(e15_is_bulkin_ep) (struct hw_endpoint *ep) ep->transfer_type == TUSB_XFER_BULK); } -// check if we need to apply Errata 15 walk-around : i.e +// check if we need to apply Errata 15 workaround : i.e // Endpoint is BULK IN and is currently in critical frame period i.e 20% of last usb frame static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoint *ep) { -- cgit v1.3.1 From 3422e0568431079715acabc63f1899578ef6240d Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 4 Feb 2023 11:43:23 +0700 Subject: change length in tud_hid_report_complete_cb() from uint8 to uint16 --- examples/device/hid_boot_interface/src/main.c | 2 +- examples/device/hid_composite/src/main.c | 2 +- examples/device/hid_composite_freertos/src/main.c | 2 +- src/class/hid/hid_device.c | 2 +- src/class/hid/hid_device.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c index ef072019c..b13428041 100644 --- a/examples/device/hid_boot_interface/src/main.c +++ b/examples/device/hid_boot_interface/src/main.c @@ -181,7 +181,7 @@ void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol) // Invoked when sent REPORT successfully to host // Application can use this to send the next report // Note: For composite reports, report[0] is report ID -void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len) +void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len) { (void) instance; (void) report; diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c index f7d76cfc7..05315f266 100644 --- a/examples/device/hid_composite/src/main.c +++ b/examples/device/hid_composite/src/main.c @@ -225,7 +225,7 @@ void hid_task(void) // Invoked when sent REPORT successfully to host // Application can use this to send the next report // Note: For composite reports, report[0] is report ID -void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len) +void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len) { (void) instance; (void) len; diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c index fb0d69258..7c9619c4b 100644 --- a/examples/device/hid_composite_freertos/src/main.c +++ b/examples/device/hid_composite_freertos/src/main.c @@ -302,7 +302,7 @@ void hid_task(void* param) // Invoked when sent REPORT successfully to host // Application can use this to send the next report // Note: For composite reports, report[0] is report ID -void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len) +void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len) { (void) instance; (void) len; diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c index 8077e4deb..2d46d760f 100644 --- a/src/class/hid/hid_device.c +++ b/src/class/hid/hid_device.c @@ -403,7 +403,7 @@ bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_ { if (tud_hid_report_complete_cb) { - tud_hid_report_complete_cb(instance, p_hid->epin_buf, (/*uint16_t*/ uint8_t) xferred_bytes); + tud_hid_report_complete_cb(instance, p_hid->epin_buf, (uint16_t) xferred_bytes); } } // Received report diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h index eeef6d3ba..17b24def1 100644 --- a/src/class/hid/hid_device.h +++ b/src/class/hid/hid_device.h @@ -116,7 +116,7 @@ TU_ATTR_WEAK bool tud_hid_set_idle_cb(uint8_t instance, uint8_t idle_rate); // Invoked when sent REPORT successfully to host // Application can use this to send the next report // Note: For composite reports, report[0] is report ID -TU_ATTR_WEAK void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len ); +TU_ATTR_WEAK void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len); //--------------------------------------------------------------------+ -- cgit v1.3.1 From 7e48da5b44e2f30095a9de42c43381b9194cfd54 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 10 Feb 2023 12:47:33 +0700 Subject: update version to 0.15.0 add changelog --- docs/info/changelog.rst | 82 ++++++++++++++++++++++++++++++++++++++++++++++++- repository.yml | 7 ++--- src/tusb_option.h | 2 +- tools/make_release.py | 40 ++++++++++++++++++++++++ 4 files changed, 125 insertions(+), 6 deletions(-) create mode 100644 tools/make_release.py (limited to 'src') diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst index bbd182866..129538f3d 100644 --- a/docs/info/changelog.rst +++ b/docs/info/changelog.rst @@ -2,6 +2,78 @@ Changelog ********* +0.15.0 +====== + +- Add codespell to detect typo +- Add support for fuzzing and bagde for oss-fuzz +- [osal] + + - Allow the use of non-static allocation for FreeRTOS + - Fix FreeRTOS wrong task switch in some cases + +- Fix tu_fifo memory overflown when repeatedly write to overwritable fifo (accumulated more than 2 depths) +- Better support for IAR (ARM) with ci build check for stm32 mcus. +- Fix Windows build for some mingw gnu make situations + +Controller Driver (DCD & HCD) +----------------------------- + +- Add new port support (WIP) for WCH CH32V307 USB Highspeed +- Add new port support (WIP) for PIC32MM/MX & PIC24 + +- [nRF] + + - Fix endpoint internal state when closed + - Fix reception of large ISO packets + +- [rp2040] + + - [dcd] Implement workaround for Errata 15. This enable SOF when bulk-in endpoint is in use and reduce its bandwidth to only 80% + - [hcd] Fix shared irq slots filling up when hcd_init() is called multiple times + - [hcd] Support host bulk endpoint using hw "interrupt" endpoint. Note speed limit is 64KB/s + +- [samd][dcd] Add support for ISO endpoint +- [dwc2][dcd] Add support for stm32u5xx +- [esp32sx] Fix Isochronous transfers only transmitted on even frame +- [lpc_ip3511][dcd] Add isochronous support and fix endpoint accidental write +- [ft90x] Improve and enhance support for FT9xx MCU, tested with more examples + +Device Stack +------------ + +- [Video] + + - Add support for MJPEG + - Fix probe on macOS + +- [MIDI] + + - Support port name strings + - fix MS Header wTotalLength computation + +- [HID] + + - Add FIDO descriptor template + - change length in tud_hid_report_complete_cb() from uint8 to uint16 + +- [CDC] + + - Fix autoflush for FIFO < MPS + - Fix tx fifo memory overflown when DTR is not set and tud_cdc_write() is called repeatedly with large enough data + +- [USBTMC] Fix packet size with highspeed + +Host Stack +---------- + +- Retry a few times with transfers in enumeration since device can be unstable when starting up +- [MSC] Rework host masstorage API. Add new **host/msc_file_explorer** example +- [CDC] + + - Add suport for host cdc + - Fix host cdc with device without IAD e.g Arduino Due + 0.14.0 ====== @@ -9,7 +81,8 @@ Changelog - Add timeout to osal_queue_receive() - Add tud_task_ext(timeout, in_isr) as generic version of tud_task(). Same as tuh_task_ext(), tuh_task() - Enable more warnings -Wnull-dereference -Wuninitialized -Wunused -Wredundant-decls -Wconversion -- Add new examples +- Add new examples + - host/bare_api to demonstrate generic (app-level) enumeration and endpoint transfer - dual/host_hid_to_device_cdc to run both device and host stack concurrently, get HID report from host and print out to device CDC. This example only work with multiple-controller MCUs and rp2040 with the help of pio-usb as added controller. @@ -17,10 +90,12 @@ Controller Driver (DCD & HCD) ----------------------------- - Enhance rhports management to better support dual roles + - CFG_TUD_ENABLED/CFG_TUH_ENABLED, CFG_TUD_MAX_SPEED/CFG_TUH_MAX_SPEED can be used to replace CFG_TUSB_RHPORT0_MODE/CFG_TUSB_RHPORT1_MODE - tud_init(rphort), tuh_init(rhport) can be used to init stack on specified roothub port (controller) instead of tusb_init(void) - Add dcd/hcd port specific defines TUP_ (stand for tinyusb port-specific) - [dwc2] + - Update to support stm32 h72x, h73x with only 1 otg controller - Fix overwrite with grstctl when disable endpoint - [EHCI] Fix an issue with EHCI driver @@ -28,6 +103,7 @@ Controller Driver (DCD & HCD) - [nrf5x] Fix DMA access race condition using atomic function - [pic32] Fix PIC32 santiy - [rp2040] + - Add PICO-PIO-USB as controller (device/host) support for rp2040 - Use shared IRQ handlers, so user can also hook the USB IRQ - Fix resumed signal not reported to device stack @@ -37,10 +113,12 @@ Device Stack ------------ - [Audio] Add support for feedback endpoint computation + - New API tud_audio_feedback_params_cb(), tud_audio_feedback_interval_isr(). - Supported computation method are: frequency with fixed/float or power of 2. Feedback with fifo count is not yet supported. - Fix nitfs (should be 3) in TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR - Fix typo in audiod_rx_done_cb() + - [DFU] Fix coexistence with other interfaces BTH, RNDIS - [MSC] Fix inquiry response additional length field - [Venndor] Improve write performance @@ -52,9 +130,11 @@ Host Stack - [HID] Open OUT endpoint if available - [Hub] hub clear port and device interrupts - [USBH] Major improvement + - Rework usbh control transfer with complete callback. New API tuh_control_xfer() though still only carry 1 usbh (no queueing) at a time. - Add generic endpoint transfer with tuh_edpt_open(), tuh_edpt_xfer(). Require `CFG_TUH_API_EDPT_XFER=1` - Support app-level enumeration with new APIs + - tuh_descriptor_get(), tuh_descriptor_get_device(), tuh_descriptor_get_configuration(), tuh_descriptor_get_hid_report() - tuh_descriptor_get_string(), tuh_descriptor_get_manufacturer_string(), tuh_descriptor_get_product_string(), tuh_descriptor_get_serial_string() - Also add _sync() as sync/blocking version for above APIs diff --git a/repository.yml b/repository.yml index dc341a3c1..702753a90 100644 --- a/repository.yml +++ b/repository.yml @@ -12,7 +12,6 @@ repo.versions: "0.12.0": "0.12.0" "0.13.0": "0.13.0" "0.14.0": "0.14.0" - - "0-dev": "0.0.0" # master - "0-latest": "0.14.0" # latest stable release - + "0.15.0": "0.15.0" + "0-latest": "0.15.0" + "0-dev": "0.0.0" diff --git a/src/tusb_option.h b/src/tusb_option.h index cf5b21c9c..eb46ce295 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -30,7 +30,7 @@ #include "common/tusb_compiler.h" #define TUSB_VERSION_MAJOR 0 -#define TUSB_VERSION_MINOR 14 +#define TUSB_VERSION_MINOR 15 #define TUSB_VERSION_REVISION 0 #define TUSB_VERSION_STRING TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION) diff --git a/tools/make_release.py b/tools/make_release.py new file mode 100644 index 000000000..7481e8864 --- /dev/null +++ b/tools/make_release.py @@ -0,0 +1,40 @@ +import re + +version = '0.15.0' + +print('version {}'.format(version)) +ver_id = version.split('.') + +################### +# src/tusb_option.h +################### +f_option_h = 'src/tusb_option.h' + +with open(f_option_h) as f: + fdata = f.read() + +fdata = re.sub(r'(#define TUSB_VERSION_MAJOR *) \d+', r"\1 {}".format(ver_id[0]), fdata) +fdata = re.sub(r'(#define TUSB_VERSION_MINOR *) \d+', r"\1 {}".format(ver_id[1]), fdata) +fdata = re.sub(r'(#define TUSB_VERSION_REVISION *) \d+', r"\1 {}".format(ver_id[2]), fdata) + +# Write the file out again +with open(f_option_h, 'w') as f: + f.write(fdata) + +################### +# repository.yml +################### +f_repository_yml = 'repository.yml' +with open(f_repository_yml) as f: + fdata = f.read() + +if fdata.find(version) < 0: + fdata = re.sub(r'("0-latest"): "\d+\.\d+\.\d+"', r'"{}": "{}"\r\n \1: "{}"'.format(version, version, version), fdata) + with open(f_repository_yml, 'w') as f: + f.write(fdata) + +################### +# docs/info/changelog.rst +################### + +print("Update docs/info/changelog.rst") -- cgit v1.3.1 From f48ae4aad7dea10e318bf82d1b59a75a3c325697 Mon Sep 17 00:00:00 2001 From: Jeff Trull Date: Fri, 10 Feb 2023 15:54:04 -0800 Subject: Adjust reserved bitfields to make SDCC happy - keep each field at or under 16b - For optimal packing, segment fields to 8b boundaries --- src/class/cdc/cdc.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index 2fecde3ca..842ea4dfe 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -377,7 +377,9 @@ typedef struct TU_ATTR_PACKED uint32_t incoming_distinctive : 1; ///< 0 : Reports only incoming ringing. 1 : Reports incoming distinctive ringing patterns. uint32_t dual_tone_multi_freq : 1; ///< 0 : Cannot report dual tone multi-frequency (DTMF) digits input remotely over the telephone line. 1 : Can report DTMF digits input remotely over the telephone line. uint32_t line_state_change : 1; ///< 0 : Does not support line state change notification. 1 : Does support line state change notification - uint32_t TU_RESERVED : 26; + uint32_t TU_RESERVED0 : 2; + uint32_t TU_RESERVED1 : 16; + uint32_t TU_RESERVED2 : 4; } bmCapabilities; }cdc_desc_func_telephone_call_state_reporting_capabilities_t; @@ -404,7 +406,8 @@ typedef struct TU_ATTR_PACKED { uint16_t dtr : 1; uint16_t rts : 1; - uint16_t : 14; + uint16_t : 6; + uint16_t : 8; } cdc_line_control_state_t; TU_VERIFY_STATIC(sizeof(cdc_line_control_state_t) == 2, "size is not correct"); -- cgit v1.3.1 From 7e2c5fcc8aa7c39f6c65d7cb85c7d4522b0050be Mon Sep 17 00:00:00 2001 From: Jeff Trull Date: Sun, 12 Feb 2023 20:52:17 -0800 Subject: Correct bitfields for cdc_desc_func_telephone_call_state_reporting_capabilities_t --- src/class/cdc/cdc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index 842ea4dfe..4658e43af 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -379,7 +379,7 @@ typedef struct TU_ATTR_PACKED uint32_t line_state_change : 1; ///< 0 : Does not support line state change notification. 1 : Does support line state change notification uint32_t TU_RESERVED0 : 2; uint32_t TU_RESERVED1 : 16; - uint32_t TU_RESERVED2 : 4; + uint32_t TU_RESERVED2 : 8; } bmCapabilities; }cdc_desc_func_telephone_call_state_reporting_capabilities_t; -- cgit v1.3.1 From fde757711785670a005095454cc0b06129f8ae80 Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Wed, 15 Feb 2023 20:02:12 -0800 Subject: Fix issue 1909 --- src/class/midi/midi_device.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c index de41706e8..eb1a770dd 100644 --- a/src/class/midi/midi_device.c +++ b/src/class/midi/midi_device.c @@ -261,11 +261,11 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const* stream->buffer[1] = data; // Check to see if we're still in a SysEx transmit. - if ( stream->buffer[0] == MIDI_CIN_SYSEX_START ) + if ( ((stream->buffer[0]) & 0xF) == MIDI_CIN_SYSEX_START ) { if ( data == MIDI_STATUS_SYSEX_END ) { - stream->buffer[0] = MIDI_CIN_SYSEX_END_1BYTE; + stream->buffer[0] = (uint8_t) ((cable_num << 4) | MIDI_CIN_SYSEX_END_1BYTE); stream->total = 2; } else @@ -308,6 +308,7 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const* stream->buffer[0] = MIDI_CIN_SYSEX_END_1BYTE; stream->total = 2; } + stream->buffer[0] |= (uint8_t)(cable_num << 4); } else { @@ -328,9 +329,9 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const* stream->index++; // See if this byte ends a SysEx. - if ( stream->buffer[0] == MIDI_CIN_SYSEX_START && data == MIDI_STATUS_SYSEX_END ) + if ( (stream->buffer[0] & 0xF) == MIDI_CIN_SYSEX_START && data == MIDI_STATUS_SYSEX_END ) { - stream->buffer[0] = MIDI_CIN_SYSEX_START + (stream->index - 1); + stream->buffer[0] = (uint8_t) ((cable_num << 4) | (MIDI_CIN_SYSEX_START + (stream->index - 1))); stream->total = stream->index; } } -- cgit v1.3.1 From d367e8f8a8acd82c89ba3c029495b9404c3b7fdb Mon Sep 17 00:00:00 2001 From: Ryzee119 Date: Sat, 4 Jun 2022 13:44:22 +0930 Subject: ohci: Expand roothub descriptors into unions --- src/portable/ohci/ohci.h | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h index f40ae24cc..c42db141a 100644 --- a/src/portable/ohci/ohci.h +++ b/src/portable/ohci/ohci.h @@ -230,8 +230,27 @@ typedef volatile struct uint32_t periodic_start; uint32_t lowspeed_threshold; - uint32_t rh_descriptorA; - uint32_t rh_descriptorB; + union { + uint32_t rh_descriptorA; + struct { + uint32_t number_downstream_ports : 8; + uint32_t power_switching_mode : 1; + uint32_t no_power_switching : 1; + uint32_t device_type : 1; + uint32_t overcurrent_protection_mode : 1; + uint32_t no_over_current_protection : 1; + uint32_t reserved : 11; + uint32_t power_on_to_good_time : 8; + } rh_descriptorA_bit; + }; + + union { + uint32_t rh_descriptorB; + struct { + uint32_t device_removable : 16; + uint32_t port_power_control_mask : 16; + } rh_descriptorB_bit; + }; union { uint32_t rh_status; -- cgit v1.3.1 From c820c8769267644af049e0be73b04b45d57e8d98 Mon Sep 17 00:00:00 2001 From: Ryzee119 Date: Sat, 4 Jun 2022 13:47:02 +0930 Subject: ohci: Support configurable number of roothub ports --- src/common/tusb_mcu.h | 1 + src/portable/ohci/ohci.c | 39 ++++++++++++++++++++++----------------- src/portable/ohci/ohci.h | 6 +++--- 3 files changed, 26 insertions(+), 20 deletions(-) (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 0b10c5118..ee2b896ac 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -55,6 +55,7 @@ #elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX) #define TUP_DCD_ENDPOINT_MAX 16 #define TUP_USBIP_OHCI + #define OHCI_RHPORTS 2 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) // TODO USB0 has 6, USB1 has 4 diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 228da6ae0..45600c03b 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -28,6 +28,10 @@ #if CFG_TUH_ENABLED && defined(TUP_USBIP_OHCI) +#ifndef OHCI_RHPORTS +#error OHCI is enabled, but OHCI_RHPORTS is not defined. +#endif + //--------------------------------------------------------------------+ // INCLUDE //--------------------------------------------------------------------+ @@ -620,29 +624,30 @@ void hcd_int_handler(uint8_t hostid) //------------- RootHub status -------------// if ( int_status & OHCI_INT_RHPORT_STATUS_CHANGE_MASK ) { - uint32_t const rhport_status = OHCI_REG->rhport_status[0] & RHPORT_ALL_CHANGE_MASK; - - // TODO dual port is not yet supported - if ( rhport_status & RHPORT_CONNECT_STATUS_CHANGE_MASK ) + for (int i = 0; i < OHCI_RHPORTS; i++) { - // TODO check if remote wake-up - if ( OHCI_REG->rhport_status_bit[0].current_connect_status ) + uint32_t const rhport_status = OHCI_REG->rhport_status[i] & RHPORT_ALL_CHANGE_MASK; + if ( rhport_status & RHPORT_CONNECT_STATUS_CHANGE_MASK ) { - // TODO reset port immediately, without this controller will got 2-3 (debouncing connection status change) - OHCI_REG->rhport_status[0] = RHPORT_PORT_RESET_STATUS_MASK; - hcd_event_device_attach(hostid, true); - }else - { - hcd_event_device_remove(hostid, true); + // TODO check if remote wake-up + if ( OHCI_REG->rhport_status_bit[i].current_connect_status ) + { + // TODO reset port immediately, without this controller will got 2-3 (debouncing connection status change) + OHCI_REG->rhport_status[i] = RHPORT_PORT_RESET_STATUS_MASK; + hcd_event_device_attach(i, true); + }else + { + hcd_event_device_remove(i, true); + } } - } - if ( rhport_status & RHPORT_PORT_SUSPEND_CHANGE_MASK) - { + if ( rhport_status & RHPORT_PORT_SUSPEND_CHANGE_MASK) + { - } + } - OHCI_REG->rhport_status[0] = rhport_status; // acknowledge all interrupt + OHCI_REG->rhport_status[i] = rhport_status; // acknowledge all interrupt + } } //------------- Transfer Complete -------------// diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h index c42db141a..b7706b636 100644 --- a/src/portable/ohci/ohci.h +++ b/src/portable/ohci/ohci.h @@ -267,7 +267,7 @@ typedef volatile struct }; union { - uint32_t rhport_status[2]; // TODO NXP OHCI controller only has 2 ports + uint32_t rhport_status[OHCI_RHPORTS]; struct { uint32_t current_connect_status : 1; uint32_t port_enable_status : 1; @@ -284,11 +284,11 @@ typedef volatile struct uint32_t port_over_current_indicator_change : 1; uint32_t port_reset_status_change : 1; uint32_t TU_RESERVED : 11; - }rhport_status_bit[2]; + }rhport_status_bit[OHCI_RHPORTS]; }; }ohci_registers_t; -TU_VERIFY_STATIC( sizeof(ohci_registers_t) == 0x5c, "size is not correct"); +TU_VERIFY_STATIC( sizeof(ohci_registers_t) == (0x54 + (4 * OHCI_RHPORTS)), "size is not correct"); #ifdef __cplusplus } -- cgit v1.3.1 From d5e6d028171a38e435ac1ab7c18ae5615f8af5cf Mon Sep 17 00:00:00 2001 From: Ryzee119 Date: Sat, 4 Jun 2022 14:06:23 +0930 Subject: ohci: Leave SMM or bios mode during init --- src/portable/ohci/ohci.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src') diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 45600c03b..364f61cf1 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -177,6 +177,22 @@ bool hcd_init(uint8_t rhport) ohci_data.bulk_head_ed.skip = 1; ohci_data.period_head_ed.skip = 1; + //If OHCI hardware is in SMM mode, gain ownership (Ref OHCI spec 5.1.1.3.3) + if (OHCI_REG->control_bit.interrupt_routing == 1) + { + OHCI_REG->command_status_bit.ownership_change_request = 1; + while (OHCI_REG->control_bit.interrupt_routing == 1) {} + } + + //If OHCI hardware has come from warm-boot, signal resume (Ref OHCI spec 5.1.1.3.4) + else if (OHCI_REG->control_bit.hc_functional_state != OHCI_CONTROL_FUNCSTATE_RESET && + OHCI_REG->control_bit.hc_functional_state != OHCI_CONTROL_FUNCSTATE_OPERATIONAL) + { + //Wait 20 ms. (Ref Usb spec 7.1.7.7) + OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_RESUME; + osal_task_delay(20); + } + // reset controller OHCI_REG->command_status_bit.controller_reset = 1; while( OHCI_REG->command_status_bit.controller_reset ) {} // should not take longer than 10 us -- cgit v1.3.1 From 2063ee5f1592979cc858b748aff51dba7cb3bcd5 Mon Sep 17 00:00:00 2001 From: Ryzee119 Date: Sat, 4 Jun 2022 14:09:21 +0930 Subject: ohci: Toggle frameinterval bit on update --- src/portable/ohci/ohci.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 364f61cf1..cf6cff364 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -212,6 +212,7 @@ bool hcd_init(uint8_t rhport) OHCI_CONTROL_LIST_BULK_ENABLE_MASK | OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK; // TODO Isochronous OHCI_REG->frame_interval = (OHCI_FMINTERVAL_FSMPS << 16) | OHCI_FMINTERVAL_FI; + OHCI_REG->frame_interval ^= (1 << 31); //Must toggle when frame_interval is updated. OHCI_REG->periodic_start = (OHCI_FMINTERVAL_FI * 9) / 10; // Periodic start is 90% of frame interval OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_OPERATIONAL; // make HC's state to operational state TODO use this to suspend (save power) -- cgit v1.3.1 From c1d0fd1bd747bfc4881ecf69bc60fbcb106a7afd Mon Sep 17 00:00:00 2001 From: Ryzee119 Date: Sat, 4 Jun 2022 14:11:34 +0930 Subject: ohci: Wait POTG time after port power --- src/portable/ohci/ohci.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index cf6cff364..0a715a962 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -217,6 +217,7 @@ bool hcd_init(uint8_t rhport) OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_OPERATIONAL; // make HC's state to operational state TODO use this to suspend (save power) OHCI_REG->rh_status_bit.local_power_status_change = 1; // set global power for ports + osal_task_delay(OHCI_REG->rh_descriptorA_bit.power_on_to_good_time * 2); // Wait POTG after power up return true; } -- cgit v1.3.1 From 5d3c0fb922604989e7f7e7f628fe43553ac78df7 Mon Sep 17 00:00:00 2001 From: Ryzee119 Date: Sat, 4 Jun 2022 14:14:53 +0930 Subject: ohci: Force reset of devices already connected on power up --- src/portable/ohci/ohci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 0a715a962..85795c5b4 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -208,7 +208,7 @@ bool hcd_init(uint8_t rhport) OHCI_INT_UNRECOVERABLE_ERROR_MASK | OHCI_INT_FRAME_OVERFLOW_MASK | OHCI_INT_RHPORT_STATUS_CHANGE_MASK | OHCI_INT_MASTER_ENABLE_MASK; - OHCI_REG->control |= OHCI_CONTROL_CONTROL_BULK_RATIO | OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK | + OHCI_REG->control = OHCI_CONTROL_CONTROL_BULK_RATIO | OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK | OHCI_CONTROL_LIST_BULK_ENABLE_MASK | OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK; // TODO Isochronous OHCI_REG->frame_interval = (OHCI_FMINTERVAL_FSMPS << 16) | OHCI_FMINTERVAL_FI; -- cgit v1.3.1 From e89e8ba392dae795663169d02952116b3f3980f3 Mon Sep 17 00:00:00 2001 From: Ryzee119 Date: Sat, 4 Jun 2022 14:18:53 +0930 Subject: ohci: Direct port commands to the correct rhport. --- src/portable/ohci/ohci.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 85795c5b4..b0c6bb63c 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -234,8 +234,7 @@ uint32_t hcd_frame_number(uint8_t rhport) //--------------------------------------------------------------------+ void hcd_port_reset(uint8_t hostid) { - (void) hostid; - OHCI_REG->rhport_status[0] = RHPORT_PORT_RESET_STATUS_MASK; + OHCI_REG->rhport_status[hostid] = RHPORT_PORT_RESET_STATUS_MASK; } void hcd_port_reset_end(uint8_t rhport) @@ -245,14 +244,12 @@ void hcd_port_reset_end(uint8_t rhport) bool hcd_port_connect_status(uint8_t hostid) { - (void) hostid; - return OHCI_REG->rhport_status_bit[0].current_connect_status; + return OHCI_REG->rhport_status_bit[hostid].current_connect_status; } tusb_speed_t hcd_port_speed_get(uint8_t hostid) { - (void) hostid; - return OHCI_REG->rhport_status_bit[0].low_speed_device_attached ? TUSB_SPEED_LOW : TUSB_SPEED_FULL; + return OHCI_REG->rhport_status_bit[hostid].low_speed_device_attached ? TUSB_SPEED_LOW : TUSB_SPEED_FULL; } // endpoints are tied to an address, which only reclaim after a long delay when enumerating -- cgit v1.3.1 From cc9c3feeaee69b369aea4fb4f70e4f0fb1033990 Mon Sep 17 00:00:00 2001 From: Ryan Wendland Date: Sat, 4 Jun 2022 22:40:06 +0930 Subject: ohci: Fix bug in ed removal --- src/portable/ohci/ohci.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index b0c6bb63c..59ffd2725 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -383,6 +383,7 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr) // point the removed ED's next pointer to list head to make sure HC can always safely move away from this ED ed->next = (uint32_t) p_head; ed->used = 0; + continue; } // check next valid since we could remove it -- cgit v1.3.1 From f87262185ec64e6ad616972720a72ffed65708ac Mon Sep 17 00:00:00 2001 From: Ryan Wendland Date: Sat, 4 Jun 2022 22:49:07 +0930 Subject: ohci: Set skip on ed prior to removal --- src/portable/ohci/ohci.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 59ffd2725..d51b9a883 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -377,12 +377,16 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr) if (ed->dev_addr == dev_addr) { + //Prevent Host Controller from processing this ED while we remove it + ed->skip = 1; + // unlink ed p_prev->next = ed->next; // point the removed ED's next pointer to list head to make sure HC can always safely move away from this ED ed->next = (uint32_t) p_head; ed->used = 0; + ed->skip = 0; continue; } -- cgit v1.3.1 From f2a6af05b1cd7c298e6781e4374d744e2625c63f Mon Sep 17 00:00:00 2001 From: Ryan Wendland Date: Thu, 9 Jun 2022 08:32:49 +0930 Subject: ohci: Add ability to separate physical and virtual memory --- src/portable/ohci/ohci.c | 51 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 34 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index d51b9a883..d85550d80 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -161,6 +161,22 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr); //--------------------------------------------------------------------+ // USBH-HCD API //--------------------------------------------------------------------+ + +//If your system requires separation of virtual and physical memory, implement +//tuh_get_phys_addr and tuh_get_virt_addr in your application. +TU_ATTR_WEAK void *tuh_get_phys_addr(void *virtual_address); +TU_ATTR_WEAK void *tuh_get_virt_addr(void *physical_address); +TU_ATTR_ALWAYS_INLINE static void *_phys_addr(void *virtual_address) +{ + if (tuh_get_phys_addr) return tuh_get_phys_addr(virtual_address); + return virtual_address; +} +TU_ATTR_ALWAYS_INLINE static void *_virt_addr(void *physical_address) +{ + if (tuh_get_virt_addr) return tuh_get_virt_addr(physical_address); + return physical_address; +} + // Initialization according to 5.1.1.4 bool hcd_init(uint8_t rhport) { @@ -170,7 +186,7 @@ bool hcd_init(uint8_t rhport) tu_memclr(&ohci_data, sizeof(ohci_data_t)); for(uint8_t i=0; i<32; i++) { // assign all interrupt pointers to period head ed - ohci_data.hcca.interrupt_table[i] = (uint32_t) &ohci_data.period_head_ed; + ohci_data.hcca.interrupt_table[i] = (uint32_t) _phys_addr(&ohci_data.period_head_ed); } ohci_data.control[0].ed.skip = 1; @@ -198,9 +214,9 @@ bool hcd_init(uint8_t rhport) while( OHCI_REG->command_status_bit.controller_reset ) {} // should not take longer than 10 us //------------- init ohci registers -------------// - OHCI_REG->control_head_ed = (uint32_t) &ohci_data.control[0].ed; - OHCI_REG->bulk_head_ed = (uint32_t) &ohci_data.bulk_head_ed; - OHCI_REG->hcca = (uint32_t) &ohci_data.hcca; + OHCI_REG->control_head_ed = (uint32_t) _phys_addr(&ohci_data.control[0].ed); + OHCI_REG->bulk_head_ed = (uint32_t) _phys_addr(&ohci_data.bulk_head_ed); + OHCI_REG->hcca = (uint32_t) _phys_addr(&ohci_data.hcca); OHCI_REG->interrupt_disable = OHCI_REG->interrupt_enable; // disable all interrupts OHCI_REG->interrupt_status = OHCI_REG->interrupt_status; // clear current set bits @@ -327,8 +343,8 @@ static void gtd_init(ohci_gtd_t* p_td, uint8_t* data_ptr, uint16_t total_bytes) p_td->delay_interrupt = OHCI_INT_ON_COMPLETE_NO; p_td->condition_code = OHCI_CCODE_NOT_ACCESSED; - p_td->current_buffer_pointer = data_ptr; - p_td->buffer_end = total_bytes ? (data_ptr + total_bytes-1) : data_ptr; + p_td->current_buffer_pointer = _phys_addr(data_ptr); + p_td->buffer_end = total_bytes ? (_phys_addr(data_ptr + total_bytes - 1)) : (uint8_t *)p_td->current_buffer_pointer; } static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr) @@ -364,7 +380,7 @@ static ohci_ed_t * ed_find_free(void) static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed) { p_ed->next = p_pre->next; - p_pre->next = (uint32_t) p_ed; + p_pre->next = (uint32_t) _phys_addr(p_ed); } static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr) @@ -373,7 +389,7 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr) while( p_prev->next ) { - ohci_ed_t* ed = (ohci_ed_t*) p_prev->next; + ohci_ed_t* ed = (ohci_ed_t*) _virt_addr((void *)p_prev->next); if (ed->dev_addr == dev_addr) { @@ -384,14 +400,14 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr) p_prev->next = ed->next; // point the removed ED's next pointer to list head to make sure HC can always safely move away from this ED - ed->next = (uint32_t) p_head; + ed->next = (uint32_t) _phys_addr(p_head); ed->used = 0; ed->skip = 0; continue; } // check next valid since we could remove it - if (p_prev->next) p_prev = (ohci_ed_t*) p_prev->next; + if (p_prev->next) p_prev = (ohci_ed_t*) _virt_addr((void *)p_prev->next); } } @@ -410,11 +426,11 @@ static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd) // tail is always NULL if ( tu_align16(p_ed->td_head.address) == 0 ) { // TD queue is empty --> head = TD - p_ed->td_head.address |= (uint32_t) p_gtd; + p_ed->td_head.address |= (uint32_t) _phys_addr(p_gtd); } else { // TODO currently only support queue up to 2 TD each endpoint at a time - ((ohci_gtd_t*) tu_align16(p_ed->td_head.address))->next = (uint32_t) p_gtd; + ((ohci_gtd_t*) tu_align16((uint32_t)_virt_addr((void *)p_ed->td_head.address)))->next = (uint32_t) _phys_addr(p_gtd); } } @@ -470,7 +486,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet qtd->delay_interrupt = 0; //------------- Attach TDs list to Control Endpoint -------------// - ed->td_head.address = (uint32_t) qtd; + ed->td_head.address = (uint32_t) _phys_addr(qtd); OHCI_REG->command_status_bit.control_list_filled = 1; @@ -496,7 +512,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * gtd->data_toggle = GTD_DT_DATA1; // Both Data and Ack stage start with DATA1 gtd->delay_interrupt = 0; - ed->td_head.address = (uint32_t) gtd; + ed->td_head.address = (uint32_t) _phys_addr(gtd); OHCI_REG->command_status_bit.control_list_filled = 1; }else @@ -544,16 +560,17 @@ static ohci_td_item_t* list_reverse(ohci_td_item_t* td_head) while(td_head != NULL) { + td_head = _virt_addr(td_head); uint32_t next = td_head->next; // make current's item become reverse's first item td_head->next = (uint32_t) td_reverse_head; - td_reverse_head = td_head; + td_reverse_head = _phys_addr(td_head); td_head = (ohci_td_item_t*) next; // advance to next item } - return td_reverse_head; + return _virt_addr(td_reverse_head); } static inline bool gtd_is_control(ohci_gtd_t const * const p_qtd) @@ -624,7 +641,7 @@ static void done_queue_isr(uint8_t hostid) hcd_event_xfer_complete(ed->dev_addr, tu_edpt_addr(ed->ep_number, dir), xferred_bytes, event, true); } - td_head = (ohci_td_item_t*) td_head->next; + td_head = (ohci_td_item_t*) _virt_addr((void *)td_head->next); } } -- cgit v1.3.1 From 75f6583c1c9ad3e0c2fc9e3427a649edbf765bef Mon Sep 17 00:00:00 2001 From: Ryzee119 Date: Mon, 13 Jun 2022 13:01:41 +0930 Subject: ohci: Use enum instead of magic number --- src/portable/ohci/ohci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index d85550d80..d16de0cca 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -483,7 +483,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet qtd->index = dev_addr; qtd->pid = PID_SETUP; qtd->data_toggle = GTD_DT_DATA0; - qtd->delay_interrupt = 0; + qtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES; //------------- Attach TDs list to Control Endpoint -------------// ed->td_head.address = (uint32_t) _phys_addr(qtd); @@ -510,7 +510,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * gtd->index = dev_addr; gtd->pid = dir ? PID_IN : PID_OUT; gtd->data_toggle = GTD_DT_DATA1; // Both Data and Ack stage start with DATA1 - gtd->delay_interrupt = 0; + gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES; ed->td_head.address = (uint32_t) _phys_addr(gtd); @@ -524,7 +524,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * gtd_init(gtd, buffer, buflen); gtd->index = ed-ohci_data.ed_pool; - gtd->delay_interrupt = 0; + gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES; td_insert_to_ed(ed, gtd); -- cgit v1.3.1 From 4e2afdf5e1d72a2232f349a878c3d4147fc43cd6 Mon Sep 17 00:00:00 2001 From: wooyay <7655456+wooyay@users.noreply.github.com> Date: Tue, 14 Feb 2023 17:03:19 +0000 Subject: ohci: Disable MIE interrupt during IRQ processing, zero HccADoneHead on completion --- src/portable/ohci/ohci.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src') diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index d16de0cca..76f97844c 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -606,6 +606,7 @@ static void done_queue_isr(uint8_t hostid) // done head is written in reversed order of completion --> need to reverse the done queue first ohci_td_item_t* td_head = list_reverse ( (ohci_td_item_t*) tu_align16(ohci_data.hcca.done_head) ); + ohci_data.hcca.done_head = 0; while( td_head != NULL ) { @@ -652,6 +653,9 @@ void hcd_int_handler(uint8_t hostid) if (int_status == 0) return; + // Disable MIE as per OHCI spec 5.3 + OHCI_REG->interrupt_disable = OHCI_INT_MASTER_ENABLE_MASK; + // Frame number overflow if ( int_status & OHCI_INT_FRAME_OVERFLOW_MASK ) { @@ -694,6 +698,8 @@ void hcd_int_handler(uint8_t hostid) } OHCI_REG->interrupt_status = int_status; // Acknowledge handled interrupt + + OHCI_REG->interrupt_enable = OHCI_INT_MASTER_ENABLE_MASK; // Enable MIE } //--------------------------------------------------------------------+ // HELPER -- cgit v1.3.1 From 03ec49450d2109a0e6ede3672e95426fd87aa48f Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Feb 2023 11:47:09 +0700 Subject: rename maros from FUZZ to _FUZZ, change TU_STATIC to static _fuzz_thread --- .vscode/settings.json | 3 --- src/class/cdc/cdc_device.c | 2 +- src/class/dfu/dfu_device.c | 14 +++++++------- src/class/hid/hid_device.c | 2 +- src/class/msc/msc_device.c | 8 ++++---- src/class/net/ecm_rndis_device.c | 17 ++++++++++------- src/class/net/ncm_device.c | 12 ++++++------ src/class/usbtmc/usbtmc_device.c | 8 ++++---- src/class/vendor/vendor_device.c | 2 +- src/class/vendor/vendor_device.h | 3 +-- src/class/video/video_device.c | 8 ++++---- src/common/tusb_compiler.h | 6 +++--- src/common/tusb_debug.h | 2 +- src/common/tusb_types.h | 4 ++-- src/device/usbd.c | 18 +++++++++--------- src/device/usbd_control.c | 4 ++-- test/fuzz/make.mk | 2 +- 17 files changed, 57 insertions(+), 58 deletions(-) delete mode 100644 .vscode/settings.json (limited to 'src') diff --git a/.vscode/settings.json b/.vscode/settings.json deleted file mode 100644 index 97924983a..000000000 --- a/.vscode/settings.json +++ /dev/null @@ -1,3 +0,0 @@ -{ - "editor.formatOnSave": false -} \ No newline at end of file diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index b943c1caf..59ed2a74c 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -76,7 +76,7 @@ typedef struct //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION TU_STATIC cdcd_interface_t _cdcd_itf[CFG_TUD_CDC]; +CFG_TUSB_MEM_SECTION static _fuzz_thread cdcd_interface_t _cdcd_itf[CFG_TUD_CDC]; static bool _prep_out_transaction (cdcd_interface_t* p_cdc) { diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c index a318603d3..9e7b8b5b1 100644 --- a/src/class/dfu/dfu_device.c +++ b/src/class/dfu/dfu_device.c @@ -56,7 +56,7 @@ typedef struct } dfu_state_ctx_t; // Only a single dfu state is allowed -CFG_TUSB_MEM_SECTION TU_STATIC dfu_state_ctx_t _dfu_ctx; +CFG_TUSB_MEM_SECTION static _fuzz_thread dfu_state_ctx_t _dfu_ctx; static void reset_state(void) { @@ -74,7 +74,7 @@ static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, tusb_cont //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= 2 -TU_STATIC tu_lookup_entry_t const _dfu_request_lookup[] = +static _fuzz_thread tu_lookup_entry_t const _dfu_request_lookup[] = { { .key = DFU_REQUEST_DETACH , .data = "DETACH" }, { .key = DFU_REQUEST_DNLOAD , .data = "DNLOAD" }, @@ -85,13 +85,13 @@ TU_STATIC tu_lookup_entry_t const _dfu_request_lookup[] = { .key = DFU_REQUEST_ABORT , .data = "ABORT" }, }; -TU_STATIC tu_lookup_table_t const _dfu_request_table = +static _fuzz_thread tu_lookup_table_t const _dfu_request_table = { .count = TU_ARRAY_SIZE(_dfu_request_lookup), .items = _dfu_request_lookup }; -TU_STATIC tu_lookup_entry_t const _dfu_state_lookup[] = +static _fuzz_thread tu_lookup_entry_t const _dfu_state_lookup[] = { { .key = APP_IDLE , .data = "APP_IDLE" }, { .key = APP_DETACH , .data = "APP_DETACH" }, @@ -106,13 +106,13 @@ TU_STATIC tu_lookup_entry_t const _dfu_state_lookup[] = { .key = DFU_ERROR , .data = "ERROR" }, }; -TU_STATIC tu_lookup_table_t const _dfu_state_table = +static _fuzz_thread tu_lookup_table_t const _dfu_state_table = { .count = TU_ARRAY_SIZE(_dfu_state_lookup), .items = _dfu_state_lookup }; -TU_STATIC tu_lookup_entry_t const _dfu_status_lookup[] = +static _fuzz_thread tu_lookup_entry_t const _dfu_status_lookup[] = { { .key = DFU_STATUS_OK , .data = "OK" }, { .key = DFU_STATUS_ERR_TARGET , .data = "errTARGET" }, @@ -132,7 +132,7 @@ TU_STATIC tu_lookup_entry_t const _dfu_status_lookup[] = { .key = DFU_STATUS_ERR_STALLEDPKT , .data = "errSTALLEDPKT" }, }; -TU_STATIC tu_lookup_table_t const _dfu_status_table = +static _fuzz_thread tu_lookup_table_t const _dfu_status_table = { .count = TU_ARRAY_SIZE(_dfu_status_lookup), .items = _dfu_status_lookup diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c index c42d1b6de..546c93010 100644 --- a/src/class/hid/hid_device.c +++ b/src/class/hid/hid_device.c @@ -58,7 +58,7 @@ typedef struct tusb_hid_descriptor_hid_t const * hid_descriptor; } hidd_interface_t; -CFG_TUSB_MEM_SECTION TU_STATIC hidd_interface_t _hidd_itf[CFG_TUD_HID]; +CFG_TUSB_MEM_SECTION static _fuzz_thread hidd_interface_t _hidd_itf[CFG_TUD_HID]; /*------------- Helpers -------------*/ static inline uint8_t get_index_by_itfnum(uint8_t itf_num) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index bf56ed9bf..e77342777 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -71,8 +71,8 @@ typedef struct uint8_t add_sense_qualifier; }mscd_interface_t; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC mscd_interface_t _mscd_itf; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE]; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread mscd_interface_t _mscd_itf; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE]; //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION @@ -202,7 +202,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= 2 -TU_ATTR_UNUSED TU_STATIC tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = +TU_ATTR_UNUSED static _fuzz_thread tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = { { .key = SCSI_CMD_TEST_UNIT_READY , .data = "Test Unit Ready" }, { .key = SCSI_CMD_INQUIRY , .data = "Inquiry" }, @@ -217,7 +217,7 @@ TU_ATTR_UNUSED TU_STATIC tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = { .key = SCSI_CMD_WRITE_10 , .data = "Write10" } }; -TU_ATTR_UNUSED TU_STATIC tu_lookup_table_t const _msc_scsi_cmd_table = +TU_ATTR_UNUSED static _fuzz_thread tu_lookup_table_t const _msc_scsi_cmd_table = { .count = TU_ARRAY_SIZE(_msc_scsi_cmd_lookup), .items = _msc_scsi_cmd_lookup diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c index 560e1768d..e2a57cb50 100644 --- a/src/class/net/ecm_rndis_device.c +++ b/src/class/net/ecm_rndis_device.c @@ -61,8 +61,11 @@ typedef struct #define CFG_TUD_NET_PACKET_PREFIX_LEN sizeof(rndis_data_packet_t) #define CFG_TUD_NET_PACKET_SUFFIX_LEN 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread +uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; + +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread +uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; struct ecm_notify_struct { @@ -70,7 +73,7 @@ struct ecm_notify_struct uint32_t downlink, uplink; }; -TU_STATIC const struct ecm_notify_struct ecm_notify_nc = +static _fuzz_thread const struct ecm_notify_struct ecm_notify_nc = { .header = { .bmRequestType = 0xA1, @@ -80,7 +83,7 @@ TU_STATIC const struct ecm_notify_struct ecm_notify_nc = }, }; -TU_STATIC const struct ecm_notify_struct ecm_notify_csc = +static _fuzz_thread const struct ecm_notify_struct ecm_notify_csc = { .header = { .bmRequestType = 0xA1, @@ -92,7 +95,7 @@ TU_STATIC const struct ecm_notify_struct ecm_notify_csc = }; // TODO remove CFG_TUSB_MEM_SECTION, control internal buffer is already in this special section -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC union +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread union { uint8_t rndis_buf[120]; struct ecm_notify_struct ecm_buf; @@ -102,9 +105,9 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC union // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ // TODO remove CFG_TUSB_MEM_SECTION -CFG_TUSB_MEM_SECTION TU_STATIC netd_interface_t _netd_itf; +CFG_TUSB_MEM_SECTION static _fuzz_thread netd_interface_t _netd_itf; -TU_STATIC bool can_xmit; +static _fuzz_thread bool can_xmit; void tud_network_recv_renew(void) { diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c index 236232191..b8a5c6d3a 100644 --- a/src/class/net/ncm_device.c +++ b/src/class/net/ncm_device.c @@ -130,7 +130,7 @@ typedef struct // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC const ntb_parameters_t ntb_parameters = { +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread const ntb_parameters_t ntb_parameters = { .wLength = sizeof(ntb_parameters_t), .bmNtbFormatsSupported = 0x01, .dwNtbInMaxSize = CFG_TUD_NCM_IN_NTB_MAX_SIZE, @@ -145,11 +145,11 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC const ntb_parameters_t ntb_par .wNtbOutMaxDatagrams = 0 }; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC transmit_ntb_t transmit_ntb[2]; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread transmit_ntb_t transmit_ntb[2]; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE]; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE]; -TU_STATIC ncm_interface_t ncm_interface; +static _fuzz_thread ncm_interface_t ncm_interface; /* * Set up the NTB state in ncm_interface to be ready to add datagrams. @@ -196,7 +196,7 @@ static void ncm_start_tx(void) { ncm_prepare_for_tx(); } -TU_STATIC struct ecm_notify_struct ncm_notify_connected = +static _fuzz_thread struct ecm_notify_struct ncm_notify_connected = { .header = { .bmRequestType_bit = { @@ -210,7 +210,7 @@ TU_STATIC struct ecm_notify_struct ncm_notify_connected = }, }; -TU_STATIC struct ecm_notify_struct ncm_notify_speed_change = +static _fuzz_thread struct ecm_notify_struct ncm_notify_speed_change = { .header = { .bmRequestType_bit = { diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index fd8220c1f..416cb9bb9 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -78,7 +78,7 @@ #ifdef xDEBUG #include "uart_util.h" -TU_STATIC char logMsg[150]; +static _fuzz_thread char logMsg[150]; #endif // Buffer size must be an exact multiple of the max packet size for both @@ -143,7 +143,7 @@ typedef struct usbtmc_capabilities_specific_t const * capabilities; } usbtmc_interface_state_t; -CFG_TUSB_MEM_SECTION TU_STATIC usbtmc_interface_state_t usbtmc_state = +CFG_TUSB_MEM_SECTION static _fuzz_thread usbtmc_interface_state_t usbtmc_state = { .itf_id = 0xFF, }; @@ -154,8 +154,8 @@ TU_VERIFY_STATIC(USBTMCD_BUFFER_SIZE >= 32u,"USBTMC dev buffer size too small"); static bool handle_devMsgOutStart(uint8_t rhport, void *data, size_t len); static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t packetLen); -TU_STATIC uint8_t termChar; -TU_STATIC uint8_t termCharRequested = false; +static _fuzz_thread uint8_t termChar; +static _fuzz_thread uint8_t termCharRequested = false; #if OSAL_MUTEX_REQUIRED static OSAL_MUTEX_DEF(usbtmcLockBuffer); diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index b33cbcf13..22124d193 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -59,7 +59,7 @@ typedef struct CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_VENDOR_EPSIZE]; } vendord_interface_t; -CFG_TUSB_MEM_SECTION TU_STATIC vendord_interface_t _vendord_itf[CFG_TUD_VENDOR]; +CFG_TUSB_MEM_SECTION static _fuzz_thread vendord_interface_t _vendord_itf[CFG_TUD_VENDOR]; #define ITF_MEM_RESET_SIZE offsetof(vendord_interface_t, rx_ff) diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h index 543500f0c..2bb6afa67 100644 --- a/src/class/vendor/vendor_device.h +++ b/src/class/vendor/vendor_device.h @@ -50,8 +50,7 @@ void tud_vendor_n_read_flush (uint8_t itf); uint32_t tud_vendor_n_write (uint8_t itf, void const* buffer, uint32_t bufsize); uint32_t tud_vendor_n_write_available (uint8_t itf); -TU_STATIC inline -uint32_t tud_vendor_n_write_str (uint8_t itf, char const* str); +static inline uint32_t tud_vendor_n_write_str (uint8_t itf, char const* str); uint32_t tud_vendor_n_flush (uint8_t itf); //--------------------------------------------------------------------+ diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 14518deac..54b45bc8e 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -125,11 +125,11 @@ typedef struct TU_ATTR_PACKED { //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION TU_STATIC videod_interface_t _videod_itf[CFG_TUD_VIDEO]; -CFG_TUSB_MEM_SECTION TU_STATIC videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING]; +CFG_TUSB_MEM_SECTION static _fuzz_thread videod_interface_t _videod_itf[CFG_TUD_VIDEO]; +CFG_TUSB_MEM_SECTION static _fuzz_thread videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING]; -TU_STATIC uint8_t const _cap_get = 0x1u; /* support for GET */ -TU_STATIC uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */ +static _fuzz_thread uint8_t const _cap_get = 0x1u; /* support for GET */ +static _fuzz_thread uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */ /** Get interface number from the interface descriptor * diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index 6a02959ca..c1a321a40 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -62,10 +62,10 @@ #endif /* --------------------- Fuzzing types -------------------------------------- */ -#ifdef FUZZ - #define TU_STATIC __thread static +#ifdef _FUZZ + #define _fuzz_thread __thread #else - #define TU_STATIC static + #define _fuzz_thread #endif // for declaration of reserved field, make use of _TU_COUNTER_ diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h index 8587b6771..e5f718f79 100644 --- a/src/common/tusb_debug.h +++ b/src/common/tusb_debug.h @@ -114,7 +114,7 @@ typedef struct static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key) { - TU_STATIC char not_found[11]; + static _fuzz_thread char not_found[11]; for(uint16_t i=0; icount; i++) { diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 56f782ca3..c4e131134 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -529,13 +529,13 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpo #if CFG_TUSB_DEBUG TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir) { - TU_STATIC const char *str[] = {"out", "in"}; + static _fuzz_thread const char *str[] = {"out", "in"}; return str[dir]; } TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t) { - TU_STATIC const char *str[] = {"control", "isochronous", "bulk", "interrupt"}; + static _fuzz_thread const char *str[] = {"control", "isochronous", "bulk", "interrupt"}; return str[t]; } #endif diff --git a/src/device/usbd.c b/src/device/usbd.c index 72fa2bd4c..3176239e7 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -76,7 +76,7 @@ typedef struct }usbd_device_t; -TU_STATIC usbd_device_t _usbd_dev; +static _fuzz_thread usbd_device_t _usbd_dev; //--------------------------------------------------------------------+ // Class Driver @@ -88,7 +88,7 @@ TU_STATIC usbd_device_t _usbd_dev; #endif // Built-in class drivers -TU_STATIC usbd_class_driver_t const _usbd_driver[] = +static _fuzz_thread usbd_class_driver_t const _usbd_driver[] = { #if CFG_TUD_CDC { @@ -238,8 +238,8 @@ TU_STATIC usbd_class_driver_t const _usbd_driver[] = enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) }; // Additional class drivers implemented by application -TU_STATIC usbd_class_driver_t const * _app_driver = NULL; -TU_STATIC uint8_t _app_driver_count = 0; +static _fuzz_thread usbd_class_driver_t const * _app_driver = NULL; +static _fuzz_thread uint8_t _app_driver_count = 0; // virtually joins built-in and application drivers together. // Application is positioned first to allow overwriting built-in ones. @@ -265,17 +265,17 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid) //--------------------------------------------------------------------+ enum { RHPORT_INVALID = 0xFFu }; -TU_STATIC uint8_t _usbd_rhport = RHPORT_INVALID; +static _fuzz_thread uint8_t _usbd_rhport = RHPORT_INVALID; // Event queue // usbd_int_set() is used as mutex in OS NONE config OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t); -TU_STATIC osal_queue_t _usbd_q; +static _fuzz_thread osal_queue_t _usbd_q; // Mutex for claiming endpoint #if OSAL_MUTEX_REQUIRED - TU_STATIC osal_mutex_def_t _ubsd_mutexdef; - TU_STATIC osal_mutex_t _usbd_mutex; + static _fuzz_thread osal_mutex_def_t _ubsd_mutexdef; + static _fuzz_thread osal_mutex_t _usbd_mutex; #else #define _usbd_mutex NULL #endif @@ -299,7 +299,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, // Debug //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= 2 -TU_STATIC char const* const _usbd_event_str[DCD_EVENT_COUNT] = +static _fuzz_thread char const* const _usbd_event_str[DCD_EVENT_COUNT] = { "Invalid" , "Bus Reset" , diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index c3ff7459d..8b071d9c6 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -53,10 +53,10 @@ typedef struct usbd_control_xfer_cb_t complete_cb; } usbd_control_xfer_t; -TU_STATIC usbd_control_xfer_t _ctrl_xfer; +static _fuzz_thread usbd_control_xfer_t _ctrl_xfer; CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN -TU_STATIC uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE]; +static _fuzz_thread uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE]; //--------------------------------------------------------------------+ // Application API diff --git a/test/fuzz/make.mk b/test/fuzz/make.mk index 5e8658ad0..e7c5518e7 100644 --- a/test/fuzz/make.mk +++ b/test/fuzz/make.mk @@ -79,7 +79,7 @@ CFLAGS += \ -Wno-error=unreachable-code \ -DOPT_MCU_FUZZ=1 \ -DCFG_TUSB_MCU=OPT_MCU_FUZZ \ - -DFUZZ + -D_FUZZ CXXFLAGS += \ -xc++ \ -- cgit v1.3.1 From 4c846af53e993d635e6fff7e2611a554b55fc441 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Feb 2023 16:18:45 +0700 Subject: rename OHCI_RHPORTS to TUP_OHCI_RHPORTS --- src/common/tusb_mcu.h | 2 +- src/portable/ohci/ohci.c | 17 ++++++++--------- src/portable/ohci/ohci.h | 6 +++--- 3 files changed, 12 insertions(+), 13 deletions(-) (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index ee2b896ac..a599c4fe9 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -55,7 +55,7 @@ #elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX) #define TUP_DCD_ENDPOINT_MAX 16 #define TUP_USBIP_OHCI - #define OHCI_RHPORTS 2 + #define TUP_OHCI_RHPORTS 2 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) // TODO USB0 has 6, USB1 has 4 diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 76f97844c..792ef65ff 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -28,8 +28,8 @@ #if CFG_TUH_ENABLED && defined(TUP_USBIP_OHCI) -#ifndef OHCI_RHPORTS -#error OHCI is enabled, but OHCI_RHPORTS is not defined. +#ifndef TUP_OHCI_RHPORTS +#error OHCI is enabled, but TUP_OHCI_RHPORTS is not defined. #endif //--------------------------------------------------------------------+ @@ -393,21 +393,20 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr) if (ed->dev_addr == dev_addr) { - //Prevent Host Controller from processing this ED while we remove it + // Prevent Host Controller from processing this ED while we remove it ed->skip = 1; - // unlink ed + // unlink ed, will also move up p_prev p_prev->next = ed->next; // point the removed ED's next pointer to list head to make sure HC can always safely move away from this ED ed->next = (uint32_t) _phys_addr(p_head); ed->used = 0; ed->skip = 0; - continue; + }else + { + p_prev = (ohci_ed_t*) _virt_addr((void *)p_prev->next); } - - // check next valid since we could remove it - if (p_prev->next) p_prev = (ohci_ed_t*) _virt_addr((void *)p_prev->next); } } @@ -665,7 +664,7 @@ void hcd_int_handler(uint8_t hostid) //------------- RootHub status -------------// if ( int_status & OHCI_INT_RHPORT_STATUS_CHANGE_MASK ) { - for (int i = 0; i < OHCI_RHPORTS; i++) + for (int i = 0; i < TUP_OHCI_RHPORTS; i++) { uint32_t const rhport_status = OHCI_REG->rhport_status[i] & RHPORT_ALL_CHANGE_MASK; if ( rhport_status & RHPORT_CONNECT_STATUS_CHANGE_MASK ) diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h index b7706b636..38c258e80 100644 --- a/src/portable/ohci/ohci.h +++ b/src/portable/ohci/ohci.h @@ -267,7 +267,7 @@ typedef volatile struct }; union { - uint32_t rhport_status[OHCI_RHPORTS]; + uint32_t rhport_status[TUP_OHCI_RHPORTS]; struct { uint32_t current_connect_status : 1; uint32_t port_enable_status : 1; @@ -284,11 +284,11 @@ typedef volatile struct uint32_t port_over_current_indicator_change : 1; uint32_t port_reset_status_change : 1; uint32_t TU_RESERVED : 11; - }rhport_status_bit[OHCI_RHPORTS]; + }rhport_status_bit[TUP_OHCI_RHPORTS]; }; }ohci_registers_t; -TU_VERIFY_STATIC( sizeof(ohci_registers_t) == (0x54 + (4 * OHCI_RHPORTS)), "size is not correct"); +TU_VERIFY_STATIC( sizeof(ohci_registers_t) == (0x54 + (4 * TUP_OHCI_RHPORTS)), "size is not correct"); #ifdef __cplusplus } -- cgit v1.3.1 From 498989ee009c388a770e7a312ae04d0a51ba745a Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Feb 2023 16:23:40 +0700 Subject: use tu_static instead of static _fuzz_thread --- src/class/cdc/cdc_device.c | 2 +- src/class/dfu/dfu_device.c | 14 +++++++------- src/class/hid/hid_device.c | 2 +- src/class/msc/msc_device.c | 8 ++++---- src/class/net/ecm_rndis_device.c | 14 +++++++------- src/class/net/ncm_device.c | 12 ++++++------ src/class/usbtmc/usbtmc_device.c | 8 ++++---- src/class/vendor/vendor_device.c | 2 +- src/class/video/video_device.c | 8 ++++---- src/common/tusb_compiler.h | 4 ++-- src/common/tusb_debug.h | 2 +- src/common/tusb_types.h | 4 ++-- src/device/usbd.c | 18 +++++++++--------- src/device/usbd_control.c | 4 ++-- test/fuzz/dcd_fuzz.cc | 2 +- test/fuzz/device/msc/src/usb_descriptors.cc | 4 ++-- test/fuzz/device/net/src/usb_descriptors.cc | 4 ++-- 17 files changed, 56 insertions(+), 56 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index 59ed2a74c..f372fe462 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -76,7 +76,7 @@ typedef struct //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION static _fuzz_thread cdcd_interface_t _cdcd_itf[CFG_TUD_CDC]; +CFG_TUSB_MEM_SECTION tu_static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC]; static bool _prep_out_transaction (cdcd_interface_t* p_cdc) { diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c index 9e7b8b5b1..464c4bd6b 100644 --- a/src/class/dfu/dfu_device.c +++ b/src/class/dfu/dfu_device.c @@ -56,7 +56,7 @@ typedef struct } dfu_state_ctx_t; // Only a single dfu state is allowed -CFG_TUSB_MEM_SECTION static _fuzz_thread dfu_state_ctx_t _dfu_ctx; +CFG_TUSB_MEM_SECTION tu_static dfu_state_ctx_t _dfu_ctx; static void reset_state(void) { @@ -74,7 +74,7 @@ static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, tusb_cont //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= 2 -static _fuzz_thread tu_lookup_entry_t const _dfu_request_lookup[] = +tu_static tu_lookup_entry_t const _dfu_request_lookup[] = { { .key = DFU_REQUEST_DETACH , .data = "DETACH" }, { .key = DFU_REQUEST_DNLOAD , .data = "DNLOAD" }, @@ -85,13 +85,13 @@ static _fuzz_thread tu_lookup_entry_t const _dfu_request_lookup[] = { .key = DFU_REQUEST_ABORT , .data = "ABORT" }, }; -static _fuzz_thread tu_lookup_table_t const _dfu_request_table = +tu_static tu_lookup_table_t const _dfu_request_table = { .count = TU_ARRAY_SIZE(_dfu_request_lookup), .items = _dfu_request_lookup }; -static _fuzz_thread tu_lookup_entry_t const _dfu_state_lookup[] = +tu_static tu_lookup_entry_t const _dfu_state_lookup[] = { { .key = APP_IDLE , .data = "APP_IDLE" }, { .key = APP_DETACH , .data = "APP_DETACH" }, @@ -106,13 +106,13 @@ static _fuzz_thread tu_lookup_entry_t const _dfu_state_lookup[] = { .key = DFU_ERROR , .data = "ERROR" }, }; -static _fuzz_thread tu_lookup_table_t const _dfu_state_table = +tu_static tu_lookup_table_t const _dfu_state_table = { .count = TU_ARRAY_SIZE(_dfu_state_lookup), .items = _dfu_state_lookup }; -static _fuzz_thread tu_lookup_entry_t const _dfu_status_lookup[] = +tu_static tu_lookup_entry_t const _dfu_status_lookup[] = { { .key = DFU_STATUS_OK , .data = "OK" }, { .key = DFU_STATUS_ERR_TARGET , .data = "errTARGET" }, @@ -132,7 +132,7 @@ static _fuzz_thread tu_lookup_entry_t const _dfu_status_lookup[] = { .key = DFU_STATUS_ERR_STALLEDPKT , .data = "errSTALLEDPKT" }, }; -static _fuzz_thread tu_lookup_table_t const _dfu_status_table = +tu_static tu_lookup_table_t const _dfu_status_table = { .count = TU_ARRAY_SIZE(_dfu_status_lookup), .items = _dfu_status_lookup diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c index 6fae5862d..ef44585f9 100644 --- a/src/class/hid/hid_device.c +++ b/src/class/hid/hid_device.c @@ -58,7 +58,7 @@ typedef struct tusb_hid_descriptor_hid_t const * hid_descriptor; } hidd_interface_t; -CFG_TUSB_MEM_SECTION static _fuzz_thread hidd_interface_t _hidd_itf[CFG_TUD_HID]; +CFG_TUSB_MEM_SECTION tu_static hidd_interface_t _hidd_itf[CFG_TUD_HID]; /*------------- Helpers -------------*/ static inline uint8_t get_index_by_itfnum(uint8_t itf_num) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index e77342777..d3c8124df 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -71,8 +71,8 @@ typedef struct uint8_t add_sense_qualifier; }mscd_interface_t; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread mscd_interface_t _mscd_itf; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE]; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static mscd_interface_t _mscd_itf; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE]; //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION @@ -202,7 +202,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= 2 -TU_ATTR_UNUSED static _fuzz_thread tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = +TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = { { .key = SCSI_CMD_TEST_UNIT_READY , .data = "Test Unit Ready" }, { .key = SCSI_CMD_INQUIRY , .data = "Inquiry" }, @@ -217,7 +217,7 @@ TU_ATTR_UNUSED static _fuzz_thread tu_lookup_entry_t const _msc_scsi_cmd_lookup[ { .key = SCSI_CMD_WRITE_10 , .data = "Write10" } }; -TU_ATTR_UNUSED static _fuzz_thread tu_lookup_table_t const _msc_scsi_cmd_table = +TU_ATTR_UNUSED tu_static tu_lookup_table_t const _msc_scsi_cmd_table = { .count = TU_ARRAY_SIZE(_msc_scsi_cmd_lookup), .items = _msc_scsi_cmd_lookup diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c index e2a57cb50..a072bfd79 100644 --- a/src/class/net/ecm_rndis_device.c +++ b/src/class/net/ecm_rndis_device.c @@ -61,10 +61,10 @@ typedef struct #define CFG_TUD_NET_PACKET_PREFIX_LEN sizeof(rndis_data_packet_t) #define CFG_TUD_NET_PACKET_SUFFIX_LEN 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; struct ecm_notify_struct @@ -73,7 +73,7 @@ struct ecm_notify_struct uint32_t downlink, uplink; }; -static _fuzz_thread const struct ecm_notify_struct ecm_notify_nc = +tu_static const struct ecm_notify_struct ecm_notify_nc = { .header = { .bmRequestType = 0xA1, @@ -83,7 +83,7 @@ static _fuzz_thread const struct ecm_notify_struct ecm_notify_nc = }, }; -static _fuzz_thread const struct ecm_notify_struct ecm_notify_csc = +tu_static const struct ecm_notify_struct ecm_notify_csc = { .header = { .bmRequestType = 0xA1, @@ -95,7 +95,7 @@ static _fuzz_thread const struct ecm_notify_struct ecm_notify_csc = }; // TODO remove CFG_TUSB_MEM_SECTION, control internal buffer is already in this special section -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread union +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static union { uint8_t rndis_buf[120]; struct ecm_notify_struct ecm_buf; @@ -105,9 +105,9 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread union // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ // TODO remove CFG_TUSB_MEM_SECTION -CFG_TUSB_MEM_SECTION static _fuzz_thread netd_interface_t _netd_itf; +CFG_TUSB_MEM_SECTION tu_static netd_interface_t _netd_itf; -static _fuzz_thread bool can_xmit; +tu_static bool can_xmit; void tud_network_recv_renew(void) { diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c index b8a5c6d3a..aa13c9535 100644 --- a/src/class/net/ncm_device.c +++ b/src/class/net/ncm_device.c @@ -130,7 +130,7 @@ typedef struct // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread const ntb_parameters_t ntb_parameters = { +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_parameters = { .wLength = sizeof(ntb_parameters_t), .bmNtbFormatsSupported = 0x01, .dwNtbInMaxSize = CFG_TUD_NCM_IN_NTB_MAX_SIZE, @@ -145,11 +145,11 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread const ntb_parameters .wNtbOutMaxDatagrams = 0 }; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread transmit_ntb_t transmit_ntb[2]; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static transmit_ntb_t transmit_ntb[2]; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE]; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE]; -static _fuzz_thread ncm_interface_t ncm_interface; +tu_static ncm_interface_t ncm_interface; /* * Set up the NTB state in ncm_interface to be ready to add datagrams. @@ -196,7 +196,7 @@ static void ncm_start_tx(void) { ncm_prepare_for_tx(); } -static _fuzz_thread struct ecm_notify_struct ncm_notify_connected = +tu_static struct ecm_notify_struct ncm_notify_connected = { .header = { .bmRequestType_bit = { @@ -210,7 +210,7 @@ static _fuzz_thread struct ecm_notify_struct ncm_notify_connected = }, }; -static _fuzz_thread struct ecm_notify_struct ncm_notify_speed_change = +tu_static struct ecm_notify_struct ncm_notify_speed_change = { .header = { .bmRequestType_bit = { diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index 416cb9bb9..a4e6eaeb3 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -78,7 +78,7 @@ #ifdef xDEBUG #include "uart_util.h" -static _fuzz_thread char logMsg[150]; +tu_static char logMsg[150]; #endif // Buffer size must be an exact multiple of the max packet size for both @@ -143,7 +143,7 @@ typedef struct usbtmc_capabilities_specific_t const * capabilities; } usbtmc_interface_state_t; -CFG_TUSB_MEM_SECTION static _fuzz_thread usbtmc_interface_state_t usbtmc_state = +CFG_TUSB_MEM_SECTION tu_static usbtmc_interface_state_t usbtmc_state = { .itf_id = 0xFF, }; @@ -154,8 +154,8 @@ TU_VERIFY_STATIC(USBTMCD_BUFFER_SIZE >= 32u,"USBTMC dev buffer size too small"); static bool handle_devMsgOutStart(uint8_t rhport, void *data, size_t len); static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t packetLen); -static _fuzz_thread uint8_t termChar; -static _fuzz_thread uint8_t termCharRequested = false; +tu_static uint8_t termChar; +tu_static uint8_t termCharRequested = false; #if OSAL_MUTEX_REQUIRED static OSAL_MUTEX_DEF(usbtmcLockBuffer); diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index 22124d193..d07bd75ec 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -59,7 +59,7 @@ typedef struct CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_VENDOR_EPSIZE]; } vendord_interface_t; -CFG_TUSB_MEM_SECTION static _fuzz_thread vendord_interface_t _vendord_itf[CFG_TUD_VENDOR]; +CFG_TUSB_MEM_SECTION tu_static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR]; #define ITF_MEM_RESET_SIZE offsetof(vendord_interface_t, rx_ff) diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index ecee73d51..02a490aee 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -125,11 +125,11 @@ typedef struct TU_ATTR_PACKED { //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION static _fuzz_thread videod_interface_t _videod_itf[CFG_TUD_VIDEO]; -CFG_TUSB_MEM_SECTION static _fuzz_thread videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING]; +CFG_TUSB_MEM_SECTION tu_static videod_interface_t _videod_itf[CFG_TUD_VIDEO]; +CFG_TUSB_MEM_SECTION tu_static videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING]; -static _fuzz_thread uint8_t const _cap_get = 0x1u; /* support for GET */ -static _fuzz_thread uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */ +tu_static uint8_t const _cap_get = 0x1u; /* support for GET */ +tu_static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */ /** Get interface number from the interface descriptor * diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index 3eb6b41f7..30478ba6d 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -63,9 +63,9 @@ /* --------------------- Fuzzing types -------------------------------------- */ #ifdef _FUZZ - #define _fuzz_thread __thread + #define tu_static static __thread #else - #define _fuzz_thread + #define tu_static static #endif // for declaration of reserved field, make use of _TU_COUNTER_ diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h index e5f718f79..82f682043 100644 --- a/src/common/tusb_debug.h +++ b/src/common/tusb_debug.h @@ -114,7 +114,7 @@ typedef struct static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key) { - static _fuzz_thread char not_found[11]; + tu_static char not_found[11]; for(uint16_t i=0; icount; i++) { diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 14d4365a0..7266a525e 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -529,13 +529,13 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpo #if CFG_TUSB_DEBUG TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir) { - static _fuzz_thread const char *str[] = {"out", "in"}; + tu_static const char *str[] = {"out", "in"}; return str[dir]; } TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t) { - static _fuzz_thread const char *str[] = {"control", "isochronous", "bulk", "interrupt"}; + tu_static const char *str[] = {"control", "isochronous", "bulk", "interrupt"}; return str[t]; } #endif diff --git a/src/device/usbd.c b/src/device/usbd.c index 3176239e7..384daccb8 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -76,7 +76,7 @@ typedef struct }usbd_device_t; -static _fuzz_thread usbd_device_t _usbd_dev; +tu_static usbd_device_t _usbd_dev; //--------------------------------------------------------------------+ // Class Driver @@ -88,7 +88,7 @@ static _fuzz_thread usbd_device_t _usbd_dev; #endif // Built-in class drivers -static _fuzz_thread usbd_class_driver_t const _usbd_driver[] = +tu_static usbd_class_driver_t const _usbd_driver[] = { #if CFG_TUD_CDC { @@ -238,8 +238,8 @@ static _fuzz_thread usbd_class_driver_t const _usbd_driver[] = enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) }; // Additional class drivers implemented by application -static _fuzz_thread usbd_class_driver_t const * _app_driver = NULL; -static _fuzz_thread uint8_t _app_driver_count = 0; +tu_static usbd_class_driver_t const * _app_driver = NULL; +tu_static uint8_t _app_driver_count = 0; // virtually joins built-in and application drivers together. // Application is positioned first to allow overwriting built-in ones. @@ -265,17 +265,17 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid) //--------------------------------------------------------------------+ enum { RHPORT_INVALID = 0xFFu }; -static _fuzz_thread uint8_t _usbd_rhport = RHPORT_INVALID; +tu_static uint8_t _usbd_rhport = RHPORT_INVALID; // Event queue // usbd_int_set() is used as mutex in OS NONE config OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t); -static _fuzz_thread osal_queue_t _usbd_q; +tu_static osal_queue_t _usbd_q; // Mutex for claiming endpoint #if OSAL_MUTEX_REQUIRED - static _fuzz_thread osal_mutex_def_t _ubsd_mutexdef; - static _fuzz_thread osal_mutex_t _usbd_mutex; + tu_static osal_mutex_def_t _ubsd_mutexdef; + tu_static osal_mutex_t _usbd_mutex; #else #define _usbd_mutex NULL #endif @@ -299,7 +299,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, // Debug //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= 2 -static _fuzz_thread char const* const _usbd_event_str[DCD_EVENT_COUNT] = +tu_static char const* const _usbd_event_str[DCD_EVENT_COUNT] = { "Invalid" , "Bus Reset" , diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index 8b071d9c6..e709658b9 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -53,10 +53,10 @@ typedef struct usbd_control_xfer_cb_t complete_cb; } usbd_control_xfer_t; -static _fuzz_thread usbd_control_xfer_t _ctrl_xfer; +tu_static usbd_control_xfer_t _ctrl_xfer; CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN -static _fuzz_thread uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE]; +tu_static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE]; //--------------------------------------------------------------------+ // Application API diff --git a/test/fuzz/dcd_fuzz.cc b/test/fuzz/dcd_fuzz.cc index 294977269..6403015dd 100644 --- a/test/fuzz/dcd_fuzz.cc +++ b/test/fuzz/dcd_fuzz.cc @@ -39,7 +39,7 @@ struct State { uint8_t address; }; -static _fuzz_thread State state = {false, 0, 0}; +tu_static State state = {false, 0, 0}; //--------------------------------------------------------------------+ // Controller API diff --git a/test/fuzz/device/msc/src/usb_descriptors.cc b/test/fuzz/device/msc/src/usb_descriptors.cc index 8f4be9655..efe4d0a3c 100644 --- a/test/fuzz/device/msc/src/usb_descriptors.cc +++ b/test/fuzz/device/msc/src/usb_descriptors.cc @@ -44,7 +44,7 @@ // Invoked when received GET DEVICE DESCRIPTOR // Application return pointer to descriptor uint8_t const *tud_descriptor_device_cb(void) { - static _fuzz_thread tusb_desc_device_t const desc_device = { + tu_static tusb_desc_device_t const desc_device = { .bLength = sizeof(tusb_desc_device_t), .bDescriptorType = TUSB_DESC_DEVICE, .bcdUSB = USB_BCD, @@ -184,7 +184,7 @@ char const *string_desc_arr[] = { }; -static _fuzz_thread uint16_t _desc_str[32]; +tu_static uint16_t _desc_str[32]; // Invoked when received GET STRING DESCRIPTOR request // Application return pointer to descriptor, whose contents must exist long diff --git a/test/fuzz/device/net/src/usb_descriptors.cc b/test/fuzz/device/net/src/usb_descriptors.cc index 903d49271..5597d49d5 100644 --- a/test/fuzz/device/net/src/usb_descriptors.cc +++ b/test/fuzz/device/net/src/usb_descriptors.cc @@ -45,7 +45,7 @@ // Invoked when received GET DEVICE DESCRIPTOR // Application return pointer to descriptor uint8_t const *tud_descriptor_device_cb(void) { - static _fuzz_thread tusb_desc_device_t const desc_device = { + tu_static tusb_desc_device_t const desc_device = { .bLength = sizeof(tusb_desc_device_t), .bDescriptorType = TUSB_DESC_DEVICE, .bcdUSB = USB_BCD, @@ -189,7 +189,7 @@ char const *string_desc_arr[] = { "TinyUSB CDC", // 4: CDC Interface }; -static _fuzz_thread uint16_t _desc_str[32]; +tu_static uint16_t _desc_str[32]; // Invoked when received GET STRING DESCRIPTOR request // Application return pointer to descriptor, whose contents must exist long -- cgit v1.3.1 From 302b9562dc6963fcb3f85571cb515f322f6d2226 Mon Sep 17 00:00:00 2001 From: mikee47 Date: Wed, 22 Feb 2023 09:58:30 +0000 Subject: MIDI_CIN_NOTE_ON definition transposed with MIDI_CIN_NOTE_OFF --- src/class/midi/midi.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/midi/midi.h b/src/class/midi/midi.h index 74dc41749..57875b1e4 100644 --- a/src/class/midi/midi.h +++ b/src/class/midi/midi.h @@ -71,8 +71,8 @@ typedef enum MIDI_CIN_SYSEX_END_1BYTE = 5, // SysEx ends with 1 data, or 1 byte system common message MIDI_CIN_SYSEX_END_2BYTE = 6, // SysEx ends with 2 data MIDI_CIN_SYSEX_END_3BYTE = 7, // SysEx ends with 3 data - MIDI_CIN_NOTE_ON = 8, - MIDI_CIN_NOTE_OFF = 9, + MIDI_CIN_NOTE_OFF = 8, + MIDI_CIN_NOTE_ON = 9, MIDI_CIN_POLY_KEYPRESS = 10, MIDI_CIN_CONTROL_CHANGE = 11, MIDI_CIN_PROGRAM_CHANGE = 12, -- cgit v1.3.1 From 1466afafeb927621f9cbb6efd2a0d7e4b6cf8d41 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Feb 2023 22:14:50 +0700 Subject: move and add optional tusb_app_virt_to_phys/tusb_app_phys_to_virt also add place holder for tusb_app_dcache_flush() and tusb_app_dcache_invalidate() --- src/common/tusb_common.h | 15 +++++++++++++++ src/common/tusb_mcu.h | 4 ++-- src/host/hcd.h | 2 +- src/osal/osal_none.h | 4 ++++ src/portable/ohci/ohci.c | 21 +++++++++++++-------- src/portable/ohci/ohci.h | 4 +++- 6 files changed, 38 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index b1ee40a1a..270339cca 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -75,6 +75,21 @@ #include "tusb_timeout.h" // TODO remove +//--------------------------------------------------------------------+ +// Optional API implemented by application if needed +// TODO move to a more ovious place/file +//--------------------------------------------------------------------+ + +// flush data cache +TU_ATTR_WEAK extern void tusb_app_dcache_flush(uintptr_t addr, uint32_t data_size); + +// invalidate data cache +TU_ATTR_WEAK extern void tusb_app_dcache_invalidate(uintptr_t addr, uint32_t data_size); + +// Optional physical <-> virtual address translation +TU_ATTR_WEAK extern void* tusb_app_virt_to_phys(void *virt_addr); +TU_ATTR_WEAK extern void* tusb_app_phys_to_virt(void *phys_addr); + //--------------------------------------------------------------------+ // Internal Inline Functions //--------------------------------------------------------------------+ diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index a599c4fe9..e7d4e2c32 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -28,8 +28,8 @@ #define TUSB_MCU_H_ //--------------------------------------------------------------------+ -// Port Specific -// TUP stand for TinyUSB Port (can be renamed) +// Port/Platform Specific +// TUP stand for TinyUSB Port/Platform (can be renamed) //--------------------------------------------------------------------+ //------------- Unaligned Memory Access -------------// diff --git a/src/host/hcd.h b/src/host/hcd.h index deebc59d4..a400626e4 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -106,7 +106,7 @@ typedef struct // Controller API //--------------------------------------------------------------------+ -// optional hcd configuration, called by tuh_config() +// optional hcd configuration, called by tuh_configure() bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) TU_ATTR_WEAK; // Initialize controller to host mode diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h index 1ad130557..2e2b3c7ce 100644 --- a/src/osal/osal_none.h +++ b/src/osal/osal_none.h @@ -35,6 +35,10 @@ // TASK API //--------------------------------------------------------------------+ +#if CFG_TUH_ENABLED +// currently only needed/available in host mode +void osal_task_delay(uint32_t msec); +#endif //--------------------------------------------------------------------+ // Binary Semaphore API diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 792ef65ff..339f8e896 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -162,18 +162,16 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr); // USBH-HCD API //--------------------------------------------------------------------+ -//If your system requires separation of virtual and physical memory, implement -//tuh_get_phys_addr and tuh_get_virt_addr in your application. -TU_ATTR_WEAK void *tuh_get_phys_addr(void *virtual_address); -TU_ATTR_WEAK void *tuh_get_virt_addr(void *physical_address); -TU_ATTR_ALWAYS_INLINE static void *_phys_addr(void *virtual_address) +// If your system requires separation of virtual and physical memory, implement +// tusb_app_virt_to_phys and tusb_app_virt_to_phys in your application. +TU_ATTR_ALWAYS_INLINE static inline void *_phys_addr(void *virtual_address) { - if (tuh_get_phys_addr) return tuh_get_phys_addr(virtual_address); + if (tusb_app_virt_to_phys) return tusb_app_virt_to_phys(virtual_address); return virtual_address; } -TU_ATTR_ALWAYS_INLINE static void *_virt_addr(void *physical_address) +TU_ATTR_ALWAYS_INLINE static inline void *_virt_addr(void *physical_address) { - if (tuh_get_virt_addr) return tuh_get_virt_addr(physical_address); + if (tusb_app_phys_to_virt) return tusb_app_phys_to_virt(physical_address); return physical_address; } @@ -206,7 +204,13 @@ bool hcd_init(uint8_t rhport) { //Wait 20 ms. (Ref Usb spec 7.1.7.7) OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_RESUME; + +#if CFG_TUSB_OS != OPT_OS_NONE + // os_none implement task delay using usb frame counter which is not started yet + // therefore cause infinite delay. + // TODO find a way to delay in case of os none e.g __nop osal_task_delay(20); +#endif } // reset controller @@ -233,6 +237,7 @@ bool hcd_init(uint8_t rhport) OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_OPERATIONAL; // make HC's state to operational state TODO use this to suspend (save power) OHCI_REG->rh_status_bit.local_power_status_change = 1; // set global power for ports + osal_task_delay(OHCI_REG->rh_descriptorA_bit.power_on_to_good_time * 2); // Wait POTG after power up return true; diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h index 38c258e80..2081ffabb 100644 --- a/src/portable/ohci/ohci.h +++ b/src/portable/ohci/ohci.h @@ -58,7 +58,9 @@ typedef struct { TU_VERIFY_STATIC( sizeof(ohci_hcca_t) == 256, "size is not correct" ); -typedef struct { +// common link item for gtd and itd for list travel +// use as pointer only +typedef struct TU_ATTR_ALIGNED(16) { uint32_t reserved[2]; volatile uint32_t next; uint32_t reserved2; -- cgit v1.3.1 From 4caa6063b092de2a9efadb6a4ac247543662731f Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Feb 2023 22:17:45 +0700 Subject: white space --- src/common/tusb_mcu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index e7d4e2c32..1f27afa4e 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -55,7 +55,7 @@ #elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX) #define TUP_DCD_ENDPOINT_MAX 16 #define TUP_USBIP_OHCI - #define TUP_OHCI_RHPORTS 2 + #define TUP_OHCI_RHPORTS 2 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) // TODO USB0 has 6, USB1 has 4 -- cgit v1.3.1 From eca96c635da52ab516e3dda47348ef8977ffd8ad Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Feb 2023 22:28:22 +0700 Subject: comment out osal_task_delay if using os none --- src/portable/ohci/ohci.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 339f8e896..b615743b8 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -169,6 +169,7 @@ TU_ATTR_ALWAYS_INLINE static inline void *_phys_addr(void *virtual_address) if (tusb_app_virt_to_phys) return tusb_app_virt_to_phys(virtual_address); return virtual_address; } + TU_ATTR_ALWAYS_INLINE static inline void *_virt_addr(void *physical_address) { if (tusb_app_phys_to_virt) return tusb_app_phys_to_virt(physical_address); @@ -238,7 +239,10 @@ bool hcd_init(uint8_t rhport) OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_OPERATIONAL; // make HC's state to operational state TODO use this to suspend (save power) OHCI_REG->rh_status_bit.local_power_status_change = 1; // set global power for ports +#if CFG_TUSB_OS != OPT_OS_NONE + // TODO as above delay osal_task_delay(OHCI_REG->rh_descriptorA_bit.power_on_to_good_time * 2); // Wait POTG after power up +#endif return true; } -- cgit v1.3.1 From e34aeb5cf69315d2d7711f0a1d040a28492d026d Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 27 Feb 2023 09:11:35 +0700 Subject: minor clean up --- src/class/audio/audio_device.c | 2 +- src/class/hid/hid_device.c | 6 +++--- src/class/midi/midi_device.c | 2 +- src/class/msc/msc_device.c | 10 +++++----- src/common/tusb_common.h | 21 ++++++++++++++++++--- src/device/usbd_control.c | 2 +- src/tusb.c | 21 --------------------- 7 files changed, 29 insertions(+), 35 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 81df95139..de5a20d6d 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -2199,7 +2199,7 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req if (len > _audiod_fct[func_id].ctrl_buf_sz) len = _audiod_fct[func_id].ctrl_buf_sz; // Copy into buffer - TU_VERIFY(tu_memcpy_s(_audiod_fct[func_id].ctrl_buf, sizeof(_audiod_fct[func_id].ctrl_buf), data, (size_t)len)==0); + TU_VERIFY(0 == tu_memcpy_s(_audiod_fct[func_id].ctrl_buf, sizeof(_audiod_fct[func_id].ctrl_buf), data, (size_t)len)); // Schedule transmit return tud_control_xfer(rhport, p_request, (void*)_audiod_fct[func_id].ctrl_buf, len); diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c index 40654eef9..37a22b609 100644 --- a/src/class/hid/hid_device.c +++ b/src/class/hid/hid_device.c @@ -93,11 +93,11 @@ bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, u if (report_id) { p_hid->epin_buf[0] = report_id; - TU_VERIFY(tu_memcpy_s(p_hid->epin_buf+1, CFG_TUD_HID_EP_BUFSIZE-1, report, len)==0); + TU_VERIFY(0 == tu_memcpy_s(p_hid->epin_buf+1, CFG_TUD_HID_EP_BUFSIZE-1, report, len)); len++; }else { - TU_VERIFY(tu_memcpy_s(p_hid->epin_buf, CFG_TUD_HID_EP_BUFSIZE, report, len)==0); + TU_VERIFY(0 == tu_memcpy_s(p_hid->epin_buf, CFG_TUD_HID_EP_BUFSIZE, report, len)); } return usbd_edpt_xfer(rhport, p_hid->ep_in, p_hid->epin_buf, len); @@ -122,7 +122,7 @@ bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modi if ( keycode ) { - TU_VERIFY(tu_memcpy_s(report.keycode, sizeof(report.keycode), keycode, sizeof(report.keycode))==0); + memcpy(report.keycode, keycode, sizeof(report.keycode)); }else { tu_memclr(report.keycode, 6); diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c index 0b52be181..92689dfb0 100644 --- a/src/class/midi/midi_device.c +++ b/src/class/midi/midi_device.c @@ -182,7 +182,7 @@ uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void* buffer, ui uint8_t const count = (uint8_t) tu_min32(stream->total - stream->index, bufsize); // Skip the header (1st byte) in the buffer - TU_VERIFY(tu_memcpy_s(buf8, bufsize, stream->buffer + 1 + stream->index, count)==0); + TU_VERIFY(0 == tu_memcpy_s(buf8, bufsize, stream->buffer + 1 + stream->index, count)); total_read += count; stream->index += count; diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index ed4a3e86c..ecc95377f 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -707,7 +707,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ read_capa10.block_size = tu_htonl(block_size); resplen = sizeof(read_capa10); - TU_VERIFY(tu_memcpy_s(buffer, bufsize, &read_capa10, (size_t) resplen)); + TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &read_capa10, (size_t) resplen)); } } break; @@ -741,7 +741,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ read_fmt_capa.block_size_u16 = tu_htons(block_size); resplen = sizeof(read_fmt_capa); - TU_VERIFY(tu_memcpy_s(buffer, bufsize, &read_fmt_capa, (size_t) resplen)==0); + TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &read_fmt_capa, (size_t) resplen)); } } break; @@ -764,7 +764,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ tud_msc_inquiry_cb(lun, inquiry_rsp.vendor_id, inquiry_rsp.product_id, inquiry_rsp.product_rev); resplen = sizeof(inquiry_rsp); - TU_VERIFY(tu_memcpy_s(buffer, bufsize, &inquiry_rsp, (size_t) resplen)==0); + TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &inquiry_rsp, (size_t) resplen)); } break; @@ -788,7 +788,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ mode_resp.write_protected = !writable; resplen = sizeof(mode_resp); - TU_VERIFY(tu_memcpy_s(buffer, bufsize, &mode_resp, (size_t) resplen)==0); + TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &mode_resp, (size_t) resplen)); } break; @@ -806,7 +806,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ sense_rsp.add_sense_qualifier = p_msc->add_sense_qualifier; resplen = sizeof(sense_rsp); - TU_VERIFY(tu_memcpy_s(buffer, bufsize, &sense_rsp, (size_t) resplen)==0); + TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &sense_rsp, (size_t) resplen)); // request sense callback could overwrite the sense data if (tud_msc_request_sense_cb) diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 78fdcfe36..3e5e1d427 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -84,11 +84,26 @@ #define tu_varclr(_var) tu_memclr(_var, sizeof(*(_var))) // This is a backport of memset_s from c11 -int32_t tu_memset_s(void *dest, size_t destsz, int ch, size_t count); +TU_ATTR_ALWAYS_INLINE static inline int tu_memset_s(void *dest, size_t destsz, int ch, size_t count) +{ + // TODO may check if desst and src is not NULL + if (count > destsz) { + return -1; + } + memset(dest, ch, count); + return 0; +} // This is a backport of memcpy_s from c11 -int32_t tu_memcpy_s(void *dest, size_t destsz, - const void * src, size_t count ); +TU_ATTR_ALWAYS_INLINE static inline int tu_memcpy_s(void *dest, size_t destsz, const void * src, size_t count ) +{ + // TODO may check if desst and src is not NULL + if (count > destsz) { + return -1; + } + memcpy(dest, src, count); + return 0; +} //------------- Bytes -------------// diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index ce4ddab66..b8a200845 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -94,7 +94,7 @@ static bool _data_stage_xact(uint8_t rhport) { ep_addr = EDPT_CTRL_IN; if ( xact_len ) { - TU_VERIFY(tu_memcpy_s(_usbd_ctrl_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)==0); + TU_VERIFY(0 == tu_memcpy_s(_usbd_ctrl_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)); } } diff --git a/src/tusb.c b/src/tusb.c index c918b0248..8318e5275 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -24,7 +24,6 @@ * This file is part of the TinyUSB stack. */ -#include "common/tusb_common.h" #include "tusb_option.h" #if CFG_TUH_ENABLED || CFG_TUD_ENABLED @@ -487,23 +486,3 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent) #endif #endif // host or device enabled - -//--------------------------------------------------------------------+ -// Common -//--------------------------------------------------------------------+ - -int32_t tu_memset_s(void *dest, size_t destsz, int ch, size_t count) { - if (count > destsz) { - return -1; - } - memset(dest, ch, count); - return 0; -} - -int32_t tu_memcpy_s(void *dest, size_t destsz, const void *src, size_t count) { - if (count > destsz) { - return -1; - } - memcpy(dest, src, count); - return 0; -} \ No newline at end of file -- cgit v1.3.1 From 4c510c12b1d0a0bfb0726c0100ff22cd892aa1e8 Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Mon, 27 Feb 2023 09:54:45 +0100 Subject: synopsys/dwc2: fix SOF interrupt handling SOF is not a flag of the GOTGINT register but of the GINTSTS register. Therefore the flag must be written in the GINTSTS register instead of the GOTGINT register to clear the interrupt. --- src/portable/synopsys/dwc2/dcd_dwc2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index c6132a1f5..7d4f31c48 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -1288,7 +1288,7 @@ void dcd_int_handler(uint8_t rhport) if(int_status & GINTSTS_SOF) { - dwc2->gotgint = GINTSTS_SOF; + dwc2->gintsts = GINTSTS_SOF; if (_sof_en) { -- cgit v1.3.1 From ffdc100cb90eefd13da77a478527ea25d982416c Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 28 Feb 2023 17:11:59 +0700 Subject: rename ep_num to ep_idx, minor clean up --- src/class/audio/audio_device.c | 105 +++++++------- src/device/usbd.c | 20 +-- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 153 ++++++++++++--------- .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 151 ++++++++++---------- 4 files changed, 223 insertions(+), 206 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 31c4783eb..ee26eddf5 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -1495,17 +1495,19 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin } #if USE_ISO_EP_ALLOCATION -#if CFG_TUD_AUDIO_ENABLE_EP_IN + #if CFG_TUD_AUDIO_ENABLE_EP_IN uint8_t ep_in = 0; uint16_t ep_in_size = 0; -#endif -#if CFG_TUD_AUDIO_ENABLE_EP_OUT + #endif + + #if CFG_TUD_AUDIO_ENABLE_EP_OUT uint8_t ep_out = 0; uint16_t ep_out_size = 0; -#endif -#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP + #endif + + #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP uint8_t ep_fb = 0; -#endif + #endif uint8_t const *p_desc = _audiod_fct[i].p_desc; uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN; @@ -1516,28 +1518,28 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc; if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) { -#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP + #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP // Explicit feedback EP if (desc_ep->bmAttributes.usage == 1) { ep_fb = desc_ep->bEndpointAddress; } -#endif + #endif // Data EP if (desc_ep->bmAttributes.usage == 0) { if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { -#if CFG_TUD_AUDIO_ENABLE_EP_IN + #if CFG_TUD_AUDIO_ENABLE_EP_IN ep_in = desc_ep->bEndpointAddress; ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size); -#endif + #endif } else { -#if CFG_TUD_AUDIO_ENABLE_EP_OUT + #if CFG_TUD_AUDIO_ENABLE_EP_OUT ep_out = desc_ep->bEndpointAddress; ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size); -#endif + #endif } } @@ -1546,26 +1548,28 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin p_desc = tu_desc_next(p_desc); } -#if CFG_TUD_AUDIO_ENABLE_EP_IN + #if CFG_TUD_AUDIO_ENABLE_EP_IN if (ep_in) { usbd_edpt_iso_alloc(rhport, ep_in, ep_in_size); } -#endif -#if CFG_TUD_AUDIO_ENABLE_EP_OUT + #endif + + #if CFG_TUD_AUDIO_ENABLE_EP_OUT if (ep_out) { usbd_edpt_iso_alloc(rhport, ep_out, ep_out_size); } -#endif -#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP + #endif + + #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP if (ep_fb) { usbd_edpt_iso_alloc(rhport, ep_fb, 4); } -#endif + #endif -#endif +#endif // USE_ISO_EP_ALLOCATION break; } @@ -1628,18 +1632,19 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * if (audio->ep_in_as_intf_num == itf) { audio->ep_in_as_intf_num = 0; -#if !USE_ISO_EP_ALLOCATION + #if !USE_ISO_EP_ALLOCATION usbd_edpt_close(rhport, audio->ep_in); -#endif + #endif + // Clear FIFOs, since data is no longer valid -#if !CFG_TUD_AUDIO_ENABLE_ENCODING + #if !CFG_TUD_AUDIO_ENABLE_ENCODING tu_fifo_clear(&audio->ep_in_ff); -#else + #else for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++) { tu_fifo_clear(&audio->tx_supp_ff[cnt]); } -#endif + #endif // Invoke callback - can be used to stop data sampling if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request)); @@ -1647,24 +1652,25 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * audio->ep_in = 0; // Necessary? } -#endif +#endif // CFG_TUD_AUDIO_ENABLE_EP_IN #if CFG_TUD_AUDIO_ENABLE_EP_OUT if (audio->ep_out_as_intf_num == itf) { audio->ep_out_as_intf_num = 0; -#if !USE_ISO_EP_ALLOCATION + #if !USE_ISO_EP_ALLOCATION usbd_edpt_close(rhport, audio->ep_out); -#endif + #endif + // Clear FIFOs, since data is no longer valid -#if !CFG_TUD_AUDIO_ENABLE_DECODING + #if !CFG_TUD_AUDIO_ENABLE_DECODING tu_fifo_clear(&audio->ep_out_ff); -#else + #else for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++) { tu_fifo_clear(&audio->rx_supp_ff[cnt]); } -#endif + #endif // Invoke callback - can be used to stop data sampling if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request)); @@ -1672,15 +1678,15 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * audio->ep_out = 0; // Necessary? // Close corresponding feedback EP -#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP -#if !USE_ISO_EP_ALLOCATION + #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP + #if !USE_ISO_EP_ALLOCATION usbd_edpt_close(rhport, audio->ep_fb); -#endif + #endif audio->ep_fb = 0; tu_memclr(&audio->feedback, sizeof(audio->feedback)); -#endif + #endif } -#endif +#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT // Save current alternative interface setting audio->alt_setting[idxItf] = alt; @@ -1724,11 +1730,11 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * audio->ep_in_sz = tu_edpt_packet_size(desc_ep); // If software encoding is enabled, parse for the corresponding parameters - doing this here means only AS interfaces with EPs get scanned for parameters -#if CFG_TUD_AUDIO_ENABLE_ENCODING + #if CFG_TUD_AUDIO_ENABLE_ENCODING audiod_parse_for_AS_params(audio, p_desc_parse_for_params, p_desc_end, itf); // Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap -#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING + #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING const uint16_t active_fifo_depth = (uint16_t) ((audio->tx_supp_ff_sz_max / audio->n_bytes_per_sampe_tx) * audio->n_bytes_per_sampe_tx); for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++) { @@ -1736,9 +1742,8 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * } audio->n_ff_used_tx = audio->n_channels_tx / audio->n_channels_per_ff_tx; TU_ASSERT( audio->n_ff_used_tx <= audio->n_tx_supp_ff ); -#endif - -#endif + #endif + #endif // Schedule first transmit if alternate interface is not zero i.e. streaming is disabled - in case no sample data is available a ZLP is loaded // It is necessary to trigger this here since the refill is done with an RX FIFO empty interrupt which can only trigger if something was in there @@ -1755,11 +1760,11 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * audio->ep_out_as_intf_num = itf; audio->ep_out_sz = tu_edpt_packet_size(desc_ep); -#if CFG_TUD_AUDIO_ENABLE_DECODING + #if CFG_TUD_AUDIO_ENABLE_DECODING audiod_parse_for_AS_params(audio, p_desc_parse_for_params, p_desc_end, itf); // Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap -#if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING + #if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING const uint16_t active_fifo_depth = (audio->rx_supp_ff_sz_max / audio->n_bytes_per_sampe_rx) * audio->n_bytes_per_sampe_rx; for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++) { @@ -1767,18 +1772,18 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * } audio->n_ff_used_rx = audio->n_channels_rx / audio->n_channels_per_ff_rx; TU_ASSERT( audio->n_ff_used_rx <= audio->n_rx_supp_ff ); -#endif -#endif + #endif + #endif // Prepare for incoming data -#if USE_LINEAR_BUFFER_RX + #if USE_LINEAR_BUFFER_RX TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_out, audio->lin_buf_out, audio->ep_out_sz), false); -#else + #else TU_VERIFY(usbd_edpt_xfer_fifo(rhport, audio->ep_out, &audio->ep_out_ff, audio->ep_out_sz), false); -#endif + #endif } -#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP + #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 1) // Check if usage is explicit data feedback { audio->ep_fb = ep_addr; @@ -1787,7 +1792,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * // Enable SOF interrupt if callback is implemented if (tud_audio_feedback_interval_isr) usbd_sof_enable(rhport, true); } -#endif + #endif #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT foundEPs += 1; @@ -1838,7 +1843,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * default: break; } } -#endif +#endif // CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP // We are done - abort loop break; diff --git a/src/device/usbd.c b/src/device/usbd.c index fd4414559..b67d3e29f 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1384,12 +1384,10 @@ bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packe { rhport = _usbd_rhport; + TU_ASSERT(dcd_edpt_iso_alloc); TU_ASSERT(tu_edpt_number(ep_addr) < CFG_TUD_ENDPPOINT_MAX); - if (dcd_edpt_iso_alloc) - return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size); - else - return false; + return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size); } bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) @@ -1399,18 +1397,14 @@ bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep uint8_t const epnum = tu_edpt_number(desc_ep->bEndpointAddress); uint8_t const dir = tu_edpt_dir(desc_ep->bEndpointAddress); + TU_ASSERT(dcd_edpt_iso_activate); TU_ASSERT(epnum < CFG_TUD_ENDPPOINT_MAX); TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed)); - if (dcd_edpt_iso_activate) - { - _usbd_dev.ep_status[epnum][dir].stalled = false; - _usbd_dev.ep_status[epnum][dir].busy = false; - _usbd_dev.ep_status[epnum][dir].claimed = false; - return dcd_edpt_iso_activate(rhport, desc_ep); - } - else - return false; + _usbd_dev.ep_status[epnum][dir].stalled = false; + _usbd_dev.ep_status[epnum][dir].busy = false; + _usbd_dev.ep_status[epnum][dir].claimed = false; + return dcd_edpt_iso_activate(rhport, desc_ep); } #endif diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index c9b244c8c..78da9d0e5 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -6,7 +6,7 @@ * Portions: * Copyright (c) 2016 STMicroelectronics * Copyright (c) 2019 Ha Thach (tinyusb.org) - * Copyright (c) 2022 Simon Kppers (skuep) + * Copyright (c) 2022 Simon Küppers (skuep) * Copyright (c) 2022 HiFiPhile * * Permission is hereby granted, free of charge, to any person obtaining a copy @@ -159,6 +159,10 @@ TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))<=(PMA_LEN TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligned to 8 bytes"); +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF +//--------------------------------------------------------------------+ + // One of these for every EP IN & OUT, uses a bit of RAM.... typedef struct { @@ -169,21 +173,9 @@ typedef struct uint16_t pma_ptr; uint16_t max_packet_size; uint16_t pma_alloc_size; - uint8_t epnum; + uint8_t ep_idx; // index for USB_EPnR register } xfer_ctl_t; -static xfer_ctl_t xfer_status[MAX_EP_COUNT][2]; - -TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr) -{ - uint8_t epnum = tu_edpt_number(ep_addr); - uint8_t dir = tu_edpt_dir(ep_addr); - // Fix -Werror=null-dereference - TU_ASSERT(epnum < MAX_EP_COUNT, &xfer_status[0][0]); - - return &xfer_status[epnum][dir]; -} - // EP allocator typedef struct { @@ -192,12 +184,18 @@ typedef struct bool allocated[2]; } ep_alloc_t; +static xfer_ctl_t xfer_status[MAX_EP_COUNT][2]; + static ep_alloc_t ep_alloc_status[STFSDEV_EP_COUNT]; static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6]; static uint8_t remoteWakeCountdown; // When wake is requested +//--------------------------------------------------------------------+ +// Prototypes +//--------------------------------------------------------------------+ + // into the stack. static void dcd_handle_bus_reset(void); static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix); @@ -217,6 +215,20 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wNBytes); static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNBytes); +//--------------------------------------------------------------------+ +// Inline helper +//--------------------------------------------------------------------+ + +TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr) +{ + uint8_t epnum = tu_edpt_number(ep_addr); + uint8_t dir = tu_edpt_dir(ep_addr); + // Fix -Werror=null-dereference + TU_ASSERT(epnum < MAX_EP_COUNT, &xfer_status[0][0]); + + return &xfer_status[epnum][dir]; +} + // Using a function due to better type checks // This seems better than having to do type casts everywhere else TU_ATTR_ALWAYS_INLINE static inline void reg16_clear_bits(__IO uint16_t *reg, uint16_t mask) { @@ -228,6 +240,10 @@ TU_ATTR_ALWAYS_INLINE static inline void clear_istr_bits(uint16_t mask) { USB->ISTR = ~mask; } +//--------------------------------------------------------------------+ +// Controller API +//--------------------------------------------------------------------+ + void dcd_init (uint8_t rhport) { /* Clocks should already be enabled */ @@ -825,6 +841,7 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type) { return i; } + // If EP of current direction is not allocated // Except for ISO endpoint, both direction should be free if(!ep_alloc_status[i].allocated[dir] && @@ -886,14 +903,14 @@ static void dcd_ep_free(uint8_t ep_addr) bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { (void)rhport; - uint8_t const epnum = dcd_ep_alloc(p_endpoint_desc->bEndpointAddress, p_endpoint_desc->bmAttributes.xfer); + uint8_t const ep_idx = dcd_ep_alloc(p_endpoint_desc->bEndpointAddress, p_endpoint_desc->bmAttributes.xfer); uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc); const uint16_t buffer_size = pcd_aligned_buffer_size(packet_size); uint16_t pma_addr; uint32_t wType; - TU_ASSERT(epnum < STFSDEV_EP_COUNT); + TU_ASSERT(ep_idx < STFSDEV_EP_COUNT); TU_ASSERT(buffer_size <= 1024); // Set type @@ -916,8 +933,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc TU_ASSERT(false); } - pcd_set_eptype(USB, epnum, wType); - pcd_set_ep_address(USB, epnum, tu_edpt_number(p_endpoint_desc->bEndpointAddress)); + pcd_set_eptype(USB, ep_idx, wType); + pcd_set_ep_address(USB, ep_idx, tu_edpt_number(p_endpoint_desc->bEndpointAddress)); // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint) // or being double-buffered (bulk endpoints) pcd_clear_ep_kind(USB,0); @@ -928,37 +945,37 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc if( (dir == TUSB_DIR_IN) || (wType == USB_EP_ISOCHRONOUS) ) { - *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr; - pcd_set_ep_tx_bufsize(USB, epnum, buffer_size); - pcd_clear_tx_dtog(USB, epnum); + *pcd_ep_tx_address_ptr(USB, ep_idx) = pma_addr; + pcd_set_ep_tx_bufsize(USB, ep_idx, buffer_size); + pcd_clear_tx_dtog(USB, ep_idx); } if( (dir == TUSB_DIR_OUT) || (wType == USB_EP_ISOCHRONOUS) ) { - *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr; - pcd_set_ep_rx_bufsize(USB, epnum, buffer_size); - pcd_clear_rx_dtog(USB, epnum); + *pcd_ep_rx_address_ptr(USB, ep_idx) = pma_addr; + pcd_set_ep_rx_bufsize(USB, ep_idx, buffer_size); + pcd_clear_rx_dtog(USB, ep_idx); } /* Enable endpoint */ if (dir == TUSB_DIR_IN) { if(wType == USB_EP_ISOCHRONOUS) { - pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS); + pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS); } else { - pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_NAK); + pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_NAK); } } else { if(wType == USB_EP_ISOCHRONOUS) { - pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS); + pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS); } else { - pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK); + pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_NAK); } } xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = packet_size; - xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum = epnum; + xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->ep_idx = ep_idx; return true; } @@ -981,16 +998,16 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) (void)rhport; xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr); - uint8_t const epnum = xfer->epnum; - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const ep_idx = xfer->ep_idx; + uint8_t const dir = tu_edpt_dir(ep_addr); if(dir == TUSB_DIR_IN) { - pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS); + pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS); } else { - pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS); + pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS); } dcd_ep_free(ep_addr); @@ -1004,19 +1021,19 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet TU_ASSERT(largest_packet_size <= 1024); - uint8_t const epnum = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS); + uint8_t const ep_idx = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS); const uint16_t buffer_size = pcd_aligned_buffer_size(largest_packet_size); /* Create a packet memory buffer area. For isochronous endpoints, * use the same buffer as the double buffer, essentially disabling double buffering */ uint16_t pma_addr = dcd_pma_alloc(ep_addr, buffer_size); - xfer_ctl_ptr(ep_addr)->epnum = epnum; + xfer_ctl_ptr(ep_addr)->ep_idx = ep_idx; - pcd_set_eptype(USB, epnum, USB_EP_ISOCHRONOUS); + pcd_set_eptype(USB, ep_idx, USB_EP_ISOCHRONOUS); - *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr; - *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr; + *pcd_ep_tx_address_ptr(USB, ep_idx) = pma_addr; + *pcd_ep_rx_address_ptr(USB, ep_idx) = pma_addr; return true; } @@ -1024,30 +1041,30 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { (void)rhport; - uint8_t const epnum = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum; - uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); + uint8_t const ep_idx = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->ep_idx; + uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc); const uint16_t buffer_size = pcd_aligned_buffer_size(packet_size); /* Disable endpoint */ if(dir == TUSB_DIR_IN) { - pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS); + pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS); } else { - pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS); + pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS); } - pcd_set_ep_address(USB, epnum, tu_edpt_number(p_endpoint_desc->bEndpointAddress)); + pcd_set_ep_address(USB, ep_idx, tu_edpt_number(p_endpoint_desc->bEndpointAddress)); // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint) // or being double-buffered (bulk endpoints) pcd_clear_ep_kind(USB,0); - pcd_set_ep_tx_bufsize(USB, epnum, buffer_size); - pcd_set_ep_rx_bufsize(USB, epnum, buffer_size); - pcd_clear_tx_dtog(USB, epnum); - pcd_clear_rx_dtog(USB, epnum); + pcd_set_ep_tx_bufsize(USB, ep_idx, buffer_size); + pcd_set_ep_rx_bufsize(USB, ep_idx, buffer_size); + pcd_clear_tx_dtog(USB, ep_idx); + pcd_clear_rx_dtog(USB, ep_idx); xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = packet_size; @@ -1093,8 +1110,8 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t (void) rhport; xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr); - uint8_t const epnum = xfer->epnum; - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const ep_idx = xfer->ep_idx; + uint8_t const dir = tu_edpt_dir(ep_addr); xfer->buffer = buffer; xfer->ff = NULL; @@ -1105,22 +1122,22 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t { // A setup token can occur immediately after an OUT STATUS packet so make sure we have a valid // buffer for the control endpoint. - if (epnum == 0 && buffer == NULL) + if (ep_idx == 0 && buffer == NULL) { xfer->buffer = (uint8_t*)_setup_packet; } if(total_bytes > xfer->max_packet_size) { - pcd_set_ep_rx_bufsize(USB,epnum,xfer->max_packet_size); + pcd_set_ep_rx_bufsize(USB,ep_idx,xfer->max_packet_size); } else { - pcd_set_ep_rx_bufsize(USB,epnum,total_bytes); + pcd_set_ep_rx_bufsize(USB,ep_idx,total_bytes); } - pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_VALID); + pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_VALID); } else // IN { - dcd_transmit_packet(xfer,epnum); + dcd_transmit_packet(xfer,ep_idx); } return true; } @@ -1130,7 +1147,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 (void) rhport; xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr); - uint8_t const epnum = xfer->epnum; + uint8_t const epnum = xfer->ep_idx; uint8_t const dir = tu_edpt_dir(ep_addr); xfer->buffer = NULL; @@ -1160,16 +1177,16 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) (void)rhport; xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr); - uint8_t const epnum = xfer->epnum; - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const ep_idx = xfer->ep_idx; + uint8_t const dir = tu_edpt_dir(ep_addr); if (dir == TUSB_DIR_IN) { // IN - pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_STALL); + pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_STALL); } else { // OUT - pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_STALL); + pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_STALL); } } @@ -1178,25 +1195,25 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) (void)rhport; xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr); - uint8_t const epnum = xfer->epnum; - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const ep_idx = xfer->ep_idx; + uint8_t const dir = tu_edpt_dir(ep_addr); if (dir == TUSB_DIR_IN) { // IN - if (pcd_get_eptype(USB, epnum) != USB_EP_ISOCHRONOUS) { - pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_NAK); + if (pcd_get_eptype(USB, ep_idx) != USB_EP_ISOCHRONOUS) { + pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_NAK); } /* Reset to DATA0 if clearing stall condition. */ - pcd_clear_tx_dtog(USB, epnum); + pcd_clear_tx_dtog(USB, ep_idx); } else { // OUT - if (pcd_get_eptype(USB, epnum) != USB_EP_ISOCHRONOUS) { - pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK); + if (pcd_get_eptype(USB, ep_idx) != USB_EP_ISOCHRONOUS) { + pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_NAK); } /* Reset to DATA0 if clearing stall condition. */ - pcd_clear_rx_dtog(USB, epnum); + pcd_clear_rx_dtog(USB, ep_idx); } } @@ -1318,7 +1335,7 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN *dstVal++ = ((temp >> 8) & 0xFF); } - if (wNBytes % 2) + if (wNBytes & 0x01) { temp = *pdwVal; pdwVal += PMA_STRIDE; diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index f4966907a..039fb13d2 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -120,9 +120,9 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR; // prototypes -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum); -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum); -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue); +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx); +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx); +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue); /* Aligned buffer size according to hardware */ TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size) @@ -138,71 +138,71 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t si } /* SetENDPOINT */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue) { - __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpNum*2u); + __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpIdx*2u); *reg = (uint16_t)wRegValue; } /* GetENDPOINT */ -TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpNum) { - __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpNum*2u); +TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) { + __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpIdx*2u); return *reg; } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wType) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wType) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= (uint32_t)USB_EP_T_MASK; regVal |= wType; regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; // These clear on write0, so must set high - pcd_set_endpoint(USBx, bEpNum, regVal); + pcd_set_endpoint(USBx, bEpIdx, regVal); } -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EP_T_FIELD; return regVal; } /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. + * @param bEpIdx Endpoint Number. * @retval None */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPREG_MASK; regVal &= ~USB_EP_CTR_RX; regVal |= USB_EP_CTR_TX; // preserve CTR_TX (clears on writing 0) - pcd_set_endpoint(USBx, bEpNum, regVal); + pcd_set_endpoint(USBx, bEpIdx, regVal); } -TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPREG_MASK; regVal &= ~USB_EP_CTR_TX; regVal |= USB_EP_CTR_RX; // preserve CTR_RX (clears on writing 0) - pcd_set_endpoint(USBx, bEpNum,regVal); + pcd_set_endpoint(USBx, bEpIdx,regVal); } /** * @brief gets counter of the tx buffer. * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. + * @param bEpIdx Endpoint Number. * @retval Counter value */ -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) { - __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpNum); + __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpIdx); return *regPtr & 0x3ffU; } -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) { - __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpNum); + __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx); return *regPtr & 0x3ffU; } @@ -229,17 +229,17 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_cnt_reg(__O uint16_t * pdwRe /** * @brief Sets address in an endpoint register. * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. + * @param bEpIdx Endpoint Number. * @param bAddr Address. * @retval None */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t bAddr) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t bAddr) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPREG_MASK; regVal |= bAddr; regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; - pcd_set_endpoint(USBx, bEpNum,regVal); + pcd_set_endpoint(USBx, bEpIdx,regVal); } TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) @@ -250,47 +250,47 @@ TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_Type } // Pointers to the PMA table entries (using the ARM address space) -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_address_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) { - return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 0u); + return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u); } -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) { - return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 1u); + return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 1u); } -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_address_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) { - return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 2u); + return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u); } -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) { - return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 3u); + return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 3u); } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { - __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpNum); + __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpIdx); *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU); } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { - __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpNum); + __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpIdx); *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU); } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { - __IO uint16_t *pdwReg = pcd_ep_tx_cnt_ptr((USBx),(bEpNum)); + __IO uint16_t *pdwReg = pcd_ep_tx_cnt_ptr((USBx),(bEpIdx)); wCount = pcd_aligned_buffer_size(wCount); pcd_set_ep_cnt_reg(pdwReg, wCount); } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { - __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpNum)); + __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpIdx)); wCount = pcd_aligned_buffer_size(wCount); pcd_set_ep_cnt_reg(pdwReg, wCount); } @@ -298,13 +298,13 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USB /** * @brief sets the status for tx transfer (bits STAT_TX[1:0]). * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. + * @param bEpIdx Endpoint Number. * @param wState new state * @retval None */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wState) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPTX_DTOGMASK; /* toggle first bit ? */ @@ -319,20 +319,20 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx } regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; - pcd_set_endpoint(USBx, bEpNum, regVal); + pcd_set_endpoint(USBx, bEpIdx, regVal); } /* pcd_set_ep_tx_status */ /** * @brief sets the status for rx transfer (bits STAT_TX[1:0]) * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. + * @param bEpIdx Endpoint Number. * @param wState new state * @retval None */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wState) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPRX_DTOGMASK; /* toggle first bit ? */ @@ -347,12 +347,12 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx } regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; - pcd_set_endpoint(USBx, bEpNum, regVal); + pcd_set_endpoint(USBx, bEpIdx, regVal); } /* pcd_set_ep_rx_status */ -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); return (regVal & USB_EPRX_STAT) >> (12u); } /* pcd_get_ep_rx_status */ @@ -360,71 +360,71 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * /** * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. + * @param bEpIdx Endpoint Number. * @retval None */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPREG_MASK; regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX; - pcd_set_endpoint(USBx, bEpNum, regVal); + pcd_set_endpoint(USBx, bEpIdx, regVal); } -TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPREG_MASK; regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX; - pcd_set_endpoint(USBx, bEpNum, regVal); + pcd_set_endpoint(USBx, bEpIdx, regVal); } /** * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. + * @param bEpIdx Endpoint Number. * @retval None */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); if((regVal & USB_EP_DTOG_RX) != 0) { - pcd_rx_dtog(USBx,bEpNum); + pcd_rx_dtog(USBx,bEpIdx); } } -TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); if((regVal & USB_EP_DTOG_TX) != 0) { - pcd_tx_dtog(USBx,bEpNum); + pcd_tx_dtog(USBx,bEpIdx); } } /** * @brief set & clear EP_KIND bit. * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. + * @param bEpIdx Endpoint Number. * @retval None */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal |= USB_EP_KIND; regVal &= USB_EPREG_MASK; regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; - pcd_set_endpoint(USBx, bEpNum, regVal); + pcd_set_endpoint(USBx, bEpIdx, regVal); } -TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum) +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPKIND_MASK; regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; - pcd_set_endpoint(USBx, bEpNum, regVal); + pcd_set_endpoint(USBx, bEpIdx, regVal); } // This checks if the device has "LPM" @@ -438,6 +438,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, u USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED ) // Number of endpoints in hardware +// TODO should use TUP_DCD_ENDPOINT_MAX #define STFSDEV_EP_COUNT (8u) #endif /* PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ */ -- cgit v1.3.1 From 5d3084a714eaa16b04e222ac4dc965ef29499e06 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Mar 2023 11:21:46 +0700 Subject: add TUP_USBIP_FSDEV and TUP_USBIP_FSDEV_STM32, clean up ifdef with stm32 --- src/class/audio/audio_device.c | 284 ++++++++++----------- src/common/tusb_mcu.h | 100 ++++++-- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 34 +-- .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 19 +- 4 files changed, 227 insertions(+), 210 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 5bccc66b7..d9c873851 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -66,71 +66,41 @@ // Use ring buffer if it's available, some MCUs need extra RAM requirements #ifndef TUD_AUDIO_PREFER_RING_BUFFER -#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT -#define TUD_AUDIO_PREFER_RING_BUFFER 0 -#else -#define TUD_AUDIO_PREFER_RING_BUFFER 1 -#endif + #if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT + #define TUD_AUDIO_PREFER_RING_BUFFER 0 + #else + #define TUD_AUDIO_PREFER_RING_BUFFER 1 + #endif #endif // Linear buffer in case target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer // is available or driver is would need to be changed dramatically // Only STM32 and dcd_transdimension use non-linear buffer for now -#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || \ - CFG_TUSB_MCU == OPT_MCU_STM32F1 || \ - CFG_TUSB_MCU == OPT_MCU_STM32F2 || \ - CFG_TUSB_MCU == OPT_MCU_STM32F3 || \ - CFG_TUSB_MCU == OPT_MCU_STM32F4 || \ - CFG_TUSB_MCU == OPT_MCU_STM32F7 || \ - CFG_TUSB_MCU == OPT_MCU_STM32H7 || \ - CFG_TUSB_MCU == OPT_MCU_STM32L0 || \ - CFG_TUSB_MCU == OPT_MCU_STM32L1 || \ - CFG_TUSB_MCU == OPT_MCU_STM32L4 || \ - CFG_TUSB_MCU == OPT_MCU_STM32G4 || \ - CFG_TUSB_MCU == OPT_MCU_STM32WB || \ - CFG_TUSB_MCU == OPT_MCU_RX63X || \ - CFG_TUSB_MCU == OPT_MCU_RX65X || \ - CFG_TUSB_MCU == OPT_MCU_RX72N || \ - CFG_TUSB_MCU == OPT_MCU_GD32VF103 || \ - CFG_TUSB_MCU == OPT_MCU_LPC18XX || \ - CFG_TUSB_MCU == OPT_MCU_LPC43XX || \ - CFG_TUSB_MCU == OPT_MCU_MIMXRT || \ +// dwc2 except esp32sx (since it may use dcd_esp32sx) +#if (defined(TUP_USBIP_DWC2) && !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)) || \ + defined(TUP_USBIP_FSDEV) || \ + CFG_TUSB_MCU == OPT_MCU_RX63X || \ + CFG_TUSB_MCU == OPT_MCU_RX65X || \ + CFG_TUSB_MCU == OPT_MCU_RX72N || \ + CFG_TUSB_MCU == OPT_MCU_LPC18XX || \ + CFG_TUSB_MCU == OPT_MCU_LPC43XX || \ + CFG_TUSB_MCU == OPT_MCU_MIMXRT || \ CFG_TUSB_MCU == OPT_MCU_MSP432E4 -#if TUD_AUDIO_PREFER_RING_BUFFER -#define USE_LINEAR_BUFFER 0 -#else -#define USE_LINEAR_BUFFER 1 -#endif + #if TUD_AUDIO_PREFER_RING_BUFFER + #define USE_LINEAR_BUFFER 0 + #else + #define USE_LINEAR_BUFFER 1 + #endif #else -#define USE_LINEAR_BUFFER 1 -#endif - -#if defined(STM32F102x6) || defined(STM32F102xB) || \ - defined(STM32F103x6) || defined(STM32F103xB) || \ - defined(STM32F103xE) || defined(STM32F103xG) -#define STM32F1_FSDEV -#endif - -#if defined(STM32L412xx) || defined(STM32L422xx) || \ - defined(STM32L432xx) || defined(STM32L433xx) || \ - defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) -#define STM32L4_FSDEV + #define USE_LINEAR_BUFFER 1 #endif // Temporarily put the check here for stm32_fsdev -#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || \ - CFG_TUSB_MCU == OPT_MCU_STM32F3 || \ - CFG_TUSB_MCU == OPT_MCU_STM32L0 || \ - CFG_TUSB_MCU == OPT_MCU_STM32L1 || \ - CFG_TUSB_MCU == OPT_MCU_STM32G4 || \ - CFG_TUSB_MCU == OPT_MCU_STM32WB || \ - (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) || \ - (TU_CHECK_MCU(OPT_MCU_STM32L4) && defined(STM32L4_FSDEV)) -#define USE_ISO_EP_ALLOCATION 1 +#ifdef TUP_USBIP_FSDEV + #define USE_ISO_EP_ALLOCATION 1 #else -#define USE_ISO_EP_ALLOCATION 0 + #define USE_ISO_EP_ALLOCATION 0 #endif // Declaration of buffers @@ -142,143 +112,159 @@ // EP IN software buffers and mutexes #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING -#if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ]; -#if CFG_FIFO_MUTEX -osal_mutex_def_t ep_in_ff_mutex_wr_1; // No need for read mutex as only USB driver reads from FIFO -#endif -#endif // CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0 -#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ]; -#if CFG_FIFO_MUTEX -osal_mutex_def_t ep_in_ff_mutex_wr_2; // No need for read mutex as only USB driver reads from FIFO -#endif -#endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0 -#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ]; -#if CFG_FIFO_MUTEX -osal_mutex_def_t ep_in_ff_mutex_wr_3; // No need for read mutex as only USB driver reads from FIFO -#endif -#endif // CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0 + #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ]; + #if CFG_FIFO_MUTEX + osal_mutex_def_t ep_in_ff_mutex_wr_1; // No need for read mutex as only USB driver reads from FIFO + #endif + #endif // CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0 + + #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ]; + #if CFG_FIFO_MUTEX + osal_mutex_def_t ep_in_ff_mutex_wr_2; // No need for read mutex as only USB driver reads from FIFO + #endif + #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0 + + #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ]; + #if CFG_FIFO_MUTEX + osal_mutex_def_t ep_in_ff_mutex_wr_3; // No need for read mutex as only USB driver reads from FIFO + #endif + #endif // CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0 #endif // CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING // Linear buffer TX in case: // - target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer is available or driver is would need to be changed dramatically OR // - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into #if CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING) -#if CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX]; -#endif -#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX]; -#endif -#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX]; -#endif + #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX]; + #endif + + #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX]; + #endif + + #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX]; + #endif #endif // CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING) // EP OUT software buffers and mutexes #if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING -#if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ]; -#if CFG_FIFO_MUTEX -osal_mutex_def_t ep_out_ff_mutex_rd_1; // No need for write mutex as only USB driver writes into FIFO -#endif -#endif // CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0 -#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ]; -#if CFG_FIFO_MUTEX -osal_mutex_def_t ep_out_ff_mutex_rd_2; // No need for write mutex as only USB driver writes into FIFO -#endif -#endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0 -#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ]; -#if CFG_FIFO_MUTEX -osal_mutex_def_t ep_out_ff_mutex_rd_3; // No need for write mutex as only USB driver writes into FIFO -#endif -#endif // CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0 + #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ]; + #if CFG_FIFO_MUTEX + osal_mutex_def_t ep_out_ff_mutex_rd_1; // No need for write mutex as only USB driver writes into FIFO + #endif + #endif // CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0 + + #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ]; + #if CFG_FIFO_MUTEX + osal_mutex_def_t ep_out_ff_mutex_rd_2; // No need for write mutex as only USB driver writes into FIFO + #endif + #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0 + + #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ]; + #if CFG_FIFO_MUTEX + osal_mutex_def_t ep_out_ff_mutex_rd_3; // No need for write mutex as only USB driver writes into FIFO + #endif + #endif // CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING // Linear buffer RX in case: // - target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer is available or driver is would need to be changed dramatically OR // - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into #if CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING) -#if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX]; -#endif -#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX]; -#endif -#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX]; -#endif + #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX]; + #endif + + #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX]; + #endif + + #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX]; + #endif #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING) // Control buffers CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_1[CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ]; + #if CFG_TUD_AUDIO > 1 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_2[CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ]; #endif + #if CFG_TUD_AUDIO > 2 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ]; #endif // Active alternate setting of interfaces uint8_t alt_setting_1[CFG_TUD_AUDIO_FUNC_1_N_AS_INT]; + #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_N_AS_INT > 0 uint8_t alt_setting_2[CFG_TUD_AUDIO_FUNC_2_N_AS_INT]; #endif + #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_N_AS_INT > 0 uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT]; #endif // Software encoding/decoding support FIFOs #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING -#if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ]; -tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; -#if CFG_FIFO_MUTEX -osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO -#endif -#endif -#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ]; -tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; -#if CFG_FIFO_MUTEX -osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO -#endif -#endif -#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ]; -tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; -#if CFG_FIFO_MUTEX -osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO -#endif -#endif + #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ]; + tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; + #if CFG_FIFO_MUTEX + osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO + #endif + #endif + + #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ]; + tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; + #if CFG_FIFO_MUTEX + osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO + #endif + #endif + + #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ]; + tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; + #if CFG_FIFO_MUTEX + osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO + #endif + #endif #endif #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING -#if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ]; -tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; -#if CFG_FIFO_MUTEX -osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO -#endif -#endif -#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ]; -tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; -#if CFG_FIFO_MUTEX -osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO -#endif -#endif -#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ]; -tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; -#if CFG_FIFO_MUTEX -osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO -#endif -#endif + #if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ]; + tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; + #if CFG_FIFO_MUTEX + osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO + #endif + #endif + + #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ]; + tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; + #if CFG_FIFO_MUTEX + osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO + #endif + #endif + + #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0 + CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ]; + tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; + #if CFG_FIFO_MUTEX + osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO + #endif + #endif #endif typedef struct diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 1f27afa4e..257d08a85 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -48,7 +48,9 @@ * - RHPORT_HIGHSPEED: support highspeed with on-chip PHY */ -//------------- NXP -------------// +//--------------------------------------------------------------------+ +// NXP +//--------------------------------------------------------------------+ #if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX) #define TUP_DCD_ENDPOINT_MAX 5 @@ -89,12 +91,16 @@ #elif TU_CHECK_MCU(OPT_MCU_MM32F327X) #define TUP_DCD_ENDPOINT_MAX 16 -//------------- Nordic -------------// +//--------------------------------------------------------------------+ +// Nordic +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_NRF5X) // 8 CBI + 1 ISO #define TUP_DCD_ENDPOINT_MAX 9 -//------------- Microchip -------------// +//--------------------------------------------------------------------+ +// Microchip +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAMD51, OPT_MCU_SAME5X) || \ TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22) #define TUP_DCD_ENDPOINT_MAX 8 @@ -117,19 +123,30 @@ #define TUP_DCD_ENDPOINT_MAX 16 #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER -//------------- ST -------------// +//--------------------------------------------------------------------+ +// ST +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_STM32F0) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 #elif TU_CHECK_MCU(OPT_MCU_STM32F1) + // - F102, F103 use fsdev + // - F105, F107 use dwc2 #if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \ defined (STM32F107xB) || defined (STM32F107xC) #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_STM32 #define TUP_DCD_ENDPOINT_MAX 4 - #else + #elif defined(STM32F102x6) || defined(STM32F102xB) || \ + defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 + #else + #error "Unsupported STM32F1 mcu" #endif #elif TU_CHECK_MCU(OPT_MCU_STM32F2) @@ -140,6 +157,8 @@ #define TUP_DCD_ENDPOINT_MAX 6 #elif TU_CHECK_MCU(OPT_MCU_STM32F3) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 #elif TU_CHECK_MCU(OPT_MCU_STM32F4) @@ -168,12 +187,18 @@ #define TUP_DCD_ENDPOINT_MAX 9 #elif TU_CHECK_MCU(OPT_MCU_STM32G4) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 #elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 #elif TU_CHECK_MCU(OPT_MCU_STM32L4) + // - L4x2, L4x3 use fsdev + // - L4x4, L4x6, L4x7, L4x9 use dwc2 #if defined (STM32L475xx) || defined (STM32L476xx) || \ defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \ defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ @@ -183,11 +208,18 @@ #define TUP_USBIP_DWC2_STM32 #define TUP_DCD_ENDPOINT_MAX 6 - #else + #elif defined(STM32L412xx) || defined(STM32L422xx) || defined(STM32L432xx) || defined(STM32L433xx) || \ + defined(STM32L442xx) || defined(STM32L443xx) || defined(STM32L452xx) || defined(STM32L462xx) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 + #else + #error "Unsupported STM32L4 mcu" #endif #elif TU_CHECK_MCU(OPT_MCU_STM32WB) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 #elif TU_CHECK_MCU(OPT_MCU_STM32U5) @@ -195,24 +227,32 @@ #define TUP_USBIP_DWC2_STM32 #define TUP_DCD_ENDPOINT_MAX 6 -//------------- Sony -------------// +//--------------------------------------------------------------------+ +// Sony +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_CXD56) #define TUP_DCD_ENDPOINT_MAX 7 #define TUP_RHPORT_HIGHSPEED 1 #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER -//------------- TI -------------// +//--------------------------------------------------------------------+ +// TI +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx) #define TUP_DCD_ENDPOINT_MAX 8 #elif TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) #define TUP_DCD_ENDPOINT_MAX 8 -//------------- ValentyUSB -------------// +//--------------------------------------------------------------------+ +// ValentyUSB (Litex) +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_VALENTYUSB_EPTRI) #define TUP_DCD_ENDPOINT_MAX 16 -//------------- Nuvoton -------------// +//--------------------------------------------------------------------+ +// Nuvoton +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_NUC121, OPT_MCU_NUC126) #define TUP_DCD_ENDPOINT_MAX 8 @@ -223,47 +263,65 @@ #define TUP_DCD_ENDPOINT_MAX 12 #define TUP_RHPORT_HIGHSPEED 1 -//------------- Espressif -------------// +//--------------------------------------------------------------------+ +// Espressif +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) #define TUP_USBIP_DWC2 #define TUP_DCD_ENDPOINT_MAX 6 -//------------- Dialog -------------// +//--------------------------------------------------------------------+ +// Dialog +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_DA1469X) #define TUP_DCD_ENDPOINT_MAX 4 -//------------- Raspberry Pi -------------// +//--------------------------------------------------------------------+ +// Raspberry Pi +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_RP2040) #define TUP_DCD_ENDPOINT_MAX 16 #define TU_ATTR_FAST_FUNC __attribute__((section(".time_critical.tinyusb"))) -//------------- Silabs -------------// +//--------------------------------------------------------------------+ +// Silabs +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_EFM32GG) #define TUP_USBIP_DWC2 #define TUP_DCD_ENDPOINT_MAX 7 -//------------- Renesas -------------// +//--------------------------------------------------------------------+ +// Renesas +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #define TUP_DCD_ENDPOINT_MAX 10 -//------------- GigaDevice -------------// +//--------------------------------------------------------------------+ +// GigaDevice +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_GD32VF103) #define TUP_USBIP_DWC2 #define TUP_DCD_ENDPOINT_MAX 4 -//------------- Broadcom -------------// +//--------------------------------------------------------------------+ +// Broadcom +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837) #define TUP_USBIP_DWC2 #define TUP_DCD_ENDPOINT_MAX 8 #define TUP_RHPORT_HIGHSPEED 1 -//------------- Broadcom -------------// +//--------------------------------------------------------------------+ +// Infineon +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_XMC4000) #define TUP_USBIP_DWC2 #define TUP_DCD_ENDPOINT_MAX 8 -//------------- BridgeTek -------------// +//--------------------------------------------------------------------+ +// BridgeTek +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_FT90X) #define TUP_DCD_ENDPOINT_MAX 8 #define TUP_RHPORT_HIGHSPEED 1 @@ -272,7 +330,9 @@ #define TUP_DCD_ENDPOINT_MAX 16 #define TUP_RHPORT_HIGHSPEED 1 -//------------ Allwinner -------------// +//--------------------------------------------------------------------+ +// Allwinner +//--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_F1C100S) #define TUP_DCD_ENDPOINT_MAX 4 diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 78da9d0e5..e49c0b52e 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -101,32 +101,15 @@ #include "tusb_option.h" -#if defined(STM32F102x6) || defined(STM32F102xB) || \ - defined(STM32F103x6) || defined(STM32F103xB) || \ - defined(STM32F103xE) || defined(STM32F103xG) -#define STM32F1_FSDEV -#endif - -#if defined(STM32L412xx) || defined(STM32L422xx) || \ - defined(STM32L432xx) || defined(STM32L433xx) || \ - defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) -#define STM32L4_FSDEV -#endif - -#if CFG_TUD_ENABLED && \ - ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32G4, OPT_MCU_STM32WB) || \ - (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) || \ - (TU_CHECK_MCU(OPT_MCU_STM32L4) && defined(STM32L4_FSDEV)) \ - ) - -// In order to reduce the dependence on HAL, we undefine this. -// Some definitions are copied to our private include file. -#undef USE_HAL_DRIVER +#if CFG_TUD_ENABLED && defined(TUP_USBIP_FSDEV) #include "device/dcd.h" -#include "portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h" +#ifdef TUP_USBIP_FSDEV_STM32 + // Undefine to reduce the dependence on HAL + #undef USE_HAL_DRIVER + #include "portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h" +#endif /***************************************************** * Configuration @@ -153,10 +136,7 @@ */ TU_VERIFY_STATIC((MAX_EP_COUNT) <= STFSDEV_EP_COUNT, "Only 8 endpoints supported on the hardware"); - -TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))<=(PMA_LENGTH), - "BTABLE does not fit in PMA RAM"); - +TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))<=(PMA_LENGTH), "BTABLE does not fit in PMA RAM"); TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligned to 8 bytes"); //--------------------------------------------------------------------+ diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 039fb13d2..015b177cf 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -1,12 +1,6 @@ /** - ****************************************************************************** - * @file dcd_stm32f0_pvt_st.h - * @brief DCD utilities from ST code - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- *

© parts COPYRIGHT(c) N Conrad

+ * Copyright(c) 2016 STMicroelectronics + * Copyright(c) N Conrad * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -30,7 +24,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - **********/ + */ // This file contains source copied from ST's HAL, and thus should have their copyright statement. @@ -41,10 +35,7 @@ #ifndef PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ #define PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ -#if defined(STM32F042x6) || \ - defined(STM32F070x6) || defined(STM32F070xB) || \ - defined(STM32F072xB) || \ - defined(STM32F078xx) +#if CFG_TUSB_MCU == OPT_MCU_STM32F0 #include "stm32f0xx.h" #define PMA_LENGTH (1024u) // F0x2 models are crystal-less @@ -52,7 +43,7 @@ // 070RB: 2 x 16 bits/word memory LPM Support, BCD Support // PMA dedicated to USB (no sharing with CAN) -#elif defined(STM32F1_FSDEV) +#elif CFG_TUSB_MCU == OPT_MCU_STM32F1 #include "stm32f1xx.h" #define PMA_LENGTH (512u) // NO internal Pull-ups -- cgit v1.3.1 From b7fa90e7066fff8a529d02c2a51a3319f25c77f8 Mon Sep 17 00:00:00 2001 From: graham sanderson Date: Thu, 2 Mar 2023 14:32:22 -0600 Subject: rp2040: Fixup lib and example compile for LLVM Embedded Toolchain for ARM --- examples/host/msc_file_explorer/src/msc_app.c | 2 +- hw/bsp/rp2040/family.cmake | 20 +++++++++++++++++--- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 2 +- 3 files changed, 19 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c index 5a1635015..eef28fe12 100644 --- a/examples/host/msc_file_explorer/src/msc_app.c +++ b/examples/host/msc_file_explorer/src/msc_app.c @@ -413,7 +413,7 @@ void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context) { for(UINT c = 0; c < count; c++) { - const char ch = buf[c]; + const uint8_t ch = buf[c]; if (isprint(ch) || iscntrl(ch)) { putchar(ch); diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index 1eab95304..82010efef 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -152,6 +152,9 @@ if (NOT TARGET _rp2040_family_inclusion_marker) if (NOT PICO_TINYUSB_NO_EXAMPLE_WARNINGS) family_add_default_example_warnings(${TARGET}) endif() + if(CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_compile_options(${TARGET} PRIVATE -Wno-unreachable-code) + endif() suppress_tinyusb_warnings() endfunction() @@ -172,8 +175,8 @@ if (NOT TARGET _rp2040_family_inclusion_marker) # For rp2040 enable pico-pio-usb if (TARGET tinyusb_pico_pio_usb) - # code does not compile with GCC 12+ - if (NOT (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.3)) + # code does not compile with non GCC, or GCC 11.3+ + if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND NOT CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.3) family_add_pico_pio_usb(${PROJECT}) endif() endif() @@ -278,7 +281,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker) COMPILE_FLAGS "-Wno-conversion") endforeach() endif() - if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.0) + if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.0) set_source_files_properties( ${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c COMPILE_FLAGS "-Wno-stringop-overflow -Wno-array-bounds") @@ -310,6 +313,17 @@ if (NOT TARGET _rp2040_family_inclusion_marker) PROPERTIES COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual -Wno-attributes") endif() + elseif(CMAKE_C_COMPILER_ID STREQUAL "Clang") + set_source_files_properties( + ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c + COMPILE_FLAGS "-Wno-unreachable-code") + set_source_files_properties( + ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c + COMPILE_FLAGS "-Wno-unreachable-code-fallthrough") + set_source_files_properties( + ${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c + PROPERTIES + COMPILE_FLAGS "-Wno-cast-qual") endif() endfunction() endif() diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index b5fa90c92..8df7bef2b 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -297,7 +297,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) if ( status & USB_INTS_SETUP_REQ_BITS ) { handled |= USB_INTS_SETUP_REQ_BITS; - uint8_t const * setup = (uint8_t const*) &usb_dpram->setup_packet; + uint8_t const * setup = remove_volatile_cast(uint8_t const*, &usb_dpram->setup_packet); // reset pid to both 1 (data and ack) reset_ep0_pid(); -- cgit v1.3.1 From 95cfa37bf56ee45f9bdd82e013c44604d29d7cb6 Mon Sep 17 00:00:00 2001 From: Nathaniel Brough Date: Sun, 5 Mar 2023 18:47:48 -0800 Subject: fix: Fix wrong destsz used with tu_memcpy_s Bug: #1935 --- src/class/audio/audio_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index d9c873851..f21dfee64 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -2290,7 +2290,7 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req if (len > _audiod_fct[func_id].ctrl_buf_sz) len = _audiod_fct[func_id].ctrl_buf_sz; // Copy into buffer - TU_VERIFY(0 == tu_memcpy_s(_audiod_fct[func_id].ctrl_buf, sizeof(_audiod_fct[func_id].ctrl_buf), data, (size_t)len)); + TU_VERIFY(0 == tu_memcpy_s(_audiod_fct[func_id].ctrl_buf, _audiod_fct[func_id].ctrl_buf_sz, data, (size_t)len)); // Schedule transmit return tud_control_xfer(rhport, p_request, (void*)_audiod_fct[func_id].ctrl_buf, len); -- cgit v1.3.1 From 410ad4d0f9ff166610655bae31328e4120b17ef2 Mon Sep 17 00:00:00 2001 From: Hubert Denkmair Date: Wed, 8 Mar 2023 12:05:58 +0100 Subject: add basic STM32G0 support --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 86 +++++++--- .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 180 +++++++++++++++------ 2 files changed, 198 insertions(+), 68 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index e49c0b52e..21ae8e6e8 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -216,7 +216,7 @@ TU_ATTR_ALWAYS_INLINE static inline void reg16_clear_bits(__IO uint16_t *reg, ui } // Bits in ISTR are cleared upon writing 0 -TU_ATTR_ALWAYS_INLINE static inline void clear_istr_bits(uint16_t mask) { +TU_ATTR_ALWAYS_INLINE static inline void clear_istr_bits(uint32_t mask) { USB->ISTR = ~mask; } @@ -242,16 +242,23 @@ void dcd_init (uint8_t rhport) { asm("NOP"); } + +#ifdef PMA_32BIT_ACCESS // CNTR register is 32bits on STM32G0, 16bit on older versions + USB->CNTR &= ~USB_CNTR_PDWN; +#else reg16_clear_bits(&USB->CNTR, USB_CNTR_PDWN);// Remove powerdown +#endif + // Wait startup time, for F042 and F070, this is <= 1 us. for(uint32_t i = 0; i<200; i++) // should be a few us { asm("NOP"); } USB->CNTR = 0; // Enable USB - - USB->BTABLE = DCD_STM32_BTABLE_BASE; +#ifndef STM32G0 // BTABLE register does not exist any more on STM32G0, it is fixed to USB SRAM base address + USB->BTABLE = DCD_STM32_BTABLE_BASE; +#endif USB->ISTR = 0; // Clear pending interrupts // Reset endpoints to disabled @@ -312,7 +319,7 @@ void dcd_sof_enable(uint8_t rhport, bool en) } else { - USB->CNTR &= (uint16_t) ~USB_CNTR_SOFM; + USB->CNTR &= ~USB_CNTR_SOFM; } } @@ -358,6 +365,9 @@ void dcd_int_enable (uint8_t rhport) NVIC_EnableIRQ(USB_LP_IRQn); NVIC_EnableIRQ(USBWakeUp_IRQn); +#elif CFG_TUSB_MCU == OPT_MCU_STM32G0 + NVIC_EnableIRQ(USB_UCPD1_2_IRQn); + #elif CFG_TUSB_MCU == OPT_MCU_STM32WB NVIC_EnableIRQ(USB_HP_IRQn); NVIC_EnableIRQ(USB_LP_IRQn); @@ -405,6 +415,9 @@ void dcd_int_disable(uint8_t rhport) NVIC_DisableIRQ(USB_LP_IRQn); NVIC_DisableIRQ(USBWakeUp_IRQn); +#elif CFG_TUSB_MCU == OPT_MCU_STM32G0 + NVIC_DisableIRQ(USB_UCPD1_2_IRQn); + #elif CFG_TUSB_MCU == OPT_MCU_STM32WB NVIC_DisableIRQ(USB_HP_IRQn); NVIC_DisableIRQ(USB_LP_IRQn); @@ -433,7 +446,7 @@ void dcd_remote_wakeup(uint8_t rhport) { (void) rhport; - USB->CNTR |= (uint16_t) USB_CNTR_RESUME; + USB->CNTR |= USB_CNTR_RESUME; remoteWakeCountdown = 4u; // required to be 1 to 15 ms, ESOF should trigger every 1ms. } @@ -534,9 +547,6 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) if((ep_addr == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) /* Setup packet */ { - // The setup_received function uses memcpy, so this must first copy the setup data into - // user memory, to allow for the 32-bit access that memcpy performs. - uint8_t userMemBuf[8]; uint32_t count = pcd_get_ep_rx_cnt(USB, EPindex); /* Get SETUP Packet*/ if(count == 8) // Setup packet should always be 8 bytes. If not, ignore it, and try again. @@ -544,8 +554,15 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) // Must reset EP to NAK (in case it had been stalling) (though, maybe too late here) pcd_set_ep_rx_status(USB,0u,USB_EP_RX_NAK); pcd_set_ep_tx_status(USB,0u,USB_EP_TX_NAK); - dcd_read_packet_memory(userMemBuf, *pcd_ep_rx_address_ptr(USB,EPindex), 8); +#ifdef PMA_32BIT_ACCESS + dcd_event_setup_received(0, (uint8_t*)(USB_PMAADDR + pcd_get_ep_rx_address(USB, EPindex)), true); +#else + // The setup_received function uses memcpy, so this must first copy the setup data into + // user memory, to allow for the 32-bit access that memcpy performs. + uint8_t userMemBuf[8]; + dcd_read_packet_memory(userMemBuf, pcd_get_ep_rx_address(USB,EPindex), 8); dcd_event_setup_received(0, (uint8_t*)userMemBuf, true); +#endif } } else @@ -568,7 +585,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) if (count != 0U) { - uint16_t addr = *pcd_ep_rx_address_ptr(USB, EPindex); + uint16_t addr = pcd_get_ep_rx_address(USB, EPindex); if (xfer->ff) { @@ -672,8 +689,13 @@ void dcd_int_handler(uint8_t rhport) { if (int_status & USB_ISTR_WKUP) { +#ifdef PMA_32BIT_ACCESS // CNTR register is 32bits on STM32G0, 16bit on older versions + USB->CNTR &= ~USB_CNTR_LPMODE; + USB->CNTR &= ~USB_CNTR_FSUSP; +#else reg16_clear_bits(&USB->CNTR, USB_CNTR_LPMODE); reg16_clear_bits(&USB->CNTR, USB_CNTR_FSUSP); +#endif clear_istr_bits(USB_ISTR_WKUP); dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); } @@ -695,7 +717,7 @@ void dcd_int_handler(uint8_t rhport) { if(int_status & USB_ISTR_ESOF) { if(remoteWakeCountdown == 1u) { - USB->CNTR &= (uint16_t)(~USB_CNTR_RESUME); + USB->CNTR &= ~USB_CNTR_RESUME; } if(remoteWakeCountdown > 0u) { @@ -722,8 +744,13 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re uint8_t const dev_addr = (uint8_t) request->wValue; // Setting new address after the whole request is complete +#ifdef PMA_32BIT_ACCESS + USB->DADDR &= ~USB_DADDR_ADD; + USB->DADDR = (USB->DADDR & ~USB_DADDR_ADD_Msk) | dev_addr; // leave the enable bit set +#else reg16_clear_bits(&USB->DADDR, USB_DADDR_ADD); USB->DADDR = (uint16_t)(USB->DADDR | dev_addr); // leave the enable bit set +#endif } } @@ -925,14 +952,14 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc if( (dir == TUSB_DIR_IN) || (wType == USB_EP_ISOCHRONOUS) ) { - *pcd_ep_tx_address_ptr(USB, ep_idx) = pma_addr; + pcd_set_ep_tx_address(USB, ep_idx, pma_addr); pcd_set_ep_tx_bufsize(USB, ep_idx, buffer_size); pcd_clear_tx_dtog(USB, ep_idx); } if( (dir == TUSB_DIR_OUT) || (wType == USB_EP_ISOCHRONOUS) ) { - *pcd_ep_rx_address_ptr(USB, ep_idx) = pma_addr; + pcd_set_ep_rx_address(USB, ep_idx, pma_addr); pcd_set_ep_rx_bufsize(USB, ep_idx, buffer_size); pcd_clear_rx_dtog(USB, ep_idx); } @@ -1011,10 +1038,10 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet xfer_ctl_ptr(ep_addr)->ep_idx = ep_idx; pcd_set_eptype(USB, ep_idx, USB_EP_ISOCHRONOUS); - - *pcd_ep_tx_address_ptr(USB, ep_idx) = pma_addr; - *pcd_ep_rx_address_ptr(USB, ep_idx) = pma_addr; - + + pcd_set_ep_tx_address(USB, ep_idx, pma_addr); + pcd_set_ep_rx_address(USB, ep_idx, pma_addr); + return true; } @@ -1063,7 +1090,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix) } uint16_t ep_reg = pcd_get_endpoint(USB, ep_ix); - uint16_t addr_ptr = *pcd_ep_tx_address_ptr(USB,ep_ix); + uint16_t addr_ptr = pcd_get_ep_tx_address(USB, ep_ix); if (xfer->ff) { @@ -1197,6 +1224,19 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) } } +#ifdef PMA_32BIT_ACCESS +static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes) +{ + // FIXME original function uses byte-access to source memory (to support non-aligned buffers) + const uint32_t* src32 = (uint32_t*)(src); + uint32_t* dst32 = (uint32_t*)(USB_PMAADDR + dst); + for (unsigned n=wNBytes/4; n>0; --n) { + *dst32++ = *src32++; + } + *dst32 = (*src32) & ((1<<8*(wNBytes % 4)) - 1); + return true; +} +#else // Packet buffer access can only be 8- or 16-bit. /** * @brief Copy a buffer from user memory area to packet memory area (PMA). @@ -1239,6 +1279,7 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si return true; } +#endif /** * @brief Copy from FIFO to packet memory area (PMA). @@ -1290,6 +1331,14 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN return true; } +#ifdef PMA_32BIT_ACCESS +static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes) +{ + // FIXME this should probably be modified for possible unaligned access? + memcpy(dst, (void*)(USB_PMAADDR+src), wNBytes); + return true; +} +#else /** * @brief Copy a buffer from packet memory area (PMA) to user memory area. * Uses byte-access of system memory and 16-bit access of packet memory @@ -1323,6 +1372,7 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN } return true; } +#endif /** * @brief Copy a buffer from user packet memory area (PMA) to FIFO. diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 015b177cf..686bfaa66 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -82,6 +82,34 @@ #include "stm32g4xx.h" #define PMA_LENGTH (1024u) +#elif CFG_TUSB_MCU == OPT_MCU_STM32G0 + #include "STM32/stm32g0xx.h" + #define PMA_32BIT_ACCESS + #define PMA_LENGTH (1024u) // FIXME it is 2048, really + #undef USB_PMAADDR + #define USB_PMAADDR USB_DRD_PMAADDR + #define USB_TypeDef USB_DRD_TypeDef + #define EP0R CHEP0R + #define USB_EP_CTR_RX USB_EP_VTRX + #define USB_EP_CTR_TX USB_EP_VTTX + #define USB_EP_T_FIELD USB_CHEP_UTYPE + #define USB_EPREG_MASK USB_CHEP_REG_MASK + #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK + #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK + #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1 + #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2 + #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1 + #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2 + #define USB_EPRX_STAT USB_CH_RX_VALID + #define USB_EPKIND_MASK USB_EP_KIND_MASK + #define USB USB_DRD_FS + #define USB_CNTR_FRES USB_CNTR_USBRST + #define USB_CNTR_RESUME USB_CNTR_L2RES + #define USB_ISTR_EP_ID USB_ISTR_IDN + #define USB_EPADDR_FIELD USB_CHEP_ADDR + #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY + #define USB_CNTR_FSUSP USB_CNTR_SUSPEN + #elif CFG_TUSB_MCU == OPT_MCU_STM32WB #include "stm32wbxx.h" #define PMA_LENGTH (1024u) @@ -105,15 +133,31 @@ #define PMA_STRIDE (1u) #endif -// And for type-safety create a new macro for the volatile address of PMAADDR +// For type-safety create a new macro for the volatile address of PMAADDR // The compiler should warn us if we cast it to a non-volatile type? +#ifdef PMA_32BIT_ACCESS +static __IO uint32_t * const pma32 = (__IO uint32_t*)USB_PMAADDR; +#else // Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden) static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR; -// prototypes -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx); -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx); -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue); +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) +{ + size_t total_word_offset = (((USBx)->BTABLE)>>1) + x; + total_word_offset *= PMA_STRIDE; + return &(pma[total_word_offset]); +} + +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) +{ + return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 1u); +} + +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) +{ + return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 3u); +} +#endif /* Aligned buffer size according to hardware */ TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size) @@ -131,13 +175,22 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t si /* SetENDPOINT */ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue) { +#ifdef PMA_32BIT_ACCESS + __O uint32_t *reg = (__O uint32_t *)(USB_DRD_BASE + bEpIdx*4); + *reg = wRegValue; +#else __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpIdx*2u); *reg = (uint16_t)wRegValue; +#endif } /* GetENDPOINT */ -TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) { +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) { +#ifdef PMA_32BIT_ACCESS + __I uint32_t *reg = (__I uint32_t *)(USB_DRD_BASE + bEpIdx*4); +#else __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpIdx*2u); +#endif return *reg; } @@ -187,34 +240,22 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, */ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) { +#ifdef PMA_32BIT_ACCESS + return (pma32[2*bEpIdx] & 0x03FF0000) >> 16; +#else __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpIdx); return *regPtr & 0x3ffU; +#endif } TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) { +#ifdef PMA_32BIT_ACCESS + return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16; +#else __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx); return *regPtr & 0x3ffU; -} - -/** - * @brief Sets counter of rx buffer with no. of blocks. - * @param dwReg Register - * @param wCount Counter. - * @param wNBlocks no. of Blocks. - * @retval None - */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_cnt_reg(__O uint16_t * pdwReg, size_t wCount) -{ - /* We assume that the buffer size is already aligned to hardware requirements. */ - uint16_t blocksize = (wCount > 62) ? 1 : 0; - uint16_t numblocks = wCount / (blocksize ? 32 : 2); - - /* There should be no remainder in the above calculation */ - TU_ASSERT((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/); - - /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */ - *pdwReg = (blocksize << 15) | ((numblocks - blocksize) << 10); +#endif } /** @@ -233,57 +274,96 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx, pcd_set_endpoint(USBx, bEpIdx,regVal); } -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx) { - size_t total_word_offset = (((USBx)->BTABLE)>>1) + x; - total_word_offset *= PMA_STRIDE; - return &(pma[total_word_offset]); +#ifdef PMA_32BIT_ACCESS + return pma32[2*bEpIdx] & 0x0000FFFFu ; +#else + return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u); +#endif } -// Pointers to the PMA table entries (using the ARM address space) -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_address_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx) { - return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u); -} -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) -{ - return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 1u); +#ifdef PMA_32BIT_ACCESS + return pma32[2*bEpIdx + 1] & 0x0000FFFFu; +#else + return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u); +#endif } -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_address_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) { - return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u); +#ifdef PMA_32BIT_ACCESS + pma32[2*bEpIdx] = (pma32[2*bEpIdx] & 0xFFFF0000u) | (addr & 0x0000FFFCu); +#else + *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u) = addr; +#endif } -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) { - return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 3u); +#ifdef PMA_32BIT_ACCESS + pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & 0xFFFF0000u) | (addr & 0x0000FFFCu); +#else + *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u) = addr; +#endif } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { +#ifdef PMA_32BIT_ACCESS + pma32[2*bEpIdx] = (pma32[2*bEpIdx] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16); +#else __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpIdx); *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU); +#endif } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { +#ifdef PMA_32BIT_ACCESS + pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16); +#else __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpIdx); *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU); +#endif } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t blocksize, uint32_t numblocks) { - __IO uint16_t *pdwReg = pcd_ep_tx_cnt_ptr((USBx),(bEpIdx)); - wCount = pcd_aligned_buffer_size(wCount); - pcd_set_ep_cnt_reg(pdwReg, wCount); + /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */ +#ifdef PMA_32BIT_ACCESS + pma32[rxtx_idx] = (pma32[rxtx_idx] & 0x0000FFFFu) | (blocksize << 31) | ((numblocks - blocksize) << 26); +#else + __IO uint16_t *pdwReg = pcd_btable_word_ptr(USBx, rxtx_idx*2u + 1u); + *pdwReg = (blocksize << 15) | ((numblocks - blocksize) << 10); +#endif } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_bufsize(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t wCount) { - __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpIdx)); wCount = pcd_aligned_buffer_size(wCount); - pcd_set_ep_cnt_reg(pdwReg, wCount); + + /* We assume that the buffer size is already aligned to hardware requirements. */ + uint16_t blocksize = (wCount > 62) ? 1 : 0; + uint16_t numblocks = wCount / (blocksize ? 32 : 2); + + /* There should be no remainder in the above calculation */ + TU_ASSERT((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/); + + /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */ + pcd_set_ep_blsize_num_blocks(USBx, rxtx_idx, blocksize, numblocks); +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) +{ + pcd_set_ep_bufsize(USBx, 2*bEpIdx, wCount); +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) +{ + pcd_set_ep_bufsize(USBx, 2*bEpIdx + 1, wCount); } /** -- cgit v1.3.1 From 8ae4f8f0699351e5bba349ccb0fab65b557afed6 Mon Sep 17 00:00:00 2001 From: Hubert Denkmair Date: Wed, 8 Mar 2023 12:05:58 +0100 Subject: add basic STM32G0 support --- src/common/tusb_mcu.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 257d08a85..957df5e9e 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -191,6 +191,11 @@ #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 +#elif TU_CHECK_MCU(OPT_MCU_STM32G0) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_STM32 + #define TUP_DCD_ENDPOINT_MAX 8 + #elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1) #define TUP_USBIP_FSDEV #define TUP_USBIP_FSDEV_STM32 -- cgit v1.3.1 From b3ad560e629be18146fd52e32235cc2ed72dc70b Mon Sep 17 00:00:00 2001 From: Hubert Denkmair Date: Wed, 8 Mar 2023 14:22:11 +0100 Subject: fix path to stm32g0xx.h --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 686bfaa66..00791eeb7 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -83,7 +83,7 @@ #define PMA_LENGTH (1024u) #elif CFG_TUSB_MCU == OPT_MCU_STM32G0 - #include "STM32/stm32g0xx.h" + #include "stm32g0xx.h" #define PMA_32BIT_ACCESS #define PMA_LENGTH (1024u) // FIXME it is 2048, really #undef USB_PMAADDR -- cgit v1.3.1 From 2cf092464b5cfabcd0a5e507459e5658e2e0ff54 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 8 Mar 2023 22:34:54 +0700 Subject: fix freertos build with iar, format/indent link_type --- .codespell/exclude-file.txt | 5 +- examples/device/cdc_msc_freertos/Makefile | 2 +- examples/device/hid_composite_freertos/Makefile | 2 +- src/portable/renesas/link/link_type.h | 1849 ++++++++++++----------- 4 files changed, 953 insertions(+), 905 deletions(-) (limited to 'src') diff --git a/.codespell/exclude-file.txt b/.codespell/exclude-file.txt index af8265cc7..660d2e07e 100644 --- a/.codespell/exclude-file.txt +++ b/.codespell/exclude-file.txt @@ -1 +1,4 @@ - return USB0.INTSTS1.BIT.ATTCH ? true : false; + return LINK_REG->INTSTS1_b.ATTCH ? true : false; + volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */ +#define LINK_REG_INTSTS1_ATTCH_Pos (11UL) /* ATTCH (Bit 11) */ +#define LINK_REG_INTSTS1_ATTCH_Msk (0x800UL) /* ATTCH (Bitfield-Mask: 0x01) */ diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile index 2d5d0cfcc..ed3b3f0ce 100644 --- a/examples/device/cdc_msc_freertos/Makefile +++ b/examples/device/cdc_msc_freertos/Makefile @@ -30,7 +30,7 @@ SRC_C += \ $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.c)) SRC_S += \ - $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s)) + $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.s)) # include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1 # SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile index 9b9c4d1b3..f4410b202 100644 --- a/examples/device/hid_composite_freertos/Makefile +++ b/examples/device/hid_composite_freertos/Makefile @@ -29,7 +29,7 @@ SRC_C += \ $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.c)) SRC_S += \ - $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s)) + $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.s)) # include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1 # SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c diff --git a/src/portable/renesas/link/link_type.h b/src/portable/renesas/link/link_type.h index eaf0b1ec4..cb3db650a 100644 --- a/src/portable/renesas/link/link_type.h +++ b/src/portable/renesas/link/link_type.h @@ -62,25 +62,23 @@ typedef struct TU_ATTR_PACKED { }; } LINK_REG_PIPE_TR_t; /* Size = 4 (0x4) */ -TU_VERIFY_STATIC(sizeof(LINK_REG_PIPE_TR_t) == 4, "incorrect size"); - /* LINK_REG Structure */ typedef struct TU_ATTR_PACKED { union { volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */ struct { - volatile uint16_t USBE : 1; /* [0..0] USB Operation Enable */ - uint16_t : 2; + volatile uint16_t USBE : 1; /* [0..0] USB Operation Enable */ + uint16_t : 2; volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */ volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */ - volatile uint16_t DRPD : 1; /* [5..5] D+/D- Line Resistor Control */ - volatile uint16_t DCFM : 1; /* [6..6] Controller Function Select */ - uint16_t : 1; - volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */ - uint16_t : 1; - volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */ - uint16_t : 5; + volatile uint16_t DRPD : 1; /* [5..5] D+/D- Line Resistor Control */ + volatile uint16_t DCFM : 1; /* [6..6] Controller Function Select */ + uint16_t : 1; + volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */ + uint16_t : 5; } SYSCFG_b; }; @@ -88,8 +86,7 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */ struct { - volatile uint16_t - BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */ + volatile uint16_t BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */ uint16_t : 12; } BUSWAIT_b; }; @@ -98,15 +95,14 @@ typedef struct TU_ATTR_PACKED { volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */ struct { - volatile const uint16_t LNST : 2; /* [1..0] USB Data Line Status Monitor */ - volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */ - uint16_t : 2; - volatile const uint16_t - SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */ - volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */ - uint16_t : 7; + volatile const uint16_t LNST : 2; /* [1..0] USB Data Line Status Monitor */ + volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; volatile const uint16_t - OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */ + SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */ + volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + volatile const uint16_t OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */ } SYSSTS0_b; }; @@ -124,16 +120,16 @@ typedef struct TU_ATTR_PACKED { struct { volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */ - uint16_t : 1; - volatile uint16_t UACT : 1; /* [4..4] USB Bus Enable */ - volatile uint16_t RESUME : 1; /* [5..5] Resume Output */ - volatile uint16_t USBRST : 1; /* [6..6] USB Bus Reset Output */ - volatile uint16_t RWUPE : 1; /* [7..7] Wakeup Detection Enable */ - volatile uint16_t WKUP : 1; /* [8..8] Wakeup Output */ - volatile uint16_t VBUSEN : 1; /* [9..9] USB_VBUSEN Output Pin Control */ - volatile uint16_t EXICEN : 1; /* [10..10] USB_EXICEN Output Pin Control */ - volatile uint16_t HNPBTOA : 1; /* [11..11] Host Negotiation Protocol (HNP) */ - uint16_t : 4; + uint16_t : 1; + volatile uint16_t UACT : 1; /* [4..4] USB Bus Enable */ + volatile uint16_t RESUME : 1; /* [5..5] Resume Output */ + volatile uint16_t USBRST : 1; /* [6..6] USB Bus Reset Output */ + volatile uint16_t RWUPE : 1; /* [7..7] Wakeup Detection Enable */ + volatile uint16_t WKUP : 1; /* [8..8] Wakeup Output */ + volatile uint16_t VBUSEN : 1; /* [9..9] USB_VBUSEN Output Pin Control */ + volatile uint16_t EXICEN : 1; /* [10..10] USB_EXICEN Output Pin Control */ + volatile uint16_t HNPBTOA : 1; /* [11..11] Host Negotiation Protocol (HNP) */ + uint16_t : 4; } DVSTCTR0_b; }; volatile const uint16_t RESERVED; @@ -214,15 +210,15 @@ typedef struct TU_ATTR_PACKED { struct { volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */ - uint16_t : 1; - volatile uint16_t ISEL : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */ - uint16_t : 2; - volatile uint16_t BIGEND : 1; /* [8..8] CFIFO Port Endian Control */ - uint16_t : 1; - volatile uint16_t MBW : 2; /* [11..10] CFIFO Port Access Bit Width */ - uint16_t : 2; - volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */ - volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ + uint16_t : 1; + volatile uint16_t ISEL : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + volatile uint16_t BIGEND : 1; /* [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + volatile uint16_t MBW : 2; /* [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */ + volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ } CFIFOSEL_b; }; @@ -230,12 +226,11 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */ struct { - volatile const uint16_t - DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ - uint16_t : 1; - volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ - volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ + volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ + uint16_t : 1; + volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ + volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; volatile const uint32_t RESERVED6; @@ -245,15 +240,14 @@ typedef struct TU_ATTR_PACKED { struct { volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ - uint16_t : 1; - volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */ - volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */ - volatile uint16_t - DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */ - volatile uint16_t REW : 1; /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ - volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ + uint16_t : 4; + volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ + uint16_t : 1; + volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */ + volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */ + volatile uint16_t DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */ + volatile uint16_t REW : 1; /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -261,12 +255,11 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */ struct { - volatile const uint16_t - DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ - uint16_t : 1; - volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ - volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ + volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ + uint16_t : 1; + volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ + volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ } D0FIFOCTR_b; }; @@ -275,15 +268,14 @@ typedef struct TU_ATTR_PACKED { struct { volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ - uint16_t : 1; - volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */ - volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */ - volatile uint16_t - DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */ - volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */ - volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ + uint16_t : 4; + volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ + uint16_t : 1; + volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */ + volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */ + volatile uint16_t DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */ + volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */ + volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -291,12 +283,11 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */ struct { - volatile const uint16_t - DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ - uint16_t : 1; - volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ - volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ + volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ + uint16_t : 1; + volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ + volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ } D1FIFOCTR_b; }; @@ -308,11 +299,11 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */ volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */ volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */ - volatile uint16_t CTRE : 1; /* [11..11] Control Transfer Stage Transition Interrupt Enable */ - volatile uint16_t DVSE : 1; /* [12..12] Device State Transition Interrupt Enable */ - volatile uint16_t SOFE : 1; /* [13..13] Frame Number Update Interrupt Enable */ - volatile uint16_t RSME : 1; /* [14..14] Resume Interrupt Enable */ - volatile uint16_t VBSE : 1; /* [15..15] VBUS Interrupt Enable */ + volatile uint16_t CTRE : 1; /* [11..11] Control Transfer Stage Transition Interrupt Enable */ + volatile uint16_t DVSE : 1; /* [12..12] Device State Transition Interrupt Enable */ + volatile uint16_t SOFE : 1; /* [13..13] Frame Number Update Interrupt Enable */ + volatile uint16_t RSME : 1; /* [14..14] Resume Interrupt Enable */ + volatile uint16_t VBSE : 1; /* [15..15] VBUS Interrupt Enable */ } INTENB0_b; }; @@ -321,16 +312,16 @@ typedef struct TU_ATTR_PACKED { struct { volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */ - uint16_t : 3; - volatile uint16_t SACKE : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */ - volatile uint16_t SIGNE : 1; /* [5..5] Setup Transaction Error Interrupt Enable */ - volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 4; - volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */ - volatile uint16_t DTCHE : 1; /* [12..12] Disconnection Detection Interrupt Enable */ - uint16_t : 1; - volatile uint16_t BCHGE : 1; /* [14..14] USB Bus Change Interrupt Enable */ - volatile uint16_t OVRCRE : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */ + uint16_t : 3; + volatile uint16_t SACKE : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */ + volatile uint16_t SIGNE : 1; /* [5..5] Setup Transaction Error Interrupt Enable */ + volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */ + volatile uint16_t DTCHE : 1; /* [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + volatile uint16_t BCHGE : 1; /* [14..14] USB Bus Change Interrupt Enable */ + volatile uint16_t OVRCRE : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */ } INTENB1_b; }; volatile const uint16_t RESERVED7; @@ -393,12 +384,12 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */ struct { - uint16_t : 4; + uint16_t : 4; volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */ - volatile uint16_t INTL : 1; /* [5..5] Interrupt Output Sense Select */ - volatile uint16_t BRDYM : 1; /* [6..6] BRDY Interrupt Status Clear Timing */ - uint16_t : 1; - volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */ + volatile uint16_t INTL : 1; /* [5..5] Interrupt Output Sense Select */ + volatile uint16_t BRDYM : 1; /* [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */ uint16_t : 7; } SOFCFG_b; }; @@ -407,17 +398,17 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */ struct { - volatile uint16_t DIRPD : 1; /* [0..0] Power-Down Control */ + volatile uint16_t DIRPD : 1; /* [0..0] Power-Down Control */ volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */ - uint16_t : 1; - volatile uint16_t CDPEN : 1; /* [3..3] Charging Downstream Port Enable */ - volatile uint16_t CLKSEL : 2; /* [5..4] Input System Clock Frequency */ - uint16_t : 2; - volatile uint16_t REPSEL : 2; /* [9..8] Terminating Resistance Adjustment Cycle */ - uint16_t : 1; + uint16_t : 1; + volatile uint16_t CDPEN : 1; /* [3..3] Charging Downstream Port Enable */ + volatile uint16_t CLKSEL : 2; /* [5..4] Input System Clock Frequency */ + uint16_t : 2; + volatile uint16_t REPSEL : 2; /* [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; volatile uint16_t REPSTART : 1; /* [11..11] Forcibly Start Terminating Resistance Adjustment */ - uint16_t : 3; - volatile uint16_t HSEB : 1; /* [15..15] CL-Only Mode */ + uint16_t : 3; + volatile uint16_t HSEB : 1; /* [15..15] CL-Only Mode */ } PHYSET_b; }; @@ -425,18 +416,18 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */ struct { - volatile const uint16_t CTSQ : 3; /* [2..0] Control Transfer Stage */ - volatile uint16_t VALID : 1; /* [3..3] USB Request Reception */ - volatile const uint16_t DVSQ : 3; /* [6..4] Device State */ + volatile const uint16_t CTSQ : 3; /* [2..0] Control Transfer Stage */ + volatile uint16_t VALID : 1; /* [3..3] USB Request Reception */ + volatile const uint16_t DVSQ : 3; /* [6..4] Device State */ volatile const uint16_t VBSTS : 1; /* [7..7] VBUS Input Status */ - volatile const uint16_t BRDY : 1; /* [8..8] Buffer Ready Interrupt Status */ - volatile const uint16_t NRDY : 1; /* [9..9] Buffer Not Ready Interrupt Status */ - volatile const uint16_t BEMP : 1; /* [10..10] Buffer Empty Interrupt Status */ - volatile uint16_t CTRT : 1; /* [11..11] Control Transfer Stage Transition Interrupt Status */ - volatile uint16_t DVST : 1; /* [12..12] Device State Transition Interrupt Status */ - volatile uint16_t SOFR : 1; /* [13..13] Frame Number Refresh Interrupt Status */ - volatile uint16_t RESM : 1; /* [14..14] Resume Interrupt Status */ - volatile uint16_t VBINT : 1; /* [15..15] VBUS Interrupt Status */ + volatile const uint16_t BRDY : 1; /* [8..8] Buffer Ready Interrupt Status */ + volatile const uint16_t NRDY : 1; /* [9..9] Buffer Not Ready Interrupt Status */ + volatile const uint16_t BEMP : 1; /* [10..10] Buffer Empty Interrupt Status */ + volatile uint16_t CTRT : 1; /* [11..11] Control Transfer Stage Transition Interrupt Status */ + volatile uint16_t DVST : 1; /* [12..12] Device State Transition Interrupt Status */ + volatile uint16_t SOFR : 1; /* [13..13] Frame Number Refresh Interrupt Status */ + volatile uint16_t RESM : 1; /* [14..14] Resume Interrupt Status */ + volatile uint16_t VBINT : 1; /* [15..15] VBUS Interrupt Status */ } INTSTS0_b; }; @@ -445,19 +436,19 @@ typedef struct TU_ATTR_PACKED { struct { volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */ - uint16_t : 3; - volatile uint16_t SACK : 1; /* [4..4] Setup Transaction Normal Response Interrupt Status */ - volatile uint16_t SIGN : 1; /* [5..5] Setup Transaction Error Interrupt Status */ - volatile uint16_t EOFERR : 1; /* [6..6] EOF Error Detection Interrupt Status */ - uint16_t : 1; - volatile uint16_t LPMEND : 1; /* [8..8] LPM Transaction End Interrupt Status */ - volatile uint16_t L1RSMEND : 1; /* [9..9] L1 Resume End Interrupt Status */ - uint16_t : 1; - volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */ - volatile uint16_t DTCH : 1; /* [12..12] USB Disconnection Detection Interrupt Status */ - uint16_t : 1; - volatile uint16_t BCHG : 1; /* [14..14] USB Bus Change Interrupt Status */ - volatile uint16_t OVRCR : 1; /* [15..15] Overcurrent Input Change Interrupt Status */ + uint16_t : 3; + volatile uint16_t SACK : 1; /* [4..4] Setup Transaction Normal Response Interrupt Status */ + volatile uint16_t SIGN : 1; /* [5..5] Setup Transaction Error Interrupt Status */ + volatile uint16_t EOFERR : 1; /* [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + volatile uint16_t LPMEND : 1; /* [8..8] LPM Transaction End Interrupt Status */ + volatile uint16_t L1RSMEND : 1; /* [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */ + volatile uint16_t DTCH : 1; /* [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + volatile uint16_t BCHG : 1; /* [14..14] USB Bus Change Interrupt Status */ + volatile uint16_t OVRCR : 1; /* [15..15] Overcurrent Input Change Interrupt Status */ } INTSTS1_b; }; volatile const uint16_t RESERVED8; @@ -521,9 +512,9 @@ typedef struct TU_ATTR_PACKED { struct { volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */ - uint16_t : 3; - volatile uint16_t CRCE : 1; /* [14..14] Receive Data Error */ - volatile uint16_t OVRN : 1; /* [15..15] Overrun/Underrun Detection Status */ + uint16_t : 3; + volatile uint16_t CRCE : 1; /* [14..14] Receive Data Error */ + volatile uint16_t OVRN : 1; /* [15..15] Overrun/Underrun Detection Status */ } FRMNUM_b; }; @@ -532,8 +523,8 @@ typedef struct TU_ATTR_PACKED { struct { volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; - volatile uint16_t DVCHG : 1; /* [15..15] Device State Change */ + uint16_t : 12; + volatile uint16_t DVCHG : 1; /* [15..15] Device State Change */ } UFRMNUM_b; }; @@ -542,9 +533,9 @@ typedef struct TU_ATTR_PACKED { struct { volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */ - uint16_t : 1; - volatile uint16_t STSRECOV0 : 3; /* [10..8] Status Recovery */ - uint16_t : 5; + uint16_t : 1; + volatile uint16_t STSRECOV0 : 3; /* [10..8] Status Recovery */ + uint16_t : 5; } USBADDR_b; }; volatile const uint16_t RESERVED9; @@ -553,9 +544,8 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */ struct { - volatile uint16_t - BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */ - volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */ + volatile uint16_t BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */ + volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */ } USBREQ_b; }; @@ -587,12 +577,12 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */ struct { - uint16_t : 4; - volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ - uint16_t : 2; + uint16_t : 4; + volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ + uint16_t : 2; volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */ - volatile uint16_t CNTMD : 1; /* [8..8] Continuous Transfer Mode */ - uint16_t : 7; + volatile uint16_t CNTMD : 1; /* [8..8] Continuous Transfer Mode */ + uint16_t : 7; } DCPCFG_b; }; @@ -600,8 +590,8 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */ struct { - volatile uint16_t MXPS : 7; /* [6..0] Maximum Packet Size */ - uint16_t : 5; + volatile uint16_t MXPS : 7; /* [6..0] Maximum Packet Size */ + uint16_t : 5; volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ } DCPMAXP_b; }; @@ -610,18 +600,18 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */ struct { - volatile uint16_t PID : 2; /* [1..0] Response PID */ - volatile uint16_t CCPL : 1; /* [2..2] Control Transfer End Enable */ - uint16_t : 2; + volatile uint16_t PID : 2; /* [1..0] Response PID */ + volatile uint16_t CCPL : 1; /* [2..2] Control Transfer End Enable */ + uint16_t : 2; volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */ volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Monitor */ - volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */ - volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ - uint16_t : 2; - volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */ - uint16_t : 2; - volatile uint16_t SUREQ : 1; /* [14..14] Setup Token Transmission */ - volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ + volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */ + volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */ + uint16_t : 2; + volatile uint16_t SUREQ : 1; /* [14..14] Setup Token Transmission */ + volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ } DCPCTR_b; }; volatile const uint16_t RESERVED10; @@ -637,18 +627,18 @@ typedef struct TU_ATTR_PACKED { volatile const uint16_t RESERVED11; union { - volatile uint16_t PIPECFG; /* (@ 0x00000068) Pipe Configuration Register */ + volatile uint16_t PIPECFG; /* (@ 0x00000068) Pipe Configuration Register */ struct { - volatile uint16_t EPNUM : 4; /* [3..0] Endpoint Number */ - volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ - uint16_t : 2; + volatile uint16_t EPNUM : 4; /* [3..0] Endpoint Number */ + volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ + uint16_t : 2; volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */ - uint16_t : 1; - volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */ - volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */ - uint16_t : 3; - volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */ + uint16_t : 1; + volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */ + volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */ } PIPECFG_b; }; volatile const uint16_t RESERVED12; @@ -657,8 +647,8 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */ struct { - volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */ - uint16_t : 3; + volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */ + uint16_t : 3; volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ } PIPEMAXP_b; }; @@ -668,29 +658,29 @@ typedef struct TU_ATTR_PACKED { struct { volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */ - uint16_t : 9; + uint16_t : 9; volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */ - uint16_t : 3; + uint16_t : 3; } PIPEPERI_b; }; union { - volatile uint16_t PIPE_CTR[9]; /* (@ 0x00000070) Pipe [0..8] Control Register */ + volatile uint16_t PIPE_CTR[9]; /* (@ 0x00000070) Pipe [0..8] Control Register */ struct { - volatile uint16_t PID : 2; /* [1..0] Response PID */ - uint16_t : 3; - volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */ - volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Confirmation */ - volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */ - volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ - volatile uint16_t ACLRM : 1; /* [9..9] Auto Buffer Clear Mode */ - volatile uint16_t ATREPM : 1; /* [10..10] Auto Response Mode */ - uint16_t : 1; - volatile const uint16_t CSSTS : 1; /* [12..12] CSSTS Status */ - volatile uint16_t CSCLR : 1; /* [13..13] CSPLIT Status Clear */ + volatile uint16_t PID : 2; /* [1..0] Response PID */ + uint16_t : 3; + volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */ + volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Confirmation */ + volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */ + volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ + volatile uint16_t ACLRM : 1; /* [9..9] Auto Buffer Clear Mode */ + volatile uint16_t ATREPM : 1; /* [10..10] Auto Response Mode */ + uint16_t : 1; + volatile const uint16_t CSSTS : 1; /* [12..12] CSSTS Status */ + volatile uint16_t CSCLR : 1; /* [13..13] CSPLIT Status Clear */ volatile const uint16_t INBUFM : 1; /* [14..14] Transmit Buffer Monitor */ - volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ + volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ } PIPE_CTR_b[9]; }; volatile const uint16_t RESERVED13; @@ -699,22 +689,22 @@ typedef struct TU_ATTR_PACKED { volatile const uint32_t RESERVED15[3]; union { - volatile uint16_t USBBCCTRL0; /* (@ 0x000000B0) BC Control Register 0 */ + volatile uint16_t USBBCCTRL0; /* (@ 0x000000B0) BC Control Register 0 */ struct { - volatile uint16_t RPDME0 : 1; /* [0..0] D- Pin Pull-Down Control */ - volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */ + volatile uint16_t RPDME0 : 1; /* [0..0] D- Pin Pull-Down Control */ + volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */ volatile uint16_t - IDMSINKE0 : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ - volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + IDMSINKE0 : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ volatile uint16_t - IDPSINKE0 : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ - volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */ - uint16_t : 1; - volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + IDPSINKE0 : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ volatile const uint16_t CHGDETSTS0 : 1; /* [8..8] D- Pin 0.6 V Input Detection Status */ - volatile const uint16_t PDDETSTS0 : 1; /* [9..9] D+ Pin 0.6 V Input Detection Status */ - uint16_t : 6; + volatile const uint16_t PDDETSTS0 : 1; /* [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; } USBBCCTRL0_b; }; volatile const uint16_t RESERVED16; @@ -736,9 +726,9 @@ typedef struct TU_ATTR_PACKED { struct { volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */ - uint16_t : 6; - volatile uint16_t VDCEN : 1; /* [7..7] USB Regulator On/Off Control */ - uint16_t : 8; + uint16_t : 6; + volatile uint16_t VDCEN : 1; /* [7..7] USB Regulator On/Off Control */ + uint16_t : 8; } USBMC_b; }; volatile const uint16_t RESERVED20; @@ -748,9 +738,9 @@ typedef struct TU_ATTR_PACKED { struct { uint16_t : 6; - volatile uint16_t USBSPD : 2; /* [7..6] Transfer Speed of Communication Target Device */ + volatile uint16_t USBSPD : 2; /* [7..6] Transfer Speed of Communication Target Device */ volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */ - volatile uint16_t UPPHUB : 4; /* [14..11] Communication Target Connecting Hub Register */ + volatile uint16_t UPPHUB : 4; /* [14..11] Communication Target Connecting Hub Register */ uint16_t : 1; } DEVADD_b[10]; }; @@ -794,15 +784,15 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */ struct { - volatile uint16_t IDPSRCE : 1; /* [0..0] IDPSRC Control */ - volatile uint16_t IDMSINKE : 1; /* [1..1] IDMSINK Control */ - volatile uint16_t VDPSRCE : 1; /* [2..2] VDPSRC Control */ - volatile uint16_t IDPSINKE : 1; /* [3..3] IDPSINK Control */ - volatile uint16_t VDMSRCE : 1; /* [4..4] VDMSRC Control */ - volatile uint16_t DCPMODE : 1; /* [5..5] DCP Mode Control */ - uint16_t : 2; + volatile uint16_t IDPSRCE : 1; /* [0..0] IDPSRC Control */ + volatile uint16_t IDMSINKE : 1; /* [1..1] IDMSINK Control */ + volatile uint16_t VDPSRCE : 1; /* [2..2] VDPSRC Control */ + volatile uint16_t IDPSINKE : 1; /* [3..3] IDPSINK Control */ + volatile uint16_t VDMSRCE : 1; /* [4..4] VDMSRC Control */ + volatile uint16_t DCPMODE : 1; /* [5..5] DCP Mode Control */ + uint16_t : 2; volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */ - volatile const uint16_t PDDETSTS : 1; /* [9..9] PDDET Status */ + volatile const uint16_t PDDETSTS : 1; /* [9..9] PDDET Status */ uint16_t : 6; } BCCTRL_b; }; @@ -812,14 +802,13 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */ struct { - volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */ - volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */ - volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */ - volatile const uint16_t - DVSQ : 4; /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */ - volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */ - uint16_t : 2; - volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */ + volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */ + volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */ + volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */ + volatile const uint16_t DVSQ : 4; /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */ + volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */ + uint16_t : 2; + volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */ uint16_t : 1; } PL1CTRL1_b; }; @@ -830,7 +819,7 @@ typedef struct TU_ATTR_PACKED { struct { uint16_t : 8; volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */ - volatile uint16_t RWEMON : 1; /* [12..12] RWE Value Monitor */ + volatile uint16_t RWEMON : 1; /* [12..12] RWE Value Monitor */ uint16_t : 3; } PL1CTRL2_b; }; @@ -839,7 +828,7 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */ struct { - volatile uint16_t L1REQ : 1; /* [0..0] L1 Transition Request */ + volatile uint16_t L1REQ : 1; /* [0..0] L1 Transition Request */ volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */ uint16_t : 13; } HL1CTRL1_b; @@ -850,11 +839,11 @@ typedef struct TU_ATTR_PACKED { struct { volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */ - uint16_t : 4; - volatile uint16_t HIRD : 4; /* [11..8] LPM Token HIRD */ - volatile uint16_t L1RWE : 1; /* [12..12] LPM Token L1 Remote Wake Enable */ - uint16_t : 2; - volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */ + uint16_t : 4; + volatile uint16_t HIRD : 4; /* [11..8] LPM Token HIRD */ + volatile uint16_t L1RWE : 1; /* [12..12] LPM Token L1 Remote Wake Enable */ + uint16_t : 2; + volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */ } HL1CTRL2_b; }; volatile const uint32_t RESERVED25[5]; @@ -864,13 +853,10 @@ typedef struct TU_ATTR_PACKED { struct { uint32_t : 20; - volatile const uint32_t - DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */ - volatile const uint32_t - DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */ - uint32_t : 1; - volatile const uint32_t - DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */ + volatile const uint32_t DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */ + volatile const uint32_t DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */ + uint32_t : 1; + volatile const uint32_t DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */ uint32_t : 8; } DPUSR0R_b; }; @@ -880,14 +866,14 @@ typedef struct TU_ATTR_PACKED { struct { uint32_t : 4; - volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */ - volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */ - uint32_t : 1; - volatile uint32_t DVBSTSHE : 1; /* [7..7] VBUS Interrupt Enable/Clear */ - uint32_t : 12; - volatile const uint32_t DOVCAH : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */ - volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */ - uint32_t : 1; + volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */ + volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + volatile uint32_t DVBSTSHE : 1; /* [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + volatile const uint32_t DOVCAH : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */ + volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */ uint32_t : 8; } DPUSR1R_b; @@ -899,14 +885,12 @@ typedef struct TU_ATTR_PACKED { struct { volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */ volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */ - uint16_t : 2; - volatile const uint16_t - DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */ - volatile const uint16_t - DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */ - uint16_t : 2; - volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */ - volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */ + uint16_t : 2; + volatile const uint16_t DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */ + volatile const uint16_t DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */ + uint16_t : 2; + volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */ + volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */ uint16_t : 6; } DPUSR2R_b; }; @@ -915,7 +899,7 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ struct { - volatile uint16_t FIXPHY : 1; /* [0..0] USB Transceiver Control Fix */ + volatile uint16_t FIXPHY : 1; /* [0..0] USB Transceiver Control Fix */ volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */ uint16_t : 14; } DPUSRCR_b; @@ -927,22 +911,19 @@ typedef struct TU_ATTR_PACKED { DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */ struct { - volatile uint32_t SRPC0 : 1; /* [0..0] USB Single End Receiver Control */ - volatile uint32_t RPUE0 : 1; /* [1..1] DP Pull-Up Resistor Control */ - uint32_t : 1; - volatile uint32_t DRPD0 : 1; /* [3..3] D+/D- Pull-Down Resistor Control */ - volatile uint32_t FIXPHY0 : 1; /* [4..4] USB Transceiver Output Fix */ - uint32_t : 11; - volatile const uint32_t DP0 : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ - volatile const uint32_t DM0 : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */ - uint32_t : 2; - volatile const uint32_t - DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */ - volatile const uint32_t - DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */ - uint32_t : 1; - volatile const uint32_t - DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */ + volatile uint32_t SRPC0 : 1; /* [0..0] USB Single End Receiver Control */ + volatile uint32_t RPUE0 : 1; /* [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + volatile uint32_t DRPD0 : 1; /* [3..3] D+/D- Pull-Down Resistor Control */ + volatile uint32_t FIXPHY0 : 1; /* [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + volatile const uint32_t DP0 : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + volatile const uint32_t DM0 : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + volatile const uint32_t DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */ + volatile const uint32_t DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */ + uint32_t : 1; + volatile const uint32_t DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */ uint32_t : 8; } DPUSR0R_FS_b; }; @@ -951,88 +932,26 @@ typedef struct TU_ATTR_PACKED { volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */ struct { - volatile uint32_t DPINTE0 : 1; /* [0..0] USB DP Interrupt Enable/Clear */ - volatile uint32_t DMINTE0 : 1; /* [1..1] USB DM Interrupt Enable/Clear */ - uint32_t : 2; - volatile uint32_t DOVRCRAE0 : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */ - volatile uint32_t DOVRCRBE0 : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */ - uint32_t : 1; - volatile uint32_t DVBSE0 : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */ - uint32_t : 8; - volatile const uint32_t DPINT0 : 1; /* [16..16] USB DP Interrupt Source Recovery */ - volatile const uint32_t DMINT0 : 1; /* [17..17] USB DM Interrupt Source Recovery */ - uint32_t : 2; + volatile uint32_t DPINTE0 : 1; /* [0..0] USB DP Interrupt Enable/Clear */ + volatile uint32_t DMINTE0 : 1; /* [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + volatile uint32_t DOVRCRAE0 : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */ + volatile uint32_t DOVRCRBE0 : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + volatile uint32_t DVBSE0 : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + volatile const uint32_t DPINT0 : 1; /* [16..16] USB DP Interrupt Source Recovery */ + volatile const uint32_t DMINT0 : 1; /* [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; volatile const uint32_t DOVRCRA0 : 1; /* [20..20] USB OVRCURA Interrupt Source Recovery */ volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */ - uint32_t : 1; - volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 1; + volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */ uint32_t : 8; } DPUSR1R_FS_b; }; } LINK_REG_t; /* Size = 1032 (0x408) */ -TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSCFG) == 0x00000000, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BUSWAIT) == 0x00000002, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSSTS0) == 0x00000004, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PLLSTA) == 0x00000006, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DVSTCTR0) == 0x00000008, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, TESTMODE) == 0x0000000C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFO) == 0x00000014, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFO) == 0x00000018, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFO) == 0x0000001C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOSEL) == 0x00000020, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOCTR) == 0x00000022, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOSEL) == 0x00000028, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOCTR) == 0x0000002A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOSEL) == 0x0000002C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOCTR) == 0x0000002E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB0) == 0x00000030, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB1) == 0x00000032, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYENB) == 0x00000036, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYENB) == 0x00000038, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPENB) == 0x0000003A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, SOFCFG) == 0x0000003C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSET) == 0x0000003E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS0) == 0x00000040, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS1) == 0x00000042, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYSTS) == 0x00000046, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYSTS) == 0x00000048, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPSTS) == 0x0000004A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, FRMNUM) == 0x0000004C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, UFRMNUM) == 0x0000004E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBADDR) == 0x00000050, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBREQ) == 0x00000054, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBVAL) == 0x00000056, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBINDX) == 0x00000058, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBLENG) == 0x0000005A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCFG) == 0x0000005C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPMAXP) == 0x0000005E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCTR) == 0x00000060, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPESEL) == 0x00000064, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPECFG) == 0x00000068, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEMAXP) == 0x0000006C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEPERI) == 0x0000006E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_CTR) == 0x00000070, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_TR) == 0x00000090, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBBCCTRL0) == 0x000000B0, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, UCKSEL) == 0x000000C4, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBMC) == 0x000000CC, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DEVADD) == 0x000000D0, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSLEW) == 0x000000F0, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPCTRL) == 0x00000100, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPSTS) == 0x00000102, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BCCTRL) == 0x00000140, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL1) == 0x00000144, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL2) == 0x00000146, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL1) == 0x00000148, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL2) == 0x0000014A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R) == 0x00000160, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R) == 0x00000164, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR2R) == 0x00000168, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSRCR) == 0x0000016A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R_FS) == 0x00000400, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R_FS) == 0x00000404, "incorrect offset"); - TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */ TU_ATTR_BIT_FIELD_ORDER_END @@ -1040,582 +959,708 @@ TU_ATTR_BIT_FIELD_ORDER_END /* Register Bit Definitions */ /*--------------------------------------------------------------------*/ -/* PIPE_TR */ -/* E */ -#define LINK_REG_PIPE_TR_E_TRENB_Pos (9UL) /* TRENB (Bit 9) */ -#define LINK_REG_PIPE_TR_E_TRENB_Msk (0x200UL) /* TRENB (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_TR_E_TRCLR_Pos (8UL) /* TRCLR (Bit 8) */ -#define LINK_REG_PIPE_TR_E_TRCLR_Msk (0x100UL) /* TRCLR (Bitfield-Mask: 0x01) */ -/* N */ -#define LINK_REG_PIPE_TR_N_TRNCNT_Pos (0UL) /* TRNCNT (Bit 0) */ -#define LINK_REG_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /* TRNCNT (Bitfield-Mask: 0xffff) */ - -/* LINK_REG */ -/* SYSCFG */ -#define LINK_REG_SYSCFG_SCKE_Pos (10UL) /* SCKE (Bit 10) */ -#define LINK_REG_SYSCFG_SCKE_Msk (0x400UL) /* SCKE (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_CNEN_Pos (8UL) /* CNEN (Bit 8) */ -#define LINK_REG_SYSCFG_CNEN_Msk (0x100UL) /* CNEN (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_DCFM_Pos (6UL) /* DCFM (Bit 6) */ -#define LINK_REG_SYSCFG_DCFM_Msk (0x40UL) /* DCFM (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_DRPD_Pos (5UL) /* DRPD (Bit 5) */ -#define LINK_REG_SYSCFG_DRPD_Msk (0x20UL) /* DRPD (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_DPRPU_Pos (4UL) /* DPRPU (Bit 4) */ -#define LINK_REG_SYSCFG_DPRPU_Msk (0x10UL) /* DPRPU (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_DMRPU_Pos (3UL) /* DMRPU (Bit 3) */ -#define LINK_REG_SYSCFG_DMRPU_Msk (0x8UL) /* DMRPU (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_USBE_Pos (0UL) /* USBE (Bit 0) */ -#define LINK_REG_SYSCFG_USBE_Msk (0x1UL) /* USBE (Bitfield-Mask: 0x01) */ -/* BUSWAIT */ -#define LINK_REG_BUSWAIT_BWAIT_Pos (0UL) /* BWAIT (Bit 0) */ -#define LINK_REG_BUSWAIT_BWAIT_Msk (0xfUL) /* BWAIT (Bitfield-Mask: 0x0f) */ -/* SYSSTS0 */ -#define LINK_REG_SYSSTS0_OVCMON_Pos (14UL) /* OVCMON (Bit 14) */ -#define LINK_REG_SYSSTS0_OVCMON_Msk (0xc000UL) /* OVCMON (Bitfield-Mask: 0x03) */ -#define LINK_REG_SYSSTS0_HTACT_Pos (6UL) /* HTACT (Bit 6) */ -#define LINK_REG_SYSSTS0_HTACT_Msk (0x40UL) /* HTACT (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSSTS0_SOFEA_Pos (5UL) /* SOFEA (Bit 5) */ -#define LINK_REG_SYSSTS0_SOFEA_Msk (0x20UL) /* SOFEA (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSSTS0_IDMON_Pos (2UL) /* IDMON (Bit 2) */ -#define LINK_REG_SYSSTS0_IDMON_Msk (0x4UL) /* IDMON (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSSTS0_LNST_Pos (0UL) /* LNST (Bit 0) */ -#define LINK_REG_SYSSTS0_LNST_Msk (0x3UL) /* LNST (Bitfield-Mask: 0x03) */ -/* PLLSTA */ -#define LINK_REG_PLLSTA_PLLLOCK_Pos (0UL) /* PLLLOCK (Bit 0) */ -#define LINK_REG_PLLSTA_PLLLOCK_Msk (0x1UL) /* PLLLOCK (Bitfield-Mask: 0x01) */ -/* DVSTCTR0 */ -#define LINK_REG_DVSTCTR0_HNPBTOA_Pos (11UL) /* HNPBTOA (Bit 11) */ -#define LINK_REG_DVSTCTR0_HNPBTOA_Msk (0x800UL) /* HNPBTOA (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_EXICEN_Pos (10UL) /* EXICEN (Bit 10) */ -#define LINK_REG_DVSTCTR0_EXICEN_Msk (0x400UL) /* EXICEN (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_VBUSEN_Pos (9UL) /* VBUSEN (Bit 9) */ -#define LINK_REG_DVSTCTR0_VBUSEN_Msk (0x200UL) /* VBUSEN (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_WKUP_Pos (8UL) /* WKUP (Bit 8) */ -#define LINK_REG_DVSTCTR0_WKUP_Msk (0x100UL) /* WKUP (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_RWUPE_Pos (7UL) /* RWUPE (Bit 7) */ -#define LINK_REG_DVSTCTR0_RWUPE_Msk (0x80UL) /* RWUPE (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_USBRST_Pos (6UL) /* USBRST (Bit 6) */ -#define LINK_REG_DVSTCTR0_USBRST_Msk (0x40UL) /* USBRST (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_RESUME_Pos (5UL) /* RESUME (Bit 5) */ -#define LINK_REG_DVSTCTR0_RESUME_Msk (0x20UL) /* RESUME (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_UACT_Pos (4UL) /* UACT (Bit 4) */ -#define LINK_REG_DVSTCTR0_UACT_Msk (0x10UL) /* UACT (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_RHST_Pos (0UL) /* RHST (Bit 0) */ -#define LINK_REG_DVSTCTR0_RHST_Msk (0x7UL) /* RHST (Bitfield-Mask: 0x07) */ -/* TESTMODE */ -#define LINK_REG_TESTMODE_UTST_Pos (0UL) /* UTST (Bit 0) */ -#define LINK_REG_TESTMODE_UTST_Msk (0xfUL) /* UTST (Bitfield-Mask: 0x0f) */ -/* CFIFOSEL */ -#define LINK_REG_CFIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ -#define LINK_REG_CFIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ -#define LINK_REG_CFIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ -#define LINK_REG_CFIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ -#define LINK_REG_CFIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ -#define LINK_REG_CFIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOSEL_ISEL_Pos (5UL) /* ISEL (Bit 5) */ -#define LINK_REG_CFIFOSEL_ISEL_Msk (0x20UL) /* ISEL (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ -#define LINK_REG_CFIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ -/* CFIFOCTR */ -#define LINK_REG_CFIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ -#define LINK_REG_CFIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ -#define LINK_REG_CFIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ -#define LINK_REG_CFIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ -#define LINK_REG_CFIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ -/* D0FIFOSEL */ -#define LINK_REG_D0FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ -#define LINK_REG_D0FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ -#define LINK_REG_D0FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ -#define LINK_REG_D0FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ -#define LINK_REG_D0FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ -#define LINK_REG_D0FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ -#define LINK_REG_D0FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ -#define LINK_REG_D0FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ -#define LINK_REG_D0FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ -/* D0FIFOCTR */ -#define LINK_REG_D0FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ -#define LINK_REG_D0FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ -#define LINK_REG_D0FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ -#define LINK_REG_D0FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ -#define LINK_REG_D0FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ -/* D1FIFOSEL */ -#define LINK_REG_D1FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ -#define LINK_REG_D1FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ -#define LINK_REG_D1FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ -#define LINK_REG_D1FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ -#define LINK_REG_D1FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ -#define LINK_REG_D1FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ -#define LINK_REG_D1FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ -#define LINK_REG_D1FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ -#define LINK_REG_D1FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ -/* D1FIFOCTR */ -#define LINK_REG_D1FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ -#define LINK_REG_D1FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ -#define LINK_REG_D1FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ -#define LINK_REG_D1FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ -#define LINK_REG_D1FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ -/* INTENB0 */ -#define LINK_REG_INTENB0_VBSE_Pos (15UL) /* VBSE (Bit 15) */ -#define LINK_REG_INTENB0_VBSE_Msk (0x8000UL) /* VBSE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_RSME_Pos (14UL) /* RSME (Bit 14) */ -#define LINK_REG_INTENB0_RSME_Msk (0x4000UL) /* RSME (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_SOFE_Pos (13UL) /* SOFE (Bit 13) */ -#define LINK_REG_INTENB0_SOFE_Msk (0x2000UL) /* SOFE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_DVSE_Pos (12UL) /* DVSE (Bit 12) */ -#define LINK_REG_INTENB0_DVSE_Msk (0x1000UL) /* DVSE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_CTRE_Pos (11UL) /* CTRE (Bit 11) */ -#define LINK_REG_INTENB0_CTRE_Msk (0x800UL) /* CTRE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_BEMPE_Pos (10UL) /* BEMPE (Bit 10) */ -#define LINK_REG_INTENB0_BEMPE_Msk (0x400UL) /* BEMPE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_NRDYE_Pos (9UL) /* NRDYE (Bit 9) */ -#define LINK_REG_INTENB0_NRDYE_Msk (0x200UL) /* NRDYE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_BRDYE_Pos (8UL) /* BRDYE (Bit 8) */ -#define LINK_REG_INTENB0_BRDYE_Msk (0x100UL) /* BRDYE (Bitfield-Mask: 0x01) */ -/* INTENB1 */ -#define LINK_REG_INTENB1_OVRCRE_Pos (15UL) /* OVRCRE (Bit 15) */ -#define LINK_REG_INTENB1_OVRCRE_Msk (0x8000UL) /* OVRCRE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_BCHGE_Pos (14UL) /* BCHGE (Bit 14) */ -#define LINK_REG_INTENB1_BCHGE_Msk (0x4000UL) /* BCHGE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_DTCHE_Pos (12UL) /* DTCHE (Bit 12) */ -#define LINK_REG_INTENB1_DTCHE_Msk (0x1000UL) /* DTCHE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_ATTCHE_Pos (11UL) /* ATTCHE (Bit 11) */ -#define LINK_REG_INTENB1_ATTCHE_Msk (0x800UL) /* ATTCHE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_EOFERRE_Pos (6UL) /* EOFERRE (Bit 6) */ -#define LINK_REG_INTENB1_EOFERRE_Msk (0x40UL) /* EOFERRE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_SIGNE_Pos (5UL) /* SIGNE (Bit 5) */ -#define LINK_REG_INTENB1_SIGNE_Msk (0x20UL) /* SIGNE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_SACKE_Pos (4UL) /* SACKE (Bit 4) */ -#define LINK_REG_INTENB1_SACKE_Msk (0x10UL) /* SACKE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_PDDETINTE0_Pos (0UL) /* PDDETINTE0 (Bit 0) */ -#define LINK_REG_INTENB1_PDDETINTE0_Msk (0x1UL) /* PDDETINTE0 (Bitfield-Mask: 0x01) */ -/* BRDYENB */ -#define LINK_REG_BRDYENB_PIPEBRDYE_Pos (0UL) /* PIPEBRDYE (Bit 0) */ -#define LINK_REG_BRDYENB_PIPEBRDYE_Msk (0x1UL) /* PIPEBRDYE (Bitfield-Mask: 0x01) */ -/* NRDYENB */ -#define LINK_REG_NRDYENB_PIPENRDYE_Pos (0UL) /* PIPENRDYE (Bit 0) */ -#define LINK_REG_NRDYENB_PIPENRDYE_Msk (0x1UL) /* PIPENRDYE (Bitfield-Mask: 0x01) */ -/* BEMPENB */ -#define LINK_REG_BEMPENB_PIPEBEMPE_Pos (0UL) /* PIPEBEMPE (Bit 0) */ -#define LINK_REG_BEMPENB_PIPEBEMPE_Msk (0x1UL) /* PIPEBEMPE (Bitfield-Mask: 0x01) */ -/* SOFCFG */ -#define LINK_REG_SOFCFG_TRNENSEL_Pos (8UL) /* TRNENSEL (Bit 8) */ -#define LINK_REG_SOFCFG_TRNENSEL_Msk (0x100UL) /* TRNENSEL (Bitfield-Mask: 0x01) */ -#define LINK_REG_SOFCFG_BRDYM_Pos (6UL) /* BRDYM (Bit 6) */ -#define LINK_REG_SOFCFG_BRDYM_Msk (0x40UL) /* BRDYM (Bitfield-Mask: 0x01) */ -#define LINK_REG_SOFCFG_INTL_Pos (5UL) /* INTL (Bit 5) */ -#define LINK_REG_SOFCFG_INTL_Msk (0x20UL) /* INTL (Bitfield-Mask: 0x01) */ -#define LINK_REG_SOFCFG_EDGESTS_Pos (4UL) /* EDGESTS (Bit 4) */ -#define LINK_REG_SOFCFG_EDGESTS_Msk (0x10UL) /* EDGESTS (Bitfield-Mask: 0x01) */ -/* PHYSET */ -#define LINK_REG_PHYSET_HSEB_Pos (15UL) /* HSEB (Bit 15) */ -#define LINK_REG_PHYSET_HSEB_Msk (0x8000UL) /* HSEB (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSET_REPSTART_Pos (11UL) /* REPSTART (Bit 11) */ -#define LINK_REG_PHYSET_REPSTART_Msk (0x800UL) /* REPSTART (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSET_REPSEL_Pos (8UL) /* REPSEL (Bit 8) */ -#define LINK_REG_PHYSET_REPSEL_Msk (0x300UL) /* REPSEL (Bitfield-Mask: 0x03) */ -#define LINK_REG_PHYSET_CLKSEL_Pos (4UL) /* CLKSEL (Bit 4) */ -#define LINK_REG_PHYSET_CLKSEL_Msk (0x30UL) /* CLKSEL (Bitfield-Mask: 0x03) */ -#define LINK_REG_PHYSET_CDPEN_Pos (3UL) /* CDPEN (Bit 3) */ -#define LINK_REG_PHYSET_CDPEN_Msk (0x8UL) /* CDPEN (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSET_PLLRESET_Pos (1UL) /* PLLRESET (Bit 1) */ -#define LINK_REG_PHYSET_PLLRESET_Msk (0x2UL) /* PLLRESET (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSET_DIRPD_Pos (0UL) /* DIRPD (Bit 0) */ -#define LINK_REG_PHYSET_DIRPD_Msk (0x1UL) /* DIRPD (Bitfield-Mask: 0x01) */ -/* INTSTS0 */ -#define LINK_REG_INTSTS0_VBINT_Pos (15UL) /* VBINT (Bit 15) */ -#define LINK_REG_INTSTS0_VBINT_Msk (0x8000UL) /* VBINT (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_RESM_Pos (14UL) /* RESM (Bit 14) */ -#define LINK_REG_INTSTS0_RESM_Msk (0x4000UL) /* RESM (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_SOFR_Pos (13UL) /* SOFR (Bit 13) */ -#define LINK_REG_INTSTS0_SOFR_Msk (0x2000UL) /* SOFR (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_DVST_Pos (12UL) /* DVST (Bit 12) */ -#define LINK_REG_INTSTS0_DVST_Msk (0x1000UL) /* DVST (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_CTRT_Pos (11UL) /* CTRT (Bit 11) */ -#define LINK_REG_INTSTS0_CTRT_Msk (0x800UL) /* CTRT (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_BEMP_Pos (10UL) /* BEMP (Bit 10) */ -#define LINK_REG_INTSTS0_BEMP_Msk (0x400UL) /* BEMP (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_NRDY_Pos (9UL) /* NRDY (Bit 9) */ -#define LINK_REG_INTSTS0_NRDY_Msk (0x200UL) /* NRDY (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_BRDY_Pos (8UL) /* BRDY (Bit 8) */ -#define LINK_REG_INTSTS0_BRDY_Msk (0x100UL) /* BRDY (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_VBSTS_Pos (7UL) /* VBSTS (Bit 7) */ -#define LINK_REG_INTSTS0_VBSTS_Msk (0x80UL) /* VBSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ -#define LINK_REG_INTSTS0_DVSQ_Msk (0x70UL) /* DVSQ (Bitfield-Mask: 0x07) */ -#define LINK_REG_INTSTS0_VALID_Pos (3UL) /* VALID (Bit 3) */ -#define LINK_REG_INTSTS0_VALID_Msk (0x8UL) /* VALID (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_CTSQ_Pos (0UL) /* CTSQ (Bit 0) */ -#define LINK_REG_INTSTS0_CTSQ_Msk (0x7UL) /* CTSQ (Bitfield-Mask: 0x07) */ -/* INTSTS1 */ -#define LINK_REG_INTSTS1_OVRCR_Pos (15UL) /* OVRCR (Bit 15) */ -#define LINK_REG_INTSTS1_OVRCR_Msk (0x8000UL) /* OVRCR (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_BCHG_Pos (14UL) /* BCHG (Bit 14) */ -#define LINK_REG_INTSTS1_BCHG_Msk (0x4000UL) /* BCHG (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_DTCH_Pos (12UL) /* DTCH (Bit 12) */ -#define LINK_REG_INTSTS1_DTCH_Msk (0x1000UL) /* DTCH (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_ATTCH_Pos (11UL) /* ATTCH (Bit 11) */ -#define LINK_REG_INTSTS1_ATTCH_Msk (0x800UL) /* ATTCH (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_L1RSMEND_Pos (9UL) /* L1RSMEND (Bit 9) */ -#define LINK_REG_INTSTS1_L1RSMEND_Msk (0x200UL) /* L1RSMEND (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_LPMEND_Pos (8UL) /* LPMEND (Bit 8) */ -#define LINK_REG_INTSTS1_LPMEND_Msk (0x100UL) /* LPMEND (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_EOFERR_Pos (6UL) /* EOFERR (Bit 6) */ -#define LINK_REG_INTSTS1_EOFERR_Msk (0x40UL) /* EOFERR (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_SIGN_Pos (5UL) /* SIGN (Bit 5) */ -#define LINK_REG_INTSTS1_SIGN_Msk (0x20UL) /* SIGN (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_SACK_Pos (4UL) /* SACK (Bit 4) */ -#define LINK_REG_INTSTS1_SACK_Msk (0x10UL) /* SACK (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_PDDETINT0_Pos (0UL) /* PDDETINT0 (Bit 0) */ -#define LINK_REG_INTSTS1_PDDETINT0_Msk (0x1UL) /* PDDETINT0 (Bitfield-Mask: 0x01) */ -/* BRDYSTS */ -#define LINK_REG_BRDYSTS_PIPEBRDY_Pos (0UL) /* PIPEBRDY (Bit 0) */ -#define LINK_REG_BRDYSTS_PIPEBRDY_Msk (0x1UL) /* PIPEBRDY (Bitfield-Mask: 0x01) */ -/* NRDYSTS */ -#define LINK_REG_NRDYSTS_PIPENRDY_Pos (0UL) /* PIPENRDY (Bit 0) */ -#define LINK_REG_NRDYSTS_PIPENRDY_Msk (0x1UL) /* PIPENRDY (Bitfield-Mask: 0x01) */ -/* BEMPSTS */ -#define LINK_REG_BEMPSTS_PIPEBEMP_Pos (0UL) /* PIPEBEMP (Bit 0) */ -#define LINK_REG_BEMPSTS_PIPEBEMP_Msk (0x1UL) /* PIPEBEMP (Bitfield-Mask: 0x01) */ -/* FRMNUM */ -#define LINK_REG_FRMNUM_OVRN_Pos (15UL) /* OVRN (Bit 15) */ -#define LINK_REG_FRMNUM_OVRN_Msk (0x8000UL) /* OVRN (Bitfield-Mask: 0x01) */ -#define LINK_REG_FRMNUM_CRCE_Pos (14UL) /* CRCE (Bit 14) */ -#define LINK_REG_FRMNUM_CRCE_Msk (0x4000UL) /* CRCE (Bitfield-Mask: 0x01) */ -#define LINK_REG_FRMNUM_FRNM_Pos (0UL) /* FRNM (Bit 0) */ -#define LINK_REG_FRMNUM_FRNM_Msk (0x7ffUL) /* FRNM (Bitfield-Mask: 0x7ff) */ -/* UFRMNUM */ -#define LINK_REG_UFRMNUM_DVCHG_Pos (15UL) /* DVCHG (Bit 15) */ -#define LINK_REG_UFRMNUM_DVCHG_Msk (0x8000UL) /* DVCHG (Bitfield-Mask: 0x01) */ -#define LINK_REG_UFRMNUM_UFRNM_Pos (0UL) /* UFRNM (Bit 0) */ -#define LINK_REG_UFRMNUM_UFRNM_Msk (0x7UL) /* UFRNM (Bitfield-Mask: 0x07) */ -/* USBADDR */ -#define LINK_REG_USBADDR_STSRECOV0_Pos (8UL) /* STSRECOV0 (Bit 8) */ -#define LINK_REG_USBADDR_STSRECOV0_Msk (0x700UL) /* STSRECOV0 (Bitfield-Mask: 0x07) */ -#define LINK_REG_USBADDR_USBADDR_Pos (0UL) /* USBADDR (Bit 0) */ -#define LINK_REG_USBADDR_USBADDR_Msk (0x7fUL) /* USBADDR (Bitfield-Mask: 0x7f) */ -/* USBREQ */ -#define LINK_REG_USBREQ_BREQUEST_Pos (8UL) /* BREQUEST (Bit 8) */ -#define LINK_REG_USBREQ_BREQUEST_Msk (0xff00UL) /* BREQUEST (Bitfield-Mask: 0xff) */ -#define LINK_REG_USBREQ_BMREQUESTTYPE_Pos (0UL) /* BMREQUESTTYPE (Bit 0) */ -#define LINK_REG_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */ -/* USBVAL */ -#define LINK_REG_USBVAL_WVALUE_Pos (0UL) /* WVALUE (Bit 0) */ -#define LINK_REG_USBVAL_WVALUE_Msk (0xffffUL) /* WVALUE (Bitfield-Mask: 0xffff) */ -/* USBINDX */ -#define LINK_REG_USBINDX_WINDEX_Pos (0UL) /* WINDEX (Bit 0) */ -#define LINK_REG_USBINDX_WINDEX_Msk (0xffffUL) /* WINDEX (Bitfield-Mask: 0xffff) */ -/* USBLENG */ -#define LINK_REG_USBLENG_WLENGTH_Pos (0UL) /* WLENGTH (Bit 0) */ -#define LINK_REG_USBLENG_WLENGTH_Msk (0xffffUL) /* WLENGTH (Bitfield-Mask: 0xffff) */ -/* DCPCFG */ -#define LINK_REG_DCPCFG_CNTMD_Pos (8UL) /* CNTMD (Bit 8) */ -#define LINK_REG_DCPCFG_CNTMD_Msk (0x100UL) /* CNTMD (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ -#define LINK_REG_DCPCFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCFG_DIR_Pos (4UL) /* DIR (Bit 4) */ -#define LINK_REG_DCPCFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ -/* DCPMAXP */ -#define LINK_REG_DCPMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ -#define LINK_REG_DCPMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ -#define LINK_REG_DCPMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ -#define LINK_REG_DCPMAXP_MXPS_Msk (0x7fUL) /* MXPS (Bitfield-Mask: 0x7f) */ -/* DCPCTR */ -#define LINK_REG_DCPCTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ -#define LINK_REG_DCPCTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_SUREQ_Pos (14UL) /* SUREQ (Bit 14) */ -#define LINK_REG_DCPCTR_SUREQ_Msk (0x4000UL) /* SUREQ (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_SUREQCLR_Pos (11UL) /* SUREQCLR (Bit 11) */ -#define LINK_REG_DCPCTR_SUREQCLR_Msk (0x800UL) /* SUREQCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ -#define LINK_REG_DCPCTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ -#define LINK_REG_DCPCTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ -#define LINK_REG_DCPCTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ -#define LINK_REG_DCPCTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_CCPL_Pos (2UL) /* CCPL (Bit 2) */ -#define LINK_REG_DCPCTR_CCPL_Msk (0x4UL) /* CCPL (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_PID_Pos (0UL) /* PID (Bit 0) */ -#define LINK_REG_DCPCTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ -/* PIPESEL */ -#define LINK_REG_PIPESEL_PIPESEL_Pos (0UL) /* PIPESEL (Bit 0) */ -#define LINK_REG_PIPESEL_PIPESEL_Msk (0xfUL) /* PIPESEL (Bitfield-Mask: 0x0f) */ -/* PIPECFG */ -#define LINK_REG_PIPECFG_TYPE_Pos (14UL) /* TYPE (Bit 14) */ -#define LINK_REG_PIPECFG_TYPE_Msk (0xc000UL) /* TYPE (Bitfield-Mask: 0x03) */ -#define LINK_REG_PIPECFG_BFRE_Pos (10UL) /* BFRE (Bit 10) */ -#define LINK_REG_PIPECFG_BFRE_Msk (0x400UL) /* BFRE (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPECFG_DBLB_Pos (9UL) /* DBLB (Bit 9) */ -#define LINK_REG_PIPECFG_DBLB_Msk (0x200UL) /* DBLB (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPECFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ -#define LINK_REG_PIPECFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPECFG_DIR_Pos (4UL) /* DIR (Bit 4) */ -#define LINK_REG_PIPECFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPECFG_EPNUM_Pos (0UL) /* EPNUM (Bit 0) */ -#define LINK_REG_PIPECFG_EPNUM_Msk (0xfUL) /* EPNUM (Bitfield-Mask: 0x0f) */ -/* PIPEMAXP */ -#define LINK_REG_PIPEMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ -#define LINK_REG_PIPEMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ -#define LINK_REG_PIPEMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ -#define LINK_REG_PIPEMAXP_MXPS_Msk (0x1ffUL) /* MXPS (Bitfield-Mask: 0x1ff) */ -/* PIPEPERI */ -#define LINK_REG_PIPEPERI_IFIS_Pos (12UL) /* IFIS (Bit 12) */ -#define LINK_REG_PIPEPERI_IFIS_Msk (0x1000UL) /* IFIS (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPEPERI_IITV_Pos (0UL) /* IITV (Bit 0) */ -#define LINK_REG_PIPEPERI_IITV_Msk (0x7UL) /* IITV (Bitfield-Mask: 0x07) */ -/* PIPE_CTR */ -#define LINK_REG_PIPE_CTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ -#define LINK_REG_PIPE_CTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_INBUFM_Pos (14UL) /* INBUFM (Bit 14) */ -#define LINK_REG_PIPE_CTR_INBUFM_Msk (0x4000UL) /* INBUFM (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_CSCLR_Pos (13UL) /* CSCLR (Bit 13) */ -#define LINK_REG_PIPE_CTR_CSCLR_Msk (0x2000UL) /* CSCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_CSSTS_Pos (12UL) /* CSSTS (Bit 12) */ -#define LINK_REG_PIPE_CTR_CSSTS_Msk (0x1000UL) /* CSSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_ATREPM_Pos (10UL) /* ATREPM (Bit 10) */ -#define LINK_REG_PIPE_CTR_ATREPM_Msk (0x400UL) /* ATREPM (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_ACLRM_Pos (9UL) /* ACLRM (Bit 9) */ -#define LINK_REG_PIPE_CTR_ACLRM_Msk (0x200UL) /* ACLRM (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ -#define LINK_REG_PIPE_CTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ -#define LINK_REG_PIPE_CTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ -#define LINK_REG_PIPE_CTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ -#define LINK_REG_PIPE_CTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_PID_Pos (0UL) /* PID (Bit 0) */ -#define LINK_REG_PIPE_CTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ -/* DEVADD */ -#define LINK_REG_DEVADD_UPPHUB_Pos (11UL) /* UPPHUB (Bit 11) */ -#define LINK_REG_DEVADD_UPPHUB_Msk (0x7800UL) /* UPPHUB (Bitfield-Mask: 0x0f) */ -#define LINK_REG_DEVADD_HUBPORT_Pos (8UL) /* HUBPORT (Bit 8) */ -#define LINK_REG_DEVADD_HUBPORT_Msk (0x700UL) /* HUBPORT (Bitfield-Mask: 0x07) */ -#define LINK_REG_DEVADD_USBSPD_Pos (6UL) /* USBSPD (Bit 6) */ -#define LINK_REG_DEVADD_USBSPD_Msk (0xc0UL) /* USBSPD (Bitfield-Mask: 0x03) */ -/* USBBCCTRL0 */ -#define LINK_REG_USBBCCTRL0_PDDETSTS0_Pos (9UL) /* PDDETSTS0 (Bit 9) */ -#define LINK_REG_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /* PDDETSTS0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /* CHGDETSTS0 (Bit 8) */ -#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /* CHGDETSTS0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_BATCHGE0_Pos (7UL) /* BATCHGE0 (Bit 7) */ -#define LINK_REG_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /* BATCHGE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_VDMSRCE0_Pos (5UL) /* VDMSRCE0 (Bit 5) */ -#define LINK_REG_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /* VDMSRCE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_IDPSINKE0_Pos (4UL) /* IDPSINKE0 (Bit 4) */ -#define LINK_REG_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /* IDPSINKE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_VDPSRCE0_Pos (3UL) /* VDPSRCE0 (Bit 3) */ -#define LINK_REG_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /* VDPSRCE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_IDMSINKE0_Pos (2UL) /* IDMSINKE0 (Bit 2) */ -#define LINK_REG_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /* IDMSINKE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_IDPSRCE0_Pos (1UL) /* IDPSRCE0 (Bit 1) */ -#define LINK_REG_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /* IDPSRCE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_RPDME0_Pos (0UL) /* RPDME0 (Bit 0) */ -#define LINK_REG_USBBCCTRL0_RPDME0_Msk (0x1UL) /* RPDME0 (Bitfield-Mask: 0x01) */ -/* UCKSEL */ -#define LINK_REG_UCKSEL_UCKSELC_Pos (0UL) /* UCKSELC (Bit 0) */ -#define LINK_REG_UCKSEL_UCKSELC_Msk (0x1UL) /* UCKSELC (Bitfield-Mask: 0x01) */ -/* USBMC */ -#define LINK_REG_USBMC_VDCEN_Pos (7UL) /* VDCEN (Bit 7) */ -#define LINK_REG_USBMC_VDCEN_Msk (0x80UL) /* VDCEN (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBMC_VDDUSBE_Pos (0UL) /* VDDUSBE (Bit 0) */ -#define LINK_REG_USBMC_VDDUSBE_Msk (0x1UL) /* VDDUSBE (Bitfield-Mask: 0x01) */ -/* PHYSLEW */ -#define LINK_REG_PHYSLEW_SLEWF01_Pos (3UL) /* SLEWF01 (Bit 3) */ -#define LINK_REG_PHYSLEW_SLEWF01_Msk (0x8UL) /* SLEWF01 (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSLEW_SLEWF00_Pos (2UL) /* SLEWF00 (Bit 2) */ -#define LINK_REG_PHYSLEW_SLEWF00_Msk (0x4UL) /* SLEWF00 (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSLEW_SLEWR01_Pos (1UL) /* SLEWR01 (Bit 1) */ -#define LINK_REG_PHYSLEW_SLEWR01_Msk (0x2UL) /* SLEWR01 (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSLEW_SLEWR00_Pos (0UL) /* SLEWR00 (Bit 0) */ -#define LINK_REG_PHYSLEW_SLEWR00_Msk (0x1UL) /* SLEWR00 (Bitfield-Mask: 0x01) */ -/* LPCTRL */ -#define LINK_REG_LPCTRL_HWUPM_Pos (7UL) /* HWUPM (Bit 7) */ -#define LINK_REG_LPCTRL_HWUPM_Msk (0x80UL) /* HWUPM (Bitfield-Mask: 0x01) */ -/* LPSTS */ -#define LINK_REG_LPSTS_SUSPENDM_Pos (14UL) /* SUSPENDM (Bit 14) */ -#define LINK_REG_LPSTS_SUSPENDM_Msk (0x4000UL) /* SUSPENDM (Bitfield-Mask: 0x01) */ -/* BCCTRL */ -#define LINK_REG_BCCTRL_PDDETSTS_Pos (9UL) /* PDDETSTS (Bit 9) */ -#define LINK_REG_BCCTRL_PDDETSTS_Msk (0x200UL) /* PDDETSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_CHGDETSTS_Pos (8UL) /* CHGDETSTS (Bit 8) */ -#define LINK_REG_BCCTRL_CHGDETSTS_Msk (0x100UL) /* CHGDETSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_DCPMODE_Pos (5UL) /* DCPMODE (Bit 5) */ -#define LINK_REG_BCCTRL_DCPMODE_Msk (0x20UL) /* DCPMODE (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_VDMSRCE_Pos (4UL) /* VDMSRCE (Bit 4) */ -#define LINK_REG_BCCTRL_VDMSRCE_Msk (0x10UL) /* VDMSRCE (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_IDPSINKE_Pos (3UL) /* IDPSINKE (Bit 3) */ -#define LINK_REG_BCCTRL_IDPSINKE_Msk (0x8UL) /* IDPSINKE (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_VDPSRCE_Pos (2UL) /* VDPSRCE (Bit 2) */ -#define LINK_REG_BCCTRL_VDPSRCE_Msk (0x4UL) /* VDPSRCE (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_IDMSINKE_Pos (1UL) /* IDMSINKE (Bit 1) */ -#define LINK_REG_BCCTRL_IDMSINKE_Msk (0x2UL) /* IDMSINKE (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_IDPSRCE_Pos (0UL) /* IDPSRCE (Bit 0) */ -#define LINK_REG_BCCTRL_IDPSRCE_Msk (0x1UL) /* IDPSRCE (Bitfield-Mask: 0x01) */ -/* PL1CTRL1 */ -#define LINK_REG_PL1CTRL1_L1EXTMD_Pos (14UL) /* L1EXTMD (Bit 14) */ -#define LINK_REG_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /* L1EXTMD (Bitfield-Mask: 0x01) */ -#define LINK_REG_PL1CTRL1_HIRDTHR_Pos (8UL) /* HIRDTHR (Bit 8) */ -#define LINK_REG_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /* HIRDTHR (Bitfield-Mask: 0x0f) */ -#define LINK_REG_PL1CTRL1_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ -#define LINK_REG_PL1CTRL1_DVSQ_Msk (0xf0UL) /* DVSQ (Bitfield-Mask: 0x0f) */ -#define LINK_REG_PL1CTRL1_L1NEGOMD_Pos (3UL) /* L1NEGOMD (Bit 3) */ -#define LINK_REG_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /* L1NEGOMD (Bitfield-Mask: 0x01) */ -#define LINK_REG_PL1CTRL1_L1RESPMD_Pos (1UL) /* L1RESPMD (Bit 1) */ -#define LINK_REG_PL1CTRL1_L1RESPMD_Msk (0x6UL) /* L1RESPMD (Bitfield-Mask: 0x03) */ -#define LINK_REG_PL1CTRL1_L1RESPEN_Pos (0UL) /* L1RESPEN (Bit 0) */ -#define LINK_REG_PL1CTRL1_L1RESPEN_Msk (0x1UL) /* L1RESPEN (Bitfield-Mask: 0x01) */ -/* PL1CTRL2 */ -#define LINK_REG_PL1CTRL2_RWEMON_Pos (12UL) /* RWEMON (Bit 12) */ -#define LINK_REG_PL1CTRL2_RWEMON_Msk (0x1000UL) /* RWEMON (Bitfield-Mask: 0x01) */ -#define LINK_REG_PL1CTRL2_HIRDMON_Pos (8UL) /* HIRDMON (Bit 8) */ -#define LINK_REG_PL1CTRL2_HIRDMON_Msk (0xf00UL) /* HIRDMON (Bitfield-Mask: 0x0f) */ -/* HL1CTRL1 */ -#define LINK_REG_HL1CTRL1_L1STATUS_Pos (1UL) /* L1STATUS (Bit 1) */ -#define LINK_REG_HL1CTRL1_L1STATUS_Msk (0x6UL) /* L1STATUS (Bitfield-Mask: 0x03) */ -#define LINK_REG_HL1CTRL1_L1REQ_Pos (0UL) /* L1REQ (Bit 0) */ -#define LINK_REG_HL1CTRL1_L1REQ_Msk (0x1UL) /* L1REQ (Bitfield-Mask: 0x01) */ -/* HL1CTRL2 */ -#define LINK_REG_HL1CTRL2_BESL_Pos (15UL) /* BESL (Bit 15) */ -#define LINK_REG_HL1CTRL2_BESL_Msk (0x8000UL) /* BESL (Bitfield-Mask: 0x01) */ -#define LINK_REG_HL1CTRL2_L1RWE_Pos (12UL) /* L1RWE (Bit 12) */ -#define LINK_REG_HL1CTRL2_L1RWE_Msk (0x1000UL) /* L1RWE (Bitfield-Mask: 0x01) */ -#define LINK_REG_HL1CTRL2_HIRD_Pos (8UL) /* HIRD (Bit 8) */ -#define LINK_REG_HL1CTRL2_HIRD_Msk (0xf00UL) /* HIRD (Bitfield-Mask: 0x0f) */ -#define LINK_REG_HL1CTRL2_L1ADDR_Pos (0UL) /* L1ADDR (Bit 0) */ -#define LINK_REG_HL1CTRL2_L1ADDR_Msk (0xfUL) /* L1ADDR (Bitfield-Mask: 0x0f) */ -/* DPUSR0R */ -#define LINK_REG_DPUSR0R_DVBSTSHM_Pos (23UL) /* DVBSTSHM (Bit 23) */ -#define LINK_REG_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_DOVCBHM_Pos (21UL) /* DOVCBHM (Bit 21) */ -#define LINK_REG_DPUSR0R_DOVCBHM_Msk (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_DOVCAHM_Pos (20UL) /* DOVCAHM (Bit 20) */ -#define LINK_REG_DPUSR0R_DOVCAHM_Msk (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */ -/* DPUSR1R */ -#define LINK_REG_DPUSR1R_DVBSTSH_Pos (23UL) /* DVBSTSH (Bit 23) */ -#define LINK_REG_DPUSR1R_DVBSTSH_Msk (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_DOVCBH_Pos (21UL) /* DOVCBH (Bit 21) */ -#define LINK_REG_DPUSR1R_DOVCBH_Msk (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_DOVCAH_Pos (20UL) /* DOVCAH (Bit 20) */ -#define LINK_REG_DPUSR1R_DOVCAH_Msk (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_DVBSTSHE_Pos (7UL) /* DVBSTSHE (Bit 7) */ -#define LINK_REG_DPUSR1R_DVBSTSHE_Msk (0x80UL) /* DVBSTSHE (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_DOVCBHE_Pos (5UL) /* DOVCBHE (Bit 5) */ -#define LINK_REG_DPUSR1R_DOVCBHE_Msk (0x20UL) /* DOVCBHE (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_DOVCAHE_Pos (4UL) /* DOVCAHE (Bit 4) */ -#define LINK_REG_DPUSR1R_DOVCAHE_Msk (0x10UL) /* DOVCAHE (Bitfield-Mask: 0x01) */ -/* DPUSR2R */ -#define LINK_REG_DPUSR2R_DMINTE_Pos (9UL) /* DMINTE (Bit 9) */ -#define LINK_REG_DPUSR2R_DMINTE_Msk (0x200UL) /* DMINTE (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR2R_DPINTE_Pos (8UL) /* DPINTE (Bit 8) */ -#define LINK_REG_DPUSR2R_DPINTE_Msk (0x100UL) /* DPINTE (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR2R_DMVAL_Pos (5UL) /* DMVAL (Bit 5) */ -#define LINK_REG_DPUSR2R_DMVAL_Msk (0x20UL) /* DMVAL (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR2R_DPVAL_Pos (4UL) /* DPVAL (Bit 4) */ -#define LINK_REG_DPUSR2R_DPVAL_Msk (0x10UL) /* DPVAL (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR2R_DMINT_Pos (1UL) /* DMINT (Bit 1) */ -#define LINK_REG_DPUSR2R_DMINT_Msk (0x2UL) /* DMINT (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR2R_DPINT_Pos (0UL) /* DPINT (Bit 0) */ -#define LINK_REG_DPUSR2R_DPINT_Msk (0x1UL) /* DPINT (Bitfield-Mask: 0x01) */ -/* DPUSRCR */ -#define LINK_REG_DPUSRCR_FIXPHYPD_Pos (1UL) /* FIXPHYPD (Bit 1) */ -#define LINK_REG_DPUSRCR_FIXPHYPD_Msk (0x2UL) /* FIXPHYPD (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSRCR_FIXPHY_Pos (0UL) /* FIXPHY (Bit 0) */ -#define LINK_REG_DPUSRCR_FIXPHY_Msk (0x1UL) /* FIXPHY (Bitfield-Mask: 0x01) */ -/* DPUSR0R_FS */ -#define LINK_REG_DPUSR0R_FS_DVBSTS0_Pos (23UL) /* DVBSTS0 (Bit 23) */ -#define LINK_REG_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_DOVCB0_Pos (21UL) /* DOVCB0 (Bit 21) */ -#define LINK_REG_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_DOVCA0_Pos (20UL) /* DOVCA0 (Bit 20) */ -#define LINK_REG_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_DM0_Pos (17UL) /* DM0 (Bit 17) */ -#define LINK_REG_DPUSR0R_FS_DM0_Msk (0x20000UL) /* DM0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_DP0_Pos (16UL) /* DP0 (Bit 16) */ -#define LINK_REG_DPUSR0R_FS_DP0_Msk (0x10000UL) /* DP0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_FIXPHY0_Pos (4UL) /* FIXPHY0 (Bit 4) */ -#define LINK_REG_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /* FIXPHY0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_DRPD0_Pos (3UL) /* DRPD0 (Bit 3) */ -#define LINK_REG_DPUSR0R_FS_DRPD0_Msk (0x8UL) /* DRPD0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_RPUE0_Pos (1UL) /* RPUE0 (Bit 1) */ -#define LINK_REG_DPUSR0R_FS_RPUE0_Msk (0x2UL) /* RPUE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_SRPC0_Pos (0UL) /* SRPC0 (Bit 0) */ -#define LINK_REG_DPUSR0R_FS_SRPC0_Msk (0x1UL) /* SRPC0 (Bitfield-Mask: 0x01) */ -/* DPUSR1R_FS */ -#define LINK_REG_DPUSR1R_FS_DVBINT0_Pos (23UL) /* DVBINT0 (Bit 23) */ -#define LINK_REG_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /* DOVRCRB0 (Bit 21) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /* DOVRCRA0 (Bit 20) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DMINT0_Pos (17UL) /* DMINT0 (Bit 17) */ -#define LINK_REG_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /* DMINT0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DPINT0_Pos (16UL) /* DPINT0 (Bit 16) */ -#define LINK_REG_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /* DPINT0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DVBSE0_Pos (7UL) /* DVBSE0 (Bit 7) */ -#define LINK_REG_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /* DVBSE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /* DOVRCRBE0 (Bit 5) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /* DOVRCRBE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /* DOVRCRAE0 (Bit 4) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /* DOVRCRAE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DMINTE0_Pos (1UL) /* DMINTE0 (Bit 1) */ -#define LINK_REG_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /* DMINTE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DPINTE0_Pos (0UL) /* DPINTE0 (Bit 0) */ -#define LINK_REG_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /* DPINTE0 (Bitfield-Mask: 0x01) */ +// PIPE_TR +// E +#define LINK_REG_PIPE_TR_E_TRENB_Pos (9UL) /* TRENB (Bit 9) */ +#define LINK_REG_PIPE_TR_E_TRENB_Msk (0x200UL) /* TRENB (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_TR_E_TRCLR_Pos (8UL) /* TRCLR (Bit 8) */ +#define LINK_REG_PIPE_TR_E_TRCLR_Msk (0x100UL) /* TRCLR (Bitfield-Mask: 0x01) */ + +// N +#define LINK_REG_PIPE_TR_N_TRNCNT_Pos (0UL) /* TRNCNT (Bit 0) */ +#define LINK_REG_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /* TRNCNT (Bitfield-Mask: 0xffff) */ + +// LINK_REG + +// SYSCFG +#define LINK_REG_SYSCFG_SCKE_Pos (10UL) /* SCKE (Bit 10) */ +#define LINK_REG_SYSCFG_SCKE_Msk (0x400UL) /* SCKE (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_CNEN_Pos (8UL) /* CNEN (Bit 8) */ +#define LINK_REG_SYSCFG_CNEN_Msk (0x100UL) /* CNEN (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_DCFM_Pos (6UL) /* DCFM (Bit 6) */ +#define LINK_REG_SYSCFG_DCFM_Msk (0x40UL) /* DCFM (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_DRPD_Pos (5UL) /* DRPD (Bit 5) */ +#define LINK_REG_SYSCFG_DRPD_Msk (0x20UL) /* DRPD (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_DPRPU_Pos (4UL) /* DPRPU (Bit 4) */ +#define LINK_REG_SYSCFG_DPRPU_Msk (0x10UL) /* DPRPU (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_DMRPU_Pos (3UL) /* DMRPU (Bit 3) */ +#define LINK_REG_SYSCFG_DMRPU_Msk (0x8UL) /* DMRPU (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_USBE_Pos (0UL) /* USBE (Bit 0) */ +#define LINK_REG_SYSCFG_USBE_Msk (0x1UL) /* USBE (Bitfield-Mask: 0x01) */ + +// BUSWAIT +#define LINK_REG_BUSWAIT_BWAIT_Pos (0UL) /* BWAIT (Bit 0) */ +#define LINK_REG_BUSWAIT_BWAIT_Msk (0xfUL) /* BWAIT (Bitfield-Mask: 0x0f) */ + +// SYSSTS0 +#define LINK_REG_SYSSTS0_OVCMON_Pos (14UL) /* OVCMON (Bit 14) */ +#define LINK_REG_SYSSTS0_OVCMON_Msk (0xc000UL) /* OVCMON (Bitfield-Mask: 0x03) */ +#define LINK_REG_SYSSTS0_HTACT_Pos (6UL) /* HTACT (Bit 6) */ +#define LINK_REG_SYSSTS0_HTACT_Msk (0x40UL) /* HTACT (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSSTS0_SOFEA_Pos (5UL) /* SOFEA (Bit 5) */ +#define LINK_REG_SYSSTS0_SOFEA_Msk (0x20UL) /* SOFEA (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSSTS0_IDMON_Pos (2UL) /* IDMON (Bit 2) */ +#define LINK_REG_SYSSTS0_IDMON_Msk (0x4UL) /* IDMON (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSSTS0_LNST_Pos (0UL) /* LNST (Bit 0) */ +#define LINK_REG_SYSSTS0_LNST_Msk (0x3UL) /* LNST (Bitfield-Mask: 0x03) */ + +// PLLSTA +#define LINK_REG_PLLSTA_PLLLOCK_Pos (0UL) /* PLLLOCK (Bit 0) */ +#define LINK_REG_PLLSTA_PLLLOCK_Msk (0x1UL) /* PLLLOCK (Bitfield-Mask: 0x01) */ + +// DVSTCTR0 +#define LINK_REG_DVSTCTR0_HNPBTOA_Pos (11UL) /* HNPBTOA (Bit 11) */ +#define LINK_REG_DVSTCTR0_HNPBTOA_Msk (0x800UL) /* HNPBTOA (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_EXICEN_Pos (10UL) /* EXICEN (Bit 10) */ +#define LINK_REG_DVSTCTR0_EXICEN_Msk (0x400UL) /* EXICEN (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_VBUSEN_Pos (9UL) /* VBUSEN (Bit 9) */ +#define LINK_REG_DVSTCTR0_VBUSEN_Msk (0x200UL) /* VBUSEN (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_WKUP_Pos (8UL) /* WKUP (Bit 8) */ +#define LINK_REG_DVSTCTR0_WKUP_Msk (0x100UL) /* WKUP (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_RWUPE_Pos (7UL) /* RWUPE (Bit 7) */ +#define LINK_REG_DVSTCTR0_RWUPE_Msk (0x80UL) /* RWUPE (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_USBRST_Pos (6UL) /* USBRST (Bit 6) */ +#define LINK_REG_DVSTCTR0_USBRST_Msk (0x40UL) /* USBRST (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_RESUME_Pos (5UL) /* RESUME (Bit 5) */ +#define LINK_REG_DVSTCTR0_RESUME_Msk (0x20UL) /* RESUME (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_UACT_Pos (4UL) /* UACT (Bit 4) */ +#define LINK_REG_DVSTCTR0_UACT_Msk (0x10UL) /* UACT (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_RHST_Pos (0UL) /* RHST (Bit 0) */ +#define LINK_REG_DVSTCTR0_RHST_Msk (0x7UL) /* RHST (Bitfield-Mask: 0x07) */ + +// TESTMODE +#define LINK_REG_TESTMODE_UTST_Pos (0UL) /* UTST (Bit 0) */ +#define LINK_REG_TESTMODE_UTST_Msk (0xfUL) /* UTST (Bitfield-Mask: 0x0f) */ + +// CFIFOSEL +#define LINK_REG_CFIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ +#define LINK_REG_CFIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ +#define LINK_REG_CFIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ +#define LINK_REG_CFIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ +#define LINK_REG_CFIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ +#define LINK_REG_CFIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOSEL_ISEL_Pos (5UL) /* ISEL (Bit 5) */ +#define LINK_REG_CFIFOSEL_ISEL_Msk (0x20UL) /* ISEL (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ +#define LINK_REG_CFIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ + +// CFIFOCTR +#define LINK_REG_CFIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ +#define LINK_REG_CFIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ +#define LINK_REG_CFIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ +#define LINK_REG_CFIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ +#define LINK_REG_CFIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ + +// D0FIFOSEL +#define LINK_REG_D0FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ +#define LINK_REG_D0FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ +#define LINK_REG_D0FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ +#define LINK_REG_D0FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ +#define LINK_REG_D0FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ +#define LINK_REG_D0FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ +#define LINK_REG_D0FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ +#define LINK_REG_D0FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ +#define LINK_REG_D0FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ + +// D0FIFOCTR +#define LINK_REG_D0FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ +#define LINK_REG_D0FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ +#define LINK_REG_D0FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ +#define LINK_REG_D0FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ +#define LINK_REG_D0FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ + +// D1FIFOSEL +#define LINK_REG_D1FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ +#define LINK_REG_D1FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ +#define LINK_REG_D1FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ +#define LINK_REG_D1FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ +#define LINK_REG_D1FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ +#define LINK_REG_D1FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ +#define LINK_REG_D1FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ +#define LINK_REG_D1FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ +#define LINK_REG_D1FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ + +// D1FIFOCTR +#define LINK_REG_D1FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ +#define LINK_REG_D1FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ +#define LINK_REG_D1FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ +#define LINK_REG_D1FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ +#define LINK_REG_D1FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ + +// INTENB0 +#define LINK_REG_INTENB0_VBSE_Pos (15UL) /* VBSE (Bit 15) */ +#define LINK_REG_INTENB0_VBSE_Msk (0x8000UL) /* VBSE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_RSME_Pos (14UL) /* RSME (Bit 14) */ +#define LINK_REG_INTENB0_RSME_Msk (0x4000UL) /* RSME (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_SOFE_Pos (13UL) /* SOFE (Bit 13) */ +#define LINK_REG_INTENB0_SOFE_Msk (0x2000UL) /* SOFE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_DVSE_Pos (12UL) /* DVSE (Bit 12) */ +#define LINK_REG_INTENB0_DVSE_Msk (0x1000UL) /* DVSE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_CTRE_Pos (11UL) /* CTRE (Bit 11) */ +#define LINK_REG_INTENB0_CTRE_Msk (0x800UL) /* CTRE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_BEMPE_Pos (10UL) /* BEMPE (Bit 10) */ +#define LINK_REG_INTENB0_BEMPE_Msk (0x400UL) /* BEMPE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_NRDYE_Pos (9UL) /* NRDYE (Bit 9) */ +#define LINK_REG_INTENB0_NRDYE_Msk (0x200UL) /* NRDYE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_BRDYE_Pos (8UL) /* BRDYE (Bit 8) */ +#define LINK_REG_INTENB0_BRDYE_Msk (0x100UL) /* BRDYE (Bitfield-Mask: 0x01) */ + +// INTENB1 +#define LINK_REG_INTENB1_OVRCRE_Pos (15UL) /* OVRCRE (Bit 15) */ +#define LINK_REG_INTENB1_OVRCRE_Msk (0x8000UL) /* OVRCRE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_BCHGE_Pos (14UL) /* BCHGE (Bit 14) */ +#define LINK_REG_INTENB1_BCHGE_Msk (0x4000UL) /* BCHGE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_DTCHE_Pos (12UL) /* DTCHE (Bit 12) */ +#define LINK_REG_INTENB1_DTCHE_Msk (0x1000UL) /* DTCHE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_ATTCHE_Pos (11UL) /* ATTCHE (Bit 11) */ +#define LINK_REG_INTENB1_ATTCHE_Msk (0x800UL) /* ATTCHE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_EOFERRE_Pos (6UL) /* EOFERRE (Bit 6) */ +#define LINK_REG_INTENB1_EOFERRE_Msk (0x40UL) /* EOFERRE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_SIGNE_Pos (5UL) /* SIGNE (Bit 5) */ +#define LINK_REG_INTENB1_SIGNE_Msk (0x20UL) /* SIGNE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_SACKE_Pos (4UL) /* SACKE (Bit 4) */ +#define LINK_REG_INTENB1_SACKE_Msk (0x10UL) /* SACKE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_PDDETINTE0_Pos (0UL) /* PDDETINTE0 (Bit 0) */ +#define LINK_REG_INTENB1_PDDETINTE0_Msk (0x1UL) /* PDDETINTE0 (Bitfield-Mask: 0x01) */ + +// BRDYENB +#define LINK_REG_BRDYENB_PIPEBRDYE_Pos (0UL) /* PIPEBRDYE (Bit 0) */ +#define LINK_REG_BRDYENB_PIPEBRDYE_Msk (0x1UL) /* PIPEBRDYE (Bitfield-Mask: 0x01) */ + +// NRDYENB +#define LINK_REG_NRDYENB_PIPENRDYE_Pos (0UL) /* PIPENRDYE (Bit 0) */ +#define LINK_REG_NRDYENB_PIPENRDYE_Msk (0x1UL) /* PIPENRDYE (Bitfield-Mask: 0x01) */ + +// BEMPENB +#define LINK_REG_BEMPENB_PIPEBEMPE_Pos (0UL) /* PIPEBEMPE (Bit 0) */ +#define LINK_REG_BEMPENB_PIPEBEMPE_Msk (0x1UL) /* PIPEBEMPE (Bitfield-Mask: 0x01) */ + +// SOFCFG +#define LINK_REG_SOFCFG_TRNENSEL_Pos (8UL) /* TRNENSEL (Bit 8) */ +#define LINK_REG_SOFCFG_TRNENSEL_Msk (0x100UL) /* TRNENSEL (Bitfield-Mask: 0x01) */ +#define LINK_REG_SOFCFG_BRDYM_Pos (6UL) /* BRDYM (Bit 6) */ +#define LINK_REG_SOFCFG_BRDYM_Msk (0x40UL) /* BRDYM (Bitfield-Mask: 0x01) */ +#define LINK_REG_SOFCFG_INTL_Pos (5UL) /* INTL (Bit 5) */ +#define LINK_REG_SOFCFG_INTL_Msk (0x20UL) /* INTL (Bitfield-Mask: 0x01) */ +#define LINK_REG_SOFCFG_EDGESTS_Pos (4UL) /* EDGESTS (Bit 4) */ +#define LINK_REG_SOFCFG_EDGESTS_Msk (0x10UL) /* EDGESTS (Bitfield-Mask: 0x01) */ + +// PHYSET +#define LINK_REG_PHYSET_HSEB_Pos (15UL) /* HSEB (Bit 15) */ +#define LINK_REG_PHYSET_HSEB_Msk (0x8000UL) /* HSEB (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSET_REPSTART_Pos (11UL) /* REPSTART (Bit 11) */ +#define LINK_REG_PHYSET_REPSTART_Msk (0x800UL) /* REPSTART (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSET_REPSEL_Pos (8UL) /* REPSEL (Bit 8) */ +#define LINK_REG_PHYSET_REPSEL_Msk (0x300UL) /* REPSEL (Bitfield-Mask: 0x03) */ +#define LINK_REG_PHYSET_CLKSEL_Pos (4UL) /* CLKSEL (Bit 4) */ +#define LINK_REG_PHYSET_CLKSEL_Msk (0x30UL) /* CLKSEL (Bitfield-Mask: 0x03) */ +#define LINK_REG_PHYSET_CDPEN_Pos (3UL) /* CDPEN (Bit 3) */ +#define LINK_REG_PHYSET_CDPEN_Msk (0x8UL) /* CDPEN (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSET_PLLRESET_Pos (1UL) /* PLLRESET (Bit 1) */ +#define LINK_REG_PHYSET_PLLRESET_Msk (0x2UL) /* PLLRESET (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSET_DIRPD_Pos (0UL) /* DIRPD (Bit 0) */ +#define LINK_REG_PHYSET_DIRPD_Msk (0x1UL) /* DIRPD (Bitfield-Mask: 0x01) */ + +// INTSTS0 +#define LINK_REG_INTSTS0_VBINT_Pos (15UL) /* VBINT (Bit 15) */ +#define LINK_REG_INTSTS0_VBINT_Msk (0x8000UL) /* VBINT (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_RESM_Pos (14UL) /* RESM (Bit 14) */ +#define LINK_REG_INTSTS0_RESM_Msk (0x4000UL) /* RESM (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_SOFR_Pos (13UL) /* SOFR (Bit 13) */ +#define LINK_REG_INTSTS0_SOFR_Msk (0x2000UL) /* SOFR (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_DVST_Pos (12UL) /* DVST (Bit 12) */ +#define LINK_REG_INTSTS0_DVST_Msk (0x1000UL) /* DVST (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_CTRT_Pos (11UL) /* CTRT (Bit 11) */ +#define LINK_REG_INTSTS0_CTRT_Msk (0x800UL) /* CTRT (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_BEMP_Pos (10UL) /* BEMP (Bit 10) */ +#define LINK_REG_INTSTS0_BEMP_Msk (0x400UL) /* BEMP (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_NRDY_Pos (9UL) /* NRDY (Bit 9) */ +#define LINK_REG_INTSTS0_NRDY_Msk (0x200UL) /* NRDY (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_BRDY_Pos (8UL) /* BRDY (Bit 8) */ +#define LINK_REG_INTSTS0_BRDY_Msk (0x100UL) /* BRDY (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_VBSTS_Pos (7UL) /* VBSTS (Bit 7) */ +#define LINK_REG_INTSTS0_VBSTS_Msk (0x80UL) /* VBSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ +#define LINK_REG_INTSTS0_DVSQ_Msk (0x70UL) /* DVSQ (Bitfield-Mask: 0x07) */ +#define LINK_REG_INTSTS0_VALID_Pos (3UL) /* VALID (Bit 3) */ +#define LINK_REG_INTSTS0_VALID_Msk (0x8UL) /* VALID (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_CTSQ_Pos (0UL) /* CTSQ (Bit 0) */ +#define LINK_REG_INTSTS0_CTSQ_Msk (0x7UL) /* CTSQ (Bitfield-Mask: 0x07) */ + +// INTSTS1 +#define LINK_REG_INTSTS1_OVRCR_Pos (15UL) /* OVRCR (Bit 15) */ +#define LINK_REG_INTSTS1_OVRCR_Msk (0x8000UL) /* OVRCR (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_BCHG_Pos (14UL) /* BCHG (Bit 14) */ +#define LINK_REG_INTSTS1_BCHG_Msk (0x4000UL) /* BCHG (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_DTCH_Pos (12UL) /* DTCH (Bit 12) */ +#define LINK_REG_INTSTS1_DTCH_Msk (0x1000UL) /* DTCH (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_ATTCH_Pos (11UL) /* ATTCH (Bit 11) */ +#define LINK_REG_INTSTS1_ATTCH_Msk (0x800UL) /* ATTCH (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_L1RSMEND_Pos (9UL) /* L1RSMEND (Bit 9) */ +#define LINK_REG_INTSTS1_L1RSMEND_Msk (0x200UL) /* L1RSMEND (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_LPMEND_Pos (8UL) /* LPMEND (Bit 8) */ +#define LINK_REG_INTSTS1_LPMEND_Msk (0x100UL) /* LPMEND (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_EOFERR_Pos (6UL) /* EOFERR (Bit 6) */ +#define LINK_REG_INTSTS1_EOFERR_Msk (0x40UL) /* EOFERR (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_SIGN_Pos (5UL) /* SIGN (Bit 5) */ +#define LINK_REG_INTSTS1_SIGN_Msk (0x20UL) /* SIGN (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_SACK_Pos (4UL) /* SACK (Bit 4) */ +#define LINK_REG_INTSTS1_SACK_Msk (0x10UL) /* SACK (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_PDDETINT0_Pos (0UL) /* PDDETINT0 (Bit 0) */ +#define LINK_REG_INTSTS1_PDDETINT0_Msk (0x1UL) /* PDDETINT0 (Bitfield-Mask: 0x01) */ + +// BRDYSTS +#define LINK_REG_BRDYSTS_PIPEBRDY_Pos (0UL) /* PIPEBRDY (Bit 0) */ +#define LINK_REG_BRDYSTS_PIPEBRDY_Msk (0x1UL) /* PIPEBRDY (Bitfield-Mask: 0x01) */ + +// NRDYSTS +#define LINK_REG_NRDYSTS_PIPENRDY_Pos (0UL) /* PIPENRDY (Bit 0) */ +#define LINK_REG_NRDYSTS_PIPENRDY_Msk (0x1UL) /* PIPENRDY (Bitfield-Mask: 0x01) */ + +// BEMPSTS +#define LINK_REG_BEMPSTS_PIPEBEMP_Pos (0UL) /* PIPEBEMP (Bit 0) */ +#define LINK_REG_BEMPSTS_PIPEBEMP_Msk (0x1UL) /* PIPEBEMP (Bitfield-Mask: 0x01) */ + +// FRMNUM +#define LINK_REG_FRMNUM_OVRN_Pos (15UL) /* OVRN (Bit 15) */ +#define LINK_REG_FRMNUM_OVRN_Msk (0x8000UL) /* OVRN (Bitfield-Mask: 0x01) */ +#define LINK_REG_FRMNUM_CRCE_Pos (14UL) /* CRCE (Bit 14) */ +#define LINK_REG_FRMNUM_CRCE_Msk (0x4000UL) /* CRCE (Bitfield-Mask: 0x01) */ +#define LINK_REG_FRMNUM_FRNM_Pos (0UL) /* FRNM (Bit 0) */ +#define LINK_REG_FRMNUM_FRNM_Msk (0x7ffUL) /* FRNM (Bitfield-Mask: 0x7ff) */ + +// UFRMNUM +#define LINK_REG_UFRMNUM_DVCHG_Pos (15UL) /* DVCHG (Bit 15) */ +#define LINK_REG_UFRMNUM_DVCHG_Msk (0x8000UL) /* DVCHG (Bitfield-Mask: 0x01) */ +#define LINK_REG_UFRMNUM_UFRNM_Pos (0UL) /* UFRNM (Bit 0) */ +#define LINK_REG_UFRMNUM_UFRNM_Msk (0x7UL) /* UFRNM (Bitfield-Mask: 0x07) */ + +// USBADDR +#define LINK_REG_USBADDR_STSRECOV0_Pos (8UL) /* STSRECOV0 (Bit 8) */ +#define LINK_REG_USBADDR_STSRECOV0_Msk (0x700UL) /* STSRECOV0 (Bitfield-Mask: 0x07) */ +#define LINK_REG_USBADDR_USBADDR_Pos (0UL) /* USBADDR (Bit 0) */ +#define LINK_REG_USBADDR_USBADDR_Msk (0x7fUL) /* USBADDR (Bitfield-Mask: 0x7f) */ + +// USBREQ +#define LINK_REG_USBREQ_BREQUEST_Pos (8UL) /* BREQUEST (Bit 8) */ +#define LINK_REG_USBREQ_BREQUEST_Msk (0xff00UL) /* BREQUEST (Bitfield-Mask: 0xff) */ +#define LINK_REG_USBREQ_BMREQUESTTYPE_Pos (0UL) /* BMREQUESTTYPE (Bit 0) */ +#define LINK_REG_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */ + +// USBVAL +#define LINK_REG_USBVAL_WVALUE_Pos (0UL) /* WVALUE (Bit 0) */ +#define LINK_REG_USBVAL_WVALUE_Msk (0xffffUL) /* WVALUE (Bitfield-Mask: 0xffff) */ + +// USBINDX +#define LINK_REG_USBINDX_WINDEX_Pos (0UL) /* WINDEX (Bit 0) */ +#define LINK_REG_USBINDX_WINDEX_Msk (0xffffUL) /* WINDEX (Bitfield-Mask: 0xffff) */ + +// USBLENG +#define LINK_REG_USBLENG_WLENGTH_Pos (0UL) /* WLENGTH (Bit 0) */ +#define LINK_REG_USBLENG_WLENGTH_Msk (0xffffUL) /* WLENGTH (Bitfield-Mask: 0xffff) */ + +// DCPCFG +#define LINK_REG_DCPCFG_CNTMD_Pos (8UL) /* CNTMD (Bit 8) */ +#define LINK_REG_DCPCFG_CNTMD_Msk (0x100UL) /* CNTMD (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ +#define LINK_REG_DCPCFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCFG_DIR_Pos (4UL) /* DIR (Bit 4) */ +#define LINK_REG_DCPCFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ + +// DCPMAXP +#define LINK_REG_DCPMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ +#define LINK_REG_DCPMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ +#define LINK_REG_DCPMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ +#define LINK_REG_DCPMAXP_MXPS_Msk (0x7fUL) /* MXPS (Bitfield-Mask: 0x7f) */ + +// DCPCTR +#define LINK_REG_DCPCTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ +#define LINK_REG_DCPCTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_SUREQ_Pos (14UL) /* SUREQ (Bit 14) */ +#define LINK_REG_DCPCTR_SUREQ_Msk (0x4000UL) /* SUREQ (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_SUREQCLR_Pos (11UL) /* SUREQCLR (Bit 11) */ +#define LINK_REG_DCPCTR_SUREQCLR_Msk (0x800UL) /* SUREQCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ +#define LINK_REG_DCPCTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ +#define LINK_REG_DCPCTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ +#define LINK_REG_DCPCTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ +#define LINK_REG_DCPCTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_CCPL_Pos (2UL) /* CCPL (Bit 2) */ +#define LINK_REG_DCPCTR_CCPL_Msk (0x4UL) /* CCPL (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_PID_Pos (0UL) /* PID (Bit 0) */ +#define LINK_REG_DCPCTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ + +// PIPESEL +#define LINK_REG_PIPESEL_PIPESEL_Pos (0UL) /* PIPESEL (Bit 0) */ +#define LINK_REG_PIPESEL_PIPESEL_Msk (0xfUL) /* PIPESEL (Bitfield-Mask: 0x0f) */ + +// PIPECFG +#define LINK_REG_PIPECFG_TYPE_Pos (14UL) /* TYPE (Bit 14) */ +#define LINK_REG_PIPECFG_TYPE_Msk (0xc000UL) /* TYPE (Bitfield-Mask: 0x03) */ +#define LINK_REG_PIPECFG_BFRE_Pos (10UL) /* BFRE (Bit 10) */ +#define LINK_REG_PIPECFG_BFRE_Msk (0x400UL) /* BFRE (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPECFG_DBLB_Pos (9UL) /* DBLB (Bit 9) */ +#define LINK_REG_PIPECFG_DBLB_Msk (0x200UL) /* DBLB (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPECFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ +#define LINK_REG_PIPECFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPECFG_DIR_Pos (4UL) /* DIR (Bit 4) */ +#define LINK_REG_PIPECFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPECFG_EPNUM_Pos (0UL) /* EPNUM (Bit 0) */ +#define LINK_REG_PIPECFG_EPNUM_Msk (0xfUL) /* EPNUM (Bitfield-Mask: 0x0f) */ + +// PIPEMAXP +#define LINK_REG_PIPEMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ +#define LINK_REG_PIPEMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ +#define LINK_REG_PIPEMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ +#define LINK_REG_PIPEMAXP_MXPS_Msk (0x1ffUL) /* MXPS (Bitfield-Mask: 0x1ff) */ + +// PIPEPERI +#define LINK_REG_PIPEPERI_IFIS_Pos (12UL) /* IFIS (Bit 12) */ +#define LINK_REG_PIPEPERI_IFIS_Msk (0x1000UL) /* IFIS (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPEPERI_IITV_Pos (0UL) /* IITV (Bit 0) */ +#define LINK_REG_PIPEPERI_IITV_Msk (0x7UL) /* IITV (Bitfield-Mask: 0x07) */ + +// PIPE_CTR +#define LINK_REG_PIPE_CTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ +#define LINK_REG_PIPE_CTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_INBUFM_Pos (14UL) /* INBUFM (Bit 14) */ +#define LINK_REG_PIPE_CTR_INBUFM_Msk (0x4000UL) /* INBUFM (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_CSCLR_Pos (13UL) /* CSCLR (Bit 13) */ +#define LINK_REG_PIPE_CTR_CSCLR_Msk (0x2000UL) /* CSCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_CSSTS_Pos (12UL) /* CSSTS (Bit 12) */ +#define LINK_REG_PIPE_CTR_CSSTS_Msk (0x1000UL) /* CSSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_ATREPM_Pos (10UL) /* ATREPM (Bit 10) */ +#define LINK_REG_PIPE_CTR_ATREPM_Msk (0x400UL) /* ATREPM (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_ACLRM_Pos (9UL) /* ACLRM (Bit 9) */ +#define LINK_REG_PIPE_CTR_ACLRM_Msk (0x200UL) /* ACLRM (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ +#define LINK_REG_PIPE_CTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ +#define LINK_REG_PIPE_CTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ +#define LINK_REG_PIPE_CTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ +#define LINK_REG_PIPE_CTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_PID_Pos (0UL) /* PID (Bit 0) */ +#define LINK_REG_PIPE_CTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ + +// DEVADD +#define LINK_REG_DEVADD_UPPHUB_Pos (11UL) /* UPPHUB (Bit 11) */ +#define LINK_REG_DEVADD_UPPHUB_Msk (0x7800UL) /* UPPHUB (Bitfield-Mask: 0x0f) */ +#define LINK_REG_DEVADD_HUBPORT_Pos (8UL) /* HUBPORT (Bit 8) */ +#define LINK_REG_DEVADD_HUBPORT_Msk (0x700UL) /* HUBPORT (Bitfield-Mask: 0x07) */ +#define LINK_REG_DEVADD_USBSPD_Pos (6UL) /* USBSPD (Bit 6) */ +#define LINK_REG_DEVADD_USBSPD_Msk (0xc0UL) /* USBSPD (Bitfield-Mask: 0x03) */ + +// USBBCCTRL0 +#define LINK_REG_USBBCCTRL0_PDDETSTS0_Pos (9UL) /* PDDETSTS0 (Bit 9) */ +#define LINK_REG_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /* PDDETSTS0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /* CHGDETSTS0 (Bit 8) */ +#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /* CHGDETSTS0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_BATCHGE0_Pos (7UL) /* BATCHGE0 (Bit 7) */ +#define LINK_REG_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /* BATCHGE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_VDMSRCE0_Pos (5UL) /* VDMSRCE0 (Bit 5) */ +#define LINK_REG_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /* VDMSRCE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_IDPSINKE0_Pos (4UL) /* IDPSINKE0 (Bit 4) */ +#define LINK_REG_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /* IDPSINKE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_VDPSRCE0_Pos (3UL) /* VDPSRCE0 (Bit 3) */ +#define LINK_REG_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /* VDPSRCE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_IDMSINKE0_Pos (2UL) /* IDMSINKE0 (Bit 2) */ +#define LINK_REG_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /* IDMSINKE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_IDPSRCE0_Pos (1UL) /* IDPSRCE0 (Bit 1) */ +#define LINK_REG_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /* IDPSRCE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_RPDME0_Pos (0UL) /* RPDME0 (Bit 0) */ +#define LINK_REG_USBBCCTRL0_RPDME0_Msk (0x1UL) /* RPDME0 (Bitfield-Mask: 0x01) */ + +// UCKSEL +#define LINK_REG_UCKSEL_UCKSELC_Pos (0UL) /* UCKSELC (Bit 0) */ +#define LINK_REG_UCKSEL_UCKSELC_Msk (0x1UL) /* UCKSELC (Bitfield-Mask: 0x01) */ + +// USBMC +#define LINK_REG_USBMC_VDCEN_Pos (7UL) /* VDCEN (Bit 7) */ +#define LINK_REG_USBMC_VDCEN_Msk (0x80UL) /* VDCEN (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBMC_VDDUSBE_Pos (0UL) /* VDDUSBE (Bit 0) */ +#define LINK_REG_USBMC_VDDUSBE_Msk (0x1UL) /* VDDUSBE (Bitfield-Mask: 0x01) */ + +// PHYSLEW +#define LINK_REG_PHYSLEW_SLEWF01_Pos (3UL) /* SLEWF01 (Bit 3) */ +#define LINK_REG_PHYSLEW_SLEWF01_Msk (0x8UL) /* SLEWF01 (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSLEW_SLEWF00_Pos (2UL) /* SLEWF00 (Bit 2) */ +#define LINK_REG_PHYSLEW_SLEWF00_Msk (0x4UL) /* SLEWF00 (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSLEW_SLEWR01_Pos (1UL) /* SLEWR01 (Bit 1) */ +#define LINK_REG_PHYSLEW_SLEWR01_Msk (0x2UL) /* SLEWR01 (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSLEW_SLEWR00_Pos (0UL) /* SLEWR00 (Bit 0) */ +#define LINK_REG_PHYSLEW_SLEWR00_Msk (0x1UL) /* SLEWR00 (Bitfield-Mask: 0x01) */ + +// LPCTRL +#define LINK_REG_LPCTRL_HWUPM_Pos (7UL) /* HWUPM (Bit 7) */ +#define LINK_REG_LPCTRL_HWUPM_Msk (0x80UL) /* HWUPM (Bitfield-Mask: 0x01) */ + +// LPSTS +#define LINK_REG_LPSTS_SUSPENDM_Pos (14UL) /* SUSPENDM (Bit 14) */ +#define LINK_REG_LPSTS_SUSPENDM_Msk (0x4000UL) /* SUSPENDM (Bitfield-Mask: 0x01) */ + +// BCCTRL +#define LINK_REG_BCCTRL_PDDETSTS_Pos (9UL) /* PDDETSTS (Bit 9) */ +#define LINK_REG_BCCTRL_PDDETSTS_Msk (0x200UL) /* PDDETSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_CHGDETSTS_Pos (8UL) /* CHGDETSTS (Bit 8) */ +#define LINK_REG_BCCTRL_CHGDETSTS_Msk (0x100UL) /* CHGDETSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_DCPMODE_Pos (5UL) /* DCPMODE (Bit 5) */ +#define LINK_REG_BCCTRL_DCPMODE_Msk (0x20UL) /* DCPMODE (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_VDMSRCE_Pos (4UL) /* VDMSRCE (Bit 4) */ +#define LINK_REG_BCCTRL_VDMSRCE_Msk (0x10UL) /* VDMSRCE (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_IDPSINKE_Pos (3UL) /* IDPSINKE (Bit 3) */ +#define LINK_REG_BCCTRL_IDPSINKE_Msk (0x8UL) /* IDPSINKE (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_VDPSRCE_Pos (2UL) /* VDPSRCE (Bit 2) */ +#define LINK_REG_BCCTRL_VDPSRCE_Msk (0x4UL) /* VDPSRCE (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_IDMSINKE_Pos (1UL) /* IDMSINKE (Bit 1) */ +#define LINK_REG_BCCTRL_IDMSINKE_Msk (0x2UL) /* IDMSINKE (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_IDPSRCE_Pos (0UL) /* IDPSRCE (Bit 0) */ +#define LINK_REG_BCCTRL_IDPSRCE_Msk (0x1UL) /* IDPSRCE (Bitfield-Mask: 0x01) */ + +// PL1CTRL1 +#define LINK_REG_PL1CTRL1_L1EXTMD_Pos (14UL) /* L1EXTMD (Bit 14) */ +#define LINK_REG_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /* L1EXTMD (Bitfield-Mask: 0x01) */ +#define LINK_REG_PL1CTRL1_HIRDTHR_Pos (8UL) /* HIRDTHR (Bit 8) */ +#define LINK_REG_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /* HIRDTHR (Bitfield-Mask: 0x0f) */ +#define LINK_REG_PL1CTRL1_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ +#define LINK_REG_PL1CTRL1_DVSQ_Msk (0xf0UL) /* DVSQ (Bitfield-Mask: 0x0f) */ +#define LINK_REG_PL1CTRL1_L1NEGOMD_Pos (3UL) /* L1NEGOMD (Bit 3) */ +#define LINK_REG_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /* L1NEGOMD (Bitfield-Mask: 0x01) */ +#define LINK_REG_PL1CTRL1_L1RESPMD_Pos (1UL) /* L1RESPMD (Bit 1) */ +#define LINK_REG_PL1CTRL1_L1RESPMD_Msk (0x6UL) /* L1RESPMD (Bitfield-Mask: 0x03) */ +#define LINK_REG_PL1CTRL1_L1RESPEN_Pos (0UL) /* L1RESPEN (Bit 0) */ +#define LINK_REG_PL1CTRL1_L1RESPEN_Msk (0x1UL) /* L1RESPEN (Bitfield-Mask: 0x01) */ + +// PL1CTRL2 +#define LINK_REG_PL1CTRL2_RWEMON_Pos (12UL) /* RWEMON (Bit 12) */ +#define LINK_REG_PL1CTRL2_RWEMON_Msk (0x1000UL) /* RWEMON (Bitfield-Mask: 0x01) */ +#define LINK_REG_PL1CTRL2_HIRDMON_Pos (8UL) /* HIRDMON (Bit 8) */ +#define LINK_REG_PL1CTRL2_HIRDMON_Msk (0xf00UL) /* HIRDMON (Bitfield-Mask: 0x0f) */ + +// HL1CTRL1 +#define LINK_REG_HL1CTRL1_L1STATUS_Pos (1UL) /* L1STATUS (Bit 1) */ +#define LINK_REG_HL1CTRL1_L1STATUS_Msk (0x6UL) /* L1STATUS (Bitfield-Mask: 0x03) */ +#define LINK_REG_HL1CTRL1_L1REQ_Pos (0UL) /* L1REQ (Bit 0) */ +#define LINK_REG_HL1CTRL1_L1REQ_Msk (0x1UL) /* L1REQ (Bitfield-Mask: 0x01) */ + +// HL1CTRL2 +#define LINK_REG_HL1CTRL2_BESL_Pos (15UL) /* BESL (Bit 15) */ +#define LINK_REG_HL1CTRL2_BESL_Msk (0x8000UL) /* BESL (Bitfield-Mask: 0x01) */ +#define LINK_REG_HL1CTRL2_L1RWE_Pos (12UL) /* L1RWE (Bit 12) */ +#define LINK_REG_HL1CTRL2_L1RWE_Msk (0x1000UL) /* L1RWE (Bitfield-Mask: 0x01) */ +#define LINK_REG_HL1CTRL2_HIRD_Pos (8UL) /* HIRD (Bit 8) */ +#define LINK_REG_HL1CTRL2_HIRD_Msk (0xf00UL) /* HIRD (Bitfield-Mask: 0x0f) */ +#define LINK_REG_HL1CTRL2_L1ADDR_Pos (0UL) /* L1ADDR (Bit 0) */ +#define LINK_REG_HL1CTRL2_L1ADDR_Msk (0xfUL) /* L1ADDR (Bitfield-Mask: 0x0f) */ + +// DPUSR0R +#define LINK_REG_DPUSR0R_DVBSTSHM_Pos (23UL) /* DVBSTSHM (Bit 23) */ +#define LINK_REG_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_DOVCBHM_Pos (21UL) /* DOVCBHM (Bit 21) */ +#define LINK_REG_DPUSR0R_DOVCBHM_Msk (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_DOVCAHM_Pos (20UL) /* DOVCAHM (Bit 20) */ +#define LINK_REG_DPUSR0R_DOVCAHM_Msk (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */ + +// DPUSR1R +#define LINK_REG_DPUSR1R_DVBSTSH_Pos (23UL) /* DVBSTSH (Bit 23) */ +#define LINK_REG_DPUSR1R_DVBSTSH_Msk (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_DOVCBH_Pos (21UL) /* DOVCBH (Bit 21) */ +#define LINK_REG_DPUSR1R_DOVCBH_Msk (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_DOVCAH_Pos (20UL) /* DOVCAH (Bit 20) */ +#define LINK_REG_DPUSR1R_DOVCAH_Msk (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_DVBSTSHE_Pos (7UL) /* DVBSTSHE (Bit 7) */ +#define LINK_REG_DPUSR1R_DVBSTSHE_Msk (0x80UL) /* DVBSTSHE (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_DOVCBHE_Pos (5UL) /* DOVCBHE (Bit 5) */ +#define LINK_REG_DPUSR1R_DOVCBHE_Msk (0x20UL) /* DOVCBHE (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_DOVCAHE_Pos (4UL) /* DOVCAHE (Bit 4) */ +#define LINK_REG_DPUSR1R_DOVCAHE_Msk (0x10UL) /* DOVCAHE (Bitfield-Mask: 0x01) */ + +// DPUSR2R +#define LINK_REG_DPUSR2R_DMINTE_Pos (9UL) /* DMINTE (Bit 9) */ +#define LINK_REG_DPUSR2R_DMINTE_Msk (0x200UL) /* DMINTE (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR2R_DPINTE_Pos (8UL) /* DPINTE (Bit 8) */ +#define LINK_REG_DPUSR2R_DPINTE_Msk (0x100UL) /* DPINTE (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR2R_DMVAL_Pos (5UL) /* DMVAL (Bit 5) */ +#define LINK_REG_DPUSR2R_DMVAL_Msk (0x20UL) /* DMVAL (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR2R_DPVAL_Pos (4UL) /* DPVAL (Bit 4) */ +#define LINK_REG_DPUSR2R_DPVAL_Msk (0x10UL) /* DPVAL (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR2R_DMINT_Pos (1UL) /* DMINT (Bit 1) */ +#define LINK_REG_DPUSR2R_DMINT_Msk (0x2UL) /* DMINT (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR2R_DPINT_Pos (0UL) /* DPINT (Bit 0) */ +#define LINK_REG_DPUSR2R_DPINT_Msk (0x1UL) /* DPINT (Bitfield-Mask: 0x01) */ + +// DPUSRCR +#define LINK_REG_DPUSRCR_FIXPHYPD_Pos (1UL) /* FIXPHYPD (Bit 1) */ +#define LINK_REG_DPUSRCR_FIXPHYPD_Msk (0x2UL) /* FIXPHYPD (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSRCR_FIXPHY_Pos (0UL) /* FIXPHY (Bit 0) */ +#define LINK_REG_DPUSRCR_FIXPHY_Msk (0x1UL) /* FIXPHY (Bitfield-Mask: 0x01) */ + +// DPUSR0R_FS +#define LINK_REG_DPUSR0R_FS_DVBSTS0_Pos (23UL) /* DVBSTS0 (Bit 23) */ +#define LINK_REG_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_DOVCB0_Pos (21UL) /* DOVCB0 (Bit 21) */ +#define LINK_REG_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_DOVCA0_Pos (20UL) /* DOVCA0 (Bit 20) */ +#define LINK_REG_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_DM0_Pos (17UL) /* DM0 (Bit 17) */ +#define LINK_REG_DPUSR0R_FS_DM0_Msk (0x20000UL) /* DM0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_DP0_Pos (16UL) /* DP0 (Bit 16) */ +#define LINK_REG_DPUSR0R_FS_DP0_Msk (0x10000UL) /* DP0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_FIXPHY0_Pos (4UL) /* FIXPHY0 (Bit 4) */ +#define LINK_REG_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /* FIXPHY0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_DRPD0_Pos (3UL) /* DRPD0 (Bit 3) */ +#define LINK_REG_DPUSR0R_FS_DRPD0_Msk (0x8UL) /* DRPD0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_RPUE0_Pos (1UL) /* RPUE0 (Bit 1) */ +#define LINK_REG_DPUSR0R_FS_RPUE0_Msk (0x2UL) /* RPUE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_SRPC0_Pos (0UL) /* SRPC0 (Bit 0) */ +#define LINK_REG_DPUSR0R_FS_SRPC0_Msk (0x1UL) /* SRPC0 (Bitfield-Mask: 0x01) */ + +// DPUSR1R_FS +#define LINK_REG_DPUSR1R_FS_DVBINT0_Pos (23UL) /* DVBINT0 (Bit 23) */ +#define LINK_REG_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /* DOVRCRB0 (Bit 21) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /* DOVRCRA0 (Bit 20) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DMINT0_Pos (17UL) /* DMINT0 (Bit 17) */ +#define LINK_REG_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /* DMINT0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DPINT0_Pos (16UL) /* DPINT0 (Bit 16) */ +#define LINK_REG_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /* DPINT0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DVBSE0_Pos (7UL) /* DVBSE0 (Bit 7) */ +#define LINK_REG_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /* DVBSE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /* DOVRCRBE0 (Bit 5) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /* DOVRCRBE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /* DOVRCRAE0 (Bit 4) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /* DOVRCRAE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DMINTE0_Pos (1UL) /* DMINTE0 (Bit 1) */ +#define LINK_REG_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /* DMINTE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DPINTE0_Pos (0UL) /* DPINTE0 (Bit 0) */ +#define LINK_REG_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /* DPINTE0 (Bitfield-Mask: 0x01) */ /*--------------------------------------------------------------------*/ /* Register Bit Utils */ /*--------------------------------------------------------------------*/ -#define LINK_REG_PIPE_CTR_PID_NAK (0U << LINK_REG_PIPE_CTR_PID_Pos) /* NAK response */ -#define LINK_REG_PIPE_CTR_PID_BUF (1U << LINK_REG_PIPE_CTR_PID_Pos) /* BUF response (depends buffer state) */ -#define LINK_REG_PIPE_CTR_PID_STALL (2U << LINK_REG_PIPE_CTR_PID_Pos) /* STALL response */ +#define LINK_REG_PIPE_CTR_PID_NAK (0U << LINK_REG_PIPE_CTR_PID_Pos) /* NAK response */ +#define LINK_REG_PIPE_CTR_PID_BUF (1U << LINK_REG_PIPE_CTR_PID_Pos) /* BUF response (depends buffer state) */ +#define LINK_REG_PIPE_CTR_PID_STALL (2U << LINK_REG_PIPE_CTR_PID_Pos) /* STALL response */ + +#define LINK_REG_DVSTCTR0_RHST_LS (1U << LINK_REG_DVSTCTR0_RHST_Pos) /* Low-speed connection */ +#define LINK_REG_DVSTCTR0_RHST_FS (2U << LINK_REG_DVSTCTR0_RHST_Pos) /* Full-speed connection */ -#define LINK_REG_DVSTCTR0_RHST_LS (1U << LINK_REG_DVSTCTR0_RHST_Pos) /* Low-speed connection */ -#define LINK_REG_DVSTCTR0_RHST_FS (2U << LINK_REG_DVSTCTR0_RHST_Pos) /* Full-speed connection */ +#define LINK_REG_DEVADD_USBSPD_LS (1U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Low-speed */ +#define LINK_REG_DEVADD_USBSPD_FS (2U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Full-speed */ -#define LINK_REG_DEVADD_USBSPD_LS (1U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Low-speed */ -#define LINK_REG_DEVADD_USBSPD_FS (2U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Full-speed */ +#define LINK_REG_CFIFOSEL_ISEL_WRITE (1U << LINK_REG_CFIFOSEL_ISEL_Pos) /* FIFO write AKA TX*/ -#define LINK_REG_CFIFOSEL_ISEL_WRITE (1U << LINK_REG_CFIFOSEL_ISEL_Pos) /* FIFO write AKA TX*/ +#define LINK_REG_FIFOSEL_BIGEND (1U << LINK_REG_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */ +#define LINK_REG_FIFOSEL_MBW_8BIT (0U << LINK_REG_CFIFOSEL_MBW_Pos) /* 8-bit width */ +#define LINK_REG_FIFOSEL_MBW_16BIT (1U << LINK_REG_CFIFOSEL_MBW_Pos) /* 16-bit width */ -#define LINK_REG_FIFOSEL_BIGEND (1U << LINK_REG_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */ -#define LINK_REG_FIFOSEL_MBW_8BIT (0U << LINK_REG_CFIFOSEL_MBW_Pos) /* 8-bit width */ -#define LINK_REG_FIFOSEL_MBW_16BIT (1U << LINK_REG_CFIFOSEL_MBW_Pos) /* 16-bit width */ +#define LINK_REG_INTSTS0_CTSQ_CTRL_RDATA (1U << LINK_REG_INTSTS0_CTSQ_Pos) -#define LINK_REG_INTSTS0_CTSQ_CTRL_RDATA (1U << LINK_REG_INTSTS0_CTSQ_Pos) +#define LINK_REG_INTSTS0_DVSQ_STATE_DEF (1U << LINK_REG_INTSTS0_DVSQ_Pos) /* Default state */ +#define LINK_REG_INTSTS0_DVSQ_STATE_ADDR (2U << LINK_REG_INTSTS0_DVSQ_Pos) /* Address state */ +#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP0 (4U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ +#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP1 (5U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ +#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP2 (6U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ +#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP3 (7U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_DEF (1U << LINK_REG_INTSTS0_DVSQ_Pos) /* Default state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_ADDR (2U << LINK_REG_INTSTS0_DVSQ_Pos) /* Address state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP0 (4U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP1 (5U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP2 (6U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP3 (7U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ +#define LINK_REG_PIPECFG_TYPE_BULK (1U << LINK_REG_PIPECFG_TYPE_Pos) +#define LINK_REG_PIPECFG_TYPE_INT (2U << LINK_REG_PIPECFG_TYPE_Pos) +#define LINK_REG_PIPECFG_TYPE_ISO (3U << LINK_REG_PIPECFG_TYPE_Pos) + +//--------------------------------------------------------------------+ +// Static Assert +//--------------------------------------------------------------------+ + +TU_VERIFY_STATIC(sizeof(LINK_REG_PIPE_TR_t) == 4, "incorrect size"); -#define LINK_REG_PIPECFG_TYPE_BULK (1U << LINK_REG_PIPECFG_TYPE_Pos) -#define LINK_REG_PIPECFG_TYPE_INT (2U << LINK_REG_PIPECFG_TYPE_Pos) -#define LINK_REG_PIPECFG_TYPE_ISO (3U << LINK_REG_PIPECFG_TYPE_Pos) +TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSCFG ) == 0x00000000, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BUSWAIT ) == 0x00000002, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSSTS0 ) == 0x00000004, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PLLSTA ) == 0x00000006, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DVSTCTR0 ) == 0x00000008, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, TESTMODE ) == 0x0000000C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFO ) == 0x00000014, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFO ) == 0x00000018, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFO ) == 0x0000001C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOSEL ) == 0x00000020, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOCTR ) == 0x00000022, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOSEL ) == 0x00000028, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOCTR ) == 0x0000002A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOSEL ) == 0x0000002C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOCTR ) == 0x0000002E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB0 ) == 0x00000030, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB1 ) == 0x00000032, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYENB ) == 0x00000036, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYENB ) == 0x00000038, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPENB ) == 0x0000003A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, SOFCFG ) == 0x0000003C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSET ) == 0x0000003E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS0 ) == 0x00000040, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS1 ) == 0x00000042, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYSTS ) == 0x00000046, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYSTS ) == 0x00000048, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPSTS ) == 0x0000004A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, FRMNUM ) == 0x0000004C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, UFRMNUM ) == 0x0000004E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBADDR ) == 0x00000050, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBREQ ) == 0x00000054, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBVAL ) == 0x00000056, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBINDX ) == 0x00000058, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBLENG ) == 0x0000005A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCFG ) == 0x0000005C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPMAXP ) == 0x0000005E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCTR ) == 0x00000060, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPESEL ) == 0x00000064, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPECFG ) == 0x00000068, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEMAXP ) == 0x0000006C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEPERI ) == 0x0000006E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_CTR ) == 0x00000070, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_TR ) == 0x00000090, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBBCCTRL0 ) == 0x000000B0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, UCKSEL ) == 0x000000C4, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBMC ) == 0x000000CC, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DEVADD ) == 0x000000D0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSLEW ) == 0x000000F0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPCTRL ) == 0x00000100, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPSTS ) == 0x00000102, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BCCTRL ) == 0x00000140, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL1 ) == 0x00000144, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL2 ) == 0x00000146, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL1 ) == 0x00000148, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL2 ) == 0x0000014A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R ) == 0x00000160, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R ) == 0x00000164, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR2R ) == 0x00000168, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSRCR ) == 0x0000016A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R_FS ) == 0x00000400, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect offset"); #ifdef __cplusplus } -- cgit v1.3.1 From 0f8e530de175e8fb289870fdd7c28ec0b16314e2 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 8 Mar 2023 23:00:01 +0700 Subject: fix incorrect merge of hcd link --- src/portable/renesas/link/hcd_link.c | 484 ++++++++++++++--------------------- 1 file changed, 194 insertions(+), 290 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c index a10fe54ea..f1ea2b821 100644 --- a/src/portable/renesas/link/hcd_link.c +++ b/src/portable/renesas/link/hcd_link.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021 Koji Kitayama @@ -27,86 +27,37 @@ #include "tusb_option.h" -#if CFG_TUH_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \ - CFG_TUSB_MCU == OPT_MCU_RX65X || \ - CFG_TUSB_MCU == OPT_MCU_RX72N ) +#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \ + CFG_TUSB_MCU == OPT_MCU_RX65X || \ + CFG_TUSB_MCU == OPT_MCU_RX72N || \ + CFG_TUSB_MCU == OPT_MCU_RAXXX) + #include "host/hcd.h" -#include "iodefine.h" +#include "link_type.h" + +#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) +#include "link_rx.h" +#elif TU_CHECK_MCU(OPT_MCU_RAXXX) +#include "link_ra.h" +#else +#error "Unsupported MCU" +#endif //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ -#define SYSTEM_PRCR_PRC1 (1<<1) -#define SYSTEM_PRCR_PRKEY (0xA5u<<8) - -#define USB_DVSTCTR0_LOW (1u) -#define USB_DVSTCTR0_FULL (2u) - -#define USB_FIFOSEL_TX ((uint16_t)(1u<<5)) -#define USB_FIFOSEL_BIGEND ((uint16_t)(1u<<8)) -#define USB_FIFOSEL_MBW_8 ((uint16_t)(0u<<10)) -#define USB_FIFOSEL_MBW_16 ((uint16_t)(1u<<10)) -#define USB_IS0_CTSQ ((uint16_t)(7u)) -#define USB_IS0_DVSQ ((uint16_t)(7u<<4)) -#define USB_IS0_VALID ((uint16_t)(1u<<3)) -#define USB_IS0_BRDY ((uint16_t)(1u<<8)) -#define USB_IS0_NRDY ((uint16_t)(1u<<9)) -#define USB_IS0_BEMP ((uint16_t)(1u<<10)) -#define USB_IS0_CTRT ((uint16_t)(1u<<11)) -#define USB_IS0_DVST ((uint16_t)(1u<<12)) -#define USB_IS0_SOFR ((uint16_t)(1u<<13)) -#define USB_IS0_RESM ((uint16_t)(1u<<14)) -#define USB_IS0_VBINT ((uint16_t)(1u<<15)) -#define USB_IS1_SACK ((uint16_t)(1u<<4)) -#define USB_IS1_SIGN ((uint16_t)(1u<<5)) -#define USB_IS1_EOFERR ((uint16_t)(1u<<6)) -#define USB_IS1_ATTCH ((uint16_t)(1u<<11)) -#define USB_IS1_DTCH ((uint16_t)(1u<<12)) -#define USB_IS1_BCHG ((uint16_t)(1u<<14)) -#define USB_IS1_OVRCR ((uint16_t)(1u<<15)) - -#define USB_IS0_CTSQ_MSK (7u) -#define USB_IS0_CTSQ_SETUP (1u) -#define USB_IS0_DVSQ_DEF (1u<<4) -#define USB_IS0_DVSQ_ADDR (2u<<4) -#define USB_IS0_DVSQ_SUSP0 (4u<<4) -#define USB_IS0_DVSQ_SUSP1 (5u<<4) -#define USB_IS0_DVSQ_SUSP2 (6u<<4) -#define USB_IS0_DVSQ_SUSP3 (7u<<4) - -#define USB_PIPECTR_PID_MSK (3u) -#define USB_PIPECTR_PID_NAK (0u) -#define USB_PIPECTR_PID_BUF (1u) -#define USB_PIPECTR_PID_STALL (2u) -#define USB_PIPECTR_CCPL (1u<<2) -#define USB_PIPECTR_SQMON (1u<<6) -#define USB_PIPECTR_SQCLR (1u<<8) -#define USB_PIPECTR_ACLRM (1u<<9) -#define USB_PIPECTR_INBUFM (1u<<14) -#define USB_PIPECTR_BSTS (1u<<15) - -#define USB_FIFOCTR_DTLN (0x1FF) -#define USB_FIFOCTR_FRDY (1u<<13) -#define USB_FIFOCTR_BCLR (1u<<14) -#define USB_FIFOCTR_BVAL (1u<<15) - -#define USB_PIPECFG_SHTNAK (1u<<7) -#define USB_PIPECFG_DBLB (1u<<9) -#define USB_PIPECFG_BULK (1u<<14) -#define USB_PIPECFG_ISO (3u<<14) -#define USB_PIPECFG_INT (2u<<14) - -#define USB_DEVADD_LOW (1u<<6) -#define USB_DEVADD_FULL (2u<<6) - -#define FIFO_REQ_CLR (1u) -#define FIFO_COMPLETE (1u<<1) - -// Start of definition of packed structs (used by the CCRX toolchain) + +/* LINK core registers */ +#if defined(__CCRX__) +#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE) +#else +#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE) +#endif + TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN -typedef struct { +typedef struct TU_ATTR_PACKED { union { struct { uint16_t : 8; @@ -119,7 +70,7 @@ typedef struct { uint16_t TRN; } reg_pipetre_t; -typedef union { +typedef union TU_ATTR_PACKED { struct { volatile uint16_t u8: 8; volatile uint16_t : 0; @@ -127,8 +78,7 @@ typedef union { volatile uint16_t u16; } hw_fifo_t; -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { void *buf; /* the start address of a transfer data buffer */ uint16_t length; /* the number of bytes in the buffer */ uint16_t remaining; /* the number of bytes remaining in the buffer */ @@ -156,28 +106,6 @@ typedef struct //--------------------------------------------------------------------+ static hcd_data_t _hcd; -static uint32_t disable_interrupt(void) -{ - uint32_t pswi; -#if defined(__CCRX__) - pswi = get_psw() & 0x010000; - clrpsw_i(); -#else - pswi = __builtin_rx_mvfc(0) & 0x010000; - __builtin_rx_clrpsw('I'); -#endif - return pswi; -} - -static void enable_interrupt(uint32_t pswi) -{ -#if defined(__CCRX__) - set_psw(get_psw() | pswi); -#else - __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi); -#endif -} - static unsigned find_pipe(unsigned xfer) { switch (xfer) { @@ -208,58 +136,49 @@ static unsigned find_pipe(unsigned xfer) static volatile uint16_t* get_pipectr(unsigned num) { - volatile uint16_t *ctr = NULL; if (num) { - ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD; - ctr += num - 1; + return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]); } else { - ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD; + return (volatile uint16_t*)&(LINK_REG->DCPCTR); } - return ctr; } static volatile reg_pipetre_t* get_pipetre(unsigned num) { volatile reg_pipetre_t* tre = NULL; if ((1 <= num) && (num <= 5)) { - tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD; - tre += num - 1; + tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E); } return tre; } static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr) { - volatile uint16_t *ctr = NULL; - const unsigned epn = tu_edpt_number(ep_addr); + const unsigned epn = tu_edpt_number(ep_addr); if (epn) { const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1]; - if (num) { - ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD; - ctr += num - 1; - } + const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1]; + return get_pipectr(num); } else { - ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD; + return get_pipectr(0); } - return ctr; } static unsigned edpt0_max_packet_size(void) { - return USB0.DCPMAXP.BIT.MXPS; + return LINK_REG->DCPMAXP_b.MXPS; } static unsigned edpt_max_packet_size(unsigned num) { - USB0.PIPESEL.WORD = num; - return USB0.PIPEMAXP.BIT.MXPS; + LINK_REG->PIPESEL = num; + return LINK_REG->PIPEMAXP_b.MXPS; } static inline void pipe_wait_for_ready(unsigned num) { - while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ; - while (!USB0.D0FIFOCTR.BIT.FRDY) ; + while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ; + while (!LINK_REG->D0FIFOCTR_b.FRDY) ; } static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) @@ -290,21 +209,22 @@ static bool pipe0_xfer_in(void) const unsigned rem = pipe->remaining; const unsigned mps = edpt0_max_packet_size(); - const unsigned vld = USB0.CFIFOCTR.BIT.DTLN; + const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { - USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; - pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len); + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; + pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } - if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR; + if (len < mps) + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; return true; } - USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF; + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF; return false; } @@ -320,10 +240,11 @@ static bool pipe0_xfer_out(void) const unsigned len = TU_MIN(mps, rem); void *buf = pipe->buf; if (len) { - pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len); + pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } - if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL; + if (len < mps) + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; pipe->remaining = rem - len; return false; } @@ -333,20 +254,21 @@ static bool pipe_xfer_in(unsigned num) pipe_state_t *pipe = &_hcd.pipe[num]; const unsigned rem = pipe->remaining; - USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8; + LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT; const unsigned mps = edpt_max_packet_size(num); pipe_wait_for_ready(num); - const unsigned vld = USB0.D0FIFOCTR.BIT.DTLN; + const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { - pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len); + pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } - if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - pipe->remaining = rem - len; + if (len < mps) + LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; return NULL != buf; @@ -364,18 +286,19 @@ static bool pipe_xfer_out(unsigned num) return true; } - USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); + LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); const unsigned mps = edpt_max_packet_size(num); pipe_wait_for_ready(num); const unsigned len = TU_MIN(rem, mps); void *buf = pipe->buf; if (len) { - pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len); + pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } - if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + if (len < mps) + LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; return false; } @@ -387,11 +310,12 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, /* configure fifo direction and access unit settings */ if (dir_in) { /* IN, a byte */ - USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8; - while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ; - } else { /* OUT, 2 bytes */ - USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0); - while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ; + LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT; + while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ; + } else { /* OUT, 2 bytes */ + LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT | + (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); + while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ; } pipe_state_t *pipe = &_hcd.pipe[0]; @@ -401,25 +325,25 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, if (buflen) { pipe->buf = buffer; if (!dir_in) { /* OUT */ - TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80)); + TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80)); pipe0_xfer_out(); } } else { /* ZLP */ pipe->buf = NULL; if (!dir_in) { /* OUT */ - USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL; + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; } - if (dir_in == USB0.DCPCFG.BIT.DIR) { - TU_ASSERT(USB_PIPECTR_PID_NAK == USB0.DCPCTR.BIT.PID); - USB0.DCPCTR.BIT.SQSET = 1; - USB0.DCPCFG.BIT.DIR = dir_in ^ 1; + if (dir_in == LINK_REG->DCPCFG_b.DIR) { + TU_ASSERT(LINK_REG_PIPE_CTR_PID_NAK == LINK_REG->DCPCTR_b.PID); + LINK_REG->DCPCTR_b.SQSET = 1; + LINK_REG->DCPCFG_b.DIR = dir_in ^ 1; } } - USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF; + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF; return true; } -static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) +static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen) { const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir_in = tu_edpt_dir(ep_addr); @@ -435,23 +359,23 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, u if (buflen) { pipe_xfer_out(num); } else { /* ZLP */ - USB0.D0FIFOSEL.WORD = num; + LINK_REG->D0FIFOSEL = num; pipe_wait_for_ready(num); - USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL; - USB0.D0FIFOSEL.WORD = 0; - while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */ } } else { volatile uint16_t *ctr = get_pipectr(num); volatile reg_pipetre_t *pt = get_pipetre(num); if (pt) { const unsigned mps = edpt_max_packet_size(num); - if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK; + if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK; pt->TRE = TU_BIT(8); pt->TRN = (buflen + mps - 1) / mps; pt->TRENB = 1; } - *ctr = USB_PIPECTR_PID_BUF; + *ctr = LINK_REG_PIPE_CTR_PID_BUF; } return true; } @@ -485,10 +409,10 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num) unsigned result; uint16_t volatile *ctr = get_pipectr(num); // TU_LOG1("NRDY %d %x\n", num, *ctr); - switch (*ctr & USB_PIPECTR_PID_MSK) { + switch (*ctr & LINK_REG_PIPE_CTR_PID_Msk) { default: return; - case USB_PIPECTR_PID_STALL: result = XFER_RESULT_STALLED; break; - case USB_PIPECTR_PID_NAK: result = XFER_RESULT_FAILED; break; + case LINK_REG_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break; + case LINK_REG_PIPE_CTR_PID_NAK: result = XFER_RESULT_FAILED; break; } pipe_state_t *pipe = &_hcd.pipe[num]; hcd_event_xfer_complete(pipe->dev, pipe->ep, @@ -520,78 +444,60 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num) } } - /*------------------------------------------------------------------*/ /* Host API *------------------------------------------------------------------*/ bool hcd_init(uint8_t rhport) { (void)rhport; - /* Enable USB0 */ - uint32_t pswi = disable_interrupt(); - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; - MSTP(USB0) = 0; - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; - enable_interrupt(pswi); - USB0.SYSCFG.BIT.SCKE = 1; - while (!USB0.SYSCFG.BIT.SCKE) ; - USB0.SYSCFG.BIT.DPRPU = 0; - USB0.SYSCFG.BIT.DRPD = 0; - USB0.SYSCFG.BIT.DCFM = 1; - - USB0.DVSTCTR0.BIT.VBUSEN = 1; - - USB0.SYSCFG.BIT.DRPD = 1; + + LINK_REG->SYSCFG_b.SCKE = 1; + while (!LINK_REG->SYSCFG_b.SCKE) ; + LINK_REG->SYSCFG_b.DPRPU = 0; + LINK_REG->SYSCFG_b.DRPD = 0; + LINK_REG->SYSCFG_b.DCFM = 1; + + LINK_REG->DVSTCTR0_b.VBUSEN = 1; + + LINK_REG->SYSCFG_b.DRPD = 1; for (volatile int i = 0; i < 30000; ++i) ; - USB0.SYSCFG.BIT.USBE = 1; + LINK_REG->SYSCFG_b.USBE = 1; - USB.DPUSR0R.BIT.FIXPHY0 = 0u; /* USB0 Transceiver Output fixed */ -#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) - USB0.PHYSLEW.LONG = 0x5; - IR(PERIB, INTB185) = 0; -#else - IR(USB0, USBI0) = 0; -#endif + // MCU specific PHY init + link_phy_init(); + + LINK_REG->PHYSLEW = 0x5; + LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */ /* Setup default control pipe */ - USB0.DCPCFG.WORD = USB_PIPECFG_SHTNAK; - USB0.DCPMAXP.WORD = 64; - USB0.INTENB0.WORD = USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP; - USB0.INTENB1.WORD = USB_IS1_SACK | USB_IS1_SIGN | - USB_IS1_ATTCH | USB_IS1_DTCH; - USB0.BEMPENB.WORD = 1; - USB0.NRDYENB.WORD = 1; - USB0.BRDYENB.WORD = 1; + LINK_REG->DCPCFG = LINK_REG_PIPECFG_SHTNAK_Msk; + LINK_REG->DCPMAXP = 64; + LINK_REG->INTENB0 = LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk; + LINK_REG->INTENB1 = LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk; + LINK_REG->BEMPENB = 1; + LINK_REG->NRDYENB = 1; + LINK_REG->BRDYENB = 1; + return true; } void hcd_int_enable(uint8_t rhport) { - (void)rhport; -#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) - IEN(PERIB, INTB185) = 1; -#else - IEN(USB0, USBI0) = 1; -#endif + link_int_enable(rhport); } void hcd_int_disable(uint8_t rhport) { - (void)rhport; -#if ( CFG_TUSB_MCU == OPT_MCU_RX72N ) - IEN(PERIB, INTB185) = 0; -#else - IEN(USB0, USBI0) = 0; -#endif + link_int_disable(rhport); } uint32_t hcd_frame_number(uint8_t rhport) { (void)rhport; - /* The device must be reset at least once after connection + /* The device must be reset at least once after connection * in order to start the frame counter. */ if (_hcd.need_reset) hcd_port_reset(rhport); - return USB0.FRMNUM.BIT.FRNM; + return LINK_REG->FRMNUM_b.FRNM; } /*--------------------------------------------------------------------+ @@ -605,18 +511,18 @@ bool hcd_port_connect_status(uint8_t rhport) void hcd_port_reset(uint8_t rhport) { - USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; - while (USB0.DCPCTR.BIT.PBUSY) ; + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; + while (LINK_REG->DCPCTR_b.PBUSY) ; hcd_int_disable(rhport); - USB0.DVSTCTR0.BIT.UACT = 0; - if (USB0.DCPCTR.BIT.SUREQ) - USB0.DCPCTR.BIT.SUREQCLR = 1; + LINK_REG->DVSTCTR0_b.UACT = 0; + if (LINK_REG->DCPCTR_b.SUREQ) + LINK_REG->DCPCTR_b.SUREQCLR = 1; hcd_int_enable(rhport); /* Reset should be asserted 10-20ms. */ - USB0.DVSTCTR0.BIT.USBRST = 1; + LINK_REG->DVSTCTR0_b.USBRST = 1; for (volatile int i = 0; i < 2400000; ++i) ; - USB0.DVSTCTR0.BIT.USBRST = 0; - USB0.DVSTCTR0.BIT.UACT = 1; + LINK_REG->DVSTCTR0_b.USBRST = 0; + LINK_REG->DVSTCTR0_b.UACT = 1; _hcd.need_reset = false; } @@ -628,10 +534,10 @@ void hcd_port_reset_end(uint8_t rhport) tusb_speed_t hcd_port_speed_get(uint8_t rhport) { (void)rhport; - switch (USB0.DVSTCTR0.BIT.RHST) { + switch (LINK_REG->DVSTCTR0_b.RHST) { default: return TUSB_SPEED_INVALID; - case USB_DVSTCTR0_FULL: return TUSB_SPEED_FULL; - case USB_DVSTCTR0_LOW: return TUSB_SPEED_LOW; + case LINK_REG_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL; + case LINK_REG_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW; } } @@ -647,13 +553,13 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) unsigned num = *ep; if (!num || dev_addr != _hcd.pipe[num].dev) continue; - ctr = (uint16_t volatile*)&USB0.PIPE1CTR.WORD + num - 1; + ctr = (uint16_t volatile*)&LINK_REG->PIPE_CTR[num - 1]; *ctr = 0; - USB0.NRDYENB.WORD &= ~TU_BIT(num); - USB0.BRDYENB.WORD &= ~TU_BIT(num); - USB0.PIPESEL.WORD = num; - USB0.PIPECFG.WORD = 0; - USB0.PIPEMAXP.WORD = 0; + LINK_REG->NRDYENB &= ~TU_BIT(num); + LINK_REG->BRDYENB &= ~TU_BIT(num); + LINK_REG->PIPESEL = num; + LINK_REG->PIPECFG = 0; + LINK_REG->PIPEMAXP = 0; _hcd.pipe[num].ep = 0; _hcd.pipe[num].dev = 0; @@ -667,36 +573,36 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { (void)rhport; - // TU_LOG1("S %d %x\n", dev_addr, USB0.DCPCTR.WORD); + // TU_LOG1("S %d %x\n", dev_addr, LINK_REG->DCPCTR); TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ - TU_ASSERT(0 == USB0.DCPCTR.BIT.SUREQ); + TU_ASSERT(0 == LINK_REG->DCPCTR_b.SUREQ); - USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; - _hcd.pipe[0].buf = NULL; - _hcd.pipe[0].length = 8; + _hcd.pipe[0].buf = NULL; + _hcd.pipe[0].length = 8; _hcd.pipe[0].remaining = 0; - _hcd.pipe[0].dev = dev_addr; + _hcd.pipe[0].dev = dev_addr; - while (USB0.DCPCTR.BIT.PBUSY) ; - USB0.DCPMAXP.WORD = (dev_addr << 12) | _hcd.ctl_mps[dev_addr]; + while (LINK_REG->DCPCTR_b.PBUSY) ; + LINK_REG->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr]; /* Set direction in advance for DATA stage */ uint8_t const bmRequesttype = setup_packet[0]; - USB0.DCPCFG.BIT.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1; + LINK_REG->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1; uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0]; - USB0.USBREQ.WORD = tu_htole16(p[0]); - USB0.USBVAL = p[1]; - USB0.USBINDX = p[2]; - USB0.USBLENG = p[3]; + LINK_REG->USBREQ = tu_htole16(p[0]); + LINK_REG->USBVAL = p[1]; + LINK_REG->USBINDX = p[2]; + LINK_REG->USBLENG = p[3]; - USB0.DCPCTR.BIT.SUREQ = 1; + LINK_REG->DCPCTR_b.SUREQ = 1; return true; } -bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *ep_desc) { (void)rhport; TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ @@ -705,14 +611,14 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const const unsigned epn = tu_edpt_number(ep_addr); const unsigned mps = tu_edpt_packet_size(ep_desc); if (0 == epn) { - USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK; + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; hcd_devtree_info_t devtree; hcd_devtree_get_info(dev_addr, &devtree); - uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t)&USB0.DEVADD0.WORD; + uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &LINK_REG->DEVADD[0]; devadd += dev_addr; - while (USB0.DCPCTR.BIT.PBUSY) ; - USB0.DCPMAXP.WORD = (dev_addr << 12) | mps; - *devadd = (TUSB_SPEED_FULL == devtree.speed) ? USB_DEVADD_FULL : USB_DEVADD_LOW; + while (LINK_REG->DCPCTR_b.PBUSY) ; + LINK_REG->DCPMAXP = (dev_addr << 12) | mps; + *devadd = (TUSB_SPEED_FULL == devtree.speed) ? LINK_REG_DEVADD_USBSPD_FS : LINK_REG_DEVADD_USBSPD_LS; _hcd.ctl_mps[dev_addr] = mps; return true; } @@ -731,25 +637,25 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const /* setup pipe */ hcd_int_disable(rhport); - USB0.PIPESEL.WORD = num; - USB0.PIPEMAXP.WORD = (dev_addr << 12) | mps; + LINK_REG->PIPESEL = num; + LINK_REG->PIPEMAXP = (dev_addr << 12) | mps; volatile uint16_t *ctr = get_pipectr(num); - *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR; + *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk; *ctr = 0; unsigned cfg = ((1 ^ dir_in) << 4) | epn; if (xfer == TUSB_XFER_BULK) { - cfg |= USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB; + cfg |= LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk; } else if (xfer == TUSB_XFER_INTERRUPT) { - cfg |= USB_PIPECFG_INT; + cfg |= LINK_REG_PIPECFG_TYPE_INT; } else { - cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB; + cfg |= LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk; } - USB0.PIPECFG.WORD = cfg; - USB0.BRDYSTS.WORD = 0x1FFu ^ TU_BIT(num); - USB0.NRDYENB.WORD |= TU_BIT(num); - USB0.BRDYENB.WORD |= TU_BIT(num); + LINK_REG->PIPECFG = cfg; + LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num); + LINK_REG->NRDYENB |= TU_BIT(num); + LINK_REG->BRDYENB |= TU_BIT(num); if (!dir_in) { - *ctr = USB_PIPECTR_PID_BUF; + *ctr = LINK_REG_PIPE_CTR_PID_BUF; } hcd_int_enable(rhport); @@ -776,12 +682,12 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) *ctr = pid & 2; *ctr = 0; } - *ctr = USB_PIPECTR_SQCLR; + *ctr = LINK_REG_PIPE_CTR_SQCLR_Msk; unsigned const epn = tu_edpt_number(ep_addr); if (!epn) return true; if (!tu_edpt_dir(ep_addr)) { /* OUT */ - *ctr = USB_PIPECTR_PID_BUF; + *ctr = LINK_REG_PIPE_CTR_PID_BUF; } return true; } @@ -799,52 +705,50 @@ void hcd_int_handler(uint8_t rhport) 20, 8, 19, 18}; #endif - unsigned is1 = USB0.INTSTS1.WORD; - unsigned is0 = USB0.INTSTS0.WORD; + unsigned is1 = LINK_REG->INTSTS1; + unsigned is0 = LINK_REG->INTSTS0; /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ - USB0.INTSTS1.WORD = ~((USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH) & is1); - USB0.INTSTS0.WORD = ~((USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP) & is0); + LINK_REG->INTSTS1 = ~((LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk) & is1); + LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk) & is0); // TU_LOG1("IS %04x %04x\n", is0, is1); - is1 &= USB0.INTENB1.WORD; - is0 &= USB0.INTENB0.WORD; + is1 &= LINK_REG->INTENB1; + is0 &= LINK_REG->INTENB0; - if (is1 & USB_IS1_SACK) { + if (is1 & LINK_REG_INTSTS1_SACK_Msk) { /* Set DATA1 in advance for the next transfer. */ - USB0.DCPCTR.BIT.SQSET = 1; - hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL, - tu_edpt_addr(0, TUSB_DIR_OUT), - 8, XFER_RESULT_SUCCESS, true); + LINK_REG->DCPCTR_b.SQSET = 1; + hcd_event_xfer_complete( + LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); } - if (is1 & USB_IS1_SIGN) { - hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL, - tu_edpt_addr(0, TUSB_DIR_OUT), - 8, XFER_RESULT_FAILED, true); + if (is1 & LINK_REG_INTSTS1_SIGN_Msk) { + hcd_event_xfer_complete( + LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); } - if (is1 & USB_IS1_ATTCH) { - USB0.DVSTCTR0.BIT.UACT = 1; + if (is1 & LINK_REG_INTSTS1_ATTCH_Msk) { + LINK_REG->DVSTCTR0_b.UACT = 1; _hcd.need_reset = true; - USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_ATTCH) | USB_IS1_DTCH; + LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_ATTCH_Msk) | LINK_REG_INTSTS1_DTCH_Msk; hcd_event_device_attach(rhport, true); } - if (is1 & USB_IS1_DTCH) { - USB0.DVSTCTR0.BIT.UACT = 0; - if (USB0.DCPCTR.BIT.SUREQ) - USB0.DCPCTR.BIT.SUREQCLR = 1; - USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_DTCH) | USB_IS1_ATTCH; + if (is1 & LINK_REG_INTSTS1_DTCH_Msk) { + LINK_REG->DVSTCTR0_b.UACT = 0; + if (LINK_REG->DCPCTR_b.SUREQ) + LINK_REG->DCPCTR_b.SUREQCLR = 1; + LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_DTCH_Msk) | LINK_REG_INTSTS1_ATTCH_Msk; hcd_event_device_remove(rhport, true); } - if (is0 & USB_IS0_BEMP) { - const unsigned s = USB0.BEMPSTS.WORD; - USB0.BEMPSTS.WORD = 0; + if (is0 & LINK_REG_INTSTS0_BEMP_Msk) { + const unsigned s = LINK_REG->BEMPSTS; + LINK_REG->BEMPSTS = 0; if (s & 1) { process_pipe0_bemp(rhport); } } - if (is0 & USB_IS0_NRDY) { - const unsigned m = USB0.NRDYENB.WORD; - unsigned s = USB0.NRDYSTS.WORD & m; - USB0.NRDYSTS.WORD = ~s; + if (is0 & LINK_REG_INTSTS0_NRDY_Msk) { + const unsigned m = LINK_REG->NRDYENB; + unsigned s = LINK_REG->NRDYSTS & m; + LINK_REG->NRDYSTS = ~s; while (s) { #if defined(__CCRX__) const unsigned num = Mod37BitPosition[(-s & s) % 37]; @@ -855,11 +759,11 @@ void hcd_int_handler(uint8_t rhport) s &= ~TU_BIT(num); } } - if (is0 & USB_IS0_BRDY) { - const unsigned m = USB0.BRDYENB.WORD; - unsigned s = USB0.BRDYSTS.WORD & m; + if (is0 & LINK_REG_INTSTS0_BRDY_Msk) { + const unsigned m = LINK_REG->BRDYENB; + unsigned s = LINK_REG->BRDYSTS & m; /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ - USB0.BRDYSTS.WORD = ~s; + LINK_REG->BRDYSTS = ~s; while (s) { #if defined(__CCRX__) const unsigned num = Mod37BitPosition[(-s & s) % 37]; -- cgit v1.3.1 From f0ddf8d10f7d58592d2ebb60025b227c8047114d Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Thu, 9 Mar 2023 14:00:37 +0100 Subject: dcd_nrf5x: ISO OUT handling For incoming ISO OUT packets it was possible to start DMA from endpoint to RAM before transfer was started resulting in unrelated memory corruption. This is scenario that causes memory corruption: - ISO OUT packet is received - Packet is transferred by DMA to transfer buffer - xfer->started is cleared and xfer->buffer is updated as it is in every case - Application takes to long to handle it (it happens when debugger is connected breakpoint is hit slowing down software). - Next ISO OUT packet arrives At this point there was no check if transfer was started and packet was copied by DMA to location beyond previous data, possibly overwriting unrelated memory. This solves the issue by checking that transfer was started and there is buffer ready for incoming packet. --- src/portable/nordic/nrf5x/dcd_nrf5x.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index afc14b010..4aeb85fc0 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -187,11 +187,16 @@ static void xact_out_dma(uint8_t epnum) } else { - // Trigger DMA move data from Endpoint -> SRAM - NRF_USBD->ISOOUT.PTR = (uint32_t) xfer->buffer; - NRF_USBD->ISOOUT.MAXCNT = xact_len; + if (xfer->started) + { + // Trigger DMA move data from Endpoint -> SRAM + NRF_USBD->ISOOUT.PTR = (uint32_t) xfer->buffer; + NRF_USBD->ISOOUT.MAXCNT = xact_len; - start_dma(&NRF_USBD->TASKS_STARTISOOUT); + start_dma(&NRF_USBD->TASKS_STARTISOOUT); + } else { + atomic_flag_clear(&_dcd.dma_running); + } } } else -- cgit v1.3.1 From 4857abdc6bc58ebd06ce87c0139ed8a789b0d440 Mon Sep 17 00:00:00 2001 From: Dan Halbert Date: Fri, 10 Mar 2023 14:01:51 -0500 Subject: rp2040: include hardware/sync.h explicitly --- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 8df7bef2b..37dec1cbf 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -29,6 +29,7 @@ #if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUD_RPI_PIO_USB #include "pico.h" +#include "hardware/sync.h" #include "rp2040_usb.h" #if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX -- cgit v1.3.1 From 0a7c08d16e10b9a252c7daeb3fe9b3abdd6ff225 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 12 Mar 2023 16:01:24 +0700 Subject: minor format --- src/portable/renesas/link/dcd_link.c | 57 +++++++++++++++++++++------ src/portable/renesas/link/hcd_link.c | 76 ++++++++++++++++++++++++++---------- src/portable/renesas/link/link_rx.h | 6 +-- 3 files changed, 104 insertions(+), 35 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c index dcbd68b8d..ce29769e0 100644 --- a/src/portable/renesas/link/dcd_link.c +++ b/src/portable/renesas/link/dcd_link.c @@ -31,10 +31,8 @@ // We disable SOF for now until needed later on #define USE_SOF 0 -#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \ - CFG_TUSB_MCU == OPT_MCU_RX65X || \ - CFG_TUSB_MCU == OPT_MCU_RX72N || \ - CFG_TUSB_MCU == OPT_MCU_RAXXX) +#if CFG_TUD_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \ + TU_CHECK_MCU(OPT_MCU_RAXXX)) #include "device/dcd.h" #include "link_type.h" @@ -250,8 +248,9 @@ static bool pipe0_xfer_in(void) pipe->buf = (uint8_t*)buf + len; } } - if (len < mps) + if (len < mps) { LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + } pipe->remaining = rem - len; return false; } @@ -273,8 +272,9 @@ static bool pipe0_xfer_out(void) pipe->buf = (uint8_t*)buf + len; } } - if (len < mps) + if (len < mps) { LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; + } pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; @@ -306,10 +306,11 @@ static bool pipe_xfer_in(unsigned num) pipe->buf = (uint8_t*)buf + len; } } - if (len < mps) + if (len < mps) { LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + } LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */ + while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; return false; } @@ -333,10 +334,11 @@ static bool pipe_xfer_out(unsigned num) pipe->buf = (uint8_t*)buf + len; } } - if (len < mps) + if (len < mps) { LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; + } LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; @@ -377,7 +379,7 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u /* configure fifo direction and access unit settings */ if (ep_addr) { /* IN, 2 bytes */ LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT | - (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); + (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ; } else { /* OUT, a byte */ LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT; @@ -541,10 +543,43 @@ static void process_set_address(uint8_t rhport) /*------------------------------------------------------------------*/ /* Device API *------------------------------------------------------------------*/ + +#if 0 // previously present in the rx driver before generalization +static uint32_t disable_interrupt(void) +{ + uint32_t pswi; +#if defined(__CCRX__) + pswi = get_psw() & 0x010000; + clrpsw_i(); +#else + pswi = __builtin_rx_mvfc(0) & 0x010000; + __builtin_rx_clrpsw('I'); +#endif + return pswi; +} + +static void enable_interrupt(uint32_t pswi) +{ +#if defined(__CCRX__) + set_psw(get_psw() | pswi); +#else + __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi); +#endif +} +#endif + void dcd_init(uint8_t rhport) { (void)rhport; +#if 0 // previously present in the rx driver before generalization + uint32_t pswi = disable_interrupt(); + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; + MSTP(USB0) = 0; + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; + enable_interrupt(pswi); +#endif + LINK_REG->SYSCFG_b.SCKE = 1; while (!LINK_REG->SYSCFG_b.SCKE) ; LINK_REG->SYSCFG_b.DRPD = 0; diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c index f1ea2b821..b16544c2f 100644 --- a/src/portable/renesas/link/hcd_link.c +++ b/src/portable/renesas/link/hcd_link.c @@ -27,10 +27,8 @@ #include "tusb_option.h" -#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \ - CFG_TUSB_MCU == OPT_MCU_RX65X || \ - CFG_TUSB_MCU == OPT_MCU_RX72N || \ - CFG_TUSB_MCU == OPT_MCU_RAXXX) +#if CFG_TUH_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \ + TU_CHECK_MCU(OPT_MCU_RAXXX)) #include "host/hcd.h" #include "link_type.h" @@ -217,8 +215,9 @@ static bool pipe0_xfer_in(void) pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } - if (len < mps) + if (len < mps) { LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; + } pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; @@ -243,8 +242,9 @@ static bool pipe0_xfer_out(void) pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } - if (len < mps) + if (len < mps) { LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + } pipe->remaining = rem - len; return false; } @@ -264,8 +264,9 @@ static bool pipe_xfer_in(unsigned num) pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } - if (len < mps) + if (len < mps) { LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; + } LINK_REG->D0FIFOSEL = 0; while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; @@ -314,7 +315,7 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ; } else { /* OUT, 2 bytes */ LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT | - (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); + (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ; } @@ -363,7 +364,7 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u pipe_wait_for_ready(num); LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */ + while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ } } else { volatile uint16_t *ctr = get_pipectr(num); @@ -447,10 +448,43 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num) /*------------------------------------------------------------------*/ /* Host API *------------------------------------------------------------------*/ + +#if 0 // previously present in the rx driver before generalization +static uint32_t disable_interrupt(void) +{ + uint32_t pswi; +#if defined(__CCRX__) + pswi = get_psw() & 0x010000; + clrpsw_i(); +#else + pswi = __builtin_rx_mvfc(0) & 0x010000; + __builtin_rx_clrpsw('I'); +#endif + return pswi; +} + +static void enable_interrupt(uint32_t pswi) +{ +#if defined(__CCRX__) + set_psw(get_psw() | pswi); +#else + __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi); +#endif +} +#endif + bool hcd_init(uint8_t rhport) { (void)rhport; +#if 0 // previously present in the rx driver before generalization + uint32_t pswi = disable_interrupt(); + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; + MSTP(USB0) = 0; + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; + enable_interrupt(pswi); +#endif + LINK_REG->SYSCFG_b.SCKE = 1; while (!LINK_REG->SYSCFG_b.SCKE) ; LINK_REG->SYSCFG_b.DPRPU = 0; @@ -470,7 +504,7 @@ bool hcd_init(uint8_t rhport) LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */ /* Setup default control pipe */ - LINK_REG->DCPCFG = LINK_REG_PIPECFG_SHTNAK_Msk; + LINK_REG->DCPCFG = LINK_REG_PIPECFG_SHTNAK_Msk; LINK_REG->DCPMAXP = 64; LINK_REG->INTENB0 = LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk; LINK_REG->INTENB1 = LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk; @@ -515,8 +549,9 @@ void hcd_port_reset(uint8_t rhport) while (LINK_REG->DCPCTR_b.PBUSY) ; hcd_int_disable(rhport); LINK_REG->DVSTCTR0_b.UACT = 0; - if (LINK_REG->DCPCTR_b.SUREQ) + if (LINK_REG->DCPCTR_b.SUREQ) { LINK_REG->DCPCTR_b.SUREQCLR = 1; + } hcd_int_enable(rhport); /* Reset should be asserted 10-20ms. */ LINK_REG->DVSTCTR0_b.USBRST = 1; @@ -580,10 +615,10 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; - _hcd.pipe[0].buf = NULL; - _hcd.pipe[0].length = 8; + _hcd.pipe[0].buf = NULL; + _hcd.pipe[0].length = 8; _hcd.pipe[0].remaining = 0; - _hcd.pipe[0].dev = dev_addr; + _hcd.pipe[0].dev = dev_addr; while (LINK_REG->DCPCTR_b.PBUSY) ; LINK_REG->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr]; @@ -593,8 +628,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet LINK_REG->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1; uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0]; - LINK_REG->USBREQ = tu_htole16(p[0]); - LINK_REG->USBVAL = p[1]; + LINK_REG->USBREQ = tu_htole16(p[0]); + LINK_REG->USBVAL = p[1]; LINK_REG->USBINDX = p[2]; LINK_REG->USBLENG = p[3]; @@ -717,12 +752,10 @@ void hcd_int_handler(uint8_t rhport) if (is1 & LINK_REG_INTSTS1_SACK_Msk) { /* Set DATA1 in advance for the next transfer. */ LINK_REG->DCPCTR_b.SQSET = 1; - hcd_event_xfer_complete( - LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); + hcd_event_xfer_complete(LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); } if (is1 & LINK_REG_INTSTS1_SIGN_Msk) { - hcd_event_xfer_complete( - LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); + hcd_event_xfer_complete(LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); } if (is1 & LINK_REG_INTSTS1_ATTCH_Msk) { LINK_REG->DVSTCTR0_b.UACT = 1; @@ -732,8 +765,9 @@ void hcd_int_handler(uint8_t rhport) } if (is1 & LINK_REG_INTSTS1_DTCH_Msk) { LINK_REG->DVSTCTR0_b.UACT = 0; - if (LINK_REG->DCPCTR_b.SUREQ) + if (LINK_REG->DCPCTR_b.SUREQ) { LINK_REG->DCPCTR_b.SUREQCLR = 1; + } LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_DTCH_Msk) | LINK_REG_INTSTS1_ATTCH_Msk; hcd_event_device_remove(rhport, true); } diff --git a/src/portable/renesas/link/link_rx.h b/src/portable/renesas/link/link_rx.h index 62f2911c2..9e31c5b46 100644 --- a/src/portable/renesas/link/link_rx.h +++ b/src/portable/renesas/link/link_rx.h @@ -39,7 +39,7 @@ extern "C" { #define LINK_REG_BASE (0x000A0000) -static inline void link_int_enable(uint8_t rhport) +TU_ATTR_ALWAYS_INLINE static inline void link_int_enable(uint8_t rhport) { (void) rhport; #if (CFG_TUSB_MCU == OPT_MCU_RX72N) @@ -49,7 +49,7 @@ static inline void link_int_enable(uint8_t rhport) #endif } -static inline void link_int_disable(uint8_t rhport) +TU_ATTR_ALWAYS_INLINE static inline void link_int_disable(uint8_t rhport) { (void) rhport; #if (CFG_TUSB_MCU == OPT_MCU_RX72N) @@ -60,7 +60,7 @@ static inline void link_int_disable(uint8_t rhport) } // MCU specific PHY init -static inline void link_phy_init(void) +TU_ATTR_ALWAYS_INLINE static inline void link_phy_init(void) { #if (CFG_TUSB_MCU == OPT_MCU_RX72N) IR(PERIB, INTB185) = 0; -- cgit v1.3.1 From f8a21fff171aa272360c89dab5faca4f688a656a Mon Sep 17 00:00:00 2001 From: Hubert Denkmair Date: Sun, 12 Mar 2023 15:51:07 +0100 Subject: dcd_write_packet_memory: use volatile modifier for destination pointer --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 21ae8e6e8..e2e1cf484 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -1228,8 +1228,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes) { // FIXME original function uses byte-access to source memory (to support non-aligned buffers) - const uint32_t* src32 = (uint32_t*)(src); - uint32_t* dst32 = (uint32_t*)(USB_PMAADDR + dst); + const uint32_t* src32 = (const uint32_t*)(src); + volatile uint32_t* dst32 = (volatile uint32_t*)(USB_PMAADDR + dst); for (unsigned n=wNBytes/4; n>0; --n) { *dst32++ = *src32++; } -- cgit v1.3.1 From f6774d561148c7c2f41b66234d080e9dfd514551 Mon Sep 17 00:00:00 2001 From: James Smith Date: Tue, 7 Feb 2023 20:46:00 -0700 Subject: Implemented tuh_hid_send_report --- src/class/hid/hid_host.c | 48 +++++++++++++++++++++++++++++++++++++++++++++--- src/class/hid/hid_host.h | 4 ++-- 2 files changed, 47 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 42b5e2f4e..22569194f 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -274,7 +274,49 @@ bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance) // return !usbh_edpt_busy(dev_addr, hid_itf->ep_in); //} -//void tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len); +bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len) +{ + TU_LOG2("HID Send Report %d\r\n", report_id); + + hidh_interface_t* hid_itf = get_instance(dev_addr, instance); + + if (hid_itf->ep_out == 0) + { + // This HID does not have an out endpoint (other than control) + return false; + } + else if (len > CFG_TUH_HID_EPOUT_BUFSIZE + || (report_id != 0 && len > (CFG_TUH_HID_EPOUT_BUFSIZE - 1))) + { + // ep_out buffer is not large enough to hold contents + return false; + } + + // claim endpoint + TU_VERIFY( usbh_edpt_claim(dev_addr, hid_itf->ep_out) ); + + if (report_id == 0) + { + // No report ID in transmission + memcpy(&hid_itf->epout_buf[0], report, len); + } + else + { + hid_itf->epout_buf[0] = report_id; + memcpy(&hid_itf->epout_buf[1], report, len); + ++len; // 1 more byte for report_id + } + + TU_LOG3_MEM(hid_itf->epout_buf, len, 2); + + if ( !usbh_edpt_xfer(dev_addr, hid_itf->ep_out, hid_itf->epout_buf, len) ) + { + usbh_edpt_release(dev_addr, hid_itf->ep_out); + return false; + } + + return true; +} //--------------------------------------------------------------------+ // USBH API @@ -349,7 +391,7 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de hidh_device_t* hid_dev = get_dev(dev_addr); TU_ASSERT(hid_dev->inst_count < CFG_TUH_HID, 0); - hidh_interface_t* hid_itf = get_instance(dev_addr, hid_dev->inst_count); + hidh_interface_t* hid_itf = get_instance(dev_addr, hid_dev->inst_count); //------------- Endpoint Descriptors -------------// p_desc = tu_desc_next(p_desc); diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h index ffc601d77..e5f159ca8 100644 --- a/src/class/hid/hid_host.h +++ b/src/class/hid/hid_host.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -106,7 +106,7 @@ bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance); // Send report using interrupt endpoint // If report_id > 0 (composite), it will be sent as 1st byte, then report contents. Otherwise only report content is sent. -//void tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len); +bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len); //--------------------------------------------------------------------+ // Callbacks (Weak is optional) -- cgit v1.3.1 From 296ce528fcc3632205cb7f6f5a2f386169fdbf36 Mon Sep 17 00:00:00 2001 From: James Smith Date: Thu, 9 Feb 2023 19:42:36 -0700 Subject: Updated host hid_controller example to demo tuh_hid_send_report --- examples/host/hid_controller/src/hid_app.c | 87 ++++++++++++++++++++++++++---- src/class/hid/hid_host.c | 2 +- src/class/hid/hid_host.h | 2 +- 3 files changed, 80 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c index 75c91400e..0444d6eb5 100644 --- a/examples/host/hid_controller/src/hid_app.c +++ b/examples/host/hid_controller/src/hid_app.c @@ -91,9 +91,8 @@ typedef struct TU_ATTR_PACKED uint8_t counter : 6; // +1 each report }; - // comment out since not used by this example - // uint8_t l2_trigger; // 0 released, 0xff fully pressed - // uint8_t r2_trigger; // as above + uint8_t l2_trigger; // 0 released, 0xff fully pressed + uint8_t r2_trigger; // as above // uint16_t timestamp; // uint8_t battery; @@ -105,15 +104,54 @@ typedef struct TU_ATTR_PACKED } sony_ds4_report_t; +typedef struct TU_ATTR_PACKED { + // First 16 bits set what data is pertinent in this structure (1 = set; 0 = not set) + uint8_t set_rumble : 1; + uint8_t set_led : 1; + uint8_t set_led_blink : 1; + uint8_t set_ext_write : 1; + uint8_t set_left_volume : 1; + uint8_t set_right_volume : 1; + uint8_t set_mic_volume : 1; + uint8_t set_speaker_volume : 1; + uint8_t set_flags2; + + uint8_t reserved; + + uint8_t motor_right; + uint8_t motor_left; + + uint8_t lightbar_red; + uint8_t lightbar_green; + uint8_t lightbar_blue; + uint8_t lightbar_blink_on; + uint8_t lightbar_blink_off; + + uint8_t ext_data[8]; + + uint8_t volume_left; + uint8_t volume_right; + uint8_t volume_mic; + uint8_t volume_speaker; + + uint8_t other[9]; +} sony_ds4_output_report_t; + +static bool ds4_mounted = false; +static uint8_t ds4_dev_addr = 0; +static uint8_t ds4_instance = 0; +static uint8_t motor_left = 0; +static uint8_t motor_right = 0; + // check if device is Sony DualShock 4 static inline bool is_sony_ds4(uint8_t dev_addr) { uint16_t vid, pid; tuh_vid_pid_get(dev_addr, &vid, &pid); - return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) // Sony DualShock4 - || (vid == 0x0f0d && pid == 0x005e) // Hori FC4 - || (vid == 0x0f0d && pid == 0x00ee) // Hori PS4 Mini (PS4-099U) + return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) // Sony DualShock4 + || (vid == 0x0f0d && pid == 0x005e) // Hori FC4 + || (vid == 0x0f0d && pid == 0x00ee) // Hori PS4 Mini (PS4-099U) || (vid == 0x1f4f && pid == 0x1002) // ASW GG xrd controller ); } @@ -124,7 +162,22 @@ static inline bool is_sony_ds4(uint8_t dev_addr) void hid_app_task(void) { - // nothing to do + if (ds4_mounted) + { + const uint32_t interval_ms = 200; + static uint32_t start_ms = 0; + + if ( board_millis() - start_ms >= interval_ms) + { + start_ms += interval_ms; + + sony_ds4_output_report_t output_report = {0}; + output_report.set_rumble = 1; + output_report.motor_left = motor_left; + output_report.motor_right = motor_right; + tuh_hid_send_report(ds4_dev_addr, ds4_instance, 5, &output_report, sizeof(output_report)); + } + } } //--------------------------------------------------------------------+ @@ -149,6 +202,14 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re // Sony DualShock 4 [CUH-ZCT2x] if ( is_sony_ds4(dev_addr) ) { + if (!ds4_mounted) + { + ds4_dev_addr = dev_addr; + ds4_instance = instance; + motor_left = 0; + motor_right = 0; + ds4_mounted = true; + } // request to receive report // tuh_hid_report_received_cb() will be invoked when report is available if ( !tuh_hid_receive_report(dev_addr, instance) ) @@ -162,6 +223,10 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance) { printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance); + if (ds4_mounted && ds4_dev_addr == dev_addr && ds4_instance == instance) + { + ds4_mounted = false; + } } // check if different than 2 @@ -179,8 +244,8 @@ bool diff_report(sony_ds4_report_t const* rpt1, sony_ds4_report_t const* rpt2) result = diff_than_2(rpt1->x, rpt2->x) || diff_than_2(rpt1->y , rpt2->y ) || diff_than_2(rpt1->z, rpt2->z) || diff_than_2(rpt1->rz, rpt2->rz); - // check the reset with mem compare - result |= memcmp(&rpt1->rz + 1, &rpt2->rz + 1, sizeof(sony_ds4_report_t)-4); + // check the rest with mem compare + result |= memcmp(&rpt1->rz + 1, &rpt2->rz + 1, sizeof(sony_ds4_report_t)-6); return result; } @@ -234,6 +299,10 @@ void process_sony_ds4(uint8_t const* report, uint16_t len) printf("\r\n"); } + // The left and right triggers control the intensity of the left and right rumble motors + motor_left = ds4_report.l2_trigger; + motor_right = ds4_report.r2_trigger; + prev_report = ds4_report; } } diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 22569194f..e5fc86267 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -274,7 +274,7 @@ bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance) // return !usbh_edpt_busy(dev_addr, hid_itf->ep_in); //} -bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len) +bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, const void* report, uint16_t len) { TU_LOG2("HID Send Report %d\r\n", report_id); diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h index e5f159ca8..c152e527a 100644 --- a/src/class/hid/hid_host.h +++ b/src/class/hid/hid_host.h @@ -106,7 +106,7 @@ bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance); // Send report using interrupt endpoint // If report_id > 0 (composite), it will be sent as 1st byte, then report contents. Otherwise only report content is sent. -bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len); +bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, const void* report, uint16_t len); //--------------------------------------------------------------------+ // Callbacks (Weak is optional) -- cgit v1.3.1 From d31aac453eaa0b56a998c3cca5d2efd4c55209af Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Mon, 13 Mar 2023 15:22:00 -0700 Subject: Flush the dcd data on reset --- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 32c2fc029..91d5524b6 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -48,6 +48,8 @@ #define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base) +// Clean means to push any cached changes to RAM and invalidate "removes" the +// entry from the cache. #if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1 #define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr #else @@ -199,6 +201,8 @@ static void bus_reset(uint8_t rhport) _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID; _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only + + CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); } void dcd_init(uint8_t rhport) -- cgit v1.3.1 From d9a9dc5ac0a9679403a75dbe3a32c4d4678998e6 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 10 Mar 2023 14:39:57 +0700 Subject: fix PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY not defined in old pico-sdk --- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 37dec1cbf..4af8c2d71 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -385,6 +385,11 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) /* Controller API *------------------------------------------------------------------*/ +// older SDK +#ifndef PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY +#define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff +#endif + void dcd_init (uint8_t rhport) { assert(rhport == 0); -- cgit v1.3.1 From bc2127b3305f5a6e689c1a3264fdee06928cd60e Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 16 Mar 2023 11:03:08 +0700 Subject: rename file link to rusb2 --- .codespell/exclude-file.txt | 4 - .codespell/ignore-words.txt | 1 + hw/bsp/ra/family.mk | 4 +- hw/bsp/rx/family.mk | 4 +- src/portable/renesas/link/dcd_link.c | 868 ---------------- src/portable/renesas/link/hcd_link.c | 813 --------------- src/portable/renesas/link/link_ra.h | 64 -- src/portable/renesas/link/link_rx.h | 76 -- src/portable/renesas/link/link_type.h | 1669 ------------------------------- src/portable/renesas/rusb2/dcd_rusb2.c | 868 ++++++++++++++++ src/portable/renesas/rusb2/hcd_rusb2.c | 813 +++++++++++++++ src/portable/renesas/rusb2/rusb2_ra.h | 62 ++ src/portable/renesas/rusb2/rusb2_rx.h | 74 ++ src/portable/renesas/rusb2/rusb2_type.h | 1669 +++++++++++++++++++++++++++++++ 14 files changed, 3491 insertions(+), 3498 deletions(-) delete mode 100644 src/portable/renesas/link/dcd_link.c delete mode 100644 src/portable/renesas/link/hcd_link.c delete mode 100644 src/portable/renesas/link/link_ra.h delete mode 100644 src/portable/renesas/link/link_rx.h delete mode 100644 src/portable/renesas/link/link_type.h create mode 100644 src/portable/renesas/rusb2/dcd_rusb2.c create mode 100644 src/portable/renesas/rusb2/hcd_rusb2.c create mode 100644 src/portable/renesas/rusb2/rusb2_ra.h create mode 100644 src/portable/renesas/rusb2/rusb2_rx.h create mode 100644 src/portable/renesas/rusb2/rusb2_type.h (limited to 'src') diff --git a/.codespell/exclude-file.txt b/.codespell/exclude-file.txt index 660d2e07e..e69de29bb 100644 --- a/.codespell/exclude-file.txt +++ b/.codespell/exclude-file.txt @@ -1,4 +0,0 @@ - return LINK_REG->INTSTS1_b.ATTCH ? true : false; - volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */ -#define LINK_REG_INTSTS1_ATTCH_Pos (11UL) /* ATTCH (Bit 11) */ -#define LINK_REG_INTSTS1_ATTCH_Msk (0x800UL) /* ATTCH (Bitfield-Mask: 0x01) */ diff --git a/.codespell/ignore-words.txt b/.codespell/ignore-words.txt index e37d97a9f..e1ad88a07 100644 --- a/.codespell/ignore-words.txt +++ b/.codespell/ignore-words.txt @@ -6,3 +6,4 @@ fro dout mot te +attch diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index e75e74104..3c681a7c3 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -20,8 +20,8 @@ CFLAGS += \ -ffreestanding SRC_C += \ - src/portable/renesas/link/dcd_link.c \ - src/portable/renesas/link/hcd_link.c \ + src/portable/renesas/rusb2/dcd_rusb2.c \ + src/portable/renesas/rusb2/hcd_rusb2.c \ hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c \ hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c \ hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_clocks.c \ diff --git a/hw/bsp/rx/family.mk b/hw/bsp/rx/family.mk index ef9db293a..3044167b9 100644 --- a/hw/bsp/rx/family.mk +++ b/hw/bsp/rx/family.mk @@ -17,8 +17,8 @@ CFLAGS += \ CFLAGS += -Wno-error=redundant-decls SRC_C += \ - src/portable/renesas/link/dcd_link.c \ - src/portable/renesas/link/hcd_link.c \ + src/portable/renesas/rusb2/dcd_rusb2.c \ + src/portable/renesas/rusb2/hcd_rusb2.c \ $(MCU_DIR)/vects.c INC += \ diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c deleted file mode 100644 index ce29769e0..000000000 --- a/src/portable/renesas/link/dcd_link.c +++ /dev/null @@ -1,868 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 Koji Kitayama - * Portions copyrighted (c) 2021 Roland Winistoerfer - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) -// We disable SOF for now until needed later on -#define USE_SOF 0 - -#if CFG_TUD_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \ - TU_CHECK_MCU(OPT_MCU_RAXXX)) - -#include "device/dcd.h" -#include "link_type.h" - -#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) -#include "link_rx.h" -#elif TU_CHECK_MCU(OPT_MCU_RAXXX) -#include "link_ra.h" -#else -#error "Unsupported MCU" -#endif - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ - -/* LINK core registers */ -#if defined(__CCRX__) -#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE) -#else -#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE) -#endif - -/* Start of definition of packed structs (used by the CCRX toolchain) */ -TU_ATTR_PACKED_BEGIN -TU_ATTR_BIT_FIELD_ORDER_BEGIN - -typedef struct TU_ATTR_PACKED { - union { - struct { - uint16_t : 8; - uint16_t TRCLR: 1; - uint16_t TRENB: 1; - uint16_t : 0; - }; - uint16_t TRE; - }; - uint16_t TRN; -} reg_pipetre_t; - -typedef union TU_ATTR_PACKED { - struct { - volatile uint16_t u8: 8; - volatile uint16_t : 0; - }; - volatile uint16_t u16; -} hw_fifo_t; - -typedef struct TU_ATTR_PACKED -{ - void *buf; /* the start address of a transfer data buffer */ - uint16_t length; /* the number of bytes in the buffer */ - uint16_t remaining; /* the number of bytes remaining in the buffer */ - struct { - uint32_t ep : 8; /* an assigned endpoint address */ - uint32_t ff : 1; /* `buf` is TU_FUFO or POD */ - uint32_t : 0; - }; -} pipe_state_t; - -TU_ATTR_PACKED_END // End of definition of packed structs (used by the CCRX toolchain) -TU_ATTR_BIT_FIELD_ORDER_END - -typedef struct -{ - pipe_state_t pipe[10]; - uint8_t ep[2][16]; /* a lookup table for a pipe index from an endpoint address */ -} dcd_data_t; - -//--------------------------------------------------------------------+ -// INTERNAL OBJECT & FUNCTION DECLARATION -//--------------------------------------------------------------------+ -static dcd_data_t _dcd; - -static unsigned find_pipe(unsigned xfer) -{ - switch (xfer) { - case TUSB_XFER_ISOCHRONOUS: - for (int i = 1; i <= 2; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_BULK: - for (int i = 3; i <= 5; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - for (int i = 1; i <= 1; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_INTERRUPT: - for (int i = 6; i <= 9; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - break; - default: - /* No support for control transfer */ - break; - } - return 0; -} - -static volatile uint16_t* get_pipectr(unsigned num) -{ - if (num) { - return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]); - } else { - return (volatile uint16_t*)&(LINK_REG->DCPCTR); - } -} - -static volatile reg_pipetre_t* get_pipetre(unsigned num) -{ - volatile reg_pipetre_t* tre = NULL; - if ((1 <= num) && (num <= 5)) { - tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E); - } - return tre; -} - -static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr) -{ - (void)rhport; - const unsigned epn = tu_edpt_number(ep_addr); - if (epn) { - const unsigned dir = tu_edpt_dir(ep_addr); - const unsigned num = _dcd.ep[dir][epn]; - return get_pipectr(num); - } else { - return get_pipectr(0); - } -} - -static unsigned edpt0_max_packet_size(void) -{ - return LINK_REG->DCPMAXP_b.MXPS; -} - -static unsigned edpt_max_packet_size(unsigned num) -{ - LINK_REG->PIPESEL = num; - return LINK_REG->PIPEMAXP; -} - -static inline void pipe_wait_for_ready(unsigned num) -{ - while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ; - while (!LINK_REG->D0FIFOCTR_b.FRDY) ; -} - -static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) -{ - volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo; - uintptr_t addr = (uintptr_t)buf; - while (len >= 2) { - reg->u16 = *(const uint16_t *)addr; - addr += 2; - len -= 2; - } - if (len) { - reg->u8 = *(const uint8_t *)addr; - ++addr; - } -} - -static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) -{ - uint8_t *p = (uint8_t*)buf; - volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ - while (len--) *p++ = *reg; -} - -static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) -{ - static const struct { - void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info); - void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n); - void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len); - } ops[] = { - /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet}, - /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, - }; - tu_fifo_buffer_info_t info; - ops[dir].tu_fifo_get_info(f, &info); - unsigned total_len = len; - len = TU_MIN(total_len, info.len_lin); - ops[dir].pipe_read_write(info.ptr_lin, fifo, len); - unsigned rem = total_len - len; - if (rem) { - len = TU_MIN(rem, info.len_wrap); - ops[dir].pipe_read_write(info.ptr_wrap, fifo, len); - rem -= len; - } - ops[dir].tu_fifo_advance(f, total_len - rem); -} - -static bool pipe0_xfer_in(void) -{ - pipe_state_t *pipe = &_dcd.pipe[0]; - const unsigned rem = pipe->remaining; - if (!rem) { - pipe->buf = NULL; - return true; - } - const unsigned mps = edpt0_max_packet_size(); - const unsigned len = TU_MIN(mps, rem); - void *buf = pipe->buf; - if (len) { - if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->CFIFO, len, TUSB_DIR_IN); - } else { - pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); - pipe->buf = (uint8_t*)buf + len; - } - } - if (len < mps) { - LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; - } - pipe->remaining = rem - len; - return false; -} - -static bool pipe0_xfer_out(void) -{ - pipe_state_t *pipe = &_dcd.pipe[0]; - const unsigned rem = pipe->remaining; - - const unsigned mps = edpt0_max_packet_size(); - const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN; - const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); - void *buf = pipe->buf; - if (len) { - if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->CFIFO, len, TUSB_DIR_OUT); - } else { - pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); - pipe->buf = (uint8_t*)buf + len; - } - } - if (len < mps) { - LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; - } - pipe->remaining = rem - len; - if ((len < mps) || (rem == len)) { - pipe->buf = NULL; - return true; - } - return false; -} - -static bool pipe_xfer_in(unsigned num) -{ - pipe_state_t *pipe = &_dcd.pipe[num]; - const unsigned rem = pipe->remaining; - - if (!rem) { - pipe->buf = NULL; - return true; - } - - LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); - const unsigned len = TU_MIN(rem, mps); - void *buf = pipe->buf; - if (len) { - if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->D0FIFO, len, TUSB_DIR_IN); - } else { - pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); - pipe->buf = (uint8_t*)buf + len; - } - } - if (len < mps) { - LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; - } - LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ - pipe->remaining = rem - len; - return false; -} - -static bool pipe_xfer_out(unsigned num) -{ - pipe_state_t *pipe = &_dcd.pipe[num]; - const unsigned rem = pipe->remaining; - - LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT; - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); - const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN; - const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); - void *buf = pipe->buf; - if (len) { - if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->D0FIFO, len, TUSB_DIR_OUT); - } else { - pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); - pipe->buf = (uint8_t*)buf + len; - } - } - if (len < mps) { - LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; - } - LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ - pipe->remaining = rem - len; - if ((len < mps) || (rem == len)) { - pipe->buf = NULL; - return NULL != buf; - } - return false; -} - -static void process_setup_packet(uint8_t rhport) -{ - uint16_t setup_packet[4]; - if (0 == (LINK_REG->INTSTS0 & LINK_REG_INTSTS0_VALID_Msk)) return; - LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; - setup_packet[0] = tu_le16toh(LINK_REG->USBREQ); - setup_packet[1] = LINK_REG->USBVAL; - setup_packet[2] = LINK_REG->USBINDX; - setup_packet[3] = LINK_REG->USBLENG; - LINK_REG->INTSTS0 = ~((uint16_t)LINK_REG_INTSTS0_VALID_Msk); - dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true); -} - -static void process_status_completion(uint8_t rhport) -{ - uint8_t ep_addr; - /* Check the data stage direction */ - if (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) { - /* IN transfer. */ - ep_addr = tu_edpt_addr(0, TUSB_DIR_IN); - } else { - /* OUT transfer. */ - ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT); - } - dcd_event_xfer_complete(rhport, ep_addr, 0, XFER_RESULT_SUCCESS, true); -} - -static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) -{ - /* configure fifo direction and access unit settings */ - if (ep_addr) { /* IN, 2 bytes */ - LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT | - (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); - while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ; - } else { /* OUT, a byte */ - LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT; - while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ; - } - - pipe_state_t *pipe = &_dcd.pipe[0]; - pipe->ff = buffer_type; - pipe->length = total_bytes; - pipe->remaining = total_bytes; - if (total_bytes) { - pipe->buf = buffer; - if (ep_addr) { /* IN */ - TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80)); - pipe0_xfer_in(); - } - LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF; - } else { - /* ZLP */ - pipe->buf = NULL; - LINK_REG->DCPCTR = LINK_REG_DCPCTR_CCPL_Msk | LINK_REG_PIPE_CTR_PID_BUF; - } - return true; -} - -static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) -{ - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir = tu_edpt_dir(ep_addr); - const unsigned num = _dcd.ep[dir][epn]; - - TU_ASSERT(num); - - pipe_state_t *pipe = &_dcd.pipe[num]; - pipe->ff = buffer_type; - pipe->buf = buffer; - pipe->length = total_bytes; - pipe->remaining = total_bytes; - if (dir) { /* IN */ - if (total_bytes) { - pipe_xfer_in(num); - } else { /* ZLP */ - LINK_REG->D0FIFOSEL = num; - pipe_wait_for_ready(num); - LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; - LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - } - } else { -#if defined(__CCRX__) - __evenaccess volatile reg_pipetre_t *pt = get_pipetre(num); -#else - volatile reg_pipetre_t *pt = get_pipetre(num); -#endif - if (pt) { - const unsigned mps = edpt_max_packet_size(num); - volatile uint16_t *ctr = get_pipectr(num); - if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK; - pt->TRE = TU_BIT(8); - pt->TRN = (total_bytes + mps - 1) / mps; - pt->TRENB = 1; - *ctr = LINK_REG_PIPE_CTR_PID_BUF; - } - } - // TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type); - return true; -} - -static bool process_edpt_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) -{ - const unsigned epn = tu_edpt_number(ep_addr); - if (0 == epn) { - return process_pipe0_xfer(buffer_type, ep_addr, buffer, total_bytes); - } else { - return process_pipe_xfer(buffer_type, ep_addr, buffer, total_bytes); - } -} - -static void process_pipe0_bemp(uint8_t rhport) -{ - bool completed = pipe0_xfer_in(); - if (completed) { - pipe_state_t *pipe = &_dcd.pipe[0]; - dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN), - pipe->length, XFER_RESULT_SUCCESS, true); - } -} - -static void process_pipe_brdy(uint8_t rhport, unsigned num) -{ - pipe_state_t *pipe = &_dcd.pipe[num]; - const unsigned dir = tu_edpt_dir(pipe->ep); - bool completed; - - if (dir) { /* IN */ - completed = pipe_xfer_in(num); - } else { - if (num) { - completed = pipe_xfer_out(num); - } else { - completed = pipe0_xfer_out(); - } - } - if (completed) { - dcd_event_xfer_complete(rhport, pipe->ep, - pipe->length - pipe->remaining, - XFER_RESULT_SUCCESS, true); - // TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining); - } -} - -static void process_bus_reset(uint8_t rhport) -{ - LINK_REG->BEMPENB = 1; - LINK_REG->BRDYENB = 1; - LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; - LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - LINK_REG->D1FIFOSEL = 0; - while (LINK_REG->D1FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&LINK_REG->PIPE_CTR[0])); - volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&LINK_REG->PIPE_TR[0].E)); - for (int i = 1; i <= 5; ++i) { - LINK_REG->PIPESEL = i; - LINK_REG->PIPECFG = 0; - *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk; - *ctr = 0; - ++ctr; - *tre = TU_BIT(8); - tre += 2; - } - for (int i = 6; i <= 9; ++i) { - LINK_REG->PIPESEL = i; - LINK_REG->PIPECFG = 0; - *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk; - *ctr = 0; - ++ctr; - } - tu_varclr(&_dcd); - dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); -} - -static void process_set_address(uint8_t rhport) -{ - const uint32_t addr = LINK_REG->USBADDR_b.USBADDR; - if (!addr) return; - const tusb_control_request_t setup_packet = { -#if defined(__CCRX__) - .bmRequestType = { 0 }, /* Note: CCRX needs the braces over this struct member */ -#else - .bmRequestType = 0, -#endif - .bRequest = TUSB_REQ_SET_ADDRESS, - .wValue = addr, - .wIndex = 0, - .wLength = 0, - }; - dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet, true); -} - -/*------------------------------------------------------------------*/ -/* Device API - *------------------------------------------------------------------*/ - -#if 0 // previously present in the rx driver before generalization -static uint32_t disable_interrupt(void) -{ - uint32_t pswi; -#if defined(__CCRX__) - pswi = get_psw() & 0x010000; - clrpsw_i(); -#else - pswi = __builtin_rx_mvfc(0) & 0x010000; - __builtin_rx_clrpsw('I'); -#endif - return pswi; -} - -static void enable_interrupt(uint32_t pswi) -{ -#if defined(__CCRX__) - set_psw(get_psw() | pswi); -#else - __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi); -#endif -} -#endif - -void dcd_init(uint8_t rhport) -{ - (void)rhport; - -#if 0 // previously present in the rx driver before generalization - uint32_t pswi = disable_interrupt(); - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; - MSTP(USB0) = 0; - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; - enable_interrupt(pswi); -#endif - - LINK_REG->SYSCFG_b.SCKE = 1; - while (!LINK_REG->SYSCFG_b.SCKE) ; - LINK_REG->SYSCFG_b.DRPD = 0; - LINK_REG->SYSCFG_b.DCFM = 0; - LINK_REG->SYSCFG_b.USBE = 1; - - // MCU specific PHY init - link_phy_init(); - - LINK_REG->PHYSLEW = 0x5; - LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */ - - /* Setup default control pipe */ - LINK_REG->DCPMAXP_b.MXPS = 64; - LINK_REG->INTENB0 = LINK_REG_INTSTS0_VBINT_Msk | LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk | - LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_CTRT_Msk | (USE_SOF ? LINK_REG_INTSTS0_SOFR_Msk : 0) | - LINK_REG_INTSTS0_RESM_Msk; - LINK_REG->BEMPENB = 1; - LINK_REG->BRDYENB = 1; - - if (LINK_REG->INTSTS0_b.VBSTS) { - dcd_connect(rhport); - } -} - -void dcd_int_enable(uint8_t rhport) -{ - link_int_enable(rhport); -} - -void dcd_int_disable(uint8_t rhport) -{ - link_int_disable(rhport); -} - -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) -{ - (void)rhport; - (void)dev_addr; -} - -void dcd_remote_wakeup(uint8_t rhport) -{ - (void)rhport; - LINK_REG->DVSTCTR0_b.WKUP = 1; -} - -void dcd_connect(uint8_t rhport) -{ - (void)rhport; - LINK_REG->SYSCFG_b.DPRPU = 1; -} - -void dcd_disconnect(uint8_t rhport) -{ - (void)rhport; - LINK_REG->SYSCFG_b.DPRPU = 0; -} - -void dcd_sof_enable(uint8_t rhport, bool en) -{ - (void) rhport; - (void) en; - - // TODO implement later -} - -//--------------------------------------------------------------------+ -// Endpoint API -//--------------------------------------------------------------------+ -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) -{ - (void)rhport; - - const unsigned ep_addr = ep_desc->bEndpointAddress; - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir = tu_edpt_dir(ep_addr); - const unsigned xfer = ep_desc->bmAttributes.xfer; - - const unsigned mps = tu_edpt_packet_size(ep_desc); - if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) { - /* USBa supports up to 256 bytes */ - return false; - } - - const unsigned num = find_pipe(xfer); - if (!num) return false; - _dcd.pipe[num].ep = ep_addr; - _dcd.ep[dir][epn] = num; - - /* setup pipe */ - dcd_int_disable(rhport); - LINK_REG->PIPESEL = num; - LINK_REG->PIPEMAXP = mps; - volatile uint16_t *ctr = get_pipectr(num); - *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk; - *ctr = 0; - unsigned cfg = (dir << 4) | epn; - if (xfer == TUSB_XFER_BULK) { - cfg |= (LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk); - } else if (xfer == TUSB_XFER_INTERRUPT) { - cfg |= LINK_REG_PIPECFG_TYPE_INT; - } else { - cfg |= (LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk); - } - LINK_REG->PIPECFG = cfg; - LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num); - LINK_REG->BRDYENB |= TU_BIT(num); - if (dir || (xfer != TUSB_XFER_BULK)) { - *ctr = LINK_REG_PIPE_CTR_PID_BUF; - } - // TU_LOG1("O %d %x %x\r\n", LINK_REG->PIPESEL, LINK_REG->PIPECFG, LINK_REG->PIPEMAXP); - dcd_int_enable(rhport); - - return true; -} - -void dcd_edpt_close_all(uint8_t rhport) -{ - unsigned i = TU_ARRAY_SIZE(_dcd.pipe); - dcd_int_disable(rhport); - while (--i) { /* Close all pipes except 0 */ - const unsigned ep_addr = _dcd.pipe[i].ep; - if (!ep_addr) continue; - dcd_edpt_close(rhport, ep_addr); - } - dcd_int_enable(rhport); -} - -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir = tu_edpt_dir(ep_addr); - const unsigned num = _dcd.ep[dir][epn]; - - LINK_REG->BRDYENB &= ~TU_BIT(num); - volatile uint16_t *ctr = get_pipectr(num); - *ctr = 0; - LINK_REG->PIPESEL = num; - LINK_REG->PIPECFG = 0; - _dcd.pipe[num].ep = 0; - _dcd.ep[dir][epn] = 0; -} - -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) -{ - bool r; - dcd_int_disable(rhport); - r = process_edpt_xfer(0, ep_addr, buffer, total_bytes); - dcd_int_enable(rhport); - return r; -} - -bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) -{ - // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1 - TU_ASSERT(ff->item_size == 1); - bool r; - dcd_int_disable(rhport); - r = process_edpt_xfer(1, ep_addr, ff, total_bytes); - dcd_int_enable(rhport); - return r; -} - -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) -{ - volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr); - if (!ctr) return; - dcd_int_disable(rhport); - const uint32_t pid = *ctr & 0x3; - *ctr = pid | LINK_REG_PIPE_CTR_PID_STALL; - *ctr = LINK_REG_PIPE_CTR_PID_STALL; - dcd_int_enable(rhport); -} - -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) -{ - volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr); - if (!ctr) return; - dcd_int_disable(rhport); - *ctr = LINK_REG_PIPE_CTR_SQCLR_Msk; - - if (tu_edpt_dir(ep_addr)) { /* IN */ - *ctr = LINK_REG_PIPE_CTR_PID_BUF; - } else { - const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)]; - LINK_REG->PIPESEL = num; - if (LINK_REG->PIPECFG_b.TYPE != 1) { - *ctr = LINK_REG_PIPE_CTR_PID_BUF; - } - } - dcd_int_enable(rhport); -} - -//--------------------------------------------------------------------+ -// ISR -//--------------------------------------------------------------------+ -void dcd_int_handler(uint8_t rhport) -{ - (void)rhport; - - unsigned is0 = LINK_REG->INTSTS0; - /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ - LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_CTRT_Msk | LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_SOFR_Msk | - LINK_REG_INTSTS0_RESM_Msk | LINK_REG_INTSTS0_VBINT_Msk) & is0) | LINK_REG_INTSTS0_VALID_Msk; - if (is0 & LINK_REG_INTSTS0_VBINT_Msk) { - if (LINK_REG->INTSTS0_b.VBSTS) { - dcd_connect(rhport); - } else { - dcd_disconnect(rhport); - } - } - if (is0 & LINK_REG_INTSTS0_RESM_Msk) { - dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); -#if (0==USE_SOF) - LINK_REG->INTENB0_b.SOFE = 0; -#endif - } - if ((is0 & LINK_REG_INTSTS0_SOFR_Msk) && LINK_REG->INTENB0_b.SOFE) { - // USBD will exit suspended mode when SOF event is received - dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); -#if (0 == USE_SOF) - LINK_REG->INTENB0_b.SOFE = 0; -#endif - } - if (is0 & LINK_REG_INTSTS0_DVST_Msk) { - switch (is0 & LINK_REG_INTSTS0_DVSQ_Msk) { - case LINK_REG_INTSTS0_DVSQ_STATE_DEF: - process_bus_reset(rhport); - break; - case LINK_REG_INTSTS0_DVSQ_STATE_ADDR: - process_set_address(rhport); - break; - case LINK_REG_INTSTS0_DVSQ_STATE_SUSP0: - case LINK_REG_INTSTS0_DVSQ_STATE_SUSP1: - case LINK_REG_INTSTS0_DVSQ_STATE_SUSP2: - case LINK_REG_INTSTS0_DVSQ_STATE_SUSP3: - dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); -#if (0==USE_SOF) - LINK_REG->INTENB0_b.SOFE = 1; -#endif - default: - break; - } - } - if (is0 & LINK_REG_INTSTS0_CTRT_Msk) { - if (is0 & LINK_REG_INTSTS0_CTSQ_CTRL_RDATA) { - /* A setup packet has been received. */ - process_setup_packet(rhport); - } else if (0 == (is0 & LINK_REG_INTSTS0_CTSQ_Msk)) { - /* A ZLP has been sent/received. */ - process_status_completion(rhport); - } - } - if (is0 & LINK_REG_INTSTS0_BEMP_Msk) { - const unsigned s = LINK_REG->BEMPSTS; - LINK_REG->BEMPSTS = 0; - if (s & 1) { - process_pipe0_bemp(rhport); - } - } - if (is0 & LINK_REG_INTSTS0_BRDY_Msk) { - const unsigned m = LINK_REG->BRDYENB; - unsigned s = LINK_REG->BRDYSTS & m; - /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ - LINK_REG->BRDYSTS = ~s; - while (s) { -#if defined(__CCRX__) - static const int Mod37BitPosition[] = { - -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4, - 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5, - 20, 8, 19, 18 - }; - - const unsigned num = Mod37BitPosition[(-s & s) % 37]; -#else - const unsigned num = __builtin_ctz(s); -#endif - process_pipe_brdy(rhport, num); - s &= ~TU_BIT(num); - } - } -} - -#endif diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c deleted file mode 100644 index b16544c2f..000000000 --- a/src/portable/renesas/link/hcd_link.c +++ /dev/null @@ -1,813 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2021 Koji Kitayama - * Portions copyrighted (c) 2021 Roland Winistoerfer - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -#if CFG_TUH_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \ - TU_CHECK_MCU(OPT_MCU_RAXXX)) - -#include "host/hcd.h" -#include "link_type.h" - -#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) -#include "link_rx.h" -#elif TU_CHECK_MCU(OPT_MCU_RAXXX) -#include "link_ra.h" -#else -#error "Unsupported MCU" -#endif - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM DECLARATION -//--------------------------------------------------------------------+ - -/* LINK core registers */ -#if defined(__CCRX__) -#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE) -#else -#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE) -#endif - -TU_ATTR_PACKED_BEGIN -TU_ATTR_BIT_FIELD_ORDER_BEGIN - -typedef struct TU_ATTR_PACKED { - union { - struct { - uint16_t : 8; - uint16_t TRCLR: 1; - uint16_t TRENB: 1; - uint16_t : 0; - }; - uint16_t TRE; - }; - uint16_t TRN; -} reg_pipetre_t; - -typedef union TU_ATTR_PACKED { - struct { - volatile uint16_t u8: 8; - volatile uint16_t : 0; - }; - volatile uint16_t u16; -} hw_fifo_t; - -typedef struct TU_ATTR_PACKED { - void *buf; /* the start address of a transfer data buffer */ - uint16_t length; /* the number of bytes in the buffer */ - uint16_t remaining; /* the number of bytes remaining in the buffer */ - struct { - uint32_t ep : 8; /* an assigned endpoint address */ - uint32_t dev : 8; /* an assigned device address */ - uint32_t ff : 1; /* `buf` is TU_FUFO or POD */ - uint32_t : 0; - }; -} pipe_state_t; - -TU_ATTR_PACKED_END // End of definition of packed structs (used by the CCRX toolchain) -TU_ATTR_BIT_FIELD_ORDER_END - -typedef struct -{ - bool need_reset; /* The device has not been reset after connection. */ - pipe_state_t pipe[10]; - uint8_t ep[4][2][15]; /* a lookup table for a pipe index from an endpoint address */ - uint8_t ctl_mps[5]; /* EP0 max packet size for each device */ -} hcd_data_t; - -//--------------------------------------------------------------------+ -// INTERNAL OBJECT & FUNCTION DECLARATION -//--------------------------------------------------------------------+ -static hcd_data_t _hcd; - -static unsigned find_pipe(unsigned xfer) -{ - switch (xfer) { - case TUSB_XFER_ISOCHRONOUS: - for (int i = 1; i <= 2; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_BULK: - for (int i = 3; i <= 5; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - for (int i = 1; i <= 1; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_INTERRUPT: - for (int i = 6; i <= 9; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - break; - default: - /* No support for control transfer */ - break; - } - return 0; -} - -static volatile uint16_t* get_pipectr(unsigned num) -{ - if (num) { - return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]); - } else { - return (volatile uint16_t*)&(LINK_REG->DCPCTR); - } -} - -static volatile reg_pipetre_t* get_pipetre(unsigned num) -{ - volatile reg_pipetre_t* tre = NULL; - if ((1 <= num) && (num <= 5)) { - tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E); - } - return tre; -} - -static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr) -{ - const unsigned epn = tu_edpt_number(ep_addr); - if (epn) { - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1]; - return get_pipectr(num); - } else { - return get_pipectr(0); - } -} - -static unsigned edpt0_max_packet_size(void) -{ - return LINK_REG->DCPMAXP_b.MXPS; -} - -static unsigned edpt_max_packet_size(unsigned num) -{ - LINK_REG->PIPESEL = num; - return LINK_REG->PIPEMAXP_b.MXPS; -} - -static inline void pipe_wait_for_ready(unsigned num) -{ - while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ; - while (!LINK_REG->D0FIFOCTR_b.FRDY) ; -} - -static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) -{ - volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; - uintptr_t addr = (uintptr_t)buf; - while (len >= 2) { - reg->u16 = *(const uint16_t *)addr; - addr += 2; - len -= 2; - } - if (len) { - reg->u8 = *(const uint8_t *)addr; - ++addr; - } -} - -static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) -{ - uint8_t *p = (uint8_t*)buf; - volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ - while (len--) *p++ = *reg; -} - -static bool pipe0_xfer_in(void) -{ - pipe_state_t *pipe = &_hcd.pipe[0]; - const unsigned rem = pipe->remaining; - - const unsigned mps = edpt0_max_packet_size(); - const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN; - const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); - void *buf = pipe->buf; - if (len) { - LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; - pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); - pipe->buf = (uint8_t*)buf + len; - } - if (len < mps) { - LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; - } - pipe->remaining = rem - len; - if ((len < mps) || (rem == len)) { - pipe->buf = NULL; - return true; - } - LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF; - return false; -} - -static bool pipe0_xfer_out(void) -{ - pipe_state_t *pipe = &_hcd.pipe[0]; - const unsigned rem = pipe->remaining; - if (!rem) { - pipe->buf = NULL; - return true; - } - const unsigned mps = edpt0_max_packet_size(); - const unsigned len = TU_MIN(mps, rem); - void *buf = pipe->buf; - if (len) { - pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); - pipe->buf = (uint8_t*)buf + len; - } - if (len < mps) { - LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; - } - pipe->remaining = rem - len; - return false; -} - -static bool pipe_xfer_in(unsigned num) -{ - pipe_state_t *pipe = &_hcd.pipe[num]; - const unsigned rem = pipe->remaining; - - LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT; - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); - const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN; - const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); - void *buf = pipe->buf; - if (len) { - pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); - pipe->buf = (uint8_t*)buf + len; - } - if (len < mps) { - LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; - } - LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - pipe->remaining = rem - len; - if ((len < mps) || (rem == len)) { - pipe->buf = NULL; - return NULL != buf; - } - return false; -} - -static bool pipe_xfer_out(unsigned num) -{ - pipe_state_t *pipe = &_hcd.pipe[num]; - const unsigned rem = pipe->remaining; - - if (!rem) { - pipe->buf = NULL; - return true; - } - - LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); - const unsigned len = TU_MIN(rem, mps); - void *buf = pipe->buf; - if (len) { - pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); - pipe->buf = (uint8_t*)buf + len; - } - if (len < mps) - LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; - LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - pipe->remaining = rem - len; - return false; -} - -static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) -{ - (void)dev_addr; - const unsigned dir_in = tu_edpt_dir(ep_addr); - - /* configure fifo direction and access unit settings */ - if (dir_in) { /* IN, a byte */ - LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT; - while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ; - } else { /* OUT, 2 bytes */ - LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT | - (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); - while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ; - } - - pipe_state_t *pipe = &_hcd.pipe[0]; - pipe->ep = ep_addr; - pipe->length = buflen; - pipe->remaining = buflen; - if (buflen) { - pipe->buf = buffer; - if (!dir_in) { /* OUT */ - TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80)); - pipe0_xfer_out(); - } - } else { /* ZLP */ - pipe->buf = NULL; - if (!dir_in) { /* OUT */ - LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; - } - if (dir_in == LINK_REG->DCPCFG_b.DIR) { - TU_ASSERT(LINK_REG_PIPE_CTR_PID_NAK == LINK_REG->DCPCTR_b.PID); - LINK_REG->DCPCTR_b.SQSET = 1; - LINK_REG->DCPCFG_b.DIR = dir_in ^ 1; - } - } - LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF; - return true; -} - -static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen) -{ - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned num = _hcd.ep[dev_addr - 1][dir_in][epn - 1]; - - TU_ASSERT(num); - - pipe_state_t *pipe = &_hcd.pipe[num]; - pipe->buf = buffer; - pipe->length = buflen; - pipe->remaining = buflen; - if (!dir_in) { /* OUT */ - if (buflen) { - pipe_xfer_out(num); - } else { /* ZLP */ - LINK_REG->D0FIFOSEL = num; - pipe_wait_for_ready(num); - LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; - LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ - } - } else { - volatile uint16_t *ctr = get_pipectr(num); - volatile reg_pipetre_t *pt = get_pipetre(num); - if (pt) { - const unsigned mps = edpt_max_packet_size(num); - if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK; - pt->TRE = TU_BIT(8); - pt->TRN = (buflen + mps - 1) / mps; - pt->TRENB = 1; - } - *ctr = LINK_REG_PIPE_CTR_PID_BUF; - } - return true; -} - -static bool process_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) -{ - const unsigned epn = tu_edpt_number(ep_addr); - if (0 == epn) { - return process_pipe0_xfer(dev_addr, ep_addr, buffer, buflen); - } else { - return process_pipe_xfer(dev_addr, ep_addr, buffer, buflen); - } -} - -static void process_pipe0_bemp(uint8_t rhport) -{ - (void)rhport; - bool completed = pipe0_xfer_out(); - if (completed) { - pipe_state_t *pipe = &_hcd.pipe[0]; - hcd_event_xfer_complete(pipe->dev, - tu_edpt_addr(0, TUSB_DIR_OUT), - pipe->length - pipe->remaining, - XFER_RESULT_SUCCESS, true); - } -} - -static void process_pipe_nrdy(uint8_t rhport, unsigned num) -{ - (void)rhport; - unsigned result; - uint16_t volatile *ctr = get_pipectr(num); - // TU_LOG1("NRDY %d %x\n", num, *ctr); - switch (*ctr & LINK_REG_PIPE_CTR_PID_Msk) { - default: return; - case LINK_REG_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break; - case LINK_REG_PIPE_CTR_PID_NAK: result = XFER_RESULT_FAILED; break; - } - pipe_state_t *pipe = &_hcd.pipe[num]; - hcd_event_xfer_complete(pipe->dev, pipe->ep, - pipe->length - pipe->remaining, - result, true); -} - -static void process_pipe_brdy(uint8_t rhport, unsigned num) -{ - (void)rhport; - pipe_state_t *pipe = &_hcd.pipe[num]; - const unsigned dir_in = tu_edpt_dir(pipe->ep); - bool completed; - - if (dir_in) { /* IN */ - if (num) { - completed = pipe_xfer_in(num); - } else { - completed = pipe0_xfer_in(); - } - } else { - completed = pipe_xfer_out(num); - } - if (completed) { - hcd_event_xfer_complete(pipe->dev, pipe->ep, - pipe->length - pipe->remaining, - XFER_RESULT_SUCCESS, true); - // TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining); - } -} - -/*------------------------------------------------------------------*/ -/* Host API - *------------------------------------------------------------------*/ - -#if 0 // previously present in the rx driver before generalization -static uint32_t disable_interrupt(void) -{ - uint32_t pswi; -#if defined(__CCRX__) - pswi = get_psw() & 0x010000; - clrpsw_i(); -#else - pswi = __builtin_rx_mvfc(0) & 0x010000; - __builtin_rx_clrpsw('I'); -#endif - return pswi; -} - -static void enable_interrupt(uint32_t pswi) -{ -#if defined(__CCRX__) - set_psw(get_psw() | pswi); -#else - __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi); -#endif -} -#endif - -bool hcd_init(uint8_t rhport) -{ - (void)rhport; - -#if 0 // previously present in the rx driver before generalization - uint32_t pswi = disable_interrupt(); - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; - MSTP(USB0) = 0; - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; - enable_interrupt(pswi); -#endif - - LINK_REG->SYSCFG_b.SCKE = 1; - while (!LINK_REG->SYSCFG_b.SCKE) ; - LINK_REG->SYSCFG_b.DPRPU = 0; - LINK_REG->SYSCFG_b.DRPD = 0; - LINK_REG->SYSCFG_b.DCFM = 1; - - LINK_REG->DVSTCTR0_b.VBUSEN = 1; - - LINK_REG->SYSCFG_b.DRPD = 1; - for (volatile int i = 0; i < 30000; ++i) ; - LINK_REG->SYSCFG_b.USBE = 1; - - // MCU specific PHY init - link_phy_init(); - - LINK_REG->PHYSLEW = 0x5; - LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */ - - /* Setup default control pipe */ - LINK_REG->DCPCFG = LINK_REG_PIPECFG_SHTNAK_Msk; - LINK_REG->DCPMAXP = 64; - LINK_REG->INTENB0 = LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk; - LINK_REG->INTENB1 = LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk; - LINK_REG->BEMPENB = 1; - LINK_REG->NRDYENB = 1; - LINK_REG->BRDYENB = 1; - - return true; -} - -void hcd_int_enable(uint8_t rhport) -{ - link_int_enable(rhport); -} - -void hcd_int_disable(uint8_t rhport) -{ - link_int_disable(rhport); -} - -uint32_t hcd_frame_number(uint8_t rhport) -{ - (void)rhport; - /* The device must be reset at least once after connection - * in order to start the frame counter. */ - if (_hcd.need_reset) hcd_port_reset(rhport); - return LINK_REG->FRMNUM_b.FRNM; -} - -/*--------------------------------------------------------------------+ - * Port API - *--------------------------------------------------------------------+*/ -bool hcd_port_connect_status(uint8_t rhport) -{ - (void)rhport; - return LINK_REG->INTSTS1_b.ATTCH ? true : false; -} - -void hcd_port_reset(uint8_t rhport) -{ - LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; - while (LINK_REG->DCPCTR_b.PBUSY) ; - hcd_int_disable(rhport); - LINK_REG->DVSTCTR0_b.UACT = 0; - if (LINK_REG->DCPCTR_b.SUREQ) { - LINK_REG->DCPCTR_b.SUREQCLR = 1; - } - hcd_int_enable(rhport); - /* Reset should be asserted 10-20ms. */ - LINK_REG->DVSTCTR0_b.USBRST = 1; - for (volatile int i = 0; i < 2400000; ++i) ; - LINK_REG->DVSTCTR0_b.USBRST = 0; - LINK_REG->DVSTCTR0_b.UACT = 1; - _hcd.need_reset = false; -} - -void hcd_port_reset_end(uint8_t rhport) -{ - (void) rhport; -} - -tusb_speed_t hcd_port_speed_get(uint8_t rhport) -{ - (void)rhport; - switch (LINK_REG->DVSTCTR0_b.RHST) { - default: return TUSB_SPEED_INVALID; - case LINK_REG_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL; - case LINK_REG_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW; - } -} - -void hcd_device_close(uint8_t rhport, uint8_t dev_addr) -{ - (void)rhport; - uint16_t volatile *ctr; - TU_ASSERT(dev_addr < 6,); /* USBa can only handle addresses from 0 to 5. */ - if (!dev_addr) return; - _hcd.ctl_mps[dev_addr] = 0; - uint8_t *ep = &_hcd.ep[dev_addr - 1][0][0]; - for (int i = 0; i < 2 * 15; ++i, ++ep) { - unsigned num = *ep; - if (!num || dev_addr != _hcd.pipe[num].dev) continue; - - ctr = (uint16_t volatile*)&LINK_REG->PIPE_CTR[num - 1]; - *ctr = 0; - LINK_REG->NRDYENB &= ~TU_BIT(num); - LINK_REG->BRDYENB &= ~TU_BIT(num); - LINK_REG->PIPESEL = num; - LINK_REG->PIPECFG = 0; - LINK_REG->PIPEMAXP = 0; - - _hcd.pipe[num].ep = 0; - _hcd.pipe[num].dev = 0; - *ep = 0; - } -} - -/*--------------------------------------------------------------------+ - * Endpoints API - *--------------------------------------------------------------------+*/ -bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) -{ - (void)rhport; - // TU_LOG1("S %d %x\n", dev_addr, LINK_REG->DCPCTR); - - TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ - TU_ASSERT(0 == LINK_REG->DCPCTR_b.SUREQ); - - LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; - - _hcd.pipe[0].buf = NULL; - _hcd.pipe[0].length = 8; - _hcd.pipe[0].remaining = 0; - _hcd.pipe[0].dev = dev_addr; - - while (LINK_REG->DCPCTR_b.PBUSY) ; - LINK_REG->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr]; - - /* Set direction in advance for DATA stage */ - uint8_t const bmRequesttype = setup_packet[0]; - LINK_REG->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1; - - uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0]; - LINK_REG->USBREQ = tu_htole16(p[0]); - LINK_REG->USBVAL = p[1]; - LINK_REG->USBINDX = p[2]; - LINK_REG->USBLENG = p[3]; - - LINK_REG->DCPCTR_b.SUREQ = 1; - return true; -} - -bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *ep_desc) -{ - (void)rhport; - TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ - - const unsigned ep_addr = ep_desc->bEndpointAddress; - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned mps = tu_edpt_packet_size(ep_desc); - if (0 == epn) { - LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; - hcd_devtree_info_t devtree; - hcd_devtree_get_info(dev_addr, &devtree); - uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &LINK_REG->DEVADD[0]; - devadd += dev_addr; - while (LINK_REG->DCPCTR_b.PBUSY) ; - LINK_REG->DCPMAXP = (dev_addr << 12) | mps; - *devadd = (TUSB_SPEED_FULL == devtree.speed) ? LINK_REG_DEVADD_USBSPD_FS : LINK_REG_DEVADD_USBSPD_LS; - _hcd.ctl_mps[dev_addr] = mps; - return true; - } - - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned xfer = ep_desc->bmAttributes.xfer; - if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) { - /* USBa supports up to 256 bytes */ - return false; - } - const unsigned num = find_pipe(xfer); - if (!num) return false; - _hcd.pipe[num].dev = dev_addr; - _hcd.pipe[num].ep = ep_addr; - _hcd.ep[dev_addr - 1][dir_in][epn - 1] = num; - - /* setup pipe */ - hcd_int_disable(rhport); - LINK_REG->PIPESEL = num; - LINK_REG->PIPEMAXP = (dev_addr << 12) | mps; - volatile uint16_t *ctr = get_pipectr(num); - *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk; - *ctr = 0; - unsigned cfg = ((1 ^ dir_in) << 4) | epn; - if (xfer == TUSB_XFER_BULK) { - cfg |= LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk; - } else if (xfer == TUSB_XFER_INTERRUPT) { - cfg |= LINK_REG_PIPECFG_TYPE_INT; - } else { - cfg |= LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk; - } - LINK_REG->PIPECFG = cfg; - LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num); - LINK_REG->NRDYENB |= TU_BIT(num); - LINK_REG->BRDYENB |= TU_BIT(num); - if (!dir_in) { - *ctr = LINK_REG_PIPE_CTR_PID_BUF; - } - hcd_int_enable(rhport); - - return true; -} - -bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) -{ - bool r; - hcd_int_disable(rhport); - // TU_LOG1("X %d %x %u\n", dev_addr, ep_addr, buflen); - r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen); - hcd_int_enable(rhport); - return r; -} - -bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) -{ - uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr); - TU_ASSERT(ctr); - - const uint32_t pid = *ctr & 0x3; - if (pid & 2) { - *ctr = pid & 2; - *ctr = 0; - } - *ctr = LINK_REG_PIPE_CTR_SQCLR_Msk; - unsigned const epn = tu_edpt_number(ep_addr); - if (!epn) return true; - - if (!tu_edpt_dir(ep_addr)) { /* OUT */ - *ctr = LINK_REG_PIPE_CTR_PID_BUF; - } - return true; -} - -//--------------------------------------------------------------------+ -// ISR -//--------------------------------------------------------------------+ -void hcd_int_handler(uint8_t rhport) -{ - (void)rhport; -#if defined(__CCRX__) - static const int Mod37BitPosition[] = { - -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4, - 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5, - 20, 8, 19, 18}; -#endif - - unsigned is1 = LINK_REG->INTSTS1; - unsigned is0 = LINK_REG->INTSTS0; - /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ - LINK_REG->INTSTS1 = ~((LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk) & is1); - LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk) & is0); - // TU_LOG1("IS %04x %04x\n", is0, is1); - is1 &= LINK_REG->INTENB1; - is0 &= LINK_REG->INTENB0; - - if (is1 & LINK_REG_INTSTS1_SACK_Msk) { - /* Set DATA1 in advance for the next transfer. */ - LINK_REG->DCPCTR_b.SQSET = 1; - hcd_event_xfer_complete(LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); - } - if (is1 & LINK_REG_INTSTS1_SIGN_Msk) { - hcd_event_xfer_complete(LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); - } - if (is1 & LINK_REG_INTSTS1_ATTCH_Msk) { - LINK_REG->DVSTCTR0_b.UACT = 1; - _hcd.need_reset = true; - LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_ATTCH_Msk) | LINK_REG_INTSTS1_DTCH_Msk; - hcd_event_device_attach(rhport, true); - } - if (is1 & LINK_REG_INTSTS1_DTCH_Msk) { - LINK_REG->DVSTCTR0_b.UACT = 0; - if (LINK_REG->DCPCTR_b.SUREQ) { - LINK_REG->DCPCTR_b.SUREQCLR = 1; - } - LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_DTCH_Msk) | LINK_REG_INTSTS1_ATTCH_Msk; - hcd_event_device_remove(rhport, true); - } - - if (is0 & LINK_REG_INTSTS0_BEMP_Msk) { - const unsigned s = LINK_REG->BEMPSTS; - LINK_REG->BEMPSTS = 0; - if (s & 1) { - process_pipe0_bemp(rhport); - } - } - if (is0 & LINK_REG_INTSTS0_NRDY_Msk) { - const unsigned m = LINK_REG->NRDYENB; - unsigned s = LINK_REG->NRDYSTS & m; - LINK_REG->NRDYSTS = ~s; - while (s) { -#if defined(__CCRX__) - const unsigned num = Mod37BitPosition[(-s & s) % 37]; -#else - const unsigned num = __builtin_ctz(s); -#endif - process_pipe_nrdy(rhport, num); - s &= ~TU_BIT(num); - } - } - if (is0 & LINK_REG_INTSTS0_BRDY_Msk) { - const unsigned m = LINK_REG->BRDYENB; - unsigned s = LINK_REG->BRDYSTS & m; - /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ - LINK_REG->BRDYSTS = ~s; - while (s) { -#if defined(__CCRX__) - const unsigned num = Mod37BitPosition[(-s & s) % 37]; -#else - const unsigned num = __builtin_ctz(s); -#endif - process_pipe_brdy(rhport, num); - s &= ~TU_BIT(num); - } - } -} - -#endif diff --git a/src/portable/renesas/link/link_ra.h b/src/portable/renesas/link/link_ra.h deleted file mode 100644 index 97618ef8f..000000000 --- a/src/portable/renesas/link/link_ra.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2022 Rafael Silva (@perigoso) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef _LINK_RA_H_ -#define _LINK_RA_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "link_type.h" - -/* renesas fsp api */ -#include "bsp_api.h" - -#define LINK_REG_BASE (0x40090000) - -TU_ATTR_ALWAYS_INLINE -static inline void link_int_enable(uint8_t rhport) -{ - (void) rhport; - NVIC_EnableIRQ(TU_IRQn); -} - -TU_ATTR_ALWAYS_INLINE -static inline void link_int_disable(uint8_t rhport) -{ - (void) rhport; - NVIC_DisableIRQ(TU_IRQn); -} - -// MCU specific PHY init -static inline void link_phy_init(void) -{ -} - -#ifdef __cplusplus -} -#endif - -#endif /* _LINK_RA_H_ */ diff --git a/src/portable/renesas/link/link_rx.h b/src/portable/renesas/link/link_rx.h deleted file mode 100644 index 9e31c5b46..000000000 --- a/src/portable/renesas/link/link_rx.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 Koji Kitayama - * Portions copyrighted (c) 2021 Roland Winistoerfer - * Copyright (c) 2022 Rafael Silva (@perigoso) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef _LINK_RX_H_ -#define _LINK_RX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "link_type.h" - -#include "iodefine.h" - -#define LINK_REG_BASE (0x000A0000) - -TU_ATTR_ALWAYS_INLINE static inline void link_int_enable(uint8_t rhport) -{ - (void) rhport; -#if (CFG_TUSB_MCU == OPT_MCU_RX72N) - IEN(PERIB, INTB185) = 1; -#else - IEN(USB0, USBI0) = 1; -#endif -} - -TU_ATTR_ALWAYS_INLINE static inline void link_int_disable(uint8_t rhport) -{ - (void) rhport; -#if (CFG_TUSB_MCU == OPT_MCU_RX72N) - IEN(PERIB, INTB185) = 0; -#else - IEN(USB0, USBI0) = 0; -#endif -} - -// MCU specific PHY init -TU_ATTR_ALWAYS_INLINE static inline void link_phy_init(void) -{ -#if (CFG_TUSB_MCU == OPT_MCU_RX72N) - IR(PERIB, INTB185) = 0; -#else - IR(USB0, USBI0) = 0; -#endif -} - -#ifdef __cplusplus -} -#endif - -#endif /* _LINK_RX_H_ */ diff --git a/src/portable/renesas/link/link_type.h b/src/portable/renesas/link/link_type.h deleted file mode 100644 index cb3db650a..000000000 --- a/src/portable/renesas/link/link_type.h +++ /dev/null @@ -1,1669 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2022 Rafael Silva (@perigoso) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef _TUSB_LINK_TYPE_H_ -#define _TUSB_LINK_TYPE_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/*--------------------------------------------------------------------*/ -/* Register Definitions */ -/*--------------------------------------------------------------------*/ - -/* Start of definition of packed structs (used by the CCRX toolchain) */ -TU_ATTR_PACKED_BEGIN -TU_ATTR_BIT_FIELD_ORDER_BEGIN - -typedef struct TU_ATTR_PACKED { - union { - volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */ - - struct { - uint16_t : 8; - volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */ - volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */ - uint16_t : 6; - } E_b; - }; - - union { - volatile uint16_t N; /* (@ 0x00000002) Pipe Transaction Counter Register */ - - struct { - volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */ - } N_b; - }; -} LINK_REG_PIPE_TR_t; /* Size = 4 (0x4) */ - -/* LINK_REG Structure */ -typedef struct TU_ATTR_PACKED { - union { - volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */ - - struct { - volatile uint16_t USBE : 1; /* [0..0] USB Operation Enable */ - uint16_t : 2; - volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */ - volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */ - volatile uint16_t DRPD : 1; /* [5..5] D+/D- Line Resistor Control */ - volatile uint16_t DCFM : 1; /* [6..6] Controller Function Select */ - uint16_t : 1; - volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */ - uint16_t : 1; - volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */ - uint16_t : 5; - } SYSCFG_b; - }; - - union { - volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */ - - struct { - volatile uint16_t BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */ - uint16_t : 12; - } BUSWAIT_b; - }; - - union { - volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */ - - struct { - volatile const uint16_t LNST : 2; /* [1..0] USB Data Line Status Monitor */ - volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */ - uint16_t : 2; - volatile const uint16_t - SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */ - volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */ - uint16_t : 7; - volatile const uint16_t OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */ - } SYSSTS0_b; - }; - - union { - volatile const uint16_t PLLSTA; /* (@ 0x00000006) PLL Status Register */ - - struct { - volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */ - uint16_t : 15; - } PLLSTA_b; - }; - - union { - volatile uint16_t DVSTCTR0; /* (@ 0x00000008) Device State Control Register 0 */ - - struct { - volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */ - uint16_t : 1; - volatile uint16_t UACT : 1; /* [4..4] USB Bus Enable */ - volatile uint16_t RESUME : 1; /* [5..5] Resume Output */ - volatile uint16_t USBRST : 1; /* [6..6] USB Bus Reset Output */ - volatile uint16_t RWUPE : 1; /* [7..7] Wakeup Detection Enable */ - volatile uint16_t WKUP : 1; /* [8..8] Wakeup Output */ - volatile uint16_t VBUSEN : 1; /* [9..9] USB_VBUSEN Output Pin Control */ - volatile uint16_t EXICEN : 1; /* [10..10] USB_EXICEN Output Pin Control */ - volatile uint16_t HNPBTOA : 1; /* [11..11] Host Negotiation Protocol (HNP) */ - uint16_t : 4; - } DVSTCTR0_b; - }; - volatile const uint16_t RESERVED; - - union { - volatile uint16_t TESTMODE; /* (@ 0x0000000C) USB Test Mode Register */ - - struct { - volatile uint16_t UTST : 4; /* [3..0] Test Mode */ - uint16_t : 12; - } TESTMODE_b; - }; - volatile const uint16_t RESERVED1; - volatile const uint32_t RESERVED2; - - union { - volatile uint32_t CFIFO; /* (@ 0x00000014) CFIFO Port Register */ - - struct { - union { - volatile uint16_t CFIFOL; /* (@ 0x00000014) CFIFO Port Register L */ - volatile uint8_t CFIFOLL; /* (@ 0x00000014) CFIFO Port Register LL */ - }; - - union { - volatile uint16_t CFIFOH; /* (@ 0x00000016) CFIFO Port Register H */ - - struct { - volatile const uint8_t RESERVED3; - volatile uint8_t CFIFOHH; /* (@ 0x00000017) CFIFO Port Register HH */ - }; - }; - }; - }; - - union { - volatile uint32_t D0FIFO; /* (@ 0x00000018) D0FIFO Port Register */ - - struct { - union { - volatile uint16_t D0FIFOL; /* (@ 0x00000018) D0FIFO Port Register L */ - volatile uint8_t D0FIFOLL; /* (@ 0x00000018) D0FIFO Port Register LL */ - }; - - union { - volatile uint16_t D0FIFOH; /* (@ 0x0000001A) D0FIFO Port Register H */ - - struct { - volatile const uint8_t RESERVED4; - volatile uint8_t D0FIFOHH; /* (@ 0x0000001B) D0FIFO Port Register HH */ - }; - }; - }; - }; - - union { - volatile uint32_t D1FIFO; /* (@ 0x0000001C) D1FIFO Port Register */ - - struct { - union { - volatile uint16_t D1FIFOL; /* (@ 0x0000001C) D1FIFO Port Register L */ - volatile uint8_t D1FIFOLL; /* (@ 0x0000001C) D1FIFO Port Register LL */ - }; - - union { - volatile uint16_t D1FIFOH; /* (@ 0x0000001E) D1FIFO Port Register H */ - - struct { - volatile const uint8_t RESERVED5; - volatile uint8_t D1FIFOHH; /* (@ 0x0000001F) D1FIFO Port Register HH */ - }; - }; - }; - }; - - union { - volatile uint16_t CFIFOSEL; /* (@ 0x00000020) CFIFO Port Select Register */ - - struct { - volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */ - uint16_t : 1; - volatile uint16_t ISEL : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */ - uint16_t : 2; - volatile uint16_t BIGEND : 1; /* [8..8] CFIFO Port Endian Control */ - uint16_t : 1; - volatile uint16_t MBW : 2; /* [11..10] CFIFO Port Access Bit Width */ - uint16_t : 2; - volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */ - volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ - } CFIFOSEL_b; - }; - - union { - volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */ - - struct { - volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ - uint16_t : 1; - volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ - volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ - } CFIFOCTR_b; - }; - volatile const uint32_t RESERVED6; - - union { - volatile uint16_t D0FIFOSEL; /* (@ 0x00000028) D0FIFO Port Select Register */ - - struct { - volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ - uint16_t : 1; - volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */ - volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */ - volatile uint16_t DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */ - volatile uint16_t REW : 1; /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ - volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ - } D0FIFOSEL_b; - }; - - union { - volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */ - - struct { - volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ - uint16_t : 1; - volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ - volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ - } D0FIFOCTR_b; - }; - - union { - volatile uint16_t D1FIFOSEL; /* (@ 0x0000002C) D1FIFO Port Select Register */ - - struct { - volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ - uint16_t : 1; - volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */ - volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */ - volatile uint16_t DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */ - volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */ - volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ - } D1FIFOSEL_b; - }; - - union { - volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */ - - struct { - volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ - uint16_t : 1; - volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ - volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ - } D1FIFOCTR_b; - }; - - union { - volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */ - - struct { - uint16_t : 8; - volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */ - volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */ - volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */ - volatile uint16_t CTRE : 1; /* [11..11] Control Transfer Stage Transition Interrupt Enable */ - volatile uint16_t DVSE : 1; /* [12..12] Device State Transition Interrupt Enable */ - volatile uint16_t SOFE : 1; /* [13..13] Frame Number Update Interrupt Enable */ - volatile uint16_t RSME : 1; /* [14..14] Resume Interrupt Enable */ - volatile uint16_t VBSE : 1; /* [15..15] VBUS Interrupt Enable */ - } INTENB0_b; - }; - - union { - volatile uint16_t INTENB1; /* (@ 0x00000032) Interrupt Enable Register 1 */ - - struct { - volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */ - uint16_t : 3; - volatile uint16_t SACKE : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */ - volatile uint16_t SIGNE : 1; /* [5..5] Setup Transaction Error Interrupt Enable */ - volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 4; - volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */ - volatile uint16_t DTCHE : 1; /* [12..12] Disconnection Detection Interrupt Enable */ - uint16_t : 1; - volatile uint16_t BCHGE : 1; /* [14..14] USB Bus Change Interrupt Enable */ - volatile uint16_t OVRCRE : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */ - } INTENB1_b; - }; - volatile const uint16_t RESERVED7; - - union { - volatile uint16_t BRDYENB; /* (@ 0x00000036) BRDY Interrupt Enable Register */ - - struct { - volatile uint16_t PIPE0BRDYE : 1; /* [0..0] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE1BRDYE : 1; /* [1..1] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE2BRDYE : 1; /* [2..2] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE3BRDYE : 1; /* [3..3] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE4BRDYE : 1; /* [4..4] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE5BRDYE : 1; /* [5..5] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE6BRDYE : 1; /* [6..6] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } BRDYENB_b; - }; - - union { - volatile uint16_t NRDYENB; /* (@ 0x00000038) NRDY Interrupt Enable Register */ - - struct { - volatile uint16_t PIPE0NRDYE : 1; /* [0..0] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE1NRDYE : 1; /* [1..1] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE2NRDYE : 1; /* [2..2] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE3NRDYE : 1; /* [3..3] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE4NRDYE : 1; /* [4..4] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE5NRDYE : 1; /* [5..5] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE6NRDYE : 1; /* [6..6] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */ - volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } NRDYENB_b; - }; - - union { - volatile uint16_t BEMPENB; /* (@ 0x0000003A) BEMP Interrupt Enable Register */ - - struct { - volatile uint16_t PIPE0BEMPE : 1; /* [0..0] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE1BEMPE : 1; /* [1..1] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE2BEMPE : 1; /* [2..2] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE3BEMPE : 1; /* [3..3] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE4BEMPE : 1; /* [4..4] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE5BEMPE : 1; /* [5..5] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE6BEMPE : 1; /* [6..6] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */ - volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */ - uint16_t : 6; - } BEMPENB_b; - }; - - union { - volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */ - - struct { - uint16_t : 4; - volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */ - volatile uint16_t INTL : 1; /* [5..5] Interrupt Output Sense Select */ - volatile uint16_t BRDYM : 1; /* [6..6] BRDY Interrupt Status Clear Timing */ - uint16_t : 1; - volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */ - uint16_t : 7; - } SOFCFG_b; - }; - - union { - volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */ - - struct { - volatile uint16_t DIRPD : 1; /* [0..0] Power-Down Control */ - volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */ - uint16_t : 1; - volatile uint16_t CDPEN : 1; /* [3..3] Charging Downstream Port Enable */ - volatile uint16_t CLKSEL : 2; /* [5..4] Input System Clock Frequency */ - uint16_t : 2; - volatile uint16_t REPSEL : 2; /* [9..8] Terminating Resistance Adjustment Cycle */ - uint16_t : 1; - volatile uint16_t REPSTART : 1; /* [11..11] Forcibly Start Terminating Resistance Adjustment */ - uint16_t : 3; - volatile uint16_t HSEB : 1; /* [15..15] CL-Only Mode */ - } PHYSET_b; - }; - - union { - volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */ - - struct { - volatile const uint16_t CTSQ : 3; /* [2..0] Control Transfer Stage */ - volatile uint16_t VALID : 1; /* [3..3] USB Request Reception */ - volatile const uint16_t DVSQ : 3; /* [6..4] Device State */ - volatile const uint16_t VBSTS : 1; /* [7..7] VBUS Input Status */ - volatile const uint16_t BRDY : 1; /* [8..8] Buffer Ready Interrupt Status */ - volatile const uint16_t NRDY : 1; /* [9..9] Buffer Not Ready Interrupt Status */ - volatile const uint16_t BEMP : 1; /* [10..10] Buffer Empty Interrupt Status */ - volatile uint16_t CTRT : 1; /* [11..11] Control Transfer Stage Transition Interrupt Status */ - volatile uint16_t DVST : 1; /* [12..12] Device State Transition Interrupt Status */ - volatile uint16_t SOFR : 1; /* [13..13] Frame Number Refresh Interrupt Status */ - volatile uint16_t RESM : 1; /* [14..14] Resume Interrupt Status */ - volatile uint16_t VBINT : 1; /* [15..15] VBUS Interrupt Status */ - } INTSTS0_b; - }; - - union { - volatile uint16_t INTSTS1; /* (@ 0x00000042) Interrupt Status Register 1 */ - - struct { - volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */ - uint16_t : 3; - volatile uint16_t SACK : 1; /* [4..4] Setup Transaction Normal Response Interrupt Status */ - volatile uint16_t SIGN : 1; /* [5..5] Setup Transaction Error Interrupt Status */ - volatile uint16_t EOFERR : 1; /* [6..6] EOF Error Detection Interrupt Status */ - uint16_t : 1; - volatile uint16_t LPMEND : 1; /* [8..8] LPM Transaction End Interrupt Status */ - volatile uint16_t L1RSMEND : 1; /* [9..9] L1 Resume End Interrupt Status */ - uint16_t : 1; - volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */ - volatile uint16_t DTCH : 1; /* [12..12] USB Disconnection Detection Interrupt Status */ - uint16_t : 1; - volatile uint16_t BCHG : 1; /* [14..14] USB Bus Change Interrupt Status */ - volatile uint16_t OVRCR : 1; /* [15..15] Overcurrent Input Change Interrupt Status */ - } INTSTS1_b; - }; - volatile const uint16_t RESERVED8; - - union { - volatile uint16_t BRDYSTS; /* (@ 0x00000046) BRDY Interrupt Status Register */ - - struct { - volatile uint16_t PIPE0BRDY : 1; /* [0..0] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE1BRDY : 1; /* [1..1] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE2BRDY : 1; /* [2..2] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE3BRDY : 1; /* [3..3] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE4BRDY : 1; /* [4..4] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE5BRDY : 1; /* [5..5] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE6BRDY : 1; /* [6..6] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */ - uint16_t : 6; - } BRDYSTS_b; - }; - - union { - volatile uint16_t NRDYSTS; /* (@ 0x00000048) NRDY Interrupt Status Register */ - - struct { - volatile uint16_t PIPE0NRDY : 1; /* [0..0] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE1NRDY : 1; /* [1..1] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE2NRDY : 1; /* [2..2] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE3NRDY : 1; /* [3..3] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE4NRDY : 1; /* [4..4] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE5NRDY : 1; /* [5..5] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE6NRDY : 1; /* [6..6] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */ - volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */ - uint16_t : 6; - } NRDYSTS_b; - }; - - union { - volatile uint16_t BEMPSTS; /* (@ 0x0000004A) BEMP Interrupt Status Register */ - - struct { - volatile uint16_t PIPE0BEMP : 1; /* [0..0] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE1BEMP : 1; /* [1..1] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE2BEMP : 1; /* [2..2] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE3BEMP : 1; /* [3..3] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE4BEMP : 1; /* [4..4] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE5BEMP : 1; /* [5..5] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE6BEMP : 1; /* [6..6] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */ - volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */ - uint16_t : 6; - } BEMPSTS_b; - }; - - union { - volatile uint16_t FRMNUM; /* (@ 0x0000004C) Frame Number Register */ - - struct { - volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */ - uint16_t : 3; - volatile uint16_t CRCE : 1; /* [14..14] Receive Data Error */ - volatile uint16_t OVRN : 1; /* [15..15] Overrun/Underrun Detection Status */ - } FRMNUM_b; - }; - - union { - volatile uint16_t UFRMNUM; /* (@ 0x0000004E) uFrame Number Register */ - - struct { - volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; - volatile uint16_t DVCHG : 1; /* [15..15] Device State Change */ - } UFRMNUM_b; - }; - - union { - volatile uint16_t USBADDR; /* (@ 0x00000050) USB Address Register */ - - struct { - volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */ - uint16_t : 1; - volatile uint16_t STSRECOV0 : 3; /* [10..8] Status Recovery */ - uint16_t : 5; - } USBADDR_b; - }; - volatile const uint16_t RESERVED9; - - union { - volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */ - - struct { - volatile uint16_t BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */ - volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */ - } USBREQ_b; - }; - - union { - volatile uint16_t USBVAL; /* (@ 0x00000056) USB Request Value Register */ - - struct { - volatile uint16_t WVALUE : 16; /* [15..0] ValueThese bits store the USB request Value value. */ - } USBVAL_b; - }; - - union { - volatile uint16_t USBINDX; /* (@ 0x00000058) USB Request Index Register */ - - struct { - volatile uint16_t WINDEX : 16; /* [15..0] IndexThese bits store the USB request wIndex value. */ - } USBINDX_b; - }; - - union { - volatile uint16_t USBLENG; /* (@ 0x0000005A) USB Request Length Register */ - - struct { - volatile uint16_t WLENGTH : 16; /* [15..0] LengthThese bits store the USB request wLength value. */ - } USBLENG_b; - }; - - union { - volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */ - - struct { - uint16_t : 4; - volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ - uint16_t : 2; - volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */ - volatile uint16_t CNTMD : 1; /* [8..8] Continuous Transfer Mode */ - uint16_t : 7; - } DCPCFG_b; - }; - - union { - volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */ - - struct { - volatile uint16_t MXPS : 7; /* [6..0] Maximum Packet Size */ - uint16_t : 5; - volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ - } DCPMAXP_b; - }; - - union { - volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */ - - struct { - volatile uint16_t PID : 2; /* [1..0] Response PID */ - volatile uint16_t CCPL : 1; /* [2..2] Control Transfer End Enable */ - uint16_t : 2; - volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */ - volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Monitor */ - volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */ - volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ - uint16_t : 2; - volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */ - uint16_t : 2; - volatile uint16_t SUREQ : 1; /* [14..14] Setup Token Transmission */ - volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ - } DCPCTR_b; - }; - volatile const uint16_t RESERVED10; - - union { - volatile uint16_t PIPESEL; /* (@ 0x00000064) Pipe Window Select Register */ - - struct { - volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */ - uint16_t : 12; - } PIPESEL_b; - }; - volatile const uint16_t RESERVED11; - - union { - volatile uint16_t PIPECFG; /* (@ 0x00000068) Pipe Configuration Register */ - - struct { - volatile uint16_t EPNUM : 4; /* [3..0] Endpoint Number */ - volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ - uint16_t : 2; - volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */ - uint16_t : 1; - volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */ - volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */ - uint16_t : 3; - volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */ - } PIPECFG_b; - }; - volatile const uint16_t RESERVED12; - - union { - volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */ - - struct { - volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */ - uint16_t : 3; - volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ - } PIPEMAXP_b; - }; - - union { - volatile uint16_t PIPEPERI; /* (@ 0x0000006E) Pipe Cycle Control Register */ - - struct { - volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */ - uint16_t : 9; - volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */ - uint16_t : 3; - } PIPEPERI_b; - }; - - union { - volatile uint16_t PIPE_CTR[9]; /* (@ 0x00000070) Pipe [0..8] Control Register */ - - struct { - volatile uint16_t PID : 2; /* [1..0] Response PID */ - uint16_t : 3; - volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */ - volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Confirmation */ - volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */ - volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ - volatile uint16_t ACLRM : 1; /* [9..9] Auto Buffer Clear Mode */ - volatile uint16_t ATREPM : 1; /* [10..10] Auto Response Mode */ - uint16_t : 1; - volatile const uint16_t CSSTS : 1; /* [12..12] CSSTS Status */ - volatile uint16_t CSCLR : 1; /* [13..13] CSPLIT Status Clear */ - volatile const uint16_t INBUFM : 1; /* [14..14] Transmit Buffer Monitor */ - volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ - } PIPE_CTR_b[9]; - }; - volatile const uint16_t RESERVED13; - volatile const uint32_t RESERVED14[3]; - volatile LINK_REG_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */ - volatile const uint32_t RESERVED15[3]; - - union { - volatile uint16_t USBBCCTRL0; /* (@ 0x000000B0) BC Control Register 0 */ - - struct { - volatile uint16_t RPDME0 : 1; /* [0..0] D- Pin Pull-Down Control */ - volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */ - volatile uint16_t - IDMSINKE0 : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ - volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ - volatile uint16_t - IDPSINKE0 : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ - volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */ - uint16_t : 1; - volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ - volatile const uint16_t CHGDETSTS0 : 1; /* [8..8] D- Pin 0.6 V Input Detection Status */ - volatile const uint16_t PDDETSTS0 : 1; /* [9..9] D+ Pin 0.6 V Input Detection Status */ - uint16_t : 6; - } USBBCCTRL0_b; - }; - volatile const uint16_t RESERVED16; - volatile const uint32_t RESERVED17[4]; - - union { - volatile uint16_t UCKSEL; /* (@ 0x000000C4) USB Clock Selection Register */ - - struct { - volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */ - uint16_t : 15; - } UCKSEL_b; - }; - volatile const uint16_t RESERVED18; - volatile const uint32_t RESERVED19; - - union { - volatile uint16_t USBMC; /* (@ 0x000000CC) USB Module Control Register */ - - struct { - volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */ - uint16_t : 6; - volatile uint16_t VDCEN : 1; /* [7..7] USB Regulator On/Off Control */ - uint16_t : 8; - } USBMC_b; - }; - volatile const uint16_t RESERVED20; - - union { - volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */ - - struct { - uint16_t : 6; - volatile uint16_t USBSPD : 2; /* [7..6] Transfer Speed of Communication Target Device */ - volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */ - volatile uint16_t UPPHUB : 4; /* [14..11] Communication Target Connecting Hub Register */ - uint16_t : 1; - } DEVADD_b[10]; - }; - volatile const uint32_t RESERVED21[3]; - - union { - volatile uint32_t PHYSLEW; /* (@ 0x000000F0) PHY Cross Point Adjustment Register */ - - struct { - volatile uint32_t SLEWR00 : 1; /* [0..0] Receiver Cross Point Adjustment 00 */ - volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */ - volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */ - volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */ - uint32_t : 28; - } PHYSLEW_b; - }; - volatile const uint32_t RESERVED22[3]; - - union { - volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */ - - struct { - uint16_t : 7; - volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */ - uint16_t : 8; - } LPCTRL_b; - }; - - union { - volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */ - - struct { - uint16_t : 14; - volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */ - uint16_t : 1; - } LPSTS_b; - }; - volatile const uint32_t RESERVED23[15]; - - union { - volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */ - - struct { - volatile uint16_t IDPSRCE : 1; /* [0..0] IDPSRC Control */ - volatile uint16_t IDMSINKE : 1; /* [1..1] IDMSINK Control */ - volatile uint16_t VDPSRCE : 1; /* [2..2] VDPSRC Control */ - volatile uint16_t IDPSINKE : 1; /* [3..3] IDPSINK Control */ - volatile uint16_t VDMSRCE : 1; /* [4..4] VDMSRC Control */ - volatile uint16_t DCPMODE : 1; /* [5..5] DCP Mode Control */ - uint16_t : 2; - volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */ - volatile const uint16_t PDDETSTS : 1; /* [9..9] PDDET Status */ - uint16_t : 6; - } BCCTRL_b; - }; - volatile const uint16_t RESERVED24; - - union { - volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */ - - struct { - volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */ - volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */ - volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */ - volatile const uint16_t DVSQ : 4; /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */ - volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */ - uint16_t : 2; - volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */ - uint16_t : 1; - } PL1CTRL1_b; - }; - - union { - volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */ - - struct { - uint16_t : 8; - volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */ - volatile uint16_t RWEMON : 1; /* [12..12] RWE Value Monitor */ - uint16_t : 3; - } PL1CTRL2_b; - }; - - union { - volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */ - - struct { - volatile uint16_t L1REQ : 1; /* [0..0] L1 Transition Request */ - volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */ - uint16_t : 13; - } HL1CTRL1_b; - }; - - union { - volatile uint16_t HL1CTRL2; /* (@ 0x0000014A) Host L1 Control Register 2 */ - - struct { - volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */ - uint16_t : 4; - volatile uint16_t HIRD : 4; /* [11..8] LPM Token HIRD */ - volatile uint16_t L1RWE : 1; /* [12..12] LPM Token L1 Remote Wake Enable */ - uint16_t : 2; - volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */ - } HL1CTRL2_b; - }; - volatile const uint32_t RESERVED25[5]; - - union { - volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */ - - struct { - uint32_t : 20; - volatile const uint32_t DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */ - volatile const uint32_t DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */ - uint32_t : 1; - volatile const uint32_t DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */ - uint32_t : 8; - } DPUSR0R_b; - }; - - union { - volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct { - uint32_t : 4; - volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */ - volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */ - uint32_t : 1; - volatile uint32_t DVBSTSHE : 1; /* [7..7] VBUS Interrupt Enable/Clear */ - uint32_t : 12; - volatile const uint32_t DOVCAH : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */ - volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */ - uint32_t : 1; - volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */ - uint32_t : 8; - } DPUSR1R_b; - }; - - union { - volatile uint16_t DPUSR2R; /* (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct { - volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */ - volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */ - uint16_t : 2; - volatile const uint16_t DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */ - volatile const uint16_t DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */ - uint16_t : 2; - volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */ - volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */ - uint16_t : 6; - } DPUSR2R_b; - }; - - union { - volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ - - struct { - volatile uint16_t FIXPHY : 1; /* [0..0] USB Transceiver Control Fix */ - volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */ - uint16_t : 14; - } DPUSRCR_b; - }; - volatile const uint32_t RESERVED26[165]; - - union { - volatile uint32_t - DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */ - - struct { - volatile uint32_t SRPC0 : 1; /* [0..0] USB Single End Receiver Control */ - volatile uint32_t RPUE0 : 1; /* [1..1] DP Pull-Up Resistor Control */ - uint32_t : 1; - volatile uint32_t DRPD0 : 1; /* [3..3] D+/D- Pull-Down Resistor Control */ - volatile uint32_t FIXPHY0 : 1; /* [4..4] USB Transceiver Output Fix */ - uint32_t : 11; - volatile const uint32_t DP0 : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ - volatile const uint32_t DM0 : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */ - uint32_t : 2; - volatile const uint32_t DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */ - volatile const uint32_t DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */ - uint32_t : 1; - volatile const uint32_t DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */ - uint32_t : 8; - } DPUSR0R_FS_b; - }; - - union { - volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */ - - struct { - volatile uint32_t DPINTE0 : 1; /* [0..0] USB DP Interrupt Enable/Clear */ - volatile uint32_t DMINTE0 : 1; /* [1..1] USB DM Interrupt Enable/Clear */ - uint32_t : 2; - volatile uint32_t DOVRCRAE0 : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */ - volatile uint32_t DOVRCRBE0 : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */ - uint32_t : 1; - volatile uint32_t DVBSE0 : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */ - uint32_t : 8; - volatile const uint32_t DPINT0 : 1; /* [16..16] USB DP Interrupt Source Recovery */ - volatile const uint32_t DMINT0 : 1; /* [17..17] USB DM Interrupt Source Recovery */ - uint32_t : 2; - volatile const uint32_t DOVRCRA0 : 1; /* [20..20] USB OVRCURA Interrupt Source Recovery */ - volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */ - uint32_t : 1; - volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */ - uint32_t : 8; - } DPUSR1R_FS_b; - }; -} LINK_REG_t; /* Size = 1032 (0x408) */ - -TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */ -TU_ATTR_BIT_FIELD_ORDER_END - -/*--------------------------------------------------------------------*/ -/* Register Bit Definitions */ -/*--------------------------------------------------------------------*/ - -// PIPE_TR -// E -#define LINK_REG_PIPE_TR_E_TRENB_Pos (9UL) /* TRENB (Bit 9) */ -#define LINK_REG_PIPE_TR_E_TRENB_Msk (0x200UL) /* TRENB (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_TR_E_TRCLR_Pos (8UL) /* TRCLR (Bit 8) */ -#define LINK_REG_PIPE_TR_E_TRCLR_Msk (0x100UL) /* TRCLR (Bitfield-Mask: 0x01) */ - -// N -#define LINK_REG_PIPE_TR_N_TRNCNT_Pos (0UL) /* TRNCNT (Bit 0) */ -#define LINK_REG_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /* TRNCNT (Bitfield-Mask: 0xffff) */ - -// LINK_REG - -// SYSCFG -#define LINK_REG_SYSCFG_SCKE_Pos (10UL) /* SCKE (Bit 10) */ -#define LINK_REG_SYSCFG_SCKE_Msk (0x400UL) /* SCKE (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_CNEN_Pos (8UL) /* CNEN (Bit 8) */ -#define LINK_REG_SYSCFG_CNEN_Msk (0x100UL) /* CNEN (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_DCFM_Pos (6UL) /* DCFM (Bit 6) */ -#define LINK_REG_SYSCFG_DCFM_Msk (0x40UL) /* DCFM (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_DRPD_Pos (5UL) /* DRPD (Bit 5) */ -#define LINK_REG_SYSCFG_DRPD_Msk (0x20UL) /* DRPD (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_DPRPU_Pos (4UL) /* DPRPU (Bit 4) */ -#define LINK_REG_SYSCFG_DPRPU_Msk (0x10UL) /* DPRPU (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_DMRPU_Pos (3UL) /* DMRPU (Bit 3) */ -#define LINK_REG_SYSCFG_DMRPU_Msk (0x8UL) /* DMRPU (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_USBE_Pos (0UL) /* USBE (Bit 0) */ -#define LINK_REG_SYSCFG_USBE_Msk (0x1UL) /* USBE (Bitfield-Mask: 0x01) */ - -// BUSWAIT -#define LINK_REG_BUSWAIT_BWAIT_Pos (0UL) /* BWAIT (Bit 0) */ -#define LINK_REG_BUSWAIT_BWAIT_Msk (0xfUL) /* BWAIT (Bitfield-Mask: 0x0f) */ - -// SYSSTS0 -#define LINK_REG_SYSSTS0_OVCMON_Pos (14UL) /* OVCMON (Bit 14) */ -#define LINK_REG_SYSSTS0_OVCMON_Msk (0xc000UL) /* OVCMON (Bitfield-Mask: 0x03) */ -#define LINK_REG_SYSSTS0_HTACT_Pos (6UL) /* HTACT (Bit 6) */ -#define LINK_REG_SYSSTS0_HTACT_Msk (0x40UL) /* HTACT (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSSTS0_SOFEA_Pos (5UL) /* SOFEA (Bit 5) */ -#define LINK_REG_SYSSTS0_SOFEA_Msk (0x20UL) /* SOFEA (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSSTS0_IDMON_Pos (2UL) /* IDMON (Bit 2) */ -#define LINK_REG_SYSSTS0_IDMON_Msk (0x4UL) /* IDMON (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSSTS0_LNST_Pos (0UL) /* LNST (Bit 0) */ -#define LINK_REG_SYSSTS0_LNST_Msk (0x3UL) /* LNST (Bitfield-Mask: 0x03) */ - -// PLLSTA -#define LINK_REG_PLLSTA_PLLLOCK_Pos (0UL) /* PLLLOCK (Bit 0) */ -#define LINK_REG_PLLSTA_PLLLOCK_Msk (0x1UL) /* PLLLOCK (Bitfield-Mask: 0x01) */ - -// DVSTCTR0 -#define LINK_REG_DVSTCTR0_HNPBTOA_Pos (11UL) /* HNPBTOA (Bit 11) */ -#define LINK_REG_DVSTCTR0_HNPBTOA_Msk (0x800UL) /* HNPBTOA (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_EXICEN_Pos (10UL) /* EXICEN (Bit 10) */ -#define LINK_REG_DVSTCTR0_EXICEN_Msk (0x400UL) /* EXICEN (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_VBUSEN_Pos (9UL) /* VBUSEN (Bit 9) */ -#define LINK_REG_DVSTCTR0_VBUSEN_Msk (0x200UL) /* VBUSEN (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_WKUP_Pos (8UL) /* WKUP (Bit 8) */ -#define LINK_REG_DVSTCTR0_WKUP_Msk (0x100UL) /* WKUP (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_RWUPE_Pos (7UL) /* RWUPE (Bit 7) */ -#define LINK_REG_DVSTCTR0_RWUPE_Msk (0x80UL) /* RWUPE (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_USBRST_Pos (6UL) /* USBRST (Bit 6) */ -#define LINK_REG_DVSTCTR0_USBRST_Msk (0x40UL) /* USBRST (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_RESUME_Pos (5UL) /* RESUME (Bit 5) */ -#define LINK_REG_DVSTCTR0_RESUME_Msk (0x20UL) /* RESUME (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_UACT_Pos (4UL) /* UACT (Bit 4) */ -#define LINK_REG_DVSTCTR0_UACT_Msk (0x10UL) /* UACT (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_RHST_Pos (0UL) /* RHST (Bit 0) */ -#define LINK_REG_DVSTCTR0_RHST_Msk (0x7UL) /* RHST (Bitfield-Mask: 0x07) */ - -// TESTMODE -#define LINK_REG_TESTMODE_UTST_Pos (0UL) /* UTST (Bit 0) */ -#define LINK_REG_TESTMODE_UTST_Msk (0xfUL) /* UTST (Bitfield-Mask: 0x0f) */ - -// CFIFOSEL -#define LINK_REG_CFIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ -#define LINK_REG_CFIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ -#define LINK_REG_CFIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ -#define LINK_REG_CFIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ -#define LINK_REG_CFIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ -#define LINK_REG_CFIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOSEL_ISEL_Pos (5UL) /* ISEL (Bit 5) */ -#define LINK_REG_CFIFOSEL_ISEL_Msk (0x20UL) /* ISEL (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ -#define LINK_REG_CFIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ - -// CFIFOCTR -#define LINK_REG_CFIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ -#define LINK_REG_CFIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ -#define LINK_REG_CFIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ -#define LINK_REG_CFIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ -#define LINK_REG_CFIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ - -// D0FIFOSEL -#define LINK_REG_D0FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ -#define LINK_REG_D0FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ -#define LINK_REG_D0FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ -#define LINK_REG_D0FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ -#define LINK_REG_D0FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ -#define LINK_REG_D0FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ -#define LINK_REG_D0FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ -#define LINK_REG_D0FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ -#define LINK_REG_D0FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ - -// D0FIFOCTR -#define LINK_REG_D0FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ -#define LINK_REG_D0FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ -#define LINK_REG_D0FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ -#define LINK_REG_D0FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ -#define LINK_REG_D0FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ - -// D1FIFOSEL -#define LINK_REG_D1FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ -#define LINK_REG_D1FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ -#define LINK_REG_D1FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ -#define LINK_REG_D1FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ -#define LINK_REG_D1FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ -#define LINK_REG_D1FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ -#define LINK_REG_D1FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ -#define LINK_REG_D1FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ -#define LINK_REG_D1FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ - -// D1FIFOCTR -#define LINK_REG_D1FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ -#define LINK_REG_D1FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ -#define LINK_REG_D1FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ -#define LINK_REG_D1FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ -#define LINK_REG_D1FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ - -// INTENB0 -#define LINK_REG_INTENB0_VBSE_Pos (15UL) /* VBSE (Bit 15) */ -#define LINK_REG_INTENB0_VBSE_Msk (0x8000UL) /* VBSE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_RSME_Pos (14UL) /* RSME (Bit 14) */ -#define LINK_REG_INTENB0_RSME_Msk (0x4000UL) /* RSME (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_SOFE_Pos (13UL) /* SOFE (Bit 13) */ -#define LINK_REG_INTENB0_SOFE_Msk (0x2000UL) /* SOFE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_DVSE_Pos (12UL) /* DVSE (Bit 12) */ -#define LINK_REG_INTENB0_DVSE_Msk (0x1000UL) /* DVSE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_CTRE_Pos (11UL) /* CTRE (Bit 11) */ -#define LINK_REG_INTENB0_CTRE_Msk (0x800UL) /* CTRE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_BEMPE_Pos (10UL) /* BEMPE (Bit 10) */ -#define LINK_REG_INTENB0_BEMPE_Msk (0x400UL) /* BEMPE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_NRDYE_Pos (9UL) /* NRDYE (Bit 9) */ -#define LINK_REG_INTENB0_NRDYE_Msk (0x200UL) /* NRDYE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_BRDYE_Pos (8UL) /* BRDYE (Bit 8) */ -#define LINK_REG_INTENB0_BRDYE_Msk (0x100UL) /* BRDYE (Bitfield-Mask: 0x01) */ - -// INTENB1 -#define LINK_REG_INTENB1_OVRCRE_Pos (15UL) /* OVRCRE (Bit 15) */ -#define LINK_REG_INTENB1_OVRCRE_Msk (0x8000UL) /* OVRCRE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_BCHGE_Pos (14UL) /* BCHGE (Bit 14) */ -#define LINK_REG_INTENB1_BCHGE_Msk (0x4000UL) /* BCHGE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_DTCHE_Pos (12UL) /* DTCHE (Bit 12) */ -#define LINK_REG_INTENB1_DTCHE_Msk (0x1000UL) /* DTCHE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_ATTCHE_Pos (11UL) /* ATTCHE (Bit 11) */ -#define LINK_REG_INTENB1_ATTCHE_Msk (0x800UL) /* ATTCHE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_EOFERRE_Pos (6UL) /* EOFERRE (Bit 6) */ -#define LINK_REG_INTENB1_EOFERRE_Msk (0x40UL) /* EOFERRE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_SIGNE_Pos (5UL) /* SIGNE (Bit 5) */ -#define LINK_REG_INTENB1_SIGNE_Msk (0x20UL) /* SIGNE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_SACKE_Pos (4UL) /* SACKE (Bit 4) */ -#define LINK_REG_INTENB1_SACKE_Msk (0x10UL) /* SACKE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_PDDETINTE0_Pos (0UL) /* PDDETINTE0 (Bit 0) */ -#define LINK_REG_INTENB1_PDDETINTE0_Msk (0x1UL) /* PDDETINTE0 (Bitfield-Mask: 0x01) */ - -// BRDYENB -#define LINK_REG_BRDYENB_PIPEBRDYE_Pos (0UL) /* PIPEBRDYE (Bit 0) */ -#define LINK_REG_BRDYENB_PIPEBRDYE_Msk (0x1UL) /* PIPEBRDYE (Bitfield-Mask: 0x01) */ - -// NRDYENB -#define LINK_REG_NRDYENB_PIPENRDYE_Pos (0UL) /* PIPENRDYE (Bit 0) */ -#define LINK_REG_NRDYENB_PIPENRDYE_Msk (0x1UL) /* PIPENRDYE (Bitfield-Mask: 0x01) */ - -// BEMPENB -#define LINK_REG_BEMPENB_PIPEBEMPE_Pos (0UL) /* PIPEBEMPE (Bit 0) */ -#define LINK_REG_BEMPENB_PIPEBEMPE_Msk (0x1UL) /* PIPEBEMPE (Bitfield-Mask: 0x01) */ - -// SOFCFG -#define LINK_REG_SOFCFG_TRNENSEL_Pos (8UL) /* TRNENSEL (Bit 8) */ -#define LINK_REG_SOFCFG_TRNENSEL_Msk (0x100UL) /* TRNENSEL (Bitfield-Mask: 0x01) */ -#define LINK_REG_SOFCFG_BRDYM_Pos (6UL) /* BRDYM (Bit 6) */ -#define LINK_REG_SOFCFG_BRDYM_Msk (0x40UL) /* BRDYM (Bitfield-Mask: 0x01) */ -#define LINK_REG_SOFCFG_INTL_Pos (5UL) /* INTL (Bit 5) */ -#define LINK_REG_SOFCFG_INTL_Msk (0x20UL) /* INTL (Bitfield-Mask: 0x01) */ -#define LINK_REG_SOFCFG_EDGESTS_Pos (4UL) /* EDGESTS (Bit 4) */ -#define LINK_REG_SOFCFG_EDGESTS_Msk (0x10UL) /* EDGESTS (Bitfield-Mask: 0x01) */ - -// PHYSET -#define LINK_REG_PHYSET_HSEB_Pos (15UL) /* HSEB (Bit 15) */ -#define LINK_REG_PHYSET_HSEB_Msk (0x8000UL) /* HSEB (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSET_REPSTART_Pos (11UL) /* REPSTART (Bit 11) */ -#define LINK_REG_PHYSET_REPSTART_Msk (0x800UL) /* REPSTART (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSET_REPSEL_Pos (8UL) /* REPSEL (Bit 8) */ -#define LINK_REG_PHYSET_REPSEL_Msk (0x300UL) /* REPSEL (Bitfield-Mask: 0x03) */ -#define LINK_REG_PHYSET_CLKSEL_Pos (4UL) /* CLKSEL (Bit 4) */ -#define LINK_REG_PHYSET_CLKSEL_Msk (0x30UL) /* CLKSEL (Bitfield-Mask: 0x03) */ -#define LINK_REG_PHYSET_CDPEN_Pos (3UL) /* CDPEN (Bit 3) */ -#define LINK_REG_PHYSET_CDPEN_Msk (0x8UL) /* CDPEN (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSET_PLLRESET_Pos (1UL) /* PLLRESET (Bit 1) */ -#define LINK_REG_PHYSET_PLLRESET_Msk (0x2UL) /* PLLRESET (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSET_DIRPD_Pos (0UL) /* DIRPD (Bit 0) */ -#define LINK_REG_PHYSET_DIRPD_Msk (0x1UL) /* DIRPD (Bitfield-Mask: 0x01) */ - -// INTSTS0 -#define LINK_REG_INTSTS0_VBINT_Pos (15UL) /* VBINT (Bit 15) */ -#define LINK_REG_INTSTS0_VBINT_Msk (0x8000UL) /* VBINT (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_RESM_Pos (14UL) /* RESM (Bit 14) */ -#define LINK_REG_INTSTS0_RESM_Msk (0x4000UL) /* RESM (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_SOFR_Pos (13UL) /* SOFR (Bit 13) */ -#define LINK_REG_INTSTS0_SOFR_Msk (0x2000UL) /* SOFR (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_DVST_Pos (12UL) /* DVST (Bit 12) */ -#define LINK_REG_INTSTS0_DVST_Msk (0x1000UL) /* DVST (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_CTRT_Pos (11UL) /* CTRT (Bit 11) */ -#define LINK_REG_INTSTS0_CTRT_Msk (0x800UL) /* CTRT (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_BEMP_Pos (10UL) /* BEMP (Bit 10) */ -#define LINK_REG_INTSTS0_BEMP_Msk (0x400UL) /* BEMP (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_NRDY_Pos (9UL) /* NRDY (Bit 9) */ -#define LINK_REG_INTSTS0_NRDY_Msk (0x200UL) /* NRDY (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_BRDY_Pos (8UL) /* BRDY (Bit 8) */ -#define LINK_REG_INTSTS0_BRDY_Msk (0x100UL) /* BRDY (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_VBSTS_Pos (7UL) /* VBSTS (Bit 7) */ -#define LINK_REG_INTSTS0_VBSTS_Msk (0x80UL) /* VBSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ -#define LINK_REG_INTSTS0_DVSQ_Msk (0x70UL) /* DVSQ (Bitfield-Mask: 0x07) */ -#define LINK_REG_INTSTS0_VALID_Pos (3UL) /* VALID (Bit 3) */ -#define LINK_REG_INTSTS0_VALID_Msk (0x8UL) /* VALID (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_CTSQ_Pos (0UL) /* CTSQ (Bit 0) */ -#define LINK_REG_INTSTS0_CTSQ_Msk (0x7UL) /* CTSQ (Bitfield-Mask: 0x07) */ - -// INTSTS1 -#define LINK_REG_INTSTS1_OVRCR_Pos (15UL) /* OVRCR (Bit 15) */ -#define LINK_REG_INTSTS1_OVRCR_Msk (0x8000UL) /* OVRCR (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_BCHG_Pos (14UL) /* BCHG (Bit 14) */ -#define LINK_REG_INTSTS1_BCHG_Msk (0x4000UL) /* BCHG (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_DTCH_Pos (12UL) /* DTCH (Bit 12) */ -#define LINK_REG_INTSTS1_DTCH_Msk (0x1000UL) /* DTCH (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_ATTCH_Pos (11UL) /* ATTCH (Bit 11) */ -#define LINK_REG_INTSTS1_ATTCH_Msk (0x800UL) /* ATTCH (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_L1RSMEND_Pos (9UL) /* L1RSMEND (Bit 9) */ -#define LINK_REG_INTSTS1_L1RSMEND_Msk (0x200UL) /* L1RSMEND (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_LPMEND_Pos (8UL) /* LPMEND (Bit 8) */ -#define LINK_REG_INTSTS1_LPMEND_Msk (0x100UL) /* LPMEND (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_EOFERR_Pos (6UL) /* EOFERR (Bit 6) */ -#define LINK_REG_INTSTS1_EOFERR_Msk (0x40UL) /* EOFERR (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_SIGN_Pos (5UL) /* SIGN (Bit 5) */ -#define LINK_REG_INTSTS1_SIGN_Msk (0x20UL) /* SIGN (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_SACK_Pos (4UL) /* SACK (Bit 4) */ -#define LINK_REG_INTSTS1_SACK_Msk (0x10UL) /* SACK (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_PDDETINT0_Pos (0UL) /* PDDETINT0 (Bit 0) */ -#define LINK_REG_INTSTS1_PDDETINT0_Msk (0x1UL) /* PDDETINT0 (Bitfield-Mask: 0x01) */ - -// BRDYSTS -#define LINK_REG_BRDYSTS_PIPEBRDY_Pos (0UL) /* PIPEBRDY (Bit 0) */ -#define LINK_REG_BRDYSTS_PIPEBRDY_Msk (0x1UL) /* PIPEBRDY (Bitfield-Mask: 0x01) */ - -// NRDYSTS -#define LINK_REG_NRDYSTS_PIPENRDY_Pos (0UL) /* PIPENRDY (Bit 0) */ -#define LINK_REG_NRDYSTS_PIPENRDY_Msk (0x1UL) /* PIPENRDY (Bitfield-Mask: 0x01) */ - -// BEMPSTS -#define LINK_REG_BEMPSTS_PIPEBEMP_Pos (0UL) /* PIPEBEMP (Bit 0) */ -#define LINK_REG_BEMPSTS_PIPEBEMP_Msk (0x1UL) /* PIPEBEMP (Bitfield-Mask: 0x01) */ - -// FRMNUM -#define LINK_REG_FRMNUM_OVRN_Pos (15UL) /* OVRN (Bit 15) */ -#define LINK_REG_FRMNUM_OVRN_Msk (0x8000UL) /* OVRN (Bitfield-Mask: 0x01) */ -#define LINK_REG_FRMNUM_CRCE_Pos (14UL) /* CRCE (Bit 14) */ -#define LINK_REG_FRMNUM_CRCE_Msk (0x4000UL) /* CRCE (Bitfield-Mask: 0x01) */ -#define LINK_REG_FRMNUM_FRNM_Pos (0UL) /* FRNM (Bit 0) */ -#define LINK_REG_FRMNUM_FRNM_Msk (0x7ffUL) /* FRNM (Bitfield-Mask: 0x7ff) */ - -// UFRMNUM -#define LINK_REG_UFRMNUM_DVCHG_Pos (15UL) /* DVCHG (Bit 15) */ -#define LINK_REG_UFRMNUM_DVCHG_Msk (0x8000UL) /* DVCHG (Bitfield-Mask: 0x01) */ -#define LINK_REG_UFRMNUM_UFRNM_Pos (0UL) /* UFRNM (Bit 0) */ -#define LINK_REG_UFRMNUM_UFRNM_Msk (0x7UL) /* UFRNM (Bitfield-Mask: 0x07) */ - -// USBADDR -#define LINK_REG_USBADDR_STSRECOV0_Pos (8UL) /* STSRECOV0 (Bit 8) */ -#define LINK_REG_USBADDR_STSRECOV0_Msk (0x700UL) /* STSRECOV0 (Bitfield-Mask: 0x07) */ -#define LINK_REG_USBADDR_USBADDR_Pos (0UL) /* USBADDR (Bit 0) */ -#define LINK_REG_USBADDR_USBADDR_Msk (0x7fUL) /* USBADDR (Bitfield-Mask: 0x7f) */ - -// USBREQ -#define LINK_REG_USBREQ_BREQUEST_Pos (8UL) /* BREQUEST (Bit 8) */ -#define LINK_REG_USBREQ_BREQUEST_Msk (0xff00UL) /* BREQUEST (Bitfield-Mask: 0xff) */ -#define LINK_REG_USBREQ_BMREQUESTTYPE_Pos (0UL) /* BMREQUESTTYPE (Bit 0) */ -#define LINK_REG_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */ - -// USBVAL -#define LINK_REG_USBVAL_WVALUE_Pos (0UL) /* WVALUE (Bit 0) */ -#define LINK_REG_USBVAL_WVALUE_Msk (0xffffUL) /* WVALUE (Bitfield-Mask: 0xffff) */ - -// USBINDX -#define LINK_REG_USBINDX_WINDEX_Pos (0UL) /* WINDEX (Bit 0) */ -#define LINK_REG_USBINDX_WINDEX_Msk (0xffffUL) /* WINDEX (Bitfield-Mask: 0xffff) */ - -// USBLENG -#define LINK_REG_USBLENG_WLENGTH_Pos (0UL) /* WLENGTH (Bit 0) */ -#define LINK_REG_USBLENG_WLENGTH_Msk (0xffffUL) /* WLENGTH (Bitfield-Mask: 0xffff) */ - -// DCPCFG -#define LINK_REG_DCPCFG_CNTMD_Pos (8UL) /* CNTMD (Bit 8) */ -#define LINK_REG_DCPCFG_CNTMD_Msk (0x100UL) /* CNTMD (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ -#define LINK_REG_DCPCFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCFG_DIR_Pos (4UL) /* DIR (Bit 4) */ -#define LINK_REG_DCPCFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ - -// DCPMAXP -#define LINK_REG_DCPMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ -#define LINK_REG_DCPMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ -#define LINK_REG_DCPMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ -#define LINK_REG_DCPMAXP_MXPS_Msk (0x7fUL) /* MXPS (Bitfield-Mask: 0x7f) */ - -// DCPCTR -#define LINK_REG_DCPCTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ -#define LINK_REG_DCPCTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_SUREQ_Pos (14UL) /* SUREQ (Bit 14) */ -#define LINK_REG_DCPCTR_SUREQ_Msk (0x4000UL) /* SUREQ (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_SUREQCLR_Pos (11UL) /* SUREQCLR (Bit 11) */ -#define LINK_REG_DCPCTR_SUREQCLR_Msk (0x800UL) /* SUREQCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ -#define LINK_REG_DCPCTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ -#define LINK_REG_DCPCTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ -#define LINK_REG_DCPCTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ -#define LINK_REG_DCPCTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_CCPL_Pos (2UL) /* CCPL (Bit 2) */ -#define LINK_REG_DCPCTR_CCPL_Msk (0x4UL) /* CCPL (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_PID_Pos (0UL) /* PID (Bit 0) */ -#define LINK_REG_DCPCTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ - -// PIPESEL -#define LINK_REG_PIPESEL_PIPESEL_Pos (0UL) /* PIPESEL (Bit 0) */ -#define LINK_REG_PIPESEL_PIPESEL_Msk (0xfUL) /* PIPESEL (Bitfield-Mask: 0x0f) */ - -// PIPECFG -#define LINK_REG_PIPECFG_TYPE_Pos (14UL) /* TYPE (Bit 14) */ -#define LINK_REG_PIPECFG_TYPE_Msk (0xc000UL) /* TYPE (Bitfield-Mask: 0x03) */ -#define LINK_REG_PIPECFG_BFRE_Pos (10UL) /* BFRE (Bit 10) */ -#define LINK_REG_PIPECFG_BFRE_Msk (0x400UL) /* BFRE (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPECFG_DBLB_Pos (9UL) /* DBLB (Bit 9) */ -#define LINK_REG_PIPECFG_DBLB_Msk (0x200UL) /* DBLB (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPECFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ -#define LINK_REG_PIPECFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPECFG_DIR_Pos (4UL) /* DIR (Bit 4) */ -#define LINK_REG_PIPECFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPECFG_EPNUM_Pos (0UL) /* EPNUM (Bit 0) */ -#define LINK_REG_PIPECFG_EPNUM_Msk (0xfUL) /* EPNUM (Bitfield-Mask: 0x0f) */ - -// PIPEMAXP -#define LINK_REG_PIPEMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ -#define LINK_REG_PIPEMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ -#define LINK_REG_PIPEMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ -#define LINK_REG_PIPEMAXP_MXPS_Msk (0x1ffUL) /* MXPS (Bitfield-Mask: 0x1ff) */ - -// PIPEPERI -#define LINK_REG_PIPEPERI_IFIS_Pos (12UL) /* IFIS (Bit 12) */ -#define LINK_REG_PIPEPERI_IFIS_Msk (0x1000UL) /* IFIS (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPEPERI_IITV_Pos (0UL) /* IITV (Bit 0) */ -#define LINK_REG_PIPEPERI_IITV_Msk (0x7UL) /* IITV (Bitfield-Mask: 0x07) */ - -// PIPE_CTR -#define LINK_REG_PIPE_CTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ -#define LINK_REG_PIPE_CTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_INBUFM_Pos (14UL) /* INBUFM (Bit 14) */ -#define LINK_REG_PIPE_CTR_INBUFM_Msk (0x4000UL) /* INBUFM (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_CSCLR_Pos (13UL) /* CSCLR (Bit 13) */ -#define LINK_REG_PIPE_CTR_CSCLR_Msk (0x2000UL) /* CSCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_CSSTS_Pos (12UL) /* CSSTS (Bit 12) */ -#define LINK_REG_PIPE_CTR_CSSTS_Msk (0x1000UL) /* CSSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_ATREPM_Pos (10UL) /* ATREPM (Bit 10) */ -#define LINK_REG_PIPE_CTR_ATREPM_Msk (0x400UL) /* ATREPM (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_ACLRM_Pos (9UL) /* ACLRM (Bit 9) */ -#define LINK_REG_PIPE_CTR_ACLRM_Msk (0x200UL) /* ACLRM (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ -#define LINK_REG_PIPE_CTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ -#define LINK_REG_PIPE_CTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ -#define LINK_REG_PIPE_CTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ -#define LINK_REG_PIPE_CTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_PID_Pos (0UL) /* PID (Bit 0) */ -#define LINK_REG_PIPE_CTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ - -// DEVADD -#define LINK_REG_DEVADD_UPPHUB_Pos (11UL) /* UPPHUB (Bit 11) */ -#define LINK_REG_DEVADD_UPPHUB_Msk (0x7800UL) /* UPPHUB (Bitfield-Mask: 0x0f) */ -#define LINK_REG_DEVADD_HUBPORT_Pos (8UL) /* HUBPORT (Bit 8) */ -#define LINK_REG_DEVADD_HUBPORT_Msk (0x700UL) /* HUBPORT (Bitfield-Mask: 0x07) */ -#define LINK_REG_DEVADD_USBSPD_Pos (6UL) /* USBSPD (Bit 6) */ -#define LINK_REG_DEVADD_USBSPD_Msk (0xc0UL) /* USBSPD (Bitfield-Mask: 0x03) */ - -// USBBCCTRL0 -#define LINK_REG_USBBCCTRL0_PDDETSTS0_Pos (9UL) /* PDDETSTS0 (Bit 9) */ -#define LINK_REG_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /* PDDETSTS0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /* CHGDETSTS0 (Bit 8) */ -#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /* CHGDETSTS0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_BATCHGE0_Pos (7UL) /* BATCHGE0 (Bit 7) */ -#define LINK_REG_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /* BATCHGE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_VDMSRCE0_Pos (5UL) /* VDMSRCE0 (Bit 5) */ -#define LINK_REG_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /* VDMSRCE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_IDPSINKE0_Pos (4UL) /* IDPSINKE0 (Bit 4) */ -#define LINK_REG_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /* IDPSINKE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_VDPSRCE0_Pos (3UL) /* VDPSRCE0 (Bit 3) */ -#define LINK_REG_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /* VDPSRCE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_IDMSINKE0_Pos (2UL) /* IDMSINKE0 (Bit 2) */ -#define LINK_REG_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /* IDMSINKE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_IDPSRCE0_Pos (1UL) /* IDPSRCE0 (Bit 1) */ -#define LINK_REG_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /* IDPSRCE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_RPDME0_Pos (0UL) /* RPDME0 (Bit 0) */ -#define LINK_REG_USBBCCTRL0_RPDME0_Msk (0x1UL) /* RPDME0 (Bitfield-Mask: 0x01) */ - -// UCKSEL -#define LINK_REG_UCKSEL_UCKSELC_Pos (0UL) /* UCKSELC (Bit 0) */ -#define LINK_REG_UCKSEL_UCKSELC_Msk (0x1UL) /* UCKSELC (Bitfield-Mask: 0x01) */ - -// USBMC -#define LINK_REG_USBMC_VDCEN_Pos (7UL) /* VDCEN (Bit 7) */ -#define LINK_REG_USBMC_VDCEN_Msk (0x80UL) /* VDCEN (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBMC_VDDUSBE_Pos (0UL) /* VDDUSBE (Bit 0) */ -#define LINK_REG_USBMC_VDDUSBE_Msk (0x1UL) /* VDDUSBE (Bitfield-Mask: 0x01) */ - -// PHYSLEW -#define LINK_REG_PHYSLEW_SLEWF01_Pos (3UL) /* SLEWF01 (Bit 3) */ -#define LINK_REG_PHYSLEW_SLEWF01_Msk (0x8UL) /* SLEWF01 (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSLEW_SLEWF00_Pos (2UL) /* SLEWF00 (Bit 2) */ -#define LINK_REG_PHYSLEW_SLEWF00_Msk (0x4UL) /* SLEWF00 (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSLEW_SLEWR01_Pos (1UL) /* SLEWR01 (Bit 1) */ -#define LINK_REG_PHYSLEW_SLEWR01_Msk (0x2UL) /* SLEWR01 (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSLEW_SLEWR00_Pos (0UL) /* SLEWR00 (Bit 0) */ -#define LINK_REG_PHYSLEW_SLEWR00_Msk (0x1UL) /* SLEWR00 (Bitfield-Mask: 0x01) */ - -// LPCTRL -#define LINK_REG_LPCTRL_HWUPM_Pos (7UL) /* HWUPM (Bit 7) */ -#define LINK_REG_LPCTRL_HWUPM_Msk (0x80UL) /* HWUPM (Bitfield-Mask: 0x01) */ - -// LPSTS -#define LINK_REG_LPSTS_SUSPENDM_Pos (14UL) /* SUSPENDM (Bit 14) */ -#define LINK_REG_LPSTS_SUSPENDM_Msk (0x4000UL) /* SUSPENDM (Bitfield-Mask: 0x01) */ - -// BCCTRL -#define LINK_REG_BCCTRL_PDDETSTS_Pos (9UL) /* PDDETSTS (Bit 9) */ -#define LINK_REG_BCCTRL_PDDETSTS_Msk (0x200UL) /* PDDETSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_CHGDETSTS_Pos (8UL) /* CHGDETSTS (Bit 8) */ -#define LINK_REG_BCCTRL_CHGDETSTS_Msk (0x100UL) /* CHGDETSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_DCPMODE_Pos (5UL) /* DCPMODE (Bit 5) */ -#define LINK_REG_BCCTRL_DCPMODE_Msk (0x20UL) /* DCPMODE (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_VDMSRCE_Pos (4UL) /* VDMSRCE (Bit 4) */ -#define LINK_REG_BCCTRL_VDMSRCE_Msk (0x10UL) /* VDMSRCE (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_IDPSINKE_Pos (3UL) /* IDPSINKE (Bit 3) */ -#define LINK_REG_BCCTRL_IDPSINKE_Msk (0x8UL) /* IDPSINKE (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_VDPSRCE_Pos (2UL) /* VDPSRCE (Bit 2) */ -#define LINK_REG_BCCTRL_VDPSRCE_Msk (0x4UL) /* VDPSRCE (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_IDMSINKE_Pos (1UL) /* IDMSINKE (Bit 1) */ -#define LINK_REG_BCCTRL_IDMSINKE_Msk (0x2UL) /* IDMSINKE (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_IDPSRCE_Pos (0UL) /* IDPSRCE (Bit 0) */ -#define LINK_REG_BCCTRL_IDPSRCE_Msk (0x1UL) /* IDPSRCE (Bitfield-Mask: 0x01) */ - -// PL1CTRL1 -#define LINK_REG_PL1CTRL1_L1EXTMD_Pos (14UL) /* L1EXTMD (Bit 14) */ -#define LINK_REG_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /* L1EXTMD (Bitfield-Mask: 0x01) */ -#define LINK_REG_PL1CTRL1_HIRDTHR_Pos (8UL) /* HIRDTHR (Bit 8) */ -#define LINK_REG_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /* HIRDTHR (Bitfield-Mask: 0x0f) */ -#define LINK_REG_PL1CTRL1_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ -#define LINK_REG_PL1CTRL1_DVSQ_Msk (0xf0UL) /* DVSQ (Bitfield-Mask: 0x0f) */ -#define LINK_REG_PL1CTRL1_L1NEGOMD_Pos (3UL) /* L1NEGOMD (Bit 3) */ -#define LINK_REG_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /* L1NEGOMD (Bitfield-Mask: 0x01) */ -#define LINK_REG_PL1CTRL1_L1RESPMD_Pos (1UL) /* L1RESPMD (Bit 1) */ -#define LINK_REG_PL1CTRL1_L1RESPMD_Msk (0x6UL) /* L1RESPMD (Bitfield-Mask: 0x03) */ -#define LINK_REG_PL1CTRL1_L1RESPEN_Pos (0UL) /* L1RESPEN (Bit 0) */ -#define LINK_REG_PL1CTRL1_L1RESPEN_Msk (0x1UL) /* L1RESPEN (Bitfield-Mask: 0x01) */ - -// PL1CTRL2 -#define LINK_REG_PL1CTRL2_RWEMON_Pos (12UL) /* RWEMON (Bit 12) */ -#define LINK_REG_PL1CTRL2_RWEMON_Msk (0x1000UL) /* RWEMON (Bitfield-Mask: 0x01) */ -#define LINK_REG_PL1CTRL2_HIRDMON_Pos (8UL) /* HIRDMON (Bit 8) */ -#define LINK_REG_PL1CTRL2_HIRDMON_Msk (0xf00UL) /* HIRDMON (Bitfield-Mask: 0x0f) */ - -// HL1CTRL1 -#define LINK_REG_HL1CTRL1_L1STATUS_Pos (1UL) /* L1STATUS (Bit 1) */ -#define LINK_REG_HL1CTRL1_L1STATUS_Msk (0x6UL) /* L1STATUS (Bitfield-Mask: 0x03) */ -#define LINK_REG_HL1CTRL1_L1REQ_Pos (0UL) /* L1REQ (Bit 0) */ -#define LINK_REG_HL1CTRL1_L1REQ_Msk (0x1UL) /* L1REQ (Bitfield-Mask: 0x01) */ - -// HL1CTRL2 -#define LINK_REG_HL1CTRL2_BESL_Pos (15UL) /* BESL (Bit 15) */ -#define LINK_REG_HL1CTRL2_BESL_Msk (0x8000UL) /* BESL (Bitfield-Mask: 0x01) */ -#define LINK_REG_HL1CTRL2_L1RWE_Pos (12UL) /* L1RWE (Bit 12) */ -#define LINK_REG_HL1CTRL2_L1RWE_Msk (0x1000UL) /* L1RWE (Bitfield-Mask: 0x01) */ -#define LINK_REG_HL1CTRL2_HIRD_Pos (8UL) /* HIRD (Bit 8) */ -#define LINK_REG_HL1CTRL2_HIRD_Msk (0xf00UL) /* HIRD (Bitfield-Mask: 0x0f) */ -#define LINK_REG_HL1CTRL2_L1ADDR_Pos (0UL) /* L1ADDR (Bit 0) */ -#define LINK_REG_HL1CTRL2_L1ADDR_Msk (0xfUL) /* L1ADDR (Bitfield-Mask: 0x0f) */ - -// DPUSR0R -#define LINK_REG_DPUSR0R_DVBSTSHM_Pos (23UL) /* DVBSTSHM (Bit 23) */ -#define LINK_REG_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_DOVCBHM_Pos (21UL) /* DOVCBHM (Bit 21) */ -#define LINK_REG_DPUSR0R_DOVCBHM_Msk (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_DOVCAHM_Pos (20UL) /* DOVCAHM (Bit 20) */ -#define LINK_REG_DPUSR0R_DOVCAHM_Msk (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */ - -// DPUSR1R -#define LINK_REG_DPUSR1R_DVBSTSH_Pos (23UL) /* DVBSTSH (Bit 23) */ -#define LINK_REG_DPUSR1R_DVBSTSH_Msk (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_DOVCBH_Pos (21UL) /* DOVCBH (Bit 21) */ -#define LINK_REG_DPUSR1R_DOVCBH_Msk (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_DOVCAH_Pos (20UL) /* DOVCAH (Bit 20) */ -#define LINK_REG_DPUSR1R_DOVCAH_Msk (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_DVBSTSHE_Pos (7UL) /* DVBSTSHE (Bit 7) */ -#define LINK_REG_DPUSR1R_DVBSTSHE_Msk (0x80UL) /* DVBSTSHE (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_DOVCBHE_Pos (5UL) /* DOVCBHE (Bit 5) */ -#define LINK_REG_DPUSR1R_DOVCBHE_Msk (0x20UL) /* DOVCBHE (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_DOVCAHE_Pos (4UL) /* DOVCAHE (Bit 4) */ -#define LINK_REG_DPUSR1R_DOVCAHE_Msk (0x10UL) /* DOVCAHE (Bitfield-Mask: 0x01) */ - -// DPUSR2R -#define LINK_REG_DPUSR2R_DMINTE_Pos (9UL) /* DMINTE (Bit 9) */ -#define LINK_REG_DPUSR2R_DMINTE_Msk (0x200UL) /* DMINTE (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR2R_DPINTE_Pos (8UL) /* DPINTE (Bit 8) */ -#define LINK_REG_DPUSR2R_DPINTE_Msk (0x100UL) /* DPINTE (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR2R_DMVAL_Pos (5UL) /* DMVAL (Bit 5) */ -#define LINK_REG_DPUSR2R_DMVAL_Msk (0x20UL) /* DMVAL (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR2R_DPVAL_Pos (4UL) /* DPVAL (Bit 4) */ -#define LINK_REG_DPUSR2R_DPVAL_Msk (0x10UL) /* DPVAL (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR2R_DMINT_Pos (1UL) /* DMINT (Bit 1) */ -#define LINK_REG_DPUSR2R_DMINT_Msk (0x2UL) /* DMINT (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR2R_DPINT_Pos (0UL) /* DPINT (Bit 0) */ -#define LINK_REG_DPUSR2R_DPINT_Msk (0x1UL) /* DPINT (Bitfield-Mask: 0x01) */ - -// DPUSRCR -#define LINK_REG_DPUSRCR_FIXPHYPD_Pos (1UL) /* FIXPHYPD (Bit 1) */ -#define LINK_REG_DPUSRCR_FIXPHYPD_Msk (0x2UL) /* FIXPHYPD (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSRCR_FIXPHY_Pos (0UL) /* FIXPHY (Bit 0) */ -#define LINK_REG_DPUSRCR_FIXPHY_Msk (0x1UL) /* FIXPHY (Bitfield-Mask: 0x01) */ - -// DPUSR0R_FS -#define LINK_REG_DPUSR0R_FS_DVBSTS0_Pos (23UL) /* DVBSTS0 (Bit 23) */ -#define LINK_REG_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_DOVCB0_Pos (21UL) /* DOVCB0 (Bit 21) */ -#define LINK_REG_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_DOVCA0_Pos (20UL) /* DOVCA0 (Bit 20) */ -#define LINK_REG_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_DM0_Pos (17UL) /* DM0 (Bit 17) */ -#define LINK_REG_DPUSR0R_FS_DM0_Msk (0x20000UL) /* DM0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_DP0_Pos (16UL) /* DP0 (Bit 16) */ -#define LINK_REG_DPUSR0R_FS_DP0_Msk (0x10000UL) /* DP0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_FIXPHY0_Pos (4UL) /* FIXPHY0 (Bit 4) */ -#define LINK_REG_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /* FIXPHY0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_DRPD0_Pos (3UL) /* DRPD0 (Bit 3) */ -#define LINK_REG_DPUSR0R_FS_DRPD0_Msk (0x8UL) /* DRPD0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_RPUE0_Pos (1UL) /* RPUE0 (Bit 1) */ -#define LINK_REG_DPUSR0R_FS_RPUE0_Msk (0x2UL) /* RPUE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_SRPC0_Pos (0UL) /* SRPC0 (Bit 0) */ -#define LINK_REG_DPUSR0R_FS_SRPC0_Msk (0x1UL) /* SRPC0 (Bitfield-Mask: 0x01) */ - -// DPUSR1R_FS -#define LINK_REG_DPUSR1R_FS_DVBINT0_Pos (23UL) /* DVBINT0 (Bit 23) */ -#define LINK_REG_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /* DOVRCRB0 (Bit 21) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /* DOVRCRA0 (Bit 20) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DMINT0_Pos (17UL) /* DMINT0 (Bit 17) */ -#define LINK_REG_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /* DMINT0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DPINT0_Pos (16UL) /* DPINT0 (Bit 16) */ -#define LINK_REG_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /* DPINT0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DVBSE0_Pos (7UL) /* DVBSE0 (Bit 7) */ -#define LINK_REG_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /* DVBSE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /* DOVRCRBE0 (Bit 5) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /* DOVRCRBE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /* DOVRCRAE0 (Bit 4) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /* DOVRCRAE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DMINTE0_Pos (1UL) /* DMINTE0 (Bit 1) */ -#define LINK_REG_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /* DMINTE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DPINTE0_Pos (0UL) /* DPINTE0 (Bit 0) */ -#define LINK_REG_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /* DPINTE0 (Bitfield-Mask: 0x01) */ - -/*--------------------------------------------------------------------*/ -/* Register Bit Utils */ -/*--------------------------------------------------------------------*/ -#define LINK_REG_PIPE_CTR_PID_NAK (0U << LINK_REG_PIPE_CTR_PID_Pos) /* NAK response */ -#define LINK_REG_PIPE_CTR_PID_BUF (1U << LINK_REG_PIPE_CTR_PID_Pos) /* BUF response (depends buffer state) */ -#define LINK_REG_PIPE_CTR_PID_STALL (2U << LINK_REG_PIPE_CTR_PID_Pos) /* STALL response */ - -#define LINK_REG_DVSTCTR0_RHST_LS (1U << LINK_REG_DVSTCTR0_RHST_Pos) /* Low-speed connection */ -#define LINK_REG_DVSTCTR0_RHST_FS (2U << LINK_REG_DVSTCTR0_RHST_Pos) /* Full-speed connection */ - -#define LINK_REG_DEVADD_USBSPD_LS (1U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Low-speed */ -#define LINK_REG_DEVADD_USBSPD_FS (2U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Full-speed */ - -#define LINK_REG_CFIFOSEL_ISEL_WRITE (1U << LINK_REG_CFIFOSEL_ISEL_Pos) /* FIFO write AKA TX*/ - -#define LINK_REG_FIFOSEL_BIGEND (1U << LINK_REG_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */ -#define LINK_REG_FIFOSEL_MBW_8BIT (0U << LINK_REG_CFIFOSEL_MBW_Pos) /* 8-bit width */ -#define LINK_REG_FIFOSEL_MBW_16BIT (1U << LINK_REG_CFIFOSEL_MBW_Pos) /* 16-bit width */ - -#define LINK_REG_INTSTS0_CTSQ_CTRL_RDATA (1U << LINK_REG_INTSTS0_CTSQ_Pos) - -#define LINK_REG_INTSTS0_DVSQ_STATE_DEF (1U << LINK_REG_INTSTS0_DVSQ_Pos) /* Default state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_ADDR (2U << LINK_REG_INTSTS0_DVSQ_Pos) /* Address state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP0 (4U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP1 (5U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP2 (6U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP3 (7U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ - -#define LINK_REG_PIPECFG_TYPE_BULK (1U << LINK_REG_PIPECFG_TYPE_Pos) -#define LINK_REG_PIPECFG_TYPE_INT (2U << LINK_REG_PIPECFG_TYPE_Pos) -#define LINK_REG_PIPECFG_TYPE_ISO (3U << LINK_REG_PIPECFG_TYPE_Pos) - -//--------------------------------------------------------------------+ -// Static Assert -//--------------------------------------------------------------------+ - -TU_VERIFY_STATIC(sizeof(LINK_REG_PIPE_TR_t) == 4, "incorrect size"); - -TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSCFG ) == 0x00000000, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BUSWAIT ) == 0x00000002, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSSTS0 ) == 0x00000004, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PLLSTA ) == 0x00000006, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DVSTCTR0 ) == 0x00000008, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, TESTMODE ) == 0x0000000C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFO ) == 0x00000014, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFO ) == 0x00000018, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFO ) == 0x0000001C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOSEL ) == 0x00000020, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOCTR ) == 0x00000022, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOSEL ) == 0x00000028, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOCTR ) == 0x0000002A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOSEL ) == 0x0000002C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOCTR ) == 0x0000002E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB0 ) == 0x00000030, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB1 ) == 0x00000032, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYENB ) == 0x00000036, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYENB ) == 0x00000038, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPENB ) == 0x0000003A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, SOFCFG ) == 0x0000003C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSET ) == 0x0000003E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS0 ) == 0x00000040, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS1 ) == 0x00000042, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYSTS ) == 0x00000046, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYSTS ) == 0x00000048, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPSTS ) == 0x0000004A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, FRMNUM ) == 0x0000004C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, UFRMNUM ) == 0x0000004E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBADDR ) == 0x00000050, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBREQ ) == 0x00000054, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBVAL ) == 0x00000056, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBINDX ) == 0x00000058, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBLENG ) == 0x0000005A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCFG ) == 0x0000005C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPMAXP ) == 0x0000005E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCTR ) == 0x00000060, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPESEL ) == 0x00000064, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPECFG ) == 0x00000068, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEMAXP ) == 0x0000006C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEPERI ) == 0x0000006E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_CTR ) == 0x00000070, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_TR ) == 0x00000090, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBBCCTRL0 ) == 0x000000B0, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, UCKSEL ) == 0x000000C4, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBMC ) == 0x000000CC, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DEVADD ) == 0x000000D0, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSLEW ) == 0x000000F0, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPCTRL ) == 0x00000100, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPSTS ) == 0x00000102, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BCCTRL ) == 0x00000140, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL1 ) == 0x00000144, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL2 ) == 0x00000146, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL1 ) == 0x00000148, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL2 ) == 0x0000014A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R ) == 0x00000160, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R ) == 0x00000164, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR2R ) == 0x00000168, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSRCR ) == 0x0000016A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R_FS ) == 0x00000400, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect offset"); - -#ifdef __cplusplus -} -#endif - -#endif /* _TUSB_LINK_TYPE_H_ */ diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c new file mode 100644 index 000000000..ec9caab2c --- /dev/null +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -0,0 +1,868 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Koji Kitayama + * Portions copyrighted (c) 2021 Roland Winistoerfer + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) +// We disable SOF for now until needed later on +#define USE_SOF 0 + +#if CFG_TUD_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \ + TU_CHECK_MCU(OPT_MCU_RAXXX)) + +#include "device/dcd.h" +#include "rusb2_type.h" + +#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) + #include "rusb2_rx.h" +#elif TU_CHECK_MCU(OPT_MCU_RAXXX) + #include "rusb2_ra.h" +#else + #error "Unsupported MCU" +#endif + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +/* LINK core registers */ +#if defined(__CCRX__) +#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE) +#else +#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE) +#endif + +/* Start of definition of packed structs (used by the CCRX toolchain) */ +TU_ATTR_PACKED_BEGIN +TU_ATTR_BIT_FIELD_ORDER_BEGIN + +typedef struct TU_ATTR_PACKED { + union { + struct { + uint16_t : 8; + uint16_t TRCLR: 1; + uint16_t TRENB: 1; + uint16_t : 0; + }; + uint16_t TRE; + }; + uint16_t TRN; +} reg_pipetre_t; + +typedef union TU_ATTR_PACKED { + struct { + volatile uint16_t u8: 8; + volatile uint16_t : 0; + }; + volatile uint16_t u16; +} hw_fifo_t; + +typedef struct TU_ATTR_PACKED +{ + void *buf; /* the start address of a transfer data buffer */ + uint16_t length; /* the number of bytes in the buffer */ + uint16_t remaining; /* the number of bytes remaining in the buffer */ + struct { + uint32_t ep : 8; /* an assigned endpoint address */ + uint32_t ff : 1; /* `buf` is TU_FUFO or POD */ + uint32_t : 0; + }; +} pipe_state_t; + +TU_ATTR_PACKED_END // End of definition of packed structs (used by the CCRX toolchain) +TU_ATTR_BIT_FIELD_ORDER_END + +typedef struct +{ + pipe_state_t pipe[10]; + uint8_t ep[2][16]; /* a lookup table for a pipe index from an endpoint address */ +} dcd_data_t; + +//--------------------------------------------------------------------+ +// INTERNAL OBJECT & FUNCTION DECLARATION +//--------------------------------------------------------------------+ +static dcd_data_t _dcd; + +static unsigned find_pipe(unsigned xfer) +{ + switch (xfer) { + case TUSB_XFER_ISOCHRONOUS: + for (int i = 1; i <= 2; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + break; + case TUSB_XFER_BULK: + for (int i = 3; i <= 5; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + for (int i = 1; i <= 1; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + break; + case TUSB_XFER_INTERRUPT: + for (int i = 6; i <= 9; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + break; + default: + /* No support for control transfer */ + break; + } + return 0; +} + +static volatile uint16_t* get_pipectr(unsigned num) +{ + if (num) { + return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]); + } else { + return (volatile uint16_t*)&(LINK_REG->DCPCTR); + } +} + +static volatile reg_pipetre_t* get_pipetre(unsigned num) +{ + volatile reg_pipetre_t* tre = NULL; + if ((1 <= num) && (num <= 5)) { + tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E); + } + return tre; +} + +static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr) +{ + (void)rhport; + const unsigned epn = tu_edpt_number(ep_addr); + if (epn) { + const unsigned dir = tu_edpt_dir(ep_addr); + const unsigned num = _dcd.ep[dir][epn]; + return get_pipectr(num); + } else { + return get_pipectr(0); + } +} + +static unsigned edpt0_max_packet_size(void) +{ + return LINK_REG->DCPMAXP_b.MXPS; +} + +static unsigned edpt_max_packet_size(unsigned num) +{ + LINK_REG->PIPESEL = num; + return LINK_REG->PIPEMAXP; +} + +static inline void pipe_wait_for_ready(unsigned num) +{ + while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ; + while (!LINK_REG->D0FIFOCTR_b.FRDY) ; +} + +static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) +{ + volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo; + uintptr_t addr = (uintptr_t)buf; + while (len >= 2) { + reg->u16 = *(const uint16_t *)addr; + addr += 2; + len -= 2; + } + if (len) { + reg->u8 = *(const uint8_t *)addr; + ++addr; + } +} + +static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) +{ + uint8_t *p = (uint8_t*)buf; + volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ + while (len--) *p++ = *reg; +} + +static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) +{ + static const struct { + void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info); + void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n); + void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len); + } ops[] = { + /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet}, + /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, + }; + tu_fifo_buffer_info_t info; + ops[dir].tu_fifo_get_info(f, &info); + unsigned total_len = len; + len = TU_MIN(total_len, info.len_lin); + ops[dir].pipe_read_write(info.ptr_lin, fifo, len); + unsigned rem = total_len - len; + if (rem) { + len = TU_MIN(rem, info.len_wrap); + ops[dir].pipe_read_write(info.ptr_wrap, fifo, len); + rem -= len; + } + ops[dir].tu_fifo_advance(f, total_len - rem); +} + +static bool pipe0_xfer_in(void) +{ + pipe_state_t *pipe = &_dcd.pipe[0]; + const unsigned rem = pipe->remaining; + if (!rem) { + pipe->buf = NULL; + return true; + } + const unsigned mps = edpt0_max_packet_size(); + const unsigned len = TU_MIN(mps, rem); + void *buf = pipe->buf; + if (len) { + if (pipe->ff) { + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->CFIFO, len, TUSB_DIR_IN); + } else { + pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); + pipe->buf = (uint8_t*)buf + len; + } + } + if (len < mps) { + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + } + pipe->remaining = rem - len; + return false; +} + +static bool pipe0_xfer_out(void) +{ + pipe_state_t *pipe = &_dcd.pipe[0]; + const unsigned rem = pipe->remaining; + + const unsigned mps = edpt0_max_packet_size(); + const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN; + const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + void *buf = pipe->buf; + if (len) { + if (pipe->ff) { + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->CFIFO, len, TUSB_DIR_OUT); + } else { + pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); + pipe->buf = (uint8_t*)buf + len; + } + } + if (len < mps) { + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; + } + pipe->remaining = rem - len; + if ((len < mps) || (rem == len)) { + pipe->buf = NULL; + return true; + } + return false; +} + +static bool pipe_xfer_in(unsigned num) +{ + pipe_state_t *pipe = &_dcd.pipe[num]; + const unsigned rem = pipe->remaining; + + if (!rem) { + pipe->buf = NULL; + return true; + } + + LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); + const unsigned mps = edpt_max_packet_size(num); + pipe_wait_for_ready(num); + const unsigned len = TU_MIN(rem, mps); + void *buf = pipe->buf; + if (len) { + if (pipe->ff) { + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->D0FIFO, len, TUSB_DIR_IN); + } else { + pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); + pipe->buf = (uint8_t*)buf + len; + } + } + if (len < mps) { + LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + } + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + pipe->remaining = rem - len; + return false; +} + +static bool pipe_xfer_out(unsigned num) +{ + pipe_state_t *pipe = &_dcd.pipe[num]; + const unsigned rem = pipe->remaining; + + LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT; + const unsigned mps = edpt_max_packet_size(num); + pipe_wait_for_ready(num); + const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN; + const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + void *buf = pipe->buf; + if (len) { + if (pipe->ff) { + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->D0FIFO, len, TUSB_DIR_OUT); + } else { + pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); + pipe->buf = (uint8_t*)buf + len; + } + } + if (len < mps) { + LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; + } + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + pipe->remaining = rem - len; + if ((len < mps) || (rem == len)) { + pipe->buf = NULL; + return NULL != buf; + } + return false; +} + +static void process_setup_packet(uint8_t rhport) +{ + uint16_t setup_packet[4]; + if (0 == (LINK_REG->INTSTS0 & LINK_REG_INTSTS0_VALID_Msk)) return; + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; + setup_packet[0] = tu_le16toh(LINK_REG->USBREQ); + setup_packet[1] = LINK_REG->USBVAL; + setup_packet[2] = LINK_REG->USBINDX; + setup_packet[3] = LINK_REG->USBLENG; + LINK_REG->INTSTS0 = ~((uint16_t)LINK_REG_INTSTS0_VALID_Msk); + dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true); +} + +static void process_status_completion(uint8_t rhport) +{ + uint8_t ep_addr; + /* Check the data stage direction */ + if (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) { + /* IN transfer. */ + ep_addr = tu_edpt_addr(0, TUSB_DIR_IN); + } else { + /* OUT transfer. */ + ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT); + } + dcd_event_xfer_complete(rhport, ep_addr, 0, XFER_RESULT_SUCCESS, true); +} + +static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) +{ + /* configure fifo direction and access unit settings */ + if (ep_addr) { /* IN, 2 bytes */ + LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT | + (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); + while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ; + } else { /* OUT, a byte */ + LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT; + while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ; + } + + pipe_state_t *pipe = &_dcd.pipe[0]; + pipe->ff = buffer_type; + pipe->length = total_bytes; + pipe->remaining = total_bytes; + if (total_bytes) { + pipe->buf = buffer; + if (ep_addr) { /* IN */ + TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80)); + pipe0_xfer_in(); + } + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF; + } else { + /* ZLP */ + pipe->buf = NULL; + LINK_REG->DCPCTR = LINK_REG_DCPCTR_CCPL_Msk | LINK_REG_PIPE_CTR_PID_BUF; + } + return true; +} + +static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) +{ + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir = tu_edpt_dir(ep_addr); + const unsigned num = _dcd.ep[dir][epn]; + + TU_ASSERT(num); + + pipe_state_t *pipe = &_dcd.pipe[num]; + pipe->ff = buffer_type; + pipe->buf = buffer; + pipe->length = total_bytes; + pipe->remaining = total_bytes; + if (dir) { /* IN */ + if (total_bytes) { + pipe_xfer_in(num); + } else { /* ZLP */ + LINK_REG->D0FIFOSEL = num; + pipe_wait_for_ready(num); + LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + } + } else { +#if defined(__CCRX__) + __evenaccess volatile reg_pipetre_t *pt = get_pipetre(num); +#else + volatile reg_pipetre_t *pt = get_pipetre(num); +#endif + if (pt) { + const unsigned mps = edpt_max_packet_size(num); + volatile uint16_t *ctr = get_pipectr(num); + if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK; + pt->TRE = TU_BIT(8); + pt->TRN = (total_bytes + mps - 1) / mps; + pt->TRENB = 1; + *ctr = LINK_REG_PIPE_CTR_PID_BUF; + } + } + // TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type); + return true; +} + +static bool process_edpt_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) +{ + const unsigned epn = tu_edpt_number(ep_addr); + if (0 == epn) { + return process_pipe0_xfer(buffer_type, ep_addr, buffer, total_bytes); + } else { + return process_pipe_xfer(buffer_type, ep_addr, buffer, total_bytes); + } +} + +static void process_pipe0_bemp(uint8_t rhport) +{ + bool completed = pipe0_xfer_in(); + if (completed) { + pipe_state_t *pipe = &_dcd.pipe[0]; + dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN), + pipe->length, XFER_RESULT_SUCCESS, true); + } +} + +static void process_pipe_brdy(uint8_t rhport, unsigned num) +{ + pipe_state_t *pipe = &_dcd.pipe[num]; + const unsigned dir = tu_edpt_dir(pipe->ep); + bool completed; + + if (dir) { /* IN */ + completed = pipe_xfer_in(num); + } else { + if (num) { + completed = pipe_xfer_out(num); + } else { + completed = pipe0_xfer_out(); + } + } + if (completed) { + dcd_event_xfer_complete(rhport, pipe->ep, + pipe->length - pipe->remaining, + XFER_RESULT_SUCCESS, true); + // TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining); + } +} + +static void process_bus_reset(uint8_t rhport) +{ + LINK_REG->BEMPENB = 1; + LINK_REG->BRDYENB = 1; + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + LINK_REG->D1FIFOSEL = 0; + while (LINK_REG->D1FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&LINK_REG->PIPE_CTR[0])); + volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&LINK_REG->PIPE_TR[0].E)); + for (int i = 1; i <= 5; ++i) { + LINK_REG->PIPESEL = i; + LINK_REG->PIPECFG = 0; + *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk; + *ctr = 0; + ++ctr; + *tre = TU_BIT(8); + tre += 2; + } + for (int i = 6; i <= 9; ++i) { + LINK_REG->PIPESEL = i; + LINK_REG->PIPECFG = 0; + *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk; + *ctr = 0; + ++ctr; + } + tu_varclr(&_dcd); + dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); +} + +static void process_set_address(uint8_t rhport) +{ + const uint32_t addr = LINK_REG->USBADDR_b.USBADDR; + if (!addr) return; + const tusb_control_request_t setup_packet = { +#if defined(__CCRX__) + .bmRequestType = { 0 }, /* Note: CCRX needs the braces over this struct member */ +#else + .bmRequestType = 0, +#endif + .bRequest = TUSB_REQ_SET_ADDRESS, + .wValue = addr, + .wIndex = 0, + .wLength = 0, + }; + dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet, true); +} + +/*------------------------------------------------------------------*/ +/* Device API + *------------------------------------------------------------------*/ + +#if 0 // previously present in the rx driver before generalization +static uint32_t disable_interrupt(void) +{ + uint32_t pswi; +#if defined(__CCRX__) + pswi = get_psw() & 0x010000; + clrpsw_i(); +#else + pswi = __builtin_rx_mvfc(0) & 0x010000; + __builtin_rx_clrpsw('I'); +#endif + return pswi; +} + +static void enable_interrupt(uint32_t pswi) +{ +#if defined(__CCRX__) + set_psw(get_psw() | pswi); +#else + __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi); +#endif +} +#endif + +void dcd_init(uint8_t rhport) +{ + (void)rhport; + +#if 0 // previously present in the rx driver before generalization + uint32_t pswi = disable_interrupt(); + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; + MSTP(USB0) = 0; + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; + enable_interrupt(pswi); +#endif + + LINK_REG->SYSCFG_b.SCKE = 1; + while (!LINK_REG->SYSCFG_b.SCKE) ; + LINK_REG->SYSCFG_b.DRPD = 0; + LINK_REG->SYSCFG_b.DCFM = 0; + LINK_REG->SYSCFG_b.USBE = 1; + + // MCU specific PHY init + link_phy_init(); + + LINK_REG->PHYSLEW = 0x5; + LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */ + + /* Setup default control pipe */ + LINK_REG->DCPMAXP_b.MXPS = 64; + LINK_REG->INTENB0 = LINK_REG_INTSTS0_VBINT_Msk | LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk | + LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_CTRT_Msk | (USE_SOF ? LINK_REG_INTSTS0_SOFR_Msk : 0) | + LINK_REG_INTSTS0_RESM_Msk; + LINK_REG->BEMPENB = 1; + LINK_REG->BRDYENB = 1; + + if (LINK_REG->INTSTS0_b.VBSTS) { + dcd_connect(rhport); + } +} + +void dcd_int_enable(uint8_t rhport) +{ + link_int_enable(rhport); +} + +void dcd_int_disable(uint8_t rhport) +{ + link_int_disable(rhport); +} + +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) +{ + (void)rhport; + (void)dev_addr; +} + +void dcd_remote_wakeup(uint8_t rhport) +{ + (void)rhport; + LINK_REG->DVSTCTR0_b.WKUP = 1; +} + +void dcd_connect(uint8_t rhport) +{ + (void)rhport; + LINK_REG->SYSCFG_b.DPRPU = 1; +} + +void dcd_disconnect(uint8_t rhport) +{ + (void)rhport; + LINK_REG->SYSCFG_b.DPRPU = 0; +} + +void dcd_sof_enable(uint8_t rhport, bool en) +{ + (void) rhport; + (void) en; + + // TODO implement later +} + +//--------------------------------------------------------------------+ +// Endpoint API +//--------------------------------------------------------------------+ +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) +{ + (void)rhport; + + const unsigned ep_addr = ep_desc->bEndpointAddress; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir = tu_edpt_dir(ep_addr); + const unsigned xfer = ep_desc->bmAttributes.xfer; + + const unsigned mps = tu_edpt_packet_size(ep_desc); + if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) { + /* USBa supports up to 256 bytes */ + return false; + } + + const unsigned num = find_pipe(xfer); + if (!num) return false; + _dcd.pipe[num].ep = ep_addr; + _dcd.ep[dir][epn] = num; + + /* setup pipe */ + dcd_int_disable(rhport); + LINK_REG->PIPESEL = num; + LINK_REG->PIPEMAXP = mps; + volatile uint16_t *ctr = get_pipectr(num); + *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk; + *ctr = 0; + unsigned cfg = (dir << 4) | epn; + if (xfer == TUSB_XFER_BULK) { + cfg |= (LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk); + } else if (xfer == TUSB_XFER_INTERRUPT) { + cfg |= LINK_REG_PIPECFG_TYPE_INT; + } else { + cfg |= (LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk); + } + LINK_REG->PIPECFG = cfg; + LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num); + LINK_REG->BRDYENB |= TU_BIT(num); + if (dir || (xfer != TUSB_XFER_BULK)) { + *ctr = LINK_REG_PIPE_CTR_PID_BUF; + } + // TU_LOG1("O %d %x %x\r\n", LINK_REG->PIPESEL, LINK_REG->PIPECFG, LINK_REG->PIPEMAXP); + dcd_int_enable(rhport); + + return true; +} + +void dcd_edpt_close_all(uint8_t rhport) +{ + unsigned i = TU_ARRAY_SIZE(_dcd.pipe); + dcd_int_disable(rhport); + while (--i) { /* Close all pipes except 0 */ + const unsigned ep_addr = _dcd.pipe[i].ep; + if (!ep_addr) continue; + dcd_edpt_close(rhport, ep_addr); + } + dcd_int_enable(rhport); +} + +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir = tu_edpt_dir(ep_addr); + const unsigned num = _dcd.ep[dir][epn]; + + LINK_REG->BRDYENB &= ~TU_BIT(num); + volatile uint16_t *ctr = get_pipectr(num); + *ctr = 0; + LINK_REG->PIPESEL = num; + LINK_REG->PIPECFG = 0; + _dcd.pipe[num].ep = 0; + _dcd.ep[dir][epn] = 0; +} + +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) +{ + bool r; + dcd_int_disable(rhport); + r = process_edpt_xfer(0, ep_addr, buffer, total_bytes); + dcd_int_enable(rhport); + return r; +} + +bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) +{ + // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1 + TU_ASSERT(ff->item_size == 1); + bool r; + dcd_int_disable(rhport); + r = process_edpt_xfer(1, ep_addr, ff, total_bytes); + dcd_int_enable(rhport); + return r; +} + +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) +{ + volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr); + if (!ctr) return; + dcd_int_disable(rhport); + const uint32_t pid = *ctr & 0x3; + *ctr = pid | LINK_REG_PIPE_CTR_PID_STALL; + *ctr = LINK_REG_PIPE_CTR_PID_STALL; + dcd_int_enable(rhport); +} + +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) +{ + volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr); + if (!ctr) return; + dcd_int_disable(rhport); + *ctr = LINK_REG_PIPE_CTR_SQCLR_Msk; + + if (tu_edpt_dir(ep_addr)) { /* IN */ + *ctr = LINK_REG_PIPE_CTR_PID_BUF; + } else { + const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)]; + LINK_REG->PIPESEL = num; + if (LINK_REG->PIPECFG_b.TYPE != 1) { + *ctr = LINK_REG_PIPE_CTR_PID_BUF; + } + } + dcd_int_enable(rhport); +} + +//--------------------------------------------------------------------+ +// ISR +//--------------------------------------------------------------------+ +void dcd_int_handler(uint8_t rhport) +{ + (void)rhport; + + unsigned is0 = LINK_REG->INTSTS0; + /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ + LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_CTRT_Msk | LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_SOFR_Msk | + LINK_REG_INTSTS0_RESM_Msk | LINK_REG_INTSTS0_VBINT_Msk) & is0) | LINK_REG_INTSTS0_VALID_Msk; + if (is0 & LINK_REG_INTSTS0_VBINT_Msk) { + if (LINK_REG->INTSTS0_b.VBSTS) { + dcd_connect(rhport); + } else { + dcd_disconnect(rhport); + } + } + if (is0 & LINK_REG_INTSTS0_RESM_Msk) { + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); +#if (0==USE_SOF) + LINK_REG->INTENB0_b.SOFE = 0; +#endif + } + if ((is0 & LINK_REG_INTSTS0_SOFR_Msk) && LINK_REG->INTENB0_b.SOFE) { + // USBD will exit suspended mode when SOF event is received + dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); +#if (0 == USE_SOF) + LINK_REG->INTENB0_b.SOFE = 0; +#endif + } + if (is0 & LINK_REG_INTSTS0_DVST_Msk) { + switch (is0 & LINK_REG_INTSTS0_DVSQ_Msk) { + case LINK_REG_INTSTS0_DVSQ_STATE_DEF: + process_bus_reset(rhport); + break; + case LINK_REG_INTSTS0_DVSQ_STATE_ADDR: + process_set_address(rhport); + break; + case LINK_REG_INTSTS0_DVSQ_STATE_SUSP0: + case LINK_REG_INTSTS0_DVSQ_STATE_SUSP1: + case LINK_REG_INTSTS0_DVSQ_STATE_SUSP2: + case LINK_REG_INTSTS0_DVSQ_STATE_SUSP3: + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); +#if (0==USE_SOF) + LINK_REG->INTENB0_b.SOFE = 1; +#endif + default: + break; + } + } + if (is0 & LINK_REG_INTSTS0_CTRT_Msk) { + if (is0 & LINK_REG_INTSTS0_CTSQ_CTRL_RDATA) { + /* A setup packet has been received. */ + process_setup_packet(rhport); + } else if (0 == (is0 & LINK_REG_INTSTS0_CTSQ_Msk)) { + /* A ZLP has been sent/received. */ + process_status_completion(rhport); + } + } + if (is0 & LINK_REG_INTSTS0_BEMP_Msk) { + const unsigned s = LINK_REG->BEMPSTS; + LINK_REG->BEMPSTS = 0; + if (s & 1) { + process_pipe0_bemp(rhport); + } + } + if (is0 & LINK_REG_INTSTS0_BRDY_Msk) { + const unsigned m = LINK_REG->BRDYENB; + unsigned s = LINK_REG->BRDYSTS & m; + /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ + LINK_REG->BRDYSTS = ~s; + while (s) { +#if defined(__CCRX__) + static const int Mod37BitPosition[] = { + -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4, + 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5, + 20, 8, 19, 18 + }; + + const unsigned num = Mod37BitPosition[(-s & s) % 37]; +#else + const unsigned num = __builtin_ctz(s); +#endif + process_pipe_brdy(rhport, num); + s &= ~TU_BIT(num); + } + } +} + +#endif diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c new file mode 100644 index 000000000..7d14aad60 --- /dev/null +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -0,0 +1,813 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Koji Kitayama + * Portions copyrighted (c) 2021 Roland Winistoerfer + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUH_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \ + TU_CHECK_MCU(OPT_MCU_RAXXX)) + +#include "host/hcd.h" +#include "rusb2_type.h" + +#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) + #include "rusb2_rx.h" +#elif TU_CHECK_MCU(OPT_MCU_RAXXX) + #include "rusb2_ra.h" +#else + #error "Unsupported MCU" +#endif + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ + +/* LINK core registers */ +#if defined(__CCRX__) +#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE) +#else +#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE) +#endif + +TU_ATTR_PACKED_BEGIN +TU_ATTR_BIT_FIELD_ORDER_BEGIN + +typedef struct TU_ATTR_PACKED { + union { + struct { + uint16_t : 8; + uint16_t TRCLR: 1; + uint16_t TRENB: 1; + uint16_t : 0; + }; + uint16_t TRE; + }; + uint16_t TRN; +} reg_pipetre_t; + +typedef union TU_ATTR_PACKED { + struct { + volatile uint16_t u8: 8; + volatile uint16_t : 0; + }; + volatile uint16_t u16; +} hw_fifo_t; + +typedef struct TU_ATTR_PACKED { + void *buf; /* the start address of a transfer data buffer */ + uint16_t length; /* the number of bytes in the buffer */ + uint16_t remaining; /* the number of bytes remaining in the buffer */ + struct { + uint32_t ep : 8; /* an assigned endpoint address */ + uint32_t dev : 8; /* an assigned device address */ + uint32_t ff : 1; /* `buf` is TU_FUFO or POD */ + uint32_t : 0; + }; +} pipe_state_t; + +TU_ATTR_PACKED_END // End of definition of packed structs (used by the CCRX toolchain) +TU_ATTR_BIT_FIELD_ORDER_END + +typedef struct +{ + bool need_reset; /* The device has not been reset after connection. */ + pipe_state_t pipe[10]; + uint8_t ep[4][2][15]; /* a lookup table for a pipe index from an endpoint address */ + uint8_t ctl_mps[5]; /* EP0 max packet size for each device */ +} hcd_data_t; + +//--------------------------------------------------------------------+ +// INTERNAL OBJECT & FUNCTION DECLARATION +//--------------------------------------------------------------------+ +static hcd_data_t _hcd; + +static unsigned find_pipe(unsigned xfer) +{ + switch (xfer) { + case TUSB_XFER_ISOCHRONOUS: + for (int i = 1; i <= 2; ++i) { + if (0 == _hcd.pipe[i].ep) return i; + } + break; + case TUSB_XFER_BULK: + for (int i = 3; i <= 5; ++i) { + if (0 == _hcd.pipe[i].ep) return i; + } + for (int i = 1; i <= 1; ++i) { + if (0 == _hcd.pipe[i].ep) return i; + } + break; + case TUSB_XFER_INTERRUPT: + for (int i = 6; i <= 9; ++i) { + if (0 == _hcd.pipe[i].ep) return i; + } + break; + default: + /* No support for control transfer */ + break; + } + return 0; +} + +static volatile uint16_t* get_pipectr(unsigned num) +{ + if (num) { + return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]); + } else { + return (volatile uint16_t*)&(LINK_REG->DCPCTR); + } +} + +static volatile reg_pipetre_t* get_pipetre(unsigned num) +{ + volatile reg_pipetre_t* tre = NULL; + if ((1 <= num) && (num <= 5)) { + tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E); + } + return tre; +} + +static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr) +{ + const unsigned epn = tu_edpt_number(ep_addr); + if (epn) { + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1]; + return get_pipectr(num); + } else { + return get_pipectr(0); + } +} + +static unsigned edpt0_max_packet_size(void) +{ + return LINK_REG->DCPMAXP_b.MXPS; +} + +static unsigned edpt_max_packet_size(unsigned num) +{ + LINK_REG->PIPESEL = num; + return LINK_REG->PIPEMAXP_b.MXPS; +} + +static inline void pipe_wait_for_ready(unsigned num) +{ + while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ; + while (!LINK_REG->D0FIFOCTR_b.FRDY) ; +} + +static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) +{ + volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; + uintptr_t addr = (uintptr_t)buf; + while (len >= 2) { + reg->u16 = *(const uint16_t *)addr; + addr += 2; + len -= 2; + } + if (len) { + reg->u8 = *(const uint8_t *)addr; + ++addr; + } +} + +static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) +{ + uint8_t *p = (uint8_t*)buf; + volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ + while (len--) *p++ = *reg; +} + +static bool pipe0_xfer_in(void) +{ + pipe_state_t *pipe = &_hcd.pipe[0]; + const unsigned rem = pipe->remaining; + + const unsigned mps = edpt0_max_packet_size(); + const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN; + const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + void *buf = pipe->buf; + if (len) { + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; + pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); + pipe->buf = (uint8_t*)buf + len; + } + if (len < mps) { + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; + } + pipe->remaining = rem - len; + if ((len < mps) || (rem == len)) { + pipe->buf = NULL; + return true; + } + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF; + return false; +} + +static bool pipe0_xfer_out(void) +{ + pipe_state_t *pipe = &_hcd.pipe[0]; + const unsigned rem = pipe->remaining; + if (!rem) { + pipe->buf = NULL; + return true; + } + const unsigned mps = edpt0_max_packet_size(); + const unsigned len = TU_MIN(mps, rem); + void *buf = pipe->buf; + if (len) { + pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); + pipe->buf = (uint8_t*)buf + len; + } + if (len < mps) { + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + } + pipe->remaining = rem - len; + return false; +} + +static bool pipe_xfer_in(unsigned num) +{ + pipe_state_t *pipe = &_hcd.pipe[num]; + const unsigned rem = pipe->remaining; + + LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT; + const unsigned mps = edpt_max_packet_size(num); + pipe_wait_for_ready(num); + const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN; + const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + void *buf = pipe->buf; + if (len) { + pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); + pipe->buf = (uint8_t*)buf + len; + } + if (len < mps) { + LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; + } + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + pipe->remaining = rem - len; + if ((len < mps) || (rem == len)) { + pipe->buf = NULL; + return NULL != buf; + } + return false; +} + +static bool pipe_xfer_out(unsigned num) +{ + pipe_state_t *pipe = &_hcd.pipe[num]; + const unsigned rem = pipe->remaining; + + if (!rem) { + pipe->buf = NULL; + return true; + } + + LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); + const unsigned mps = edpt_max_packet_size(num); + pipe_wait_for_ready(num); + const unsigned len = TU_MIN(rem, mps); + void *buf = pipe->buf; + if (len) { + pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); + pipe->buf = (uint8_t*)buf + len; + } + if (len < mps) + LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + pipe->remaining = rem - len; + return false; +} + +static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) +{ + (void)dev_addr; + const unsigned dir_in = tu_edpt_dir(ep_addr); + + /* configure fifo direction and access unit settings */ + if (dir_in) { /* IN, a byte */ + LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT; + while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ; + } else { /* OUT, 2 bytes */ + LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT | + (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); + while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ; + } + + pipe_state_t *pipe = &_hcd.pipe[0]; + pipe->ep = ep_addr; + pipe->length = buflen; + pipe->remaining = buflen; + if (buflen) { + pipe->buf = buffer; + if (!dir_in) { /* OUT */ + TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80)); + pipe0_xfer_out(); + } + } else { /* ZLP */ + pipe->buf = NULL; + if (!dir_in) { /* OUT */ + LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + } + if (dir_in == LINK_REG->DCPCFG_b.DIR) { + TU_ASSERT(LINK_REG_PIPE_CTR_PID_NAK == LINK_REG->DCPCTR_b.PID); + LINK_REG->DCPCTR_b.SQSET = 1; + LINK_REG->DCPCFG_b.DIR = dir_in ^ 1; + } + } + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF; + return true; +} + +static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen) +{ + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned num = _hcd.ep[dev_addr - 1][dir_in][epn - 1]; + + TU_ASSERT(num); + + pipe_state_t *pipe = &_hcd.pipe[num]; + pipe->buf = buffer; + pipe->length = buflen; + pipe->remaining = buflen; + if (!dir_in) { /* OUT */ + if (buflen) { + pipe_xfer_out(num); + } else { /* ZLP */ + LINK_REG->D0FIFOSEL = num; + pipe_wait_for_ready(num); + LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + LINK_REG->D0FIFOSEL = 0; + while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + } + } else { + volatile uint16_t *ctr = get_pipectr(num); + volatile reg_pipetre_t *pt = get_pipetre(num); + if (pt) { + const unsigned mps = edpt_max_packet_size(num); + if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK; + pt->TRE = TU_BIT(8); + pt->TRN = (buflen + mps - 1) / mps; + pt->TRENB = 1; + } + *ctr = LINK_REG_PIPE_CTR_PID_BUF; + } + return true; +} + +static bool process_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) +{ + const unsigned epn = tu_edpt_number(ep_addr); + if (0 == epn) { + return process_pipe0_xfer(dev_addr, ep_addr, buffer, buflen); + } else { + return process_pipe_xfer(dev_addr, ep_addr, buffer, buflen); + } +} + +static void process_pipe0_bemp(uint8_t rhport) +{ + (void)rhport; + bool completed = pipe0_xfer_out(); + if (completed) { + pipe_state_t *pipe = &_hcd.pipe[0]; + hcd_event_xfer_complete(pipe->dev, + tu_edpt_addr(0, TUSB_DIR_OUT), + pipe->length - pipe->remaining, + XFER_RESULT_SUCCESS, true); + } +} + +static void process_pipe_nrdy(uint8_t rhport, unsigned num) +{ + (void)rhport; + unsigned result; + uint16_t volatile *ctr = get_pipectr(num); + // TU_LOG1("NRDY %d %x\n", num, *ctr); + switch (*ctr & LINK_REG_PIPE_CTR_PID_Msk) { + default: return; + case LINK_REG_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break; + case LINK_REG_PIPE_CTR_PID_NAK: result = XFER_RESULT_FAILED; break; + } + pipe_state_t *pipe = &_hcd.pipe[num]; + hcd_event_xfer_complete(pipe->dev, pipe->ep, + pipe->length - pipe->remaining, + result, true); +} + +static void process_pipe_brdy(uint8_t rhport, unsigned num) +{ + (void)rhport; + pipe_state_t *pipe = &_hcd.pipe[num]; + const unsigned dir_in = tu_edpt_dir(pipe->ep); + bool completed; + + if (dir_in) { /* IN */ + if (num) { + completed = pipe_xfer_in(num); + } else { + completed = pipe0_xfer_in(); + } + } else { + completed = pipe_xfer_out(num); + } + if (completed) { + hcd_event_xfer_complete(pipe->dev, pipe->ep, + pipe->length - pipe->remaining, + XFER_RESULT_SUCCESS, true); + // TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining); + } +} + +/*------------------------------------------------------------------*/ +/* Host API + *------------------------------------------------------------------*/ + +#if 0 // previously present in the rx driver before generalization +static uint32_t disable_interrupt(void) +{ + uint32_t pswi; +#if defined(__CCRX__) + pswi = get_psw() & 0x010000; + clrpsw_i(); +#else + pswi = __builtin_rx_mvfc(0) & 0x010000; + __builtin_rx_clrpsw('I'); +#endif + return pswi; +} + +static void enable_interrupt(uint32_t pswi) +{ +#if defined(__CCRX__) + set_psw(get_psw() | pswi); +#else + __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi); +#endif +} +#endif + +bool hcd_init(uint8_t rhport) +{ + (void)rhport; + +#if 0 // previously present in the rx driver before generalization + uint32_t pswi = disable_interrupt(); + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; + MSTP(USB0) = 0; + SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; + enable_interrupt(pswi); +#endif + + LINK_REG->SYSCFG_b.SCKE = 1; + while (!LINK_REG->SYSCFG_b.SCKE) ; + LINK_REG->SYSCFG_b.DPRPU = 0; + LINK_REG->SYSCFG_b.DRPD = 0; + LINK_REG->SYSCFG_b.DCFM = 1; + + LINK_REG->DVSTCTR0_b.VBUSEN = 1; + + LINK_REG->SYSCFG_b.DRPD = 1; + for (volatile int i = 0; i < 30000; ++i) ; + LINK_REG->SYSCFG_b.USBE = 1; + + // MCU specific PHY init + link_phy_init(); + + LINK_REG->PHYSLEW = 0x5; + LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */ + + /* Setup default control pipe */ + LINK_REG->DCPCFG = LINK_REG_PIPECFG_SHTNAK_Msk; + LINK_REG->DCPMAXP = 64; + LINK_REG->INTENB0 = LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk; + LINK_REG->INTENB1 = LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk; + LINK_REG->BEMPENB = 1; + LINK_REG->NRDYENB = 1; + LINK_REG->BRDYENB = 1; + + return true; +} + +void hcd_int_enable(uint8_t rhport) +{ + link_int_enable(rhport); +} + +void hcd_int_disable(uint8_t rhport) +{ + link_int_disable(rhport); +} + +uint32_t hcd_frame_number(uint8_t rhport) +{ + (void)rhport; + /* The device must be reset at least once after connection + * in order to start the frame counter. */ + if (_hcd.need_reset) hcd_port_reset(rhport); + return LINK_REG->FRMNUM_b.FRNM; +} + +/*--------------------------------------------------------------------+ + * Port API + *--------------------------------------------------------------------+*/ +bool hcd_port_connect_status(uint8_t rhport) +{ + (void)rhport; + return LINK_REG->INTSTS1_b.ATTCH ? true : false; +} + +void hcd_port_reset(uint8_t rhport) +{ + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; + while (LINK_REG->DCPCTR_b.PBUSY) ; + hcd_int_disable(rhport); + LINK_REG->DVSTCTR0_b.UACT = 0; + if (LINK_REG->DCPCTR_b.SUREQ) { + LINK_REG->DCPCTR_b.SUREQCLR = 1; + } + hcd_int_enable(rhport); + /* Reset should be asserted 10-20ms. */ + LINK_REG->DVSTCTR0_b.USBRST = 1; + for (volatile int i = 0; i < 2400000; ++i) ; + LINK_REG->DVSTCTR0_b.USBRST = 0; + LINK_REG->DVSTCTR0_b.UACT = 1; + _hcd.need_reset = false; +} + +void hcd_port_reset_end(uint8_t rhport) +{ + (void) rhport; +} + +tusb_speed_t hcd_port_speed_get(uint8_t rhport) +{ + (void)rhport; + switch (LINK_REG->DVSTCTR0_b.RHST) { + default: return TUSB_SPEED_INVALID; + case LINK_REG_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL; + case LINK_REG_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW; + } +} + +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) +{ + (void)rhport; + uint16_t volatile *ctr; + TU_ASSERT(dev_addr < 6,); /* USBa can only handle addresses from 0 to 5. */ + if (!dev_addr) return; + _hcd.ctl_mps[dev_addr] = 0; + uint8_t *ep = &_hcd.ep[dev_addr - 1][0][0]; + for (int i = 0; i < 2 * 15; ++i, ++ep) { + unsigned num = *ep; + if (!num || dev_addr != _hcd.pipe[num].dev) continue; + + ctr = (uint16_t volatile*)&LINK_REG->PIPE_CTR[num - 1]; + *ctr = 0; + LINK_REG->NRDYENB &= ~TU_BIT(num); + LINK_REG->BRDYENB &= ~TU_BIT(num); + LINK_REG->PIPESEL = num; + LINK_REG->PIPECFG = 0; + LINK_REG->PIPEMAXP = 0; + + _hcd.pipe[num].ep = 0; + _hcd.pipe[num].dev = 0; + *ep = 0; + } +} + +/*--------------------------------------------------------------------+ + * Endpoints API + *--------------------------------------------------------------------+*/ +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) +{ + (void)rhport; + // TU_LOG1("S %d %x\n", dev_addr, LINK_REG->DCPCTR); + + TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ + TU_ASSERT(0 == LINK_REG->DCPCTR_b.SUREQ); + + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; + + _hcd.pipe[0].buf = NULL; + _hcd.pipe[0].length = 8; + _hcd.pipe[0].remaining = 0; + _hcd.pipe[0].dev = dev_addr; + + while (LINK_REG->DCPCTR_b.PBUSY) ; + LINK_REG->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr]; + + /* Set direction in advance for DATA stage */ + uint8_t const bmRequesttype = setup_packet[0]; + LINK_REG->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1; + + uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0]; + LINK_REG->USBREQ = tu_htole16(p[0]); + LINK_REG->USBVAL = p[1]; + LINK_REG->USBINDX = p[2]; + LINK_REG->USBLENG = p[3]; + + LINK_REG->DCPCTR_b.SUREQ = 1; + return true; +} + +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *ep_desc) +{ + (void)rhport; + TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ + + const unsigned ep_addr = ep_desc->bEndpointAddress; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned mps = tu_edpt_packet_size(ep_desc); + if (0 == epn) { + LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; + hcd_devtree_info_t devtree; + hcd_devtree_get_info(dev_addr, &devtree); + uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &LINK_REG->DEVADD[0]; + devadd += dev_addr; + while (LINK_REG->DCPCTR_b.PBUSY) ; + LINK_REG->DCPMAXP = (dev_addr << 12) | mps; + *devadd = (TUSB_SPEED_FULL == devtree.speed) ? LINK_REG_DEVADD_USBSPD_FS : LINK_REG_DEVADD_USBSPD_LS; + _hcd.ctl_mps[dev_addr] = mps; + return true; + } + + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned xfer = ep_desc->bmAttributes.xfer; + if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) { + /* USBa supports up to 256 bytes */ + return false; + } + const unsigned num = find_pipe(xfer); + if (!num) return false; + _hcd.pipe[num].dev = dev_addr; + _hcd.pipe[num].ep = ep_addr; + _hcd.ep[dev_addr - 1][dir_in][epn - 1] = num; + + /* setup pipe */ + hcd_int_disable(rhport); + LINK_REG->PIPESEL = num; + LINK_REG->PIPEMAXP = (dev_addr << 12) | mps; + volatile uint16_t *ctr = get_pipectr(num); + *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk; + *ctr = 0; + unsigned cfg = ((1 ^ dir_in) << 4) | epn; + if (xfer == TUSB_XFER_BULK) { + cfg |= LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk; + } else if (xfer == TUSB_XFER_INTERRUPT) { + cfg |= LINK_REG_PIPECFG_TYPE_INT; + } else { + cfg |= LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk; + } + LINK_REG->PIPECFG = cfg; + LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num); + LINK_REG->NRDYENB |= TU_BIT(num); + LINK_REG->BRDYENB |= TU_BIT(num); + if (!dir_in) { + *ctr = LINK_REG_PIPE_CTR_PID_BUF; + } + hcd_int_enable(rhport); + + return true; +} + +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) +{ + bool r; + hcd_int_disable(rhport); + // TU_LOG1("X %d %x %u\n", dev_addr, ep_addr, buflen); + r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen); + hcd_int_enable(rhport); + return r; +} + +bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) +{ + uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr); + TU_ASSERT(ctr); + + const uint32_t pid = *ctr & 0x3; + if (pid & 2) { + *ctr = pid & 2; + *ctr = 0; + } + *ctr = LINK_REG_PIPE_CTR_SQCLR_Msk; + unsigned const epn = tu_edpt_number(ep_addr); + if (!epn) return true; + + if (!tu_edpt_dir(ep_addr)) { /* OUT */ + *ctr = LINK_REG_PIPE_CTR_PID_BUF; + } + return true; +} + +//--------------------------------------------------------------------+ +// ISR +//--------------------------------------------------------------------+ +void hcd_int_handler(uint8_t rhport) +{ + (void)rhport; +#if defined(__CCRX__) + static const int Mod37BitPosition[] = { + -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4, + 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5, + 20, 8, 19, 18}; +#endif + + unsigned is1 = LINK_REG->INTSTS1; + unsigned is0 = LINK_REG->INTSTS0; + /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ + LINK_REG->INTSTS1 = ~((LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk) & is1); + LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk) & is0); + // TU_LOG1("IS %04x %04x\n", is0, is1); + is1 &= LINK_REG->INTENB1; + is0 &= LINK_REG->INTENB0; + + if (is1 & LINK_REG_INTSTS1_SACK_Msk) { + /* Set DATA1 in advance for the next transfer. */ + LINK_REG->DCPCTR_b.SQSET = 1; + hcd_event_xfer_complete(LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); + } + if (is1 & LINK_REG_INTSTS1_SIGN_Msk) { + hcd_event_xfer_complete(LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); + } + if (is1 & LINK_REG_INTSTS1_ATTCH_Msk) { + LINK_REG->DVSTCTR0_b.UACT = 1; + _hcd.need_reset = true; + LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_ATTCH_Msk) | LINK_REG_INTSTS1_DTCH_Msk; + hcd_event_device_attach(rhport, true); + } + if (is1 & LINK_REG_INTSTS1_DTCH_Msk) { + LINK_REG->DVSTCTR0_b.UACT = 0; + if (LINK_REG->DCPCTR_b.SUREQ) { + LINK_REG->DCPCTR_b.SUREQCLR = 1; + } + LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_DTCH_Msk) | LINK_REG_INTSTS1_ATTCH_Msk; + hcd_event_device_remove(rhport, true); + } + + if (is0 & LINK_REG_INTSTS0_BEMP_Msk) { + const unsigned s = LINK_REG->BEMPSTS; + LINK_REG->BEMPSTS = 0; + if (s & 1) { + process_pipe0_bemp(rhport); + } + } + if (is0 & LINK_REG_INTSTS0_NRDY_Msk) { + const unsigned m = LINK_REG->NRDYENB; + unsigned s = LINK_REG->NRDYSTS & m; + LINK_REG->NRDYSTS = ~s; + while (s) { +#if defined(__CCRX__) + const unsigned num = Mod37BitPosition[(-s & s) % 37]; +#else + const unsigned num = __builtin_ctz(s); +#endif + process_pipe_nrdy(rhport, num); + s &= ~TU_BIT(num); + } + } + if (is0 & LINK_REG_INTSTS0_BRDY_Msk) { + const unsigned m = LINK_REG->BRDYENB; + unsigned s = LINK_REG->BRDYSTS & m; + /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ + LINK_REG->BRDYSTS = ~s; + while (s) { +#if defined(__CCRX__) + const unsigned num = Mod37BitPosition[(-s & s) % 37]; +#else + const unsigned num = __builtin_ctz(s); +#endif + process_pipe_brdy(rhport, num); + s &= ~TU_BIT(num); + } + } +} + +#endif diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h new file mode 100644 index 000000000..a73b13951 --- /dev/null +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -0,0 +1,62 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2022 Rafael Silva (@perigoso) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _LINK_RA_H_ +#define _LINK_RA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* renesas fsp api */ +#include "bsp_api.h" + +#define LINK_REG_BASE (0x40090000) + +TU_ATTR_ALWAYS_INLINE +static inline void link_int_enable(uint8_t rhport) +{ + (void) rhport; + NVIC_EnableIRQ(TU_IRQn); +} + +TU_ATTR_ALWAYS_INLINE +static inline void link_int_disable(uint8_t rhport) +{ + (void) rhport; + NVIC_DisableIRQ(TU_IRQn); +} + +// MCU specific PHY init +static inline void link_phy_init(void) +{ +} + +#ifdef __cplusplus +} +#endif + +#endif /* _LINK_RA_H_ */ diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h new file mode 100644 index 000000000..e43253569 --- /dev/null +++ b/src/portable/renesas/rusb2/rusb2_rx.h @@ -0,0 +1,74 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Koji Kitayama + * Portions copyrighted (c) 2021 Roland Winistoerfer + * Copyright (c) 2022 Rafael Silva (@perigoso) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _LINK_RX_H_ +#define _LINK_RX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "iodefine.h" + +#define LINK_REG_BASE (0x000A0000) + +TU_ATTR_ALWAYS_INLINE static inline void link_int_enable(uint8_t rhport) +{ + (void) rhport; +#if (CFG_TUSB_MCU == OPT_MCU_RX72N) + IEN(PERIB, INTB185) = 1; +#else + IEN(USB0, USBI0) = 1; +#endif +} + +TU_ATTR_ALWAYS_INLINE static inline void link_int_disable(uint8_t rhport) +{ + (void) rhport; +#if (CFG_TUSB_MCU == OPT_MCU_RX72N) + IEN(PERIB, INTB185) = 0; +#else + IEN(USB0, USBI0) = 0; +#endif +} + +// MCU specific PHY init +TU_ATTR_ALWAYS_INLINE static inline void link_phy_init(void) +{ +#if (CFG_TUSB_MCU == OPT_MCU_RX72N) + IR(PERIB, INTB185) = 0; +#else + IR(USB0, USBI0) = 0; +#endif +} + +#ifdef __cplusplus +} +#endif + +#endif /* _LINK_RX_H_ */ diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h new file mode 100644 index 000000000..cb3db650a --- /dev/null +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -0,0 +1,1669 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2022 Rafael Silva (@perigoso) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_LINK_TYPE_H_ +#define _TUSB_LINK_TYPE_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*--------------------------------------------------------------------*/ +/* Register Definitions */ +/*--------------------------------------------------------------------*/ + +/* Start of definition of packed structs (used by the CCRX toolchain) */ +TU_ATTR_PACKED_BEGIN +TU_ATTR_BIT_FIELD_ORDER_BEGIN + +typedef struct TU_ATTR_PACKED { + union { + volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct { + uint16_t : 8; + volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */ + volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union { + volatile uint16_t N; /* (@ 0x00000002) Pipe Transaction Counter Register */ + + struct { + volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */ + } N_b; + }; +} LINK_REG_PIPE_TR_t; /* Size = 4 (0x4) */ + +/* LINK_REG Structure */ +typedef struct TU_ATTR_PACKED { + union { + volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */ + + struct { + volatile uint16_t USBE : 1; /* [0..0] USB Operation Enable */ + uint16_t : 2; + volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */ + volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */ + volatile uint16_t DRPD : 1; /* [5..5] D+/D- Line Resistor Control */ + volatile uint16_t DCFM : 1; /* [6..6] Controller Function Select */ + uint16_t : 1; + volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union { + volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */ + + struct { + volatile uint16_t BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union { + volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */ + + struct { + volatile const uint16_t LNST : 2; /* [1..0] USB Data Line Status Monitor */ + volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + volatile const uint16_t + SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */ + volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + volatile const uint16_t OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */ + } SYSSTS0_b; + }; + + union { + volatile const uint16_t PLLSTA; /* (@ 0x00000006) PLL Status Register */ + + struct { + volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union { + volatile uint16_t DVSTCTR0; /* (@ 0x00000008) Device State Control Register 0 */ + + struct { + volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */ + uint16_t : 1; + volatile uint16_t UACT : 1; /* [4..4] USB Bus Enable */ + volatile uint16_t RESUME : 1; /* [5..5] Resume Output */ + volatile uint16_t USBRST : 1; /* [6..6] USB Bus Reset Output */ + volatile uint16_t RWUPE : 1; /* [7..7] Wakeup Detection Enable */ + volatile uint16_t WKUP : 1; /* [8..8] Wakeup Output */ + volatile uint16_t VBUSEN : 1; /* [9..9] USB_VBUSEN Output Pin Control */ + volatile uint16_t EXICEN : 1; /* [10..10] USB_EXICEN Output Pin Control */ + volatile uint16_t HNPBTOA : 1; /* [11..11] Host Negotiation Protocol (HNP) */ + uint16_t : 4; + } DVSTCTR0_b; + }; + volatile const uint16_t RESERVED; + + union { + volatile uint16_t TESTMODE; /* (@ 0x0000000C) USB Test Mode Register */ + + struct { + volatile uint16_t UTST : 4; /* [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + volatile const uint16_t RESERVED1; + volatile const uint32_t RESERVED2; + + union { + volatile uint32_t CFIFO; /* (@ 0x00000014) CFIFO Port Register */ + + struct { + union { + volatile uint16_t CFIFOL; /* (@ 0x00000014) CFIFO Port Register L */ + volatile uint8_t CFIFOLL; /* (@ 0x00000014) CFIFO Port Register LL */ + }; + + union { + volatile uint16_t CFIFOH; /* (@ 0x00000016) CFIFO Port Register H */ + + struct { + volatile const uint8_t RESERVED3; + volatile uint8_t CFIFOHH; /* (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union { + volatile uint32_t D0FIFO; /* (@ 0x00000018) D0FIFO Port Register */ + + struct { + union { + volatile uint16_t D0FIFOL; /* (@ 0x00000018) D0FIFO Port Register L */ + volatile uint8_t D0FIFOLL; /* (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union { + volatile uint16_t D0FIFOH; /* (@ 0x0000001A) D0FIFO Port Register H */ + + struct { + volatile const uint8_t RESERVED4; + volatile uint8_t D0FIFOHH; /* (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union { + volatile uint32_t D1FIFO; /* (@ 0x0000001C) D1FIFO Port Register */ + + struct { + union { + volatile uint16_t D1FIFOL; /* (@ 0x0000001C) D1FIFO Port Register L */ + volatile uint8_t D1FIFOLL; /* (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union { + volatile uint16_t D1FIFOH; /* (@ 0x0000001E) D1FIFO Port Register H */ + + struct { + volatile const uint8_t RESERVED5; + volatile uint8_t D1FIFOHH; /* (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union { + volatile uint16_t CFIFOSEL; /* (@ 0x00000020) CFIFO Port Select Register */ + + struct { + volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + volatile uint16_t ISEL : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + volatile uint16_t BIGEND : 1; /* [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + volatile uint16_t MBW : 2; /* [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */ + volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union { + volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */ + + struct { + volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ + uint16_t : 1; + volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ + volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + volatile const uint32_t RESERVED6; + + union { + volatile uint16_t D0FIFOSEL; /* (@ 0x00000028) D0FIFO Port Select Register */ + + struct { + volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ + uint16_t : 1; + volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */ + volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */ + volatile uint16_t DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */ + volatile uint16_t REW : 1; /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union { + volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */ + + struct { + volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ + uint16_t : 1; + volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ + volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union { + volatile uint16_t D1FIFOSEL; /* (@ 0x0000002C) D1FIFO Port Select Register */ + + struct { + volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ + uint16_t : 1; + volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */ + volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */ + volatile uint16_t DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */ + volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */ + volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union { + volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */ + + struct { + volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ + uint16_t : 1; + volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ + volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union { + volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */ + + struct { + uint16_t : 8; + volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */ + volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */ + volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */ + volatile uint16_t CTRE : 1; /* [11..11] Control Transfer Stage Transition Interrupt Enable */ + volatile uint16_t DVSE : 1; /* [12..12] Device State Transition Interrupt Enable */ + volatile uint16_t SOFE : 1; /* [13..13] Frame Number Update Interrupt Enable */ + volatile uint16_t RSME : 1; /* [14..14] Resume Interrupt Enable */ + volatile uint16_t VBSE : 1; /* [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union { + volatile uint16_t INTENB1; /* (@ 0x00000032) Interrupt Enable Register 1 */ + + struct { + volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + volatile uint16_t SACKE : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */ + volatile uint16_t SIGNE : 1; /* [5..5] Setup Transaction Error Interrupt Enable */ + volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */ + volatile uint16_t DTCHE : 1; /* [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + volatile uint16_t BCHGE : 1; /* [14..14] USB Bus Change Interrupt Enable */ + volatile uint16_t OVRCRE : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + volatile const uint16_t RESERVED7; + + union { + volatile uint16_t BRDYENB; /* (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct { + volatile uint16_t PIPE0BRDYE : 1; /* [0..0] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE1BRDYE : 1; /* [1..1] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE2BRDYE : 1; /* [2..2] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE3BRDYE : 1; /* [3..3] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE4BRDYE : 1; /* [4..4] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE5BRDYE : 1; /* [5..5] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE6BRDYE : 1; /* [6..6] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union { + volatile uint16_t NRDYENB; /* (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct { + volatile uint16_t PIPE0NRDYE : 1; /* [0..0] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE1NRDYE : 1; /* [1..1] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE2NRDYE : 1; /* [2..2] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE3NRDYE : 1; /* [3..3] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE4NRDYE : 1; /* [4..4] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE5NRDYE : 1; /* [5..5] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE6NRDYE : 1; /* [6..6] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */ + volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union { + volatile uint16_t BEMPENB; /* (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct { + volatile uint16_t PIPE0BEMPE : 1; /* [0..0] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE1BEMPE : 1; /* [1..1] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE2BEMPE : 1; /* [2..2] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE3BEMPE : 1; /* [3..3] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE4BEMPE : 1; /* [4..4] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE5BEMPE : 1; /* [5..5] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE6BEMPE : 1; /* [6..6] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */ + volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union { + volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */ + + struct { + uint16_t : 4; + volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */ + volatile uint16_t INTL : 1; /* [5..5] Interrupt Output Sense Select */ + volatile uint16_t BRDYM : 1; /* [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union { + volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */ + + struct { + volatile uint16_t DIRPD : 1; /* [0..0] Power-Down Control */ + volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */ + uint16_t : 1; + volatile uint16_t CDPEN : 1; /* [3..3] Charging Downstream Port Enable */ + volatile uint16_t CLKSEL : 2; /* [5..4] Input System Clock Frequency */ + uint16_t : 2; + volatile uint16_t REPSEL : 2; /* [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + volatile uint16_t REPSTART : 1; /* [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + volatile uint16_t HSEB : 1; /* [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union { + volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */ + + struct { + volatile const uint16_t CTSQ : 3; /* [2..0] Control Transfer Stage */ + volatile uint16_t VALID : 1; /* [3..3] USB Request Reception */ + volatile const uint16_t DVSQ : 3; /* [6..4] Device State */ + volatile const uint16_t VBSTS : 1; /* [7..7] VBUS Input Status */ + volatile const uint16_t BRDY : 1; /* [8..8] Buffer Ready Interrupt Status */ + volatile const uint16_t NRDY : 1; /* [9..9] Buffer Not Ready Interrupt Status */ + volatile const uint16_t BEMP : 1; /* [10..10] Buffer Empty Interrupt Status */ + volatile uint16_t CTRT : 1; /* [11..11] Control Transfer Stage Transition Interrupt Status */ + volatile uint16_t DVST : 1; /* [12..12] Device State Transition Interrupt Status */ + volatile uint16_t SOFR : 1; /* [13..13] Frame Number Refresh Interrupt Status */ + volatile uint16_t RESM : 1; /* [14..14] Resume Interrupt Status */ + volatile uint16_t VBINT : 1; /* [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union { + volatile uint16_t INTSTS1; /* (@ 0x00000042) Interrupt Status Register 1 */ + + struct { + volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + volatile uint16_t SACK : 1; /* [4..4] Setup Transaction Normal Response Interrupt Status */ + volatile uint16_t SIGN : 1; /* [5..5] Setup Transaction Error Interrupt Status */ + volatile uint16_t EOFERR : 1; /* [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + volatile uint16_t LPMEND : 1; /* [8..8] LPM Transaction End Interrupt Status */ + volatile uint16_t L1RSMEND : 1; /* [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */ + volatile uint16_t DTCH : 1; /* [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + volatile uint16_t BCHG : 1; /* [14..14] USB Bus Change Interrupt Status */ + volatile uint16_t OVRCR : 1; /* [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + volatile const uint16_t RESERVED8; + + union { + volatile uint16_t BRDYSTS; /* (@ 0x00000046) BRDY Interrupt Status Register */ + + struct { + volatile uint16_t PIPE0BRDY : 1; /* [0..0] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE1BRDY : 1; /* [1..1] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE2BRDY : 1; /* [2..2] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE3BRDY : 1; /* [3..3] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE4BRDY : 1; /* [4..4] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE5BRDY : 1; /* [5..5] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE6BRDY : 1; /* [6..6] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union { + volatile uint16_t NRDYSTS; /* (@ 0x00000048) NRDY Interrupt Status Register */ + + struct { + volatile uint16_t PIPE0NRDY : 1; /* [0..0] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE1NRDY : 1; /* [1..1] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE2NRDY : 1; /* [2..2] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE3NRDY : 1; /* [3..3] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE4NRDY : 1; /* [4..4] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE5NRDY : 1; /* [5..5] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE6NRDY : 1; /* [6..6] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */ + volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union { + volatile uint16_t BEMPSTS; /* (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct { + volatile uint16_t PIPE0BEMP : 1; /* [0..0] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE1BEMP : 1; /* [1..1] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE2BEMP : 1; /* [2..2] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE3BEMP : 1; /* [3..3] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE4BEMP : 1; /* [4..4] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE5BEMP : 1; /* [5..5] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE6BEMP : 1; /* [6..6] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */ + volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union { + volatile uint16_t FRMNUM; /* (@ 0x0000004C) Frame Number Register */ + + struct { + volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + volatile uint16_t CRCE : 1; /* [14..14] Receive Data Error */ + volatile uint16_t OVRN : 1; /* [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union { + volatile uint16_t UFRMNUM; /* (@ 0x0000004E) uFrame Number Register */ + + struct { + volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + volatile uint16_t DVCHG : 1; /* [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union { + volatile uint16_t USBADDR; /* (@ 0x00000050) USB Address Register */ + + struct { + volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */ + uint16_t : 1; + volatile uint16_t STSRECOV0 : 3; /* [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + volatile const uint16_t RESERVED9; + + union { + volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */ + + struct { + volatile uint16_t BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */ + volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union { + volatile uint16_t USBVAL; /* (@ 0x00000056) USB Request Value Register */ + + struct { + volatile uint16_t WVALUE : 16; /* [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union { + volatile uint16_t USBINDX; /* (@ 0x00000058) USB Request Index Register */ + + struct { + volatile uint16_t WINDEX : 16; /* [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union { + volatile uint16_t USBLENG; /* (@ 0x0000005A) USB Request Length Register */ + + struct { + volatile uint16_t WLENGTH : 16; /* [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union { + volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */ + + struct { + uint16_t : 4; + volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ + uint16_t : 2; + volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */ + volatile uint16_t CNTMD : 1; /* [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union { + volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct { + volatile uint16_t MXPS : 7; /* [6..0] Maximum Packet Size */ + uint16_t : 5; + volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ + } DCPMAXP_b; + }; + + union { + volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */ + + struct { + volatile uint16_t PID : 2; /* [1..0] Response PID */ + volatile uint16_t CCPL : 1; /* [2..2] Control Transfer End Enable */ + uint16_t : 2; + volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */ + volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Monitor */ + volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */ + volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */ + uint16_t : 2; + volatile uint16_t SUREQ : 1; /* [14..14] Setup Token Transmission */ + volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ + } DCPCTR_b; + }; + volatile const uint16_t RESERVED10; + + union { + volatile uint16_t PIPESEL; /* (@ 0x00000064) Pipe Window Select Register */ + + struct { + volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + volatile const uint16_t RESERVED11; + + union { + volatile uint16_t PIPECFG; /* (@ 0x00000068) Pipe Configuration Register */ + + struct { + volatile uint16_t EPNUM : 4; /* [3..0] Endpoint Number */ + volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ + uint16_t : 2; + volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */ + volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */ + } PIPECFG_b; + }; + volatile const uint16_t RESERVED12; + + union { + volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct { + volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */ + uint16_t : 3; + volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union { + volatile uint16_t PIPEPERI; /* (@ 0x0000006E) Pipe Cycle Control Register */ + + struct { + volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */ + uint16_t : 9; + volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union { + volatile uint16_t PIPE_CTR[9]; /* (@ 0x00000070) Pipe [0..8] Control Register */ + + struct { + volatile uint16_t PID : 2; /* [1..0] Response PID */ + uint16_t : 3; + volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */ + volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Confirmation */ + volatile uint16_t SQSET : 1; /* [7..7] Sequence Toggle Bit Set */ + volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ + volatile uint16_t ACLRM : 1; /* [9..9] Auto Buffer Clear Mode */ + volatile uint16_t ATREPM : 1; /* [10..10] Auto Response Mode */ + uint16_t : 1; + volatile const uint16_t CSSTS : 1; /* [12..12] CSSTS Status */ + volatile uint16_t CSCLR : 1; /* [13..13] CSPLIT Status Clear */ + volatile const uint16_t INBUFM : 1; /* [14..14] Transmit Buffer Monitor */ + volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + volatile const uint16_t RESERVED13; + volatile const uint32_t RESERVED14[3]; + volatile LINK_REG_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */ + volatile const uint32_t RESERVED15[3]; + + union { + volatile uint16_t USBBCCTRL0; /* (@ 0x000000B0) BC Control Register 0 */ + + struct { + volatile uint16_t RPDME0 : 1; /* [0..0] D- Pin Pull-Down Control */ + volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */ + volatile uint16_t + IDMSINKE0 : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + volatile uint16_t + IDPSINKE0 : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + volatile const uint16_t CHGDETSTS0 : 1; /* [8..8] D- Pin 0.6 V Input Detection Status */ + volatile const uint16_t PDDETSTS0 : 1; /* [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + volatile const uint16_t RESERVED16; + volatile const uint32_t RESERVED17[4]; + + union { + volatile uint16_t UCKSEL; /* (@ 0x000000C4) USB Clock Selection Register */ + + struct { + volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + volatile const uint16_t RESERVED18; + volatile const uint32_t RESERVED19; + + union { + volatile uint16_t USBMC; /* (@ 0x000000CC) USB Module Control Register */ + + struct { + volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + volatile uint16_t VDCEN : 1; /* [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + volatile const uint16_t RESERVED20; + + union { + volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */ + + struct { + uint16_t : 6; + volatile uint16_t USBSPD : 2; /* [7..6] Transfer Speed of Communication Target Device */ + volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */ + volatile uint16_t UPPHUB : 4; /* [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + volatile const uint32_t RESERVED21[3]; + + union { + volatile uint32_t PHYSLEW; /* (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct { + volatile uint32_t SLEWR00 : 1; /* [0..0] Receiver Cross Point Adjustment 00 */ + volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */ + volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */ + volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + volatile const uint32_t RESERVED22[3]; + + union { + volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */ + + struct { + uint16_t : 7; + volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union { + volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */ + + struct { + uint16_t : 14; + volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + volatile const uint32_t RESERVED23[15]; + + union { + volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */ + + struct { + volatile uint16_t IDPSRCE : 1; /* [0..0] IDPSRC Control */ + volatile uint16_t IDMSINKE : 1; /* [1..1] IDMSINK Control */ + volatile uint16_t VDPSRCE : 1; /* [2..2] VDPSRC Control */ + volatile uint16_t IDPSINKE : 1; /* [3..3] IDPSINK Control */ + volatile uint16_t VDMSRCE : 1; /* [4..4] VDMSRC Control */ + volatile uint16_t DCPMODE : 1; /* [5..5] DCP Mode Control */ + uint16_t : 2; + volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */ + volatile const uint16_t PDDETSTS : 1; /* [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + volatile const uint16_t RESERVED24; + + union { + volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */ + + struct { + volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */ + volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */ + volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */ + volatile const uint16_t DVSQ : 4; /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */ + volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */ + uint16_t : 2; + volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union { + volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */ + + struct { + uint16_t : 8; + volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */ + volatile uint16_t RWEMON : 1; /* [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union { + volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */ + + struct { + volatile uint16_t L1REQ : 1; /* [0..0] L1 Transition Request */ + volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union { + volatile uint16_t HL1CTRL2; /* (@ 0x0000014A) Host L1 Control Register 2 */ + + struct { + volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */ + uint16_t : 4; + volatile uint16_t HIRD : 4; /* [11..8] LPM Token HIRD */ + volatile uint16_t L1RWE : 1; /* [12..12] LPM Token L1 Remote Wake Enable */ + uint16_t : 2; + volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */ + } HL1CTRL2_b; + }; + volatile const uint32_t RESERVED25[5]; + + union { + volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */ + + struct { + uint32_t : 20; + volatile const uint32_t DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */ + volatile const uint32_t DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */ + uint32_t : 1; + volatile const uint32_t DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union { + volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct { + uint32_t : 4; + volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */ + volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + volatile uint32_t DVBSTSHE : 1; /* [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + volatile const uint32_t DOVCAH : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */ + volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union { + volatile uint16_t DPUSR2R; /* (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct { + volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */ + volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + volatile const uint16_t DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */ + volatile const uint16_t DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */ + uint16_t : 2; + volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */ + volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union { + volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct { + volatile uint16_t FIXPHY : 1; /* [0..0] USB Transceiver Control Fix */ + volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + volatile const uint32_t RESERVED26[165]; + + union { + volatile uint32_t + DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */ + + struct { + volatile uint32_t SRPC0 : 1; /* [0..0] USB Single End Receiver Control */ + volatile uint32_t RPUE0 : 1; /* [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + volatile uint32_t DRPD0 : 1; /* [3..3] D+/D- Pull-Down Resistor Control */ + volatile uint32_t FIXPHY0 : 1; /* [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + volatile const uint32_t DP0 : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + volatile const uint32_t DM0 : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + volatile const uint32_t DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */ + volatile const uint32_t DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */ + uint32_t : 1; + volatile const uint32_t DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union { + volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */ + + struct { + volatile uint32_t DPINTE0 : 1; /* [0..0] USB DP Interrupt Enable/Clear */ + volatile uint32_t DMINTE0 : 1; /* [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + volatile uint32_t DOVRCRAE0 : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */ + volatile uint32_t DOVRCRBE0 : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + volatile uint32_t DVBSE0 : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + volatile const uint32_t DPINT0 : 1; /* [16..16] USB DP Interrupt Source Recovery */ + volatile const uint32_t DMINT0 : 1; /* [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + volatile const uint32_t DOVRCRA0 : 1; /* [20..20] USB OVRCURA Interrupt Source Recovery */ + volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} LINK_REG_t; /* Size = 1032 (0x408) */ + +TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */ +TU_ATTR_BIT_FIELD_ORDER_END + +/*--------------------------------------------------------------------*/ +/* Register Bit Definitions */ +/*--------------------------------------------------------------------*/ + +// PIPE_TR +// E +#define LINK_REG_PIPE_TR_E_TRENB_Pos (9UL) /* TRENB (Bit 9) */ +#define LINK_REG_PIPE_TR_E_TRENB_Msk (0x200UL) /* TRENB (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_TR_E_TRCLR_Pos (8UL) /* TRCLR (Bit 8) */ +#define LINK_REG_PIPE_TR_E_TRCLR_Msk (0x100UL) /* TRCLR (Bitfield-Mask: 0x01) */ + +// N +#define LINK_REG_PIPE_TR_N_TRNCNT_Pos (0UL) /* TRNCNT (Bit 0) */ +#define LINK_REG_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /* TRNCNT (Bitfield-Mask: 0xffff) */ + +// LINK_REG + +// SYSCFG +#define LINK_REG_SYSCFG_SCKE_Pos (10UL) /* SCKE (Bit 10) */ +#define LINK_REG_SYSCFG_SCKE_Msk (0x400UL) /* SCKE (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_CNEN_Pos (8UL) /* CNEN (Bit 8) */ +#define LINK_REG_SYSCFG_CNEN_Msk (0x100UL) /* CNEN (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_DCFM_Pos (6UL) /* DCFM (Bit 6) */ +#define LINK_REG_SYSCFG_DCFM_Msk (0x40UL) /* DCFM (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_DRPD_Pos (5UL) /* DRPD (Bit 5) */ +#define LINK_REG_SYSCFG_DRPD_Msk (0x20UL) /* DRPD (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_DPRPU_Pos (4UL) /* DPRPU (Bit 4) */ +#define LINK_REG_SYSCFG_DPRPU_Msk (0x10UL) /* DPRPU (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_DMRPU_Pos (3UL) /* DMRPU (Bit 3) */ +#define LINK_REG_SYSCFG_DMRPU_Msk (0x8UL) /* DMRPU (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSCFG_USBE_Pos (0UL) /* USBE (Bit 0) */ +#define LINK_REG_SYSCFG_USBE_Msk (0x1UL) /* USBE (Bitfield-Mask: 0x01) */ + +// BUSWAIT +#define LINK_REG_BUSWAIT_BWAIT_Pos (0UL) /* BWAIT (Bit 0) */ +#define LINK_REG_BUSWAIT_BWAIT_Msk (0xfUL) /* BWAIT (Bitfield-Mask: 0x0f) */ + +// SYSSTS0 +#define LINK_REG_SYSSTS0_OVCMON_Pos (14UL) /* OVCMON (Bit 14) */ +#define LINK_REG_SYSSTS0_OVCMON_Msk (0xc000UL) /* OVCMON (Bitfield-Mask: 0x03) */ +#define LINK_REG_SYSSTS0_HTACT_Pos (6UL) /* HTACT (Bit 6) */ +#define LINK_REG_SYSSTS0_HTACT_Msk (0x40UL) /* HTACT (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSSTS0_SOFEA_Pos (5UL) /* SOFEA (Bit 5) */ +#define LINK_REG_SYSSTS0_SOFEA_Msk (0x20UL) /* SOFEA (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSSTS0_IDMON_Pos (2UL) /* IDMON (Bit 2) */ +#define LINK_REG_SYSSTS0_IDMON_Msk (0x4UL) /* IDMON (Bitfield-Mask: 0x01) */ +#define LINK_REG_SYSSTS0_LNST_Pos (0UL) /* LNST (Bit 0) */ +#define LINK_REG_SYSSTS0_LNST_Msk (0x3UL) /* LNST (Bitfield-Mask: 0x03) */ + +// PLLSTA +#define LINK_REG_PLLSTA_PLLLOCK_Pos (0UL) /* PLLLOCK (Bit 0) */ +#define LINK_REG_PLLSTA_PLLLOCK_Msk (0x1UL) /* PLLLOCK (Bitfield-Mask: 0x01) */ + +// DVSTCTR0 +#define LINK_REG_DVSTCTR0_HNPBTOA_Pos (11UL) /* HNPBTOA (Bit 11) */ +#define LINK_REG_DVSTCTR0_HNPBTOA_Msk (0x800UL) /* HNPBTOA (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_EXICEN_Pos (10UL) /* EXICEN (Bit 10) */ +#define LINK_REG_DVSTCTR0_EXICEN_Msk (0x400UL) /* EXICEN (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_VBUSEN_Pos (9UL) /* VBUSEN (Bit 9) */ +#define LINK_REG_DVSTCTR0_VBUSEN_Msk (0x200UL) /* VBUSEN (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_WKUP_Pos (8UL) /* WKUP (Bit 8) */ +#define LINK_REG_DVSTCTR0_WKUP_Msk (0x100UL) /* WKUP (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_RWUPE_Pos (7UL) /* RWUPE (Bit 7) */ +#define LINK_REG_DVSTCTR0_RWUPE_Msk (0x80UL) /* RWUPE (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_USBRST_Pos (6UL) /* USBRST (Bit 6) */ +#define LINK_REG_DVSTCTR0_USBRST_Msk (0x40UL) /* USBRST (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_RESUME_Pos (5UL) /* RESUME (Bit 5) */ +#define LINK_REG_DVSTCTR0_RESUME_Msk (0x20UL) /* RESUME (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_UACT_Pos (4UL) /* UACT (Bit 4) */ +#define LINK_REG_DVSTCTR0_UACT_Msk (0x10UL) /* UACT (Bitfield-Mask: 0x01) */ +#define LINK_REG_DVSTCTR0_RHST_Pos (0UL) /* RHST (Bit 0) */ +#define LINK_REG_DVSTCTR0_RHST_Msk (0x7UL) /* RHST (Bitfield-Mask: 0x07) */ + +// TESTMODE +#define LINK_REG_TESTMODE_UTST_Pos (0UL) /* UTST (Bit 0) */ +#define LINK_REG_TESTMODE_UTST_Msk (0xfUL) /* UTST (Bitfield-Mask: 0x0f) */ + +// CFIFOSEL +#define LINK_REG_CFIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ +#define LINK_REG_CFIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ +#define LINK_REG_CFIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ +#define LINK_REG_CFIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ +#define LINK_REG_CFIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ +#define LINK_REG_CFIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOSEL_ISEL_Pos (5UL) /* ISEL (Bit 5) */ +#define LINK_REG_CFIFOSEL_ISEL_Msk (0x20UL) /* ISEL (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ +#define LINK_REG_CFIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ + +// CFIFOCTR +#define LINK_REG_CFIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ +#define LINK_REG_CFIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ +#define LINK_REG_CFIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ +#define LINK_REG_CFIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ +#define LINK_REG_CFIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ +#define LINK_REG_CFIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ + +// D0FIFOSEL +#define LINK_REG_D0FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ +#define LINK_REG_D0FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ +#define LINK_REG_D0FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ +#define LINK_REG_D0FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ +#define LINK_REG_D0FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ +#define LINK_REG_D0FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ +#define LINK_REG_D0FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ +#define LINK_REG_D0FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ +#define LINK_REG_D0FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ + +// D0FIFOCTR +#define LINK_REG_D0FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ +#define LINK_REG_D0FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ +#define LINK_REG_D0FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ +#define LINK_REG_D0FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ +#define LINK_REG_D0FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ +#define LINK_REG_D0FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ + +// D1FIFOSEL +#define LINK_REG_D1FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ +#define LINK_REG_D1FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ +#define LINK_REG_D1FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ +#define LINK_REG_D1FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ +#define LINK_REG_D1FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ +#define LINK_REG_D1FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ +#define LINK_REG_D1FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ +#define LINK_REG_D1FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ +#define LINK_REG_D1FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ + +// D1FIFOCTR +#define LINK_REG_D1FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ +#define LINK_REG_D1FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ +#define LINK_REG_D1FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ +#define LINK_REG_D1FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ +#define LINK_REG_D1FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ +#define LINK_REG_D1FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ + +// INTENB0 +#define LINK_REG_INTENB0_VBSE_Pos (15UL) /* VBSE (Bit 15) */ +#define LINK_REG_INTENB0_VBSE_Msk (0x8000UL) /* VBSE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_RSME_Pos (14UL) /* RSME (Bit 14) */ +#define LINK_REG_INTENB0_RSME_Msk (0x4000UL) /* RSME (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_SOFE_Pos (13UL) /* SOFE (Bit 13) */ +#define LINK_REG_INTENB0_SOFE_Msk (0x2000UL) /* SOFE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_DVSE_Pos (12UL) /* DVSE (Bit 12) */ +#define LINK_REG_INTENB0_DVSE_Msk (0x1000UL) /* DVSE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_CTRE_Pos (11UL) /* CTRE (Bit 11) */ +#define LINK_REG_INTENB0_CTRE_Msk (0x800UL) /* CTRE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_BEMPE_Pos (10UL) /* BEMPE (Bit 10) */ +#define LINK_REG_INTENB0_BEMPE_Msk (0x400UL) /* BEMPE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_NRDYE_Pos (9UL) /* NRDYE (Bit 9) */ +#define LINK_REG_INTENB0_NRDYE_Msk (0x200UL) /* NRDYE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB0_BRDYE_Pos (8UL) /* BRDYE (Bit 8) */ +#define LINK_REG_INTENB0_BRDYE_Msk (0x100UL) /* BRDYE (Bitfield-Mask: 0x01) */ + +// INTENB1 +#define LINK_REG_INTENB1_OVRCRE_Pos (15UL) /* OVRCRE (Bit 15) */ +#define LINK_REG_INTENB1_OVRCRE_Msk (0x8000UL) /* OVRCRE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_BCHGE_Pos (14UL) /* BCHGE (Bit 14) */ +#define LINK_REG_INTENB1_BCHGE_Msk (0x4000UL) /* BCHGE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_DTCHE_Pos (12UL) /* DTCHE (Bit 12) */ +#define LINK_REG_INTENB1_DTCHE_Msk (0x1000UL) /* DTCHE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_ATTCHE_Pos (11UL) /* ATTCHE (Bit 11) */ +#define LINK_REG_INTENB1_ATTCHE_Msk (0x800UL) /* ATTCHE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_EOFERRE_Pos (6UL) /* EOFERRE (Bit 6) */ +#define LINK_REG_INTENB1_EOFERRE_Msk (0x40UL) /* EOFERRE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_SIGNE_Pos (5UL) /* SIGNE (Bit 5) */ +#define LINK_REG_INTENB1_SIGNE_Msk (0x20UL) /* SIGNE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_SACKE_Pos (4UL) /* SACKE (Bit 4) */ +#define LINK_REG_INTENB1_SACKE_Msk (0x10UL) /* SACKE (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTENB1_PDDETINTE0_Pos (0UL) /* PDDETINTE0 (Bit 0) */ +#define LINK_REG_INTENB1_PDDETINTE0_Msk (0x1UL) /* PDDETINTE0 (Bitfield-Mask: 0x01) */ + +// BRDYENB +#define LINK_REG_BRDYENB_PIPEBRDYE_Pos (0UL) /* PIPEBRDYE (Bit 0) */ +#define LINK_REG_BRDYENB_PIPEBRDYE_Msk (0x1UL) /* PIPEBRDYE (Bitfield-Mask: 0x01) */ + +// NRDYENB +#define LINK_REG_NRDYENB_PIPENRDYE_Pos (0UL) /* PIPENRDYE (Bit 0) */ +#define LINK_REG_NRDYENB_PIPENRDYE_Msk (0x1UL) /* PIPENRDYE (Bitfield-Mask: 0x01) */ + +// BEMPENB +#define LINK_REG_BEMPENB_PIPEBEMPE_Pos (0UL) /* PIPEBEMPE (Bit 0) */ +#define LINK_REG_BEMPENB_PIPEBEMPE_Msk (0x1UL) /* PIPEBEMPE (Bitfield-Mask: 0x01) */ + +// SOFCFG +#define LINK_REG_SOFCFG_TRNENSEL_Pos (8UL) /* TRNENSEL (Bit 8) */ +#define LINK_REG_SOFCFG_TRNENSEL_Msk (0x100UL) /* TRNENSEL (Bitfield-Mask: 0x01) */ +#define LINK_REG_SOFCFG_BRDYM_Pos (6UL) /* BRDYM (Bit 6) */ +#define LINK_REG_SOFCFG_BRDYM_Msk (0x40UL) /* BRDYM (Bitfield-Mask: 0x01) */ +#define LINK_REG_SOFCFG_INTL_Pos (5UL) /* INTL (Bit 5) */ +#define LINK_REG_SOFCFG_INTL_Msk (0x20UL) /* INTL (Bitfield-Mask: 0x01) */ +#define LINK_REG_SOFCFG_EDGESTS_Pos (4UL) /* EDGESTS (Bit 4) */ +#define LINK_REG_SOFCFG_EDGESTS_Msk (0x10UL) /* EDGESTS (Bitfield-Mask: 0x01) */ + +// PHYSET +#define LINK_REG_PHYSET_HSEB_Pos (15UL) /* HSEB (Bit 15) */ +#define LINK_REG_PHYSET_HSEB_Msk (0x8000UL) /* HSEB (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSET_REPSTART_Pos (11UL) /* REPSTART (Bit 11) */ +#define LINK_REG_PHYSET_REPSTART_Msk (0x800UL) /* REPSTART (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSET_REPSEL_Pos (8UL) /* REPSEL (Bit 8) */ +#define LINK_REG_PHYSET_REPSEL_Msk (0x300UL) /* REPSEL (Bitfield-Mask: 0x03) */ +#define LINK_REG_PHYSET_CLKSEL_Pos (4UL) /* CLKSEL (Bit 4) */ +#define LINK_REG_PHYSET_CLKSEL_Msk (0x30UL) /* CLKSEL (Bitfield-Mask: 0x03) */ +#define LINK_REG_PHYSET_CDPEN_Pos (3UL) /* CDPEN (Bit 3) */ +#define LINK_REG_PHYSET_CDPEN_Msk (0x8UL) /* CDPEN (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSET_PLLRESET_Pos (1UL) /* PLLRESET (Bit 1) */ +#define LINK_REG_PHYSET_PLLRESET_Msk (0x2UL) /* PLLRESET (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSET_DIRPD_Pos (0UL) /* DIRPD (Bit 0) */ +#define LINK_REG_PHYSET_DIRPD_Msk (0x1UL) /* DIRPD (Bitfield-Mask: 0x01) */ + +// INTSTS0 +#define LINK_REG_INTSTS0_VBINT_Pos (15UL) /* VBINT (Bit 15) */ +#define LINK_REG_INTSTS0_VBINT_Msk (0x8000UL) /* VBINT (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_RESM_Pos (14UL) /* RESM (Bit 14) */ +#define LINK_REG_INTSTS0_RESM_Msk (0x4000UL) /* RESM (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_SOFR_Pos (13UL) /* SOFR (Bit 13) */ +#define LINK_REG_INTSTS0_SOFR_Msk (0x2000UL) /* SOFR (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_DVST_Pos (12UL) /* DVST (Bit 12) */ +#define LINK_REG_INTSTS0_DVST_Msk (0x1000UL) /* DVST (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_CTRT_Pos (11UL) /* CTRT (Bit 11) */ +#define LINK_REG_INTSTS0_CTRT_Msk (0x800UL) /* CTRT (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_BEMP_Pos (10UL) /* BEMP (Bit 10) */ +#define LINK_REG_INTSTS0_BEMP_Msk (0x400UL) /* BEMP (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_NRDY_Pos (9UL) /* NRDY (Bit 9) */ +#define LINK_REG_INTSTS0_NRDY_Msk (0x200UL) /* NRDY (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_BRDY_Pos (8UL) /* BRDY (Bit 8) */ +#define LINK_REG_INTSTS0_BRDY_Msk (0x100UL) /* BRDY (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_VBSTS_Pos (7UL) /* VBSTS (Bit 7) */ +#define LINK_REG_INTSTS0_VBSTS_Msk (0x80UL) /* VBSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ +#define LINK_REG_INTSTS0_DVSQ_Msk (0x70UL) /* DVSQ (Bitfield-Mask: 0x07) */ +#define LINK_REG_INTSTS0_VALID_Pos (3UL) /* VALID (Bit 3) */ +#define LINK_REG_INTSTS0_VALID_Msk (0x8UL) /* VALID (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS0_CTSQ_Pos (0UL) /* CTSQ (Bit 0) */ +#define LINK_REG_INTSTS0_CTSQ_Msk (0x7UL) /* CTSQ (Bitfield-Mask: 0x07) */ + +// INTSTS1 +#define LINK_REG_INTSTS1_OVRCR_Pos (15UL) /* OVRCR (Bit 15) */ +#define LINK_REG_INTSTS1_OVRCR_Msk (0x8000UL) /* OVRCR (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_BCHG_Pos (14UL) /* BCHG (Bit 14) */ +#define LINK_REG_INTSTS1_BCHG_Msk (0x4000UL) /* BCHG (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_DTCH_Pos (12UL) /* DTCH (Bit 12) */ +#define LINK_REG_INTSTS1_DTCH_Msk (0x1000UL) /* DTCH (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_ATTCH_Pos (11UL) /* ATTCH (Bit 11) */ +#define LINK_REG_INTSTS1_ATTCH_Msk (0x800UL) /* ATTCH (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_L1RSMEND_Pos (9UL) /* L1RSMEND (Bit 9) */ +#define LINK_REG_INTSTS1_L1RSMEND_Msk (0x200UL) /* L1RSMEND (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_LPMEND_Pos (8UL) /* LPMEND (Bit 8) */ +#define LINK_REG_INTSTS1_LPMEND_Msk (0x100UL) /* LPMEND (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_EOFERR_Pos (6UL) /* EOFERR (Bit 6) */ +#define LINK_REG_INTSTS1_EOFERR_Msk (0x40UL) /* EOFERR (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_SIGN_Pos (5UL) /* SIGN (Bit 5) */ +#define LINK_REG_INTSTS1_SIGN_Msk (0x20UL) /* SIGN (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_SACK_Pos (4UL) /* SACK (Bit 4) */ +#define LINK_REG_INTSTS1_SACK_Msk (0x10UL) /* SACK (Bitfield-Mask: 0x01) */ +#define LINK_REG_INTSTS1_PDDETINT0_Pos (0UL) /* PDDETINT0 (Bit 0) */ +#define LINK_REG_INTSTS1_PDDETINT0_Msk (0x1UL) /* PDDETINT0 (Bitfield-Mask: 0x01) */ + +// BRDYSTS +#define LINK_REG_BRDYSTS_PIPEBRDY_Pos (0UL) /* PIPEBRDY (Bit 0) */ +#define LINK_REG_BRDYSTS_PIPEBRDY_Msk (0x1UL) /* PIPEBRDY (Bitfield-Mask: 0x01) */ + +// NRDYSTS +#define LINK_REG_NRDYSTS_PIPENRDY_Pos (0UL) /* PIPENRDY (Bit 0) */ +#define LINK_REG_NRDYSTS_PIPENRDY_Msk (0x1UL) /* PIPENRDY (Bitfield-Mask: 0x01) */ + +// BEMPSTS +#define LINK_REG_BEMPSTS_PIPEBEMP_Pos (0UL) /* PIPEBEMP (Bit 0) */ +#define LINK_REG_BEMPSTS_PIPEBEMP_Msk (0x1UL) /* PIPEBEMP (Bitfield-Mask: 0x01) */ + +// FRMNUM +#define LINK_REG_FRMNUM_OVRN_Pos (15UL) /* OVRN (Bit 15) */ +#define LINK_REG_FRMNUM_OVRN_Msk (0x8000UL) /* OVRN (Bitfield-Mask: 0x01) */ +#define LINK_REG_FRMNUM_CRCE_Pos (14UL) /* CRCE (Bit 14) */ +#define LINK_REG_FRMNUM_CRCE_Msk (0x4000UL) /* CRCE (Bitfield-Mask: 0x01) */ +#define LINK_REG_FRMNUM_FRNM_Pos (0UL) /* FRNM (Bit 0) */ +#define LINK_REG_FRMNUM_FRNM_Msk (0x7ffUL) /* FRNM (Bitfield-Mask: 0x7ff) */ + +// UFRMNUM +#define LINK_REG_UFRMNUM_DVCHG_Pos (15UL) /* DVCHG (Bit 15) */ +#define LINK_REG_UFRMNUM_DVCHG_Msk (0x8000UL) /* DVCHG (Bitfield-Mask: 0x01) */ +#define LINK_REG_UFRMNUM_UFRNM_Pos (0UL) /* UFRNM (Bit 0) */ +#define LINK_REG_UFRMNUM_UFRNM_Msk (0x7UL) /* UFRNM (Bitfield-Mask: 0x07) */ + +// USBADDR +#define LINK_REG_USBADDR_STSRECOV0_Pos (8UL) /* STSRECOV0 (Bit 8) */ +#define LINK_REG_USBADDR_STSRECOV0_Msk (0x700UL) /* STSRECOV0 (Bitfield-Mask: 0x07) */ +#define LINK_REG_USBADDR_USBADDR_Pos (0UL) /* USBADDR (Bit 0) */ +#define LINK_REG_USBADDR_USBADDR_Msk (0x7fUL) /* USBADDR (Bitfield-Mask: 0x7f) */ + +// USBREQ +#define LINK_REG_USBREQ_BREQUEST_Pos (8UL) /* BREQUEST (Bit 8) */ +#define LINK_REG_USBREQ_BREQUEST_Msk (0xff00UL) /* BREQUEST (Bitfield-Mask: 0xff) */ +#define LINK_REG_USBREQ_BMREQUESTTYPE_Pos (0UL) /* BMREQUESTTYPE (Bit 0) */ +#define LINK_REG_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */ + +// USBVAL +#define LINK_REG_USBVAL_WVALUE_Pos (0UL) /* WVALUE (Bit 0) */ +#define LINK_REG_USBVAL_WVALUE_Msk (0xffffUL) /* WVALUE (Bitfield-Mask: 0xffff) */ + +// USBINDX +#define LINK_REG_USBINDX_WINDEX_Pos (0UL) /* WINDEX (Bit 0) */ +#define LINK_REG_USBINDX_WINDEX_Msk (0xffffUL) /* WINDEX (Bitfield-Mask: 0xffff) */ + +// USBLENG +#define LINK_REG_USBLENG_WLENGTH_Pos (0UL) /* WLENGTH (Bit 0) */ +#define LINK_REG_USBLENG_WLENGTH_Msk (0xffffUL) /* WLENGTH (Bitfield-Mask: 0xffff) */ + +// DCPCFG +#define LINK_REG_DCPCFG_CNTMD_Pos (8UL) /* CNTMD (Bit 8) */ +#define LINK_REG_DCPCFG_CNTMD_Msk (0x100UL) /* CNTMD (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ +#define LINK_REG_DCPCFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCFG_DIR_Pos (4UL) /* DIR (Bit 4) */ +#define LINK_REG_DCPCFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ + +// DCPMAXP +#define LINK_REG_DCPMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ +#define LINK_REG_DCPMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ +#define LINK_REG_DCPMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ +#define LINK_REG_DCPMAXP_MXPS_Msk (0x7fUL) /* MXPS (Bitfield-Mask: 0x7f) */ + +// DCPCTR +#define LINK_REG_DCPCTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ +#define LINK_REG_DCPCTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_SUREQ_Pos (14UL) /* SUREQ (Bit 14) */ +#define LINK_REG_DCPCTR_SUREQ_Msk (0x4000UL) /* SUREQ (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_SUREQCLR_Pos (11UL) /* SUREQCLR (Bit 11) */ +#define LINK_REG_DCPCTR_SUREQCLR_Msk (0x800UL) /* SUREQCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ +#define LINK_REG_DCPCTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ +#define LINK_REG_DCPCTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ +#define LINK_REG_DCPCTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ +#define LINK_REG_DCPCTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_CCPL_Pos (2UL) /* CCPL (Bit 2) */ +#define LINK_REG_DCPCTR_CCPL_Msk (0x4UL) /* CCPL (Bitfield-Mask: 0x01) */ +#define LINK_REG_DCPCTR_PID_Pos (0UL) /* PID (Bit 0) */ +#define LINK_REG_DCPCTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ + +// PIPESEL +#define LINK_REG_PIPESEL_PIPESEL_Pos (0UL) /* PIPESEL (Bit 0) */ +#define LINK_REG_PIPESEL_PIPESEL_Msk (0xfUL) /* PIPESEL (Bitfield-Mask: 0x0f) */ + +// PIPECFG +#define LINK_REG_PIPECFG_TYPE_Pos (14UL) /* TYPE (Bit 14) */ +#define LINK_REG_PIPECFG_TYPE_Msk (0xc000UL) /* TYPE (Bitfield-Mask: 0x03) */ +#define LINK_REG_PIPECFG_BFRE_Pos (10UL) /* BFRE (Bit 10) */ +#define LINK_REG_PIPECFG_BFRE_Msk (0x400UL) /* BFRE (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPECFG_DBLB_Pos (9UL) /* DBLB (Bit 9) */ +#define LINK_REG_PIPECFG_DBLB_Msk (0x200UL) /* DBLB (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPECFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ +#define LINK_REG_PIPECFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPECFG_DIR_Pos (4UL) /* DIR (Bit 4) */ +#define LINK_REG_PIPECFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPECFG_EPNUM_Pos (0UL) /* EPNUM (Bit 0) */ +#define LINK_REG_PIPECFG_EPNUM_Msk (0xfUL) /* EPNUM (Bitfield-Mask: 0x0f) */ + +// PIPEMAXP +#define LINK_REG_PIPEMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ +#define LINK_REG_PIPEMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ +#define LINK_REG_PIPEMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ +#define LINK_REG_PIPEMAXP_MXPS_Msk (0x1ffUL) /* MXPS (Bitfield-Mask: 0x1ff) */ + +// PIPEPERI +#define LINK_REG_PIPEPERI_IFIS_Pos (12UL) /* IFIS (Bit 12) */ +#define LINK_REG_PIPEPERI_IFIS_Msk (0x1000UL) /* IFIS (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPEPERI_IITV_Pos (0UL) /* IITV (Bit 0) */ +#define LINK_REG_PIPEPERI_IITV_Msk (0x7UL) /* IITV (Bitfield-Mask: 0x07) */ + +// PIPE_CTR +#define LINK_REG_PIPE_CTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ +#define LINK_REG_PIPE_CTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_INBUFM_Pos (14UL) /* INBUFM (Bit 14) */ +#define LINK_REG_PIPE_CTR_INBUFM_Msk (0x4000UL) /* INBUFM (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_CSCLR_Pos (13UL) /* CSCLR (Bit 13) */ +#define LINK_REG_PIPE_CTR_CSCLR_Msk (0x2000UL) /* CSCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_CSSTS_Pos (12UL) /* CSSTS (Bit 12) */ +#define LINK_REG_PIPE_CTR_CSSTS_Msk (0x1000UL) /* CSSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_ATREPM_Pos (10UL) /* ATREPM (Bit 10) */ +#define LINK_REG_PIPE_CTR_ATREPM_Msk (0x400UL) /* ATREPM (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_ACLRM_Pos (9UL) /* ACLRM (Bit 9) */ +#define LINK_REG_PIPE_CTR_ACLRM_Msk (0x200UL) /* ACLRM (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ +#define LINK_REG_PIPE_CTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ +#define LINK_REG_PIPE_CTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ +#define LINK_REG_PIPE_CTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ +#define LINK_REG_PIPE_CTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ +#define LINK_REG_PIPE_CTR_PID_Pos (0UL) /* PID (Bit 0) */ +#define LINK_REG_PIPE_CTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ + +// DEVADD +#define LINK_REG_DEVADD_UPPHUB_Pos (11UL) /* UPPHUB (Bit 11) */ +#define LINK_REG_DEVADD_UPPHUB_Msk (0x7800UL) /* UPPHUB (Bitfield-Mask: 0x0f) */ +#define LINK_REG_DEVADD_HUBPORT_Pos (8UL) /* HUBPORT (Bit 8) */ +#define LINK_REG_DEVADD_HUBPORT_Msk (0x700UL) /* HUBPORT (Bitfield-Mask: 0x07) */ +#define LINK_REG_DEVADD_USBSPD_Pos (6UL) /* USBSPD (Bit 6) */ +#define LINK_REG_DEVADD_USBSPD_Msk (0xc0UL) /* USBSPD (Bitfield-Mask: 0x03) */ + +// USBBCCTRL0 +#define LINK_REG_USBBCCTRL0_PDDETSTS0_Pos (9UL) /* PDDETSTS0 (Bit 9) */ +#define LINK_REG_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /* PDDETSTS0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /* CHGDETSTS0 (Bit 8) */ +#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /* CHGDETSTS0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_BATCHGE0_Pos (7UL) /* BATCHGE0 (Bit 7) */ +#define LINK_REG_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /* BATCHGE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_VDMSRCE0_Pos (5UL) /* VDMSRCE0 (Bit 5) */ +#define LINK_REG_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /* VDMSRCE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_IDPSINKE0_Pos (4UL) /* IDPSINKE0 (Bit 4) */ +#define LINK_REG_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /* IDPSINKE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_VDPSRCE0_Pos (3UL) /* VDPSRCE0 (Bit 3) */ +#define LINK_REG_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /* VDPSRCE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_IDMSINKE0_Pos (2UL) /* IDMSINKE0 (Bit 2) */ +#define LINK_REG_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /* IDMSINKE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_IDPSRCE0_Pos (1UL) /* IDPSRCE0 (Bit 1) */ +#define LINK_REG_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /* IDPSRCE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBBCCTRL0_RPDME0_Pos (0UL) /* RPDME0 (Bit 0) */ +#define LINK_REG_USBBCCTRL0_RPDME0_Msk (0x1UL) /* RPDME0 (Bitfield-Mask: 0x01) */ + +// UCKSEL +#define LINK_REG_UCKSEL_UCKSELC_Pos (0UL) /* UCKSELC (Bit 0) */ +#define LINK_REG_UCKSEL_UCKSELC_Msk (0x1UL) /* UCKSELC (Bitfield-Mask: 0x01) */ + +// USBMC +#define LINK_REG_USBMC_VDCEN_Pos (7UL) /* VDCEN (Bit 7) */ +#define LINK_REG_USBMC_VDCEN_Msk (0x80UL) /* VDCEN (Bitfield-Mask: 0x01) */ +#define LINK_REG_USBMC_VDDUSBE_Pos (0UL) /* VDDUSBE (Bit 0) */ +#define LINK_REG_USBMC_VDDUSBE_Msk (0x1UL) /* VDDUSBE (Bitfield-Mask: 0x01) */ + +// PHYSLEW +#define LINK_REG_PHYSLEW_SLEWF01_Pos (3UL) /* SLEWF01 (Bit 3) */ +#define LINK_REG_PHYSLEW_SLEWF01_Msk (0x8UL) /* SLEWF01 (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSLEW_SLEWF00_Pos (2UL) /* SLEWF00 (Bit 2) */ +#define LINK_REG_PHYSLEW_SLEWF00_Msk (0x4UL) /* SLEWF00 (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSLEW_SLEWR01_Pos (1UL) /* SLEWR01 (Bit 1) */ +#define LINK_REG_PHYSLEW_SLEWR01_Msk (0x2UL) /* SLEWR01 (Bitfield-Mask: 0x01) */ +#define LINK_REG_PHYSLEW_SLEWR00_Pos (0UL) /* SLEWR00 (Bit 0) */ +#define LINK_REG_PHYSLEW_SLEWR00_Msk (0x1UL) /* SLEWR00 (Bitfield-Mask: 0x01) */ + +// LPCTRL +#define LINK_REG_LPCTRL_HWUPM_Pos (7UL) /* HWUPM (Bit 7) */ +#define LINK_REG_LPCTRL_HWUPM_Msk (0x80UL) /* HWUPM (Bitfield-Mask: 0x01) */ + +// LPSTS +#define LINK_REG_LPSTS_SUSPENDM_Pos (14UL) /* SUSPENDM (Bit 14) */ +#define LINK_REG_LPSTS_SUSPENDM_Msk (0x4000UL) /* SUSPENDM (Bitfield-Mask: 0x01) */ + +// BCCTRL +#define LINK_REG_BCCTRL_PDDETSTS_Pos (9UL) /* PDDETSTS (Bit 9) */ +#define LINK_REG_BCCTRL_PDDETSTS_Msk (0x200UL) /* PDDETSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_CHGDETSTS_Pos (8UL) /* CHGDETSTS (Bit 8) */ +#define LINK_REG_BCCTRL_CHGDETSTS_Msk (0x100UL) /* CHGDETSTS (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_DCPMODE_Pos (5UL) /* DCPMODE (Bit 5) */ +#define LINK_REG_BCCTRL_DCPMODE_Msk (0x20UL) /* DCPMODE (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_VDMSRCE_Pos (4UL) /* VDMSRCE (Bit 4) */ +#define LINK_REG_BCCTRL_VDMSRCE_Msk (0x10UL) /* VDMSRCE (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_IDPSINKE_Pos (3UL) /* IDPSINKE (Bit 3) */ +#define LINK_REG_BCCTRL_IDPSINKE_Msk (0x8UL) /* IDPSINKE (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_VDPSRCE_Pos (2UL) /* VDPSRCE (Bit 2) */ +#define LINK_REG_BCCTRL_VDPSRCE_Msk (0x4UL) /* VDPSRCE (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_IDMSINKE_Pos (1UL) /* IDMSINKE (Bit 1) */ +#define LINK_REG_BCCTRL_IDMSINKE_Msk (0x2UL) /* IDMSINKE (Bitfield-Mask: 0x01) */ +#define LINK_REG_BCCTRL_IDPSRCE_Pos (0UL) /* IDPSRCE (Bit 0) */ +#define LINK_REG_BCCTRL_IDPSRCE_Msk (0x1UL) /* IDPSRCE (Bitfield-Mask: 0x01) */ + +// PL1CTRL1 +#define LINK_REG_PL1CTRL1_L1EXTMD_Pos (14UL) /* L1EXTMD (Bit 14) */ +#define LINK_REG_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /* L1EXTMD (Bitfield-Mask: 0x01) */ +#define LINK_REG_PL1CTRL1_HIRDTHR_Pos (8UL) /* HIRDTHR (Bit 8) */ +#define LINK_REG_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /* HIRDTHR (Bitfield-Mask: 0x0f) */ +#define LINK_REG_PL1CTRL1_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ +#define LINK_REG_PL1CTRL1_DVSQ_Msk (0xf0UL) /* DVSQ (Bitfield-Mask: 0x0f) */ +#define LINK_REG_PL1CTRL1_L1NEGOMD_Pos (3UL) /* L1NEGOMD (Bit 3) */ +#define LINK_REG_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /* L1NEGOMD (Bitfield-Mask: 0x01) */ +#define LINK_REG_PL1CTRL1_L1RESPMD_Pos (1UL) /* L1RESPMD (Bit 1) */ +#define LINK_REG_PL1CTRL1_L1RESPMD_Msk (0x6UL) /* L1RESPMD (Bitfield-Mask: 0x03) */ +#define LINK_REG_PL1CTRL1_L1RESPEN_Pos (0UL) /* L1RESPEN (Bit 0) */ +#define LINK_REG_PL1CTRL1_L1RESPEN_Msk (0x1UL) /* L1RESPEN (Bitfield-Mask: 0x01) */ + +// PL1CTRL2 +#define LINK_REG_PL1CTRL2_RWEMON_Pos (12UL) /* RWEMON (Bit 12) */ +#define LINK_REG_PL1CTRL2_RWEMON_Msk (0x1000UL) /* RWEMON (Bitfield-Mask: 0x01) */ +#define LINK_REG_PL1CTRL2_HIRDMON_Pos (8UL) /* HIRDMON (Bit 8) */ +#define LINK_REG_PL1CTRL2_HIRDMON_Msk (0xf00UL) /* HIRDMON (Bitfield-Mask: 0x0f) */ + +// HL1CTRL1 +#define LINK_REG_HL1CTRL1_L1STATUS_Pos (1UL) /* L1STATUS (Bit 1) */ +#define LINK_REG_HL1CTRL1_L1STATUS_Msk (0x6UL) /* L1STATUS (Bitfield-Mask: 0x03) */ +#define LINK_REG_HL1CTRL1_L1REQ_Pos (0UL) /* L1REQ (Bit 0) */ +#define LINK_REG_HL1CTRL1_L1REQ_Msk (0x1UL) /* L1REQ (Bitfield-Mask: 0x01) */ + +// HL1CTRL2 +#define LINK_REG_HL1CTRL2_BESL_Pos (15UL) /* BESL (Bit 15) */ +#define LINK_REG_HL1CTRL2_BESL_Msk (0x8000UL) /* BESL (Bitfield-Mask: 0x01) */ +#define LINK_REG_HL1CTRL2_L1RWE_Pos (12UL) /* L1RWE (Bit 12) */ +#define LINK_REG_HL1CTRL2_L1RWE_Msk (0x1000UL) /* L1RWE (Bitfield-Mask: 0x01) */ +#define LINK_REG_HL1CTRL2_HIRD_Pos (8UL) /* HIRD (Bit 8) */ +#define LINK_REG_HL1CTRL2_HIRD_Msk (0xf00UL) /* HIRD (Bitfield-Mask: 0x0f) */ +#define LINK_REG_HL1CTRL2_L1ADDR_Pos (0UL) /* L1ADDR (Bit 0) */ +#define LINK_REG_HL1CTRL2_L1ADDR_Msk (0xfUL) /* L1ADDR (Bitfield-Mask: 0x0f) */ + +// DPUSR0R +#define LINK_REG_DPUSR0R_DVBSTSHM_Pos (23UL) /* DVBSTSHM (Bit 23) */ +#define LINK_REG_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_DOVCBHM_Pos (21UL) /* DOVCBHM (Bit 21) */ +#define LINK_REG_DPUSR0R_DOVCBHM_Msk (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_DOVCAHM_Pos (20UL) /* DOVCAHM (Bit 20) */ +#define LINK_REG_DPUSR0R_DOVCAHM_Msk (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */ + +// DPUSR1R +#define LINK_REG_DPUSR1R_DVBSTSH_Pos (23UL) /* DVBSTSH (Bit 23) */ +#define LINK_REG_DPUSR1R_DVBSTSH_Msk (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_DOVCBH_Pos (21UL) /* DOVCBH (Bit 21) */ +#define LINK_REG_DPUSR1R_DOVCBH_Msk (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_DOVCAH_Pos (20UL) /* DOVCAH (Bit 20) */ +#define LINK_REG_DPUSR1R_DOVCAH_Msk (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_DVBSTSHE_Pos (7UL) /* DVBSTSHE (Bit 7) */ +#define LINK_REG_DPUSR1R_DVBSTSHE_Msk (0x80UL) /* DVBSTSHE (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_DOVCBHE_Pos (5UL) /* DOVCBHE (Bit 5) */ +#define LINK_REG_DPUSR1R_DOVCBHE_Msk (0x20UL) /* DOVCBHE (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_DOVCAHE_Pos (4UL) /* DOVCAHE (Bit 4) */ +#define LINK_REG_DPUSR1R_DOVCAHE_Msk (0x10UL) /* DOVCAHE (Bitfield-Mask: 0x01) */ + +// DPUSR2R +#define LINK_REG_DPUSR2R_DMINTE_Pos (9UL) /* DMINTE (Bit 9) */ +#define LINK_REG_DPUSR2R_DMINTE_Msk (0x200UL) /* DMINTE (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR2R_DPINTE_Pos (8UL) /* DPINTE (Bit 8) */ +#define LINK_REG_DPUSR2R_DPINTE_Msk (0x100UL) /* DPINTE (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR2R_DMVAL_Pos (5UL) /* DMVAL (Bit 5) */ +#define LINK_REG_DPUSR2R_DMVAL_Msk (0x20UL) /* DMVAL (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR2R_DPVAL_Pos (4UL) /* DPVAL (Bit 4) */ +#define LINK_REG_DPUSR2R_DPVAL_Msk (0x10UL) /* DPVAL (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR2R_DMINT_Pos (1UL) /* DMINT (Bit 1) */ +#define LINK_REG_DPUSR2R_DMINT_Msk (0x2UL) /* DMINT (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR2R_DPINT_Pos (0UL) /* DPINT (Bit 0) */ +#define LINK_REG_DPUSR2R_DPINT_Msk (0x1UL) /* DPINT (Bitfield-Mask: 0x01) */ + +// DPUSRCR +#define LINK_REG_DPUSRCR_FIXPHYPD_Pos (1UL) /* FIXPHYPD (Bit 1) */ +#define LINK_REG_DPUSRCR_FIXPHYPD_Msk (0x2UL) /* FIXPHYPD (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSRCR_FIXPHY_Pos (0UL) /* FIXPHY (Bit 0) */ +#define LINK_REG_DPUSRCR_FIXPHY_Msk (0x1UL) /* FIXPHY (Bitfield-Mask: 0x01) */ + +// DPUSR0R_FS +#define LINK_REG_DPUSR0R_FS_DVBSTS0_Pos (23UL) /* DVBSTS0 (Bit 23) */ +#define LINK_REG_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_DOVCB0_Pos (21UL) /* DOVCB0 (Bit 21) */ +#define LINK_REG_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_DOVCA0_Pos (20UL) /* DOVCA0 (Bit 20) */ +#define LINK_REG_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_DM0_Pos (17UL) /* DM0 (Bit 17) */ +#define LINK_REG_DPUSR0R_FS_DM0_Msk (0x20000UL) /* DM0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_DP0_Pos (16UL) /* DP0 (Bit 16) */ +#define LINK_REG_DPUSR0R_FS_DP0_Msk (0x10000UL) /* DP0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_FIXPHY0_Pos (4UL) /* FIXPHY0 (Bit 4) */ +#define LINK_REG_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /* FIXPHY0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_DRPD0_Pos (3UL) /* DRPD0 (Bit 3) */ +#define LINK_REG_DPUSR0R_FS_DRPD0_Msk (0x8UL) /* DRPD0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_RPUE0_Pos (1UL) /* RPUE0 (Bit 1) */ +#define LINK_REG_DPUSR0R_FS_RPUE0_Msk (0x2UL) /* RPUE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR0R_FS_SRPC0_Pos (0UL) /* SRPC0 (Bit 0) */ +#define LINK_REG_DPUSR0R_FS_SRPC0_Msk (0x1UL) /* SRPC0 (Bitfield-Mask: 0x01) */ + +// DPUSR1R_FS +#define LINK_REG_DPUSR1R_FS_DVBINT0_Pos (23UL) /* DVBINT0 (Bit 23) */ +#define LINK_REG_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /* DOVRCRB0 (Bit 21) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /* DOVRCRA0 (Bit 20) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DMINT0_Pos (17UL) /* DMINT0 (Bit 17) */ +#define LINK_REG_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /* DMINT0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DPINT0_Pos (16UL) /* DPINT0 (Bit 16) */ +#define LINK_REG_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /* DPINT0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DVBSE0_Pos (7UL) /* DVBSE0 (Bit 7) */ +#define LINK_REG_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /* DVBSE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /* DOVRCRBE0 (Bit 5) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /* DOVRCRBE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /* DOVRCRAE0 (Bit 4) */ +#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /* DOVRCRAE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DMINTE0_Pos (1UL) /* DMINTE0 (Bit 1) */ +#define LINK_REG_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /* DMINTE0 (Bitfield-Mask: 0x01) */ +#define LINK_REG_DPUSR1R_FS_DPINTE0_Pos (0UL) /* DPINTE0 (Bit 0) */ +#define LINK_REG_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /* DPINTE0 (Bitfield-Mask: 0x01) */ + +/*--------------------------------------------------------------------*/ +/* Register Bit Utils */ +/*--------------------------------------------------------------------*/ +#define LINK_REG_PIPE_CTR_PID_NAK (0U << LINK_REG_PIPE_CTR_PID_Pos) /* NAK response */ +#define LINK_REG_PIPE_CTR_PID_BUF (1U << LINK_REG_PIPE_CTR_PID_Pos) /* BUF response (depends buffer state) */ +#define LINK_REG_PIPE_CTR_PID_STALL (2U << LINK_REG_PIPE_CTR_PID_Pos) /* STALL response */ + +#define LINK_REG_DVSTCTR0_RHST_LS (1U << LINK_REG_DVSTCTR0_RHST_Pos) /* Low-speed connection */ +#define LINK_REG_DVSTCTR0_RHST_FS (2U << LINK_REG_DVSTCTR0_RHST_Pos) /* Full-speed connection */ + +#define LINK_REG_DEVADD_USBSPD_LS (1U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Low-speed */ +#define LINK_REG_DEVADD_USBSPD_FS (2U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Full-speed */ + +#define LINK_REG_CFIFOSEL_ISEL_WRITE (1U << LINK_REG_CFIFOSEL_ISEL_Pos) /* FIFO write AKA TX*/ + +#define LINK_REG_FIFOSEL_BIGEND (1U << LINK_REG_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */ +#define LINK_REG_FIFOSEL_MBW_8BIT (0U << LINK_REG_CFIFOSEL_MBW_Pos) /* 8-bit width */ +#define LINK_REG_FIFOSEL_MBW_16BIT (1U << LINK_REG_CFIFOSEL_MBW_Pos) /* 16-bit width */ + +#define LINK_REG_INTSTS0_CTSQ_CTRL_RDATA (1U << LINK_REG_INTSTS0_CTSQ_Pos) + +#define LINK_REG_INTSTS0_DVSQ_STATE_DEF (1U << LINK_REG_INTSTS0_DVSQ_Pos) /* Default state */ +#define LINK_REG_INTSTS0_DVSQ_STATE_ADDR (2U << LINK_REG_INTSTS0_DVSQ_Pos) /* Address state */ +#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP0 (4U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ +#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP1 (5U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ +#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP2 (6U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ +#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP3 (7U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ + +#define LINK_REG_PIPECFG_TYPE_BULK (1U << LINK_REG_PIPECFG_TYPE_Pos) +#define LINK_REG_PIPECFG_TYPE_INT (2U << LINK_REG_PIPECFG_TYPE_Pos) +#define LINK_REG_PIPECFG_TYPE_ISO (3U << LINK_REG_PIPECFG_TYPE_Pos) + +//--------------------------------------------------------------------+ +// Static Assert +//--------------------------------------------------------------------+ + +TU_VERIFY_STATIC(sizeof(LINK_REG_PIPE_TR_t) == 4, "incorrect size"); + +TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSCFG ) == 0x00000000, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BUSWAIT ) == 0x00000002, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSSTS0 ) == 0x00000004, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PLLSTA ) == 0x00000006, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DVSTCTR0 ) == 0x00000008, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, TESTMODE ) == 0x0000000C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFO ) == 0x00000014, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFO ) == 0x00000018, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFO ) == 0x0000001C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOSEL ) == 0x00000020, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOCTR ) == 0x00000022, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOSEL ) == 0x00000028, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOCTR ) == 0x0000002A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOSEL ) == 0x0000002C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOCTR ) == 0x0000002E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB0 ) == 0x00000030, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB1 ) == 0x00000032, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYENB ) == 0x00000036, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYENB ) == 0x00000038, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPENB ) == 0x0000003A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, SOFCFG ) == 0x0000003C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSET ) == 0x0000003E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS0 ) == 0x00000040, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS1 ) == 0x00000042, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYSTS ) == 0x00000046, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYSTS ) == 0x00000048, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPSTS ) == 0x0000004A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, FRMNUM ) == 0x0000004C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, UFRMNUM ) == 0x0000004E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBADDR ) == 0x00000050, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBREQ ) == 0x00000054, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBVAL ) == 0x00000056, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBINDX ) == 0x00000058, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBLENG ) == 0x0000005A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCFG ) == 0x0000005C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPMAXP ) == 0x0000005E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCTR ) == 0x00000060, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPESEL ) == 0x00000064, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPECFG ) == 0x00000068, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEMAXP ) == 0x0000006C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEPERI ) == 0x0000006E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_CTR ) == 0x00000070, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_TR ) == 0x00000090, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBBCCTRL0 ) == 0x000000B0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, UCKSEL ) == 0x000000C4, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBMC ) == 0x000000CC, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DEVADD ) == 0x000000D0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSLEW ) == 0x000000F0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPCTRL ) == 0x00000100, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPSTS ) == 0x00000102, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, BCCTRL ) == 0x00000140, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL1 ) == 0x00000144, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL2 ) == 0x00000146, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL1 ) == 0x00000148, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL2 ) == 0x0000014A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R ) == 0x00000160, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R ) == 0x00000164, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR2R ) == 0x00000168, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSRCR ) == 0x0000016A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R_FS ) == 0x00000400, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect offset"); + +#ifdef __cplusplus +} +#endif + +#endif /* _TUSB_LINK_TYPE_H_ */ -- cgit v1.3.1 From 92aed7e3e0600570da239729d1e83ede69be8158 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 16 Mar 2023 11:28:10 +0700 Subject: rename symbols --- docs/reference/supported.rst | 4 +- src/portable/renesas/rusb2/dcd_rusb2.c | 276 ++++---- src/portable/renesas/rusb2/hcd_rusb2.c | 294 ++++---- src/portable/renesas/rusb2/rusb2_ra.h | 10 +- src/portable/renesas/rusb2/rusb2_rx.h | 8 +- src/portable/renesas/rusb2/rusb2_type.h | 1138 +++++++++++++++---------------- 6 files changed, 864 insertions(+), 866 deletions(-) (limited to 'src') diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index 30a685854..ae16d361d 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -62,9 +62,9 @@ Supported MCUs +--------------+---------+-------------+--------+------+-----------+-------------------+--------------+ | Raspberry Pi | RP2040 | ✔ | ✔ | ✖ | rp2040, pio_usb | | +--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+ -| Renesas | RX | 63N, 65N, 72N | ✔ | ✔ | ✖ | link | | +| Renesas | RX | 63N, 65N, 72N | ✔ | ✔ | ✖ | rusb2 | | | +-----+-----------------+--------+------+-----------+-------------------+--------------+ -| | RA | XXX | ✔ | ✔ | | link | | +| | RA | XXX | ✔ | ✔ | | rusb2 | | +--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+ | Silabs | EFM32GG12 | ✔ | | ✖ | dwc2 | | +--------------+-----------------------+--------+------+-----------+-------------------+--------------+ diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index ec9caab2c..78584125f 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -51,9 +51,9 @@ /* LINK core registers */ #if defined(__CCRX__) -#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE) + #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE) #else -#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE) + #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE) #endif /* Start of definition of packed structs (used by the CCRX toolchain) */ @@ -138,9 +138,9 @@ static unsigned find_pipe(unsigned xfer) static volatile uint16_t* get_pipectr(unsigned num) { if (num) { - return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]); + return (volatile uint16_t*)&(RUSB2->PIPE_CTR[num - 1]); } else { - return (volatile uint16_t*)&(LINK_REG->DCPCTR); + return (volatile uint16_t*)&(RUSB2->DCPCTR); } } @@ -148,7 +148,7 @@ static volatile reg_pipetre_t* get_pipetre(unsigned num) { volatile reg_pipetre_t* tre = NULL; if ((1 <= num) && (num <= 5)) { - tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E); + tre = (volatile reg_pipetre_t*)&(RUSB2->PIPE_TR[num - 1].E); } return tre; } @@ -168,19 +168,19 @@ static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr) static unsigned edpt0_max_packet_size(void) { - return LINK_REG->DCPMAXP_b.MXPS; + return RUSB2->DCPMAXP_b.MXPS; } static unsigned edpt_max_packet_size(unsigned num) { - LINK_REG->PIPESEL = num; - return LINK_REG->PIPEMAXP; + RUSB2->PIPESEL = num; + return RUSB2->PIPEMAXP; } static inline void pipe_wait_for_ready(unsigned num) { - while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ; - while (!LINK_REG->D0FIFOCTR_b.FRDY) ; + while (RUSB2->D0FIFOSEL_b.CURPIPE != num) ; + while (!RUSB2->D0FIFOCTR_b.FRDY) ; } static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) @@ -242,14 +242,14 @@ static bool pipe0_xfer_in(void) void *buf = pipe->buf; if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->CFIFO, len, TUSB_DIR_IN); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->CFIFO, len, TUSB_DIR_IN); } else { - pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); + pipe_write_packet(buf, (volatile void*)&RUSB2->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } } if (len < mps) { - LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; } pipe->remaining = rem - len; return false; @@ -261,19 +261,19 @@ static bool pipe0_xfer_out(void) const unsigned rem = pipe->remaining; const unsigned mps = edpt0_max_packet_size(); - const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN; + const unsigned vld = RUSB2->CFIFOCTR_b.DTLN; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->CFIFO, len, TUSB_DIR_OUT); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->CFIFO, len, TUSB_DIR_OUT); } else { - pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); + pipe_read_packet(buf, (volatile void*)&RUSB2->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } } if (len < mps) { - LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; + RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; } pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { @@ -293,24 +293,24 @@ static bool pipe_xfer_in(unsigned num) return true; } - LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); + RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); const unsigned mps = edpt_max_packet_size(num); pipe_wait_for_ready(num); const unsigned len = TU_MIN(rem, mps); void *buf = pipe->buf; if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->D0FIFO, len, TUSB_DIR_IN); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->D0FIFO, len, TUSB_DIR_IN); } else { - pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); + pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } } if (len < mps) { - LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; } - LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + RUSB2->D0FIFOSEL = 0; + while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; return false; } @@ -320,25 +320,25 @@ static bool pipe_xfer_out(unsigned num) pipe_state_t *pipe = &_dcd.pipe[num]; const unsigned rem = pipe->remaining; - LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT; + RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT; const unsigned mps = edpt_max_packet_size(num); pipe_wait_for_ready(num); - const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN; + const unsigned vld = RUSB2->D0FIFOCTR_b.DTLN; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->D0FIFO, len, TUSB_DIR_OUT); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->D0FIFO, len, TUSB_DIR_OUT); } else { - pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); + pipe_read_packet(buf, (volatile void*)&RUSB2->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } } if (len < mps) { - LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; + RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; } - LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + RUSB2->D0FIFOSEL = 0; + while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; @@ -350,13 +350,13 @@ static bool pipe_xfer_out(unsigned num) static void process_setup_packet(uint8_t rhport) { uint16_t setup_packet[4]; - if (0 == (LINK_REG->INTSTS0 & LINK_REG_INTSTS0_VALID_Msk)) return; - LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; - setup_packet[0] = tu_le16toh(LINK_REG->USBREQ); - setup_packet[1] = LINK_REG->USBVAL; - setup_packet[2] = LINK_REG->USBINDX; - setup_packet[3] = LINK_REG->USBLENG; - LINK_REG->INTSTS0 = ~((uint16_t)LINK_REG_INTSTS0_VALID_Msk); + if (0 == (RUSB2->INTSTS0 & RUSB2_INTSTS0_VALID_Msk)) return; + RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; + setup_packet[0] = tu_le16toh(RUSB2->USBREQ); + setup_packet[1] = RUSB2->USBVAL; + setup_packet[2] = RUSB2->USBINDX; + setup_packet[3] = RUSB2->USBLENG; + RUSB2->INTSTS0 = ~((uint16_t)RUSB2_INTSTS0_VALID_Msk); dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true); } @@ -364,7 +364,7 @@ static void process_status_completion(uint8_t rhport) { uint8_t ep_addr; /* Check the data stage direction */ - if (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) { + if (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) { /* IN transfer. */ ep_addr = tu_edpt_addr(0, TUSB_DIR_IN); } else { @@ -378,12 +378,12 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u { /* configure fifo direction and access unit settings */ if (ep_addr) { /* IN, 2 bytes */ - LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT | - (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); - while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ; + RUSB2->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT | + (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); + while (!(RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ; } else { /* OUT, a byte */ - LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT; - while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ; + RUSB2->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT; + while (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ; } pipe_state_t *pipe = &_dcd.pipe[0]; @@ -393,14 +393,14 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u if (total_bytes) { pipe->buf = buffer; if (ep_addr) { /* IN */ - TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80)); + TU_ASSERT(RUSB2->DCPCTR_b.BSTS && (RUSB2->USBREQ & 0x80)); pipe0_xfer_in(); } - LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF; + RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF; } else { /* ZLP */ pipe->buf = NULL; - LINK_REG->DCPCTR = LINK_REG_DCPCTR_CCPL_Msk | LINK_REG_PIPE_CTR_PID_BUF; + RUSB2->DCPCTR = RUSB2_DCPCTR_CCPL_Msk | RUSB2_PIPE_CTR_PID_BUF; } return true; } @@ -422,11 +422,11 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui if (total_bytes) { pipe_xfer_in(num); } else { /* ZLP */ - LINK_REG->D0FIFOSEL = num; + RUSB2->D0FIFOSEL = num; pipe_wait_for_ready(num); - LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; - LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + RUSB2->D0FIFOSEL = 0; + while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ } } else { #if defined(__CCRX__) @@ -437,11 +437,11 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui if (pt) { const unsigned mps = edpt_max_packet_size(num); volatile uint16_t *ctr = get_pipectr(num); - if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK; + if (*ctr & 0x3) *ctr = RUSB2_PIPE_CTR_PID_NAK; pt->TRE = TU_BIT(8); pt->TRN = (total_bytes + mps - 1) / mps; pt->TRENB = 1; - *ctr = LINK_REG_PIPE_CTR_PID_BUF; + *ctr = RUSB2_PIPE_CTR_PID_BUF; } } // TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type); @@ -493,28 +493,28 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num) static void process_bus_reset(uint8_t rhport) { - LINK_REG->BEMPENB = 1; - LINK_REG->BRDYENB = 1; - LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; - LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - LINK_REG->D1FIFOSEL = 0; - while (LINK_REG->D1FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&LINK_REG->PIPE_CTR[0])); - volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&LINK_REG->PIPE_TR[0].E)); + RUSB2->BEMPENB = 1; + RUSB2->BRDYENB = 1; + RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; + RUSB2->D0FIFOSEL = 0; + while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + RUSB2->D1FIFOSEL = 0; + while (RUSB2->D1FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&RUSB2->PIPE_CTR[0])); + volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&RUSB2->PIPE_TR[0].E)); for (int i = 1; i <= 5; ++i) { - LINK_REG->PIPESEL = i; - LINK_REG->PIPECFG = 0; - *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk; + RUSB2->PIPESEL = i; + RUSB2->PIPECFG = 0; + *ctr = RUSB2_PIPE_CTR_ACLRM_Msk; *ctr = 0; ++ctr; *tre = TU_BIT(8); tre += 2; } for (int i = 6; i <= 9; ++i) { - LINK_REG->PIPESEL = i; - LINK_REG->PIPECFG = 0; - *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk; + RUSB2->PIPESEL = i; + RUSB2->PIPECFG = 0; + *ctr = RUSB2_PIPE_CTR_ACLRM_Msk; *ctr = 0; ++ctr; } @@ -524,7 +524,7 @@ static void process_bus_reset(uint8_t rhport) static void process_set_address(uint8_t rhport) { - const uint32_t addr = LINK_REG->USBADDR_b.USBADDR; + const uint32_t addr = RUSB2->USBADDR_b.USBADDR; if (!addr) return; const tusb_control_request_t setup_packet = { #if defined(__CCRX__) @@ -580,39 +580,39 @@ void dcd_init(uint8_t rhport) enable_interrupt(pswi); #endif - LINK_REG->SYSCFG_b.SCKE = 1; - while (!LINK_REG->SYSCFG_b.SCKE) ; - LINK_REG->SYSCFG_b.DRPD = 0; - LINK_REG->SYSCFG_b.DCFM = 0; - LINK_REG->SYSCFG_b.USBE = 1; + RUSB2->SYSCFG_b.SCKE = 1; + while (!RUSB2->SYSCFG_b.SCKE) ; + RUSB2->SYSCFG_b.DRPD = 0; + RUSB2->SYSCFG_b.DCFM = 0; + RUSB2->SYSCFG_b.USBE = 1; // MCU specific PHY init - link_phy_init(); + rusb2_phy_init(); - LINK_REG->PHYSLEW = 0x5; - LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */ + RUSB2->PHYSLEW = 0x5; + RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */ /* Setup default control pipe */ - LINK_REG->DCPMAXP_b.MXPS = 64; - LINK_REG->INTENB0 = LINK_REG_INTSTS0_VBINT_Msk | LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk | - LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_CTRT_Msk | (USE_SOF ? LINK_REG_INTSTS0_SOFR_Msk : 0) | - LINK_REG_INTSTS0_RESM_Msk; - LINK_REG->BEMPENB = 1; - LINK_REG->BRDYENB = 1; - - if (LINK_REG->INTSTS0_b.VBSTS) { + RUSB2->DCPMAXP_b.MXPS = 64; + RUSB2->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk | + RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) | + RUSB2_INTSTS0_RESM_Msk; + RUSB2->BEMPENB = 1; + RUSB2->BRDYENB = 1; + + if (RUSB2->INTSTS0_b.VBSTS) { dcd_connect(rhport); } } void dcd_int_enable(uint8_t rhport) { - link_int_enable(rhport); + rusb2_int_enable(rhport); } void dcd_int_disable(uint8_t rhport) { - link_int_disable(rhport); + rusb2_int_disable(rhport); } void dcd_set_address(uint8_t rhport, uint8_t dev_addr) @@ -624,19 +624,19 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) void dcd_remote_wakeup(uint8_t rhport) { (void)rhport; - LINK_REG->DVSTCTR0_b.WKUP = 1; + RUSB2->DVSTCTR0_b.WKUP = 1; } void dcd_connect(uint8_t rhport) { (void)rhport; - LINK_REG->SYSCFG_b.DPRPU = 1; + RUSB2->SYSCFG_b.DPRPU = 1; } void dcd_disconnect(uint8_t rhport) { (void)rhport; - LINK_REG->SYSCFG_b.DPRPU = 0; + RUSB2->SYSCFG_b.DPRPU = 0; } void dcd_sof_enable(uint8_t rhport, bool en) @@ -672,26 +672,26 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) /* setup pipe */ dcd_int_disable(rhport); - LINK_REG->PIPESEL = num; - LINK_REG->PIPEMAXP = mps; + RUSB2->PIPESEL = num; + RUSB2->PIPEMAXP = mps; volatile uint16_t *ctr = get_pipectr(num); - *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk; + *ctr = RUSB2_PIPE_CTR_ACLRM_Msk | RUSB2_PIPE_CTR_SQCLR_Msk; *ctr = 0; unsigned cfg = (dir << 4) | epn; if (xfer == TUSB_XFER_BULK) { - cfg |= (LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk); + cfg |= (RUSB2_PIPECFG_TYPE_BULK | RUSB2_PIPECFG_SHTNAK_Msk | RUSB2_PIPECFG_DBLB_Msk); } else if (xfer == TUSB_XFER_INTERRUPT) { - cfg |= LINK_REG_PIPECFG_TYPE_INT; + cfg |= RUSB2_PIPECFG_TYPE_INT; } else { - cfg |= (LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk); + cfg |= (RUSB2_PIPECFG_TYPE_ISO | RUSB2_PIPECFG_DBLB_Msk); } - LINK_REG->PIPECFG = cfg; - LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num); - LINK_REG->BRDYENB |= TU_BIT(num); + RUSB2->PIPECFG = cfg; + RUSB2->BRDYSTS = 0x1FFu ^ TU_BIT(num); + RUSB2->BRDYENB |= TU_BIT(num); if (dir || (xfer != TUSB_XFER_BULK)) { - *ctr = LINK_REG_PIPE_CTR_PID_BUF; + *ctr = RUSB2_PIPE_CTR_PID_BUF; } - // TU_LOG1("O %d %x %x\r\n", LINK_REG->PIPESEL, LINK_REG->PIPECFG, LINK_REG->PIPEMAXP); + // TU_LOG1("O %d %x %x\r\n", RUSB2->PIPESEL, RUSB2->PIPECFG, RUSB2->PIPEMAXP); dcd_int_enable(rhport); return true; @@ -716,11 +716,11 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) const unsigned dir = tu_edpt_dir(ep_addr); const unsigned num = _dcd.ep[dir][epn]; - LINK_REG->BRDYENB &= ~TU_BIT(num); + RUSB2->BRDYENB &= ~TU_BIT(num); volatile uint16_t *ctr = get_pipectr(num); *ctr = 0; - LINK_REG->PIPESEL = num; - LINK_REG->PIPECFG = 0; + RUSB2->PIPESEL = num; + RUSB2->PIPECFG = 0; _dcd.pipe[num].ep = 0; _dcd.ep[dir][epn] = 0; } @@ -751,8 +751,8 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) if (!ctr) return; dcd_int_disable(rhport); const uint32_t pid = *ctr & 0x3; - *ctr = pid | LINK_REG_PIPE_CTR_PID_STALL; - *ctr = LINK_REG_PIPE_CTR_PID_STALL; + *ctr = pid | RUSB2_PIPE_CTR_PID_STALL; + *ctr = RUSB2_PIPE_CTR_PID_STALL; dcd_int_enable(rhport); } @@ -761,15 +761,15 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr); if (!ctr) return; dcd_int_disable(rhport); - *ctr = LINK_REG_PIPE_CTR_SQCLR_Msk; + *ctr = RUSB2_PIPE_CTR_SQCLR_Msk; if (tu_edpt_dir(ep_addr)) { /* IN */ - *ctr = LINK_REG_PIPE_CTR_PID_BUF; + *ctr = RUSB2_PIPE_CTR_PID_BUF; } else { const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)]; - LINK_REG->PIPESEL = num; - if (LINK_REG->PIPECFG_b.TYPE != 1) { - *ctr = LINK_REG_PIPE_CTR_PID_BUF; + RUSB2->PIPESEL = num; + if (RUSB2->PIPECFG_b.TYPE != 1) { + *ctr = RUSB2_PIPE_CTR_PID_BUF; } } dcd_int_enable(rhport); @@ -782,71 +782,71 @@ void dcd_int_handler(uint8_t rhport) { (void)rhport; - unsigned is0 = LINK_REG->INTSTS0; + unsigned is0 = RUSB2->INTSTS0; /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ - LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_CTRT_Msk | LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_SOFR_Msk | - LINK_REG_INTSTS0_RESM_Msk | LINK_REG_INTSTS0_VBINT_Msk) & is0) | LINK_REG_INTSTS0_VALID_Msk; - if (is0 & LINK_REG_INTSTS0_VBINT_Msk) { - if (LINK_REG->INTSTS0_b.VBSTS) { + RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_CTRT_Msk | RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_SOFR_Msk | + RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_VBINT_Msk) & is0) | RUSB2_INTSTS0_VALID_Msk; + if (is0 & RUSB2_INTSTS0_VBINT_Msk) { + if (RUSB2->INTSTS0_b.VBSTS) { dcd_connect(rhport); } else { dcd_disconnect(rhport); } } - if (is0 & LINK_REG_INTSTS0_RESM_Msk) { + if (is0 & RUSB2_INTSTS0_RESM_Msk) { dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); #if (0==USE_SOF) - LINK_REG->INTENB0_b.SOFE = 0; + RUSB2->INTENB0_b.SOFE = 0; #endif } - if ((is0 & LINK_REG_INTSTS0_SOFR_Msk) && LINK_REG->INTENB0_b.SOFE) { + if ((is0 & RUSB2_INTSTS0_SOFR_Msk) && RUSB2->INTENB0_b.SOFE) { // USBD will exit suspended mode when SOF event is received dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); #if (0 == USE_SOF) - LINK_REG->INTENB0_b.SOFE = 0; + RUSB2->INTENB0_b.SOFE = 0; #endif } - if (is0 & LINK_REG_INTSTS0_DVST_Msk) { - switch (is0 & LINK_REG_INTSTS0_DVSQ_Msk) { - case LINK_REG_INTSTS0_DVSQ_STATE_DEF: + if (is0 & RUSB2_INTSTS0_DVST_Msk) { + switch (is0 & RUSB2_INTSTS0_DVSQ_Msk) { + case RUSB2_INTSTS0_DVSQ_STATE_DEF: process_bus_reset(rhport); break; - case LINK_REG_INTSTS0_DVSQ_STATE_ADDR: + case RUSB2_INTSTS0_DVSQ_STATE_ADDR: process_set_address(rhport); break; - case LINK_REG_INTSTS0_DVSQ_STATE_SUSP0: - case LINK_REG_INTSTS0_DVSQ_STATE_SUSP1: - case LINK_REG_INTSTS0_DVSQ_STATE_SUSP2: - case LINK_REG_INTSTS0_DVSQ_STATE_SUSP3: + case RUSB2_INTSTS0_DVSQ_STATE_SUSP0: + case RUSB2_INTSTS0_DVSQ_STATE_SUSP1: + case RUSB2_INTSTS0_DVSQ_STATE_SUSP2: + case RUSB2_INTSTS0_DVSQ_STATE_SUSP3: dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); #if (0==USE_SOF) - LINK_REG->INTENB0_b.SOFE = 1; + RUSB2->INTENB0_b.SOFE = 1; #endif default: break; } } - if (is0 & LINK_REG_INTSTS0_CTRT_Msk) { - if (is0 & LINK_REG_INTSTS0_CTSQ_CTRL_RDATA) { + if (is0 & RUSB2_INTSTS0_CTRT_Msk) { + if (is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA) { /* A setup packet has been received. */ process_setup_packet(rhport); - } else if (0 == (is0 & LINK_REG_INTSTS0_CTSQ_Msk)) { + } else if (0 == (is0 & RUSB2_INTSTS0_CTSQ_Msk)) { /* A ZLP has been sent/received. */ process_status_completion(rhport); } } - if (is0 & LINK_REG_INTSTS0_BEMP_Msk) { - const unsigned s = LINK_REG->BEMPSTS; - LINK_REG->BEMPSTS = 0; + if (is0 & RUSB2_INTSTS0_BEMP_Msk) { + const unsigned s = RUSB2->BEMPSTS; + RUSB2->BEMPSTS = 0; if (s & 1) { process_pipe0_bemp(rhport); } } - if (is0 & LINK_REG_INTSTS0_BRDY_Msk) { - const unsigned m = LINK_REG->BRDYENB; - unsigned s = LINK_REG->BRDYSTS & m; + if (is0 & RUSB2_INTSTS0_BRDY_Msk) { + const unsigned m = RUSB2->BRDYENB; + unsigned s = RUSB2->BRDYSTS & m; /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ - LINK_REG->BRDYSTS = ~s; + RUSB2->BRDYSTS = ~s; while (s) { #if defined(__CCRX__) static const int Mod37BitPosition[] = { diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 7d14aad60..e4743223e 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -47,9 +47,9 @@ /* LINK core registers */ #if defined(__CCRX__) -#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE) + #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE) #else -#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE) + #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE) #endif TU_ATTR_PACKED_BEGIN @@ -135,9 +135,9 @@ static unsigned find_pipe(unsigned xfer) static volatile uint16_t* get_pipectr(unsigned num) { if (num) { - return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]); + return (volatile uint16_t*)&(RUSB2->PIPE_CTR[num - 1]); } else { - return (volatile uint16_t*)&(LINK_REG->DCPCTR); + return (volatile uint16_t*)&(RUSB2->DCPCTR); } } @@ -145,7 +145,7 @@ static volatile reg_pipetre_t* get_pipetre(unsigned num) { volatile reg_pipetre_t* tre = NULL; if ((1 <= num) && (num <= 5)) { - tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E); + tre = (volatile reg_pipetre_t*)&(RUSB2->PIPE_TR[num - 1].E); } return tre; } @@ -164,19 +164,19 @@ static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr) static unsigned edpt0_max_packet_size(void) { - return LINK_REG->DCPMAXP_b.MXPS; + return RUSB2->DCPMAXP_b.MXPS; } static unsigned edpt_max_packet_size(unsigned num) { - LINK_REG->PIPESEL = num; - return LINK_REG->PIPEMAXP_b.MXPS; + RUSB2->PIPESEL = num; + return RUSB2->PIPEMAXP_b.MXPS; } static inline void pipe_wait_for_ready(unsigned num) { - while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ; - while (!LINK_REG->D0FIFOCTR_b.FRDY) ; + while (RUSB2->D0FIFOSEL_b.CURPIPE != num) ; + while (!RUSB2->D0FIFOCTR_b.FRDY) ; } static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) @@ -207,23 +207,23 @@ static bool pipe0_xfer_in(void) const unsigned rem = pipe->remaining; const unsigned mps = edpt0_max_packet_size(); - const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN; + const unsigned vld = RUSB2->CFIFOCTR_b.DTLN; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { - LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; - pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); + RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; + pipe_read_packet(buf, (volatile void*)&RUSB2->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } if (len < mps) { - LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; + RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; } pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; return true; } - LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF; + RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF; return false; } @@ -239,11 +239,11 @@ static bool pipe0_xfer_out(void) const unsigned len = TU_MIN(mps, rem); void *buf = pipe->buf; if (len) { - pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len); + pipe_write_packet(buf, (volatile void*)&RUSB2->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } if (len < mps) { - LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; } pipe->remaining = rem - len; return false; @@ -254,21 +254,21 @@ static bool pipe_xfer_in(unsigned num) pipe_state_t *pipe = &_hcd.pipe[num]; const unsigned rem = pipe->remaining; - LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT; + RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT; const unsigned mps = edpt_max_packet_size(num); pipe_wait_for_ready(num); - const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN; + const unsigned vld = RUSB2->D0FIFOCTR_b.DTLN; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { - pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); + pipe_read_packet(buf, (volatile void*)&RUSB2->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } if (len < mps) { - LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk; + RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; } - LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + RUSB2->D0FIFOSEL = 0; + while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; @@ -287,19 +287,19 @@ static bool pipe_xfer_out(unsigned num) return true; } - LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); + RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); const unsigned mps = edpt_max_packet_size(num); pipe_wait_for_ready(num); const unsigned len = TU_MIN(rem, mps); void *buf = pipe->buf; if (len) { - pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len); + pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } if (len < mps) - LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; - LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + RUSB2->D0FIFOSEL = 0; + while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; return false; } @@ -311,12 +311,12 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, /* configure fifo direction and access unit settings */ if (dir_in) { /* IN, a byte */ - LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT; - while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ; + RUSB2->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT; + while (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ; } else { /* OUT, 2 bytes */ - LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT | - (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0); - while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ; + RUSB2->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT | + (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); + while (!(RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ; } pipe_state_t *pipe = &_hcd.pipe[0]; @@ -326,21 +326,21 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, if (buflen) { pipe->buf = buffer; if (!dir_in) { /* OUT */ - TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80)); + TU_ASSERT(RUSB2->DCPCTR_b.BSTS && (RUSB2->USBREQ & 0x80)); pipe0_xfer_out(); } } else { /* ZLP */ pipe->buf = NULL; if (!dir_in) { /* OUT */ - LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; + RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; } - if (dir_in == LINK_REG->DCPCFG_b.DIR) { - TU_ASSERT(LINK_REG_PIPE_CTR_PID_NAK == LINK_REG->DCPCTR_b.PID); - LINK_REG->DCPCTR_b.SQSET = 1; - LINK_REG->DCPCFG_b.DIR = dir_in ^ 1; + if (dir_in == RUSB2->DCPCFG_b.DIR) { + TU_ASSERT(RUSB2_PIPE_CTR_PID_NAK == RUSB2->DCPCTR_b.PID); + RUSB2->DCPCTR_b.SQSET = 1; + RUSB2->DCPCFG_b.DIR = dir_in ^ 1; } } - LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF; + RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF; return true; } @@ -360,23 +360,23 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u if (buflen) { pipe_xfer_out(num); } else { /* ZLP */ - LINK_REG->D0FIFOSEL = num; + RUSB2->D0FIFOSEL = num; pipe_wait_for_ready(num); - LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk; - LINK_REG->D0FIFOSEL = 0; - while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + RUSB2->D0FIFOSEL = 0; + while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ } } else { volatile uint16_t *ctr = get_pipectr(num); volatile reg_pipetre_t *pt = get_pipetre(num); if (pt) { const unsigned mps = edpt_max_packet_size(num); - if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK; + if (*ctr & 0x3) *ctr = RUSB2_PIPE_CTR_PID_NAK; pt->TRE = TU_BIT(8); pt->TRN = (buflen + mps - 1) / mps; pt->TRENB = 1; } - *ctr = LINK_REG_PIPE_CTR_PID_BUF; + *ctr = RUSB2_PIPE_CTR_PID_BUF; } return true; } @@ -410,10 +410,10 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num) unsigned result; uint16_t volatile *ctr = get_pipectr(num); // TU_LOG1("NRDY %d %x\n", num, *ctr); - switch (*ctr & LINK_REG_PIPE_CTR_PID_Msk) { + switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) { default: return; - case LINK_REG_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break; - case LINK_REG_PIPE_CTR_PID_NAK: result = XFER_RESULT_FAILED; break; + case RUSB2_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break; + case RUSB2_PIPE_CTR_PID_NAK: result = XFER_RESULT_FAILED; break; } pipe_state_t *pipe = &_hcd.pipe[num]; hcd_event_xfer_complete(pipe->dev, pipe->ep, @@ -485,44 +485,44 @@ bool hcd_init(uint8_t rhport) enable_interrupt(pswi); #endif - LINK_REG->SYSCFG_b.SCKE = 1; - while (!LINK_REG->SYSCFG_b.SCKE) ; - LINK_REG->SYSCFG_b.DPRPU = 0; - LINK_REG->SYSCFG_b.DRPD = 0; - LINK_REG->SYSCFG_b.DCFM = 1; + RUSB2->SYSCFG_b.SCKE = 1; + while (!RUSB2->SYSCFG_b.SCKE) ; + RUSB2->SYSCFG_b.DPRPU = 0; + RUSB2->SYSCFG_b.DRPD = 0; + RUSB2->SYSCFG_b.DCFM = 1; - LINK_REG->DVSTCTR0_b.VBUSEN = 1; + RUSB2->DVSTCTR0_b.VBUSEN = 1; - LINK_REG->SYSCFG_b.DRPD = 1; + RUSB2->SYSCFG_b.DRPD = 1; for (volatile int i = 0; i < 30000; ++i) ; - LINK_REG->SYSCFG_b.USBE = 1; + RUSB2->SYSCFG_b.USBE = 1; // MCU specific PHY init - link_phy_init(); + rusb2_phy_init(); - LINK_REG->PHYSLEW = 0x5; - LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */ + RUSB2->PHYSLEW = 0x5; + RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */ /* Setup default control pipe */ - LINK_REG->DCPCFG = LINK_REG_PIPECFG_SHTNAK_Msk; - LINK_REG->DCPMAXP = 64; - LINK_REG->INTENB0 = LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk; - LINK_REG->INTENB1 = LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk; - LINK_REG->BEMPENB = 1; - LINK_REG->NRDYENB = 1; - LINK_REG->BRDYENB = 1; + RUSB2->DCPCFG = RUSB2_PIPECFG_SHTNAK_Msk; + RUSB2->DCPMAXP = 64; + RUSB2->INTENB0 = RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk; + RUSB2->INTENB1 = RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk; + RUSB2->BEMPENB = 1; + RUSB2->NRDYENB = 1; + RUSB2->BRDYENB = 1; return true; } void hcd_int_enable(uint8_t rhport) { - link_int_enable(rhport); + rusb2_int_enable(rhport); } void hcd_int_disable(uint8_t rhport) { - link_int_disable(rhport); + rusb2_int_disable(rhport); } uint32_t hcd_frame_number(uint8_t rhport) @@ -531,7 +531,7 @@ uint32_t hcd_frame_number(uint8_t rhport) /* The device must be reset at least once after connection * in order to start the frame counter. */ if (_hcd.need_reset) hcd_port_reset(rhport); - return LINK_REG->FRMNUM_b.FRNM; + return RUSB2->FRMNUM_b.FRNM; } /*--------------------------------------------------------------------+ @@ -540,24 +540,24 @@ uint32_t hcd_frame_number(uint8_t rhport) bool hcd_port_connect_status(uint8_t rhport) { (void)rhport; - return LINK_REG->INTSTS1_b.ATTCH ? true : false; + return RUSB2->INTSTS1_b.ATTCH ? true : false; } void hcd_port_reset(uint8_t rhport) { - LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; - while (LINK_REG->DCPCTR_b.PBUSY) ; + RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; + while (RUSB2->DCPCTR_b.PBUSY) ; hcd_int_disable(rhport); - LINK_REG->DVSTCTR0_b.UACT = 0; - if (LINK_REG->DCPCTR_b.SUREQ) { - LINK_REG->DCPCTR_b.SUREQCLR = 1; + RUSB2->DVSTCTR0_b.UACT = 0; + if (RUSB2->DCPCTR_b.SUREQ) { + RUSB2->DCPCTR_b.SUREQCLR = 1; } hcd_int_enable(rhport); /* Reset should be asserted 10-20ms. */ - LINK_REG->DVSTCTR0_b.USBRST = 1; + RUSB2->DVSTCTR0_b.USBRST = 1; for (volatile int i = 0; i < 2400000; ++i) ; - LINK_REG->DVSTCTR0_b.USBRST = 0; - LINK_REG->DVSTCTR0_b.UACT = 1; + RUSB2->DVSTCTR0_b.USBRST = 0; + RUSB2->DVSTCTR0_b.UACT = 1; _hcd.need_reset = false; } @@ -569,10 +569,10 @@ void hcd_port_reset_end(uint8_t rhport) tusb_speed_t hcd_port_speed_get(uint8_t rhport) { (void)rhport; - switch (LINK_REG->DVSTCTR0_b.RHST) { + switch (RUSB2->DVSTCTR0_b.RHST) { default: return TUSB_SPEED_INVALID; - case LINK_REG_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL; - case LINK_REG_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW; + case RUSB2_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL; + case RUSB2_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW; } } @@ -588,13 +588,13 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) unsigned num = *ep; if (!num || dev_addr != _hcd.pipe[num].dev) continue; - ctr = (uint16_t volatile*)&LINK_REG->PIPE_CTR[num - 1]; + ctr = (uint16_t volatile*)&RUSB2->PIPE_CTR[num - 1]; *ctr = 0; - LINK_REG->NRDYENB &= ~TU_BIT(num); - LINK_REG->BRDYENB &= ~TU_BIT(num); - LINK_REG->PIPESEL = num; - LINK_REG->PIPECFG = 0; - LINK_REG->PIPEMAXP = 0; + RUSB2->NRDYENB &= ~TU_BIT(num); + RUSB2->BRDYENB &= ~TU_BIT(num); + RUSB2->PIPESEL = num; + RUSB2->PIPECFG = 0; + RUSB2->PIPEMAXP = 0; _hcd.pipe[num].ep = 0; _hcd.pipe[num].dev = 0; @@ -608,32 +608,32 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { (void)rhport; - // TU_LOG1("S %d %x\n", dev_addr, LINK_REG->DCPCTR); + // TU_LOG1("S %d %x\n", dev_addr, RUSB2->DCPCTR); TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ - TU_ASSERT(0 == LINK_REG->DCPCTR_b.SUREQ); + TU_ASSERT(0 == RUSB2->DCPCTR_b.SUREQ); - LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; + RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; _hcd.pipe[0].buf = NULL; _hcd.pipe[0].length = 8; _hcd.pipe[0].remaining = 0; _hcd.pipe[0].dev = dev_addr; - while (LINK_REG->DCPCTR_b.PBUSY) ; - LINK_REG->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr]; + while (RUSB2->DCPCTR_b.PBUSY) ; + RUSB2->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr]; /* Set direction in advance for DATA stage */ uint8_t const bmRequesttype = setup_packet[0]; - LINK_REG->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1; + RUSB2->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1; uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0]; - LINK_REG->USBREQ = tu_htole16(p[0]); - LINK_REG->USBVAL = p[1]; - LINK_REG->USBINDX = p[2]; - LINK_REG->USBLENG = p[3]; + RUSB2->USBREQ = tu_htole16(p[0]); + RUSB2->USBVAL = p[1]; + RUSB2->USBINDX = p[2]; + RUSB2->USBLENG = p[3]; - LINK_REG->DCPCTR_b.SUREQ = 1; + RUSB2->DCPCTR_b.SUREQ = 1; return true; } @@ -646,14 +646,14 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const const unsigned epn = tu_edpt_number(ep_addr); const unsigned mps = tu_edpt_packet_size(ep_desc); if (0 == epn) { - LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK; + RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; hcd_devtree_info_t devtree; hcd_devtree_get_info(dev_addr, &devtree); - uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &LINK_REG->DEVADD[0]; + uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &RUSB2->DEVADD[0]; devadd += dev_addr; - while (LINK_REG->DCPCTR_b.PBUSY) ; - LINK_REG->DCPMAXP = (dev_addr << 12) | mps; - *devadd = (TUSB_SPEED_FULL == devtree.speed) ? LINK_REG_DEVADD_USBSPD_FS : LINK_REG_DEVADD_USBSPD_LS; + while (RUSB2->DCPCTR_b.PBUSY) ; + RUSB2->DCPMAXP = (dev_addr << 12) | mps; + *devadd = (TUSB_SPEED_FULL == devtree.speed) ? RUSB2_DEVADD_USBSPD_FS : RUSB2_DEVADD_USBSPD_LS; _hcd.ctl_mps[dev_addr] = mps; return true; } @@ -672,25 +672,25 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const /* setup pipe */ hcd_int_disable(rhport); - LINK_REG->PIPESEL = num; - LINK_REG->PIPEMAXP = (dev_addr << 12) | mps; + RUSB2->PIPESEL = num; + RUSB2->PIPEMAXP = (dev_addr << 12) | mps; volatile uint16_t *ctr = get_pipectr(num); - *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk; + *ctr = RUSB2_PIPE_CTR_ACLRM_Msk | RUSB2_PIPE_CTR_SQCLR_Msk; *ctr = 0; unsigned cfg = ((1 ^ dir_in) << 4) | epn; if (xfer == TUSB_XFER_BULK) { - cfg |= LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk; + cfg |= RUSB2_PIPECFG_TYPE_BULK | RUSB2_PIPECFG_SHTNAK_Msk | RUSB2_PIPECFG_DBLB_Msk; } else if (xfer == TUSB_XFER_INTERRUPT) { - cfg |= LINK_REG_PIPECFG_TYPE_INT; + cfg |= RUSB2_PIPECFG_TYPE_INT; } else { - cfg |= LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk; + cfg |= RUSB2_PIPECFG_TYPE_ISO | RUSB2_PIPECFG_DBLB_Msk; } - LINK_REG->PIPECFG = cfg; - LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num); - LINK_REG->NRDYENB |= TU_BIT(num); - LINK_REG->BRDYENB |= TU_BIT(num); + RUSB2->PIPECFG = cfg; + RUSB2->BRDYSTS = 0x1FFu ^ TU_BIT(num); + RUSB2->NRDYENB |= TU_BIT(num); + RUSB2->BRDYENB |= TU_BIT(num); if (!dir_in) { - *ctr = LINK_REG_PIPE_CTR_PID_BUF; + *ctr = RUSB2_PIPE_CTR_PID_BUF; } hcd_int_enable(rhport); @@ -717,12 +717,12 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) *ctr = pid & 2; *ctr = 0; } - *ctr = LINK_REG_PIPE_CTR_SQCLR_Msk; + *ctr = RUSB2_PIPE_CTR_SQCLR_Msk; unsigned const epn = tu_edpt_number(ep_addr); if (!epn) return true; if (!tu_edpt_dir(ep_addr)) { /* OUT */ - *ctr = LINK_REG_PIPE_CTR_PID_BUF; + *ctr = RUSB2_PIPE_CTR_PID_BUF; } return true; } @@ -740,49 +740,49 @@ void hcd_int_handler(uint8_t rhport) 20, 8, 19, 18}; #endif - unsigned is1 = LINK_REG->INTSTS1; - unsigned is0 = LINK_REG->INTSTS0; + unsigned is1 = RUSB2->INTSTS1; + unsigned is0 = RUSB2->INTSTS0; /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ - LINK_REG->INTSTS1 = ~((LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk) & is1); - LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk) & is0); + RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1); + RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0); // TU_LOG1("IS %04x %04x\n", is0, is1); - is1 &= LINK_REG->INTENB1; - is0 &= LINK_REG->INTENB0; + is1 &= RUSB2->INTENB1; + is0 &= RUSB2->INTENB0; - if (is1 & LINK_REG_INTSTS1_SACK_Msk) { + if (is1 & RUSB2_INTSTS1_SACK_Msk) { /* Set DATA1 in advance for the next transfer. */ - LINK_REG->DCPCTR_b.SQSET = 1; - hcd_event_xfer_complete(LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); + RUSB2->DCPCTR_b.SQSET = 1; + hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); } - if (is1 & LINK_REG_INTSTS1_SIGN_Msk) { - hcd_event_xfer_complete(LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); + if (is1 & RUSB2_INTSTS1_SIGN_Msk) { + hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); } - if (is1 & LINK_REG_INTSTS1_ATTCH_Msk) { - LINK_REG->DVSTCTR0_b.UACT = 1; + if (is1 & RUSB2_INTSTS1_ATTCH_Msk) { + RUSB2->DVSTCTR0_b.UACT = 1; _hcd.need_reset = true; - LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_ATTCH_Msk) | LINK_REG_INTSTS1_DTCH_Msk; + RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; hcd_event_device_attach(rhport, true); } - if (is1 & LINK_REG_INTSTS1_DTCH_Msk) { - LINK_REG->DVSTCTR0_b.UACT = 0; - if (LINK_REG->DCPCTR_b.SUREQ) { - LINK_REG->DCPCTR_b.SUREQCLR = 1; + if (is1 & RUSB2_INTSTS1_DTCH_Msk) { + RUSB2->DVSTCTR0_b.UACT = 0; + if (RUSB2->DCPCTR_b.SUREQ) { + RUSB2->DCPCTR_b.SUREQCLR = 1; } - LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_DTCH_Msk) | LINK_REG_INTSTS1_ATTCH_Msk; + RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_DTCH_Msk) | RUSB2_INTSTS1_ATTCH_Msk; hcd_event_device_remove(rhport, true); } - if (is0 & LINK_REG_INTSTS0_BEMP_Msk) { - const unsigned s = LINK_REG->BEMPSTS; - LINK_REG->BEMPSTS = 0; + if (is0 & RUSB2_INTSTS0_BEMP_Msk) { + const unsigned s = RUSB2->BEMPSTS; + RUSB2->BEMPSTS = 0; if (s & 1) { process_pipe0_bemp(rhport); } } - if (is0 & LINK_REG_INTSTS0_NRDY_Msk) { - const unsigned m = LINK_REG->NRDYENB; - unsigned s = LINK_REG->NRDYSTS & m; - LINK_REG->NRDYSTS = ~s; + if (is0 & RUSB2_INTSTS0_NRDY_Msk) { + const unsigned m = RUSB2->NRDYENB; + unsigned s = RUSB2->NRDYSTS & m; + RUSB2->NRDYSTS = ~s; while (s) { #if defined(__CCRX__) const unsigned num = Mod37BitPosition[(-s & s) % 37]; @@ -793,11 +793,11 @@ void hcd_int_handler(uint8_t rhport) s &= ~TU_BIT(num); } } - if (is0 & LINK_REG_INTSTS0_BRDY_Msk) { - const unsigned m = LINK_REG->BRDYENB; - unsigned s = LINK_REG->BRDYSTS & m; + if (is0 & RUSB2_INTSTS0_BRDY_Msk) { + const unsigned m = RUSB2->BRDYENB; + unsigned s = RUSB2->BRDYSTS & m; /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ - LINK_REG->BRDYSTS = ~s; + RUSB2->BRDYSTS = ~s; while (s) { #if defined(__CCRX__) const unsigned num = Mod37BitPosition[(-s & s) % 37]; diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index a73b13951..24658e95a 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -34,24 +34,22 @@ extern "C" { /* renesas fsp api */ #include "bsp_api.h" -#define LINK_REG_BASE (0x40090000) +#define RUSB2_REG_BASE (0x40090000) -TU_ATTR_ALWAYS_INLINE -static inline void link_int_enable(uint8_t rhport) +TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) { (void) rhport; NVIC_EnableIRQ(TU_IRQn); } -TU_ATTR_ALWAYS_INLINE -static inline void link_int_disable(uint8_t rhport) +TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) { (void) rhport; NVIC_DisableIRQ(TU_IRQn); } // MCU specific PHY init -static inline void link_phy_init(void) +TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) { } diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h index e43253569..c28689df1 100644 --- a/src/portable/renesas/rusb2/rusb2_rx.h +++ b/src/portable/renesas/rusb2/rusb2_rx.h @@ -35,9 +35,9 @@ extern "C" { #include "iodefine.h" -#define LINK_REG_BASE (0x000A0000) +#define RUSB2_REG_BASE (0x000A0000) -TU_ATTR_ALWAYS_INLINE static inline void link_int_enable(uint8_t rhport) +TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) { (void) rhport; #if (CFG_TUSB_MCU == OPT_MCU_RX72N) @@ -47,7 +47,7 @@ TU_ATTR_ALWAYS_INLINE static inline void link_int_enable(uint8_t rhport) #endif } -TU_ATTR_ALWAYS_INLINE static inline void link_int_disable(uint8_t rhport) +TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) { (void) rhport; #if (CFG_TUSB_MCU == OPT_MCU_RX72N) @@ -58,7 +58,7 @@ TU_ATTR_ALWAYS_INLINE static inline void link_int_disable(uint8_t rhport) } // MCU specific PHY init -TU_ATTR_ALWAYS_INLINE static inline void link_phy_init(void) +TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) { #if (CFG_TUSB_MCU == OPT_MCU_RX72N) IR(PERIB, INTB185) = 0; diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index cb3db650a..6a5c7f8ff 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -60,7 +60,7 @@ typedef struct TU_ATTR_PACKED { volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */ } N_b; }; -} LINK_REG_PIPE_TR_t; /* Size = 4 (0x4) */ +} RUSB2_PIPE_TR_t; /* Size = 4 (0x4) */ /* LINK_REG Structure */ typedef struct TU_ATTR_PACKED { @@ -685,7 +685,7 @@ typedef struct TU_ATTR_PACKED { }; volatile const uint16_t RESERVED13; volatile const uint32_t RESERVED14[3]; - volatile LINK_REG_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */ + volatile RUSB2_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */ volatile const uint32_t RESERVED15[3]; union { @@ -950,7 +950,7 @@ typedef struct TU_ATTR_PACKED { uint32_t : 8; } DPUSR1R_FS_b; }; -} LINK_REG_t; /* Size = 1032 (0x408) */ +} RUSB2_REG_t; /* Size = 1032 (0x408) */ TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */ TU_ATTR_BIT_FIELD_ORDER_END @@ -961,706 +961,706 @@ TU_ATTR_BIT_FIELD_ORDER_END // PIPE_TR // E -#define LINK_REG_PIPE_TR_E_TRENB_Pos (9UL) /* TRENB (Bit 9) */ -#define LINK_REG_PIPE_TR_E_TRENB_Msk (0x200UL) /* TRENB (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_TR_E_TRCLR_Pos (8UL) /* TRCLR (Bit 8) */ -#define LINK_REG_PIPE_TR_E_TRCLR_Msk (0x100UL) /* TRCLR (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPE_TR_E_TRENB_Pos (9UL) /* TRENB (Bit 9) */ +#define RUSB2_PIPE_TR_E_TRENB_Msk (0x200UL) /* TRENB (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPE_TR_E_TRCLR_Pos (8UL) /* TRCLR (Bit 8) */ +#define RUSB2_PIPE_TR_E_TRCLR_Msk (0x100UL) /* TRCLR (Bitfield-Mask: 0x01) */ // N -#define LINK_REG_PIPE_TR_N_TRNCNT_Pos (0UL) /* TRNCNT (Bit 0) */ -#define LINK_REG_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /* TRNCNT (Bitfield-Mask: 0xffff) */ +#define RUSB2_PIPE_TR_N_TRNCNT_Pos (0UL) /* TRNCNT (Bit 0) */ +#define RUSB2_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /* TRNCNT (Bitfield-Mask: 0xffff) */ // LINK_REG // SYSCFG -#define LINK_REG_SYSCFG_SCKE_Pos (10UL) /* SCKE (Bit 10) */ -#define LINK_REG_SYSCFG_SCKE_Msk (0x400UL) /* SCKE (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_CNEN_Pos (8UL) /* CNEN (Bit 8) */ -#define LINK_REG_SYSCFG_CNEN_Msk (0x100UL) /* CNEN (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_DCFM_Pos (6UL) /* DCFM (Bit 6) */ -#define LINK_REG_SYSCFG_DCFM_Msk (0x40UL) /* DCFM (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_DRPD_Pos (5UL) /* DRPD (Bit 5) */ -#define LINK_REG_SYSCFG_DRPD_Msk (0x20UL) /* DRPD (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_DPRPU_Pos (4UL) /* DPRPU (Bit 4) */ -#define LINK_REG_SYSCFG_DPRPU_Msk (0x10UL) /* DPRPU (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_DMRPU_Pos (3UL) /* DMRPU (Bit 3) */ -#define LINK_REG_SYSCFG_DMRPU_Msk (0x8UL) /* DMRPU (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSCFG_USBE_Pos (0UL) /* USBE (Bit 0) */ -#define LINK_REG_SYSCFG_USBE_Msk (0x1UL) /* USBE (Bitfield-Mask: 0x01) */ +#define RUSB2_SYSCFG_SCKE_Pos (10UL) /* SCKE (Bit 10) */ +#define RUSB2_SYSCFG_SCKE_Msk (0x400UL) /* SCKE (Bitfield-Mask: 0x01) */ +#define RUSB2_SYSCFG_CNEN_Pos (8UL) /* CNEN (Bit 8) */ +#define RUSB2_SYSCFG_CNEN_Msk (0x100UL) /* CNEN (Bitfield-Mask: 0x01) */ +#define RUSB2_SYSCFG_DCFM_Pos (6UL) /* DCFM (Bit 6) */ +#define RUSB2_SYSCFG_DCFM_Msk (0x40UL) /* DCFM (Bitfield-Mask: 0x01) */ +#define RUSB2_SYSCFG_DRPD_Pos (5UL) /* DRPD (Bit 5) */ +#define RUSB2_SYSCFG_DRPD_Msk (0x20UL) /* DRPD (Bitfield-Mask: 0x01) */ +#define RUSB2_SYSCFG_DPRPU_Pos (4UL) /* DPRPU (Bit 4) */ +#define RUSB2_SYSCFG_DPRPU_Msk (0x10UL) /* DPRPU (Bitfield-Mask: 0x01) */ +#define RUSB2_SYSCFG_DMRPU_Pos (3UL) /* DMRPU (Bit 3) */ +#define RUSB2_SYSCFG_DMRPU_Msk (0x8UL) /* DMRPU (Bitfield-Mask: 0x01) */ +#define RUSB2_SYSCFG_USBE_Pos (0UL) /* USBE (Bit 0) */ +#define RUSB2_SYSCFG_USBE_Msk (0x1UL) /* USBE (Bitfield-Mask: 0x01) */ // BUSWAIT -#define LINK_REG_BUSWAIT_BWAIT_Pos (0UL) /* BWAIT (Bit 0) */ -#define LINK_REG_BUSWAIT_BWAIT_Msk (0xfUL) /* BWAIT (Bitfield-Mask: 0x0f) */ +#define RUSB2_BUSWAIT_BWAIT_Pos (0UL) /* BWAIT (Bit 0) */ +#define RUSB2_BUSWAIT_BWAIT_Msk (0xfUL) /* BWAIT (Bitfield-Mask: 0x0f) */ // SYSSTS0 -#define LINK_REG_SYSSTS0_OVCMON_Pos (14UL) /* OVCMON (Bit 14) */ -#define LINK_REG_SYSSTS0_OVCMON_Msk (0xc000UL) /* OVCMON (Bitfield-Mask: 0x03) */ -#define LINK_REG_SYSSTS0_HTACT_Pos (6UL) /* HTACT (Bit 6) */ -#define LINK_REG_SYSSTS0_HTACT_Msk (0x40UL) /* HTACT (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSSTS0_SOFEA_Pos (5UL) /* SOFEA (Bit 5) */ -#define LINK_REG_SYSSTS0_SOFEA_Msk (0x20UL) /* SOFEA (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSSTS0_IDMON_Pos (2UL) /* IDMON (Bit 2) */ -#define LINK_REG_SYSSTS0_IDMON_Msk (0x4UL) /* IDMON (Bitfield-Mask: 0x01) */ -#define LINK_REG_SYSSTS0_LNST_Pos (0UL) /* LNST (Bit 0) */ -#define LINK_REG_SYSSTS0_LNST_Msk (0x3UL) /* LNST (Bitfield-Mask: 0x03) */ +#define RUSB2_SYSSTS0_OVCMON_Pos (14UL) /* OVCMON (Bit 14) */ +#define RUSB2_SYSSTS0_OVCMON_Msk (0xc000UL) /* OVCMON (Bitfield-Mask: 0x03) */ +#define RUSB2_SYSSTS0_HTACT_Pos (6UL) /* HTACT (Bit 6) */ +#define RUSB2_SYSSTS0_HTACT_Msk (0x40UL) /* HTACT (Bitfield-Mask: 0x01) */ +#define RUSB2_SYSSTS0_SOFEA_Pos (5UL) /* SOFEA (Bit 5) */ +#define RUSB2_SYSSTS0_SOFEA_Msk (0x20UL) /* SOFEA (Bitfield-Mask: 0x01) */ +#define RUSB2_SYSSTS0_IDMON_Pos (2UL) /* IDMON (Bit 2) */ +#define RUSB2_SYSSTS0_IDMON_Msk (0x4UL) /* IDMON (Bitfield-Mask: 0x01) */ +#define RUSB2_SYSSTS0_LNST_Pos (0UL) /* LNST (Bit 0) */ +#define RUSB2_SYSSTS0_LNST_Msk (0x3UL) /* LNST (Bitfield-Mask: 0x03) */ // PLLSTA -#define LINK_REG_PLLSTA_PLLLOCK_Pos (0UL) /* PLLLOCK (Bit 0) */ -#define LINK_REG_PLLSTA_PLLLOCK_Msk (0x1UL) /* PLLLOCK (Bitfield-Mask: 0x01) */ +#define RUSB2_PLLSTA_PLLLOCK_Pos (0UL) /* PLLLOCK (Bit 0) */ +#define RUSB2_PLLSTA_PLLLOCK_Msk (0x1UL) /* PLLLOCK (Bitfield-Mask: 0x01) */ // DVSTCTR0 -#define LINK_REG_DVSTCTR0_HNPBTOA_Pos (11UL) /* HNPBTOA (Bit 11) */ -#define LINK_REG_DVSTCTR0_HNPBTOA_Msk (0x800UL) /* HNPBTOA (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_EXICEN_Pos (10UL) /* EXICEN (Bit 10) */ -#define LINK_REG_DVSTCTR0_EXICEN_Msk (0x400UL) /* EXICEN (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_VBUSEN_Pos (9UL) /* VBUSEN (Bit 9) */ -#define LINK_REG_DVSTCTR0_VBUSEN_Msk (0x200UL) /* VBUSEN (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_WKUP_Pos (8UL) /* WKUP (Bit 8) */ -#define LINK_REG_DVSTCTR0_WKUP_Msk (0x100UL) /* WKUP (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_RWUPE_Pos (7UL) /* RWUPE (Bit 7) */ -#define LINK_REG_DVSTCTR0_RWUPE_Msk (0x80UL) /* RWUPE (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_USBRST_Pos (6UL) /* USBRST (Bit 6) */ -#define LINK_REG_DVSTCTR0_USBRST_Msk (0x40UL) /* USBRST (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_RESUME_Pos (5UL) /* RESUME (Bit 5) */ -#define LINK_REG_DVSTCTR0_RESUME_Msk (0x20UL) /* RESUME (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_UACT_Pos (4UL) /* UACT (Bit 4) */ -#define LINK_REG_DVSTCTR0_UACT_Msk (0x10UL) /* UACT (Bitfield-Mask: 0x01) */ -#define LINK_REG_DVSTCTR0_RHST_Pos (0UL) /* RHST (Bit 0) */ -#define LINK_REG_DVSTCTR0_RHST_Msk (0x7UL) /* RHST (Bitfield-Mask: 0x07) */ +#define RUSB2_DVSTCTR0_HNPBTOA_Pos (11UL) /* HNPBTOA (Bit 11) */ +#define RUSB2_DVSTCTR0_HNPBTOA_Msk (0x800UL) /* HNPBTOA (Bitfield-Mask: 0x01) */ +#define RUSB2_DVSTCTR0_EXICEN_Pos (10UL) /* EXICEN (Bit 10) */ +#define RUSB2_DVSTCTR0_EXICEN_Msk (0x400UL) /* EXICEN (Bitfield-Mask: 0x01) */ +#define RUSB2_DVSTCTR0_VBUSEN_Pos (9UL) /* VBUSEN (Bit 9) */ +#define RUSB2_DVSTCTR0_VBUSEN_Msk (0x200UL) /* VBUSEN (Bitfield-Mask: 0x01) */ +#define RUSB2_DVSTCTR0_WKUP_Pos (8UL) /* WKUP (Bit 8) */ +#define RUSB2_DVSTCTR0_WKUP_Msk (0x100UL) /* WKUP (Bitfield-Mask: 0x01) */ +#define RUSB2_DVSTCTR0_RWUPE_Pos (7UL) /* RWUPE (Bit 7) */ +#define RUSB2_DVSTCTR0_RWUPE_Msk (0x80UL) /* RWUPE (Bitfield-Mask: 0x01) */ +#define RUSB2_DVSTCTR0_USBRST_Pos (6UL) /* USBRST (Bit 6) */ +#define RUSB2_DVSTCTR0_USBRST_Msk (0x40UL) /* USBRST (Bitfield-Mask: 0x01) */ +#define RUSB2_DVSTCTR0_RESUME_Pos (5UL) /* RESUME (Bit 5) */ +#define RUSB2_DVSTCTR0_RESUME_Msk (0x20UL) /* RESUME (Bitfield-Mask: 0x01) */ +#define RUSB2_DVSTCTR0_UACT_Pos (4UL) /* UACT (Bit 4) */ +#define RUSB2_DVSTCTR0_UACT_Msk (0x10UL) /* UACT (Bitfield-Mask: 0x01) */ +#define RUSB2_DVSTCTR0_RHST_Pos (0UL) /* RHST (Bit 0) */ +#define RUSB2_DVSTCTR0_RHST_Msk (0x7UL) /* RHST (Bitfield-Mask: 0x07) */ // TESTMODE -#define LINK_REG_TESTMODE_UTST_Pos (0UL) /* UTST (Bit 0) */ -#define LINK_REG_TESTMODE_UTST_Msk (0xfUL) /* UTST (Bitfield-Mask: 0x0f) */ +#define RUSB2_TESTMODE_UTST_Pos (0UL) /* UTST (Bit 0) */ +#define RUSB2_TESTMODE_UTST_Msk (0xfUL) /* UTST (Bitfield-Mask: 0x0f) */ // CFIFOSEL -#define LINK_REG_CFIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ -#define LINK_REG_CFIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ -#define LINK_REG_CFIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ -#define LINK_REG_CFIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ -#define LINK_REG_CFIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ -#define LINK_REG_CFIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOSEL_ISEL_Pos (5UL) /* ISEL (Bit 5) */ -#define LINK_REG_CFIFOSEL_ISEL_Msk (0x20UL) /* ISEL (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ -#define LINK_REG_CFIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ +#define RUSB2_CFIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ +#define RUSB2_CFIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ +#define RUSB2_CFIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ +#define RUSB2_CFIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ +#define RUSB2_CFIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ +#define RUSB2_CFIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ +#define RUSB2_CFIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ +#define RUSB2_CFIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ +#define RUSB2_CFIFOSEL_ISEL_Pos (5UL) /* ISEL (Bit 5) */ +#define RUSB2_CFIFOSEL_ISEL_Msk (0x20UL) /* ISEL (Bitfield-Mask: 0x01) */ +#define RUSB2_CFIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ +#define RUSB2_CFIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ // CFIFOCTR -#define LINK_REG_CFIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ -#define LINK_REG_CFIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ -#define LINK_REG_CFIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ -#define LINK_REG_CFIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ -#define LINK_REG_CFIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ -#define LINK_REG_CFIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ +#define RUSB2_CFIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ +#define RUSB2_CFIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ +#define RUSB2_CFIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ +#define RUSB2_CFIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ +#define RUSB2_CFIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ +#define RUSB2_CFIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ +#define RUSB2_CFIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ +#define RUSB2_CFIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ // D0FIFOSEL -#define LINK_REG_D0FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ -#define LINK_REG_D0FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ -#define LINK_REG_D0FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ -#define LINK_REG_D0FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ -#define LINK_REG_D0FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ -#define LINK_REG_D0FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ -#define LINK_REG_D0FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ -#define LINK_REG_D0FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ -#define LINK_REG_D0FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ +#define RUSB2_D0FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ +#define RUSB2_D0FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ +#define RUSB2_D0FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ +#define RUSB2_D0FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ +#define RUSB2_D0FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ +#define RUSB2_D0FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ +#define RUSB2_D0FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ +#define RUSB2_D0FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ +#define RUSB2_D0FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ +#define RUSB2_D0FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ +#define RUSB2_D0FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ +#define RUSB2_D0FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ +#define RUSB2_D0FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ +#define RUSB2_D0FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ // D0FIFOCTR -#define LINK_REG_D0FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ -#define LINK_REG_D0FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ -#define LINK_REG_D0FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ -#define LINK_REG_D0FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ -#define LINK_REG_D0FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ -#define LINK_REG_D0FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ +#define RUSB2_D0FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ +#define RUSB2_D0FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ +#define RUSB2_D0FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ +#define RUSB2_D0FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ +#define RUSB2_D0FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ +#define RUSB2_D0FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ +#define RUSB2_D0FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ +#define RUSB2_D0FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ // D1FIFOSEL -#define LINK_REG_D1FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ -#define LINK_REG_D1FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ -#define LINK_REG_D1FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ -#define LINK_REG_D1FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ -#define LINK_REG_D1FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ -#define LINK_REG_D1FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ -#define LINK_REG_D1FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ -#define LINK_REG_D1FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ -#define LINK_REG_D1FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ +#define RUSB2_D1FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ +#define RUSB2_D1FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ +#define RUSB2_D1FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ +#define RUSB2_D1FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ +#define RUSB2_D1FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ +#define RUSB2_D1FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ +#define RUSB2_D1FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ +#define RUSB2_D1FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ +#define RUSB2_D1FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ +#define RUSB2_D1FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ +#define RUSB2_D1FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ +#define RUSB2_D1FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ +#define RUSB2_D1FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ +#define RUSB2_D1FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ // D1FIFOCTR -#define LINK_REG_D1FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ -#define LINK_REG_D1FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ -#define LINK_REG_D1FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ -#define LINK_REG_D1FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ -#define LINK_REG_D1FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ -#define LINK_REG_D1FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ +#define RUSB2_D1FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ +#define RUSB2_D1FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ +#define RUSB2_D1FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ +#define RUSB2_D1FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ +#define RUSB2_D1FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ +#define RUSB2_D1FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ +#define RUSB2_D1FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ +#define RUSB2_D1FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ // INTENB0 -#define LINK_REG_INTENB0_VBSE_Pos (15UL) /* VBSE (Bit 15) */ -#define LINK_REG_INTENB0_VBSE_Msk (0x8000UL) /* VBSE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_RSME_Pos (14UL) /* RSME (Bit 14) */ -#define LINK_REG_INTENB0_RSME_Msk (0x4000UL) /* RSME (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_SOFE_Pos (13UL) /* SOFE (Bit 13) */ -#define LINK_REG_INTENB0_SOFE_Msk (0x2000UL) /* SOFE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_DVSE_Pos (12UL) /* DVSE (Bit 12) */ -#define LINK_REG_INTENB0_DVSE_Msk (0x1000UL) /* DVSE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_CTRE_Pos (11UL) /* CTRE (Bit 11) */ -#define LINK_REG_INTENB0_CTRE_Msk (0x800UL) /* CTRE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_BEMPE_Pos (10UL) /* BEMPE (Bit 10) */ -#define LINK_REG_INTENB0_BEMPE_Msk (0x400UL) /* BEMPE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_NRDYE_Pos (9UL) /* NRDYE (Bit 9) */ -#define LINK_REG_INTENB0_NRDYE_Msk (0x200UL) /* NRDYE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB0_BRDYE_Pos (8UL) /* BRDYE (Bit 8) */ -#define LINK_REG_INTENB0_BRDYE_Msk (0x100UL) /* BRDYE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB0_VBSE_Pos (15UL) /* VBSE (Bit 15) */ +#define RUSB2_INTENB0_VBSE_Msk (0x8000UL) /* VBSE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB0_RSME_Pos (14UL) /* RSME (Bit 14) */ +#define RUSB2_INTENB0_RSME_Msk (0x4000UL) /* RSME (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB0_SOFE_Pos (13UL) /* SOFE (Bit 13) */ +#define RUSB2_INTENB0_SOFE_Msk (0x2000UL) /* SOFE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB0_DVSE_Pos (12UL) /* DVSE (Bit 12) */ +#define RUSB2_INTENB0_DVSE_Msk (0x1000UL) /* DVSE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB0_CTRE_Pos (11UL) /* CTRE (Bit 11) */ +#define RUSB2_INTENB0_CTRE_Msk (0x800UL) /* CTRE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB0_BEMPE_Pos (10UL) /* BEMPE (Bit 10) */ +#define RUSB2_INTENB0_BEMPE_Msk (0x400UL) /* BEMPE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB0_NRDYE_Pos (9UL) /* NRDYE (Bit 9) */ +#define RUSB2_INTENB0_NRDYE_Msk (0x200UL) /* NRDYE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB0_BRDYE_Pos (8UL) /* BRDYE (Bit 8) */ +#define RUSB2_INTENB0_BRDYE_Msk (0x100UL) /* BRDYE (Bitfield-Mask: 0x01) */ // INTENB1 -#define LINK_REG_INTENB1_OVRCRE_Pos (15UL) /* OVRCRE (Bit 15) */ -#define LINK_REG_INTENB1_OVRCRE_Msk (0x8000UL) /* OVRCRE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_BCHGE_Pos (14UL) /* BCHGE (Bit 14) */ -#define LINK_REG_INTENB1_BCHGE_Msk (0x4000UL) /* BCHGE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_DTCHE_Pos (12UL) /* DTCHE (Bit 12) */ -#define LINK_REG_INTENB1_DTCHE_Msk (0x1000UL) /* DTCHE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_ATTCHE_Pos (11UL) /* ATTCHE (Bit 11) */ -#define LINK_REG_INTENB1_ATTCHE_Msk (0x800UL) /* ATTCHE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_EOFERRE_Pos (6UL) /* EOFERRE (Bit 6) */ -#define LINK_REG_INTENB1_EOFERRE_Msk (0x40UL) /* EOFERRE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_SIGNE_Pos (5UL) /* SIGNE (Bit 5) */ -#define LINK_REG_INTENB1_SIGNE_Msk (0x20UL) /* SIGNE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_SACKE_Pos (4UL) /* SACKE (Bit 4) */ -#define LINK_REG_INTENB1_SACKE_Msk (0x10UL) /* SACKE (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTENB1_PDDETINTE0_Pos (0UL) /* PDDETINTE0 (Bit 0) */ -#define LINK_REG_INTENB1_PDDETINTE0_Msk (0x1UL) /* PDDETINTE0 (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB1_OVRCRE_Pos (15UL) /* OVRCRE (Bit 15) */ +#define RUSB2_INTENB1_OVRCRE_Msk (0x8000UL) /* OVRCRE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB1_BCHGE_Pos (14UL) /* BCHGE (Bit 14) */ +#define RUSB2_INTENB1_BCHGE_Msk (0x4000UL) /* BCHGE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB1_DTCHE_Pos (12UL) /* DTCHE (Bit 12) */ +#define RUSB2_INTENB1_DTCHE_Msk (0x1000UL) /* DTCHE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB1_ATTCHE_Pos (11UL) /* ATTCHE (Bit 11) */ +#define RUSB2_INTENB1_ATTCHE_Msk (0x800UL) /* ATTCHE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB1_EOFERRE_Pos (6UL) /* EOFERRE (Bit 6) */ +#define RUSB2_INTENB1_EOFERRE_Msk (0x40UL) /* EOFERRE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB1_SIGNE_Pos (5UL) /* SIGNE (Bit 5) */ +#define RUSB2_INTENB1_SIGNE_Msk (0x20UL) /* SIGNE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB1_SACKE_Pos (4UL) /* SACKE (Bit 4) */ +#define RUSB2_INTENB1_SACKE_Msk (0x10UL) /* SACKE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB1_PDDETINTE0_Pos (0UL) /* PDDETINTE0 (Bit 0) */ +#define RUSB2_INTENB1_PDDETINTE0_Msk (0x1UL) /* PDDETINTE0 (Bitfield-Mask: 0x01) */ // BRDYENB -#define LINK_REG_BRDYENB_PIPEBRDYE_Pos (0UL) /* PIPEBRDYE (Bit 0) */ -#define LINK_REG_BRDYENB_PIPEBRDYE_Msk (0x1UL) /* PIPEBRDYE (Bitfield-Mask: 0x01) */ +#define RUSB2_BRDYENB_PIPEBRDYE_Pos (0UL) /* PIPEBRDYE (Bit 0) */ +#define RUSB2_BRDYENB_PIPEBRDYE_Msk (0x1UL) /* PIPEBRDYE (Bitfield-Mask: 0x01) */ // NRDYENB -#define LINK_REG_NRDYENB_PIPENRDYE_Pos (0UL) /* PIPENRDYE (Bit 0) */ -#define LINK_REG_NRDYENB_PIPENRDYE_Msk (0x1UL) /* PIPENRDYE (Bitfield-Mask: 0x01) */ +#define RUSB2_NRDYENB_PIPENRDYE_Pos (0UL) /* PIPENRDYE (Bit 0) */ +#define RUSB2_NRDYENB_PIPENRDYE_Msk (0x1UL) /* PIPENRDYE (Bitfield-Mask: 0x01) */ // BEMPENB -#define LINK_REG_BEMPENB_PIPEBEMPE_Pos (0UL) /* PIPEBEMPE (Bit 0) */ -#define LINK_REG_BEMPENB_PIPEBEMPE_Msk (0x1UL) /* PIPEBEMPE (Bitfield-Mask: 0x01) */ +#define RUSB2_BEMPENB_PIPEBEMPE_Pos (0UL) /* PIPEBEMPE (Bit 0) */ +#define RUSB2_BEMPENB_PIPEBEMPE_Msk (0x1UL) /* PIPEBEMPE (Bitfield-Mask: 0x01) */ // SOFCFG -#define LINK_REG_SOFCFG_TRNENSEL_Pos (8UL) /* TRNENSEL (Bit 8) */ -#define LINK_REG_SOFCFG_TRNENSEL_Msk (0x100UL) /* TRNENSEL (Bitfield-Mask: 0x01) */ -#define LINK_REG_SOFCFG_BRDYM_Pos (6UL) /* BRDYM (Bit 6) */ -#define LINK_REG_SOFCFG_BRDYM_Msk (0x40UL) /* BRDYM (Bitfield-Mask: 0x01) */ -#define LINK_REG_SOFCFG_INTL_Pos (5UL) /* INTL (Bit 5) */ -#define LINK_REG_SOFCFG_INTL_Msk (0x20UL) /* INTL (Bitfield-Mask: 0x01) */ -#define LINK_REG_SOFCFG_EDGESTS_Pos (4UL) /* EDGESTS (Bit 4) */ -#define LINK_REG_SOFCFG_EDGESTS_Msk (0x10UL) /* EDGESTS (Bitfield-Mask: 0x01) */ +#define RUSB2_SOFCFG_TRNENSEL_Pos (8UL) /* TRNENSEL (Bit 8) */ +#define RUSB2_SOFCFG_TRNENSEL_Msk (0x100UL) /* TRNENSEL (Bitfield-Mask: 0x01) */ +#define RUSB2_SOFCFG_BRDYM_Pos (6UL) /* BRDYM (Bit 6) */ +#define RUSB2_SOFCFG_BRDYM_Msk (0x40UL) /* BRDYM (Bitfield-Mask: 0x01) */ +#define RUSB2_SOFCFG_INTL_Pos (5UL) /* INTL (Bit 5) */ +#define RUSB2_SOFCFG_INTL_Msk (0x20UL) /* INTL (Bitfield-Mask: 0x01) */ +#define RUSB2_SOFCFG_EDGESTS_Pos (4UL) /* EDGESTS (Bit 4) */ +#define RUSB2_SOFCFG_EDGESTS_Msk (0x10UL) /* EDGESTS (Bitfield-Mask: 0x01) */ // PHYSET -#define LINK_REG_PHYSET_HSEB_Pos (15UL) /* HSEB (Bit 15) */ -#define LINK_REG_PHYSET_HSEB_Msk (0x8000UL) /* HSEB (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSET_REPSTART_Pos (11UL) /* REPSTART (Bit 11) */ -#define LINK_REG_PHYSET_REPSTART_Msk (0x800UL) /* REPSTART (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSET_REPSEL_Pos (8UL) /* REPSEL (Bit 8) */ -#define LINK_REG_PHYSET_REPSEL_Msk (0x300UL) /* REPSEL (Bitfield-Mask: 0x03) */ -#define LINK_REG_PHYSET_CLKSEL_Pos (4UL) /* CLKSEL (Bit 4) */ -#define LINK_REG_PHYSET_CLKSEL_Msk (0x30UL) /* CLKSEL (Bitfield-Mask: 0x03) */ -#define LINK_REG_PHYSET_CDPEN_Pos (3UL) /* CDPEN (Bit 3) */ -#define LINK_REG_PHYSET_CDPEN_Msk (0x8UL) /* CDPEN (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSET_PLLRESET_Pos (1UL) /* PLLRESET (Bit 1) */ -#define LINK_REG_PHYSET_PLLRESET_Msk (0x2UL) /* PLLRESET (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSET_DIRPD_Pos (0UL) /* DIRPD (Bit 0) */ -#define LINK_REG_PHYSET_DIRPD_Msk (0x1UL) /* DIRPD (Bitfield-Mask: 0x01) */ +#define RUSB2_PHYSET_HSEB_Pos (15UL) /* HSEB (Bit 15) */ +#define RUSB2_PHYSET_HSEB_Msk (0x8000UL) /* HSEB (Bitfield-Mask: 0x01) */ +#define RUSB2_PHYSET_REPSTART_Pos (11UL) /* REPSTART (Bit 11) */ +#define RUSB2_PHYSET_REPSTART_Msk (0x800UL) /* REPSTART (Bitfield-Mask: 0x01) */ +#define RUSB2_PHYSET_REPSEL_Pos (8UL) /* REPSEL (Bit 8) */ +#define RUSB2_PHYSET_REPSEL_Msk (0x300UL) /* REPSEL (Bitfield-Mask: 0x03) */ +#define RUSB2_PHYSET_CLKSEL_Pos (4UL) /* CLKSEL (Bit 4) */ +#define RUSB2_PHYSET_CLKSEL_Msk (0x30UL) /* CLKSEL (Bitfield-Mask: 0x03) */ +#define RUSB2_PHYSET_CDPEN_Pos (3UL) /* CDPEN (Bit 3) */ +#define RUSB2_PHYSET_CDPEN_Msk (0x8UL) /* CDPEN (Bitfield-Mask: 0x01) */ +#define RUSB2_PHYSET_PLLRESET_Pos (1UL) /* PLLRESET (Bit 1) */ +#define RUSB2_PHYSET_PLLRESET_Msk (0x2UL) /* PLLRESET (Bitfield-Mask: 0x01) */ +#define RUSB2_PHYSET_DIRPD_Pos (0UL) /* DIRPD (Bit 0) */ +#define RUSB2_PHYSET_DIRPD_Msk (0x1UL) /* DIRPD (Bitfield-Mask: 0x01) */ // INTSTS0 -#define LINK_REG_INTSTS0_VBINT_Pos (15UL) /* VBINT (Bit 15) */ -#define LINK_REG_INTSTS0_VBINT_Msk (0x8000UL) /* VBINT (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_RESM_Pos (14UL) /* RESM (Bit 14) */ -#define LINK_REG_INTSTS0_RESM_Msk (0x4000UL) /* RESM (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_SOFR_Pos (13UL) /* SOFR (Bit 13) */ -#define LINK_REG_INTSTS0_SOFR_Msk (0x2000UL) /* SOFR (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_DVST_Pos (12UL) /* DVST (Bit 12) */ -#define LINK_REG_INTSTS0_DVST_Msk (0x1000UL) /* DVST (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_CTRT_Pos (11UL) /* CTRT (Bit 11) */ -#define LINK_REG_INTSTS0_CTRT_Msk (0x800UL) /* CTRT (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_BEMP_Pos (10UL) /* BEMP (Bit 10) */ -#define LINK_REG_INTSTS0_BEMP_Msk (0x400UL) /* BEMP (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_NRDY_Pos (9UL) /* NRDY (Bit 9) */ -#define LINK_REG_INTSTS0_NRDY_Msk (0x200UL) /* NRDY (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_BRDY_Pos (8UL) /* BRDY (Bit 8) */ -#define LINK_REG_INTSTS0_BRDY_Msk (0x100UL) /* BRDY (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_VBSTS_Pos (7UL) /* VBSTS (Bit 7) */ -#define LINK_REG_INTSTS0_VBSTS_Msk (0x80UL) /* VBSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ -#define LINK_REG_INTSTS0_DVSQ_Msk (0x70UL) /* DVSQ (Bitfield-Mask: 0x07) */ -#define LINK_REG_INTSTS0_VALID_Pos (3UL) /* VALID (Bit 3) */ -#define LINK_REG_INTSTS0_VALID_Msk (0x8UL) /* VALID (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS0_CTSQ_Pos (0UL) /* CTSQ (Bit 0) */ -#define LINK_REG_INTSTS0_CTSQ_Msk (0x7UL) /* CTSQ (Bitfield-Mask: 0x07) */ +#define RUSB2_INTSTS0_VBINT_Pos (15UL) /* VBINT (Bit 15) */ +#define RUSB2_INTSTS0_VBINT_Msk (0x8000UL) /* VBINT (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS0_RESM_Pos (14UL) /* RESM (Bit 14) */ +#define RUSB2_INTSTS0_RESM_Msk (0x4000UL) /* RESM (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS0_SOFR_Pos (13UL) /* SOFR (Bit 13) */ +#define RUSB2_INTSTS0_SOFR_Msk (0x2000UL) /* SOFR (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS0_DVST_Pos (12UL) /* DVST (Bit 12) */ +#define RUSB2_INTSTS0_DVST_Msk (0x1000UL) /* DVST (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS0_CTRT_Pos (11UL) /* CTRT (Bit 11) */ +#define RUSB2_INTSTS0_CTRT_Msk (0x800UL) /* CTRT (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS0_BEMP_Pos (10UL) /* BEMP (Bit 10) */ +#define RUSB2_INTSTS0_BEMP_Msk (0x400UL) /* BEMP (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS0_NRDY_Pos (9UL) /* NRDY (Bit 9) */ +#define RUSB2_INTSTS0_NRDY_Msk (0x200UL) /* NRDY (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS0_BRDY_Pos (8UL) /* BRDY (Bit 8) */ +#define RUSB2_INTSTS0_BRDY_Msk (0x100UL) /* BRDY (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS0_VBSTS_Pos (7UL) /* VBSTS (Bit 7) */ +#define RUSB2_INTSTS0_VBSTS_Msk (0x80UL) /* VBSTS (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS0_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ +#define RUSB2_INTSTS0_DVSQ_Msk (0x70UL) /* DVSQ (Bitfield-Mask: 0x07) */ +#define RUSB2_INTSTS0_VALID_Pos (3UL) /* VALID (Bit 3) */ +#define RUSB2_INTSTS0_VALID_Msk (0x8UL) /* VALID (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS0_CTSQ_Pos (0UL) /* CTSQ (Bit 0) */ +#define RUSB2_INTSTS0_CTSQ_Msk (0x7UL) /* CTSQ (Bitfield-Mask: 0x07) */ // INTSTS1 -#define LINK_REG_INTSTS1_OVRCR_Pos (15UL) /* OVRCR (Bit 15) */ -#define LINK_REG_INTSTS1_OVRCR_Msk (0x8000UL) /* OVRCR (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_BCHG_Pos (14UL) /* BCHG (Bit 14) */ -#define LINK_REG_INTSTS1_BCHG_Msk (0x4000UL) /* BCHG (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_DTCH_Pos (12UL) /* DTCH (Bit 12) */ -#define LINK_REG_INTSTS1_DTCH_Msk (0x1000UL) /* DTCH (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_ATTCH_Pos (11UL) /* ATTCH (Bit 11) */ -#define LINK_REG_INTSTS1_ATTCH_Msk (0x800UL) /* ATTCH (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_L1RSMEND_Pos (9UL) /* L1RSMEND (Bit 9) */ -#define LINK_REG_INTSTS1_L1RSMEND_Msk (0x200UL) /* L1RSMEND (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_LPMEND_Pos (8UL) /* LPMEND (Bit 8) */ -#define LINK_REG_INTSTS1_LPMEND_Msk (0x100UL) /* LPMEND (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_EOFERR_Pos (6UL) /* EOFERR (Bit 6) */ -#define LINK_REG_INTSTS1_EOFERR_Msk (0x40UL) /* EOFERR (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_SIGN_Pos (5UL) /* SIGN (Bit 5) */ -#define LINK_REG_INTSTS1_SIGN_Msk (0x20UL) /* SIGN (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_SACK_Pos (4UL) /* SACK (Bit 4) */ -#define LINK_REG_INTSTS1_SACK_Msk (0x10UL) /* SACK (Bitfield-Mask: 0x01) */ -#define LINK_REG_INTSTS1_PDDETINT0_Pos (0UL) /* PDDETINT0 (Bit 0) */ -#define LINK_REG_INTSTS1_PDDETINT0_Msk (0x1UL) /* PDDETINT0 (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS1_OVRCR_Pos (15UL) /* OVRCR (Bit 15) */ +#define RUSB2_INTSTS1_OVRCR_Msk (0x8000UL) /* OVRCR (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS1_BCHG_Pos (14UL) /* BCHG (Bit 14) */ +#define RUSB2_INTSTS1_BCHG_Msk (0x4000UL) /* BCHG (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS1_DTCH_Pos (12UL) /* DTCH (Bit 12) */ +#define RUSB2_INTSTS1_DTCH_Msk (0x1000UL) /* DTCH (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS1_ATTCH_Pos (11UL) /* ATTCH (Bit 11) */ +#define RUSB2_INTSTS1_ATTCH_Msk (0x800UL) /* ATTCH (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS1_L1RSMEND_Pos (9UL) /* L1RSMEND (Bit 9) */ +#define RUSB2_INTSTS1_L1RSMEND_Msk (0x200UL) /* L1RSMEND (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS1_LPMEND_Pos (8UL) /* LPMEND (Bit 8) */ +#define RUSB2_INTSTS1_LPMEND_Msk (0x100UL) /* LPMEND (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS1_EOFERR_Pos (6UL) /* EOFERR (Bit 6) */ +#define RUSB2_INTSTS1_EOFERR_Msk (0x40UL) /* EOFERR (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS1_SIGN_Pos (5UL) /* SIGN (Bit 5) */ +#define RUSB2_INTSTS1_SIGN_Msk (0x20UL) /* SIGN (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS1_SACK_Pos (4UL) /* SACK (Bit 4) */ +#define RUSB2_INTSTS1_SACK_Msk (0x10UL) /* SACK (Bitfield-Mask: 0x01) */ +#define RUSB2_INTSTS1_PDDETINT0_Pos (0UL) /* PDDETINT0 (Bit 0) */ +#define RUSB2_INTSTS1_PDDETINT0_Msk (0x1UL) /* PDDETINT0 (Bitfield-Mask: 0x01) */ // BRDYSTS -#define LINK_REG_BRDYSTS_PIPEBRDY_Pos (0UL) /* PIPEBRDY (Bit 0) */ -#define LINK_REG_BRDYSTS_PIPEBRDY_Msk (0x1UL) /* PIPEBRDY (Bitfield-Mask: 0x01) */ +#define RUSB2_BRDYSTS_PIPEBRDY_Pos (0UL) /* PIPEBRDY (Bit 0) */ +#define RUSB2_BRDYSTS_PIPEBRDY_Msk (0x1UL) /* PIPEBRDY (Bitfield-Mask: 0x01) */ // NRDYSTS -#define LINK_REG_NRDYSTS_PIPENRDY_Pos (0UL) /* PIPENRDY (Bit 0) */ -#define LINK_REG_NRDYSTS_PIPENRDY_Msk (0x1UL) /* PIPENRDY (Bitfield-Mask: 0x01) */ +#define RUSB2_NRDYSTS_PIPENRDY_Pos (0UL) /* PIPENRDY (Bit 0) */ +#define RUSB2_NRDYSTS_PIPENRDY_Msk (0x1UL) /* PIPENRDY (Bitfield-Mask: 0x01) */ // BEMPSTS -#define LINK_REG_BEMPSTS_PIPEBEMP_Pos (0UL) /* PIPEBEMP (Bit 0) */ -#define LINK_REG_BEMPSTS_PIPEBEMP_Msk (0x1UL) /* PIPEBEMP (Bitfield-Mask: 0x01) */ +#define RUSB2_BEMPSTS_PIPEBEMP_Pos (0UL) /* PIPEBEMP (Bit 0) */ +#define RUSB2_BEMPSTS_PIPEBEMP_Msk (0x1UL) /* PIPEBEMP (Bitfield-Mask: 0x01) */ // FRMNUM -#define LINK_REG_FRMNUM_OVRN_Pos (15UL) /* OVRN (Bit 15) */ -#define LINK_REG_FRMNUM_OVRN_Msk (0x8000UL) /* OVRN (Bitfield-Mask: 0x01) */ -#define LINK_REG_FRMNUM_CRCE_Pos (14UL) /* CRCE (Bit 14) */ -#define LINK_REG_FRMNUM_CRCE_Msk (0x4000UL) /* CRCE (Bitfield-Mask: 0x01) */ -#define LINK_REG_FRMNUM_FRNM_Pos (0UL) /* FRNM (Bit 0) */ -#define LINK_REG_FRMNUM_FRNM_Msk (0x7ffUL) /* FRNM (Bitfield-Mask: 0x7ff) */ +#define RUSB2_FRMNUM_OVRN_Pos (15UL) /* OVRN (Bit 15) */ +#define RUSB2_FRMNUM_OVRN_Msk (0x8000UL) /* OVRN (Bitfield-Mask: 0x01) */ +#define RUSB2_FRMNUM_CRCE_Pos (14UL) /* CRCE (Bit 14) */ +#define RUSB2_FRMNUM_CRCE_Msk (0x4000UL) /* CRCE (Bitfield-Mask: 0x01) */ +#define RUSB2_FRMNUM_FRNM_Pos (0UL) /* FRNM (Bit 0) */ +#define RUSB2_FRMNUM_FRNM_Msk (0x7ffUL) /* FRNM (Bitfield-Mask: 0x7ff) */ // UFRMNUM -#define LINK_REG_UFRMNUM_DVCHG_Pos (15UL) /* DVCHG (Bit 15) */ -#define LINK_REG_UFRMNUM_DVCHG_Msk (0x8000UL) /* DVCHG (Bitfield-Mask: 0x01) */ -#define LINK_REG_UFRMNUM_UFRNM_Pos (0UL) /* UFRNM (Bit 0) */ -#define LINK_REG_UFRMNUM_UFRNM_Msk (0x7UL) /* UFRNM (Bitfield-Mask: 0x07) */ +#define RUSB2_UFRMNUM_DVCHG_Pos (15UL) /* DVCHG (Bit 15) */ +#define RUSB2_UFRMNUM_DVCHG_Msk (0x8000UL) /* DVCHG (Bitfield-Mask: 0x01) */ +#define RUSB2_UFRMNUM_UFRNM_Pos (0UL) /* UFRNM (Bit 0) */ +#define RUSB2_UFRMNUM_UFRNM_Msk (0x7UL) /* UFRNM (Bitfield-Mask: 0x07) */ // USBADDR -#define LINK_REG_USBADDR_STSRECOV0_Pos (8UL) /* STSRECOV0 (Bit 8) */ -#define LINK_REG_USBADDR_STSRECOV0_Msk (0x700UL) /* STSRECOV0 (Bitfield-Mask: 0x07) */ -#define LINK_REG_USBADDR_USBADDR_Pos (0UL) /* USBADDR (Bit 0) */ -#define LINK_REG_USBADDR_USBADDR_Msk (0x7fUL) /* USBADDR (Bitfield-Mask: 0x7f) */ +#define RUSB2_USBADDR_STSRECOV0_Pos (8UL) /* STSRECOV0 (Bit 8) */ +#define RUSB2_USBADDR_STSRECOV0_Msk (0x700UL) /* STSRECOV0 (Bitfield-Mask: 0x07) */ +#define RUSB2_USBADDR_USBADDR_Pos (0UL) /* USBADDR (Bit 0) */ +#define RUSB2_USBADDR_USBADDR_Msk (0x7fUL) /* USBADDR (Bitfield-Mask: 0x7f) */ // USBREQ -#define LINK_REG_USBREQ_BREQUEST_Pos (8UL) /* BREQUEST (Bit 8) */ -#define LINK_REG_USBREQ_BREQUEST_Msk (0xff00UL) /* BREQUEST (Bitfield-Mask: 0xff) */ -#define LINK_REG_USBREQ_BMREQUESTTYPE_Pos (0UL) /* BMREQUESTTYPE (Bit 0) */ -#define LINK_REG_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +#define RUSB2_USBREQ_BREQUEST_Pos (8UL) /* BREQUEST (Bit 8) */ +#define RUSB2_USBREQ_BREQUEST_Msk (0xff00UL) /* BREQUEST (Bitfield-Mask: 0xff) */ +#define RUSB2_USBREQ_BMREQUESTTYPE_Pos (0UL) /* BMREQUESTTYPE (Bit 0) */ +#define RUSB2_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */ // USBVAL -#define LINK_REG_USBVAL_WVALUE_Pos (0UL) /* WVALUE (Bit 0) */ -#define LINK_REG_USBVAL_WVALUE_Msk (0xffffUL) /* WVALUE (Bitfield-Mask: 0xffff) */ +#define RUSB2_USBVAL_WVALUE_Pos (0UL) /* WVALUE (Bit 0) */ +#define RUSB2_USBVAL_WVALUE_Msk (0xffffUL) /* WVALUE (Bitfield-Mask: 0xffff) */ // USBINDX -#define LINK_REG_USBINDX_WINDEX_Pos (0UL) /* WINDEX (Bit 0) */ -#define LINK_REG_USBINDX_WINDEX_Msk (0xffffUL) /* WINDEX (Bitfield-Mask: 0xffff) */ +#define RUSB2_USBINDX_WINDEX_Pos (0UL) /* WINDEX (Bit 0) */ +#define RUSB2_USBINDX_WINDEX_Msk (0xffffUL) /* WINDEX (Bitfield-Mask: 0xffff) */ // USBLENG -#define LINK_REG_USBLENG_WLENGTH_Pos (0UL) /* WLENGTH (Bit 0) */ -#define LINK_REG_USBLENG_WLENGTH_Msk (0xffffUL) /* WLENGTH (Bitfield-Mask: 0xffff) */ +#define RUSB2_USBLENG_WLENGTH_Pos (0UL) /* WLENGTH (Bit 0) */ +#define RUSB2_USBLENG_WLENGTH_Msk (0xffffUL) /* WLENGTH (Bitfield-Mask: 0xffff) */ // DCPCFG -#define LINK_REG_DCPCFG_CNTMD_Pos (8UL) /* CNTMD (Bit 8) */ -#define LINK_REG_DCPCFG_CNTMD_Msk (0x100UL) /* CNTMD (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ -#define LINK_REG_DCPCFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCFG_DIR_Pos (4UL) /* DIR (Bit 4) */ -#define LINK_REG_DCPCFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ +#define RUSB2_DCPCFG_CNTMD_Pos (8UL) /* CNTMD (Bit 8) */ +#define RUSB2_DCPCFG_CNTMD_Msk (0x100UL) /* CNTMD (Bitfield-Mask: 0x01) */ +#define RUSB2_DCPCFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ +#define RUSB2_DCPCFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ +#define RUSB2_DCPCFG_DIR_Pos (4UL) /* DIR (Bit 4) */ +#define RUSB2_DCPCFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ // DCPMAXP -#define LINK_REG_DCPMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ -#define LINK_REG_DCPMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ -#define LINK_REG_DCPMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ -#define LINK_REG_DCPMAXP_MXPS_Msk (0x7fUL) /* MXPS (Bitfield-Mask: 0x7f) */ +#define RUSB2_DCPMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ +#define RUSB2_DCPMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ +#define RUSB2_DCPMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ +#define RUSB2_DCPMAXP_MXPS_Msk (0x7fUL) /* MXPS (Bitfield-Mask: 0x7f) */ // DCPCTR -#define LINK_REG_DCPCTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ -#define LINK_REG_DCPCTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_SUREQ_Pos (14UL) /* SUREQ (Bit 14) */ -#define LINK_REG_DCPCTR_SUREQ_Msk (0x4000UL) /* SUREQ (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_SUREQCLR_Pos (11UL) /* SUREQCLR (Bit 11) */ -#define LINK_REG_DCPCTR_SUREQCLR_Msk (0x800UL) /* SUREQCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ -#define LINK_REG_DCPCTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ -#define LINK_REG_DCPCTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ -#define LINK_REG_DCPCTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ -#define LINK_REG_DCPCTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_CCPL_Pos (2UL) /* CCPL (Bit 2) */ -#define LINK_REG_DCPCTR_CCPL_Msk (0x4UL) /* CCPL (Bitfield-Mask: 0x01) */ -#define LINK_REG_DCPCTR_PID_Pos (0UL) /* PID (Bit 0) */ -#define LINK_REG_DCPCTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ +#define RUSB2_DCPCTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ +#define RUSB2_DCPCTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ +#define RUSB2_DCPCTR_SUREQ_Pos (14UL) /* SUREQ (Bit 14) */ +#define RUSB2_DCPCTR_SUREQ_Msk (0x4000UL) /* SUREQ (Bitfield-Mask: 0x01) */ +#define RUSB2_DCPCTR_SUREQCLR_Pos (11UL) /* SUREQCLR (Bit 11) */ +#define RUSB2_DCPCTR_SUREQCLR_Msk (0x800UL) /* SUREQCLR (Bitfield-Mask: 0x01) */ +#define RUSB2_DCPCTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ +#define RUSB2_DCPCTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ +#define RUSB2_DCPCTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ +#define RUSB2_DCPCTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ +#define RUSB2_DCPCTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ +#define RUSB2_DCPCTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ +#define RUSB2_DCPCTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ +#define RUSB2_DCPCTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ +#define RUSB2_DCPCTR_CCPL_Pos (2UL) /* CCPL (Bit 2) */ +#define RUSB2_DCPCTR_CCPL_Msk (0x4UL) /* CCPL (Bitfield-Mask: 0x01) */ +#define RUSB2_DCPCTR_PID_Pos (0UL) /* PID (Bit 0) */ +#define RUSB2_DCPCTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ // PIPESEL -#define LINK_REG_PIPESEL_PIPESEL_Pos (0UL) /* PIPESEL (Bit 0) */ -#define LINK_REG_PIPESEL_PIPESEL_Msk (0xfUL) /* PIPESEL (Bitfield-Mask: 0x0f) */ +#define RUSB2_PIPESEL_PIPESEL_Pos (0UL) /* PIPESEL (Bit 0) */ +#define RUSB2_PIPESEL_PIPESEL_Msk (0xfUL) /* PIPESEL (Bitfield-Mask: 0x0f) */ // PIPECFG -#define LINK_REG_PIPECFG_TYPE_Pos (14UL) /* TYPE (Bit 14) */ -#define LINK_REG_PIPECFG_TYPE_Msk (0xc000UL) /* TYPE (Bitfield-Mask: 0x03) */ -#define LINK_REG_PIPECFG_BFRE_Pos (10UL) /* BFRE (Bit 10) */ -#define LINK_REG_PIPECFG_BFRE_Msk (0x400UL) /* BFRE (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPECFG_DBLB_Pos (9UL) /* DBLB (Bit 9) */ -#define LINK_REG_PIPECFG_DBLB_Msk (0x200UL) /* DBLB (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPECFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ -#define LINK_REG_PIPECFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPECFG_DIR_Pos (4UL) /* DIR (Bit 4) */ -#define LINK_REG_PIPECFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPECFG_EPNUM_Pos (0UL) /* EPNUM (Bit 0) */ -#define LINK_REG_PIPECFG_EPNUM_Msk (0xfUL) /* EPNUM (Bitfield-Mask: 0x0f) */ +#define RUSB2_PIPECFG_TYPE_Pos (14UL) /* TYPE (Bit 14) */ +#define RUSB2_PIPECFG_TYPE_Msk (0xc000UL) /* TYPE (Bitfield-Mask: 0x03) */ +#define RUSB2_PIPECFG_BFRE_Pos (10UL) /* BFRE (Bit 10) */ +#define RUSB2_PIPECFG_BFRE_Msk (0x400UL) /* BFRE (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPECFG_DBLB_Pos (9UL) /* DBLB (Bit 9) */ +#define RUSB2_PIPECFG_DBLB_Msk (0x200UL) /* DBLB (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPECFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ +#define RUSB2_PIPECFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPECFG_DIR_Pos (4UL) /* DIR (Bit 4) */ +#define RUSB2_PIPECFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPECFG_EPNUM_Pos (0UL) /* EPNUM (Bit 0) */ +#define RUSB2_PIPECFG_EPNUM_Msk (0xfUL) /* EPNUM (Bitfield-Mask: 0x0f) */ // PIPEMAXP -#define LINK_REG_PIPEMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ -#define LINK_REG_PIPEMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ -#define LINK_REG_PIPEMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ -#define LINK_REG_PIPEMAXP_MXPS_Msk (0x1ffUL) /* MXPS (Bitfield-Mask: 0x1ff) */ +#define RUSB2_PIPEMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ +#define RUSB2_PIPEMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ +#define RUSB2_PIPEMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ +#define RUSB2_PIPEMAXP_MXPS_Msk (0x1ffUL) /* MXPS (Bitfield-Mask: 0x1ff) */ // PIPEPERI -#define LINK_REG_PIPEPERI_IFIS_Pos (12UL) /* IFIS (Bit 12) */ -#define LINK_REG_PIPEPERI_IFIS_Msk (0x1000UL) /* IFIS (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPEPERI_IITV_Pos (0UL) /* IITV (Bit 0) */ -#define LINK_REG_PIPEPERI_IITV_Msk (0x7UL) /* IITV (Bitfield-Mask: 0x07) */ +#define RUSB2_PIPEPERI_IFIS_Pos (12UL) /* IFIS (Bit 12) */ +#define RUSB2_PIPEPERI_IFIS_Msk (0x1000UL) /* IFIS (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPEPERI_IITV_Pos (0UL) /* IITV (Bit 0) */ +#define RUSB2_PIPEPERI_IITV_Msk (0x7UL) /* IITV (Bitfield-Mask: 0x07) */ // PIPE_CTR -#define LINK_REG_PIPE_CTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ -#define LINK_REG_PIPE_CTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_INBUFM_Pos (14UL) /* INBUFM (Bit 14) */ -#define LINK_REG_PIPE_CTR_INBUFM_Msk (0x4000UL) /* INBUFM (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_CSCLR_Pos (13UL) /* CSCLR (Bit 13) */ -#define LINK_REG_PIPE_CTR_CSCLR_Msk (0x2000UL) /* CSCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_CSSTS_Pos (12UL) /* CSSTS (Bit 12) */ -#define LINK_REG_PIPE_CTR_CSSTS_Msk (0x1000UL) /* CSSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_ATREPM_Pos (10UL) /* ATREPM (Bit 10) */ -#define LINK_REG_PIPE_CTR_ATREPM_Msk (0x400UL) /* ATREPM (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_ACLRM_Pos (9UL) /* ACLRM (Bit 9) */ -#define LINK_REG_PIPE_CTR_ACLRM_Msk (0x200UL) /* ACLRM (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ -#define LINK_REG_PIPE_CTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ -#define LINK_REG_PIPE_CTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ -#define LINK_REG_PIPE_CTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ -#define LINK_REG_PIPE_CTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ -#define LINK_REG_PIPE_CTR_PID_Pos (0UL) /* PID (Bit 0) */ -#define LINK_REG_PIPE_CTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ +#define RUSB2_PIPE_CTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ +#define RUSB2_PIPE_CTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPE_CTR_INBUFM_Pos (14UL) /* INBUFM (Bit 14) */ +#define RUSB2_PIPE_CTR_INBUFM_Msk (0x4000UL) /* INBUFM (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPE_CTR_CSCLR_Pos (13UL) /* CSCLR (Bit 13) */ +#define RUSB2_PIPE_CTR_CSCLR_Msk (0x2000UL) /* CSCLR (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPE_CTR_CSSTS_Pos (12UL) /* CSSTS (Bit 12) */ +#define RUSB2_PIPE_CTR_CSSTS_Msk (0x1000UL) /* CSSTS (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPE_CTR_ATREPM_Pos (10UL) /* ATREPM (Bit 10) */ +#define RUSB2_PIPE_CTR_ATREPM_Msk (0x400UL) /* ATREPM (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPE_CTR_ACLRM_Pos (9UL) /* ACLRM (Bit 9) */ +#define RUSB2_PIPE_CTR_ACLRM_Msk (0x200UL) /* ACLRM (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPE_CTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ +#define RUSB2_PIPE_CTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPE_CTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ +#define RUSB2_PIPE_CTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPE_CTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ +#define RUSB2_PIPE_CTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPE_CTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ +#define RUSB2_PIPE_CTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPE_CTR_PID_Pos (0UL) /* PID (Bit 0) */ +#define RUSB2_PIPE_CTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ // DEVADD -#define LINK_REG_DEVADD_UPPHUB_Pos (11UL) /* UPPHUB (Bit 11) */ -#define LINK_REG_DEVADD_UPPHUB_Msk (0x7800UL) /* UPPHUB (Bitfield-Mask: 0x0f) */ -#define LINK_REG_DEVADD_HUBPORT_Pos (8UL) /* HUBPORT (Bit 8) */ -#define LINK_REG_DEVADD_HUBPORT_Msk (0x700UL) /* HUBPORT (Bitfield-Mask: 0x07) */ -#define LINK_REG_DEVADD_USBSPD_Pos (6UL) /* USBSPD (Bit 6) */ -#define LINK_REG_DEVADD_USBSPD_Msk (0xc0UL) /* USBSPD (Bitfield-Mask: 0x03) */ +#define RUSB2_DEVADD_UPPHUB_Pos (11UL) /* UPPHUB (Bit 11) */ +#define RUSB2_DEVADD_UPPHUB_Msk (0x7800UL) /* UPPHUB (Bitfield-Mask: 0x0f) */ +#define RUSB2_DEVADD_HUBPORT_Pos (8UL) /* HUBPORT (Bit 8) */ +#define RUSB2_DEVADD_HUBPORT_Msk (0x700UL) /* HUBPORT (Bitfield-Mask: 0x07) */ +#define RUSB2_DEVADD_USBSPD_Pos (6UL) /* USBSPD (Bit 6) */ +#define RUSB2_DEVADD_USBSPD_Msk (0xc0UL) /* USBSPD (Bitfield-Mask: 0x03) */ // USBBCCTRL0 -#define LINK_REG_USBBCCTRL0_PDDETSTS0_Pos (9UL) /* PDDETSTS0 (Bit 9) */ -#define LINK_REG_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /* PDDETSTS0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /* CHGDETSTS0 (Bit 8) */ -#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /* CHGDETSTS0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_BATCHGE0_Pos (7UL) /* BATCHGE0 (Bit 7) */ -#define LINK_REG_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /* BATCHGE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_VDMSRCE0_Pos (5UL) /* VDMSRCE0 (Bit 5) */ -#define LINK_REG_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /* VDMSRCE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_IDPSINKE0_Pos (4UL) /* IDPSINKE0 (Bit 4) */ -#define LINK_REG_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /* IDPSINKE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_VDPSRCE0_Pos (3UL) /* VDPSRCE0 (Bit 3) */ -#define LINK_REG_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /* VDPSRCE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_IDMSINKE0_Pos (2UL) /* IDMSINKE0 (Bit 2) */ -#define LINK_REG_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /* IDMSINKE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_IDPSRCE0_Pos (1UL) /* IDPSRCE0 (Bit 1) */ -#define LINK_REG_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /* IDPSRCE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBBCCTRL0_RPDME0_Pos (0UL) /* RPDME0 (Bit 0) */ -#define LINK_REG_USBBCCTRL0_RPDME0_Msk (0x1UL) /* RPDME0 (Bitfield-Mask: 0x01) */ +#define RUSB2_USBBCCTRL0_PDDETSTS0_Pos (9UL) /* PDDETSTS0 (Bit 9) */ +#define RUSB2_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /* PDDETSTS0 (Bitfield-Mask: 0x01) */ +#define RUSB2_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /* CHGDETSTS0 (Bit 8) */ +#define RUSB2_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /* CHGDETSTS0 (Bitfield-Mask: 0x01) */ +#define RUSB2_USBBCCTRL0_BATCHGE0_Pos (7UL) /* BATCHGE0 (Bit 7) */ +#define RUSB2_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /* BATCHGE0 (Bitfield-Mask: 0x01) */ +#define RUSB2_USBBCCTRL0_VDMSRCE0_Pos (5UL) /* VDMSRCE0 (Bit 5) */ +#define RUSB2_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /* VDMSRCE0 (Bitfield-Mask: 0x01) */ +#define RUSB2_USBBCCTRL0_IDPSINKE0_Pos (4UL) /* IDPSINKE0 (Bit 4) */ +#define RUSB2_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /* IDPSINKE0 (Bitfield-Mask: 0x01) */ +#define RUSB2_USBBCCTRL0_VDPSRCE0_Pos (3UL) /* VDPSRCE0 (Bit 3) */ +#define RUSB2_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /* VDPSRCE0 (Bitfield-Mask: 0x01) */ +#define RUSB2_USBBCCTRL0_IDMSINKE0_Pos (2UL) /* IDMSINKE0 (Bit 2) */ +#define RUSB2_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /* IDMSINKE0 (Bitfield-Mask: 0x01) */ +#define RUSB2_USBBCCTRL0_IDPSRCE0_Pos (1UL) /* IDPSRCE0 (Bit 1) */ +#define RUSB2_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /* IDPSRCE0 (Bitfield-Mask: 0x01) */ +#define RUSB2_USBBCCTRL0_RPDME0_Pos (0UL) /* RPDME0 (Bit 0) */ +#define RUSB2_USBBCCTRL0_RPDME0_Msk (0x1UL) /* RPDME0 (Bitfield-Mask: 0x01) */ // UCKSEL -#define LINK_REG_UCKSEL_UCKSELC_Pos (0UL) /* UCKSELC (Bit 0) */ -#define LINK_REG_UCKSEL_UCKSELC_Msk (0x1UL) /* UCKSELC (Bitfield-Mask: 0x01) */ +#define RUSB2_UCKSEL_UCKSELC_Pos (0UL) /* UCKSELC (Bit 0) */ +#define RUSB2_UCKSEL_UCKSELC_Msk (0x1UL) /* UCKSELC (Bitfield-Mask: 0x01) */ // USBMC -#define LINK_REG_USBMC_VDCEN_Pos (7UL) /* VDCEN (Bit 7) */ -#define LINK_REG_USBMC_VDCEN_Msk (0x80UL) /* VDCEN (Bitfield-Mask: 0x01) */ -#define LINK_REG_USBMC_VDDUSBE_Pos (0UL) /* VDDUSBE (Bit 0) */ -#define LINK_REG_USBMC_VDDUSBE_Msk (0x1UL) /* VDDUSBE (Bitfield-Mask: 0x01) */ +#define RUSB2_USBMC_VDCEN_Pos (7UL) /* VDCEN (Bit 7) */ +#define RUSB2_USBMC_VDCEN_Msk (0x80UL) /* VDCEN (Bitfield-Mask: 0x01) */ +#define RUSB2_USBMC_VDDUSBE_Pos (0UL) /* VDDUSBE (Bit 0) */ +#define RUSB2_USBMC_VDDUSBE_Msk (0x1UL) /* VDDUSBE (Bitfield-Mask: 0x01) */ // PHYSLEW -#define LINK_REG_PHYSLEW_SLEWF01_Pos (3UL) /* SLEWF01 (Bit 3) */ -#define LINK_REG_PHYSLEW_SLEWF01_Msk (0x8UL) /* SLEWF01 (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSLEW_SLEWF00_Pos (2UL) /* SLEWF00 (Bit 2) */ -#define LINK_REG_PHYSLEW_SLEWF00_Msk (0x4UL) /* SLEWF00 (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSLEW_SLEWR01_Pos (1UL) /* SLEWR01 (Bit 1) */ -#define LINK_REG_PHYSLEW_SLEWR01_Msk (0x2UL) /* SLEWR01 (Bitfield-Mask: 0x01) */ -#define LINK_REG_PHYSLEW_SLEWR00_Pos (0UL) /* SLEWR00 (Bit 0) */ -#define LINK_REG_PHYSLEW_SLEWR00_Msk (0x1UL) /* SLEWR00 (Bitfield-Mask: 0x01) */ +#define RUSB2_PHYSLEW_SLEWF01_Pos (3UL) /* SLEWF01 (Bit 3) */ +#define RUSB2_PHYSLEW_SLEWF01_Msk (0x8UL) /* SLEWF01 (Bitfield-Mask: 0x01) */ +#define RUSB2_PHYSLEW_SLEWF00_Pos (2UL) /* SLEWF00 (Bit 2) */ +#define RUSB2_PHYSLEW_SLEWF00_Msk (0x4UL) /* SLEWF00 (Bitfield-Mask: 0x01) */ +#define RUSB2_PHYSLEW_SLEWR01_Pos (1UL) /* SLEWR01 (Bit 1) */ +#define RUSB2_PHYSLEW_SLEWR01_Msk (0x2UL) /* SLEWR01 (Bitfield-Mask: 0x01) */ +#define RUSB2_PHYSLEW_SLEWR00_Pos (0UL) /* SLEWR00 (Bit 0) */ +#define RUSB2_PHYSLEW_SLEWR00_Msk (0x1UL) /* SLEWR00 (Bitfield-Mask: 0x01) */ // LPCTRL -#define LINK_REG_LPCTRL_HWUPM_Pos (7UL) /* HWUPM (Bit 7) */ -#define LINK_REG_LPCTRL_HWUPM_Msk (0x80UL) /* HWUPM (Bitfield-Mask: 0x01) */ +#define RUSB2_LPCTRL_HWUPM_Pos (7UL) /* HWUPM (Bit 7) */ +#define RUSB2_LPCTRL_HWUPM_Msk (0x80UL) /* HWUPM (Bitfield-Mask: 0x01) */ // LPSTS -#define LINK_REG_LPSTS_SUSPENDM_Pos (14UL) /* SUSPENDM (Bit 14) */ -#define LINK_REG_LPSTS_SUSPENDM_Msk (0x4000UL) /* SUSPENDM (Bitfield-Mask: 0x01) */ +#define RUSB2_LPSTS_SUSPENDM_Pos (14UL) /* SUSPENDM (Bit 14) */ +#define RUSB2_LPSTS_SUSPENDM_Msk (0x4000UL) /* SUSPENDM (Bitfield-Mask: 0x01) */ // BCCTRL -#define LINK_REG_BCCTRL_PDDETSTS_Pos (9UL) /* PDDETSTS (Bit 9) */ -#define LINK_REG_BCCTRL_PDDETSTS_Msk (0x200UL) /* PDDETSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_CHGDETSTS_Pos (8UL) /* CHGDETSTS (Bit 8) */ -#define LINK_REG_BCCTRL_CHGDETSTS_Msk (0x100UL) /* CHGDETSTS (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_DCPMODE_Pos (5UL) /* DCPMODE (Bit 5) */ -#define LINK_REG_BCCTRL_DCPMODE_Msk (0x20UL) /* DCPMODE (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_VDMSRCE_Pos (4UL) /* VDMSRCE (Bit 4) */ -#define LINK_REG_BCCTRL_VDMSRCE_Msk (0x10UL) /* VDMSRCE (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_IDPSINKE_Pos (3UL) /* IDPSINKE (Bit 3) */ -#define LINK_REG_BCCTRL_IDPSINKE_Msk (0x8UL) /* IDPSINKE (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_VDPSRCE_Pos (2UL) /* VDPSRCE (Bit 2) */ -#define LINK_REG_BCCTRL_VDPSRCE_Msk (0x4UL) /* VDPSRCE (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_IDMSINKE_Pos (1UL) /* IDMSINKE (Bit 1) */ -#define LINK_REG_BCCTRL_IDMSINKE_Msk (0x2UL) /* IDMSINKE (Bitfield-Mask: 0x01) */ -#define LINK_REG_BCCTRL_IDPSRCE_Pos (0UL) /* IDPSRCE (Bit 0) */ -#define LINK_REG_BCCTRL_IDPSRCE_Msk (0x1UL) /* IDPSRCE (Bitfield-Mask: 0x01) */ +#define RUSB2_BCCTRL_PDDETSTS_Pos (9UL) /* PDDETSTS (Bit 9) */ +#define RUSB2_BCCTRL_PDDETSTS_Msk (0x200UL) /* PDDETSTS (Bitfield-Mask: 0x01) */ +#define RUSB2_BCCTRL_CHGDETSTS_Pos (8UL) /* CHGDETSTS (Bit 8) */ +#define RUSB2_BCCTRL_CHGDETSTS_Msk (0x100UL) /* CHGDETSTS (Bitfield-Mask: 0x01) */ +#define RUSB2_BCCTRL_DCPMODE_Pos (5UL) /* DCPMODE (Bit 5) */ +#define RUSB2_BCCTRL_DCPMODE_Msk (0x20UL) /* DCPMODE (Bitfield-Mask: 0x01) */ +#define RUSB2_BCCTRL_VDMSRCE_Pos (4UL) /* VDMSRCE (Bit 4) */ +#define RUSB2_BCCTRL_VDMSRCE_Msk (0x10UL) /* VDMSRCE (Bitfield-Mask: 0x01) */ +#define RUSB2_BCCTRL_IDPSINKE_Pos (3UL) /* IDPSINKE (Bit 3) */ +#define RUSB2_BCCTRL_IDPSINKE_Msk (0x8UL) /* IDPSINKE (Bitfield-Mask: 0x01) */ +#define RUSB2_BCCTRL_VDPSRCE_Pos (2UL) /* VDPSRCE (Bit 2) */ +#define RUSB2_BCCTRL_VDPSRCE_Msk (0x4UL) /* VDPSRCE (Bitfield-Mask: 0x01) */ +#define RUSB2_BCCTRL_IDMSINKE_Pos (1UL) /* IDMSINKE (Bit 1) */ +#define RUSB2_BCCTRL_IDMSINKE_Msk (0x2UL) /* IDMSINKE (Bitfield-Mask: 0x01) */ +#define RUSB2_BCCTRL_IDPSRCE_Pos (0UL) /* IDPSRCE (Bit 0) */ +#define RUSB2_BCCTRL_IDPSRCE_Msk (0x1UL) /* IDPSRCE (Bitfield-Mask: 0x01) */ // PL1CTRL1 -#define LINK_REG_PL1CTRL1_L1EXTMD_Pos (14UL) /* L1EXTMD (Bit 14) */ -#define LINK_REG_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /* L1EXTMD (Bitfield-Mask: 0x01) */ -#define LINK_REG_PL1CTRL1_HIRDTHR_Pos (8UL) /* HIRDTHR (Bit 8) */ -#define LINK_REG_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /* HIRDTHR (Bitfield-Mask: 0x0f) */ -#define LINK_REG_PL1CTRL1_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ -#define LINK_REG_PL1CTRL1_DVSQ_Msk (0xf0UL) /* DVSQ (Bitfield-Mask: 0x0f) */ -#define LINK_REG_PL1CTRL1_L1NEGOMD_Pos (3UL) /* L1NEGOMD (Bit 3) */ -#define LINK_REG_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /* L1NEGOMD (Bitfield-Mask: 0x01) */ -#define LINK_REG_PL1CTRL1_L1RESPMD_Pos (1UL) /* L1RESPMD (Bit 1) */ -#define LINK_REG_PL1CTRL1_L1RESPMD_Msk (0x6UL) /* L1RESPMD (Bitfield-Mask: 0x03) */ -#define LINK_REG_PL1CTRL1_L1RESPEN_Pos (0UL) /* L1RESPEN (Bit 0) */ -#define LINK_REG_PL1CTRL1_L1RESPEN_Msk (0x1UL) /* L1RESPEN (Bitfield-Mask: 0x01) */ +#define RUSB2_PL1CTRL1_L1EXTMD_Pos (14UL) /* L1EXTMD (Bit 14) */ +#define RUSB2_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /* L1EXTMD (Bitfield-Mask: 0x01) */ +#define RUSB2_PL1CTRL1_HIRDTHR_Pos (8UL) /* HIRDTHR (Bit 8) */ +#define RUSB2_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /* HIRDTHR (Bitfield-Mask: 0x0f) */ +#define RUSB2_PL1CTRL1_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ +#define RUSB2_PL1CTRL1_DVSQ_Msk (0xf0UL) /* DVSQ (Bitfield-Mask: 0x0f) */ +#define RUSB2_PL1CTRL1_L1NEGOMD_Pos (3UL) /* L1NEGOMD (Bit 3) */ +#define RUSB2_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /* L1NEGOMD (Bitfield-Mask: 0x01) */ +#define RUSB2_PL1CTRL1_L1RESPMD_Pos (1UL) /* L1RESPMD (Bit 1) */ +#define RUSB2_PL1CTRL1_L1RESPMD_Msk (0x6UL) /* L1RESPMD (Bitfield-Mask: 0x03) */ +#define RUSB2_PL1CTRL1_L1RESPEN_Pos (0UL) /* L1RESPEN (Bit 0) */ +#define RUSB2_PL1CTRL1_L1RESPEN_Msk (0x1UL) /* L1RESPEN (Bitfield-Mask: 0x01) */ // PL1CTRL2 -#define LINK_REG_PL1CTRL2_RWEMON_Pos (12UL) /* RWEMON (Bit 12) */ -#define LINK_REG_PL1CTRL2_RWEMON_Msk (0x1000UL) /* RWEMON (Bitfield-Mask: 0x01) */ -#define LINK_REG_PL1CTRL2_HIRDMON_Pos (8UL) /* HIRDMON (Bit 8) */ -#define LINK_REG_PL1CTRL2_HIRDMON_Msk (0xf00UL) /* HIRDMON (Bitfield-Mask: 0x0f) */ +#define RUSB2_PL1CTRL2_RWEMON_Pos (12UL) /* RWEMON (Bit 12) */ +#define RUSB2_PL1CTRL2_RWEMON_Msk (0x1000UL) /* RWEMON (Bitfield-Mask: 0x01) */ +#define RUSB2_PL1CTRL2_HIRDMON_Pos (8UL) /* HIRDMON (Bit 8) */ +#define RUSB2_PL1CTRL2_HIRDMON_Msk (0xf00UL) /* HIRDMON (Bitfield-Mask: 0x0f) */ // HL1CTRL1 -#define LINK_REG_HL1CTRL1_L1STATUS_Pos (1UL) /* L1STATUS (Bit 1) */ -#define LINK_REG_HL1CTRL1_L1STATUS_Msk (0x6UL) /* L1STATUS (Bitfield-Mask: 0x03) */ -#define LINK_REG_HL1CTRL1_L1REQ_Pos (0UL) /* L1REQ (Bit 0) */ -#define LINK_REG_HL1CTRL1_L1REQ_Msk (0x1UL) /* L1REQ (Bitfield-Mask: 0x01) */ +#define RUSB2_HL1CTRL1_L1STATUS_Pos (1UL) /* L1STATUS (Bit 1) */ +#define RUSB2_HL1CTRL1_L1STATUS_Msk (0x6UL) /* L1STATUS (Bitfield-Mask: 0x03) */ +#define RUSB2_HL1CTRL1_L1REQ_Pos (0UL) /* L1REQ (Bit 0) */ +#define RUSB2_HL1CTRL1_L1REQ_Msk (0x1UL) /* L1REQ (Bitfield-Mask: 0x01) */ // HL1CTRL2 -#define LINK_REG_HL1CTRL2_BESL_Pos (15UL) /* BESL (Bit 15) */ -#define LINK_REG_HL1CTRL2_BESL_Msk (0x8000UL) /* BESL (Bitfield-Mask: 0x01) */ -#define LINK_REG_HL1CTRL2_L1RWE_Pos (12UL) /* L1RWE (Bit 12) */ -#define LINK_REG_HL1CTRL2_L1RWE_Msk (0x1000UL) /* L1RWE (Bitfield-Mask: 0x01) */ -#define LINK_REG_HL1CTRL2_HIRD_Pos (8UL) /* HIRD (Bit 8) */ -#define LINK_REG_HL1CTRL2_HIRD_Msk (0xf00UL) /* HIRD (Bitfield-Mask: 0x0f) */ -#define LINK_REG_HL1CTRL2_L1ADDR_Pos (0UL) /* L1ADDR (Bit 0) */ -#define LINK_REG_HL1CTRL2_L1ADDR_Msk (0xfUL) /* L1ADDR (Bitfield-Mask: 0x0f) */ +#define RUSB2_HL1CTRL2_BESL_Pos (15UL) /* BESL (Bit 15) */ +#define RUSB2_HL1CTRL2_BESL_Msk (0x8000UL) /* BESL (Bitfield-Mask: 0x01) */ +#define RUSB2_HL1CTRL2_L1RWE_Pos (12UL) /* L1RWE (Bit 12) */ +#define RUSB2_HL1CTRL2_L1RWE_Msk (0x1000UL) /* L1RWE (Bitfield-Mask: 0x01) */ +#define RUSB2_HL1CTRL2_HIRD_Pos (8UL) /* HIRD (Bit 8) */ +#define RUSB2_HL1CTRL2_HIRD_Msk (0xf00UL) /* HIRD (Bitfield-Mask: 0x0f) */ +#define RUSB2_HL1CTRL2_L1ADDR_Pos (0UL) /* L1ADDR (Bit 0) */ +#define RUSB2_HL1CTRL2_L1ADDR_Msk (0xfUL) /* L1ADDR (Bitfield-Mask: 0x0f) */ // DPUSR0R -#define LINK_REG_DPUSR0R_DVBSTSHM_Pos (23UL) /* DVBSTSHM (Bit 23) */ -#define LINK_REG_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_DOVCBHM_Pos (21UL) /* DOVCBHM (Bit 21) */ -#define LINK_REG_DPUSR0R_DOVCBHM_Msk (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_DOVCAHM_Pos (20UL) /* DOVCAHM (Bit 20) */ -#define LINK_REG_DPUSR0R_DOVCAHM_Msk (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR0R_DVBSTSHM_Pos (23UL) /* DVBSTSHM (Bit 23) */ +#define RUSB2_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR0R_DOVCBHM_Pos (21UL) /* DOVCBHM (Bit 21) */ +#define RUSB2_DPUSR0R_DOVCBHM_Msk (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR0R_DOVCAHM_Pos (20UL) /* DOVCAHM (Bit 20) */ +#define RUSB2_DPUSR0R_DOVCAHM_Msk (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */ // DPUSR1R -#define LINK_REG_DPUSR1R_DVBSTSH_Pos (23UL) /* DVBSTSH (Bit 23) */ -#define LINK_REG_DPUSR1R_DVBSTSH_Msk (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_DOVCBH_Pos (21UL) /* DOVCBH (Bit 21) */ -#define LINK_REG_DPUSR1R_DOVCBH_Msk (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_DOVCAH_Pos (20UL) /* DOVCAH (Bit 20) */ -#define LINK_REG_DPUSR1R_DOVCAH_Msk (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_DVBSTSHE_Pos (7UL) /* DVBSTSHE (Bit 7) */ -#define LINK_REG_DPUSR1R_DVBSTSHE_Msk (0x80UL) /* DVBSTSHE (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_DOVCBHE_Pos (5UL) /* DOVCBHE (Bit 5) */ -#define LINK_REG_DPUSR1R_DOVCBHE_Msk (0x20UL) /* DOVCBHE (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_DOVCAHE_Pos (4UL) /* DOVCAHE (Bit 4) */ -#define LINK_REG_DPUSR1R_DOVCAHE_Msk (0x10UL) /* DOVCAHE (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_DVBSTSH_Pos (23UL) /* DVBSTSH (Bit 23) */ +#define RUSB2_DPUSR1R_DVBSTSH_Msk (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_DOVCBH_Pos (21UL) /* DOVCBH (Bit 21) */ +#define RUSB2_DPUSR1R_DOVCBH_Msk (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_DOVCAH_Pos (20UL) /* DOVCAH (Bit 20) */ +#define RUSB2_DPUSR1R_DOVCAH_Msk (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_DVBSTSHE_Pos (7UL) /* DVBSTSHE (Bit 7) */ +#define RUSB2_DPUSR1R_DVBSTSHE_Msk (0x80UL) /* DVBSTSHE (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_DOVCBHE_Pos (5UL) /* DOVCBHE (Bit 5) */ +#define RUSB2_DPUSR1R_DOVCBHE_Msk (0x20UL) /* DOVCBHE (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_DOVCAHE_Pos (4UL) /* DOVCAHE (Bit 4) */ +#define RUSB2_DPUSR1R_DOVCAHE_Msk (0x10UL) /* DOVCAHE (Bitfield-Mask: 0x01) */ // DPUSR2R -#define LINK_REG_DPUSR2R_DMINTE_Pos (9UL) /* DMINTE (Bit 9) */ -#define LINK_REG_DPUSR2R_DMINTE_Msk (0x200UL) /* DMINTE (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR2R_DPINTE_Pos (8UL) /* DPINTE (Bit 8) */ -#define LINK_REG_DPUSR2R_DPINTE_Msk (0x100UL) /* DPINTE (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR2R_DMVAL_Pos (5UL) /* DMVAL (Bit 5) */ -#define LINK_REG_DPUSR2R_DMVAL_Msk (0x20UL) /* DMVAL (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR2R_DPVAL_Pos (4UL) /* DPVAL (Bit 4) */ -#define LINK_REG_DPUSR2R_DPVAL_Msk (0x10UL) /* DPVAL (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR2R_DMINT_Pos (1UL) /* DMINT (Bit 1) */ -#define LINK_REG_DPUSR2R_DMINT_Msk (0x2UL) /* DMINT (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR2R_DPINT_Pos (0UL) /* DPINT (Bit 0) */ -#define LINK_REG_DPUSR2R_DPINT_Msk (0x1UL) /* DPINT (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR2R_DMINTE_Pos (9UL) /* DMINTE (Bit 9) */ +#define RUSB2_DPUSR2R_DMINTE_Msk (0x200UL) /* DMINTE (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR2R_DPINTE_Pos (8UL) /* DPINTE (Bit 8) */ +#define RUSB2_DPUSR2R_DPINTE_Msk (0x100UL) /* DPINTE (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR2R_DMVAL_Pos (5UL) /* DMVAL (Bit 5) */ +#define RUSB2_DPUSR2R_DMVAL_Msk (0x20UL) /* DMVAL (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR2R_DPVAL_Pos (4UL) /* DPVAL (Bit 4) */ +#define RUSB2_DPUSR2R_DPVAL_Msk (0x10UL) /* DPVAL (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR2R_DMINT_Pos (1UL) /* DMINT (Bit 1) */ +#define RUSB2_DPUSR2R_DMINT_Msk (0x2UL) /* DMINT (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR2R_DPINT_Pos (0UL) /* DPINT (Bit 0) */ +#define RUSB2_DPUSR2R_DPINT_Msk (0x1UL) /* DPINT (Bitfield-Mask: 0x01) */ // DPUSRCR -#define LINK_REG_DPUSRCR_FIXPHYPD_Pos (1UL) /* FIXPHYPD (Bit 1) */ -#define LINK_REG_DPUSRCR_FIXPHYPD_Msk (0x2UL) /* FIXPHYPD (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSRCR_FIXPHY_Pos (0UL) /* FIXPHY (Bit 0) */ -#define LINK_REG_DPUSRCR_FIXPHY_Msk (0x1UL) /* FIXPHY (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSRCR_FIXPHYPD_Pos (1UL) /* FIXPHYPD (Bit 1) */ +#define RUSB2_DPUSRCR_FIXPHYPD_Msk (0x2UL) /* FIXPHYPD (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSRCR_FIXPHY_Pos (0UL) /* FIXPHY (Bit 0) */ +#define RUSB2_DPUSRCR_FIXPHY_Msk (0x1UL) /* FIXPHY (Bitfield-Mask: 0x01) */ // DPUSR0R_FS -#define LINK_REG_DPUSR0R_FS_DVBSTS0_Pos (23UL) /* DVBSTS0 (Bit 23) */ -#define LINK_REG_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_DOVCB0_Pos (21UL) /* DOVCB0 (Bit 21) */ -#define LINK_REG_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_DOVCA0_Pos (20UL) /* DOVCA0 (Bit 20) */ -#define LINK_REG_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_DM0_Pos (17UL) /* DM0 (Bit 17) */ -#define LINK_REG_DPUSR0R_FS_DM0_Msk (0x20000UL) /* DM0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_DP0_Pos (16UL) /* DP0 (Bit 16) */ -#define LINK_REG_DPUSR0R_FS_DP0_Msk (0x10000UL) /* DP0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_FIXPHY0_Pos (4UL) /* FIXPHY0 (Bit 4) */ -#define LINK_REG_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /* FIXPHY0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_DRPD0_Pos (3UL) /* DRPD0 (Bit 3) */ -#define LINK_REG_DPUSR0R_FS_DRPD0_Msk (0x8UL) /* DRPD0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_RPUE0_Pos (1UL) /* RPUE0 (Bit 1) */ -#define LINK_REG_DPUSR0R_FS_RPUE0_Msk (0x2UL) /* RPUE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR0R_FS_SRPC0_Pos (0UL) /* SRPC0 (Bit 0) */ -#define LINK_REG_DPUSR0R_FS_SRPC0_Msk (0x1UL) /* SRPC0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR0R_FS_DVBSTS0_Pos (23UL) /* DVBSTS0 (Bit 23) */ +#define RUSB2_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR0R_FS_DOVCB0_Pos (21UL) /* DOVCB0 (Bit 21) */ +#define RUSB2_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR0R_FS_DOVCA0_Pos (20UL) /* DOVCA0 (Bit 20) */ +#define RUSB2_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR0R_FS_DM0_Pos (17UL) /* DM0 (Bit 17) */ +#define RUSB2_DPUSR0R_FS_DM0_Msk (0x20000UL) /* DM0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR0R_FS_DP0_Pos (16UL) /* DP0 (Bit 16) */ +#define RUSB2_DPUSR0R_FS_DP0_Msk (0x10000UL) /* DP0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR0R_FS_FIXPHY0_Pos (4UL) /* FIXPHY0 (Bit 4) */ +#define RUSB2_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /* FIXPHY0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR0R_FS_DRPD0_Pos (3UL) /* DRPD0 (Bit 3) */ +#define RUSB2_DPUSR0R_FS_DRPD0_Msk (0x8UL) /* DRPD0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR0R_FS_RPUE0_Pos (1UL) /* RPUE0 (Bit 1) */ +#define RUSB2_DPUSR0R_FS_RPUE0_Msk (0x2UL) /* RPUE0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR0R_FS_SRPC0_Pos (0UL) /* SRPC0 (Bit 0) */ +#define RUSB2_DPUSR0R_FS_SRPC0_Msk (0x1UL) /* SRPC0 (Bitfield-Mask: 0x01) */ // DPUSR1R_FS -#define LINK_REG_DPUSR1R_FS_DVBINT0_Pos (23UL) /* DVBINT0 (Bit 23) */ -#define LINK_REG_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /* DOVRCRB0 (Bit 21) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /* DOVRCRA0 (Bit 20) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DMINT0_Pos (17UL) /* DMINT0 (Bit 17) */ -#define LINK_REG_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /* DMINT0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DPINT0_Pos (16UL) /* DPINT0 (Bit 16) */ -#define LINK_REG_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /* DPINT0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DVBSE0_Pos (7UL) /* DVBSE0 (Bit 7) */ -#define LINK_REG_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /* DVBSE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /* DOVRCRBE0 (Bit 5) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /* DOVRCRBE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /* DOVRCRAE0 (Bit 4) */ -#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /* DOVRCRAE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DMINTE0_Pos (1UL) /* DMINTE0 (Bit 1) */ -#define LINK_REG_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /* DMINTE0 (Bitfield-Mask: 0x01) */ -#define LINK_REG_DPUSR1R_FS_DPINTE0_Pos (0UL) /* DPINTE0 (Bit 0) */ -#define LINK_REG_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /* DPINTE0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_FS_DVBINT0_Pos (23UL) /* DVBINT0 (Bit 23) */ +#define RUSB2_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /* DOVRCRB0 (Bit 21) */ +#define RUSB2_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /* DOVRCRA0 (Bit 20) */ +#define RUSB2_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_FS_DMINT0_Pos (17UL) /* DMINT0 (Bit 17) */ +#define RUSB2_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /* DMINT0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_FS_DPINT0_Pos (16UL) /* DPINT0 (Bit 16) */ +#define RUSB2_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /* DPINT0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_FS_DVBSE0_Pos (7UL) /* DVBSE0 (Bit 7) */ +#define RUSB2_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /* DVBSE0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /* DOVRCRBE0 (Bit 5) */ +#define RUSB2_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /* DOVRCRBE0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /* DOVRCRAE0 (Bit 4) */ +#define RUSB2_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /* DOVRCRAE0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_FS_DMINTE0_Pos (1UL) /* DMINTE0 (Bit 1) */ +#define RUSB2_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /* DMINTE0 (Bitfield-Mask: 0x01) */ +#define RUSB2_DPUSR1R_FS_DPINTE0_Pos (0UL) /* DPINTE0 (Bit 0) */ +#define RUSB2_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /* DPINTE0 (Bitfield-Mask: 0x01) */ /*--------------------------------------------------------------------*/ /* Register Bit Utils */ /*--------------------------------------------------------------------*/ -#define LINK_REG_PIPE_CTR_PID_NAK (0U << LINK_REG_PIPE_CTR_PID_Pos) /* NAK response */ -#define LINK_REG_PIPE_CTR_PID_BUF (1U << LINK_REG_PIPE_CTR_PID_Pos) /* BUF response (depends buffer state) */ -#define LINK_REG_PIPE_CTR_PID_STALL (2U << LINK_REG_PIPE_CTR_PID_Pos) /* STALL response */ +#define RUSB2_PIPE_CTR_PID_NAK (0U << RUSB2_PIPE_CTR_PID_Pos) /* NAK response */ +#define RUSB2_PIPE_CTR_PID_BUF (1U << RUSB2_PIPE_CTR_PID_Pos) /* BUF response (depends buffer state) */ +#define RUSB2_PIPE_CTR_PID_STALL (2U << RUSB2_PIPE_CTR_PID_Pos) /* STALL response */ -#define LINK_REG_DVSTCTR0_RHST_LS (1U << LINK_REG_DVSTCTR0_RHST_Pos) /* Low-speed connection */ -#define LINK_REG_DVSTCTR0_RHST_FS (2U << LINK_REG_DVSTCTR0_RHST_Pos) /* Full-speed connection */ +#define RUSB2_DVSTCTR0_RHST_LS (1U << RUSB2_DVSTCTR0_RHST_Pos) /* Low-speed connection */ +#define RUSB2_DVSTCTR0_RHST_FS (2U << RUSB2_DVSTCTR0_RHST_Pos) /* Full-speed connection */ -#define LINK_REG_DEVADD_USBSPD_LS (1U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Low-speed */ -#define LINK_REG_DEVADD_USBSPD_FS (2U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Full-speed */ +#define RUSB2_DEVADD_USBSPD_LS (1U << RUSB2_DEVADD_USBSPD_Pos) /* Target Device Low-speed */ +#define RUSB2_DEVADD_USBSPD_FS (2U << RUSB2_DEVADD_USBSPD_Pos) /* Target Device Full-speed */ -#define LINK_REG_CFIFOSEL_ISEL_WRITE (1U << LINK_REG_CFIFOSEL_ISEL_Pos) /* FIFO write AKA TX*/ +#define RUSB2_CFIFOSEL_ISEL_WRITE (1U << RUSB2_CFIFOSEL_ISEL_Pos) /* FIFO write AKA TX*/ -#define LINK_REG_FIFOSEL_BIGEND (1U << LINK_REG_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */ -#define LINK_REG_FIFOSEL_MBW_8BIT (0U << LINK_REG_CFIFOSEL_MBW_Pos) /* 8-bit width */ -#define LINK_REG_FIFOSEL_MBW_16BIT (1U << LINK_REG_CFIFOSEL_MBW_Pos) /* 16-bit width */ +#define RUSB2_FIFOSEL_BIGEND (1U << RUSB2_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */ +#define RUSB2_FIFOSEL_MBW_8BIT (0U << RUSB2_CFIFOSEL_MBW_Pos) /* 8-bit width */ +#define RUSB2_FIFOSEL_MBW_16BIT (1U << RUSB2_CFIFOSEL_MBW_Pos) /* 16-bit width */ -#define LINK_REG_INTSTS0_CTSQ_CTRL_RDATA (1U << LINK_REG_INTSTS0_CTSQ_Pos) +#define RUSB2_INTSTS0_CTSQ_CTRL_RDATA (1U << RUSB2_INTSTS0_CTSQ_Pos) -#define LINK_REG_INTSTS0_DVSQ_STATE_DEF (1U << LINK_REG_INTSTS0_DVSQ_Pos) /* Default state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_ADDR (2U << LINK_REG_INTSTS0_DVSQ_Pos) /* Address state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP0 (4U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP1 (5U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP2 (6U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ -#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP3 (7U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */ +#define RUSB2_INTSTS0_DVSQ_STATE_DEF (1U << RUSB2_INTSTS0_DVSQ_Pos) /* Default state */ +#define RUSB2_INTSTS0_DVSQ_STATE_ADDR (2U << RUSB2_INTSTS0_DVSQ_Pos) /* Address state */ +#define RUSB2_INTSTS0_DVSQ_STATE_SUSP0 (4U << RUSB2_INTSTS0_DVSQ_Pos) /* Suspend state */ +#define RUSB2_INTSTS0_DVSQ_STATE_SUSP1 (5U << RUSB2_INTSTS0_DVSQ_Pos) /* Suspend state */ +#define RUSB2_INTSTS0_DVSQ_STATE_SUSP2 (6U << RUSB2_INTSTS0_DVSQ_Pos) /* Suspend state */ +#define RUSB2_INTSTS0_DVSQ_STATE_SUSP3 (7U << RUSB2_INTSTS0_DVSQ_Pos) /* Suspend state */ -#define LINK_REG_PIPECFG_TYPE_BULK (1U << LINK_REG_PIPECFG_TYPE_Pos) -#define LINK_REG_PIPECFG_TYPE_INT (2U << LINK_REG_PIPECFG_TYPE_Pos) -#define LINK_REG_PIPECFG_TYPE_ISO (3U << LINK_REG_PIPECFG_TYPE_Pos) +#define RUSB2_PIPECFG_TYPE_BULK (1U << RUSB2_PIPECFG_TYPE_Pos) +#define RUSB2_PIPECFG_TYPE_INT (2U << RUSB2_PIPECFG_TYPE_Pos) +#define RUSB2_PIPECFG_TYPE_ISO (3U << RUSB2_PIPECFG_TYPE_Pos) //--------------------------------------------------------------------+ // Static Assert //--------------------------------------------------------------------+ -TU_VERIFY_STATIC(sizeof(LINK_REG_PIPE_TR_t) == 4, "incorrect size"); - -TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSCFG ) == 0x00000000, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BUSWAIT ) == 0x00000002, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSSTS0 ) == 0x00000004, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PLLSTA ) == 0x00000006, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DVSTCTR0 ) == 0x00000008, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, TESTMODE ) == 0x0000000C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFO ) == 0x00000014, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFO ) == 0x00000018, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFO ) == 0x0000001C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOSEL ) == 0x00000020, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOCTR ) == 0x00000022, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOSEL ) == 0x00000028, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOCTR ) == 0x0000002A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOSEL ) == 0x0000002C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOCTR ) == 0x0000002E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB0 ) == 0x00000030, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB1 ) == 0x00000032, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYENB ) == 0x00000036, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYENB ) == 0x00000038, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPENB ) == 0x0000003A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, SOFCFG ) == 0x0000003C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSET ) == 0x0000003E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS0 ) == 0x00000040, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS1 ) == 0x00000042, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYSTS ) == 0x00000046, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYSTS ) == 0x00000048, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPSTS ) == 0x0000004A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, FRMNUM ) == 0x0000004C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, UFRMNUM ) == 0x0000004E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBADDR ) == 0x00000050, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBREQ ) == 0x00000054, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBVAL ) == 0x00000056, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBINDX ) == 0x00000058, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBLENG ) == 0x0000005A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCFG ) == 0x0000005C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPMAXP ) == 0x0000005E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCTR ) == 0x00000060, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPESEL ) == 0x00000064, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPECFG ) == 0x00000068, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEMAXP ) == 0x0000006C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEPERI ) == 0x0000006E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_CTR ) == 0x00000070, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_TR ) == 0x00000090, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBBCCTRL0 ) == 0x000000B0, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, UCKSEL ) == 0x000000C4, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBMC ) == 0x000000CC, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DEVADD ) == 0x000000D0, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSLEW ) == 0x000000F0, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPCTRL ) == 0x00000100, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPSTS ) == 0x00000102, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, BCCTRL ) == 0x00000140, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL1 ) == 0x00000144, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL2 ) == 0x00000146, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL1 ) == 0x00000148, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL2 ) == 0x0000014A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R ) == 0x00000160, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R ) == 0x00000164, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR2R ) == 0x00000168, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSRCR ) == 0x0000016A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R_FS ) == 0x00000400, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect offset"); +TU_VERIFY_STATIC(sizeof(RUSB2_PIPE_TR_t) == 4, "incorrect size"); + +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSCFG ) == 0x00000000, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BUSWAIT ) == 0x00000002, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSSTS0 ) == 0x00000004, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PLLSTA ) == 0x00000006, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DVSTCTR0 ) == 0x00000008, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, TESTMODE ) == 0x0000000C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFO ) == 0x00000014, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFO ) == 0x00000018, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFO ) == 0x0000001C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFOSEL ) == 0x00000020, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFOCTR ) == 0x00000022, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFOSEL ) == 0x00000028, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFOCTR ) == 0x0000002A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFOSEL ) == 0x0000002C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFOCTR ) == 0x0000002E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTENB0 ) == 0x00000030, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTENB1 ) == 0x00000032, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BRDYENB ) == 0x00000036, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, NRDYENB ) == 0x00000038, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BEMPENB ) == 0x0000003A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SOFCFG ) == 0x0000003C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PHYSET ) == 0x0000003E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTSTS0 ) == 0x00000040, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTSTS1 ) == 0x00000042, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BRDYSTS ) == 0x00000046, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, NRDYSTS ) == 0x00000048, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BEMPSTS ) == 0x0000004A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, FRMNUM ) == 0x0000004C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, UFRMNUM ) == 0x0000004E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBADDR ) == 0x00000050, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBREQ ) == 0x00000054, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBVAL ) == 0x00000056, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBINDX ) == 0x00000058, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBLENG ) == 0x0000005A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPCFG ) == 0x0000005C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPMAXP ) == 0x0000005E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPCTR ) == 0x00000060, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPESEL ) == 0x00000064, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPECFG ) == 0x00000068, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPEMAXP ) == 0x0000006C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPEPERI ) == 0x0000006E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPE_CTR ) == 0x00000070, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPE_TR ) == 0x00000090, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBBCCTRL0 ) == 0x000000B0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, UCKSEL ) == 0x000000C4, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBMC ) == 0x000000CC, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DEVADD ) == 0x000000D0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PHYSLEW ) == 0x000000F0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, LPCTRL ) == 0x00000100, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, LPSTS ) == 0x00000102, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BCCTRL ) == 0x00000140, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PL1CTRL1 ) == 0x00000144, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PL1CTRL2 ) == 0x00000146, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, HL1CTRL1 ) == 0x00000148, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, HL1CTRL2 ) == 0x0000014A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR0R ) == 0x00000160, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R ) == 0x00000164, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR2R ) == 0x00000168, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSRCR ) == 0x0000016A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR0R_FS ) == 0x00000400, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect offset"); #ifdef __cplusplus } -- cgit v1.3.1 From e7d212f33760f13b0102a307569aac0ed8e14bd2 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 16 Mar 2023 23:21:15 +0700 Subject: more fix --- hw/bsp/stm32u5/family.mk | 2 +- src/portable/renesas/rusb2/rusb2_ra.h | 6 +++--- src/portable/renesas/rusb2/rusb2_rx.h | 6 +++--- src/portable/renesas/rusb2/rusb2_type.h | 6 +++--- 4 files changed, 10 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk index 23d7f4dda..e1c496dee 100644 --- a/hw/bsp/stm32u5/family.mk +++ b/hw/bsp/stm32u5/family.mk @@ -39,7 +39,7 @@ INC += \ $(TOP)/$(BOARD_PATH) # For freeRTOS port source -FREERTOS_PORTABLE_SRC = ARM_CM33_NTZ/non_secure +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure # flash target using on-board stlink flash: flash-stlink diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 24658e95a..5785850cc 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -24,8 +24,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef _LINK_RA_H_ -#define _LINK_RA_H_ +#ifndef _RUSB2_RA_H_ +#define _RUSB2_RA_H_ #ifdef __cplusplus extern "C" { @@ -57,4 +57,4 @@ TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) } #endif -#endif /* _LINK_RA_H_ */ +#endif /* _RUSB2_RA_H_ */ diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h index c28689df1..397c0d56c 100644 --- a/src/portable/renesas/rusb2/rusb2_rx.h +++ b/src/portable/renesas/rusb2/rusb2_rx.h @@ -26,8 +26,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef _LINK_RX_H_ -#define _LINK_RX_H_ +#ifndef _RUSB2_RX_H_ +#define _RUSB2_RX_H_ #ifdef __cplusplus extern "C" { @@ -71,4 +71,4 @@ TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) } #endif -#endif /* _LINK_RX_H_ */ +#endif /* _RUSB2_RX_H_ */ diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index 6a5c7f8ff..7a2898366 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -24,8 +24,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef _TUSB_LINK_TYPE_H_ -#define _TUSB_LINK_TYPE_H_ +#ifndef _TUSB_RUSB2_TYPE_H_ +#define _TUSB_RUSB2_TYPE_H_ #include @@ -1666,4 +1666,4 @@ TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect of } #endif -#endif /* _TUSB_LINK_TYPE_H_ */ +#endif /* _TUSB_RUSB2_TYPE_H_ */ -- cgit v1.3.1 From f349ae77029c3a82bd9509c1ad57e3e6cd815596 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 17 Mar 2023 13:58:01 +0700 Subject: fix enumerate one device at a time --- src/host/usbh.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 12b0ed203..45a2a0c66 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -54,8 +54,6 @@ // USBH-HCD common data structure //--------------------------------------------------------------------+ -// device0 struct must be strictly a subset of normal device struct -// TODO refactor later typedef struct { // port @@ -63,15 +61,13 @@ typedef struct uint8_t hub_addr; uint8_t hub_port; uint8_t speed; + volatile uint8_t enumerating; - struct TU_ATTR_PACKED - { - volatile uint8_t connected : 1; - volatile uint8_t addressed : 1; - volatile uint8_t configured : 1; - volatile uint8_t suspended : 1; - }; - +// struct TU_ATTR_PACKED { +// uint8_t speed : 4; // packed speed to save footprint +// volatile uint8_t enumerating : 1; +// uint8_t TU_RESERVED : 3; +// }; } usbh_dev0_t; typedef struct { @@ -402,10 +398,18 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) switch (event.event_id) { case HCD_EVENT_DEVICE_ATTACH: - // TODO due to the shared _usbh_ctrl_buf, we must complete enumerating + // due to the shared _usbh_ctrl_buf, we must complete enumerating // one device before enumerating another one. - TU_LOG_USBH("[%u:] USBH DEVICE ATTACH\r\n", event.rhport); - enum_new_device(&event); + if ( _dev0.enumerating ) + { + TU_LOG1("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport); + osal_queue_send(_usbh_q, &event, in_isr); + }else + { + TU_LOG1("[%u:] USBH DEVICE ATTACH\r\n", event.rhport); + _dev0.enumerating = 1; + enum_new_device(&event); + } break; case HCD_EVENT_DEVICE_REMOVE: @@ -1623,6 +1627,9 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) static void enum_full_complete(void) { + // mark enumeration as complete + _dev0.enumerating = 0; + #if CFG_TUH_HUB // get next hub status if (_dev0.hub_addr) hub_edpt_status_xfer(_dev0.hub_addr); -- cgit v1.3.1 From 317177c83d3c28d66bfe60be971ff37a44bd84df Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 17 Mar 2023 14:06:25 +0700 Subject: update host example, add pio-pico-usb for rp2040 --- examples/host/bare_api/CMakeLists.txt | 5 +++++ examples/host/bare_api/src/tusb_config.h | 4 ++-- examples/host/cdc_msc_hid/CMakeLists.txt | 5 +++++ examples/host/cdc_msc_hid/src/tusb_config.h | 6 +++--- examples/host/hid_controller/CMakeLists.txt | 5 +++++ examples/host/hid_controller/src/tusb_config.h | 7 +++---- examples/host/msc_file_explorer/CMakeLists.txt | 4 ++++ examples/host/msc_file_explorer/src/tusb_config.h | 6 +++--- hw/bsp/rp2040/family.mk | 3 --- src/class/cdc/cdc_host.c | 8 ++++---- src/common/tusb_common.h | 6 ++++++ src/common/tusb_types.h | 5 ----- 12 files changed, 40 insertions(+), 24 deletions(-) (limited to 'src') diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt index 4879613b4..616edd4ac 100644 --- a/examples/host/bare_api/CMakeLists.txt +++ b/examples/host/bare_api/CMakeLists.txt @@ -25,3 +25,8 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. family_configure_host_example(${PROJECT}) + +# Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host +if(FAMILY STREQUAL "rp2040") + family_add_pico_pio_usb(${PROJECT}) +endif() diff --git a/examples/host/bare_api/src/tusb_config.h b/examples/host/bare_api/src/tusb_config.h index 701aa6d90..64be41a4e 100644 --- a/examples/host/bare_api/src/tusb_config.h +++ b/examples/host/bare_api/src/tusb_config.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -100,7 +100,7 @@ // max device support (excluding hub device) // 1 hub typically has 4 ports -#define CFG_TUH_DEVICE_MAX (CFG_TUH_HUB ? 4 : 1) +#define CFG_TUH_DEVICE_MAX (3*CFG_TUH_HUB + 1) // Max endpoint per device #define CFG_TUH_ENDPOINT_MAX 8 diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt index dbba6bf44..d7d1a54d7 100644 --- a/examples/host/cdc_msc_hid/CMakeLists.txt +++ b/examples/host/cdc_msc_hid/CMakeLists.txt @@ -28,3 +28,8 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. family_configure_host_example(${PROJECT}) + +# Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host +if(FAMILY STREQUAL "rp2040") + family_add_pico_pio_usb(${PROJECT}) +endif() diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index 139a921d1..4b50f2096 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -101,8 +101,8 @@ #define CFG_TUH_MSC 1 #define CFG_TUH_VENDOR 0 -// max device support (excluding hub device) -#define CFG_TUH_DEVICE_MAX (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports +// max device support (excluding hub device): 1 hub typically has 4 ports +#define CFG_TUH_DEVICE_MAX (3*CFG_TUH_HUB + 1) //------------- HID -------------// #define CFG_TUH_HID_EPIN_BUFSIZE 64 diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt index aa50b5a52..ac3070b82 100644 --- a/examples/host/hid_controller/CMakeLists.txt +++ b/examples/host/hid_controller/CMakeLists.txt @@ -26,3 +26,8 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. family_configure_host_example(${PROJECT}) + +# Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host +if(FAMILY STREQUAL "rp2040") + family_add_pico_pio_usb(${PROJECT}) +endif() diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h index e6d6f873d..2e0dd0dbe 100644 --- a/examples/host/hid_controller/src/tusb_config.h +++ b/examples/host/hid_controller/src/tusb_config.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -101,9 +101,8 @@ #define CFG_TUH_MSC 0 #define CFG_TUH_VENDOR 0 -// max device support (excluding hub device) -// 1 hub typically has 4 ports -#define CFG_TUH_DEVICE_MAX (CFG_TUH_HUB ? 4 : 1) +// max device support (excluding hub device): 1 hub typically has 4 ports +#define CFG_TUH_DEVICE_MAX (3*CFG_TUH_HUB + 1) //------------- HID -------------// diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt index 2c06eafee..7955b3078 100644 --- a/examples/host/msc_file_explorer/CMakeLists.txt +++ b/examples/host/msc_file_explorer/CMakeLists.txt @@ -32,3 +32,7 @@ target_include_directories(${PROJECT} PUBLIC # in hw/bsp/FAMILY/family.cmake for details. family_configure_host_example(${PROJECT}) +# Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host +if(FAMILY STREQUAL "rp2040") + family_add_pico_pio_usb(${PROJECT}) +endif() diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h index ddf8368f4..eaf3ea6d4 100644 --- a/examples/host/msc_file_explorer/src/tusb_config.h +++ b/examples/host/msc_file_explorer/src/tusb_config.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -101,8 +101,8 @@ #define CFG_TUH_HID 0 // typical keyboard + mouse device can have 3-4 HID interfaces #define CFG_TUH_VENDOR 0 -// max device support (excluding hub device) -#define CFG_TUH_DEVICE_MAX (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports +// max device support (excluding hub device): 1 hub typically has 4 ports +#define CFG_TUH_DEVICE_MAX (3*CFG_TUH_HUB + 1) //------------- MSC -------------// #define CFG_TUH_MSC_MAXLUN 4 // typical for most card reader diff --git a/hw/bsp/rp2040/family.mk b/hw/bsp/rp2040/family.mk index cf6b53793..25d1ad9c5 100644 --- a/hw/bsp/rp2040/family.mk +++ b/hw/bsp/rp2040/family.mk @@ -13,9 +13,6 @@ $(BUILD): all: $(BUILD) $(MAKE) -C $(BUILD) -clean: - $(RM) -rf $(BUILD) - flash: flash-pyocd flash-uf2: @$(CP) $(BUILD)/$(PROJECT).uf2 /media/$(USER)/RPI-RP2 diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index e9c3d34cb..011ee49dc 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -97,7 +97,7 @@ static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr) } } - return TUSB_INDEX_INVALID; + return TU_INDEX_INVALID_8; } @@ -124,7 +124,7 @@ uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num) if (p_cdc->daddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i; } - return TUSB_INDEX_INVALID; + return TU_INDEX_INVALID_8; } bool tuh_cdc_itf_get_info(uint8_t idx, tuh_cdc_itf_info_t* info) @@ -533,7 +533,7 @@ static void process_cdc_config(tuh_xfer_t* xfer) uintptr_t const state = xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - TU_ASSERT(idx != TUSB_INDEX_INVALID, ); + TU_ASSERT(idx != TU_INDEX_INVALID_8, ); switch(state) { diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 957491aa9..faccf8726 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -75,6 +75,12 @@ #include "tusb_timeout.h" // TODO remove +enum +{ + TU_INDEX_INVALID_8 = 0xFFu +}; + + //--------------------------------------------------------------------+ // Optional API implemented by application if needed // TODO move to a more ovious place/file diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 7266a525e..d567bd482 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -273,11 +273,6 @@ enum CONTROL_STAGE_ACK }; -enum -{ - TUSB_INDEX_INVALID = 0xff -}; - //--------------------------------------------------------------------+ // USB Descriptors //--------------------------------------------------------------------+ -- cgit v1.3.1 From e1fda007f6ad7f05452cd2bb02f8578197b9339e Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 17 Mar 2023 14:46:02 +0700 Subject: minor refactor to invalid index --- src/host/usbh.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 45a2a0c66..aeab681e9 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -118,10 +118,6 @@ typedef struct { // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -// Invalid driver ID in itf2drv[] ep2drv[][] mapping -enum { DRVID_INVALID = 0xFFu }; -enum { CONTROLLER_INVALID = 0xFFu }; - #if CFG_TUSB_DEBUG >= 2 #define DRIVER_NAME(_name) .name = _name, #else @@ -199,7 +195,7 @@ enum { CONFIG_NUM = 1 }; // default to use configuration 1 // sum of end device + hub #define TOTAL_DEVICES (CFG_TUH_DEVICE_MAX + CFG_TUH_HUB) -static uint8_t _usbh_controller = CONTROLLER_INVALID; +static uint8_t _usbh_controller = TU_INDEX_INVALID_8; // Device with address = 0 for enumeration static usbh_dev0_t _dev0; @@ -307,13 +303,13 @@ tusb_speed_t tuh_speed_get (uint8_t dev_addr) static void clear_device(usbh_device_t* dev) { tu_memclr(dev, sizeof(usbh_device_t)); - memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping - memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping + memset(dev->itf2drv, TU_INDEX_INVALID_8, sizeof(dev->itf2drv)); // invalid mapping + memset(dev->ep2drv , TU_INDEX_INVALID_8, sizeof(dev->ep2drv )); // invalid mapping } bool tuh_inited(void) { - return _usbh_controller != CONTROLLER_INVALID; + return _usbh_controller != TU_INDEX_INVALID_8; } bool tuh_init(uint8_t controller_id) @@ -402,11 +398,11 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) // one device before enumerating another one. if ( _dev0.enumerating ) { - TU_LOG1("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport); + TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport); osal_queue_send(_usbh_q, &event, in_isr); }else { - TU_LOG1("[%u:] USBH DEVICE ATTACH\r\n", event.rhport); + TU_LOG_USBH("[%u:] USBH DEVICE ATTACH\r\n", event.rhport); _dev0.enumerating = 1; enum_new_device(&event); } @@ -1362,11 +1358,11 @@ static void process_enumeration(tuh_xfer_t* xfer) dev->configured = 1; - // Start the Set Configuration process for interfaces (itf = DRVID_INVALID) + // Start the Set Configuration process for interfaces (itf = TU_INDEX_INVALID_8) // Since driver can perform control transfer within its set_config, this is done asynchronously. // The process continue with next interface when class driver complete its sequence with usbh_driver_set_config_complete() - // TODO use separated API instead of using DRVID_INVALID - usbh_driver_set_config_complete(daddr, DRVID_INVALID); + // TODO use separated API instead of using TU_INDEX_INVALID_8 + usbh_driver_set_config_complete(daddr, TU_INDEX_INVALID_8); } break; @@ -1566,7 +1562,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur uint8_t const itf_num = desc_itf->bInterfaceNumber+i; // Interface number must not be used already - TU_ASSERT( DRVID_INVALID == dev->itf2drv[itf_num] ); + TU_ASSERT( TU_INDEX_INVALID_8 == dev->itf2drv[itf_num] ); dev->itf2drv[itf_num] = drv_id; } @@ -1600,7 +1596,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) // IAD binding interface such as CDCs should return itf_num + 1 when complete // with usbh_driver_set_config_complete() uint8_t const drv_id = dev->itf2drv[itf_num]; - if (drv_id != DRVID_INVALID) + if (drv_id != TU_INDEX_INVALID_8) { usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id]; TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num); -- cgit v1.3.1 From 3623ba1884ddff23e9b64766cb6dd032f1425846 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 17 Mar 2023 16:12:49 +0700 Subject: fix trailing space and new line temporarily disable codespell --- .gitattributes | 6 +- .github/ISSUE_TEMPLATE/bug_report.yml | 6 +- .github/workflows/trigger.yml | 4 +- .pre-commit-config.yaml | 10 +- .readthedocs.yaml | 1 - docs/assets/stack.svg | 2 +- docs/contributing/code_of_conduct.rst | 2 +- docs/info/changelog.rst | 54 +- docs/info/contributors.rst | 2 +- docs/reference/getting_started.rst | 14 +- examples/device/audio_4_channel_mic/skip.txt | 2 +- examples/device/audio_4_channel_mic/src/main.c | 2 +- .../audio_4_channel_mic/src/plot_audio_samples.py | 1 - .../audio_4_channel_mic/src/usb_descriptors.c | 2 +- examples/device/audio_test/CMakeLists.txt | 2 +- examples/device/audio_test/skip.txt | 2 +- examples/device/audio_test/src/main.c | 2 +- .../device/audio_test/src/plot_audio_samples.py | 3 +- examples/device/audio_test/src/usb_descriptors.c | 2 +- .../device/audio_test_multi_rate/CMakeLists.txt | 2 +- examples/device/audio_test_multi_rate/skip.txt | 2 +- examples/device/audio_test_multi_rate/src/main.c | 10 +- .../src/plot_audio_samples.py | 3 +- .../device/audio_test_multi_rate/src/tusb_config.h | 2 +- .../audio_test_multi_rate/src/usb_descriptors.c | 2 +- .../audio_test_multi_rate/src/usb_descriptors.h | 4 +- examples/device/board_test/src/CMakeLists.txt | 2 +- examples/device/board_test/src/main.c | 2 +- examples/device/cdc_dual_ports/CMakeLists.txt | 2 +- examples/device/cdc_dual_ports/src/main.c | 2 +- .../device/cdc_dual_ports/src/usb_descriptors.c | 2 +- examples/device/cdc_msc/CMakeLists.txt | 2 +- examples/device/cdc_msc/skip.txt | 2 +- examples/device/cdc_msc/src/main.c | 2 +- examples/device/cdc_msc/src/msc_disk.c | 2 +- examples/device/cdc_msc/src/usb_descriptors.c | 2 +- examples/device/cdc_msc_freertos/src/main.c | 2 +- examples/device/cdc_msc_freertos/src/msc_disk.c | 2 +- .../device/cdc_msc_freertos/src/usb_descriptors.c | 2 +- examples/device/dfu_runtime/CMakeLists.txt | 2 +- examples/device/dfu_runtime/src/main.c | 2 +- .../device/dynamic_configuration/CMakeLists.txt | 2 +- examples/device/dynamic_configuration/skip.txt | 2 +- examples/device/dynamic_configuration/src/main.c | 2 +- .../device/dynamic_configuration/src/msc_disk.c | 2 +- .../dynamic_configuration/src/usb_descriptors.c | 2 +- examples/device/hid_boot_interface/CMakeLists.txt | 2 +- examples/device/hid_boot_interface/Makefile | 2 +- examples/device/hid_boot_interface/src/main.c | 2 +- .../hid_boot_interface/src/usb_descriptors.c | 2 +- .../hid_boot_interface/src/usb_descriptors.h | 2 +- examples/device/hid_composite/CMakeLists.txt | 2 +- examples/device/hid_composite/src/main.c | 2 +- .../device/hid_composite/src/usb_descriptors.c | 2 +- .../device/hid_composite/src/usb_descriptors.h | 2 +- examples/device/hid_composite_freertos/src/main.c | 2 +- .../hid_composite_freertos/src/usb_descriptors.c | 2 +- .../hid_composite_freertos/src/usb_descriptors.h | 2 +- examples/device/hid_generic_inout/CMakeLists.txt | 2 +- examples/device/hid_generic_inout/hid_test.js | 3 +- examples/device/hid_generic_inout/src/main.c | 2 +- .../device/hid_generic_inout/src/usb_descriptors.c | 2 +- .../device/hid_multiple_interface/CMakeLists.txt | 2 +- examples/device/midi_test/CMakeLists.txt | 2 +- examples/device/midi_test/src/main.c | 2 +- examples/device/midi_test/src/usb_descriptors.c | 2 +- examples/device/msc_dual_lun/CMakeLists.txt | 2 +- examples/device/msc_dual_lun/skip.txt | 2 +- examples/device/msc_dual_lun/src/main.c | 2 +- examples/device/msc_dual_lun/src/msc_disk_dual.c | 2 +- examples/device/msc_dual_lun/src/usb_descriptors.c | 2 +- examples/device/net_lwip_webserver/CMakeLists.txt | 2 +- examples/device/net_lwip_webserver/skip.txt | 2 +- examples/device/net_lwip_webserver/src/arch/cc.h | 32 +- examples/device/net_lwip_webserver/src/lwipopts.h | 28 +- examples/device/net_lwip_webserver/src/main.c | 6 +- .../net_lwip_webserver/src/usb_descriptors.c | 4 +- examples/device/uac2_headset/CMakeLists.txt | 2 +- examples/device/uac2_headset/src/main.c | 4 +- examples/device/uac2_headset/src/usb_descriptors.c | 2 +- examples/device/uac2_headset/src/usb_descriptors.h | 2 +- examples/device/usbtmc/CMakeLists.txt | 2 +- examples/device/usbtmc/src/main.c | 2 +- examples/device/usbtmc/visaQuery.py | 26 +- examples/device/video_capture/CMakeLists.txt | 2 +- examples/device/video_capture/src/main.c | 2 +- .../device/video_capture/src/usb_descriptors.c | 2 +- .../device/video_capture/src/usb_descriptors.h | 2 +- examples/device/webusb_serial/CMakeLists.txt | 2 +- examples/device/webusb_serial/src/main.c | 2 +- .../device/webusb_serial/src/usb_descriptors.c | 2 +- .../device/webusb_serial/src/usb_descriptors.h | 2 +- examples/dual/host_hid_to_device_cdc/src/main.c | 2 +- .../host_hid_to_device_cdc/src/usb_descriptors.c | 2 +- examples/host/bare_api/src/main.c | 2 +- examples/host/cdc_msc_hid/src/main.c | 2 +- examples/host/cdc_msc_hid/src/msc_app.c | 3 +- examples/host/hid_controller/src/main.c | 2 +- examples/host/msc_file_explorer/src/main.c | 2 +- examples/host/msc_file_explorer/src/msc_app.c | 2 +- examples/rules.mk | 2 +- hw/bsp/ansi_escape.h | 2 +- hw/bsp/board.c | 2 +- hw/bsp/board.h | 2 +- .../boards/raspberrypi_zero_w/board.h | 2 +- .../boards/raspberrypi_zero_w/board.mk | 2 +- hw/bsp/broadcom_32bit/family.c | 2 +- .../broadcom_64bit/boards/raspberrypi_cm4/board.h | 2 +- .../boards/raspberrypi_zero2w/board.h | 2 +- hw/bsp/broadcom_64bit/family.c | 2 +- hw/bsp/brtmm90x/family.c | 7 +- hw/bsp/brtmm90x/family.mk | 8 +- hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h | 2 +- .../ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c | 4 +- hw/bsp/ch32v307/ch32v307.ld | 35 +- hw/bsp/ch32v307/ch32v30x_conf.h | 7 +- hw/bsp/ch32v307/ch32v30x_it.c | 2 - hw/bsp/ch32v307/ch32v30x_it.h | 2 - hw/bsp/ch32v307/core_riscv.h | 7 +- hw/bsp/ch32v307/system_ch32v30x.c | 140 ++--- hw/bsp/ch32v307/system_ch32v30x.h | 9 +- hw/bsp/da14695_dk_usb/da14695_dk_usb.c | 2 +- hw/bsp/da14695_dk_usb/da1469x.ld | 1 - hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c | 2 +- hw/bsp/da1469x_dk_pro/da1469x.ld | 1 - hw/bsp/ea4088qs/ea4088qs.c | 2 +- hw/bsp/ea4088qs/lpc4088.ld | 54 +- hw/bsp/ea4357/ea4357.c | 2 +- hw/bsp/ea4357/lpc4357.ld | 106 ++-- hw/bsp/ea4357/pca9532.c | 6 +- hw/bsp/ea4357/pca9532.h | 2 +- hw/bsp/esp32s2/boards/CMakeLists.txt | 2 +- .../boards/adafruit_feather_esp32s2/board.cmake | 2 +- .../boards/adafruit_feather_esp32s2/board.h | 2 +- .../boards/adafruit_magtag_29gray/board.cmake | 2 +- .../esp32s2/boards/adafruit_magtag_29gray/board.h | 2 +- .../boards/adafruit_metro_esp32s2/board.cmake | 2 +- .../esp32s2/boards/adafruit_metro_esp32s2/board.h | 2 +- hw/bsp/esp32s2/boards/esp32s2.c | 3 +- .../esp32s2/boards/espressif_kaluga_1/board.cmake | 2 +- hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h | 2 +- .../esp32s2/boards/espressif_saola_1/board.cmake | 2 +- hw/bsp/esp32s2/boards/espressif_saola_1/board.h | 2 +- hw/bsp/esp32s2/components/led_strip/CMakeLists.txt | 1 - hw/bsp/esp32s2/family.cmake | 2 +- hw/bsp/esp32s2/family.mk | 1 - hw/bsp/esp32s3/boards/CMakeLists.txt | 2 +- hw/bsp/esp32s3/boards/esp32s3.c | 3 +- .../esp32s3/boards/espressif_addax_1/board.cmake | 2 +- hw/bsp/esp32s3/boards/espressif_addax_1/board.h | 2 +- .../boards/espressif_s3_devkitc/board.cmake | 2 +- hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h | 2 +- .../boards/espressif_s3_devkitm/board.cmake | 2 +- hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h | 2 +- hw/bsp/esp32s3/components/led_strip/CMakeLists.txt | 1 - hw/bsp/esp32s3/family.cmake | 2 +- hw/bsp/esp32s3/family.mk | 1 - hw/bsp/f1c100s/README.md | 2 +- hw/bsp/f1c100s/board.h | 2 +- hw/bsp/f1c100s/board.mk | 6 +- hw/bsp/f1c100s/f1c100s.c | 4 +- hw/bsp/family_support.cmake | 2 +- hw/bsp/fomu/boards/fomu/board.mk | 2 +- hw/bsp/fomu/fomu.c | 2 +- hw/bsp/fomu/include/hw/common.h | 2 +- hw/bsp/fomu/include/irq.h | 2 +- hw/bsp/frdm_k32l2b/board.h | 2 +- hw/bsp/frdm_k32l2b/frdm_k32l2b.c | 12 +- hw/bsp/frdm_kl25z/frdm_kl25z.c | 4 +- hw/bsp/gd32vf103/family.c | 2 +- hw/bsp/gd32vf103/system_gd32vf103.c | 10 +- hw/bsp/imxrt/boards/metro_m7_1011/board.h | 2 +- hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld | 2 +- hw/bsp/imxrt/boards/mimxrt1010_evk/board.h | 2 +- hw/bsp/imxrt/boards/mimxrt1015_evk/board.h | 2 +- hw/bsp/imxrt/boards/mimxrt1020_evk/board.h | 2 +- hw/bsp/imxrt/boards/mimxrt1024_evk/board.h | 2 +- hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h | 2 +- hw/bsp/imxrt/boards/mimxrt1060_evk/board.h | 2 +- hw/bsp/imxrt/boards/mimxrt1064_evk/board.h | 2 +- hw/bsp/imxrt/boards/teensy_40/board.h | 2 +- hw/bsp/imxrt/boards/teensy_40/board.mk | 2 +- hw/bsp/imxrt/boards/teensy_41/board.h | 2 +- hw/bsp/imxrt/boards/teensy_41/board.mk | 2 +- hw/bsp/imxrt/family.c | 2 +- hw/bsp/kuiic/K32L2B31xxxxA_flash.ld | 1 - hw/bsp/kuiic/board.h | 2 +- hw/bsp/kuiic/kuiic.c | 16 +- hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld | 60 +- hw/bsp/lpc15/family.c | 2 +- hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld | 86 +-- hw/bsp/lpc18/boards/mcb1800/lpc1857.ld | 106 ++-- hw/bsp/lpc18/family.c | 2 +- hw/bsp/lpc54/boards/lpcxpresso54628/board.mk | 2 +- hw/bsp/lpc54/family.c | 2 +- .../double_m33_express/LPC55S69_cm33_core0_uf2.ld | 1 - hw/bsp/lpc55/family.c | 2 +- hw/bsp/lpcxpresso11u37/lpc11u37.ld | 50 +- hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c | 2 +- hw/bsp/lpcxpresso11u68/lpc11u68.ld | 68 +-- hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c | 2 +- hw/bsp/lpcxpresso1347/lpc1347.ld | 68 +-- hw/bsp/lpcxpresso1347/lpcxpresso1347.c | 4 +- hw/bsp/lpcxpresso1769/lpc1769.ld | 54 +- hw/bsp/lpcxpresso1769/lpcxpresso1769.c | 2 +- hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c | 2 +- hw/bsp/mbed1768/lpc1768.ld | 54 +- hw/bsp/mbed1768/mbed1768.c | 2 +- hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld | 8 +- hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c | 4 +- hw/bsp/ngx4330/ngx4330.c | 2 +- hw/bsp/ngx4330/ngx4330.ld | 80 +-- hw/bsp/nrf/boards/adafruit_clue/board.h | 2 +- .../nrf/boards/adafruit_clue/nrf52840_s140_v6.ld | 4 +- .../arduino_nano33_ble/arduino_nano33_ble.ld | 2 +- hw/bsp/nrf/boards/arduino_nano33_ble/board.h | 2 +- .../nrf/boards/circuitplayground_bluefruit/board.h | 2 +- .../nrf52840_s140_v6.ld | 4 +- hw/bsp/nrf/boards/feather_nrf52840_express/board.h | 2 +- .../feather_nrf52840_express/nrf52840_s140_v6.ld | 4 +- hw/bsp/nrf/boards/feather_nrf52840_sense/board.h | 2 +- .../feather_nrf52840_sense/nrf52840_s140_v6.ld | 4 +- hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h | 2 +- .../boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld | 4 +- hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h | 2 +- hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk | 2 +- hw/bsp/nrf/boards/pca10056/board.h | 2 +- hw/bsp/nrf/boards/pca10059/board.h | 2 +- hw/bsp/nrf/boards/pca10100/board.h | 2 +- hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h | 2 +- hw/bsp/nrf/family.c | 2 +- hw/bsp/nutiny_nuc121s/nuc121_flash.ld | 2 +- hw/bsp/nutiny_nuc121s/nutiny_nuc121.c | 2 +- hw/bsp/nutiny_nuc125s/nuc125_flash.ld | 2 +- hw/bsp/nutiny_nuc125s/nutiny_nuc125.c | 2 +- hw/bsp/nutiny_nuc126v/nutiny_nuc126.c | 2 +- hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c | 2 +- hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c | 2 +- hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c | 2 +- hw/bsp/pic32mz/family.c | 2 +- hw/bsp/rp2040/board.h | 2 +- hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake | 2 +- hw/bsp/rp2040/family.cmake | 2 +- hw/bsp/rx/boards/gr_citrus/gr_citrus.c | 6 +- hw/bsp/rx/boards/rx65n_target/rx65n_target.c | 2 +- .../boards/samd11_xplained/samd11d14am_flash.ld | 4 +- hw/bsp/samd21/boards/atsamd21_xpro/board.h | 2 +- .../boards/circuitplayground_express/board.h | 2 +- hw/bsp/samd21/boards/curiosity_nano/board.h | 2 +- hw/bsp/samd21/boards/feather_m0_express/board.h | 2 +- hw/bsp/samd21/boards/itsybitsy_m0/board.h | 2 +- hw/bsp/samd21/boards/luna_d21/board.h | 2 +- hw/bsp/samd21/boards/luna_d21/board.mk | 1 - hw/bsp/samd21/boards/metro_m0_express/board.h | 2 +- hw/bsp/samd21/boards/qtpy/board.h | 2 +- hw/bsp/samd21/boards/seeeduino_xiao/board.h | 2 +- hw/bsp/samd21/boards/trinket_m0/board.h | 1 - hw/bsp/samd21/boards/trinket_m0/board.mk | 1 - hw/bsp/samd21/family.c | 2 +- hw/bsp/samd51/boards/feather_m4_express/board.h | 2 +- hw/bsp/samd51/boards/itsybitsy_m4/board.h | 2 +- hw/bsp/samd51/boards/metro_m4_express/board.h | 2 +- hw/bsp/samd51/boards/metro_m4_express/board.mk | 1 - hw/bsp/samd51/boards/pybadge/board.h | 2 +- hw/bsp/samd51/boards/pyportal/board.h | 2 +- hw/bsp/samd51/family.c | 2 +- hw/bsp/same54xplainedpro/same54p20a_flash.ld | 4 +- hw/bsp/same54xplainedpro/same54p20a_sram.ld | 4 +- hw/bsp/samg55xplained/samg55xplained.c | 2 +- hw/bsp/saml2x/boards/atsaml21_xpro/board.h | 2 +- hw/bsp/saml2x/boards/saml22_feather/board.h | 2 +- .../saml2x/boards/saml22_feather/saml22_feather.ld | 4 +- hw/bsp/saml2x/boards/sensorwatch_m0/board.h | 2 +- .../saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld | 4 +- hw/bsp/saml2x/family.c | 2 +- hw/bsp/sltb009a/sltb009a.c | 4 +- hw/bsp/spresense/board_spresense.c | 6 +- hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h | 2 +- hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk | 2 +- .../stm32f070rbnucleo/stm32F070rbtx_flash.ld | 14 +- .../boards/stm32f072disco/STM32F072RBTx_FLASH.ld | 8 +- hw/bsp/stm32f0/boards/stm32f072disco/board.h | 2 +- hw/bsp/stm32f0/boards/stm32f072eval/board.h | 2 +- hw/bsp/stm32f0/family.c | 2 +- hw/bsp/stm32f0/stm32f0xx_hal_conf.h | 51 +- .../boards/stm32f103_bluepill/STM32F103X8_FLASH.ld | 6 +- hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h | 2 +- .../boards/stm32f103_mini_2/STM32F103XC_FLASH.ld | 6 +- hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h | 2 +- hw/bsp/stm32f1/family.c | 8 +- hw/bsp/stm32f1/stm32f1xx_hal_conf.h | 44 +- hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld | 8 +- hw/bsp/stm32f207nucleo/stm32f207nucleo.c | 4 +- hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h | 56 +- hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld | 18 +- hw/bsp/stm32f303disco/stm32f303disco.c | 2 +- hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h | 38 +- .../feather_stm32f405/STM32F405RGTx_FLASH.ld | 18 +- hw/bsp/stm32f4/boards/feather_stm32f405/board.h | 2 +- .../boards/pyboardv11/STM32F405RGTx_FLASH.ld | 18 +- hw/bsp/stm32f4/boards/pyboardv11/board.h | 2 +- .../stm32f401blackpill/STM32F401VCTx_FLASH.ld | 8 +- hw/bsp/stm32f4/boards/stm32f401blackpill/board.h | 2 +- .../boards/stm32f401blackpill/stm32f4xx_hal_conf.h | 82 +-- .../boards/stm32f407disco/STM32F407VGTx_FLASH.ld | 18 +- hw/bsp/stm32f4/boards/stm32f407disco/board.h | 2 +- .../boards/stm32f407disco/stm32f4xx_hal_conf.h | 82 +-- .../stm32f411blackpill/STM32F411CEUx_FLASH.ld | 8 +- hw/bsp/stm32f4/boards/stm32f411blackpill/board.h | 2 +- .../boards/stm32f411blackpill/stm32f4xx_hal_conf.h | 82 +-- .../boards/stm32f411disco/STM32F411VETx_FLASH.ld | 8 +- hw/bsp/stm32f4/boards/stm32f411disco/board.h | 2 +- .../boards/stm32f411disco/stm32f4xx_hal_conf.h | 82 +-- .../boards/stm32f412disco/STM32F412ZGTx_FLASH.ld | 8 +- hw/bsp/stm32f4/boards/stm32f412disco/board.h | 2 +- .../boards/stm32f412disco/stm32f4xx_hal_conf.h | 82 +-- .../boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld | 8 +- .../boards/stm32f412nucleo/stm32f4xx_hal_conf.h | 82 +-- .../boards/stm32f439nucleo/stm32f4xx_hal_conf.h | 70 +-- hw/bsp/stm32f4/family.c | 2 +- hw/bsp/stm32f7/boards/stlinkv3mini/board.h | 2 +- hw/bsp/stm32f7/boards/stm32f723disco/board.h | 2 +- hw/bsp/stm32f7/boards/stm32f746disco/board.h | 2 +- .../boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld | 6 +- hw/bsp/stm32f7/boards/stm32f746nucleo/board.h | 2 +- .../boards/stm32f746nucleo/stm32f7xx_hal_conf.h | 52 +- .../boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld | 8 +- hw/bsp/stm32f7/boards/stm32f767nucleo/board.h | 2 +- hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk | 2 +- .../boards/stm32f767nucleo/stm32f7xx_hal_conf.h | 52 +- hw/bsp/stm32f7/boards/stm32f769disco/board.h | 2 +- .../boards/stm32g474nucleo/STM32G474RETx_FLASH.ld | 8 +- hw/bsp/stm32g4/family.c | 2 +- hw/bsp/stm32g4/stm32g4xx_hal_conf.h | 26 +- hw/bsp/stm32h7/boards/daisyseed/board.mk | 1 - .../boards/daisyseed/stm32h750ibkx_flash.ld | 2 - .../boards/stm32h743eval/stm32h743xx_flash.ld | 8 +- .../boards/stm32h743nucleo/stm32h743xx_flash.ld | 8 +- hw/bsp/stm32h7/boards/stm32h745disco/board.mk | 1 - .../waveshare_openh743i/STM32H743IITX_FLASH.ld | 2 - hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk | 2 +- hw/bsp/stm32h7/family.c | 2 +- hw/bsp/stm32h7/stm32h7xx_hal_conf.h | 6 +- .../boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld | 8 +- hw/bsp/stm32l0/boards/stm32l052dap52/board.h | 34 +- hw/bsp/stm32l0/family.c | 2 +- hw/bsp/stm32l0/stm32l0xx_hal_conf.h | 49 +- hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld | 8 +- hw/bsp/stm32l0538disco/stm32l0538disco.c | 2 +- hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h | 102 ++-- .../boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld | 14 +- hw/bsp/stm32l4/boards/stm32l412nucleo/board.h | 6 +- .../boards/stm32l476disco/STM32L476VGTx_FLASH.ld | 14 +- hw/bsp/stm32l4/boards/stm32l476disco/board.h | 2 +- .../boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld | 12 +- hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h | 2 +- .../boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld | 6 +- hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h | 2 +- hw/bsp/stm32l4/stm32l4xx_hal_conf.h | 10 +- hw/bsp/stm32u5/stm32u5xx_hal_conf.h | 1 - .../stm32wb55nucleo/stm32wb55xx_flash_cm4.ld | 8 +- hw/bsp/stm32wb/family.c | 2 +- hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk | 2 +- hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld | 24 +- hw/bsp/tm4c123/family.c | 1 - hw/bsp/xmc4000/boards/xmc4500_relax/board.h | 2 +- hw/mcu/bridgetek/ft9xx/Readme.md | 4 +- hw/mcu/bridgetek/ft9xx/scripts/crt0.S | 8 +- hw/mcu/dialog/README.md | 4 +- .../da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt | 1 - .../sdk/bsp/include/cmsis_compiler.h | 1 - .../SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h | 10 +- .../SDK_10.0.8.105/sdk/bsp/include/core_cm0.h | 2 +- .../SDK_10.0.8.105/sdk/bsp/include/core_cm33.h | 4 +- .../SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h | 33 +- hw/mcu/dialog/da1469x/da1469x.ld | 1 - hw/mcu/dialog/da1469x/include/mcu/mcu.h | 1 - .../nrf5x/s140_nrf52_6.1.1_API/include/ble.h | 2 +- .../nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h | 2 +- lib/SEGGER_RTT/RTT/SEGGER_RTT.c | 16 +- lib/SEGGER_RTT/RTT/SEGGER_RTT.h | 2 +- lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S | 6 +- lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h | 12 +- lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c | 4 +- lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c | 42 +- lib/fatfs/source/00history.txt | 1 - lib/fatfs/source/00readme.txt | 1 - lib/fatfs/source/diskio.c | 1 - lib/fatfs/source/ff.c | 1 - lib/fatfs/source/ffsystem.c | 1 - lib/networking/dhserver.c | 10 +- lib/networking/dhserver.h | 6 +- lib/networking/dnserver.c | 8 +- lib/networking/dnserver.h | 6 +- lib/networking/ndis.h | 10 +- lib/networking/rndis_protocol.h | 28 +- lib/networking/rndis_reports.c | 14 +- src/class/audio/audio.h | 6 +- src/class/audio/audio_device.c | 6 +- src/class/audio/audio_device.h | 4 +- src/class/bth/bth_device.h | 2 +- src/class/cdc/cdc_device.c | 12 +- src/class/cdc/cdc_device.h | 2 +- src/class/cdc/cdc_host.h | 2 +- src/class/cdc/cdc_rndis.h | 2 +- src/class/cdc/cdc_rndis_host.c | 2 +- src/class/cdc/cdc_rndis_host.h | 2 +- src/class/hid/hid.h | 2 +- src/class/midi/midi.h | 2 +- src/class/midi/midi_device.c | 2 +- src/class/midi/midi_device.h | 2 +- src/class/msc/msc.h | 2 +- src/class/msc/msc_device.h | 2 +- src/class/msc/msc_host.c | 12 +- src/class/msc/msc_host.h | 2 +- src/class/net/ecm_rndis_device.c | 2 +- src/class/net/ncm_device.c | 2 +- src/class/net/net_device.h | 2 +- src/class/usbtmc/usbtmc.h | 1 - src/class/usbtmc/usbtmc_device.c | 4 +- src/class/vendor/vendor_device.h | 2 +- src/class/vendor/vendor_host.c | 2 +- src/class/vendor/vendor_host.h | 2 +- src/class/video/video_device.c | 2 +- src/common/tusb_compiler.h | 4 +- src/common/tusb_timeout.h | 2 +- src/common/tusb_verify.h | 2 +- src/device/dcd.h | 2 +- src/device/usbd.c | 4 +- src/device/usbd_pvt.h | 2 +- src/host/hcd.h | 2 +- src/host/hub.c | 4 +- src/host/usbh.h | 2 +- src/osal/osal.h | 2 +- src/osal/osal_freertos.h | 2 +- src/osal/osal_none.h | 2 +- src/osal/osal_pico.h | 2 +- src/osal/osal_rtx4.h | 4 +- src/portable/bridgetek/ft9xx/dcd_ft9xx.c | 78 +-- src/portable/chipidea/ci_hs/ci_hs_type.h | 2 +- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 2 +- src/portable/chipidea/ci_hs/hcd_ci_hs.c | 2 +- src/portable/ehci/ehci.c | 6 +- src/portable/espressif/esp32sx/dcd_esp32sx.c | 1 - src/portable/mentor/musb/dcd_musb.c | 8 +- src/portable/mentor/musb/hcd_musb.c | 4 +- src/portable/microchip/pic/dcd_pic.c | 4 +- src/portable/microchip/pic32mz/usbhs_registers.h | 40 +- src/portable/microchip/samg/dcd_samg.c | 2 +- src/portable/microchip/samx7x/common_usb_regs.h | 6 +- src/portable/microchip/samx7x/dcd_samx7x.c | 36 +- src/portable/nordic/nrf5x/dcd_nrf5x.c | 2 +- src/portable/nuvoton/nuc120/dcd_nuc120.c | 6 +- src/portable/nuvoton/nuc121/dcd_nuc121.c | 6 +- src/portable/nuvoton/nuc505/dcd_nuc505.c | 6 +- src/portable/nxp/khci/dcd_khci.c | 6 +- src/portable/nxp/khci/hcd_khci.c | 4 +- src/portable/nxp/lpc17_40/dcd_lpc17_40.c | 2 +- src/portable/nxp/lpc17_40/dcd_lpc17_40.h | 2 +- src/portable/nxp/lpc17_40/hcd_lpc17_40.c | 3 +- src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 7 +- .../nxp/transdimension/common_transdimension.h | 2 +- .../nxp/transdimension/dcd_transdimension.c | 2 +- .../nxp/transdimension/hcd_transdimension.c | 2 +- src/portable/ohci/ohci.c | 3 +- src/portable/raspberrypi/pio_usb/dcd_pio_usb.c | 2 +- src/portable/raspberrypi/rp2040/rp2040_usb.h | 2 +- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 45 +- src/portable/st/synopsys/synopsys_common.h | 672 ++++++++++----------- src/portable/sunxi/dcd_sunxi_musb.c | 6 +- src/portable/template/dcd_template.c | 2 +- src/portable/valentyusb/eptri/dcd_eptri.c | 2 +- src/portable/valentyusb/eptri/dcd_eptri.h | 2 +- src/portable/wch/ch32v307/dcd_usbhs.c | 8 +- test/fuzz/dcd_fuzz.cc | 4 +- test/fuzz/device/cdc/CMakeLists.txt | 2 +- test/fuzz/device/cdc/src/fuzz.cc | 4 +- test/fuzz/device/msc/CMakeLists.txt | 2 +- test/fuzz/device/msc/src/fuzz.cc | 1 - test/fuzz/device/net/CMakeLists.txt | 2 +- test/fuzz/device/net/src/arch/cc.h | 32 +- test/fuzz/device/net/src/fuzz.cc | 2 +- test/fuzz/device/net/src/lwipopts.h | 28 +- test/fuzz/dicts/cdc.dict | 1 - test/fuzz/make.mk | 3 +- test/fuzz/msc_fuzz.cc | 2 +- test/fuzz/net_fuzz.cc | 2 +- test/fuzz/rules.mk | 6 +- test/unit-test/test/device/msc/test_msc_device.c | 2 +- test/unit-test/test/device/usbd/test_usbd.c | 2 +- test/unit-test/test/test_fifo.c | 2 +- test/unit-test/vendor/ceedling/lib/ceedling.rb | 1 - .../ceedling/lib/ceedling/build_invoker_utils.rb | 14 +- .../vendor/ceedling/lib/ceedling/cacheinator.rb | 10 +- .../ceedling/lib/ceedling/cacheinator_helper.rb | 2 +- .../vendor/ceedling/lib/ceedling/cmock_builder.rb | 8 +- .../vendor/ceedling/lib/ceedling/configurator.rb | 1 - .../ceedling/lib/ceedling/configurator_plugins.rb | 2 +- .../ceedling/lib/ceedling/configurator_setup.rb | 2 +- .../lib/ceedling/configurator_validator.rb | 78 +-- .../vendor/ceedling/lib/ceedling/erb_wrapper.rb | 2 +- .../vendor/ceedling/lib/ceedling/file_finder.rb | 1 - .../ceedling/lib/ceedling/file_finder_helper.rb | 22 +- .../ceedling/lib/ceedling/file_system_utils.rb | 14 +- .../ceedling/lib/ceedling/file_system_wrapper.rb | 2 +- .../vendor/ceedling/lib/ceedling/flaginator.rb | 14 +- .../ceedling/lib/ceedling/generator_helper.rb | 8 +- .../lib/ceedling/generator_test_results.rb | 2 +- .../generator_test_results_sanity_checker.rb | 22 +- .../vendor/ceedling/lib/ceedling/loginator.rb | 6 +- .../vendor/ceedling/lib/ceedling/makefile.rb | 4 +- .../vendor/ceedling/lib/ceedling/objects.yml | 2 +- .../vendor/ceedling/lib/ceedling/par_map.rb | 1 - .../vendor/ceedling/lib/ceedling/plugin.rb | 8 +- .../vendor/ceedling/lib/ceedling/plugin_builder.rb | 4 +- .../ceedling/lib/ceedling/plugin_reportinator.rb | 40 +- .../lib/ceedling/plugin_reportinator_helper.rb | 10 +- .../ceedling/preprocessinator_includes_handler.rb | 2 +- .../lib/ceedling/project_config_manager.rb | 2 +- .../vendor/ceedling/lib/ceedling/rake_utils.rb | 2 +- .../vendor/ceedling/lib/ceedling/reportinator.rb | 4 +- .../vendor/ceedling/lib/ceedling/rules_cmock.rake | 2 +- .../ceedling/lib/ceedling/rules_preprocess.rake | 5 +- .../ceedling/lib/ceedling/rules_release.rake | 1 - .../ceedling/rules_release_deep_dependencies.rake | 3 +- .../vendor/ceedling/lib/ceedling/rules_tests.rake | 1 - .../ceedling/rules_tests_deep_dependencies.rake | 1 - .../vendor/ceedling/lib/ceedling/setupinator.rb | 8 +- .../vendor/ceedling/lib/ceedling/stream_wrapper.rb | 2 +- .../vendor/ceedling/lib/ceedling/streaminator.rb | 2 +- .../ceedling/lib/ceedling/streaminator_helper.rb | 2 +- .../vendor/ceedling/lib/ceedling/system_utils.rb | 6 +- .../vendor/ceedling/lib/ceedling/task_invoker.rb | 20 +- .../vendor/ceedling/lib/ceedling/tasks_base.rake | 1 - .../ceedling/lib/ceedling/tasks_filesystem.rake | 2 - .../ceedling/lib/ceedling/tasks_release.rake | 11 +- .../vendor/ceedling/lib/ceedling/tasks_tests.rake | 1 - .../ceedling/lib/ceedling/test_invoker_helper.rb | 8 +- .../vendor/ceedling/plugins/beep/lib/beep.rb | 1 - .../vendor/ceedling/plugins/bullseye/README.md | 2 +- .../ceedling/plugins/bullseye/assets/template.erb | 1 - .../ceedling/plugins/bullseye/lib/bullseye.rb | 26 +- .../ceedling/plugins/colour_report/README.md | 2 +- .../plugins/command_hooks/lib/command_hooks.rb | 1 - .../plugins/compile_commands_json/README.md | 2 +- .../plugins/fake_function_framework/Rakefile | 2 +- .../examples/fff_example/project.yml | 2 +- .../examples/fff_example/src/display.c | 2 +- .../lib/fff_mock_generator.rb | 2 +- .../spec/fff_mock_header_generator_spec.rb | 2 +- .../spec/fff_mock_source_generator_spec.rb | 2 +- .../spec/header_generator.rb | 2 +- .../fake_function_framework/src/fff_unity_helper.h | 2 +- .../ceedling/plugins/gcov/assets/template.erb | 1 - .../plugins/gcov/lib/reportinator_helper.rb | 2 +- .../ceedling/plugins/json_tests_report/README.md | 4 +- .../json_tests_report/lib/json_tests_report.rb | 4 +- .../ceedling/plugins/module_generator/README.md | 4 +- .../module_generator/config/module_generator.yml | 2 +- .../stdout_gtestlike_tests_report/README.md | 4 +- .../plugins/stdout_ide_tests_report/README.md | 2 +- .../plugins/stdout_pretty_tests_report/README.md | 2 +- .../stdout_pretty_tests_report/assets/template.erb | 1 - .../lib/stdout_pretty_tests_report.rb | 8 +- .../vendor/ceedling/plugins/subprojects/README.md | 14 +- .../ceedling/plugins/subprojects/subprojects.rake | 3 +- .../plugins/teamcity_tests_report/README.md | 2 +- .../ceedling/vendor/c_exception/lib/CException.c | 1 - .../ceedling/vendor/c_exception/lib/meson.build | 2 +- .../vendor/ceedling/vendor/cmock/src/cmock.c | 1 - .../vendor/ceedling/vendor/cmock/src/meson.build | 2 +- .../vendor/ceedling/vendor/diy/lib/diy.rb | 60 +- .../vendor/ceedling/vendor/diy/lib/diy/factory.rb | 5 +- .../ceedling/vendor/unity/auto/generate_config.yml | 2 +- .../vendor/ceedling/vendor/unity/src/meson.build | 2 +- tools/build_board.py | 2 +- tools/build_utils.py | 2 +- tools/iar_template.ipcf | 2 +- tools/mksunxi.py | 2 +- tools/pcapng_to_corpus.py | 10 +- tools/usb_drivers/tinyusb_win_usbser.inf | 2 +- 581 files changed, 2553 insertions(+), 2694 deletions(-) (limited to 'src') diff --git a/.gitattributes b/.gitattributes index 2342decc3..140ae8929 100644 --- a/.gitattributes +++ b/.gitattributes @@ -1,10 +1,10 @@ # Set the default behavior, in case people don't have core.autocrlf set. * text=auto -*.c text -*.cpp text +*.c text +*.cpp text *.h text -*.icf text +*.icf text *.js text *.json text *.ld text diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml index 8c39b95e1..dc5f0ee16 100644 --- a/.github/ISSUE_TEMPLATE/bug_report.yml +++ b/.github/ISSUE_TEMPLATE/bug_report.yml @@ -54,7 +54,7 @@ body: Exact steps in chronological order, details should be specific e.g if you use a command/script to test with, please post it as well. 1. Go to '...' 2. Click on '....' - 3. See error + 3. See error validations: required: true @@ -63,9 +63,9 @@ body: label: Debug Log as txt file placeholder: | Attach your debug log txt file here, where the issue occurred, best with comments to explain the actual events. - + Note1: Please DO NOT paste your lengthy log contents here since it hurts the readability. - Note2: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h. + Note2: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h. More information can be found at [example's readme](https://github.com/hathach/tinyusb/blob/master/docs/getting_started.md) validations: required: false diff --git a/.github/workflows/trigger.yml b/.github/workflows/trigger.yml index 11e58d86c..86c699dac 100644 --- a/.github/workflows/trigger.yml +++ b/.github/workflows/trigger.yml @@ -43,7 +43,7 @@ jobs: if [ -n "$(git status --porcelain)" ]; then git add . git commit --message "Update from https://github.com/$GITHUB_REPOSITORY/commit/$GITHUB_SHA" - git push + git push fi - name: Create tinyusb_src Release @@ -53,7 +53,7 @@ jobs: cd tinyusb_src git tag ${{ github.event.release.tag_name }} git push origin ${{ github.event.release.tag_name }} - + # Send POST reqwuest to release https://docs.github.com/en/rest/reference/repos#create-a-release bb="For release note, please checkout https://github.com/hathach/tinyusb/releases/tag/${{ github.event.release.tag_name }}" curl -X POST -H "Authorization: token ${{ secrets.API_TOKEN_GITHUB }}" -H "Accept: application/vnd.github.v3+json" --data '{"tag_name": "${{ github.event.release.tag_name }}", "name": "${{ github.event.release.name }}", "body": "$bb", "draft": ${{ github.event.release.draft }}, "prerelease": ${{ github.event.release.prerelease }}}' https://api.github.com/repos/hathach/tinyusb_src/releases diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index ea2372f07..976f04e63 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -13,11 +13,11 @@ repos: - repo: local hooks: - - id: codespell - name: codespell - entry: codespell - types_or: [c, header] - language: system + #- id: codespell + # name: codespell + # entry: codespell + # types_or: [c, header] + # language: system - id: unit-test name: unit-test diff --git a/.readthedocs.yaml b/.readthedocs.yaml index e83cd90fd..1421b397a 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml @@ -15,4 +15,3 @@ python: submodules: include: [] recursive: false - \ No newline at end of file diff --git a/docs/assets/stack.svg b/docs/assets/stack.svg index 85fe35e96..ed46c8649 100644 --- a/docs/assets/stack.svg +++ b/docs/assets/stack.svg @@ -1 +1 @@ - \ No newline at end of file + diff --git a/docs/contributing/code_of_conduct.rst b/docs/contributing/code_of_conduct.rst index b52bf14c5..82627099f 120000 --- a/docs/contributing/code_of_conduct.rst +++ b/docs/contributing/code_of_conduct.rst @@ -1 +1 @@ -../../CODE_OF_CONDUCT.rst \ No newline at end of file +../../CODE_OF_CONDUCT.rst diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst index 451e3dace..ca715cb58 100644 --- a/docs/info/changelog.rst +++ b/docs/info/changelog.rst @@ -15,7 +15,7 @@ Changelog - Fix tu_fifo memory overflown when repeatedly write to overwritable fifo (accumulated more than 2 depths) - Better support for IAR (ARM) with ci build check for stm32 mcus. - Fix Windows build for some mingw gnu make situations - + Controller Driver (DCD & HCD) ----------------------------- @@ -27,7 +27,7 @@ Controller Driver (DCD & HCD) - Fix endpoint internal state when closed - Fix reception of large ISO packets -- [rp2040] +- [rp2040] - [dcd] Implement workaround for Errata 15. This enable SOF when bulk-in endpoint is in use and reduce its bandwidth to only 80% - [hcd] Fix shared irq slots filling up when hcd_init() is called multiple times @@ -51,7 +51,7 @@ Device Stack - Support port name strings - fix MS Header wTotalLength computation - + - [HID] - Add FIDO descriptor template @@ -60,7 +60,7 @@ Device Stack - [CDC] - Fix autoflush for FIFO < MPS - - Fix tx fifo memory overflown when DTR is not set and tud_cdc_write() is called repeatedly with large enough data + - Fix tx fifo memory overflown when DTR is not set and tud_cdc_write() is called repeatedly with large enough data - [USBTMC] Fix packet size with highspeed @@ -100,14 +100,14 @@ Controller Driver (DCD & HCD) - Fix overwrite with grstctl when disable endpoint - [EHCI] Fix an issue with EHCI driver - [msp430] Fix for possible bug in msp430-elf-gcc 9.3.0 -- [nrf5x] Fix DMA access race condition using atomic function +- [nrf5x] Fix DMA access race condition using atomic function - [pic32] Fix PIC32 santiy - [rp2040] - Add PICO-PIO-USB as controller (device/host) support for rp2040 - Use shared IRQ handlers, so user can also hook the USB IRQ - Fix resumed signal not reported to device stack -- [stm32fsdev] Add support for stm32wb55 +- [stm32fsdev] Add support for stm32wb55 Device Stack ------------ @@ -159,7 +159,7 @@ Controller Driver (DCD & HCD) - [F1C100s] Add new DCD for Allwinner F1C100s family - [PIC32MZ] Add new DCD for PIC32MZ - [nRF] Fix/Enhance various race condition with: EASY DMA, request HFXO, EPOUT -- [ChipIdea] rename Transdimension to more popular ChipIdea Highspeed, +- [ChipIdea] rename Transdimension to more popular ChipIdea Highspeed, - [RP2040] various update/fix for hcd/dcd - [FT9XX] new DCD port for Bridgetek FT90x and FT93x devices - [DA1469X] Fix resume @@ -246,7 +246,7 @@ RP2040 ^^^^^^ - Add RP2040 suspend & resume support -- Implement double buffer for both host and device (#891). However device EPOUT is still single buffered due to techinical issue with short packet +- Implement double buffer for both host and device (#891). However device EPOUT is still single buffered due to techinical issue with short packet Device Stack ------------ @@ -267,7 +267,7 @@ DFU ^^^ - Enhance DFU implementation to support multiple alternate interface and better support bwPollTimeout -- Rename CFG_TUD_DFU_MODE to simply CFG_TUD_DFU +- Rename CFG_TUD_DFU_MODE to simply CFG_TUD_DFU HID ^^^ @@ -287,7 +287,7 @@ UAC2 ^^^^ - Fix bug and enhance of UAC2 - + Vendor ^^^^^^ @@ -479,7 +479,7 @@ Host Controller Driver (HCD) - Move echi/ohci files to portable/ - Rename hcd_lpc18_43 to hcd_transdimension - Sub hcd API with hcd_ehci_init(), hcd_ehci_register_addr() - + - Update NXP transdimention hcd_init() to reset controller to host mode - Ported hcd to rt10xx @@ -529,13 +529,13 @@ Device Controller Driver - ESP32-S2: - Add bus suspend and wakeup support - + - SAMD21: - Fix (walkaround) samd21 setup_packet overflow by USB DMA - + - STM32 Synopsys: - Rework USB FIFO allocation scheme and allow RX FIFO size reduction - + - Sony CXD56 - Update Update Spresense SDK to 2.0.2 - Fix dcd issues with setup packets @@ -554,17 +554,17 @@ USB Device - CDC - Allow to transmit data, even if the host does not support control line states i.e set DTR - + - HID - change default CFG_TUD_HID_EP_BUFSIZE from 16 to 64 - + - MIDI - Fix midi sysex sending bug - + - MSC - Invoke only scsi complete callback after status transaction is complete. - Fix scsi_mode_sense6_t padding, which cause IAR compiler internal error. - + - USBTMC - Change interrupt endpoint example size to 8 instead of 2 for better compatibility with mcu @@ -614,20 +614,20 @@ Device Controller Driver - Fix FIFO flush during stall - Implement dcd_edpt_close() API - Support F105, F107 - + - Enhance STM32 fsdev - Improve dcd fifo allocation - Fix ISTR race condition - Support remap USB IRQ on supported MCUs - Implement dcd_edpt_close() API - + - Enhance NUC 505: enhance set configure behavior - Enhance SAMD - Fix race condition with setup packet - Add SAMD11 option `OPT_MCU_SAMD11` - Add SAME5x option `OPT_MCU_SAME5X` - + - Fix SAMG control data toggle and stall race condition - Enhance nRF @@ -659,7 +659,7 @@ USB Device - `usbd_driver_open()` add max length argument, and return length of interface (0 for not supported). Return value is used for finding appropriate driver - Add application implemented class driver via `usbd_app_driver_get_cb()` - IAD is handled to assign driver id - + - Added `tud_descriptor_device_qualifier_cb()` callback - Optimize `tu_fifo` bulk write/read transfer - Forward non-std control request to class driver @@ -675,12 +675,12 @@ USB Device - Send zero length packet for end of data when needed - Add `tud_cdc_tx_complete_cb()` callback - Change tud_cdc_n_write_flush() return number of bytes forced to transfer, and flush when writing enough data to fifo - + - MIDI: - Add packet interface - Add multiple jack descriptors - Fix MIDI driver for sysex - + - DFU Runtime: fix response to SET_INTERFACE and DFU_GETSTATUS request - Rename some configure macro to make it clear that those are used directly for endpoint transfer @@ -688,7 +688,7 @@ USB Device - CFG_TUD_CDC_EPSIZE to CFG_TUD_CDC_EP_BUFSIZE - CFG_TUD_MSC_BUFSIZE to CFG_TUD_MSC_EP_BUFSIZE - CFG_TUD_MIDI_EPSIZE to CFG_TUD_MIDI_EP_BUFSIZE - + - HID: - Fix gamepad template descriptor - Add multiple HID interface API @@ -700,7 +700,7 @@ USB Host - Rework USB host stack (still work in progress) - Fix compile error with pipehandle - Rework usbh control and enumeration as non-blocking - + - Improve Hub, MSC, HID host driver Examples @@ -713,7 +713,7 @@ Examples - Enhance `net_lwip_webserver` example - Add multiple configuration: RNDIS for Windows, CDC-ECM for macOS (Linux will work with both) - Update lwip to STABLE-2_1_2_RELEASE for net_lwip_webserver - + - Added new Audio example: audio_test uac2_headsest New Boards diff --git a/docs/info/contributors.rst b/docs/info/contributors.rst index b3748ccb5..02608919f 120000 --- a/docs/info/contributors.rst +++ b/docs/info/contributors.rst @@ -1 +1 @@ -../../CONTRIBUTORS.rst \ No newline at end of file +../../CONTRIBUTORS.rst diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst index e328757ba..ef4a6ba61 100644 --- a/docs/reference/getting_started.rst +++ b/docs/reference/getting_started.rst @@ -44,18 +44,18 @@ For your convenience, TinyUSB contains a handful of examples for both host and d $ git clone https://github.com/hathach/tinyusb tinyusb $ cd tinyusb -Some TinyUSB examples also requires external submodule libraries in ``/lib`` such as FreeRTOS, Lightweight IP to build. Run following command to fetch them +Some TinyUSB examples also requires external submodule libraries in ``/lib`` such as FreeRTOS, Lightweight IP to build. Run following command to fetch them .. code-block:: $ git submodule update --init lib -Some ports will also require a port-specific SDK (e.g. RP2040) or binary (e.g. Sony Spresense) to build examples. They are out of scope for tinyusb, you should download/install it first according to its manufacturer guide. +Some ports will also require a port-specific SDK (e.g. RP2040) or binary (e.g. Sony Spresense) to build examples. They are out of scope for tinyusb, you should download/install it first according to its manufacturer guide. Build ^^^^^ -To build example, first change directory to an example folder. +To build example, first change directory to an example folder. .. code-block:: @@ -118,7 +118,7 @@ To compile for debugging add ``DEBUG=1``\ , for example Log ~~~ -Should you have an issue running example and/or submitting an bug report. You could enable TinyUSB built-in debug logging with optional ``LOG=``. LOG=1 will only print out error message, LOG=2 print more information with on-going events. LOG=3 or higher is not used yet. +Should you have an issue running example and/or submitting an bug report. You could enable TinyUSB built-in debug logging with optional ``LOG=``. LOG=1 will only print out error message, LOG=2 print more information with on-going events. LOG=3 or higher is not used yet. .. code-block:: @@ -127,7 +127,7 @@ Should you have an issue running example and/or submitting an bug report. You co Logger ~~~~~~ -By default log message is printed via on-board UART which is slow and take lots of CPU time comparing to USB speed. If your board support on-board/external debugger, it would be more efficient to use it for logging. There are 2 protocols: +By default log message is printed via on-board UART which is slow and take lots of CPU time comparing to USB speed. If your board support on-board/external debugger, it would be more efficient to use it for logging. There are 2 protocols: * `LOGGER=rtt`: use `Segger RTT protocol `_ @@ -178,12 +178,12 @@ IAR Project Connection files are provided to import TinyUSB stack into your proj * Take example of STM32F0: - + - You need `stm32l0xx.h`, `startup_stm32f0xx.s`, `system_stm32f0xx.c`. - `STM32L0xx_HAL_Driver` is only needed to run examples, TinyUSB stack itself doesn't rely on MCU's SDKs. -* Open `Tools -> Configure Custom Argument Variables` (Switch to `Global` tab if you want to do it for all your projects) +* Open `Tools -> Configure Custom Argument Variables` (Switch to `Global` tab if you want to do it for all your projects) Click `New Group ...`, name it to `TUSB`, Click `Add Variable ...`, name it to `TUSB_DIR`, change it's value to the path of your TinyUSB stack, for example `C:\\tinyusb` diff --git a/examples/device/audio_4_channel_mic/skip.txt b/examples/device/audio_4_channel_mic/skip.txt index ae9b57f1f..1ee86a485 100644 --- a/examples/device/audio_4_channel_mic/skip.txt +++ b/examples/device/audio_4_channel_mic/skip.txt @@ -1,3 +1,3 @@ mcu:SAMD11 mcu:SAME5X -mcu:SAMG \ No newline at end of file +mcu:SAMG diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c index a6af5fd19..26d8c48c5 100644 --- a/examples/device/audio_4_channel_mic/src/main.c +++ b/examples/device/audio_4_channel_mic/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Reinhard Panhuber diff --git a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py index 9ab15135d..8312b4e28 100644 --- a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py +++ b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py @@ -31,4 +31,3 @@ if __name__ == '__main__': plt.ylabel('Amplitude') plt.title('MicNode 4 Channel') plt.show() - \ No newline at end of file diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c index 8929f3057..8bf9eebc4 100644 --- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c +++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/audio_test/CMakeLists.txt b/examples/device/audio_test/CMakeLists.txt index cb321f9a8..f6e10e2ea 100644 --- a/examples/device/audio_test/CMakeLists.txt +++ b/examples/device/audio_test/CMakeLists.txt @@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/audio_test/skip.txt b/examples/device/audio_test/skip.txt index ae9b57f1f..1ee86a485 100644 --- a/examples/device/audio_test/skip.txt +++ b/examples/device/audio_test/skip.txt @@ -1,3 +1,3 @@ mcu:SAMD11 mcu:SAME5X -mcu:SAMG \ No newline at end of file +mcu:SAMG diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c index 56961e427..f9cc63cdd 100644 --- a/examples/device/audio_test/src/main.c +++ b/examples/device/audio_test/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Reinhard Panhuber diff --git a/examples/device/audio_test/src/plot_audio_samples.py b/examples/device/audio_test/src/plot_audio_samples.py index 2303df3d0..1504684a6 100644 --- a/examples/device/audio_test/src/plot_audio_samples.py +++ b/examples/device/audio_test/src/plot_audio_samples.py @@ -32,7 +32,6 @@ if __name__ == '__main__': plt.ylabel('Amplitude') plt.title('MicNode') plt.show() - + samples = np.array(myrecording) np.savetxt('Output.csv', samples, delimiter=",", fmt='%s') - \ No newline at end of file diff --git a/examples/device/audio_test/src/usb_descriptors.c b/examples/device/audio_test/src/usb_descriptors.c index da3e203d7..891e90802 100644 --- a/examples/device/audio_test/src/usb_descriptors.c +++ b/examples/device/audio_test/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/audio_test_multi_rate/CMakeLists.txt b/examples/device/audio_test_multi_rate/CMakeLists.txt index cb321f9a8..f6e10e2ea 100644 --- a/examples/device/audio_test_multi_rate/CMakeLists.txt +++ b/examples/device/audio_test_multi_rate/CMakeLists.txt @@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/audio_test_multi_rate/skip.txt b/examples/device/audio_test_multi_rate/skip.txt index ae9b57f1f..1ee86a485 100644 --- a/examples/device/audio_test_multi_rate/skip.txt +++ b/examples/device/audio_test_multi_rate/skip.txt @@ -1,3 +1,3 @@ mcu:SAMD11 mcu:SAME5X -mcu:SAMG \ No newline at end of file +mcu:SAMG diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c index 0e11a509b..4dd53dd34 100644 --- a/examples/device/audio_test_multi_rate/src/main.c +++ b/examples/device/audio_test_multi_rate/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Reinhard Panhuber @@ -165,7 +165,7 @@ bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_reque (void)rhport; //uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex)); uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue)); - + // Clear buffer when streaming format is changed if(alt != 0) { @@ -257,7 +257,7 @@ bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * return false; } } - + // Clock Source unit if ( entityID == UAC2_ENTITY_CLOCK ) { @@ -279,7 +279,7 @@ bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * return false; } } - + return false; // Yet not implemented } @@ -491,7 +491,7 @@ bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uin pData_32[cnt] = (uint32_t)startVal++ << 16U; } } - + return true; } diff --git a/examples/device/audio_test_multi_rate/src/plot_audio_samples.py b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py index 4a5f15a9c..c92e49957 100644 --- a/examples/device/audio_test_multi_rate/src/plot_audio_samples.py +++ b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py @@ -32,7 +32,6 @@ if __name__ == '__main__': plt.ylabel('Amplitude') plt.title('MicNode') plt.show() - + samples = np.array(myrecording) np.savetxt('Output.csv', samples, delimiter=",", fmt='%s') - \ No newline at end of file diff --git a/examples/device/audio_test_multi_rate/src/tusb_config.h b/examples/device/audio_test_multi_rate/src/tusb_config.h index d8b6511d6..1c8288bce 100644 --- a/examples/device/audio_test_multi_rate/src/tusb_config.h +++ b/examples/device/audio_test_multi_rate/src/tusb_config.h @@ -111,7 +111,7 @@ extern "C" { // How many formats are used, need to adjust USB descriptor if changed #define CFG_TUD_AUDIO_FUNC_1_N_FORMATS 2 - + // 16bit in 16bit slots #define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX 2 #define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX 16 diff --git a/examples/device/audio_test_multi_rate/src/usb_descriptors.c b/examples/device/audio_test_multi_rate/src/usb_descriptors.c index 92e791a72..276bf8aa0 100644 --- a/examples/device/audio_test_multi_rate/src/usb_descriptors.c +++ b/examples/device/audio_test_multi_rate/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/audio_test_multi_rate/src/usb_descriptors.h b/examples/device/audio_test_multi_rate/src/usb_descriptors.h index 77e2fe6c1..8d8a03e49 100644 --- a/examples/device/audio_test_multi_rate/src/usb_descriptors.h +++ b/examples/device/audio_test_multi_rate/src/usb_descriptors.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2022 HiFiPhile @@ -99,4 +99,4 @@ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000) -#endif \ No newline at end of file +#endif diff --git a/examples/device/board_test/src/CMakeLists.txt b/examples/device/board_test/src/CMakeLists.txt index e4e1f4e9a..37625f441 100644 --- a/examples/device/board_test/src/CMakeLists.txt +++ b/examples/device/board_test/src/CMakeLists.txt @@ -2,7 +2,7 @@ idf_component_register(SRCS "main.c" INCLUDE_DIRS "." REQUIRES freertos soc) - + file(TO_NATIVE_PATH "${TOP}/hw/bsp/${FAMILY}/boards/${BOARD}/board.cmake" board_cmake) if(EXISTS ${board_cmake}) diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c index 0289ca15f..e8e393717 100644 --- a/examples/device/board_test/src/main.c +++ b/examples/device/board_test/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/cdc_dual_ports/CMakeLists.txt b/examples/device/cdc_dual_ports/CMakeLists.txt index abc4d91da..acaa54198 100644 --- a/examples/device/cdc_dual_ports/CMakeLists.txt +++ b/examples/device/cdc_dual_ports/CMakeLists.txt @@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c index 0264f0566..c0296191b 100644 --- a/examples/device/cdc_dual_ports/src/main.c +++ b/examples/device/cdc_dual_ports/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c index 4eb8c7c27..8be404cc9 100644 --- a/examples/device/cdc_dual_ports/src/usb_descriptors.c +++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt index fa6e83b7e..8e4db9d29 100644 --- a/examples/device/cdc_msc/CMakeLists.txt +++ b/examples/device/cdc_msc/CMakeLists.txt @@ -26,4 +26,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/cdc_msc/skip.txt b/examples/device/cdc_msc/skip.txt index d844feae8..eadb6e74a 100644 --- a/examples/device/cdc_msc/skip.txt +++ b/examples/device/cdc_msc/skip.txt @@ -1 +1 @@ -mcu:SAMD11 \ No newline at end of file +mcu:SAMD11 diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c index c83299e59..207dd728c 100644 --- a/examples/device/cdc_msc/src/main.c +++ b/examples/device/cdc_msc/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c index e67e381ce..f8f37a577 100644 --- a/examples/device/cdc_msc/src/msc_disk.c +++ b/examples/device/cdc_msc/src/msc_disk.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c index 6b59ed50f..44c849277 100644 --- a/examples/device/cdc_msc/src/usb_descriptors.c +++ b/examples/device/cdc_msc/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index cfb14aa2b..0e8a24d02 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c index a895f4738..707c8d578 100644 --- a/examples/device/cdc_msc_freertos/src/msc_disk.c +++ b/examples/device/cdc_msc_freertos/src/msc_disk.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c index 30a712275..822442724 100644 --- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c +++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/dfu_runtime/CMakeLists.txt b/examples/device/dfu_runtime/CMakeLists.txt index abc4d91da..acaa54198 100644 --- a/examples/device/dfu_runtime/CMakeLists.txt +++ b/examples/device/dfu_runtime/CMakeLists.txt @@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c index bd9a91c27..4ec2fa31d 100644 --- a/examples/device/dfu_runtime/src/main.c +++ b/examples/device/dfu_runtime/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/dynamic_configuration/CMakeLists.txt b/examples/device/dynamic_configuration/CMakeLists.txt index fa6e83b7e..8e4db9d29 100644 --- a/examples/device/dynamic_configuration/CMakeLists.txt +++ b/examples/device/dynamic_configuration/CMakeLists.txt @@ -26,4 +26,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/dynamic_configuration/skip.txt b/examples/device/dynamic_configuration/skip.txt index d844feae8..eadb6e74a 100644 --- a/examples/device/dynamic_configuration/skip.txt +++ b/examples/device/dynamic_configuration/skip.txt @@ -1 +1 @@ -mcu:SAMD11 \ No newline at end of file +mcu:SAMD11 diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c index 33a603343..90794e979 100644 --- a/examples/device/dynamic_configuration/src/main.c +++ b/examples/device/dynamic_configuration/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/dynamic_configuration/src/msc_disk.c b/examples/device/dynamic_configuration/src/msc_disk.c index e8cb03fdd..27856a1a4 100644 --- a/examples/device/dynamic_configuration/src/msc_disk.c +++ b/examples/device/dynamic_configuration/src/msc_disk.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c index 092229b99..0590bd679 100644 --- a/examples/device/dynamic_configuration/src/usb_descriptors.c +++ b/examples/device/dynamic_configuration/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/hid_boot_interface/CMakeLists.txt b/examples/device/hid_boot_interface/CMakeLists.txt index abc4d91da..acaa54198 100644 --- a/examples/device/hid_boot_interface/CMakeLists.txt +++ b/examples/device/hid_boot_interface/CMakeLists.txt @@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/hid_boot_interface/Makefile b/examples/device/hid_boot_interface/Makefile index d58a539e8..b3f2cc588 100644 --- a/examples/device/hid_boot_interface/Makefile +++ b/examples/device/hid_boot_interface/Makefile @@ -8,7 +8,7 @@ INC += \ EXAMPLE_SOURCE = \ src/main.c \ src/usb_descriptors.c - + SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) include ../../rules.mk diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c index b13428041..1a155996a 100644 --- a/examples/device/hid_boot_interface/src/main.c +++ b/examples/device/hid_boot_interface/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/hid_boot_interface/src/usb_descriptors.c b/examples/device/hid_boot_interface/src/usb_descriptors.c index a0d7e9f15..10345ab41 100644 --- a/examples/device/hid_boot_interface/src/usb_descriptors.c +++ b/examples/device/hid_boot_interface/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/hid_boot_interface/src/usb_descriptors.h b/examples/device/hid_boot_interface/src/usb_descriptors.h index 57cf0e2c0..6fee9e223 100644 --- a/examples/device/hid_boot_interface/src/usb_descriptors.h +++ b/examples/device/hid_boot_interface/src/usb_descriptors.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/hid_composite/CMakeLists.txt b/examples/device/hid_composite/CMakeLists.txt index abc4d91da..acaa54198 100644 --- a/examples/device/hid_composite/CMakeLists.txt +++ b/examples/device/hid_composite/CMakeLists.txt @@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c index 05315f266..4edb045c2 100644 --- a/examples/device/hid_composite/src/main.c +++ b/examples/device/hid_composite/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/hid_composite/src/usb_descriptors.c b/examples/device/hid_composite/src/usb_descriptors.c index 2988baee2..347bbf29a 100644 --- a/examples/device/hid_composite/src/usb_descriptors.c +++ b/examples/device/hid_composite/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/hid_composite/src/usb_descriptors.h b/examples/device/hid_composite/src/usb_descriptors.h index ca8925ad9..e733d31dd 100644 --- a/examples/device/hid_composite/src/usb_descriptors.h +++ b/examples/device/hid_composite/src/usb_descriptors.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c index 7c9619c4b..ca02af100 100644 --- a/examples/device/hid_composite_freertos/src/main.c +++ b/examples/device/hid_composite_freertos/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/hid_composite_freertos/src/usb_descriptors.c b/examples/device/hid_composite_freertos/src/usb_descriptors.c index 4df12d3db..30f327d5e 100644 --- a/examples/device/hid_composite_freertos/src/usb_descriptors.c +++ b/examples/device/hid_composite_freertos/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/hid_composite_freertos/src/usb_descriptors.h b/examples/device/hid_composite_freertos/src/usb_descriptors.h index ca8925ad9..e733d31dd 100644 --- a/examples/device/hid_composite_freertos/src/usb_descriptors.h +++ b/examples/device/hid_composite_freertos/src/usb_descriptors.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/hid_generic_inout/CMakeLists.txt b/examples/device/hid_generic_inout/CMakeLists.txt index abc4d91da..acaa54198 100644 --- a/examples/device/hid_generic_inout/CMakeLists.txt +++ b/examples/device/hid_generic_inout/CMakeLists.txt @@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/hid_generic_inout/hid_test.js b/examples/device/hid_generic_inout/hid_test.js index daa958fd5..16bc723e2 100644 --- a/examples/device/hid_generic_inout/hid_test.js +++ b/examples/device/hid_generic_inout/hid_test.js @@ -48,7 +48,7 @@ if( deviceInfo ) { function anySupportedBoard(d) { - + for (var key in boards) { if (boards.hasOwnProperty(key)) { if (isDevice(boards[key],d)) { @@ -65,4 +65,3 @@ function isDevice(board,d){ // product id 0xff is matches all return d.vendorId==board[0] && (d.productId==board[1] || board[1] == 0xFFFF); } - diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c index 5b7daf118..6649b49b5 100644 --- a/examples/device/hid_generic_inout/src/main.c +++ b/examples/device/hid_generic_inout/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/hid_generic_inout/src/usb_descriptors.c b/examples/device/hid_generic_inout/src/usb_descriptors.c index cd4838407..8377a0f47 100644 --- a/examples/device/hid_generic_inout/src/usb_descriptors.c +++ b/examples/device/hid_generic_inout/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/hid_multiple_interface/CMakeLists.txt b/examples/device/hid_multiple_interface/CMakeLists.txt index abc4d91da..acaa54198 100644 --- a/examples/device/hid_multiple_interface/CMakeLists.txt +++ b/examples/device/hid_multiple_interface/CMakeLists.txt @@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/midi_test/CMakeLists.txt b/examples/device/midi_test/CMakeLists.txt index abc4d91da..acaa54198 100644 --- a/examples/device/midi_test/CMakeLists.txt +++ b/examples/device/midi_test/CMakeLists.txt @@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c index 3310348bd..66fa72063 100644 --- a/examples/device/midi_test/src/main.c +++ b/examples/device/midi_test/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c index c84a873b1..4845dcf57 100644 --- a/examples/device/midi_test/src/usb_descriptors.c +++ b/examples/device/midi_test/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/msc_dual_lun/CMakeLists.txt b/examples/device/msc_dual_lun/CMakeLists.txt index 9e834ae21..9188ab06c 100644 --- a/examples/device/msc_dual_lun/CMakeLists.txt +++ b/examples/device/msc_dual_lun/CMakeLists.txt @@ -26,4 +26,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/msc_dual_lun/skip.txt b/examples/device/msc_dual_lun/skip.txt index 3549c702a..47e561cf0 100644 --- a/examples/device/msc_dual_lun/skip.txt +++ b/examples/device/msc_dual_lun/skip.txt @@ -1,2 +1,2 @@ mcu:SAMD11 -mcu:MKL25ZXX \ No newline at end of file +mcu:MKL25ZXX diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c index 96790d20c..0a7284939 100644 --- a/examples/device/msc_dual_lun/src/main.c +++ b/examples/device/msc_dual_lun/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c index 2b773b43b..b1047acdb 100644 --- a/examples/device/msc_dual_lun/src/msc_disk_dual.c +++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c index d8dbb5ce3..2de81111c 100644 --- a/examples/device/msc_dual_lun/src/usb_descriptors.c +++ b/examples/device/msc_dual_lun/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt index 9fe1a325e..5f1e37931 100644 --- a/examples/device/net_lwip_webserver/CMakeLists.txt +++ b/examples/device/net_lwip_webserver/CMakeLists.txt @@ -80,4 +80,4 @@ if (EXISTS ${TOP}/lib/lwip/src) # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. family_configure_device_example(${PROJECT}) -endif() \ No newline at end of file +endif() diff --git a/examples/device/net_lwip_webserver/skip.txt b/examples/device/net_lwip_webserver/skip.txt index 68761b058..b0e5235ac 100644 --- a/examples/device/net_lwip_webserver/skip.txt +++ b/examples/device/net_lwip_webserver/skip.txt @@ -7,4 +7,4 @@ mcu:STM32L0 mcu:MKL25ZXX family:broadcom_64bit family:broadcom_32bit -board:curiosity_nano \ No newline at end of file +board:curiosity_nano diff --git a/examples/device/net_lwip_webserver/src/arch/cc.h b/examples/device/net_lwip_webserver/src/arch/cc.h index 56a0cacf7..9f30b91cb 100644 --- a/examples/device/net_lwip_webserver/src/arch/cc.h +++ b/examples/device/net_lwip_webserver/src/arch/cc.h @@ -1,8 +1,8 @@ /* * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, @@ -11,21 +11,21 @@ * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. + * derived from this software without specific prior written permission. * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY * OF SUCH DAMAGE. * * This file is part of the lwIP TCP/IP stack. - * + * * Author: Adam Dunkels * */ @@ -42,7 +42,7 @@ typedef int sys_prot_t; #if defined (__ICCARM__) #define PACK_STRUCT_BEGIN -#define PACK_STRUCT_STRUCT +#define PACK_STRUCT_STRUCT #define PACK_STRUCT_END #define PACK_STRUCT_FIELD(x) x #define PACK_STRUCT_USE_INCLUDES @@ -50,7 +50,7 @@ typedef int sys_prot_t; #elif defined (__CC_ARM) #define PACK_STRUCT_BEGIN __packed -#define PACK_STRUCT_STRUCT +#define PACK_STRUCT_STRUCT #define PACK_STRUCT_END #define PACK_STRUCT_FIELD(x) x diff --git a/examples/device/net_lwip_webserver/src/lwipopts.h b/examples/device/net_lwip_webserver/src/lwipopts.h index a215017c7..336c9243d 100644 --- a/examples/device/net_lwip_webserver/src/lwipopts.h +++ b/examples/device/net_lwip_webserver/src/lwipopts.h @@ -1,8 +1,8 @@ /* * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, @@ -11,21 +11,21 @@ * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. + * derived from this software without specific prior written permission. * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY * OF SUCH DAMAGE. * * This file is part of the lwIP TCP/IP stack. - * + * * Author: Simon Goldschmidt * */ diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c index 33b4d38b6..88081ffe2 100644 --- a/examples/device/net_lwip_webserver/src/main.c +++ b/examples/device/net_lwip_webserver/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Peter Lawrence @@ -39,7 +39,7 @@ and likely their manufacturer has not tested such functionality. Some code work The smartphone may only have an ECM driver, but refuse to automatically pick ECM (unlike the OSes above); try modifying ./examples/devices/net_lwip_webserver/usb_descriptors.c so that CONFIG_ID_ECM is default. -The smartphone may be artificially picky about which Ethernet MAC address to recognize; if this happens, +The smartphone may be artificially picky about which Ethernet MAC address to recognize; if this happens, try changing the first byte of tud_network_mac_address[] below from 0x02 to 0x00 (clearing bit 1). */ @@ -170,7 +170,7 @@ bool dns_query_proc(const char *name, ip4_addr_t *addr) bool tud_network_recv_cb(const uint8_t *src, uint16_t size) { - /* this shouldn't happen, but if we get another packet before + /* this shouldn't happen, but if we get another packet before parsing the previous, we must signal our inability to accept it */ if (received_frame) return false; diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c index bee51790a..3c0ed3db7 100644 --- a/examples/device/net_lwip_webserver/src/usb_descriptors.c +++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -77,7 +77,7 @@ tusb_desc_device_t const desc_device = .bDeviceClass = TUSB_CLASS_MISC, .bDeviceSubClass = MISC_SUBCLASS_COMMON, .bDeviceProtocol = MISC_PROTOCOL_IAD, - + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, .idVendor = 0xCafe, diff --git a/examples/device/uac2_headset/CMakeLists.txt b/examples/device/uac2_headset/CMakeLists.txt index abc4d91da..acaa54198 100644 --- a/examples/device/uac2_headset/CMakeLists.txt +++ b/examples/device/uac2_headset/CMakeLists.txt @@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c index 01707d51b..bafd40d34 100644 --- a/examples/device/uac2_headset/src/main.c +++ b/examples/device/uac2_headset/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Jerzy Kasenberg @@ -176,7 +176,7 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t rangef.subrange[i].bRes = 0; TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes); } - + return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &rangef, sizeof(rangef)); } } diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c index 07c86b903..0a0b4c602 100644 --- a/examples/device/uac2_headset/src/usb_descriptors.c +++ b/examples/device/uac2_headset/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Ha Thach (tinyusb.org) diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h index 342b4fac1..5525c916a 100644 --- a/examples/device/uac2_headset/src/usb_descriptors.h +++ b/examples/device/uac2_headset/src/usb_descriptors.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Jerzy Kasenbreg diff --git a/examples/device/usbtmc/CMakeLists.txt b/examples/device/usbtmc/CMakeLists.txt index c49603c26..b4678dc5e 100644 --- a/examples/device/usbtmc/CMakeLists.txt +++ b/examples/device/usbtmc/CMakeLists.txt @@ -26,4 +26,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c index 6945d8743..da7f0418a 100644 --- a/examples/device/usbtmc/src/main.c +++ b/examples/device/usbtmc/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/usbtmc/visaQuery.py b/examples/device/usbtmc/visaQuery.py index c4e5ad2b9..ca65daf97 100644 --- a/examples/device/usbtmc/visaQuery.py +++ b/examples/device/usbtmc/visaQuery.py @@ -36,8 +36,8 @@ def test_trig(): time.sleep(0.3) # SRQ may have some delay assert (inst.read_stb() & 0x40), "SRQ not set after 0.3 seconds" assert (inst.read_stb() == 0) - - + + def test_mav(): inst.write("delay 50") inst.read_stb() # clear STB @@ -45,15 +45,15 @@ def test_mav(): inst.write("123") time.sleep(0.3) assert (inst.read_stb() & 0x10), "MAV not set after 0.5 seconds" - + rsp = inst.read() assert(rsp == "123\r\n") - - + + def test_srq(): assert (inst.read_stb() == 0) inst.write("123") - + #inst.enable_event(pyvisa.constants.VI_EVENT_SERVICE_REQ, pyvisa.constants.VI_QUEUE) #waitrsp = inst.wait_on_event(pyvisa.constants.VI_EVENT_SERVICE_REQ, 5000) #inst.discard_events(pyvisa.constants.VI_EVENT_SERVICE_REQ, pyvisa.constants.VI_QUEUE) @@ -64,7 +64,7 @@ def test_srq(): assert (stb == 0x50),msg assert (inst.read_stb() == 0x10), "SRQ set at second read!" - + rsp = inst.read() assert(rsp == "123\r\n") @@ -110,7 +110,7 @@ def test_abort_in(): inst.timeout = 800 y = inst.read() assert(y == "xxx\r\n") - + def test_indicate(): # perform indicator pulse usb_iface = inst.get_visa_attribute(pyvisa.constants.VI_ATTR_USB_INTFC_NUM) @@ -120,8 +120,8 @@ def test_indicate(): assert(retv == b'\x01') else: assert((retv[1] == pyvisa.constants.StatusCode(0)) and (retv[0] == b'\x01')), f"indicator pulse failed: retv={retv}" - - + + def test_multi_read(): old_chunk_size = inst.chunk_size longstr = "0123456789abcdefghijklmnopqrstuvwxyz" * 10 @@ -133,7 +133,7 @@ def test_multi_read(): y = inst.read() assert (x + "\r\n" == y) #inst.chunk_size = old_chunk_size - + def test_stall_ep0(): usb_iface = inst.get_visa_attribute(pyvisa.constants.VI_ATTR_USB_INTFC_NUM) inst.read_stb() @@ -143,7 +143,7 @@ def test_stall_ep0(): assert(False) except pyvisa.VisaIOError: pass - + assert (inst.read_stb() == 0) @@ -153,7 +153,7 @@ print(reslist) if (len(reslist) == 0): sys.exit() - + inst = rm.open_resource(reslist[0]); inst.timeout = 3000 diff --git a/examples/device/video_capture/CMakeLists.txt b/examples/device/video_capture/CMakeLists.txt index b92a2b804..f1ef247e1 100644 --- a/examples/device/video_capture/CMakeLists.txt +++ b/examples/device/video_capture/CMakeLists.txt @@ -31,4 +31,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index 3ceebe821..08db1b00f 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c index 0cf772010..af18d15d1 100644 --- a/examples/device/video_capture/src/usb_descriptors.c +++ b/examples/device/video_capture/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h index f1ed3c8e9..93f148a82 100644 --- a/examples/device/video_capture/src/usb_descriptors.h +++ b/examples/device/video_capture/src/usb_descriptors.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Jerzy Kasenbreg diff --git a/examples/device/webusb_serial/CMakeLists.txt b/examples/device/webusb_serial/CMakeLists.txt index abc4d91da..acaa54198 100644 --- a/examples/device/webusb_serial/CMakeLists.txt +++ b/examples/device/webusb_serial/CMakeLists.txt @@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c index 604d30a83..24456f9f3 100644 --- a/examples/device/webusb_serial/src/main.c +++ b/examples/device/webusb_serial/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c index 99f5caaf9..b2593001c 100644 --- a/examples/device/webusb_serial/src/usb_descriptors.c +++ b/examples/device/webusb_serial/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/device/webusb_serial/src/usb_descriptors.h b/examples/device/webusb_serial/src/usb_descriptors.h index 19f1ff3f3..a1c4a2cf1 100644 --- a/examples/device/webusb_serial/src/usb_descriptors.h +++ b/examples/device/webusb_serial/src/usb_descriptors.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c index bd7870274..817c63c70 100644 --- a/examples/dual/host_hid_to_device_cdc/src/main.c +++ b/examples/dual/host_hid_to_device_cdc/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c b/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c index 6b0a89127..63b6bc603 100644 --- a/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c +++ b/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c index 51cab2de0..bb7fa850e 100644 --- a/examples/host/bare_api/src/main.c +++ b/examples/host/bare_api/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c index b34810252..23312296f 100644 --- a/examples/host/cdc_msc_hid/src/main.c +++ b/examples/host/cdc_msc_hid/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/host/cdc_msc_hid/src/msc_app.c b/examples/host/cdc_msc_hid/src/msc_app.c index 797d55f8a..e9c9676b8 100644 --- a/examples/host/cdc_msc_hid/src/msc_app.c +++ b/examples/host/cdc_msc_hid/src/msc_app.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -68,4 +68,3 @@ void tuh_msc_umount_cb(uint8_t dev_addr) (void) dev_addr; printf("A MassStorage device is unmounted\r\n"); } - diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c index 299a3ff10..3380e9246 100644 --- a/examples/host/hid_controller/src/main.c +++ b/examples/host/hid_controller/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c index ab2cfd498..40c88a7d3 100644 --- a/examples/host/msc_file_explorer/src/main.c +++ b/examples/host/msc_file_explorer/src/main.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c index eef28fe12..003e2865b 100644 --- a/examples/host/msc_file_explorer/src/msc_app.c +++ b/examples/host/msc_file_explorer/src/msc_app.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/examples/rules.mk b/examples/rules.mk index f8e4001ec..56ad89fd0 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -283,4 +283,4 @@ copy-artifact: $(BIN) # Print out the value of a make variable. # https://stackoverflow.com/questions/16467718/how-to-print-out-a-variable-in-makefile print-%: - @echo $* = $($*) \ No newline at end of file + @echo $* = $($*) diff --git a/hw/bsp/ansi_escape.h b/hw/bsp/ansi_escape.h index 6e62ee20a..15af2f3ab 100644 --- a/hw/bsp/ansi_escape.h +++ b/hw/bsp/ansi_escape.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/board.c b/hw/bsp/board.c index 14858c2b6..e715bdf2e 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2018, hathach (tinyusb.org) diff --git a/hw/bsp/board.h b/hw/bsp/board.h index 0a10294d0..036556731 100644 --- a/hw/bsp/board.h +++ b/hw/bsp/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h index 1d3565d5c..84a106346 100644 --- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h +++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk index 52e9e45c4..77811d18d 100644 --- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk +++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk @@ -2,4 +2,4 @@ CFLAGS += -mcpu=arm1176jzf-s \ -DBCM_VERSION=2835 \ -DCFG_TUSB_MCU=OPT_MCU_BCM2835 -SUFFIX = +SUFFIX = diff --git a/hw/bsp/broadcom_32bit/family.c b/hw/bsp/broadcom_32bit/family.c index f7a11fb49..42ad4b666 100644 --- a/hw/bsp/broadcom_32bit/family.c +++ b/hw/bsp/broadcom_32bit/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h index 1d3565d5c..84a106346 100644 --- a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h +++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h index 1d3565d5c..84a106346 100644 --- a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h +++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/broadcom_64bit/family.c b/hw/bsp/broadcom_64bit/family.c index f7a11fb49..42ad4b666 100644 --- a/hw/bsp/broadcom_64bit/family.c +++ b/hw/bsp/broadcom_64bit/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c index 3b6b03904..f812c922f 100644 --- a/hw/bsp/brtmm90x/family.c +++ b/hw/bsp/brtmm90x/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright 2021 Bridgetek Pte Ltd @@ -70,7 +70,7 @@ void board_init(void) board_uart_write(WELCOME_MSG, sizeof(WELCOME_MSG)); #ifdef BOARD_GPIO_LED - gpio_function(BOARD_GPIO_LED, pad_func_0); + gpio_function(BOARD_GPIO_LED, pad_func_0); gpio_idrive(BOARD_GPIO_LED, pad_drive_12mA); gpio_dir(BOARD_GPIO_LED, pad_dir_output); #endif @@ -233,7 +233,7 @@ int board_uart_write(void const *buf, int len) uint32_t board_millis(void) { uint32_t safe_ms; - + CRITICAL_SECTION_BEGIN safe_ms = timer_ms; CRITICAL_SECTION_END @@ -254,4 +254,3 @@ void chip_reboot(void) dbg_memory_copy(0xfe, 0, 0, 255); #endif } - diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk index 0ddf47a3a..6df0bfdfe 100644 --- a/hw/bsp/brtmm90x/family.mk +++ b/hw/bsp/brtmm90x/family.mk @@ -5,7 +5,7 @@ SKIP_NANOLIB = 1 # Set to use FT90X prebuilt libraries. FT9XX_PREBUILT_LIBS = 0 ifeq ($(FT9XX_PREBUILT_LIBS),1) -# If the FT90X toolchain is installed on Windows systems then the SDK +# If the FT90X toolchain is installed on Windows systems then the SDK # include files and prebuilt libraries are at: %FT90X_TOOLCHAIN%/hardware FT9XX_SDK = $(FT90X_TOOLCHAIN)/hardware INC += "$(FT9XX_SDK)/include" @@ -21,7 +21,7 @@ endif # Add include files which are within the TinyUSB directory structure. INC += \ - $(TOP)/$(BOARD_PATH) + $(TOP)/$(BOARD_PATH) # Add required C Compiler flags for FT90X. CFLAGS += \ @@ -30,7 +30,7 @@ CFLAGS += \ -fvar-tracking-assignments \ -fmessage-length=0 \ -ffunction-sections \ - -DCFG_TUSB_MCU=OPT_MCU_FT90X + -DCFG_TUSB_MCU=OPT_MCU_FT90X # Maximum USB device speed supported by the board CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED @@ -45,7 +45,7 @@ LDFLAGS += $(addprefix -L,$(LDINC)) \ -Wl,-lc # Additional Source files for FT90X. -SRC_C += src/portable/bridgetek/ft9xx/dcd_ft9xx.c +SRC_C += src/portable/bridgetek/ft9xx/dcd_ft9xx.c # Linker library. ifneq ($(FT9XX_PREBUILT_LIBS),1) diff --git a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h b/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h index 0eab34916..7b488096e 100644 --- a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h +++ b/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2023 Ha Thach (tinyusb.org) for Adafruit Industries diff --git a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c b/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c index 45fc9e3aa..db3551ca7 100644 --- a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c +++ b/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c @@ -36,7 +36,7 @@ static unsigned int tx_produce; static volatile unsigned int tx_consume; void USART1_IRQHandler(void) __attribute__((naked)); -void USART1_IRQHandler(void) { +void USART1_IRQHandler(void) { __asm volatile ("call USART1_IRQHandler_impl; mret"); } @@ -57,7 +57,7 @@ __attribute__((used)) void USART1_IRQHandler_impl(void) void uart_write(char c) { unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX; - + NVIC_DisableIRQ(USART1_IRQn); if((tx_consume != tx_produce) || (USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET)) { tx_buf[tx_produce] = c; diff --git a/hw/bsp/ch32v307/ch32v307.ld b/hw/bsp/ch32v307/ch32v307.ld index af7c06615..55bd10cd0 100644 --- a/hw/bsp/ch32v307/ch32v307.ld +++ b/hw/bsp/ch32v307/ch32v307.ld @@ -41,7 +41,7 @@ SECTIONS *(.glue_7t) *(.gnu.linkonce.t.*) . = ALIGN(4); - } >FLASH AT>FLASH + } >FLASH AT>FLASH .fini : { @@ -50,31 +50,31 @@ SECTIONS } >FLASH AT>FLASH PROVIDE( _etext = . ); - PROVIDE( _eitcm = . ); + PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH AT>FLASH - + } >FLASH AT>FLASH + .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH AT>FLASH - + } >FLASH AT>FLASH + .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH AT>FLASH - + } >FLASH AT>FLASH + .ctors : { /* gcc uses crtbegin.o to find the start of @@ -95,8 +95,8 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - } >FLASH AT>FLASH - + } >FLASH AT>FLASH + .dtors : { KEEP (*crtbegin.o(.dtors)) @@ -104,17 +104,17 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - } >FLASH AT>FLASH + } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); - } >RAM AT>FLASH + } >RAM AT>FLASH .dlalign : { - . = ALIGN(4); + . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH @@ -145,7 +145,7 @@ SECTIONS *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) - *(.gnu.linkonce.b.*) + *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); @@ -156,15 +156,12 @@ SECTIONS .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { - PROVIDE( _heap_end = . ); + PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); __freertos_irq_stack_top = .; - } >RAM + } >RAM } - - - diff --git a/hw/bsp/ch32v307/ch32v30x_conf.h b/hw/bsp/ch32v307/ch32v30x_conf.h index 399feaf68..0b86ad390 100644 --- a/hw/bsp/ch32v307/ch32v30x_conf.h +++ b/hw/bsp/ch32v307/ch32v30x_conf.h @@ -6,7 +6,7 @@ * Description : Library configuration file. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * SPDX-License-Identifier: Apache-2.0 -*******************************************************************************/ +*******************************************************************************/ #ifndef __CH32V30x_CONF_H #define __CH32V30x_CONF_H @@ -36,8 +36,3 @@ #endif /* __CH32V30x_CONF_H */ - - - - - diff --git a/hw/bsp/ch32v307/ch32v30x_it.c b/hw/bsp/ch32v307/ch32v30x_it.c index d348dd989..c329c5613 100644 --- a/hw/bsp/ch32v307/ch32v30x_it.c +++ b/hw/bsp/ch32v307/ch32v30x_it.c @@ -45,5 +45,3 @@ __attribute__((used)) void HardFault_Handler_impl(void) { } } - - diff --git a/hw/bsp/ch32v307/ch32v30x_it.h b/hw/bsp/ch32v307/ch32v30x_it.h index 42f285edf..f3977a8be 100644 --- a/hw/bsp/ch32v307/ch32v30x_it.h +++ b/hw/bsp/ch32v307/ch32v30x_it.h @@ -14,5 +14,3 @@ #endif /* __CH32V30x_IT_H */ - - diff --git a/hw/bsp/ch32v307/core_riscv.h b/hw/bsp/ch32v307/core_riscv.h index 2e94ec683..a7ce10a00 100644 --- a/hw/bsp/ch32v307/core_riscv.h +++ b/hw/bsp/ch32v307/core_riscv.h @@ -336,7 +336,7 @@ RV_STATIC_INLINE void NVIC_SystemReset(void) } -/* Core_Exported_Functions */ +/* Core_Exported_Functions */ extern uint32_t __get_FFLAGS(void); extern void __set_FFLAGS(uint32_t value); extern uint32_t __get_FRM(void); @@ -377,8 +377,3 @@ extern uint32_t __get_SP(void); #endif - - - - - diff --git a/hw/bsp/ch32v307/system_ch32v30x.c b/hw/bsp/ch32v307/system_ch32v30x.c index 12b18d7b8..23f783df4 100644 --- a/hw/bsp/ch32v307/system_ch32v30x.c +++ b/hw/bsp/ch32v307/system_ch32v30x.c @@ -8,17 +8,17 @@ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * SPDX-License-Identifier: Apache-2.0 *********************************************************************************/ -#include "ch32v30x.h" +#include "ch32v30x.h" -/* -* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after * reset the HSI is used as SYSCLK source). -* If none of the define below is enabled, the HSI is used as System clock source. +* If none of the define below is enabled, the HSI is used as System clock source. */ // #define SYSCLK_FREQ_HSE HSE_VALUE -/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ //#define SYSCLK_FREQ_48MHz 48000000 -/* #define SYSCLK_FREQ_56MHz 56000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ //#define SYSCLK_FREQ_72MHz 72000000 //#define SYSCLK_FREQ_96MHz 96000000 //#define SYSCLK_FREQ_120MHz 120000000 @@ -60,7 +60,7 @@ static void SetSysClock(void); #elif defined SYSCLK_FREQ_48MHz static void SetSysClockTo48(void); #elif defined SYSCLK_FREQ_56MHz - static void SetSysClockTo56(void); + static void SetSysClockTo56(void); #elif defined SYSCLK_FREQ_72MHz static void SetSysClockTo72(void); @@ -90,7 +90,7 @@ void SystemInit (void) RCC->CFGR0 &= (uint32_t)0xF8FF0000; #else RCC->CFGR0 &= (uint32_t)0xF0FF0000; -#endif +#endif RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; @@ -101,8 +101,8 @@ void SystemInit (void) RCC->INTR = 0x00FF0000; RCC->CFGR2 = 0x00000000; #else - RCC->INTR = 0x009F0000; -#endif + RCC->INTR = 0x009F0000; +#endif SetSysClock(); } @@ -118,18 +118,18 @@ void SystemCoreClockUpdate (void) uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0; tmp = RCC->CFGR0 & RCC_SWS; - + switch (tmp) { case 0x00: SystemCoreClock = HSI_VALUE; break; - case 0x04: + case 0x04: SystemCoreClock = HSE_VALUE; break; - case 0x08: + case 0x08: pllmull = RCC->CFGR0 & RCC_PLLMULL; - pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllsource = RCC->CFGR0 & RCC_PLLSRC; pllmull = ( pllmull >> 18) + 2; #ifdef CH32V30x_D8 @@ -149,7 +149,7 @@ void SystemCoreClockUpdate (void) SystemCoreClock = (HSI_VALUE >> 1) * pllmull; } else - { + { if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) { SystemCoreClock = (HSE_VALUE >> 1) * pllmull; @@ -167,9 +167,9 @@ void SystemCoreClockUpdate (void) SystemCoreClock = HSI_VALUE; break; } - + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; - SystemCoreClock >>= tmp; + SystemCoreClock >>= tmp; } /********************************************************************* @@ -188,7 +188,7 @@ static void SetSysClock(void) #elif defined SYSCLK_FREQ_48MHz SetSysClockTo48(); #elif defined SYSCLK_FREQ_56MHz - SetSysClockTo56(); + SetSysClockTo56(); #elif defined SYSCLK_FREQ_72MHz SetSysClockTo72(); #elif defined SYSCLK_FREQ_96MHz @@ -199,9 +199,9 @@ static void SetSysClock(void) SetSysClockTo144(); #endif - + /* If none of the define above is enabled, the HSI is used as System clock - * source (default after reset) + * source (default after reset) */ } @@ -218,14 +218,14 @@ static void SetSysClock(void) static void SetSysClockToHSE(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - + RCC->CTLR |= ((uint32_t)RCC_HSEON); - + /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; + StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CTLR & RCC_HSERDY) != RESET) @@ -235,20 +235,20 @@ static void SetSysClockToHSE(void) else { HSEStatus = (uint32_t)0x00; - } + } if (HSEStatus == (uint32_t)0x01) { /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; - + /* Select HSE as system clock source */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; /* Wait till HSE is used as system clock source */ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) @@ -256,11 +256,11 @@ static void SetSysClockToHSE(void) } } else - { + { /* If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error + * configuration. User can add here some code to deal with this error */ - } + } } #elif defined SYSCLK_FREQ_24MHz @@ -275,14 +275,14 @@ static void SetSysClockToHSE(void) static void SetSysClockTo24(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - + RCC->CTLR |= ((uint32_t)RCC_HSEON); - + /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; + StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CTLR & RCC_HSERDY) != RESET) @@ -292,13 +292,13 @@ static void SetSysClockTo24(void) else { HSEStatus = (uint32_t)0x00; - } + } if (HSEStatus == (uint32_t)0x01) { /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; @@ -318,18 +318,18 @@ static void SetSysClockTo24(void) } /* Select PLL as system clock source */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) { } } else - { + { /* If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error + * configuration. User can add here some code to deal with this error */ - } + } } #elif defined SYSCLK_FREQ_48MHz @@ -344,14 +344,14 @@ static void SetSysClockTo24(void) static void SetSysClockTo48(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - + + RCC->CTLR |= ((uint32_t)RCC_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; + StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CTLR & RCC_HSERDY) != RESET) @@ -361,14 +361,14 @@ static void SetSysClockTo48(void) else { HSEStatus = (uint32_t)0x00; - } + } if (HSEStatus == (uint32_t)0x01) { /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; @@ -389,19 +389,19 @@ static void SetSysClockTo48(void) } /* Select PLL as system clock source */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) { } } else - { + { /* * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error + * configuration. User can add here some code to deal with this error */ - } + } } #elif defined SYSCLK_FREQ_56MHz @@ -416,14 +416,14 @@ static void SetSysClockTo48(void) static void SetSysClockTo56(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - + RCC->CTLR |= ((uint32_t)RCC_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; + StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CTLR & RCC_HSERDY) != RESET) @@ -433,17 +433,17 @@ static void SetSysClockTo56(void) else { HSEStatus = (uint32_t)0x00; - } + } if (HSEStatus == (uint32_t)0x01) { /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); @@ -462,19 +462,19 @@ static void SetSysClockTo56(void) /* Select PLL as system clock source */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) { } } else - { + { /* * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error + * configuration. User can add here some code to deal with this error */ - } + } } #elif defined SYSCLK_FREQ_72MHz @@ -489,14 +489,14 @@ static void SetSysClockTo56(void) static void SetSysClockTo72(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - + RCC->CTLR |= ((uint32_t)RCC_HSEON); - + /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; + StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CTLR & RCC_HSERDY) != RESET) @@ -506,17 +506,17 @@ static void SetSysClockTo72(void) else { HSEStatus = (uint32_t)0x00; - } + } if (HSEStatus == (uint32_t)0x01) { /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); @@ -532,20 +532,20 @@ static void SetSysClockTo72(void) /* Wait till PLL is ready */ while((RCC->CTLR & RCC_PLLRDY) == 0) { - } + } /* Select PLL as system clock source */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) { } } else - { + { /* * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error + * configuration. User can add here some code to deal with this error */ } } diff --git a/hw/bsp/ch32v307/system_ch32v30x.h b/hw/bsp/ch32v307/system_ch32v30x.h index 0e0ef4e51..ad81058c7 100644 --- a/hw/bsp/ch32v307/system_ch32v30x.h +++ b/hw/bsp/ch32v307/system_ch32v30x.h @@ -7,16 +7,16 @@ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * SPDX-License-Identifier: Apache-2.0 *******************************************************************************/ -#ifndef __SYSTEM_CH32V30x_H +#ifndef __SYSTEM_CH32V30x_H #define __SYSTEM_CH32V30x_H #ifdef __cplusplus extern "C" { -#endif +#endif extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ -/* System_Exported_Functions */ +/* System_Exported_Functions */ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); @@ -25,6 +25,3 @@ extern void SystemCoreClockUpdate(void); #endif #endif /*__CH32V30x_SYSTEM_H */ - - - diff --git a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c index a4d996810..3abb488f2 100644 --- a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c +++ b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Jerzy Kasenberg diff --git a/hw/bsp/da14695_dk_usb/da1469x.ld b/hw/bsp/da14695_dk_usb/da1469x.ld index 96507d6e7..8cc1d9d99 100644 --- a/hw/bsp/da14695_dk_usb/da1469x.ld +++ b/hw/bsp/da14695_dk_usb/da1469x.ld @@ -242,4 +242,3 @@ SECTIONS /* Check that intvect is at the beginning of RAM */ ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM") } - diff --git a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c index 13113fb95..abe7f54cb 100644 --- a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c +++ b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Jerzy Kasenberg diff --git a/hw/bsp/da1469x_dk_pro/da1469x.ld b/hw/bsp/da1469x_dk_pro/da1469x.ld index 96507d6e7..8cc1d9d99 100644 --- a/hw/bsp/da1469x_dk_pro/da1469x.ld +++ b/hw/bsp/da1469x_dk_pro/da1469x.ld @@ -242,4 +242,3 @@ SECTIONS /* Check that intvect is at the beginning of RAM */ ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM") } - diff --git a/hw/bsp/ea4088qs/ea4088qs.c b/hw/bsp/ea4088qs/ea4088qs.c index 7150ed393..ace72fef0 100644 --- a/hw/bsp/ea4088qs/ea4088qs.c +++ b/hw/bsp/ea4088qs/ea4088qs.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/ea4088qs/lpc4088.ld b/hw/bsp/ea4088qs/lpc4088.ld index 4b1cddd6e..5897707f6 100644 --- a/hw/bsp/ea4088qs/lpc4088.ld +++ b/hw/bsp/ea4088qs/lpc4088.ld @@ -11,24 +11,24 @@ MEMORY { /* Define each memory region */ - MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */ - RamLoc64 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x10000 /* 64K bytes (alias RAM) */ - RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */ + MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */ + RamLoc64 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x10000 /* 64K bytes (alias RAM) */ + RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */ } /* Define a symbol for the top of each memory region */ - __base_MFlash512 = 0x0 ; /* MFlash512 */ - __base_Flash = 0x0 ; /* Flash */ - __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */ - __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */ - __base_RamLoc64 = 0x10000000 ; /* RamLoc64 */ - __base_RAM = 0x10000000 ; /* RAM */ - __top_RamLoc64 = 0x10000000 + 0x10000 ; /* 64K bytes */ - __top_RAM = 0x10000000 + 0x10000 ; /* 64K bytes */ - __base_RamPeriph32 = 0x20000000 ; /* RamPeriph32 */ - __base_RAM2 = 0x20000000 ; /* RAM2 */ - __top_RamPeriph32 = 0x20000000 + 0x8000 ; /* 32K bytes */ - __top_RAM2 = 0x20000000 + 0x8000 ; /* 32K bytes */ + __base_MFlash512 = 0x0 ; /* MFlash512 */ + __base_Flash = 0x0 ; /* Flash */ + __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */ + __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */ + __base_RamLoc64 = 0x10000000 ; /* RamLoc64 */ + __base_RAM = 0x10000000 ; /* RAM */ + __top_RamLoc64 = 0x10000000 + 0x10000 ; /* 64K bytes */ + __top_RAM = 0x10000000 + 0x10000 ; /* 64K bytes */ + __base_RamPeriph32 = 0x20000000 ; /* RamPeriph32 */ + __base_RAM2 = 0x20000000 ; /* RAM2 */ + __top_RamPeriph32 = 0x20000000 + 0x8000 ; /* 32K bytes */ + __top_RAM2 = 0x20000000 + 0x8000 ; /* 32K bytes */ ENTRY(ResetISR) @@ -72,9 +72,9 @@ SECTIONS } > MFlash512 /* * for exception handling/unwind - some Newlib functions (in common - * with C++ and STDC++) use this. + * with C++ and STDC++) use this. */ - .ARM.extab : ALIGN(4) + .ARM.extab : ALIGN(4) { *(.ARM.extab* .gnu.linkonce.armextab.*) } > MFlash512 @@ -88,7 +88,7 @@ SECTIONS __exidx_end = .; _etext = .; - + /* DATA section for RamPeriph32 */ .data_RAM2 : ALIGN(4) @@ -130,7 +130,7 @@ SECTIONS *(.bss.$RamPeriph32*) . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ PROVIDE(__end_bss_RAM2 = .) ; - } > RamPeriph32 + } > RamPeriph32 /* MAIN BSS SECTION */ .bss : ALIGN(4) @@ -149,13 +149,13 @@ SECTIONS *(.noinit.$RAM2*) *(.noinit.$RamPeriph32*) . = ALIGN(4) ; - } > RamPeriph32 + } > RamPeriph32 /* DEFAULT NOINIT SECTION */ .noinit (NOLOAD): ALIGN(4) { _noinit = .; - *(.noinit*) + *(.noinit*) . = ALIGN(4) ; _end_noinit = .; } > RamLoc64 @@ -163,11 +163,11 @@ SECTIONS PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc64 - 0); /* ## Create checksum value (used in startup) ## */ - PROVIDE(__valid_user_code_checksum = 0 - - (_vStackTop - + (ResetISR + 1) - + (NMI_Handler + 1) - + (HardFault_Handler + 1) + PROVIDE(__valid_user_code_checksum = 0 - + (_vStackTop + + (ResetISR + 1) + + (NMI_Handler + 1) + + (HardFault_Handler + 1) + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */ @@ -181,4 +181,4 @@ SECTIONS _image_start = LOADADDR(.text); _image_end = LOADADDR(.data) + SIZEOF(.data); _image_size = _image_end - _image_start; -} \ No newline at end of file +} diff --git a/hw/bsp/ea4357/ea4357.c b/hw/bsp/ea4357/ea4357.c index f88d3b89e..68bcaa123 100644 --- a/hw/bsp/ea4357/ea4357.c +++ b/hw/bsp/ea4357/ea4357.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/ea4357/lpc4357.ld b/hw/bsp/ea4357/lpc4357.ld index 14a0df328..e3dfbfda1 100644 --- a/hw/bsp/ea4357/lpc4357.ld +++ b/hw/bsp/ea4357/lpc4357.ld @@ -11,44 +11,44 @@ MEMORY { /* Define each memory region */ - MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */ - MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */ - RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */ - RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */ - RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */ - RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */ - RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */ + MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */ + MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */ + RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */ + RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */ + RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */ + RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */ + RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */ } /* Define a symbol for the top of each memory region */ - __base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */ - __base_Flash = 0x1a000000 ; /* Flash */ - __top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */ - __top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */ - __base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */ - __base_Flash2 = 0x1b000000 ; /* Flash2 */ - __top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */ - __top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */ - __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */ - __base_RAM = 0x10000000 ; /* RAM */ - __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */ - __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */ - __base_RamLoc40 = 0x10080000 ; /* RamLoc40 */ - __base_RAM2 = 0x10080000 ; /* RAM2 */ - __top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */ - __top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */ - __base_RamAHB32 = 0x20000000 ; /* RamAHB32 */ - __base_RAM3 = 0x20000000 ; /* RAM3 */ - __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */ - __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */ - __base_RamAHB16 = 0x20008000 ; /* RamAHB16 */ - __base_RAM4 = 0x20008000 ; /* RAM4 */ - __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */ - __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */ - __base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */ - __base_RAM5 = 0x2000c000 ; /* RAM5 */ - __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */ - __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */ + __base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */ + __base_Flash = 0x1a000000 ; /* Flash */ + __top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */ + __top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */ + __base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */ + __base_Flash2 = 0x1b000000 ; /* Flash2 */ + __top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */ + __top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */ + __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */ + __base_RAM = 0x10000000 ; /* RAM */ + __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */ + __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */ + __base_RamLoc40 = 0x10080000 ; /* RamLoc40 */ + __base_RAM2 = 0x10080000 ; /* RAM2 */ + __top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */ + __top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */ + __base_RamAHB32 = 0x20000000 ; /* RamAHB32 */ + __base_RAM3 = 0x20000000 ; /* RAM3 */ + __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */ + __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */ + __base_RamAHB16 = 0x20008000 ; /* RamAHB16 */ + __base_RAM4 = 0x20008000 ; /* RAM4 */ + __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */ + __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */ + __base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */ + __base_RAM5 = 0x2000c000 ; /* RAM5 */ + __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */ + __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */ ENTRY(ResetISR) @@ -119,9 +119,9 @@ SECTIONS } > MFlashA512 /* * for exception handling/unwind - some Newlib functions (in common - * with C++ and STDC++) use this. + * with C++ and STDC++) use this. */ - .ARM.extab : ALIGN(4) + .ARM.extab : ALIGN(4) { *(.ARM.extab* .gnu.linkonce.armextab.*) } > MFlashA512 @@ -135,7 +135,7 @@ SECTIONS __exidx_end = .; _etext = .; - + /* DATA section for RamLoc40 */ .data_RAM2 : ALIGN(4) @@ -216,7 +216,7 @@ SECTIONS *(.bss.$RamLoc40*) . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ PROVIDE(__end_bss_RAM2 = .) ; - } > RamLoc40 + } > RamLoc40 /* BSS section for RamAHB32 */ .bss_RAM3 : ALIGN(4) @@ -226,7 +226,7 @@ SECTIONS *(.bss.$RamAHB32*) . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ PROVIDE(__end_bss_RAM3 = .) ; - } > RamAHB32 + } > RamAHB32 /* BSS section for RamAHB16 */ .bss_RAM4 : ALIGN(4) @@ -236,7 +236,7 @@ SECTIONS *(.bss.$RamAHB16*) . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ PROVIDE(__end_bss_RAM4 = .) ; - } > RamAHB16 + } > RamAHB16 /* BSS section for RamAHB_ETB16 */ .bss_RAM5 : ALIGN(4) @@ -246,7 +246,7 @@ SECTIONS *(.bss.$RamAHB_ETB16*) . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ PROVIDE(__end_bss_RAM5 = .) ; - } > RamAHB_ETB16 + } > RamAHB_ETB16 /* MAIN BSS SECTION */ .bss : ALIGN(4) @@ -265,7 +265,7 @@ SECTIONS *(.noinit.$RAM2*) *(.noinit.$RamLoc40*) . = ALIGN(4) ; - } > RamLoc40 + } > RamLoc40 /* NOINIT section for RamAHB32 */ .noinit_RAM3 (NOLOAD) : ALIGN(4) @@ -273,7 +273,7 @@ SECTIONS *(.noinit.$RAM3*) *(.noinit.$RamAHB32*) . = ALIGN(4) ; - } > RamAHB32 + } > RamAHB32 /* NOINIT section for RamAHB16 */ .noinit_RAM4 (NOLOAD) : ALIGN(4) @@ -281,7 +281,7 @@ SECTIONS *(.noinit.$RAM4*) *(.noinit.$RamAHB16*) . = ALIGN(4) ; - } > RamAHB16 + } > RamAHB16 /* NOINIT section for RamAHB_ETB16 */ .noinit_RAM5 (NOLOAD) : ALIGN(4) @@ -289,13 +289,13 @@ SECTIONS *(.noinit.$RAM5*) *(.noinit.$RamAHB_ETB16*) . = ALIGN(4) ; - } > RamAHB_ETB16 + } > RamAHB_ETB16 /* DEFAULT NOINIT SECTION */ .noinit (NOLOAD): ALIGN(4) { _noinit = .; - *(.noinit*) + *(.noinit*) . = ALIGN(4) ; _end_noinit = .; } > RamLoc32 @@ -303,11 +303,11 @@ SECTIONS PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0); /* ## Create checksum value (used in startup) ## */ - PROVIDE(__valid_user_code_checksum = 0 - - (_vStackTop - + (ResetISR + 1) - + (NMI_Handler + 1) - + (HardFault_Handler + 1) + PROVIDE(__valid_user_code_checksum = 0 - + (_vStackTop + + (ResetISR + 1) + + (NMI_Handler + 1) + + (HardFault_Handler + 1) + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */ @@ -321,4 +321,4 @@ SECTIONS _image_start = LOADADDR(.text); _image_end = LOADADDR(.data) + SIZEOF(.data); _image_size = _image_end - _image_start; -} \ No newline at end of file +} diff --git a/hw/bsp/ea4357/pca9532.c b/hw/bsp/ea4357/pca9532.c index eae3805c2..150167cde 100644 --- a/hw/bsp/ea4357/pca9532.c +++ b/hw/bsp/ea4357/pca9532.c @@ -57,7 +57,7 @@ static uint16_t ledStateShadow = 0; * Local Functions *****************************************************************************/ -static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len) +static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len) { I2CM_XFER_T i2cData; @@ -75,7 +75,7 @@ static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len) return SUCCESS; } -static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len) +static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len) { I2CM_XFER_T i2cData; @@ -181,7 +181,7 @@ uint16_t pca9532_getLedState (uint32_t shadow) * A blinking LED may be reported as on or off depending on * its state when reading the Input register. */ - + buf[0] = PCA9532_INPUT0; I2CWrite(PCA9532_I2C_ADDR, buf, 1); diff --git a/hw/bsp/ea4357/pca9532.h b/hw/bsp/ea4357/pca9532.h index 7a7c6e145..f21c1ff09 100644 --- a/hw/bsp/ea4357/pca9532.h +++ b/hw/bsp/ea4357/pca9532.h @@ -48,7 +48,7 @@ #define KEY_MASK 0x000F /* - * MMC Card Detect and MMC Write Protect are mapped to LED4 + * MMC Card Detect and MMC Write Protect are mapped to LED4 * and LED5 on the PCA9532. Please note that WP is active low. */ diff --git a/hw/bsp/esp32s2/boards/CMakeLists.txt b/hw/bsp/esp32s2/boards/CMakeLists.txt index c3c687a70..ff90acbde 100644 --- a/hw/bsp/esp32s2/boards/CMakeLists.txt +++ b/hw/bsp/esp32s2/boards/CMakeLists.txt @@ -8,5 +8,5 @@ include("${BOARD}/board.cmake") target_include_directories(${COMPONENT_TARGET} PUBLIC "${TOP}/hw" - "${TOP}/src" + "${TOP}/src" ) diff --git a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake b/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake index d33962676..e39ceb887 100644 --- a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake +++ b/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake @@ -14,4 +14,4 @@ set(IDF_TARGET "esp32s2" FORCE) target_compile_options(${COMPONENT_TARGET} PUBLIC "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2" "-DCFG_TUSB_OS=OPT_OS_FREERTOS" -) \ No newline at end of file +) diff --git a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h b/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h index 43e00901d..1f8dc2cea 100644 --- a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h +++ b/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake b/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake index d33962676..e39ceb887 100644 --- a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake +++ b/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake @@ -14,4 +14,4 @@ set(IDF_TARGET "esp32s2" FORCE) target_compile_options(${COMPONENT_TARGET} PUBLIC "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2" "-DCFG_TUSB_OS=OPT_OS_FREERTOS" -) \ No newline at end of file +) diff --git a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h b/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h index 16e30b685..084a7aaf2 100644 --- a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h +++ b/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake b/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake index d5c17b9be..16b0e9cdd 100644 --- a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake +++ b/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake @@ -14,4 +14,4 @@ set(IDF_TARGET "esp32s2" FORCE) target_compile_options(${COMPONENT_TARGET} PUBLIC "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2" "-DCFG_TUSB_OS=OPT_OS_FREERTOS" -) \ No newline at end of file +) diff --git a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h b/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h index 49a2474bc..2ec80ef47 100644 --- a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h +++ b/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/esp32s2/boards/esp32s2.c b/hw/bsp/esp32s2/boards/esp32s2.c index a7ca82deb..015d8305b 100644 --- a/hw/bsp/esp32s2/boards/esp32s2.c +++ b/hw/bsp/esp32s2/boards/esp32s2.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) @@ -150,4 +150,3 @@ int board_uart_write(void const * buf, int len) (void) buf; (void) len; return 0; } - diff --git a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake b/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake index d5c17b9be..16b0e9cdd 100644 --- a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake +++ b/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake @@ -14,4 +14,4 @@ set(IDF_TARGET "esp32s2" FORCE) target_compile_options(${COMPONENT_TARGET} PUBLIC "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2" "-DCFG_TUSB_OS=OPT_OS_FREERTOS" -) \ No newline at end of file +) diff --git a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h b/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h index 6bb44f76d..0acb9c439 100644 --- a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h +++ b/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake b/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake index d5c17b9be..16b0e9cdd 100644 --- a/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake +++ b/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake @@ -14,4 +14,4 @@ set(IDF_TARGET "esp32s2" FORCE) target_compile_options(${COMPONENT_TARGET} PUBLIC "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2" "-DCFG_TUSB_OS=OPT_OS_FREERTOS" -) \ No newline at end of file +) diff --git a/hw/bsp/esp32s2/boards/espressif_saola_1/board.h b/hw/bsp/esp32s2/boards/espressif_saola_1/board.h index f450b9a8b..e068efef9 100644 --- a/hw/bsp/esp32s2/boards/espressif_saola_1/board.h +++ b/hw/bsp/esp32s2/boards/espressif_saola_1/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt b/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt index 6d0fcbc86..8266c5a1c 100644 --- a/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt +++ b/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt @@ -5,4 +5,3 @@ idf_component_register(SRCS "${component_srcs}" PRIV_INCLUDE_DIRS "" PRIV_REQUIRES "driver" REQUIRES "") - diff --git a/hw/bsp/esp32s2/family.cmake b/hw/bsp/esp32s2/family.cmake index f3d41d041..0973adcac 100644 --- a/hw/bsp/esp32s2/family.cmake +++ b/hw/bsp/esp32s2/family.cmake @@ -1,7 +1,7 @@ cmake_minimum_required(VERSION 3.5) # Add example src and bsp directories -set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s2/boards" "${TOP}/hw/bsp/esp32s2/components") +set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s2/boards" "${TOP}/hw/bsp/esp32s2/components") include($ENV{IDF_PATH}/tools/cmake/project.cmake) set(SUPPORTED_TARGETS esp32s2) set(FAMILY_MCUS ESP32S2) diff --git a/hw/bsp/esp32s2/family.mk b/hw/bsp/esp32s2/family.mk index b95098e15..fba0f038b 100644 --- a/hw/bsp/esp32s2/family.mk +++ b/hw/bsp/esp32s2/family.mk @@ -21,4 +21,3 @@ UF2_FAMILY_ID = 0xbfdd4eee $(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin @echo CREATE $@ $(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b 0x0 -c -o $@ $^ - diff --git a/hw/bsp/esp32s3/boards/CMakeLists.txt b/hw/bsp/esp32s3/boards/CMakeLists.txt index e1b921ae9..311c6e900 100644 --- a/hw/bsp/esp32s3/boards/CMakeLists.txt +++ b/hw/bsp/esp32s3/boards/CMakeLists.txt @@ -10,5 +10,5 @@ idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PAT target_include_directories(${COMPONENT_TARGET} PUBLIC "${FREERTOS_ORIG_INCLUDE_PATH}" "${TOP}/hw" - "${TOP}/src" + "${TOP}/src" ) diff --git a/hw/bsp/esp32s3/boards/esp32s3.c b/hw/bsp/esp32s3/boards/esp32s3.c index a7ca82deb..015d8305b 100644 --- a/hw/bsp/esp32s3/boards/esp32s3.c +++ b/hw/bsp/esp32s3/boards/esp32s3.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) @@ -150,4 +150,3 @@ int board_uart_write(void const * buf, int len) (void) buf; (void) len; return 0; } - diff --git a/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake b/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake index 8996ff9dc..2bff4f836 100644 --- a/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake +++ b/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake @@ -4,4 +4,4 @@ target_include_directories(${COMPONENT_LIB} PRIVATE .) target_compile_options(${COMPONENT_TARGET} PUBLIC "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3" "-DCFG_TUSB_OS=OPT_OS_FREERTOS" -) \ No newline at end of file +) diff --git a/hw/bsp/esp32s3/boards/espressif_addax_1/board.h b/hw/bsp/esp32s3/boards/espressif_addax_1/board.h index fff24ba44..d4690f732 100644 --- a/hw/bsp/esp32s3/boards/espressif_addax_1/board.h +++ b/hw/bsp/esp32s3/boards/espressif_addax_1/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake b/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake index 8996ff9dc..2bff4f836 100644 --- a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake +++ b/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake @@ -4,4 +4,4 @@ target_include_directories(${COMPONENT_LIB} PRIVATE .) target_compile_options(${COMPONENT_TARGET} PUBLIC "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3" "-DCFG_TUSB_OS=OPT_OS_FREERTOS" -) \ No newline at end of file +) diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h b/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h index c7940c56e..fe33b5c43 100644 --- a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h +++ b/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake b/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake index 8996ff9dc..2bff4f836 100644 --- a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake +++ b/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake @@ -4,4 +4,4 @@ target_include_directories(${COMPONENT_LIB} PRIVATE .) target_compile_options(${COMPONENT_TARGET} PUBLIC "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3" "-DCFG_TUSB_OS=OPT_OS_FREERTOS" -) \ No newline at end of file +) diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h b/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h index c7940c56e..fe33b5c43 100644 --- a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h +++ b/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt b/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt index 6d0fcbc86..8266c5a1c 100644 --- a/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt +++ b/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt @@ -5,4 +5,3 @@ idf_component_register(SRCS "${component_srcs}" PRIV_INCLUDE_DIRS "" PRIV_REQUIRES "driver" REQUIRES "") - diff --git a/hw/bsp/esp32s3/family.cmake b/hw/bsp/esp32s3/family.cmake index 511dd58bb..0bcad035e 100644 --- a/hw/bsp/esp32s3/family.cmake +++ b/hw/bsp/esp32s3/family.cmake @@ -1,7 +1,7 @@ cmake_minimum_required(VERSION 3.5) # Add example src and bsp directories -set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s3/boards" "${TOP}/hw/bsp/esp32s3/components") +set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s3/boards" "${TOP}/hw/bsp/esp32s3/components") include($ENV{IDF_PATH}/tools/cmake/project.cmake) set(SUPPORTED_TARGETS esp32s3) set(FAMILY_MCUS ESP32S3) diff --git a/hw/bsp/esp32s3/family.mk b/hw/bsp/esp32s3/family.mk index cf153ffc2..d82a1c969 100644 --- a/hw/bsp/esp32s3/family.mk +++ b/hw/bsp/esp32s3/family.mk @@ -23,4 +23,3 @@ UF2_FAMILY_ID = 0xc47e5767 $(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin @echo CREATE $@ $(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b 0x0 -c -o $@ $^ - diff --git a/hw/bsp/f1c100s/README.md b/hw/bsp/f1c100s/README.md index 4aa1e153b..f7a863c34 100644 --- a/hw/bsp/f1c100s/README.md +++ b/hw/bsp/f1c100s/README.md @@ -17,4 +17,4 @@ Flash: `make BOARD=f1c100s flash` will write the image to SPI flash, and then re ## TODO -* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT` high speed MCU check in examples (maybe we should extract the logic?) \ No newline at end of file +* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT` high speed MCU check in examples (maybe we should extract the logic?) diff --git a/hw/bsp/f1c100s/board.h b/hw/bsp/f1c100s/board.h index 238ac796d..0ef9a1700 100644 --- a/hw/bsp/f1c100s/board.h +++ b/hw/bsp/f1c100s/board.h @@ -1 +1 @@ -// Nothing valuable here \ No newline at end of file +// Nothing valuable here diff --git a/hw/bsp/f1c100s/board.mk b/hw/bsp/f1c100s/board.mk index 5fe26a9ea..9062483b0 100644 --- a/hw/bsp/f1c100s/board.mk +++ b/hw/bsp/f1c100s/board.mk @@ -32,7 +32,7 @@ SRC_C += \ $(MCU_DIR)/machine/sys-spi-flash.c \ $(MCU_DIR)/machine/f1c100s-intc.c \ $(MCU_DIR)/lib/malloc.c \ - $(MCU_DIR)/lib/printf.c + $(MCU_DIR)/lib/printf.c SRC_S += \ $(MCU_DIR)/machine/start.S \ @@ -47,6 +47,6 @@ INC += \ flash: flash-xfel exec: $(BUILD)/$(PROJECT).bin - xfel ddr + xfel ddr xfel write 0x80000000 $< - xfel exec 0x80000000 \ No newline at end of file + xfel exec 0x80000000 diff --git a/hw/bsp/f1c100s/f1c100s.c b/hw/bsp/f1c100s/f1c100s.c index d45072ecb..5dcae33f7 100644 --- a/hw/bsp/f1c100s/f1c100s.c +++ b/hw/bsp/f1c100s/f1c100s.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -125,6 +125,6 @@ static void timer_init(void) { f1c100s_intc_set_isr(F1C100S_IRQ_TIMER0, timer_handler); f1c100s_intc_enable_irq(F1C100S_IRQ_TIMER0); } -#else +#else static void timer_init(void) { } #endif diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 601cd54f5..08bb20bc3 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -139,4 +139,4 @@ if (NOT TARGET _family_support_marker) # save it in case of re-inclusion set(FAMILY_MCUS ${FAMILY_MCUS} CACHE INTERNAL "") -endif() \ No newline at end of file +endif() diff --git a/hw/bsp/fomu/boards/fomu/board.mk b/hw/bsp/fomu/boards/fomu/board.mk index 8ced11412..b5545c89a 100644 --- a/hw/bsp/fomu/boards/fomu/board.mk +++ b/hw/bsp/fomu/boards/fomu/board.mk @@ -1 +1 @@ -# place holder \ No newline at end of file +# place holder diff --git a/hw/bsp/fomu/fomu.c b/hw/bsp/fomu/fomu.c index 33c630303..e079e7c5b 100644 --- a/hw/bsp/fomu/fomu.c +++ b/hw/bsp/fomu/fomu.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/fomu/include/hw/common.h b/hw/bsp/fomu/include/hw/common.h index 6a97ca2e9..b902bc4f2 100644 --- a/hw/bsp/fomu/include/hw/common.h +++ b/hw/bsp/fomu/include/hw/common.h @@ -30,4 +30,4 @@ static inline uint32_t csr_readl(uint32_t addr) { return *(volatile uint32_t *)addr; } -#endif /* _HW_COMMON_H_ */ \ No newline at end of file +#endif /* _HW_COMMON_H_ */ diff --git a/hw/bsp/fomu/include/irq.h b/hw/bsp/fomu/include/irq.h index a82218907..dc96c228d 100644 --- a/hw/bsp/fomu/include/irq.h +++ b/hw/bsp/fomu/include/irq.h @@ -68,4 +68,4 @@ static inline unsigned int irq_pending(void) } #endif -#endif /* __IRQ_H */ \ No newline at end of file +#endif /* __IRQ_H */ diff --git a/hw/bsp/frdm_k32l2b/board.h b/hw/bsp/frdm_k32l2b/board.h index 825367915..8d21fdcd4 100644 --- a/hw/bsp/frdm_k32l2b/board.h +++ b/hw/bsp/frdm_k32l2b/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, Ha Thach (tinyusb.org) diff --git a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/frdm_k32l2b/frdm_k32l2b.c index 924bb18e9..8d2b39500 100644 --- a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c +++ b/hw/bsp/frdm_k32l2b/frdm_k32l2b.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2018, hathach (tinyusb.org) @@ -56,10 +56,10 @@ void board_init(void) gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); const port_pin_config_t BUTTON_CFG = { - kPORT_PullUp, - kPORT_FastSlewRate, - kPORT_PassiveFilterDisable, - kPORT_LowDriveStrength, + kPORT_PullUp, + kPORT_FastSlewRate, + kPORT_PassiveFilterDisable, + kPORT_LowDriveStrength, kPORT_MuxAsGpio }; PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); @@ -68,7 +68,7 @@ void board_init(void) PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2); /* PORTA2 (pin 24) is configured as LPUART0_TX */ PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2); - + SIM->SOPT5 = ((SIM->SOPT5 & /* Mask bits to zero which are setting */ (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK))) diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/frdm_kl25z/frdm_kl25z.c index 8d93fdbaa..46f85f6a5 100644 --- a/hw/bsp/frdm_kl25z/frdm_kl25z.c +++ b/hw/bsp/frdm_kl25z/frdm_kl25z.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2018, hathach (tinyusb.org) @@ -103,7 +103,7 @@ void board_init(void) // Button CLOCK_EnableClock(BUTTON_PIN_CLOCK); port_pin_config_t button_port = { - .pullSelect = kPORT_PullUp, + .pullSelect = kPORT_PullUp, .mux = BUTTON_PIN_FUNCTION, }; PORT_SetPinConfig(BUTTON_PIN_PORT, BUTTON_PIN, &button_port); diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c index 60a326d27..113c4c304 100644 --- a/hw/bsp/gd32vf103/family.c +++ b/hw/bsp/gd32vf103/family.c @@ -44,7 +44,7 @@ void USBFS_IRQHandler(void) { tud_int_handler(0); } // According to GD32VF103 user manual clock tree: // Systick clock = AHB clock / 4. -#define TIMER_TICKS ((SystemCoreClock / 4) / 1000) +#define TIMER_TICKS ((SystemCoreClock / 4) / 1000) #define BUTTON_PORT GPIOA #define BUTTON_PIN GPIO_PIN_0 diff --git a/hw/bsp/gd32vf103/system_gd32vf103.c b/hw/bsp/gd32vf103/system_gd32vf103.c index c2001a980..200852abf 100644 --- a/hw/bsp/gd32vf103/system_gd32vf103.c +++ b/hw/bsp/gd32vf103/system_gd32vf103.c @@ -95,7 +95,7 @@ void SystemInit(void) /* reset the RCC clock configuration to the default reset state */ /* enable IRC8M */ RCU_CTL |= RCU_CTL_IRC8MEN; - + /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); @@ -107,7 +107,7 @@ void SystemInit(void) RCU_CTL &= ~(RCU_CTL_HXTALBPS); /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ - + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); RCU_CFG1 = 0x00000000U; @@ -141,12 +141,12 @@ void SystemCoreClockUpdate(void) case SEL_IRC8M: SystemCoreClock = IRC8M_VALUE; break; - + /* HXTAL is selected as CK_SYS */ case SEL_HXTAL: SystemCoreClock = HXTAL_VALUE; break; - + /* PLL is selected as CK_SYS */ case SEL_PLL: /* PLL clock source selection, HXTAL or IRC8M/2 */ @@ -313,7 +313,7 @@ static void system_clock_72m_hxtal(void) /* APB1 = AHB/2 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ + /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.h b/hw/bsp/imxrt/boards/metro_m7_1011/board.h index 7fa2f8541..3c172ebb9 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011/board.h +++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, Ha Thach (tinyusb.org) diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld index 30dd84373..960fc6891 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld +++ b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld @@ -35,7 +35,7 @@ MEMORY { m_flash_config (RX) : ORIGIN = 0x60000400, LENGTH = 0x00000C00 m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 - + m_interrupts (RX) : ORIGIN = 0x6000C000, LENGTH = 0x00000400 m_text (RX) : ORIGIN = 0x6000C400, LENGTH = (8*1024*1024 - 0xC400) m_qacode (RX) : ORIGIN = 0x00000000, LENGTH = 0x00008000 diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h index 4f21b52fa..926f45618 100644 --- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, Ha Thach (tinyusb.org) diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h index 932ce7fd7..10d9fad07 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, Ha Thach (tinyusb.org) diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h index 56ed5855b..284bb08e7 100644 --- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, Ha Thach (tinyusb.org) diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h index 152c9ab18..9100072e2 100644 --- a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, Ha Thach (tinyusb.org) diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h index 0472f608c..beb69bf2b 100644 --- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, Ha Thach (tinyusb.org) diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h index 7fa37e33f..0f45f72e1 100644 --- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, Ha Thach (tinyusb.org) diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h index 5f51e91a2..37ad94eef 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, Ha Thach (tinyusb.org) diff --git a/hw/bsp/imxrt/boards/teensy_40/board.h b/hw/bsp/imxrt/boards/teensy_40/board.h index b3cc0a8c5..cac773442 100644 --- a/hw/bsp/imxrt/boards/teensy_40/board.h +++ b/hw/bsp/imxrt/boards/teensy_40/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, Ha Thach (tinyusb.org) diff --git a/hw/bsp/imxrt/boards/teensy_40/board.mk b/hw/bsp/imxrt/boards/teensy_40/board.mk index 0ad5ea5c0..45ca0fb6e 100644 --- a/hw/bsp/imxrt/boards/teensy_40/board.mk +++ b/hw/bsp/imxrt/boards/teensy_40/board.mk @@ -5,6 +5,6 @@ MCU_VARIANT = MIMXRT1062 JLINK_DEVICE = MIMXRT1062xxx6A # flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli -# Make sure it is in your PATH +# Make sure it is in your PATH flash: $(BUILD)/$(PROJECT).hex teensy_loader_cli --mcu=imxrt1062 -v -w $< diff --git a/hw/bsp/imxrt/boards/teensy_41/board.h b/hw/bsp/imxrt/boards/teensy_41/board.h index b0b4931c7..72c18f540 100644 --- a/hw/bsp/imxrt/boards/teensy_41/board.h +++ b/hw/bsp/imxrt/boards/teensy_41/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, Ha Thach (tinyusb.org) diff --git a/hw/bsp/imxrt/boards/teensy_41/board.mk b/hw/bsp/imxrt/boards/teensy_41/board.mk index 0ad5ea5c0..45ca0fb6e 100644 --- a/hw/bsp/imxrt/boards/teensy_41/board.mk +++ b/hw/bsp/imxrt/boards/teensy_41/board.mk @@ -5,6 +5,6 @@ MCU_VARIANT = MIMXRT1062 JLINK_DEVICE = MIMXRT1062xxx6A # flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli -# Make sure it is in your PATH +# Make sure it is in your PATH flash: $(BUILD)/$(PROJECT).hex teensy_loader_cli --mcu=imxrt1062 -v -w $< diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index e28a6174a..5eb672c24 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2018, hathach (tinyusb.org) diff --git a/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld b/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld index 5420ffc00..f478a99c7 100644 --- a/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld +++ b/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld @@ -214,4 +214,3 @@ SECTIONS ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") } - diff --git a/hw/bsp/kuiic/board.h b/hw/bsp/kuiic/board.h index 78ad83a2e..1e2d4f18b 100644 --- a/hw/bsp/kuiic/board.h +++ b/hw/bsp/kuiic/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, Ha Thach (tinyusb.org) diff --git a/hw/bsp/kuiic/kuiic.c b/hw/bsp/kuiic/kuiic.c index 7aaa9e03c..97677d47a 100644 --- a/hw/bsp/kuiic/kuiic.c +++ b/hw/bsp/kuiic/kuiic.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2018, hathach (tinyusb.org) @@ -96,10 +96,10 @@ void board_init(void) CLOCK_EnableClock(kCLOCK_PortD); CLOCK_EnableClock(kCLOCK_PortE); - + gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 1 }; GPIO_PinInit(GPIOA, 1U, &led_config); - PORT_SetPinMux(PORTA, 1U, kPORT_MuxAsGpio); + PORT_SetPinMux(PORTA, 1U, kPORT_MuxAsGpio); led_config.outputLogic = 0; GPIO_PinInit(GPIOA, 2U, &led_config); PORT_SetPinMux(PORTA, 2U, kPORT_MuxAsGpio); @@ -108,10 +108,10 @@ void board_init(void) gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); const port_pin_config_t BUTTON_CFG = { - kPORT_PullUp, - kPORT_FastSlewRate, - kPORT_PassiveFilterDisable, - kPORT_LowDriveStrength, + kPORT_PullUp, + kPORT_FastSlewRate, + kPORT_PassiveFilterDisable, + kPORT_LowDriveStrength, kPORT_MuxAsGpio }; PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); @@ -121,7 +121,7 @@ void board_init(void) PORT_SetPinMux(PORTC, 3U, kPORT_MuxAlt3); /* PORTA2 (pin 24) is configured as LPUART0_TX */ PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3); - + SIM->SOPT5 = ((SIM->SOPT5 & /* Mask bits to zero which are setting */ (~(SIM_SOPT5_LPUART1TXSRC_MASK | SIM_SOPT5_LPUART1RXSRC_MASK))) diff --git a/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld b/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld index 6dd12ade1..d8079717e 100644 --- a/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld +++ b/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld @@ -13,29 +13,29 @@ MEMORY { /* Define each memory region */ - MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */ - Ram0_16 (rwx) : ORIGIN = 0x2000000, LENGTH = 0x4000 /* 16K bytes (alias RAM) */ - Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes (alias RAM2) */ - Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes (alias RAM3) */ + MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */ + Ram0_16 (rwx) : ORIGIN = 0x2000000, LENGTH = 0x4000 /* 16K bytes (alias RAM) */ + Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes (alias RAM2) */ + Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes (alias RAM3) */ } /* Define a symbol for the top of each memory region */ - __base_MFlash256 = 0x0 ; /* MFlash256 */ - __base_Flash = 0x0 ; /* Flash */ - __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */ - __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */ - __base_Ram0_16 = 0x2000000 ; /* Ram0_16 */ - __base_RAM = 0x2000000 ; /* RAM */ - __top_Ram0_16 = 0x2000000 + 0x4000 ; /* 16K bytes */ - __top_RAM = 0x2000000 + 0x4000 ; /* 16K bytes */ - __base_Ram1_16 = 0x2004000 ; /* Ram1_16 */ - __base_RAM2 = 0x2004000 ; /* RAM2 */ - __top_Ram1_16 = 0x2004000 + 0x4000 ; /* 16K bytes */ - __top_RAM2 = 0x2004000 + 0x4000 ; /* 16K bytes */ - __base_Ram2_4 = 0x2008000 ; /* Ram2_4 */ - __base_RAM3 = 0x2008000 ; /* RAM3 */ - __top_Ram2_4 = 0x2008000 + 0x1000 ; /* 4K bytes */ - __top_RAM3 = 0x2008000 + 0x1000 ; /* 4K bytes */ + __base_MFlash256 = 0x0 ; /* MFlash256 */ + __base_Flash = 0x0 ; /* Flash */ + __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */ + __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */ + __base_Ram0_16 = 0x2000000 ; /* Ram0_16 */ + __base_RAM = 0x2000000 ; /* RAM */ + __top_Ram0_16 = 0x2000000 + 0x4000 ; /* 16K bytes */ + __top_RAM = 0x2000000 + 0x4000 ; /* 16K bytes */ + __base_Ram1_16 = 0x2004000 ; /* Ram1_16 */ + __base_RAM2 = 0x2004000 ; /* RAM2 */ + __top_Ram1_16 = 0x2004000 + 0x4000 ; /* 16K bytes */ + __top_RAM2 = 0x2004000 + 0x4000 ; /* 16K bytes */ + __base_Ram2_4 = 0x2008000 ; /* Ram2_4 */ + __base_RAM3 = 0x2008000 ; /* RAM3 */ + __top_Ram2_4 = 0x2008000 + 0x1000 ; /* 4K bytes */ + __top_RAM3 = 0x2008000 + 0x1000 ; /* 4K bytes */ ENTRY(ResetISR) @@ -84,9 +84,9 @@ SECTIONS } > MFlash256 /* * for exception handling/unwind - some Newlib functions (in common - * with C++ and STDC++) use this. + * with C++ and STDC++) use this. */ - .ARM.extab : ALIGN(4) + .ARM.extab : ALIGN(4) { *(.ARM.extab* .gnu.linkonce.armextab.*) } > MFlash256 @@ -98,9 +98,9 @@ SECTIONS *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > MFlash256 __exidx_end = .; - + _etext = .; - + /* DATA section for Ram1_16 */ .data_RAM2 : ALIGN(4) @@ -225,11 +225,11 @@ SECTIONS PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_Ram0_16 - 0); /* ## Create checksum value (used in startup) ## */ - PROVIDE(__valid_user_code_checksum = 0 - - (_vStackTop - + (ResetISR + 1) - + (NMI_Handler + 1) - + (HardFault_Handler + 1) + PROVIDE(__valid_user_code_checksum = 0 - + (_vStackTop + + (ResetISR + 1) + + (NMI_Handler + 1) + + (HardFault_Handler + 1) + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */ @@ -243,4 +243,4 @@ SECTIONS _image_start = LOADADDR(.text); _image_end = LOADADDR(.data) + SIZEOF(.data); _image_size = _image_end - _image_start; -} \ No newline at end of file +} diff --git a/hw/bsp/lpc15/family.c b/hw/bsp/lpc15/family.c index 7f5984a3e..30a3e51e1 100644 --- a/hw/bsp/lpc15/family.c +++ b/hw/bsp/lpc15/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld b/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld index 51fd1539d..f12c1760c 100644 --- a/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld +++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld @@ -12,43 +12,43 @@ MEMORY { /* Define each memory region */ - MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */ - MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */ - RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */ - RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */ - RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */ - RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */ - RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */ + MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */ + MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */ + RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */ + RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */ + RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */ + RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */ + RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */ } /* Define a symbol for the top of each memory region */ -__base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */ -__base_Flash = 0x1a000000 ; /* Flash */ -__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */ -__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */ -__base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */ -__base_Flash2 = 0x1b000000 ; /* Flash2 */ -__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */ -__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */ -__base_RamLoc32 = 0x10000000 ; /* RamLoc32 */ -__base_RAM = 0x10000000 ; /* RAM */ -__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */ -__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */ -__base_RamLoc40 = 0x10080000 ; /* RamLoc40 */ -__base_RAM2 = 0x10080000 ; /* RAM2 */ -__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */ -__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */ -__base_RamAHB32 = 0x20000000 ; /* RamAHB32 */ -__base_RAM3 = 0x20000000 ; /* RAM3 */ -__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */ -__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */ -__base_RamAHB16 = 0x20008000 ; /* RamAHB16 */ -__base_RAM4 = 0x20008000 ; /* RAM4 */ -__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */ -__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */ -__base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */ -__base_RAM5 = 0x2000c000 ; /* RAM5 */ -__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */ +__base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */ +__base_Flash = 0x1a000000 ; /* Flash */ +__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */ +__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */ +__base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */ +__base_Flash2 = 0x1b000000 ; /* Flash2 */ +__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */ +__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */ +__base_RamLoc32 = 0x10000000 ; /* RamLoc32 */ +__base_RAM = 0x10000000 ; /* RAM */ +__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */ +__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */ +__base_RamLoc40 = 0x10080000 ; /* RamLoc40 */ +__base_RAM2 = 0x10080000 ; /* RAM2 */ +__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */ +__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */ +__base_RamAHB32 = 0x20000000 ; /* RamAHB32 */ +__base_RAM3 = 0x20000000 ; /* RAM3 */ +__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */ +__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */ +__base_RamAHB16 = 0x20008000 ; /* RamAHB16 */ +__base_RAM4 = 0x20008000 ; /* RAM4 */ +__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */ +__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */ +__base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */ +__base_RAM5 = 0x2000c000 ; /* RAM5 */ +__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */ __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */ ENTRY(ResetISR) @@ -137,9 +137,9 @@ SECTIONS *(.ARM.exidx* .gnu.linkonce.armexidx.*) __exidx_end = .; } > MFlashA512 - + _etext = .; - + /* DATA section for RamLoc40 */ .data_RAM2 : ALIGN(4) @@ -377,17 +377,17 @@ SECTIONS . = ALIGN(4) ; _end_noinit = .; PROVIDE(__end_noinit_RAM = .) ; - PROVIDE(__end_noinit_RamLoc32 = .) ; + PROVIDE(__end_noinit_RamLoc32 = .) ; } > RamLoc32 AT> RamLoc32 PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .); PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0); /* ## Create checksum value (used in startup) ## */ - PROVIDE(__valid_user_code_checksum = 0 - - (_vStackTop - + (ResetISR + 1) - + (NMI_Handler + 1) - + (HardFault_Handler + 1) + PROVIDE(__valid_user_code_checksum = 0 - + (_vStackTop + + (ResetISR + 1) + + (NMI_Handler + 1) + + (HardFault_Handler + 1) + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */ @@ -401,4 +401,4 @@ SECTIONS _image_start = LOADADDR(.text); _image_end = LOADADDR(.data) + SIZEOF(.data); _image_size = _image_end - _image_start; -} \ No newline at end of file +} diff --git a/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld b/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld index 9a308e342..9a67e8946 100644 --- a/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld +++ b/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld @@ -11,44 +11,44 @@ MEMORY { /* Define each memory region */ - MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */ - MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */ - RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */ - RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */ - RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */ - RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */ - RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */ + MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */ + MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */ + RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */ + RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */ + RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */ + RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */ + RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */ } /* Define a symbol for the top of each memory region */ -__base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */ -__base_Flash = 0x1a000000 ; /* Flash */ -__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */ -__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */ -__base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */ -__base_Flash2 = 0x1b000000 ; /* Flash2 */ -__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */ -__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */ -__base_RamLoc32 = 0x10000000 ; /* RamLoc32 */ -__base_RAM = 0x10000000 ; /* RAM */ -__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */ -__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */ -__base_RamLoc40 = 0x10080000 ; /* RamLoc40 */ -__base_RAM2 = 0x10080000 ; /* RAM2 */ -__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */ -__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */ -__base_RamAHB32 = 0x20000000 ; /* RamAHB32 */ -__base_RAM3 = 0x20000000 ; /* RAM3 */ -__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */ -__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */ -__base_RamAHB16 = 0x20008000 ; /* RamAHB16 */ -__base_RAM4 = 0x20008000 ; /* RAM4 */ -__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */ -__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */ -__base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */ -__base_RAM5 = 0x2000c000 ; /* RAM5 */ -__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */ -__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */ +__base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */ +__base_Flash = 0x1a000000 ; /* Flash */ +__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */ +__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */ +__base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */ +__base_Flash2 = 0x1b000000 ; /* Flash2 */ +__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */ +__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */ +__base_RamLoc32 = 0x10000000 ; /* RamLoc32 */ +__base_RAM = 0x10000000 ; /* RAM */ +__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */ +__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */ +__base_RamLoc40 = 0x10080000 ; /* RamLoc40 */ +__base_RAM2 = 0x10080000 ; /* RAM2 */ +__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */ +__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */ +__base_RamAHB32 = 0x20000000 ; /* RamAHB32 */ +__base_RAM3 = 0x20000000 ; /* RAM3 */ +__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */ +__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */ +__base_RamAHB16 = 0x20008000 ; /* RamAHB16 */ +__base_RAM4 = 0x20008000 ; /* RAM4 */ +__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */ +__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */ +__base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */ +__base_RAM5 = 0x2000c000 ; /* RAM5 */ +__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */ +__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */ ENTRY(ResetISR) @@ -118,9 +118,9 @@ SECTIONS } > MFlashA512 /* * for exception handling/unwind - some Newlib functions (in common - * with C++ and STDC++) use this. + * with C++ and STDC++) use this. */ - .ARM.extab : ALIGN(4) + .ARM.extab : ALIGN(4) { *(.ARM.extab* .gnu.linkonce.armextab.*) } > MFlashA512 @@ -134,7 +134,7 @@ SECTIONS __exidx_end = .; _etext = .; - + /* DATA section for RamLoc40 */ .data_RAM2 : ALIGN(4) @@ -215,7 +215,7 @@ SECTIONS *(.bss.$RamLoc40*) . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ PROVIDE(__end_bss_RAM2 = .) ; - } > RamLoc40 + } > RamLoc40 /* BSS section for RamAHB32 */ .bss_RAM3 : ALIGN(4) @@ -225,7 +225,7 @@ SECTIONS *(.bss.$RamAHB32*) . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ PROVIDE(__end_bss_RAM3 = .) ; - } > RamAHB32 + } > RamAHB32 /* BSS section for RamAHB16 */ .bss_RAM4 : ALIGN(4) @@ -235,7 +235,7 @@ SECTIONS *(.bss.$RamAHB16*) . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ PROVIDE(__end_bss_RAM4 = .) ; - } > RamAHB16 + } > RamAHB16 /* BSS section for RamAHB_ETB16 */ .bss_RAM5 : ALIGN(4) @@ -245,7 +245,7 @@ SECTIONS *(.bss.$RamAHB_ETB16*) . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ PROVIDE(__end_bss_RAM5 = .) ; - } > RamAHB_ETB16 + } > RamAHB_ETB16 /* MAIN BSS SECTION */ .bss : ALIGN(4) @@ -264,7 +264,7 @@ SECTIONS *(.noinit.$RAM2*) *(.noinit.$RamLoc40*) . = ALIGN(4) ; - } > RamLoc40 + } > RamLoc40 /* NOINIT section for RamAHB32 */ .noinit_RAM3 (NOLOAD) : ALIGN(4) @@ -272,7 +272,7 @@ SECTIONS *(.noinit.$RAM3*) *(.noinit.$RamAHB32*) . = ALIGN(4) ; - } > RamAHB32 + } > RamAHB32 /* NOINIT section for RamAHB16 */ .noinit_RAM4 (NOLOAD) : ALIGN(4) @@ -280,7 +280,7 @@ SECTIONS *(.noinit.$RAM4*) *(.noinit.$RamAHB16*) . = ALIGN(4) ; - } > RamAHB16 + } > RamAHB16 /* NOINIT section for RamAHB_ETB16 */ .noinit_RAM5 (NOLOAD) : ALIGN(4) @@ -288,13 +288,13 @@ SECTIONS *(.noinit.$RAM5*) *(.noinit.$RamAHB_ETB16*) . = ALIGN(4) ; - } > RamAHB_ETB16 + } > RamAHB_ETB16 /* DEFAULT NOINIT SECTION */ .noinit (NOLOAD): ALIGN(4) { _noinit = .; - *(.noinit*) + *(.noinit*) . = ALIGN(4) ; _end_noinit = .; } > RamLoc32 @@ -302,11 +302,11 @@ SECTIONS PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0); /* ## Create checksum value (used in startup) ## */ - PROVIDE(__valid_user_code_checksum = 0 - - (_vStackTop - + (ResetISR + 1) - + (NMI_Handler + 1) - + (HardFault_Handler + 1) + PROVIDE(__valid_user_code_checksum = 0 - + (_vStackTop + + (ResetISR + 1) + + (NMI_Handler + 1) + + (HardFault_Handler + 1) + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */ @@ -320,4 +320,4 @@ SECTIONS _image_start = LOADADDR(.text); _image_end = LOADADDR(.data) + SIZEOF(.data); _image_size = _image_end - _image_start; -} \ No newline at end of file +} diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c index 72c20e034..57f9d55da 100644 --- a/hw/bsp/lpc18/family.c +++ b/hw/bsp/lpc18/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk b/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk index 925374cc8..5f15e2bbe 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk +++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk @@ -15,4 +15,4 @@ PYOCD_TARGET = LPC54628 #flash: flash-pyocd -flash: flash-jlink \ No newline at end of file +flash: flash-jlink diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c index 621788948..fe9cfcc47 100644 --- a/hw/bsp/lpc54/family.c +++ b/hw/bsp/lpc54/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2018, hathach (tinyusb.org) diff --git a/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld b/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld index 6b5d852aa..e2197b972 100644 --- a/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld +++ b/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld @@ -231,4 +231,3 @@ SECTIONS ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") } - diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c index 5b6c56dd3..3ed00e7da 100644 --- a/hw/bsp/lpc55/family.c +++ b/hw/bsp/lpc55/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2018, hathach (tinyusb.org) diff --git a/hw/bsp/lpcxpresso11u37/lpc11u37.ld b/hw/bsp/lpcxpresso11u37/lpc11u37.ld index 6a2dfb7f5..8e0a4e4c6 100644 --- a/hw/bsp/lpcxpresso11u37/lpc11u37.ld +++ b/hw/bsp/lpcxpresso11u37/lpc11u37.ld @@ -12,24 +12,24 @@ MEMORY { /* Define each memory region */ - MFlash128 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K bytes (alias Flash) */ - RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */ - RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */ + MFlash128 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K bytes (alias Flash) */ + RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */ + RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */ } /* Define a symbol for the top of each memory region */ - __base_MFlash128 = 0x0 ; /* MFlash128 */ - __base_Flash = 0x0 ; /* Flash */ - __top_MFlash128 = 0x0 + 0x20000 ; /* 128K bytes */ - __top_Flash = 0x0 + 0x20000 ; /* 128K bytes */ - __base_RamLoc8 = 0x10000000 ; /* RamLoc8 */ - __base_RAM = 0x10000000 ; /* RAM */ - __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */ - __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */ - __base_RamUsb2 = 0x20004000 ; /* RamUsb2 */ - __base_RAM2 = 0x20004000 ; /* RAM2 */ - __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */ - __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */ + __base_MFlash128 = 0x0 ; /* MFlash128 */ + __base_Flash = 0x0 ; /* Flash */ + __top_MFlash128 = 0x0 + 0x20000 ; /* 128K bytes */ + __top_Flash = 0x0 + 0x20000 ; /* 128K bytes */ + __base_RamLoc8 = 0x10000000 ; /* RamLoc8 */ + __base_RAM = 0x10000000 ; /* RAM */ + __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */ + __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */ + __base_RamUsb2 = 0x20004000 ; /* RamUsb2 */ + __base_RAM2 = 0x20004000 ; /* RAM2 */ + __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */ + __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */ ENTRY(ResetISR) @@ -74,9 +74,9 @@ SECTIONS } > MFlash128 /* * for exception handling/unwind - some Newlib functions (in common - * with C++ and STDC++) use this. + * with C++ and STDC++) use this. */ - .ARM.extab : ALIGN(4) + .ARM.extab : ALIGN(4) { *(.ARM.extab* .gnu.linkonce.armextab.*) } > MFlash128 @@ -88,9 +88,9 @@ SECTIONS *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > MFlash128 __exidx_end = .; - + _etext = .; - + /* DATA section for RamUsb2 */ .data_RAM2 : ALIGN(4) @@ -176,11 +176,11 @@ SECTIONS PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0); /* ## Create checksum value (used in startup) ## */ - PROVIDE(__valid_user_code_checksum = 0 - - (_vStackTop - + (ResetISR + 1) - + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1) - + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1) + PROVIDE(__valid_user_code_checksum = 0 - + (_vStackTop + + (ResetISR + 1) + + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1) + + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1) ) ); @@ -192,4 +192,4 @@ SECTIONS _image_start = LOADADDR(.text); _image_end = LOADADDR(.data) + SIZEOF(.data); _image_size = _image_end - _image_start; -} \ No newline at end of file +} diff --git a/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c b/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c index 11f1797a2..79cd685c3 100644 --- a/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c +++ b/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/lpcxpresso11u68/lpc11u68.ld b/hw/bsp/lpcxpresso11u68/lpc11u68.ld index 56d9e4b89..4a35b192e 100644 --- a/hw/bsp/lpcxpresso11u68/lpc11u68.ld +++ b/hw/bsp/lpcxpresso11u68/lpc11u68.ld @@ -11,29 +11,29 @@ MEMORY { /* Define each memory region */ - MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */ - Ram0_32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */ - Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */ - Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */ + MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */ + Ram0_32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */ + Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */ + Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */ } /* Define a symbol for the top of each memory region */ - __base_MFlash256 = 0x0 ; /* MFlash256 */ - __base_Flash = 0x0 ; /* Flash */ - __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */ - __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */ - __base_Ram0_32 = 0x10000000 ; /* Ram0_32 */ - __base_RAM = 0x10000000 ; /* RAM */ - __top_Ram0_32 = 0x10000000 + 0x8000 ; /* 32K bytes */ - __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */ - __base_Ram1_2 = 0x20000000 ; /* Ram1_2 */ - __base_RAM2 = 0x20000000 ; /* RAM2 */ - __top_Ram1_2 = 0x20000000 + 0x800 ; /* 2K bytes */ - __top_RAM2 = 0x20000000 + 0x800 ; /* 2K bytes */ - __base_Ram2USB_2 = 0x20004000 ; /* Ram2USB_2 */ - __base_RAM3 = 0x20004000 ; /* RAM3 */ - __top_Ram2USB_2 = 0x20004000 + 0x800 ; /* 2K bytes */ - __top_RAM3 = 0x20004000 + 0x800 ; /* 2K bytes */ + __base_MFlash256 = 0x0 ; /* MFlash256 */ + __base_Flash = 0x0 ; /* Flash */ + __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */ + __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */ + __base_Ram0_32 = 0x10000000 ; /* Ram0_32 */ + __base_RAM = 0x10000000 ; /* RAM */ + __top_Ram0_32 = 0x10000000 + 0x8000 ; /* 32K bytes */ + __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */ + __base_Ram1_2 = 0x20000000 ; /* Ram1_2 */ + __base_RAM2 = 0x20000000 ; /* RAM2 */ + __top_Ram1_2 = 0x20000000 + 0x800 ; /* 2K bytes */ + __top_RAM2 = 0x20000000 + 0x800 ; /* 2K bytes */ + __base_Ram2USB_2 = 0x20004000 ; /* Ram2USB_2 */ + __base_RAM3 = 0x20004000 ; /* RAM3 */ + __top_Ram2USB_2 = 0x20004000 + 0x800 ; /* 2K bytes */ + __top_RAM3 = 0x20004000 + 0x800 ; /* 2K bytes */ ENTRY(ResetISR) @@ -82,9 +82,9 @@ SECTIONS } > MFlash256 /* * for exception handling/unwind - some Newlib functions (in common - * with C++ and STDC++) use this. + * with C++ and STDC++) use this. */ - .ARM.extab : ALIGN(4) + .ARM.extab : ALIGN(4) { *(.ARM.extab* .gnu.linkonce.armextab.*) } > MFlash256 @@ -98,7 +98,7 @@ SECTIONS __exidx_end = .; _etext = .; - + /* possible MTB section for Ram1_2 */ .mtb_buffer_RAM2 (NOLOAD) : { @@ -172,7 +172,7 @@ SECTIONS *(.bss.$Ram1_2*) . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ PROVIDE(__end_bss_RAM2 = .) ; - } > Ram1_2 + } > Ram1_2 /* BSS section for Ram2USB_2 */ .bss_RAM3 : ALIGN(4) @@ -182,7 +182,7 @@ SECTIONS *(.bss.$Ram2USB_2*) . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ PROVIDE(__end_bss_RAM3 = .) ; - } > Ram2USB_2 + } > Ram2USB_2 /* MAIN BSS SECTION */ .bss : ALIGN(4) @@ -201,7 +201,7 @@ SECTIONS *(.noinit.$RAM2*) *(.noinit.$Ram1_2*) . = ALIGN(4) ; - } > Ram1_2 + } > Ram1_2 /* NOINIT section for Ram2USB_2 */ .noinit_RAM3 (NOLOAD) : ALIGN(4) @@ -209,13 +209,13 @@ SECTIONS *(.noinit.$RAM3*) *(.noinit.$Ram2USB_2*) . = ALIGN(4) ; - } > Ram2USB_2 + } > Ram2USB_2 /* DEFAULT NOINIT SECTION */ .noinit (NOLOAD): ALIGN(4) { _noinit = .; - *(.noinit*) + *(.noinit*) . = ALIGN(4) ; _end_noinit = .; } > Ram0_32 @@ -223,11 +223,11 @@ SECTIONS PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_Ram0_32 - 0); /* ## Create checksum value (used in startup) ## */ - PROVIDE(__valid_user_code_checksum = 0 - - (_vStackTop - + (ResetISR + 1) - + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1) - + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1) + PROVIDE(__valid_user_code_checksum = 0 - + (_vStackTop + + (ResetISR + 1) + + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1) + + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1) ) ); @@ -239,4 +239,4 @@ SECTIONS _image_start = LOADADDR(.text); _image_end = LOADADDR(.data) + SIZEOF(.data); _image_size = _image_end - _image_start; -} \ No newline at end of file +} diff --git a/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c b/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c index e33a5c6e5..a04e43867 100644 --- a/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c +++ b/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/lpcxpresso1347/lpc1347.ld b/hw/bsp/lpcxpresso1347/lpc1347.ld index 42a4bb25c..a2111cd1c 100644 --- a/hw/bsp/lpcxpresso1347/lpc1347.ld +++ b/hw/bsp/lpcxpresso1347/lpc1347.ld @@ -11,29 +11,29 @@ MEMORY { /* Define each memory region */ - MFlash64 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K bytes (alias Flash) */ - RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */ - RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */ - RamPeriph2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */ + MFlash64 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K bytes (alias Flash) */ + RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */ + RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */ + RamPeriph2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */ } /* Define a symbol for the top of each memory region */ - __base_MFlash64 = 0x0 ; /* MFlash64 */ - __base_Flash = 0x0 ; /* Flash */ - __top_MFlash64 = 0x0 + 0x10000 ; /* 64K bytes */ - __top_Flash = 0x0 + 0x10000 ; /* 64K bytes */ - __base_RamLoc8 = 0x10000000 ; /* RamLoc8 */ - __base_RAM = 0x10000000 ; /* RAM */ - __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */ - __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */ - __base_RamUsb2 = 0x20004000 ; /* RamUsb2 */ - __base_RAM2 = 0x20004000 ; /* RAM2 */ - __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */ - __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */ - __base_RamPeriph2 = 0x20000000 ; /* RamPeriph2 */ - __base_RAM3 = 0x20000000 ; /* RAM3 */ - __top_RamPeriph2 = 0x20000000 + 0x800 ; /* 2K bytes */ - __top_RAM3 = 0x20000000 + 0x800 ; /* 2K bytes */ + __base_MFlash64 = 0x0 ; /* MFlash64 */ + __base_Flash = 0x0 ; /* Flash */ + __top_MFlash64 = 0x0 + 0x10000 ; /* 64K bytes */ + __top_Flash = 0x0 + 0x10000 ; /* 64K bytes */ + __base_RamLoc8 = 0x10000000 ; /* RamLoc8 */ + __base_RAM = 0x10000000 ; /* RAM */ + __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */ + __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */ + __base_RamUsb2 = 0x20004000 ; /* RamUsb2 */ + __base_RAM2 = 0x20004000 ; /* RAM2 */ + __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */ + __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */ + __base_RamPeriph2 = 0x20000000 ; /* RamPeriph2 */ + __base_RAM3 = 0x20000000 ; /* RAM3 */ + __top_RamPeriph2 = 0x20000000 + 0x800 ; /* 2K bytes */ + __top_RAM3 = 0x20000000 + 0x800 ; /* 2K bytes */ ENTRY(ResetISR) @@ -82,9 +82,9 @@ SECTIONS } > MFlash64 /* * for exception handling/unwind - some Newlib functions (in common - * with C++ and STDC++) use this. + * with C++ and STDC++) use this. */ - .ARM.extab : ALIGN(4) + .ARM.extab : ALIGN(4) { *(.ARM.extab* .gnu.linkonce.armextab.*) } > MFlash64 @@ -98,7 +98,7 @@ SECTIONS __exidx_end = .; _etext = .; - + /* DATA section for RamUsb2 */ .data_RAM2 : ALIGN(4) @@ -153,7 +153,7 @@ SECTIONS *(.bss.$RamUsb2*) . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ PROVIDE(__end_bss_RAM2 = .) ; - } > RamUsb2 + } > RamUsb2 /* BSS section for RamPeriph2 */ .bss_RAM3 : ALIGN(4) @@ -163,7 +163,7 @@ SECTIONS *(.bss.$RamPeriph2*) . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ PROVIDE(__end_bss_RAM3 = .) ; - } > RamPeriph2 + } > RamPeriph2 /* MAIN BSS SECTION */ .bss : ALIGN(4) @@ -182,7 +182,7 @@ SECTIONS *(.noinit.$RAM2*) *(.noinit.$RamUsb2*) . = ALIGN(4) ; - } > RamUsb2 + } > RamUsb2 /* NOINIT section for RamPeriph2 */ .noinit_RAM3 (NOLOAD) : ALIGN(4) @@ -190,13 +190,13 @@ SECTIONS *(.noinit.$RAM3*) *(.noinit.$RamPeriph2*) . = ALIGN(4) ; - } > RamPeriph2 + } > RamPeriph2 /* DEFAULT NOINIT SECTION */ .noinit (NOLOAD): ALIGN(4) { _noinit = .; - *(.noinit*) + *(.noinit*) . = ALIGN(4) ; _end_noinit = .; } > RamLoc8 @@ -204,11 +204,11 @@ SECTIONS PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0); /* ## Create checksum value (used in startup) ## */ - PROVIDE(__valid_user_code_checksum = 0 - - (_vStackTop - + (ResetISR + 1) - + (NMI_Handler + 1) - + (HardFault_Handler + 1) + PROVIDE(__valid_user_code_checksum = 0 - + (_vStackTop + + (ResetISR + 1) + + (NMI_Handler + 1) + + (HardFault_Handler + 1) + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */ @@ -222,4 +222,4 @@ SECTIONS _image_start = LOADADDR(.text); _image_end = LOADADDR(.data) + SIZEOF(.data); _image_size = _image_end - _image_start; -} \ No newline at end of file +} diff --git a/hw/bsp/lpcxpresso1347/lpcxpresso1347.c b/hw/bsp/lpcxpresso1347/lpcxpresso1347.c index a9a67ae3a..8ee611037 100644 --- a/hw/bsp/lpcxpresso1347/lpcxpresso1347.c +++ b/hw/bsp/lpcxpresso1347/lpcxpresso1347.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -64,7 +64,7 @@ const uint32_t ExtRateIn = 0; /* Pin muxing table, only items that need changing from their default pin state are in this table. */ -static const PINMUX_GRP_T pinmuxing[] = +static const PINMUX_GRP_T pinmuxing[] = { {0, 1, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_1 used for CLKOUT */ {0, 2, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_PULLUP)}, /* PIO0_2 used for SSEL */ diff --git a/hw/bsp/lpcxpresso1769/lpc1769.ld b/hw/bsp/lpcxpresso1769/lpc1769.ld index d1c83d8e2..095bd3d92 100644 --- a/hw/bsp/lpcxpresso1769/lpc1769.ld +++ b/hw/bsp/lpcxpresso1769/lpc1769.ld @@ -11,24 +11,24 @@ MEMORY { /* Define each memory region */ - MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */ - RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */ - RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */ + MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */ + RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */ + RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */ } /* Define a symbol for the top of each memory region */ - __base_MFlash512 = 0x0 ; /* MFlash512 */ - __base_Flash = 0x0 ; /* Flash */ - __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */ - __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */ - __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */ - __base_RAM = 0x10000000 ; /* RAM */ - __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */ - __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */ - __base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */ - __base_RAM2 = 0x2007c000 ; /* RAM2 */ - __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */ - __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */ + __base_MFlash512 = 0x0 ; /* MFlash512 */ + __base_Flash = 0x0 ; /* Flash */ + __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */ + __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */ + __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */ + __base_RAM = 0x10000000 ; /* RAM */ + __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */ + __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */ + __base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */ + __base_RAM2 = 0x2007c000 ; /* RAM2 */ + __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */ + __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */ ENTRY(ResetISR) @@ -72,9 +72,9 @@ SECTIONS } > MFlash512 /* * for exception handling/unwind - some Newlib functions (in common - * with C++ and STDC++) use this. + * with C++ and STDC++) use this. */ - .ARM.extab : ALIGN(4) + .ARM.extab : ALIGN(4) { *(.ARM.extab* .gnu.linkonce.armextab.*) } > MFlash512 @@ -88,7 +88,7 @@ SECTIONS __exidx_end = .; _etext = .; - + /* DATA section for RamAHB32 */ .data_RAM2 : ALIGN(4) @@ -130,7 +130,7 @@ SECTIONS *(.bss.$RamAHB32*) . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ PROVIDE(__end_bss_RAM2 = .) ; - } > RamAHB32 + } > RamAHB32 /* MAIN BSS SECTION */ .bss : ALIGN(4) @@ -149,13 +149,13 @@ SECTIONS *(.noinit.$RAM2*) *(.noinit.$RamAHB32*) . = ALIGN(4) ; - } > RamAHB32 + } > RamAHB32 /* DEFAULT NOINIT SECTION */ .noinit (NOLOAD): ALIGN(4) { _noinit = .; - *(.noinit*) + *(.noinit*) . = ALIGN(4) ; _end_noinit = .; } > RamLoc32 @@ -163,11 +163,11 @@ SECTIONS PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0); /* ## Create checksum value (used in startup) ## */ - PROVIDE(__valid_user_code_checksum = 0 - - (_vStackTop - + (ResetISR + 1) - + (NMI_Handler + 1) - + (HardFault_Handler + 1) + PROVIDE(__valid_user_code_checksum = 0 - + (_vStackTop + + (ResetISR + 1) + + (NMI_Handler + 1) + + (HardFault_Handler + 1) + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */ @@ -181,4 +181,4 @@ SECTIONS _image_start = LOADADDR(.text); _image_end = LOADADDR(.data) + SIZEOF(.data); _image_size = _image_end - _image_start; -} \ No newline at end of file +} diff --git a/hw/bsp/lpcxpresso1769/lpcxpresso1769.c b/hw/bsp/lpcxpresso1769/lpcxpresso1769.c index b7bce93d2..24333ad1a 100644 --- a/hw/bsp/lpcxpresso1769/lpcxpresso1769.c +++ b/hw/bsp/lpcxpresso1769/lpcxpresso1769.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c b/hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c index 6bade7743..c94b0d6d8 100644 --- a/hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c +++ b/hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2018, hathach (tinyusb.org) diff --git a/hw/bsp/mbed1768/lpc1768.ld b/hw/bsp/mbed1768/lpc1768.ld index d1c83d8e2..095bd3d92 100644 --- a/hw/bsp/mbed1768/lpc1768.ld +++ b/hw/bsp/mbed1768/lpc1768.ld @@ -11,24 +11,24 @@ MEMORY { /* Define each memory region */ - MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */ - RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */ - RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */ + MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */ + RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */ + RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */ } /* Define a symbol for the top of each memory region */ - __base_MFlash512 = 0x0 ; /* MFlash512 */ - __base_Flash = 0x0 ; /* Flash */ - __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */ - __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */ - __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */ - __base_RAM = 0x10000000 ; /* RAM */ - __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */ - __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */ - __base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */ - __base_RAM2 = 0x2007c000 ; /* RAM2 */ - __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */ - __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */ + __base_MFlash512 = 0x0 ; /* MFlash512 */ + __base_Flash = 0x0 ; /* Flash */ + __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */ + __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */ + __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */ + __base_RAM = 0x10000000 ; /* RAM */ + __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */ + __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */ + __base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */ + __base_RAM2 = 0x2007c000 ; /* RAM2 */ + __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */ + __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */ ENTRY(ResetISR) @@ -72,9 +72,9 @@ SECTIONS } > MFlash512 /* * for exception handling/unwind - some Newlib functions (in common - * with C++ and STDC++) use this. + * with C++ and STDC++) use this. */ - .ARM.extab : ALIGN(4) + .ARM.extab : ALIGN(4) { *(.ARM.extab* .gnu.linkonce.armextab.*) } > MFlash512 @@ -88,7 +88,7 @@ SECTIONS __exidx_end = .; _etext = .; - + /* DATA section for RamAHB32 */ .data_RAM2 : ALIGN(4) @@ -130,7 +130,7 @@ SECTIONS *(.bss.$RamAHB32*) . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ PROVIDE(__end_bss_RAM2 = .) ; - } > RamAHB32 + } > RamAHB32 /* MAIN BSS SECTION */ .bss : ALIGN(4) @@ -149,13 +149,13 @@ SECTIONS *(.noinit.$RAM2*) *(.noinit.$RamAHB32*) . = ALIGN(4) ; - } > RamAHB32 + } > RamAHB32 /* DEFAULT NOINIT SECTION */ .noinit (NOLOAD): ALIGN(4) { _noinit = .; - *(.noinit*) + *(.noinit*) . = ALIGN(4) ; _end_noinit = .; } > RamLoc32 @@ -163,11 +163,11 @@ SECTIONS PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0); /* ## Create checksum value (used in startup) ## */ - PROVIDE(__valid_user_code_checksum = 0 - - (_vStackTop - + (ResetISR + 1) - + (NMI_Handler + 1) - + (HardFault_Handler + 1) + PROVIDE(__valid_user_code_checksum = 0 - + (_vStackTop + + (ResetISR + 1) + + (NMI_Handler + 1) + + (HardFault_Handler + 1) + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */ @@ -181,4 +181,4 @@ SECTIONS _image_start = LOADADDR(.text); _image_end = LOADADDR(.data) + SIZEOF(.data); _image_size = _image_end - _image_start; -} \ No newline at end of file +} diff --git a/hw/bsp/mbed1768/mbed1768.c b/hw/bsp/mbed1768/mbed1768.c index 08cf3adbd..9f3d294d3 100644 --- a/hw/bsp/mbed1768/mbed1768.c +++ b/hw/bsp/mbed1768/mbed1768.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld index 0b45ee7bd..796ed04f6 100644 --- a/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld +++ b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 MM32 SE TEAM @@ -110,7 +110,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -121,7 +121,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -149,7 +149,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c index 9793ba241..c3f5bc16d 100644 --- a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c +++ b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 MM32 SE TEAM @@ -57,7 +57,7 @@ const int baudrate = 115200; void board_init (void) { -// usb clock +// usb clock USB_DeviceClockInit(); if ( SysTick_Config(SystemCoreClock / 1000) ) diff --git a/hw/bsp/ngx4330/ngx4330.c b/hw/bsp/ngx4330/ngx4330.c index 4fc314165..d61f775c7 100644 --- a/hw/bsp/ngx4330/ngx4330.c +++ b/hw/bsp/ngx4330/ngx4330.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/ngx4330/ngx4330.ld b/hw/bsp/ngx4330/ngx4330.ld index 7bd363f08..300869c20 100644 --- a/hw/bsp/ngx4330/ngx4330.ld +++ b/hw/bsp/ngx4330/ngx4330.ld @@ -12,39 +12,39 @@ MEMORY { /* Define each memory region */ - RamLoc128 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000 /* 128K bytes (alias RAM) */ - RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes (alias RAM2) */ - RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */ - RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */ - RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */ - SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 0x400000 /* 4M bytes (alias Flash) */ + RamLoc128 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000 /* 128K bytes (alias RAM) */ + RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes (alias RAM2) */ + RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */ + RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */ + RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */ + SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 0x400000 /* 4M bytes (alias Flash) */ } /* Define a symbol for the top of each memory region */ - __base_RamLoc128 = 0x10000000 ; /* RamLoc128 */ - __base_RAM = 0x10000000 ; /* RAM */ - __top_RamLoc128 = 0x10000000 + 0x20000 ; /* 128K bytes */ - __top_RAM = 0x10000000 + 0x20000 ; /* 128K bytes */ - __base_RamLoc72 = 0x10080000 ; /* RamLoc72 */ - __base_RAM2 = 0x10080000 ; /* RAM2 */ - __top_RamLoc72 = 0x10080000 + 0x12000 ; /* 72K bytes */ - __top_RAM2 = 0x10080000 + 0x12000 ; /* 72K bytes */ - __base_RamAHB32 = 0x20000000 ; /* RamAHB32 */ - __base_RAM3 = 0x20000000 ; /* RAM3 */ - __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */ - __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */ - __base_RamAHB16 = 0x20008000 ; /* RamAHB16 */ - __base_RAM4 = 0x20008000 ; /* RAM4 */ - __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */ - __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */ - __base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */ - __base_RAM5 = 0x2000c000 ; /* RAM5 */ - __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */ - __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */ - __base_SPIFI = 0x14000000 ; /* SPIFI */ - __base_Flash = 0x14000000 ; /* Flash */ - __top_SPIFI = 0x14000000 + 0x400000 ; /* 4M bytes */ - __top_Flash = 0x14000000 + 0x400000 ; /* 4M bytes */ + __base_RamLoc128 = 0x10000000 ; /* RamLoc128 */ + __base_RAM = 0x10000000 ; /* RAM */ + __top_RamLoc128 = 0x10000000 + 0x20000 ; /* 128K bytes */ + __top_RAM = 0x10000000 + 0x20000 ; /* 128K bytes */ + __base_RamLoc72 = 0x10080000 ; /* RamLoc72 */ + __base_RAM2 = 0x10080000 ; /* RAM2 */ + __top_RamLoc72 = 0x10080000 + 0x12000 ; /* 72K bytes */ + __top_RAM2 = 0x10080000 + 0x12000 ; /* 72K bytes */ + __base_RamAHB32 = 0x20000000 ; /* RamAHB32 */ + __base_RAM3 = 0x20000000 ; /* RAM3 */ + __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */ + __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */ + __base_RamAHB16 = 0x20008000 ; /* RamAHB16 */ + __base_RAM4 = 0x20008000 ; /* RAM4 */ + __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */ + __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */ + __base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */ + __base_RAM5 = 0x2000c000 ; /* RAM5 */ + __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */ + __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */ + __base_SPIFI = 0x14000000 ; /* SPIFI */ + __base_Flash = 0x14000000 ; /* Flash */ + __top_SPIFI = 0x14000000 + 0x400000 ; /* 4M bytes */ + __top_Flash = 0x14000000 + 0x400000 ; /* 4M bytes */ ENTRY(ResetISR) @@ -103,9 +103,9 @@ SECTIONS } > SPIFI /* * for exception handling/unwind - some Newlib functions (in common - * with C++ and STDC++) use this. + * with C++ and STDC++) use this. */ - .ARM.extab : ALIGN(4) + .ARM.extab : ALIGN(4) { *(.ARM.extab* .gnu.linkonce.armextab.*) } > SPIFI @@ -117,9 +117,9 @@ SECTIONS *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > SPIFI __exidx_end = .; - + _etext = .; - + /* DATA section for RamLoc72 */ .data_RAM2 : ALIGN(4) @@ -322,11 +322,11 @@ SECTIONS PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc128 - 0); /* ## Create checksum value (used in startup) ## */ - PROVIDE(__valid_user_code_checksum = 0 - - (_vStackTop - + (ResetISR + 1) - + (NMI_Handler + 1) - + (HardFault_Handler + 1) + PROVIDE(__valid_user_code_checksum = 0 - + (_vStackTop + + (ResetISR + 1) + + (NMI_Handler + 1) + + (HardFault_Handler + 1) + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */ @@ -340,4 +340,4 @@ SECTIONS _image_start = LOADADDR(.text); _image_end = LOADADDR(.data) + SIZEOF(.data); _image_size = _image_end - _image_start; -} \ No newline at end of file +} diff --git a/hw/bsp/nrf/boards/adafruit_clue/board.h b/hw/bsp/nrf/boards/adafruit_clue/board.h index 2c58e8fe8..8d6df786e 100644 --- a/hw/bsp/nrf/boards/adafruit_clue/board.h +++ b/hw/bsp/nrf/boards/adafruit_clue/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld index 5314a4e93..71c55bb81 100755 --- a/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld +++ b/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld @@ -13,7 +13,7 @@ MEMORY * - Max ATT MTU * - Concurrent connection peripheral + central + secure links * - Event Len, HVN queue, Write CMD queue - */ + */ RAM (rwx) : ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400 } @@ -26,7 +26,7 @@ SECTIONS KEEP(*(.svc_data)) PROVIDE(__stop_svc_data = .); } > RAM - + .fs_data : { PROVIDE(__start_fs_data = .); diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld b/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld index f570740b6..f609f743f 100755 --- a/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld +++ b/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld @@ -20,7 +20,7 @@ SECTIONS KEEP(*(.svc_data)) PROVIDE(__stop_svc_data = .); } > RAM - + .fs_data : { PROVIDE(__start_fs_data = .); diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/board.h b/hw/bsp/nrf/boards/arduino_nano33_ble/board.h index d548e01c3..00fa8d8ea 100644 --- a/hw/bsp/nrf/boards/arduino_nano33_ble/board.h +++ b/hw/bsp/nrf/boards/arduino_nano33_ble/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h index a86c9dc7f..3dd354efa 100644 --- a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h +++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld index 5314a4e93..71c55bb81 100755 --- a/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld +++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld @@ -13,7 +13,7 @@ MEMORY * - Max ATT MTU * - Concurrent connection peripheral + central + secure links * - Event Len, HVN queue, Write CMD queue - */ + */ RAM (rwx) : ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400 } @@ -26,7 +26,7 @@ SECTIONS KEEP(*(.svc_data)) PROVIDE(__stop_svc_data = .); } > RAM - + .fs_data : { PROVIDE(__start_fs_data = .); diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h index 3208a948a..8e6ce3230 100644 --- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h +++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld index 5314a4e93..71c55bb81 100644 --- a/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld +++ b/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld @@ -13,7 +13,7 @@ MEMORY * - Max ATT MTU * - Concurrent connection peripheral + central + secure links * - Event Len, HVN queue, Write CMD queue - */ + */ RAM (rwx) : ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400 } @@ -26,7 +26,7 @@ SECTIONS KEEP(*(.svc_data)) PROVIDE(__stop_svc_data = .); } > RAM - + .fs_data : { PROVIDE(__start_fs_data = .); diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h index ece6e34cb..605deea24 100644 --- a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h +++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld index 5314a4e93..71c55bb81 100644 --- a/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld +++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld @@ -13,7 +13,7 @@ MEMORY * - Max ATT MTU * - Concurrent connection peripheral + central + secure links * - Event Len, HVN queue, Write CMD queue - */ + */ RAM (rwx) : ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400 } @@ -26,7 +26,7 @@ SECTIONS KEEP(*(.svc_data)) PROVIDE(__stop_svc_data = .); } > RAM - + .fs_data : { PROVIDE(__start_fs_data = .); diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h index 132173a80..33c370f53 100644 --- a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h +++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld index 5314a4e93..71c55bb81 100644 --- a/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld +++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld @@ -13,7 +13,7 @@ MEMORY * - Max ATT MTU * - Concurrent connection peripheral + central + secure links * - Event Len, HVN queue, Write CMD queue - */ + */ RAM (rwx) : ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400 } @@ -26,7 +26,7 @@ SECTIONS KEEP(*(.svc_data)) PROVIDE(__stop_svc_data = .); } > RAM - + .fs_data : { PROVIDE(__start_fs_data = .); diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h index 01dd1f24f..072cb2714 100644 --- a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h +++ b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk index 3afa234aa..f25ec8f34 100644 --- a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk +++ b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk @@ -12,4 +12,4 @@ $(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex flash: $(BUILD)/$(PROJECT).zip @:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0) - $(NRFUTIL) dfu usb-serial --package $^ -p $(SERIAL) -b 115200 \ No newline at end of file + $(NRFUTIL) dfu usb-serial --package $^ -p $(SERIAL) -b 115200 diff --git a/hw/bsp/nrf/boards/pca10056/board.h b/hw/bsp/nrf/boards/pca10056/board.h index ab12d21aa..50d3067b3 100644 --- a/hw/bsp/nrf/boards/pca10056/board.h +++ b/hw/bsp/nrf/boards/pca10056/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/nrf/boards/pca10059/board.h b/hw/bsp/nrf/boards/pca10059/board.h index 0810be648..ea3f4030d 100644 --- a/hw/bsp/nrf/boards/pca10059/board.h +++ b/hw/bsp/nrf/boards/pca10059/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/nrf/boards/pca10100/board.h b/hw/bsp/nrf/boards/pca10100/board.h index 881133035..2b2579732 100644 --- a/hw/bsp/nrf/boards/pca10100/board.h +++ b/hw/bsp/nrf/boards/pca10100/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h index dcf829d9c..bc203f073 100644 --- a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h +++ b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index a07332d4c..02cec31ef 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/nutiny_nuc121s/nuc121_flash.ld b/hw/bsp/nutiny_nuc121s/nuc121_flash.ld index 3966b276e..0c599a561 100644 --- a/hw/bsp/nutiny_nuc121s/nuc121_flash.ld +++ b/hw/bsp/nutiny_nuc121s/nuc121_flash.ld @@ -69,7 +69,7 @@ SECTIONS *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) - + *(.rodata*) KEEP(*(.eh_frame*)) diff --git a/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c b/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c index 7117a3422..ec66f8deb 100644 --- a/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c +++ b/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/nutiny_nuc125s/nuc125_flash.ld b/hw/bsp/nutiny_nuc125s/nuc125_flash.ld index 3966b276e..0c599a561 100644 --- a/hw/bsp/nutiny_nuc125s/nuc125_flash.ld +++ b/hw/bsp/nutiny_nuc125s/nuc125_flash.ld @@ -69,7 +69,7 @@ SECTIONS *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) - + *(.rodata*) KEEP(*(.eh_frame*)) diff --git a/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c b/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c index 7117a3422..ec66f8deb 100644 --- a/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c +++ b/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c b/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c index da62e7bd2..90fa2ffd8 100644 --- a/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c +++ b/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c b/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c index 0d78116b8..9e7eacb23 100644 --- a/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c +++ b/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c b/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c index 49e66d2d0..1fc97e3dc 100644 --- a/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c +++ b/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c b/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c index e47ec5f31..0bb6cb728 100644 --- a/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c +++ b/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2022 Jerzy Kasenberg diff --git a/hw/bsp/pic32mz/family.c b/hw/bsp/pic32mz/family.c index 786f04978..895e23899 100644 --- a/hw/bsp/pic32mz/family.c +++ b/hw/bsp/pic32mz/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2022 Jerzy Kasenberg diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h index e7eab088e..1eeeaf9af 100644 --- a/hw/bsp/rp2040/board.h +++ b/hw/bsp/rp2040/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021, Ha Thach (tinyusb.org) diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake index 8280c835d..f9887c09c 100644 --- a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake @@ -1 +1 @@ -set(PICO_BOARD pico) \ No newline at end of file +set(PICO_BOARD pico) diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index 678bce274..5d80ab66e 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -55,7 +55,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker) message("Compiling TinyUSB with CFG_TUSB_DEBUG=1") set(TINYUSB_DEBUG_LEVEL 1) endif() - + target_compile_definitions(tinyusb_common_base INTERFACE CFG_TUSB_MCU=OPT_MCU_RP2040 CFG_TUSB_OS=${TINYUSB_OPT_OS} diff --git a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c index 9bd9399f6..4f87153ac 100644 --- a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c +++ b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c @@ -33,9 +33,9 @@ * - Short EMLE pad and 3.3V(GR-CITRUS pin name) with a wire. * * The pads are [the back side of GR-CITRUS](https://www.slideshare.net/MinaoYamamoto/grcitrusrx631/2). - * + * * Connect the pins between GR-CITRUS and JLink as follows. - * + * * | Function | GR-CITRUS pin | JLink pin No.| note | * |:---------:|:-------------:|:------------:|:--------:| * | VTref | 3.3V | 1 | | @@ -91,7 +91,7 @@ void INT_Excep_SCI0_TXI0(void) { uint8_t *buf = sci0_buf[0].buf; uint32_t cnt = sci0_buf[0].cnt; - + if (!buf || !cnt) { SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE); return; diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c index 3c729ad50..691038fc8 100644 --- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c +++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c @@ -126,7 +126,7 @@ void INT_Excep_SCI5_TXI5(void) { uint8_t *buf = sci_buf[0].buf; uint32_t cnt = sci_buf[0].cnt; - + if (!buf || !cnt) { SCI5.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE); return; diff --git a/hw/bsp/samd11/boards/samd11_xplained/samd11d14am_flash.ld b/hw/bsp/samd11/boards/samd11_xplained/samd11d14am_flash.ld index 8b3124c0e..9e12acec8 100644 --- a/hw/bsp/samd11/boards/samd11_xplained/samd11d14am_flash.ld +++ b/hw/bsp/samd11/boards/samd11_xplained/samd11d14am_flash.ld @@ -14,9 +14,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/hw/bsp/samd21/boards/atsamd21_xpro/board.h b/hw/bsp/samd21/boards/atsamd21_xpro/board.h index a3e03997c..315e40c78 100644 --- a/hw/bsp/samd21/boards/atsamd21_xpro/board.h +++ b/hw/bsp/samd21/boards/atsamd21_xpro/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/samd21/boards/circuitplayground_express/board.h b/hw/bsp/samd21/boards/circuitplayground_express/board.h index 2d7da1c0b..0037db00d 100644 --- a/hw/bsp/samd21/boards/circuitplayground_express/board.h +++ b/hw/bsp/samd21/boards/circuitplayground_express/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/samd21/boards/curiosity_nano/board.h b/hw/bsp/samd21/boards/curiosity_nano/board.h index 67924d809..1a4a833a3 100644 --- a/hw/bsp/samd21/boards/curiosity_nano/board.h +++ b/hw/bsp/samd21/boards/curiosity_nano/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/samd21/boards/feather_m0_express/board.h b/hw/bsp/samd21/boards/feather_m0_express/board.h index b9292b9af..8e0caa6bd 100644 --- a/hw/bsp/samd21/boards/feather_m0_express/board.h +++ b/hw/bsp/samd21/boards/feather_m0_express/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/samd21/boards/itsybitsy_m0/board.h b/hw/bsp/samd21/boards/itsybitsy_m0/board.h index 177fb695e..6ee814da5 100644 --- a/hw/bsp/samd21/boards/itsybitsy_m0/board.h +++ b/hw/bsp/samd21/boards/itsybitsy_m0/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/samd21/boards/luna_d21/board.h b/hw/bsp/samd21/boards/luna_d21/board.h index 2e0a2a60f..776063636 100644 --- a/hw/bsp/samd21/boards/luna_d21/board.h +++ b/hw/bsp/samd21/boards/luna_d21/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021, Ha Thach (tinyusb.org) diff --git a/hw/bsp/samd21/boards/luna_d21/board.mk b/hw/bsp/samd21/boards/luna_d21/board.mk index 27a634e3a..508a72b1f 100644 --- a/hw/bsp/samd21/boards/luna_d21/board.mk +++ b/hw/bsp/samd21/boards/luna_d21/board.mk @@ -8,4 +8,3 @@ JLINK_DEVICE = ATSAMD21G18 # flash using dfu-util flash: $(BUILD)/$(PROJECT).bin dfu-util -a 0 -d 1d50:615c -D $< || dfu-util -a 0 -d 16d0:05a5 -D $< - diff --git a/hw/bsp/samd21/boards/metro_m0_express/board.h b/hw/bsp/samd21/boards/metro_m0_express/board.h index 13b7556b0..d26aae53c 100644 --- a/hw/bsp/samd21/boards/metro_m0_express/board.h +++ b/hw/bsp/samd21/boards/metro_m0_express/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/samd21/boards/qtpy/board.h b/hw/bsp/samd21/boards/qtpy/board.h index 6f8325e49..9ba39e966 100644 --- a/hw/bsp/samd21/boards/qtpy/board.h +++ b/hw/bsp/samd21/boards/qtpy/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/samd21/boards/seeeduino_xiao/board.h b/hw/bsp/samd21/boards/seeeduino_xiao/board.h index 0d1e9cef1..1bd63d6d9 100644 --- a/hw/bsp/samd21/boards/seeeduino_xiao/board.h +++ b/hw/bsp/samd21/boards/seeeduino_xiao/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/samd21/boards/trinket_m0/board.h b/hw/bsp/samd21/boards/trinket_m0/board.h index c8692e6bd..741f2a7f3 100644 --- a/hw/bsp/samd21/boards/trinket_m0/board.h +++ b/hw/bsp/samd21/boards/trinket_m0/board.h @@ -31,4 +31,3 @@ // UART #define UART_SERCOM 0 - diff --git a/hw/bsp/samd21/boards/trinket_m0/board.mk b/hw/bsp/samd21/boards/trinket_m0/board.mk index 803ffe892..6addf13b7 100644 --- a/hw/bsp/samd21/boards/trinket_m0/board.mk +++ b/hw/bsp/samd21/boards/trinket_m0/board.mk @@ -2,4 +2,3 @@ CFLAGS += -D__SAMD21E18A__ -DCFG_EXAMPLE_VIDEO_READONLY # All source paths should be relative to the top level. LD_FILE = $(BOARD_PATH)/trinket_m0.ld - diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c index 494dc393a..308fb51b5 100644 --- a/hw/bsp/samd21/family.c +++ b/hw/bsp/samd21/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/samd51/boards/feather_m4_express/board.h b/hw/bsp/samd51/boards/feather_m4_express/board.h index 1d5ed8040..4629643fd 100644 --- a/hw/bsp/samd51/boards/feather_m4_express/board.h +++ b/hw/bsp/samd51/boards/feather_m4_express/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/samd51/boards/itsybitsy_m4/board.h b/hw/bsp/samd51/boards/itsybitsy_m4/board.h index 0760d4288..272315771 100644 --- a/hw/bsp/samd51/boards/itsybitsy_m4/board.h +++ b/hw/bsp/samd51/boards/itsybitsy_m4/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.h b/hw/bsp/samd51/boards/metro_m4_express/board.h index ab10ae4f8..5d7734576 100644 --- a/hw/bsp/samd51/boards/metro_m4_express/board.h +++ b/hw/bsp/samd51/boards/metro_m4_express/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.mk b/hw/bsp/samd51/boards/metro_m4_express/board.mk index d7953cc24..57a680e91 100644 --- a/hw/bsp/samd51/boards/metro_m4_express/board.mk +++ b/hw/bsp/samd51/boards/metro_m4_express/board.mk @@ -7,4 +7,3 @@ LD_FILE = $(BOARD_PATH)/$(BOARD).ld JLINK_DEVICE = ATSAMD51J19 flash: flash-bossac - diff --git a/hw/bsp/samd51/boards/pybadge/board.h b/hw/bsp/samd51/boards/pybadge/board.h index 1d5ed8040..4629643fd 100644 --- a/hw/bsp/samd51/boards/pybadge/board.h +++ b/hw/bsp/samd51/boards/pybadge/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/samd51/boards/pyportal/board.h b/hw/bsp/samd51/boards/pyportal/board.h index 9e51ded32..ff04c900b 100644 --- a/hw/bsp/samd51/boards/pyportal/board.h +++ b/hw/bsp/samd51/boards/pyportal/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c index 020e638c4..3da89ee14 100644 --- a/hw/bsp/samd51/family.c +++ b/hw/bsp/samd51/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/same54xplainedpro/same54p20a_flash.ld b/hw/bsp/same54xplainedpro/same54p20a_flash.ld index 97072bfe6..1f427a066 100644 --- a/hw/bsp/same54xplainedpro/same54p20a_flash.ld +++ b/hw/bsp/same54xplainedpro/same54p20a_flash.ld @@ -14,9 +14,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/hw/bsp/same54xplainedpro/same54p20a_sram.ld b/hw/bsp/same54xplainedpro/same54p20a_sram.ld index 6219f4afe..e6e33ec48 100644 --- a/hw/bsp/same54xplainedpro/same54p20a_sram.ld +++ b/hw/bsp/same54xplainedpro/same54p20a_sram.ld @@ -14,9 +14,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/hw/bsp/samg55xplained/samg55xplained.c b/hw/bsp/samg55xplained/samg55xplained.c index 027c88e2f..6e1ed56a9 100644 --- a/hw/bsp/samg55xplained/samg55xplained.c +++ b/hw/bsp/samg55xplained/samg55xplained.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, hathach (tinyusb.org) diff --git a/hw/bsp/saml2x/boards/atsaml21_xpro/board.h b/hw/bsp/saml2x/boards/atsaml21_xpro/board.h index a3e03997c..315e40c78 100644 --- a/hw/bsp/saml2x/boards/atsaml21_xpro/board.h +++ b/hw/bsp/saml2x/boards/atsaml21_xpro/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/saml2x/boards/saml22_feather/board.h b/hw/bsp/saml2x/boards/saml22_feather/board.h index 13a326000..72e9897b6 100644 --- a/hw/bsp/saml2x/boards/saml22_feather/board.h +++ b/hw/bsp/saml2x/boards/saml22_feather/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld b/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld index d1aaa44fc..156c3e7e4 100644 --- a/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld +++ b/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld @@ -14,9 +14,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/board.h b/hw/bsp/saml2x/boards/sensorwatch_m0/board.h index 7fc690ab2..735f6afc8 100644 --- a/hw/bsp/saml2x/boards/sensorwatch_m0/board.h +++ b/hw/bsp/saml2x/boards/sensorwatch_m0/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld b/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld index d1aaa44fc..156c3e7e4 100644 --- a/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld +++ b/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld @@ -14,9 +14,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. * You may obtain a copy of the Licence at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/hw/bsp/saml2x/family.c b/hw/bsp/saml2x/family.c index 470fde750..f119d23a1 100644 --- a/hw/bsp/saml2x/family.c +++ b/hw/bsp/saml2x/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/sltb009a/sltb009a.c b/hw/bsp/sltb009a/sltb009a.c index b5eb5ed5d..2a5d112a8 100644 --- a/hw/bsp/sltb009a/sltb009a.c +++ b/hw/bsp/sltb009a/sltb009a.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021 Rafael Silva (@perigoso) @@ -712,7 +712,7 @@ uint32_t board_millis(void) * @retval None */ void assert_failed(char *file, uint32_t line) -{ +{ /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ diff --git a/hw/bsp/spresense/board_spresense.c b/hw/bsp/spresense/board_spresense.c index 256bccd15..5f778ad70 100644 --- a/hw/bsp/spresense/board_spresense.c +++ b/hw/bsp/spresense/board_spresense.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright 2019 Sony Semiconductor Solutions Corporation @@ -64,7 +64,7 @@ void board_led_write(bool state) // a '1' means active (pressed), a '0' means inactive. uint32_t board_button_read(void) { - if (board_gpio_read(BUTTON_PIN)) + if (board_gpio_read(BUTTON_PIN)) { return 0; } @@ -96,7 +96,7 @@ uint32_t board_millis(void) /* Wait until RTC is available */ while (g_rtc_enabled == false); - if (clock_gettime(CLOCK_MONOTONIC, &tp)) + if (clock_gettime(CLOCK_MONOTONIC, &tp)) { return 0; } diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h index 7c527e2c2..9af81e63c 100644 --- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h +++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk index cf787a103..1cc443352 100644 --- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk +++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk @@ -12,4 +12,4 @@ IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f070xb_flash.icf JLINK_DEVICE = stm32f070rb # flash target using on-board stlink -flash: flash-stlink \ No newline at end of file +flash: flash-stlink diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld index 4a6491510..6bb9d33cb 100644 --- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld +++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld @@ -102,12 +102,12 @@ SECTIONS . = ALIGN(4); } >FLASH - .ARM.extab : { + .ARM.extab : { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >FLASH - + .ARM : { . = ALIGN(4); __exidx_start = .; @@ -124,7 +124,7 @@ SECTIONS PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); } >FLASH - + .init_array : { . = ALIGN(4); @@ -134,7 +134,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); } >FLASH - + .fini_array : { . = ALIGN(4); @@ -149,7 +149,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections into "RAM" Ram type memory */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -158,9 +158,9 @@ SECTIONS . = ALIGN(4); _edata = .; /* define a global symbol at data end */ - + } >RAM AT> FLASH - + /* Uninitialized data section into "RAM" Ram type memory */ . = ALIGN(4); .bss : diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld b/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld index f0879e929..8715e0723 100644 --- a/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld +++ b/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld @@ -114,7 +114,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -125,7 +125,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -153,7 +153,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -165,5 +165,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.h b/hw/bsp/stm32f0/boards/stm32f072disco/board.h index 0b1824b8e..1febd01e8 100644 --- a/hw/bsp/stm32f0/boards/stm32f072disco/board.h +++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.h b/hw/bsp/stm32f0/boards/stm32f072eval/board.h index 8869d5dc9..7dcfa3e85 100644 --- a/hw/bsp/stm32f0/boards/stm32f072eval/board.h +++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c index 884208fb1..bfa843494 100644 --- a/hw/bsp/stm32f0/family.c +++ b/hw/bsp/stm32f0/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f0/stm32f0xx_hal_conf.h b/hw/bsp/stm32f0/stm32f0xx_hal_conf.h index 0bf053e13..b205464f3 100644 --- a/hw/bsp/stm32f0/stm32f0xx_hal_conf.h +++ b/hw/bsp/stm32f0/stm32f0xx_hal_conf.h @@ -15,7 +15,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F0xx_HAL_CONF_H @@ -30,9 +30,9 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /*#define HAL_ADC_MODULE_ENABLED */ /*#define HAL_CAN_MODULE_ENABLED */ /*#define HAL_CEC_MODULE_ENABLED */ @@ -65,15 +65,15 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ /** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - * Timeout value + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + * Timeout value */ #if !defined (HSE_STARTUP_TIMEOUT) #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ @@ -82,24 +82,24 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** - * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup - * Timeout value + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + * Timeout value */ -#if !defined (HSI_STARTUP_TIMEOUT) +#if !defined (HSI_STARTUP_TIMEOUT) #define HSI_STARTUP_TIMEOUT 5000U /*!< Time out for HSI start up */ -#endif /* HSI_STARTUP_TIMEOUT */ +#endif /* HSI_STARTUP_TIMEOUT */ /** * @brief Internal High Speed oscillator for ADC (HSI14) value. */ -#if !defined (HSI14_VALUE) +#if !defined (HSI14_VALUE) #define HSI14_VALUE 14000000U /*!< Value of the Internal High Speed oscillator for ADC in Hz. The real value may vary depending on the variations in voltage and temperature. */ @@ -108,7 +108,7 @@ /** * @brief Internal High Speed oscillator for USB (HSI48) value. */ -#if !defined (HSI48_VALUE) +#if !defined (HSI48_VALUE) #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB in Hz. The real value may vary depending on the variations in voltage and temperature. */ @@ -117,8 +117,8 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) - #define LSI_VALUE 32000U +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000U #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ @@ -127,7 +127,7 @@ */ #if !defined (LSE_VALUE) #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ +#endif /* LSE_VALUE */ /** * @brief Time out for LSE start up value in ms. @@ -143,8 +143,8 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ -#define VDD_VALUE 3300U /*!< Value of VDD in mv */ + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */ /* Warning: Must be set to higher priority for HAL_Delay() */ /* and HAL_GetTick() usage under interrupt context */ @@ -175,14 +175,14 @@ /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ - #define USE_FULL_ASSERT 1 + #define USE_FULL_ASSERT 1 /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -299,7 +299,7 @@ * @brief The assert_param macro is used for function's parameters check. * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ @@ -308,8 +308,8 @@ void assert_failed(const char* file, uint32_t line); #else #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - +#endif /* USE_FULL_ASSERT */ + #ifdef __cplusplus } #endif @@ -318,4 +318,3 @@ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld b/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld index c434ca038..95836522e 100644 --- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld +++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld @@ -114,7 +114,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -125,7 +125,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -153,7 +153,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h index 57a607ed5..8fa8f4ffa 100644 --- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h +++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld b/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld index da637d1b0..524ac7c03 100644 --- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld +++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld @@ -114,7 +114,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -125,7 +125,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -153,7 +153,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h index bedce7f14..c8dba4268 100644 --- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h +++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c index 6f0471096..5e112de70 100644 --- a/hw/bsp/stm32f1/family.c +++ b/hw/bsp/stm32f1/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -53,7 +53,7 @@ void USBWakeUp_IRQHandler(void) void board_init(void) { board_stm32f1_clock_init(); - + // Enable All GPIOs clocks __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); @@ -70,7 +70,7 @@ void board_init(void) NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); NVIC_SetPriority(USBWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); #endif - + // LED GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Pin = LED_PIN; @@ -153,7 +153,7 @@ void HardFault_Handler (void) * @retval None */ void assert_failed(const char *file, uint32_t line) -{ +{ /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ diff --git a/hw/bsp/stm32f1/stm32f1xx_hal_conf.h b/hw/bsp/stm32f1/stm32f1xx_hal_conf.h index 5243e5bca..45ef993da 100644 --- a/hw/bsp/stm32f1/stm32f1xx_hal_conf.h +++ b/hw/bsp/stm32f1/stm32f1xx_hal_conf.h @@ -32,7 +32,7 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ #define HAL_MODULE_ENABLED /* #define HAL_ADC_MODULE_ENABLED */ @@ -69,9 +69,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #if defined(USE_STM3210C_EVAL) #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */ #else @@ -86,7 +86,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz */ @@ -95,7 +95,7 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) +#if !defined (LSI_VALUE) #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations @@ -119,7 +119,7 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ + */ #define VDD_VALUE 3300U /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY 0x00U /*!< tick interrupt priority */ #define USE_RTOS 0U @@ -151,7 +151,7 @@ /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ @@ -168,7 +168,7 @@ #define MAC_ADDR4 0U #define MAC_ADDR5 0U -/* Definition of the Ethernet driver buffers size and count */ +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB 8U /* 8 Rx buffers of size ETH_RX_BUF_SIZE */ @@ -176,9 +176,9 @@ /* Section 2: PHY configuration section */ -/* DP83848 PHY Address*/ +/* DP83848 PHY Address*/ #define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY 0x000000FFU /* PHY Configuration delay */ #define PHY_CONFIG_DELAY 0x00000FFFU @@ -190,7 +190,7 @@ #define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - + #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -205,13 +205,13 @@ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - + /* Section 4: Extended PHY Registers */ #define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ #define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ #define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - + #define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ #define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ #define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ @@ -233,7 +233,7 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -243,7 +243,7 @@ #ifdef HAL_GPIO_MODULE_ENABLED #include "stm32f1xx_hal_gpio.h" #endif /* HAL_GPIO_MODULE_ENABLED */ - + #ifdef HAL_EXTI_MODULE_ENABLED #include "stm32f1xx_hal_exti.h" #endif /* HAL_EXTI_MODULE_ENABLED */ @@ -251,7 +251,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f1xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CAN_MODULE_ENABLED #include "stm32f1xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ @@ -310,15 +310,15 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f1xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ +#endif /* HAL_PCCARD_MODULE_ENABLED */ #ifdef HAL_SD_MODULE_ENABLED #include "stm32f1xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ +#endif /* HAL_SD_MODULE_ENABLED */ #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f1xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_SPI_MODULE_ENABLED #include "stm32f1xx_hal_spi.h" @@ -358,7 +358,7 @@ * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ @@ -367,8 +367,8 @@ void assert_failed(const char* file, uint32_t line); #else #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - +#endif /* USE_FULL_ASSERT */ + #ifdef __cplusplus } #endif diff --git a/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld b/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld index 5010435ae..3fce1b578 100644 --- a/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld +++ b/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld @@ -114,7 +114,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -125,7 +125,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -153,7 +153,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -165,5 +165,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32f207nucleo/stm32f207nucleo.c b/hw/bsp/stm32f207nucleo/stm32f207nucleo.c index d77643661..80f762c93 100644 --- a/hw/bsp/stm32f207nucleo/stm32f207nucleo.c +++ b/hw/bsp/stm32f207nucleo/stm32f207nucleo.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -105,7 +105,7 @@ void SystemClock_Config(void) void board_init(void) { SystemClock_Config(); - + #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); diff --git a/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h b/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h index 2ab46b260..b38a9d951 100644 --- a/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h +++ b/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h @@ -15,7 +15,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F2xx_HAL_CONF_H @@ -30,9 +30,9 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CRC_MODULE_ENABLED */ @@ -42,7 +42,7 @@ /* #define HAL_DMA_MODULE_ENABLED */ /* #define HAL_ETH_MODULE_ENABLED */ #define HAL_EXTI_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_PCCARD_MODULE_ENABLED */ @@ -52,8 +52,8 @@ /* #define HAL_I2C_MODULE_ENABLED */ /* #define HAL_I2S_MODULE_ENABLED */ /* #define HAL_IWDG_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SD_MODULE_ENABLED */ @@ -65,7 +65,7 @@ /* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ #define HAL_CORTEX_MODULE_ENABLED -#define HAL_PCD_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED /* #define HAL_HCD_MODULE_ENABLED */ @@ -73,9 +73,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -86,7 +86,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ @@ -95,7 +95,7 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) +#if !defined (LSI_VALUE) #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations @@ -113,8 +113,8 @@ /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the Internal oscillator in Hz*/ @@ -126,7 +126,7 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ + */ #define VDD_VALUE 3300U /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ #define USE_RTOS 0U @@ -163,7 +163,7 @@ /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ @@ -180,7 +180,7 @@ #define MAC_ADDR4 0U #define MAC_ADDR5 0U -/* Definition of the Ethernet driver buffers size and count */ +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ @@ -190,7 +190,7 @@ /* LAN8742A PHY Address*/ #define LAN8742A_PHY_ADDRESS 0x00U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY 0x000000FFU /* PHY Configuration delay */ #define PHY_CONFIG_DELAY 0x00000FFFU @@ -202,7 +202,7 @@ #define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - + #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -217,7 +217,7 @@ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - + /* Section 4: Extended PHY Registers */ #define PHY_SR ((uint16_t)0x1F) /*!< PHY special control/ status register Offset */ @@ -228,7 +228,7 @@ #define PHY_ISFR ((uint16_t)0x1D) /*!< PHY Interrupt Source Flag register Offset */ #define PHY_ISFR_INT4 ((uint16_t)0x0010) /*!< PHY Link down inturrupt */ - + /* ################## SPI peripheral configuration ########################## */ /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver @@ -240,7 +240,7 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -258,7 +258,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f2xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f2xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -276,7 +276,7 @@ #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f2xx_hal_cryp.h" + #include "stm32f2xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DAC_MODULE_ENABLED @@ -294,7 +294,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f2xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f2xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -309,7 +309,7 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f2xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ +#endif /* HAL_PCCARD_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f2xx_hal_hash.h" @@ -378,14 +378,14 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f2xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ @@ -402,6 +402,6 @@ #endif #endif /* __STM32F2xx_HAL_CONF_H */ - + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld b/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld index 7f46c71b2..981107af1 100644 --- a/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld +++ b/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld @@ -115,7 +115,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -128,11 +128,11 @@ SECTIONS _siccmram = LOADADDR(.ccmram); - /* CCM-RAM section - * - * IMPORTANT NOTE! + /* CCM-RAM section + * + * IMPORTANT NOTE! * If initialized variables will be placed in this section, - * the startup code needs to be modified to copy the init-values. + * the startup code needs to be modified to copy the init-values. */ .ccmram : { @@ -140,12 +140,12 @@ SECTIONS _sccmram = .; /* create a global symbol at ccmram start */ *(.ccmram) *(.ccmram*) - + . = ALIGN(4); _eccmram = .; /* create a global symbol at ccmram end */ } >CCMRAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -173,7 +173,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -185,5 +185,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32f303disco/stm32f303disco.c b/hw/bsp/stm32f303disco/stm32f303disco.c index 940c49d26..ac9bda983 100644 --- a/hw/bsp/stm32f303disco/stm32f303disco.c +++ b/hw/bsp/stm32f303disco/stm32f303disco.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h b/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h index 0abcbb019..82d3765af 100644 --- a/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h +++ b/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h @@ -15,7 +15,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_HAL_CONF_H @@ -30,9 +30,9 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CAN_LEGACY_MODULE_ENABLED */ @@ -57,7 +57,7 @@ /* #define HAL_OPAMP_MODULE_ENABLED */ /* #define HAL_PCD_MODULE_ENABLED */ /* #define HAL_PWR_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SDADC_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */ @@ -73,15 +73,15 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ /** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - * Timeout value + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + * Timeout value */ #if !defined (HSE_STARTUP_TIMEOUT) #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ @@ -90,25 +90,25 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE (8000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** - * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup - * Timeout value + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + * Timeout value */ -#if !defined (HSI_STARTUP_TIMEOUT) +#if !defined (HSI_STARTUP_TIMEOUT) #define HSI_STARTUP_TIMEOUT (5000U) /*!< Time out for HSI start up */ -#endif /* HSI_STARTUP_TIMEOUT */ +#endif /* HSI_STARTUP_TIMEOUT */ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (40000U) +#if !defined (LSI_VALUE) + #define LSI_VALUE (40000U) #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ @@ -124,11 +124,11 @@ */ #if !defined (LSE_STARTUP_TIMEOUT) #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ +#endif /* LSE_STARTUP_TIMEOUT */ /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source + * This value is used by the I2S HAL module to compute the I2S clock source * frequency, this source is inserted directly through I2S_CKIN pad. * - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal) * - External clock not generated on EVAL 373 @@ -256,8 +256,8 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f3xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - +#endif /* HAL_PCCARD_MODULE_ENABLED */ + #ifdef HAL_HRTIM_MODULE_ENABLED #include "stm32f3xx_hal_hrtim.h" #endif /* HAL_HRTIM_MODULE_ENABLED */ diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld b/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld index 9eb53bcc0..0dc2879a4 100644 --- a/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld @@ -115,7 +115,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -128,11 +128,11 @@ SECTIONS _siccmram = LOADADDR(.ccmram); - /* CCM-RAM section - * - * IMPORTANT NOTE! + /* CCM-RAM section + * + * IMPORTANT NOTE! * If initialized variables will be placed in this section, - * the startup code needs to be modified to copy the init-values. + * the startup code needs to be modified to copy the init-values. */ .ccmram : { @@ -140,12 +140,12 @@ SECTIONS _sccmram = .; /* create a global symbol at ccmram start */ *(.ccmram) *(.ccmram*) - + . = ALIGN(4); _eccmram = .; /* create a global symbol at ccmram end */ } >CCMRAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -173,7 +173,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -185,5 +185,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h index 19d0a1ea4..d1ad2a6ce 100644 --- a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h +++ b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld b/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld index 9eb53bcc0..0dc2879a4 100644 --- a/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld @@ -115,7 +115,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -128,11 +128,11 @@ SECTIONS _siccmram = LOADADDR(.ccmram); - /* CCM-RAM section - * - * IMPORTANT NOTE! + /* CCM-RAM section + * + * IMPORTANT NOTE! * If initialized variables will be placed in this section, - * the startup code needs to be modified to copy the init-values. + * the startup code needs to be modified to copy the init-values. */ .ccmram : { @@ -140,12 +140,12 @@ SECTIONS _sccmram = .; /* create a global symbol at ccmram start */ *(.ccmram) *(.ccmram*) - + . = ALIGN(4); _eccmram = .; /* create a global symbol at ccmram end */ } >CCMRAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -173,7 +173,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -185,5 +185,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32f4/boards/pyboardv11/board.h b/hw/bsp/stm32f4/boards/pyboardv11/board.h index 685919c57..c126f0666 100644 --- a/hw/bsp/stm32f4/boards/pyboardv11/board.h +++ b/hw/bsp/stm32f4/boards/pyboardv11/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld index 2bc5f6c14..b91f456ca 100644 --- a/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld @@ -114,7 +114,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -125,7 +125,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -153,7 +153,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -165,5 +165,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h index e1fef7277..e6c99a462 100644 --- a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h +++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h index 2ab9a1d57..16f081cfb 100644 --- a/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h +++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h @@ -15,7 +15,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_CONF_H @@ -30,38 +30,38 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ /* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_PCCARD_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED /* #define HAL_EXTI_MODULE_ENABLED */ /* #define HAL_I2C_MODULE_ENABLED */ /* #define HAL_SMBUS_MODULE_ENABLED */ /* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LTDC_MODULE_ENABLED */ /* #define HAL_DSI_MODULE_ENABLED */ #define HAL_PWR_MODULE_ENABLED /* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ @@ -69,11 +69,11 @@ // #define HAL_SPI_MODULE_ENABLED /* #define HAL_TIM_MODULE_ENABLED */ #define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED /* #define HAL_PCD_MODULE_ENABLED */ /* #define HAL_HCD_MODULE_ENABLED */ /* #define HAL_FMPI2C_MODULE_ENABLED */ @@ -86,9 +86,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE (25000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -99,7 +99,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ @@ -108,8 +108,8 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000U) #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ @@ -126,8 +126,8 @@ /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ @@ -139,9 +139,9 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ + */ #define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ +#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ #define USE_RTOS 0U #define PREFETCH_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U @@ -188,7 +188,7 @@ /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ @@ -205,7 +205,7 @@ #define MAC_ADDR4 0U #define MAC_ADDR5 0U -/* Definition of the Ethernet driver buffers size and count */ +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ @@ -213,9 +213,9 @@ /* Section 2: PHY configuration section */ -/* DP83848 PHY Address*/ +/* DP83848 PHY Address*/ #define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY 0x000000FFU /* PHY Configuration delay */ #define PHY_CONFIG_DELAY 0x00000FFFU @@ -227,7 +227,7 @@ #define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - + #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -242,13 +242,13 @@ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - + /* Section 4: Extended PHY Registers */ #define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ #define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ #define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - + #define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ #define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ #define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ @@ -270,7 +270,7 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -288,7 +288,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f4xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f4xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -310,7 +310,7 @@ #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" + #include "stm32f4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DMA2D_MODULE_ENABLED @@ -332,7 +332,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -347,11 +347,11 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - +#endif /* HAL_PCCARD_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f4xx_hal_hash.h" @@ -432,7 +432,7 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + #ifdef HAL_DSI_MODULE_ENABLED #include "stm32f4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ @@ -471,7 +471,7 @@ * @brief The assert_param macro is used for function's parameters check. * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld index aac6577ea..549787945 100644 --- a/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld @@ -115,7 +115,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -128,11 +128,11 @@ SECTIONS _siccmram = LOADADDR(.ccmram); - /* CCM-RAM section - * - * IMPORTANT NOTE! + /* CCM-RAM section + * + * IMPORTANT NOTE! * If initialized variables will be placed in this section, - * the startup code needs to be modified to copy the init-values. + * the startup code needs to be modified to copy the init-values. */ .ccmram : { @@ -140,12 +140,12 @@ SECTIONS _sccmram = .; /* create a global symbol at ccmram start */ *(.ccmram) *(.ccmram*) - + . = ALIGN(4); _eccmram = .; /* create a global symbol at ccmram end */ } >CCMRAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -173,7 +173,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -185,5 +185,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/board.h b/hw/bsp/stm32f4/boards/stm32f407disco/board.h index 693e0393f..c38f354ce 100644 --- a/hw/bsp/stm32f4/boards/stm32f407disco/board.h +++ b/hw/bsp/stm32f4/boards/stm32f407disco/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h index 7864f8d5f..e24e782ea 100644 --- a/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h +++ b/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h @@ -15,7 +15,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_CONF_H @@ -30,38 +30,38 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ /* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_PCCARD_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED /* #define HAL_EXTI_MODULE_ENABLED */ /* #define HAL_I2C_MODULE_ENABLED */ /* #define HAL_SMBUS_MODULE_ENABLED */ /* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LTDC_MODULE_ENABLED */ /* #define HAL_DSI_MODULE_ENABLED */ #define HAL_PWR_MODULE_ENABLED /* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ @@ -69,11 +69,11 @@ // #define HAL_SPI_MODULE_ENABLED /* #define HAL_TIM_MODULE_ENABLED */ #define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED /* #define HAL_PCD_MODULE_ENABLED */ /* #define HAL_HCD_MODULE_ENABLED */ /* #define HAL_FMPI2C_MODULE_ENABLED */ @@ -86,9 +86,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -99,7 +99,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ @@ -108,8 +108,8 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000U) #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ @@ -126,8 +126,8 @@ /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ @@ -139,9 +139,9 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ + */ #define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ +#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ #define USE_RTOS 0U #define PREFETCH_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U @@ -188,7 +188,7 @@ /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ @@ -205,7 +205,7 @@ #define MAC_ADDR4 0U #define MAC_ADDR5 0U -/* Definition of the Ethernet driver buffers size and count */ +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ @@ -213,9 +213,9 @@ /* Section 2: PHY configuration section */ -/* DP83848 PHY Address*/ +/* DP83848 PHY Address*/ #define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY 0x000000FFU /* PHY Configuration delay */ #define PHY_CONFIG_DELAY 0x00000FFFU @@ -227,7 +227,7 @@ #define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - + #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -242,13 +242,13 @@ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - + /* Section 4: Extended PHY Registers */ #define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ #define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ #define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - + #define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ #define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ #define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ @@ -270,7 +270,7 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -288,7 +288,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f4xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f4xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -310,7 +310,7 @@ #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" + #include "stm32f4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DMA2D_MODULE_ENABLED @@ -332,7 +332,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -347,11 +347,11 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - +#endif /* HAL_PCCARD_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f4xx_hal_hash.h" @@ -432,7 +432,7 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + #ifdef HAL_DSI_MODULE_ENABLED #include "stm32f4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ @@ -471,7 +471,7 @@ * @brief The assert_param macro is used for function's parameters check. * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld index 56dcea605..45912ac32 100644 --- a/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld @@ -114,7 +114,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -125,7 +125,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -153,7 +153,7 @@ SECTIONS . = ALIGN(4); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -165,5 +165,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h index e1fef7277..e6c99a462 100644 --- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h +++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h index 2ab9a1d57..16f081cfb 100644 --- a/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h +++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h @@ -15,7 +15,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_CONF_H @@ -30,38 +30,38 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ /* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_PCCARD_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED /* #define HAL_EXTI_MODULE_ENABLED */ /* #define HAL_I2C_MODULE_ENABLED */ /* #define HAL_SMBUS_MODULE_ENABLED */ /* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LTDC_MODULE_ENABLED */ /* #define HAL_DSI_MODULE_ENABLED */ #define HAL_PWR_MODULE_ENABLED /* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ @@ -69,11 +69,11 @@ // #define HAL_SPI_MODULE_ENABLED /* #define HAL_TIM_MODULE_ENABLED */ #define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED /* #define HAL_PCD_MODULE_ENABLED */ /* #define HAL_HCD_MODULE_ENABLED */ /* #define HAL_FMPI2C_MODULE_ENABLED */ @@ -86,9 +86,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE (25000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -99,7 +99,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ @@ -108,8 +108,8 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000U) #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ @@ -126,8 +126,8 @@ /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ @@ -139,9 +139,9 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ + */ #define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ +#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ #define USE_RTOS 0U #define PREFETCH_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U @@ -188,7 +188,7 @@ /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ @@ -205,7 +205,7 @@ #define MAC_ADDR4 0U #define MAC_ADDR5 0U -/* Definition of the Ethernet driver buffers size and count */ +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ @@ -213,9 +213,9 @@ /* Section 2: PHY configuration section */ -/* DP83848 PHY Address*/ +/* DP83848 PHY Address*/ #define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY 0x000000FFU /* PHY Configuration delay */ #define PHY_CONFIG_DELAY 0x00000FFFU @@ -227,7 +227,7 @@ #define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - + #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -242,13 +242,13 @@ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - + /* Section 4: Extended PHY Registers */ #define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ #define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ #define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - + #define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ #define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ #define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ @@ -270,7 +270,7 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -288,7 +288,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f4xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f4xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -310,7 +310,7 @@ #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" + #include "stm32f4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DMA2D_MODULE_ENABLED @@ -332,7 +332,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -347,11 +347,11 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - +#endif /* HAL_PCCARD_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f4xx_hal_hash.h" @@ -432,7 +432,7 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + #ifdef HAL_DSI_MODULE_ENABLED #include "stm32f4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ @@ -471,7 +471,7 @@ * @brief The assert_param macro is used for function's parameters check. * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld index 4477229ea..85bf5c4c4 100644 --- a/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld @@ -114,7 +114,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -125,7 +125,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -153,7 +153,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -165,5 +165,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/board.h b/hw/bsp/stm32f4/boards/stm32f411disco/board.h index 008a94a5d..57d1e061e 100644 --- a/hw/bsp/stm32f4/boards/stm32f411disco/board.h +++ b/hw/bsp/stm32f4/boards/stm32f411disco/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h index 7864f8d5f..e24e782ea 100644 --- a/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h +++ b/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h @@ -15,7 +15,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_CONF_H @@ -30,38 +30,38 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ /* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_PCCARD_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED /* #define HAL_EXTI_MODULE_ENABLED */ /* #define HAL_I2C_MODULE_ENABLED */ /* #define HAL_SMBUS_MODULE_ENABLED */ /* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LTDC_MODULE_ENABLED */ /* #define HAL_DSI_MODULE_ENABLED */ #define HAL_PWR_MODULE_ENABLED /* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ @@ -69,11 +69,11 @@ // #define HAL_SPI_MODULE_ENABLED /* #define HAL_TIM_MODULE_ENABLED */ #define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED /* #define HAL_PCD_MODULE_ENABLED */ /* #define HAL_HCD_MODULE_ENABLED */ /* #define HAL_FMPI2C_MODULE_ENABLED */ @@ -86,9 +86,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -99,7 +99,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ @@ -108,8 +108,8 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000U) #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ @@ -126,8 +126,8 @@ /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ @@ -139,9 +139,9 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ + */ #define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ +#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ #define USE_RTOS 0U #define PREFETCH_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U @@ -188,7 +188,7 @@ /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ @@ -205,7 +205,7 @@ #define MAC_ADDR4 0U #define MAC_ADDR5 0U -/* Definition of the Ethernet driver buffers size and count */ +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ @@ -213,9 +213,9 @@ /* Section 2: PHY configuration section */ -/* DP83848 PHY Address*/ +/* DP83848 PHY Address*/ #define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY 0x000000FFU /* PHY Configuration delay */ #define PHY_CONFIG_DELAY 0x00000FFFU @@ -227,7 +227,7 @@ #define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - + #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -242,13 +242,13 @@ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - + /* Section 4: Extended PHY Registers */ #define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ #define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ #define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - + #define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ #define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ #define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ @@ -270,7 +270,7 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -288,7 +288,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f4xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f4xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -310,7 +310,7 @@ #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" + #include "stm32f4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DMA2D_MODULE_ENABLED @@ -332,7 +332,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -347,11 +347,11 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - +#endif /* HAL_PCCARD_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f4xx_hal_hash.h" @@ -432,7 +432,7 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + #ifdef HAL_DSI_MODULE_ENABLED #include "stm32f4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ @@ -471,7 +471,7 @@ * @brief The assert_param macro is used for function's parameters check. * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld index 2372cc1d9..38dd3d321 100644 --- a/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld @@ -114,7 +114,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -125,7 +125,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -153,7 +153,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -165,5 +165,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.h b/hw/bsp/stm32f4/boards/stm32f412disco/board.h index 7f4a4fa15..d61b70eb9 100644 --- a/hw/bsp/stm32f4/boards/stm32f412disco/board.h +++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h index 7864f8d5f..e24e782ea 100644 --- a/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h +++ b/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h @@ -15,7 +15,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_CONF_H @@ -30,38 +30,38 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ /* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_PCCARD_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED /* #define HAL_EXTI_MODULE_ENABLED */ /* #define HAL_I2C_MODULE_ENABLED */ /* #define HAL_SMBUS_MODULE_ENABLED */ /* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LTDC_MODULE_ENABLED */ /* #define HAL_DSI_MODULE_ENABLED */ #define HAL_PWR_MODULE_ENABLED /* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ @@ -69,11 +69,11 @@ // #define HAL_SPI_MODULE_ENABLED /* #define HAL_TIM_MODULE_ENABLED */ #define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED /* #define HAL_PCD_MODULE_ENABLED */ /* #define HAL_HCD_MODULE_ENABLED */ /* #define HAL_FMPI2C_MODULE_ENABLED */ @@ -86,9 +86,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -99,7 +99,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ @@ -108,8 +108,8 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000U) #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ @@ -126,8 +126,8 @@ /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ @@ -139,9 +139,9 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ + */ #define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ +#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ #define USE_RTOS 0U #define PREFETCH_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U @@ -188,7 +188,7 @@ /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ @@ -205,7 +205,7 @@ #define MAC_ADDR4 0U #define MAC_ADDR5 0U -/* Definition of the Ethernet driver buffers size and count */ +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ @@ -213,9 +213,9 @@ /* Section 2: PHY configuration section */ -/* DP83848 PHY Address*/ +/* DP83848 PHY Address*/ #define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY 0x000000FFU /* PHY Configuration delay */ #define PHY_CONFIG_DELAY 0x00000FFFU @@ -227,7 +227,7 @@ #define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - + #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -242,13 +242,13 @@ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - + /* Section 4: Extended PHY Registers */ #define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ #define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ #define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - + #define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ #define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ #define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ @@ -270,7 +270,7 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -288,7 +288,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f4xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f4xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -310,7 +310,7 @@ #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" + #include "stm32f4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DMA2D_MODULE_ENABLED @@ -332,7 +332,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -347,11 +347,11 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - +#endif /* HAL_PCCARD_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f4xx_hal_hash.h" @@ -432,7 +432,7 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + #ifdef HAL_DSI_MODULE_ENABLED #include "stm32f4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ @@ -471,7 +471,7 @@ * @brief The assert_param macro is used for function's parameters check. * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld index 2372cc1d9..38dd3d321 100644 --- a/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld +++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld @@ -114,7 +114,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -125,7 +125,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -153,7 +153,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -165,5 +165,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h index 7864f8d5f..e24e782ea 100644 --- a/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h +++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h @@ -15,7 +15,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_CONF_H @@ -30,38 +30,38 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ /* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_PCCARD_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED /* #define HAL_EXTI_MODULE_ENABLED */ /* #define HAL_I2C_MODULE_ENABLED */ /* #define HAL_SMBUS_MODULE_ENABLED */ /* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LTDC_MODULE_ENABLED */ /* #define HAL_DSI_MODULE_ENABLED */ #define HAL_PWR_MODULE_ENABLED /* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ @@ -69,11 +69,11 @@ // #define HAL_SPI_MODULE_ENABLED /* #define HAL_TIM_MODULE_ENABLED */ #define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED /* #define HAL_PCD_MODULE_ENABLED */ /* #define HAL_HCD_MODULE_ENABLED */ /* #define HAL_FMPI2C_MODULE_ENABLED */ @@ -86,9 +86,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -99,7 +99,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ @@ -108,8 +108,8 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000U) #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ @@ -126,8 +126,8 @@ /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ @@ -139,9 +139,9 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ + */ #define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ +#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ #define USE_RTOS 0U #define PREFETCH_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U @@ -188,7 +188,7 @@ /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ @@ -205,7 +205,7 @@ #define MAC_ADDR4 0U #define MAC_ADDR5 0U -/* Definition of the Ethernet driver buffers size and count */ +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ @@ -213,9 +213,9 @@ /* Section 2: PHY configuration section */ -/* DP83848 PHY Address*/ +/* DP83848 PHY Address*/ #define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY 0x000000FFU /* PHY Configuration delay */ #define PHY_CONFIG_DELAY 0x00000FFFU @@ -227,7 +227,7 @@ #define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - + #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -242,13 +242,13 @@ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - + /* Section 4: Extended PHY Registers */ #define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ #define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ #define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - + #define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ #define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ #define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ @@ -270,7 +270,7 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -288,7 +288,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f4xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f4xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -310,7 +310,7 @@ #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" + #include "stm32f4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DMA2D_MODULE_ENABLED @@ -332,7 +332,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -347,11 +347,11 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - +#endif /* HAL_PCCARD_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f4xx_hal_hash.h" @@ -432,7 +432,7 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + #ifdef HAL_DSI_MODULE_ENABLED #include "stm32f4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ @@ -471,7 +471,7 @@ * @brief The assert_param macro is used for function's parameters check. * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h index a2c11d717..7bbd6b54f 100644 --- a/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h +++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h @@ -15,7 +15,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_CONF_H @@ -30,38 +30,38 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ /* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_PCCARD_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED /* #define HAL_EXTI_MODULE_ENABLED */ /* #define HAL_I2C_MODULE_ENABLED */ /* #define HAL_SMBUS_MODULE_ENABLED */ /* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LTDC_MODULE_ENABLED */ /* #define HAL_DSI_MODULE_ENABLED */ #define HAL_PWR_MODULE_ENABLED /* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ @@ -69,11 +69,11 @@ // #define HAL_SPI_MODULE_ENABLED /* #define HAL_TIM_MODULE_ENABLED */ #define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED /* #define HAL_PCD_MODULE_ENABLED */ /* #define HAL_HCD_MODULE_ENABLED */ /* #define HAL_FMPI2C_MODULE_ENABLED */ @@ -86,9 +86,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -99,7 +99,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ @@ -108,8 +108,8 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000U) #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ @@ -126,8 +126,8 @@ /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ @@ -139,9 +139,9 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ + */ #define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ +#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ #define USE_RTOS 0U #define PREFETCH_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U @@ -188,7 +188,7 @@ /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ @@ -263,7 +263,7 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -281,7 +281,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f4xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f4xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -303,7 +303,7 @@ #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" + #include "stm32f4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DMA2D_MODULE_ENABLED @@ -325,7 +325,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -340,11 +340,11 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - +#endif /* HAL_PCCARD_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f4xx_hal_hash.h" @@ -425,7 +425,7 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + #ifdef HAL_DSI_MODULE_ENABLED #include "stm32f4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ @@ -464,7 +464,7 @@ * @brief The assert_param macro is used for function's parameters check. * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c index 93ab5bb35..a308bae05 100644 --- a/hw/bsp/stm32f4/family.c +++ b/hw/bsp/stm32f4/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/board.h b/hw/bsp/stm32f7/boards/stlinkv3mini/board.h index d0ef6625f..ed02df061 100644 --- a/hw/bsp/stm32f7/boards/stlinkv3mini/board.h +++ b/hw/bsp/stm32f7/boards/stlinkv3mini/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.h b/hw/bsp/stm32f7/boards/stm32f723disco/board.h index 93d83efc6..258786b7f 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/board.h +++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.h b/hw/bsp/stm32f7/boards/stm32f746disco/board.h index ee342b9f5..1c7e6dd2b 100644 --- a/hw/bsp/stm32f7/boards/stm32f746disco/board.h +++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld index e1e60bc78..eeb0e29f3 100644 --- a/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld +++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld @@ -114,7 +114,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -125,7 +125,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -153,7 +153,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h index 92c109a72..cf895af87 100644 --- a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h +++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h b/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h index 234191b00..03dec8f0d 100644 --- a/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h +++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32f7xx_hal_conf.h * @author MCD Application Team - * @brief HAL configuration file. + * @brief HAL configuration file. ****************************************************************************** * @attention * @@ -15,7 +15,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_HAL_CONF_H @@ -30,9 +30,9 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CAN_LEGACY_MODULE_ENABLED */ @@ -44,7 +44,7 @@ #define HAL_DMA_MODULE_ENABLED /* #define HAL_DMA2D_MODULE_ENABLED */ /* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ @@ -58,7 +58,7 @@ /* #define HAL_LTDC_MODULE_ENABLED */ #define HAL_PWR_MODULE_ENABLED /* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ @@ -84,9 +84,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -97,7 +97,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ @@ -106,7 +106,7 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) +#if !defined (LSI_VALUE) #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations @@ -124,8 +124,8 @@ /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ @@ -137,7 +137,7 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ + */ #define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */ #define USE_RTOS 0U @@ -185,7 +185,7 @@ /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1 */ @@ -202,7 +202,7 @@ #define MAC_ADDR4 0U #define MAC_ADDR5 0U -/* Definition of the Ethernet driver buffers size and count */ +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB ((uint32_t)5) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ @@ -211,7 +211,7 @@ /* Section 2: PHY configuration section */ /* LAN8742A PHY Address*/ #define LAN8742A_PHY_ADDRESS 0x00 -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY ((uint32_t)0x00000FFF) /* PHY Configuration delay */ #define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) @@ -223,7 +223,7 @@ #define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ - + #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -238,7 +238,7 @@ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - + /* Section 4: Extended PHY Registers */ #define PHY_SR ((uint16_t)0x1F) /*!< PHY special control/ status register Offset */ @@ -261,7 +261,7 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -275,7 +275,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f7xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f7xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -301,7 +301,7 @@ #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f7xx_hal_cryp.h" + #include "stm32f7xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DMA2D_MODULE_ENABLED @@ -323,7 +323,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f7xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f7xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -338,7 +338,7 @@ #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f7xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f7xx_hal_hash.h" @@ -443,14 +443,14 @@ #ifdef HAL_MDIOS_MODULE_ENABLED #include "stm32f7xx_hal_mdios.h" #endif /* HAL_MDIOS_MODULE_ENABLED */ - + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ @@ -467,6 +467,6 @@ #endif #endif /* __STM32F7xx_HAL_CONF_H */ - + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld index 3785f9cbf..520a75539 100644 --- a/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld +++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld @@ -114,7 +114,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -125,7 +125,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -153,7 +153,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -165,5 +165,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h index 1283f2313..e053572a7 100644 --- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h +++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk index a460245b2..be5862612 100644 --- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk +++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk @@ -1,5 +1,5 @@ PORT ?= 0 -SPEED ?= full +SPEED ?= full CFLAGS += \ -DSTM32F767xx \ diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h b/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h index 234191b00..03dec8f0d 100644 --- a/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h +++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32f7xx_hal_conf.h * @author MCD Application Team - * @brief HAL configuration file. + * @brief HAL configuration file. ****************************************************************************** * @attention * @@ -15,7 +15,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_HAL_CONF_H @@ -30,9 +30,9 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CAN_LEGACY_MODULE_ENABLED */ @@ -44,7 +44,7 @@ #define HAL_DMA_MODULE_ENABLED /* #define HAL_DMA2D_MODULE_ENABLED */ /* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ @@ -58,7 +58,7 @@ /* #define HAL_LTDC_MODULE_ENABLED */ #define HAL_PWR_MODULE_ENABLED /* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ @@ -84,9 +84,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -97,7 +97,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ @@ -106,7 +106,7 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) +#if !defined (LSI_VALUE) #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations @@ -124,8 +124,8 @@ /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ @@ -137,7 +137,7 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ + */ #define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */ #define USE_RTOS 0U @@ -185,7 +185,7 @@ /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1 */ @@ -202,7 +202,7 @@ #define MAC_ADDR4 0U #define MAC_ADDR5 0U -/* Definition of the Ethernet driver buffers size and count */ +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB ((uint32_t)5) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ @@ -211,7 +211,7 @@ /* Section 2: PHY configuration section */ /* LAN8742A PHY Address*/ #define LAN8742A_PHY_ADDRESS 0x00 -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY ((uint32_t)0x00000FFF) /* PHY Configuration delay */ #define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) @@ -223,7 +223,7 @@ #define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ - + #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -238,7 +238,7 @@ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - + /* Section 4: Extended PHY Registers */ #define PHY_SR ((uint16_t)0x1F) /*!< PHY special control/ status register Offset */ @@ -261,7 +261,7 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -275,7 +275,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f7xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f7xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -301,7 +301,7 @@ #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f7xx_hal_cryp.h" + #include "stm32f7xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DMA2D_MODULE_ENABLED @@ -323,7 +323,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f7xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f7xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -338,7 +338,7 @@ #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f7xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f7xx_hal_hash.h" @@ -443,14 +443,14 @@ #ifdef HAL_MDIOS_MODULE_ENABLED #include "stm32f7xx_hal_mdios.h" #endif /* HAL_MDIOS_MODULE_ENABLED */ - + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ @@ -467,6 +467,6 @@ #endif #endif /* __STM32F7xx_HAL_CONF_H */ - + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/board.h b/hw/bsp/stm32f7/boards/stm32f769disco/board.h index 5ec217f5f..472af0b98 100644 --- a/hw/bsp/stm32f7/boards/stm32f769disco/board.h +++ b/hw/bsp/stm32f7/boards/stm32f769disco/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld index 9c327483b..c43829994 100644 --- a/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld +++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld @@ -135,7 +135,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -146,7 +146,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -174,7 +174,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -186,5 +186,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c index f3ba54576..f5177fd10 100644 --- a/hw/bsp/stm32g4/family.c +++ b/hw/bsp/stm32g4/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32g4/stm32g4xx_hal_conf.h b/hw/bsp/stm32g4/stm32g4xx_hal_conf.h index ad5f7dbd4..632c4f0ac 100644 --- a/hw/bsp/stm32g4/stm32g4xx_hal_conf.h +++ b/hw/bsp/stm32g4/stm32g4xx_hal_conf.h @@ -15,7 +15,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_CONF_H @@ -30,10 +30,10 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ - -#define HAL_MODULE_ENABLED + +#define HAL_MODULE_ENABLED /*#define HAL_ADC_MODULE_ENABLED */ /*#define HAL_COMP_MODULE_ENABLED */ @@ -111,9 +111,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE (24000000UL) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -124,7 +124,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ @@ -145,10 +145,10 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) +#if !defined (LSI_VALUE) /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ -#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /** * @brief External Low Speed oscillator (LSE) value. @@ -156,7 +156,7 @@ The real value may vary depending on the variations in voltage and temperature.* */ #if !defined (LSE_VALUE) #define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ +#endif /* LSE_VALUE */ #if !defined (LSE_STARTUP_TIMEOUT) #define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ @@ -177,10 +177,10 @@ The real value may vary depending on the variations in voltage and temperature.* /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ + */ #define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0UL) /*!< tick interrupt priority (lowest by default) */ +#define TICK_INT_PRIORITY (0UL) /*!< tick interrupt priority (lowest by default) */ #define USE_RTOS 0U #define PREFETCH_ENABLE 0U #define INSTRUCTION_CACHE_ENABLE 1U @@ -188,7 +188,7 @@ The real value may vary depending on the variations in voltage and temperature.* /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.mk b/hw/bsp/stm32h7/boards/daisyseed/board.mk index 4d718f04e..d53782496 100644 --- a/hw/bsp/stm32h7/boards/daisyseed/board.mk +++ b/hw/bsp/stm32h7/boards/daisyseed/board.mk @@ -16,4 +16,3 @@ JLINK_DEVICE = stm32h750ibk6_m7 # flash target using on-board stlink flash: flash-stlink - diff --git a/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_flash.ld b/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_flash.ld index 83904067a..3588ada5b 100644 --- a/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_flash.ld +++ b/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_flash.ld @@ -172,5 +172,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld b/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld index 7ee40671c..336afc01f 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld +++ b/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld @@ -118,7 +118,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -129,7 +129,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >DTCMRAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -157,7 +157,7 @@ SECTIONS . = ALIGN(8); } >DTCMRAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -169,5 +169,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld b/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld index 7ee40671c..336afc01f 100644 --- a/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld +++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld @@ -118,7 +118,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -129,7 +129,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >DTCMRAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -157,7 +157,7 @@ SECTIONS . = ALIGN(8); } >DTCMRAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -169,5 +169,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.mk b/hw/bsp/stm32h7/boards/stm32h745disco/board.mk index b51b109f6..86347ade7 100644 --- a/hw/bsp/stm32h7/boards/stm32h745disco/board.mk +++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.mk @@ -19,4 +19,3 @@ JLINK_DEVICE = stm32h745xi_m7 # flash target using on-board stlink flash: flash-stlink - diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld b/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld index e99bb977b..697a1a1df 100644 --- a/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld +++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld @@ -171,5 +171,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk index fbf4b55c6..e8202d9fc 100644 --- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk +++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk @@ -21,4 +21,4 @@ IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h743xx_flash.icf JLINK_DEVICE = stm32h743ii # flash target using jlink -flash: flash-jlink \ No newline at end of file +flash: flash-jlink diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index 65ffc8ef4..35b2cd55b 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -91,7 +91,7 @@ void board_init(void) #endif NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); #endif - + GPIO_InitTypeDef GPIO_InitStruct; // LED diff --git a/hw/bsp/stm32h7/stm32h7xx_hal_conf.h b/hw/bsp/stm32h7/stm32h7xx_hal_conf.h index a7cc6d826..216fc82f2 100644 --- a/hw/bsp/stm32h7/stm32h7xx_hal_conf.h +++ b/hw/bsp/stm32h7/stm32h7xx_hal_conf.h @@ -1,7 +1,7 @@ /** ****************************************************************************** * @file stm32h7xx_hal_conf_template.h - * @brief HAL configuration template file. + * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32h7xx_hal_conf.h. ****************************************************************************** @@ -32,7 +32,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32H7xx_HAL_CONF_H @@ -478,6 +478,6 @@ #endif #endif /* __STM32H7xx_HAL_CONF_H */ - + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld b/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld index dfefe59f1..d4d5b6ca5 100644 --- a/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld +++ b/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld @@ -114,7 +114,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -125,7 +125,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -153,7 +153,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -165,5 +165,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/board.h b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h index 8ad3e43c8..c8963199b 100644 --- a/hw/bsp/stm32l0/boards/stm32l052dap52/board.h +++ b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) @@ -58,43 +58,43 @@ static inline void board_stm32l0_clock_init(void) RCC_OscInitTypeDef RCC_OscInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; static RCC_CRSInitTypeDef RCC_CRSInitStruct; - + /* Enable HSI Oscillator to be used as System clock source Enable HSI48 Oscillator to be used as USB clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - + HAL_RCC_OscConfig(&RCC_OscInitStruct); + /* Select HSI48 as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /* Select HSI as system clock source and configure the HCLK, PCLK1 and PCLK2 + + /* Select HSI as system clock source and configure the HCLK, PCLK1 and PCLK2 clock dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); - + /*Configure the clock recovery system (CRS)**********************************/ - + /*Enable CRS Clock*/ - __HAL_RCC_CRS_CLK_ENABLE(); - + __HAL_RCC_CRS_CLK_ENABLE(); + /* Default Synchro Signal division factor (not divided) */ - RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1; + RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1; /* Set the SYNCSRC[1:0] bits according to CRS_Source value */ - RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB; + RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB; /* HSI48 is synchronized with USB SOF at 1KHz rate */ RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000); - RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT; + RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT; /* Set the TRIM[5:0] to the default value*/ - RCC_CRSInitStruct.HSI48CalibrationValue = 0x20; - /* Start automatic synchronization */ + RCC_CRSInitStruct.HSI48CalibrationValue = 0x20; + /* Start automatic synchronization */ HAL_RCCEx_CRSConfig (&RCC_CRSInitStruct); } diff --git a/hw/bsp/stm32l0/family.c b/hw/bsp/stm32l0/family.c index dcd71a513..6bce88b39 100644 --- a/hw/bsp/stm32l0/family.c +++ b/hw/bsp/stm32l0/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32l0/stm32l0xx_hal_conf.h b/hw/bsp/stm32l0/stm32l0xx_hal_conf.h index cc20ea8e0..e3a131043 100644 --- a/hw/bsp/stm32l0/stm32l0xx_hal_conf.h +++ b/hw/bsp/stm32l0/stm32l0xx_hal_conf.h @@ -2,22 +2,22 @@ ****************************************************************************** * @file stm32l0xx_hal_conf.h * @author MCD Application Team - * @brief HAL configuration template file. + * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32l0xx_hal_conf.h. ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. + *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L0xx_HAL_CONF_H @@ -32,9 +32,9 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /*#define HAL_ADC_MODULE_ENABLED */ /*#define HAL_COMP_MODULE_ENABLED */ /*#define HAL_CRC_MODULE_ENABLED */ @@ -69,9 +69,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -90,7 +90,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ @@ -99,7 +99,7 @@ /** * @brief Internal High Speed oscillator for USB (HSI48) value. */ -#if !defined (HSI48_VALUE) +#if !defined (HSI48_VALUE) #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz. The real value may vary depending on the variations in voltage and temperature. */ @@ -108,7 +108,7 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) +#if !defined (LSI_VALUE) #define LSI_VALUE ((uint32_t)37000U) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations @@ -128,24 +128,24 @@ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ - + /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ + */ #define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U +#define TICK_INT_PRIORITY (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U #define PREREAD_ENABLE 0U #define BUFFER_CACHE_DISABLE 0U /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ @@ -191,13 +191,13 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED #include "stm32l0xx_hal_rcc.h" #endif /* HAL_RCC_MODULE_ENABLED */ - + #ifdef HAL_GPIO_MODULE_ENABLED #include "stm32l0xx_hal_gpio.h" #endif /* HAL_GPIO_MODULE_ENABLED */ @@ -233,11 +233,11 @@ #ifdef HAL_FIREWALL_MODULE_ENABLED #include "stm32l0xx_hal_firewall.h" #endif /* HAL_FIREWALL_MODULE_ENABLED */ - + #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32l0xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_I2C_MODULE_ENABLED #include "stm32l0xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ @@ -257,7 +257,7 @@ #ifdef HAL_LPTIM_MODULE_ENABLED #include "stm32l0xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ - + #ifdef HAL_PWR_MODULE_ENABLED #include "stm32l0xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ @@ -316,7 +316,7 @@ * @brief The assert_param macro is used for function's parameters check. * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ @@ -332,7 +332,6 @@ #endif #endif /* __STM32L0xx_HAL_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld b/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld index 79427d80b..033dcc0ad 100644 --- a/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld +++ b/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld @@ -114,7 +114,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -125,7 +125,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -153,7 +153,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -165,5 +165,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32l0538disco/stm32l0538disco.c b/hw/bsp/stm32l0538disco/stm32l0538disco.c index f4c38d150..46f6f0ff6 100644 --- a/hw/bsp/stm32l0538disco/stm32l0538disco.c +++ b/hw/bsp/stm32l0538disco/stm32l0538disco.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h b/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h index 773b74e29..a917214c3 100644 --- a/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h +++ b/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h @@ -7,39 +7,39 @@ * * Copyright (c) 2016 STMicroelectronics International N.V. All rights reserved. * - * Redistribution and use in source and binary forms, with or without + * Redistribution and use in source and binary forms, with or without * modification, are permitted, provided that the following conditions are met: * - * 1. Redistribution of source code must retain the above copyright notice, + * 1. Redistribution of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this + * 4. This software, including modifications and/or derivative works of this * software, must execute solely and exclusively on microcontroller or * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L0xx_HAL_CONF_H @@ -54,36 +54,36 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED // #define HAL_ADC_MODULE_ENABLED -/* #define HAL_COMP_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_COMP_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ #define HAL_DMA_MODULE_ENABLED /* #define HAL_FIREWALL_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED #define HAL_GPIO_MODULE_ENABLED /* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ /* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LCD_MODULE_ENABLED */ +/* #define HAL_LCD_MODULE_ENABLED */ /* #define HAL_LPTIM_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED //#define HAL_RNG_MODULE_ENABLED /* #define HAL_RTC_MODULE_ENABLED */ //#define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ /* #define HAL_TSC_MODULE_ENABLED */ -/* #define HAL_UART_MODULE_ENABLED */ -/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ //#define HAL_PCD_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED /* #define HAL_PCD_MODULE_ENABLED */ @@ -93,9 +93,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -114,7 +114,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ @@ -123,7 +123,7 @@ /** * @brief Internal High Speed oscillator for USB (HSI48) value. */ -#if !defined (HSI48_VALUE) +#if !defined (HSI48_VALUE) #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz. The real value may vary depending on the variations in voltage and temperature. */ @@ -132,7 +132,7 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) +#if !defined (LSI_VALUE) #define LSI_VALUE ((uint32_t)37000U) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations @@ -152,24 +152,24 @@ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ - + /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U #define PREREAD_ENABLE 1U #define BUFFER_CACHE_DISABLE 0U /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1 */ @@ -185,7 +185,7 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -199,7 +199,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32l0xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32l0xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -211,7 +211,7 @@ #ifdef HAL_COMP_MODULE_ENABLED #include "stm32l0xx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ - + #ifdef HAL_CRC_MODULE_ENABLED #include "stm32l0xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ @@ -231,7 +231,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32l0xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_I2C_MODULE_ENABLED #include "stm32l0xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ @@ -251,7 +251,7 @@ #ifdef HAL_LPTIM_MODULE_ENABLED #include "stm32l0xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ - + #ifdef HAL_PWR_MODULE_ENABLED #include "stm32l0xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ @@ -310,7 +310,7 @@ * @brief The assert_param macro is used for function's parameters check. * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ @@ -326,6 +326,6 @@ #endif #endif /* __STM32L0xx_HAL_CONF_H */ - + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld index d4b86b3e3..4ae4a4cf4 100644 --- a/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld +++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld @@ -83,8 +83,8 @@ SECTIONS . = ALIGN(8); } >FLASH - .ARM.extab : - { + .ARM.extab : + { . = ALIGN(8); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(8); @@ -105,7 +105,7 @@ SECTIONS PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(8); } >FLASH - + .init_array : { . = ALIGN(8); @@ -129,7 +129,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(8); _sdata = .; /* create a global symbol at data start */ @@ -140,7 +140,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -168,7 +168,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -180,5 +180,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h index 704d742cc..72d17b760 100644 --- a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h +++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) @@ -94,7 +94,7 @@ static inline void board_clock_init(void) RCC_OscInitStruct.PLL.PLLN = 10; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; - + HAL_RCC_OscConfig(&RCC_OscInitStruct); /** Initializes the CPU, AHB and APB buses clocks @@ -122,7 +122,7 @@ static inline void board_clock_init(void) RCC_CRSInitStruct.HSI48CalibrationValue = 32; HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct); - + /* Select HSI48 output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld index d6865f49d..3bb13ed85 100644 --- a/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld +++ b/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld @@ -82,8 +82,8 @@ SECTIONS . = ALIGN(8); } >FLASH - .ARM.extab : - { + .ARM.extab : + { . = ALIGN(8); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(8); @@ -104,7 +104,7 @@ SECTIONS PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(8); } >FLASH - + .init_array : { . = ALIGN(8); @@ -128,7 +128,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(8); _sdata = .; /* create a global symbol at data start */ @@ -139,7 +139,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -167,7 +167,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -179,5 +179,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - - diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.h b/hw/bsp/stm32l4/boards/stm32l476disco/board.h index 42c657d5e..9d4351b39 100644 --- a/hw/bsp/stm32l4/boards/stm32l476disco/board.h +++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld index c1a490a70..02c07dd74 100644 --- a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld +++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld @@ -102,12 +102,12 @@ SECTIONS . = ALIGN(4); } >ROM - .ARM.extab : { + .ARM.extab : { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >ROM - + .ARM : { . = ALIGN(4); __exidx_start = .; @@ -124,7 +124,7 @@ SECTIONS PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); } >ROM - + .init_array : { . = ALIGN(4); @@ -134,7 +134,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); } >ROM - + .fini_array : { . = ALIGN(4); @@ -149,7 +149,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections into "RAM" Ram type memory */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -158,7 +158,7 @@ SECTIONS . = ALIGN(4); _edata = .; /* define a global symbol at data end */ - + } >RAM AT> ROM /* Uninitialized data section into "RAM" Ram type memory */ diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h index 1df389aed..47ada6bb9 100644 --- a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h +++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld index f77c72d1b..267a87a8b 100644 --- a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld +++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld @@ -114,7 +114,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -125,7 +125,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -153,7 +153,7 @@ SECTIONS . = ALIGN(8); } >RAM - + /* Remove information from the standard libraries */ /DISCARD/ : diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h index 1df389aed..47ada6bb9 100644 --- a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h +++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) diff --git a/hw/bsp/stm32l4/stm32l4xx_hal_conf.h b/hw/bsp/stm32l4/stm32l4xx_hal_conf.h index 312f86da1..25dbc0523 100644 --- a/hw/bsp/stm32l4/stm32l4xx_hal_conf.h +++ b/hw/bsp/stm32l4/stm32l4xx_hal_conf.h @@ -50,7 +50,7 @@ /* #define HAL_NAND_MODULE_ENABLED */ // #define HAL_NOR_MODULE_ENABLED // #define HAL_SRAM_MODULE_ENABLED -/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED //#define HAL_I2C_MODULE_ENABLED /* #define HAL_IRDA_MODULE_ENABLED */ @@ -115,7 +115,7 @@ * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency * which is subject to manufacturing process variations. */ -#if !defined (HSI48_VALUE) +#if !defined (HSI48_VALUE) #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. The real value my vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ @@ -123,7 +123,7 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) +#if !defined (LSI_VALUE) #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations @@ -142,7 +142,7 @@ /** * @brief External clock source for SAI1 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source * frequency. */ #if !defined (EXTERNAL_SAI1_CLOCK_VALUE) @@ -151,7 +151,7 @@ /** * @brief External clock source for SAI2 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source * frequency. */ #if !defined (EXTERNAL_SAI2_CLOCK_VALUE) diff --git a/hw/bsp/stm32u5/stm32u5xx_hal_conf.h b/hw/bsp/stm32u5/stm32u5xx_hal_conf.h index 15dffa813..87c3683de 100644 --- a/hw/bsp/stm32u5/stm32u5xx_hal_conf.h +++ b/hw/bsp/stm32u5/stm32u5xx_hal_conf.h @@ -503,4 +503,3 @@ #endif #endif /* STM32U5xx_HAL_CONF_H */ - diff --git a/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld b/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld index 660f30161..916f11866 100644 --- a/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld +++ b/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld @@ -113,7 +113,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -124,7 +124,7 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM1 AT> FLASH - + /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -152,7 +152,7 @@ SECTIONS . = ALIGN(8); } >RAM1 - + /* Remove information from the standard libraries */ /DISCARD/ : @@ -167,5 +167,3 @@ SECTIONS MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED } - - diff --git a/hw/bsp/stm32wb/family.c b/hw/bsp/stm32wb/family.c index 525d637ea..e9ca59866 100644 --- a/hw/bsp/stm32wb/family.c +++ b/hw/bsp/stm32wb/family.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2022 Jerzy Kasenberg diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk index d60365d1d..0ff24ab60 100644 --- a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk +++ b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk @@ -1,5 +1,5 @@ CFLAGS += -DTM4C123GH6PM - + LD_FILE = $(BOARD_PATH)/tm4c123.ld # For flash-jlink target diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld index e2720a9ac..351857bd6 100644 --- a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld +++ b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld @@ -6,37 +6,37 @@ _Min_Heap_Size = 0; /* required amount of heap */ _Min_Stack_Size = 0x1000; /* required amount of stack */ -MEMORY +MEMORY { FLASH(rx) : ORIGIN = 0x00000000, LENGTH = 256K SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 32K } -SECTIONS +SECTIONS { - .text : + .text : { . = ALIGN(4) ; - *(.vectors) - *(.text) + *(.vectors) + *(.text) *(.text.*) *(.init) *(.fini) *(.rodata) *(.rodata.*) - . = ALIGN(4) ; - __end_text = . ; + . = ALIGN(4) ; + __end_text = . ; } >FLASH - + .data : AT(ADDR(.text) + SIZEOF(.text)) { . = ALIGN(4); - __start_data = . ; + __start_data = . ; __la_data = LOADADDR(.data); - *(.data) + *(.data) *(.data.*) . = ALIGN(4); - __end_data = . ; + __end_data = . ; } >SRAM @@ -47,7 +47,7 @@ SECTIONS __bss_start__ = __start_bss; *(.bss) *(.bss.*) - *(.COMMON) + *(.COMMON) __end_bss = . ; . = ALIGN(4); }>SRAM diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c123/family.c index 87b94289b..3f4f43220 100644 --- a/hw/bsp/tm4c123/family.c +++ b/hw/bsp/tm4c123/family.c @@ -175,4 +175,3 @@ uint32_t board_millis (void) return system_ticks; } #endif - diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.h b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h index 3e2cb9583..2d4764f40 100644 --- a/hw/bsp/xmc4000/boards/xmc4500_relax/board.h +++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021, Ha Thach (tinyusb.org) diff --git a/hw/mcu/bridgetek/ft9xx/Readme.md b/hw/mcu/bridgetek/ft9xx/Readme.md index 1db91058c..adf8fc765 100644 --- a/hw/mcu/bridgetek/ft9xx/Readme.md +++ b/hw/mcu/bridgetek/ft9xx/Readme.md @@ -2,6 +2,6 @@ **BridgeTek** provides a hardware abstraction library with software source code for the SDKs for FT9xx software family. -Whole SDK repository is installed as part of the FT9xx Toolchain and can be downloaded from BridgeTek web page `https://www.brtchip.com`. +Whole SDK repository is installed as part of the FT9xx Toolchain and can be downloaded from BridgeTek web page `https://www.brtchip.com`. -Registers definition files, and included peripheral register definition files have licenses that allow for redistribution. +Registers definition files, and included peripheral register definition files have licenses that allow for redistribution. diff --git a/hw/mcu/bridgetek/ft9xx/scripts/crt0.S b/hw/mcu/bridgetek/ft9xx/scripts/crt0.S index 62fa266ee..380b31c37 100644 --- a/hw/mcu/bridgetek/ft9xx/scripts/crt0.S +++ b/hw/mcu/bridgetek/ft9xx/scripts/crt0.S @@ -50,11 +50,11 @@ _start: codestart: jmp init - + .global _exithook _exithook: # Debugger uses '_exithook' at 0x90 to catch program exit return - + init: # Disable all interrupts ldk $r0,0x80 @@ -63,12 +63,12 @@ init: .else sta.b 0x100e3,$r0 .endif - + # Reset all peripherals # lda.l $r0, 0x10018 # bins.l $r0, $r0, 0x23F # Set bit 31 # sta.l 0x10018, $r0 - + # Initialize DATA by copying from program memory ldk.l $r0,__data_load_start ldk.l $r1,__data_load_end diff --git a/hw/mcu/dialog/README.md b/hw/mcu/dialog/README.md index 69676f081..33d270aac 100644 --- a/hw/mcu/dialog/README.md +++ b/hw/mcu/dialog/README.md @@ -3,7 +3,5 @@ **Dialog Semiconductors** provides SDKs for DA146x MCU family. Most of the files there can't be redistributed. Registers definition file `DA1469xAB.h` and some **ARM** originated headers are have licenses that allow -for redistribution. +for redistribution. Whole SDK repository can be downloaded from Dialog Semiconductor web page `https://www.dialog.com` - - diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt index b324eb286..7e8067a6f 100644 --- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt +++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt @@ -24,4 +24,3 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h index fdb1a971c..8f871ea31 100644 --- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h +++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h @@ -268,4 +268,3 @@ #endif /* __CMSIS_COMPILER_H */ - diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h index 47a4b59d8..812c3789a 100644 --- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h +++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h @@ -47,9 +47,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif @@ -586,7 +586,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. - + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ @@ -631,7 +631,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. - + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ @@ -768,7 +768,7 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) +#if __has_builtin(__builtin_arm_get_fpscr) // Re-enable using built-in when GCC has been fixed // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h index e2cf6b966..a8cd3ea45 100644 --- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h +++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h @@ -62,7 +62,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM0 definitions */ #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h index 7249e1331..05b61383e 100644 --- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h +++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h @@ -2065,7 +2065,7 @@ typedef struct /* Special LR values for Secure/Non-Secure call handling and exception handling */ -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ @@ -2080,7 +2080,7 @@ typedef struct /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else +#else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h index bc3b05109..50bb56333 100644 --- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h +++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h @@ -103,7 +103,7 @@ (MPU_RLAR_EN_Msk)) #if defined(MPU_RLAR_PXN_Pos) - + /** \brief Region Limit Address Register with PXN value * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. @@ -114,7 +114,7 @@ ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ (MPU_RLAR_EN_Msk)) - + #endif /** @@ -124,7 +124,7 @@ typedef struct { uint32_t RBAR; /*!< Region Base Address Register value */ uint32_t RLAR; /*!< Region Limit Address Register value */ } ARM_MPU_Region_t; - + /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ @@ -185,11 +185,11 @@ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t at const uint8_t reg = idx / 4U; const uint32_t pos = ((idx % 4U) * 8U); const uint32_t mask = 0xFFU << pos; - + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { return; // invalid index } - + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); } @@ -236,7 +236,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ +{ ARM_MPU_ClrRegionEx(MPU_NS, rnr); } #endif @@ -246,7 +246,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) { mpu->RNR = rnr; @@ -258,7 +258,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t r * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); @@ -269,10 +269,10 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rla * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) { - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); } #endif @@ -284,7 +284,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; - for (i = 0U; i < len; ++i) + for (i = 0U; i < len; ++i) { dst[i] = src[i]; } @@ -296,7 +296,7 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_ * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; if (cnt == 1U) { @@ -305,7 +305,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ } else { uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - + mpu->RNR = rnrBase; while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { uint32_t c = MPU_TYPE_RALIASES - rnrOffset; @@ -316,7 +316,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ rnrBase += MPU_TYPE_RALIASES; mpu->RNR = rnrBase; } - + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); } } @@ -326,7 +326,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU, rnr, table, cnt); } @@ -337,11 +337,10 @@ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, u * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); } #endif #endif - diff --git a/hw/mcu/dialog/da1469x/da1469x.ld b/hw/mcu/dialog/da1469x/da1469x.ld index c91dea841..0133f3759 100644 --- a/hw/mcu/dialog/da1469x/da1469x.ld +++ b/hw/mcu/dialog/da1469x/da1469x.ld @@ -225,4 +225,3 @@ SECTIONS /* Check that intvect is at the beginning of RAM */ ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM") } - diff --git a/hw/mcu/dialog/da1469x/include/mcu/mcu.h b/hw/mcu/dialog/da1469x/include/mcu/mcu.h index 1e6736785..38961e828 100644 --- a/hw/mcu/dialog/da1469x/include/mcu/mcu.h +++ b/hw/mcu/dialog/da1469x/include/mcu/mcu.h @@ -162,4 +162,3 @@ void mcu_gpio_exit_sleep(void); #endif #endif /* __MCU_MCU_H_ */ - diff --git a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h index 76a432bfd..9ba24f458 100644 --- a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h +++ b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h @@ -539,7 +539,7 @@ SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_v /**@brief Remove a Vendor Specific base UUID. - * + * * @details This call removes a Vendor Specific base UUID that has been added with @ref sd_ble_uuid_vs_add. This function allows * the application to reuse memory allocated for Vendor Specific base UUIDs. * diff --git a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h index c434fefb3..e11149435 100644 --- a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h +++ b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h @@ -1666,7 +1666,7 @@ SVCALL(SD_BLE_GAP_ADDR_GET, uint32_t, sd_ble_gap_addr_get(ble_gap_addr_t *p_addr * * @retval ::NRF_SUCCESS Address successfully retrieved. * @retval ::NRF_ERROR_INVALID_ADDR Invalid or NULL pointer supplied. - * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found. * @retval ::NRF_ERROR_INVALID_STATE The advertising set is currently not advertising. */ SVCALL(SD_BLE_GAP_ADV_ADDR_GET, uint32_t, sd_ble_gap_adv_addr_get(uint8_t adv_handle, ble_gap_addr_t *p_addr)); diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c index a7ae013dd..c8de8e0f3 100644 --- a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c +++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c @@ -62,7 +62,7 @@ Additional information: WrOff == (RdOff - 1): Buffer is full WrOff > RdOff: Free space includes wrap-around WrOff < RdOff: Used space includes wrap-around - (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0): + (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0): Buffer full and wrap-around after next byte @@ -504,7 +504,7 @@ static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) { * Reads characters from SEGGER real-time-terminal control block * which have been previously stored by the application. * Do not lock against interrupts and multiple access. -* Used to do the same operation that J-Link does, to transfer +* Used to do the same operation that J-Link does, to transfer * RTT data via other channels, such as TCP/IP or UART. * * Parameters @@ -693,7 +693,7 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe * Function description * Reads characters from SEGGER real-time-terminal control block * which have been previously stored by the application. -* Used to do the same operation that J-Link does, to transfer +* Used to do the same operation that J-Link does, to transfer * RTT data via other channels, such as TCP/IP or UART. * * Parameters @@ -708,7 +708,7 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe * This function must not be called when J-Link might also do RTT. * This function locks against all other RTT operations. I.e. during * the read operation, writing is also locked. -* If only one consumer reads from the up buffer, +* If only one consumer reads from the up buffer, * call sEGGER_RTT_ReadUpBufferNoLock() instead. */ unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { @@ -766,7 +766,7 @@ unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSiz * Function description * Stores a specified number of characters in SEGGER RTT * control block. -* SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application +* SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application * and overwrites data if the data does not fit into the buffer. * * Parameters @@ -779,7 +779,7 @@ unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSiz * (2) For performance reasons this function does not call Init() * and may only be called after RTT has been initialized. * Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -* (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link +* (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link * connection reads RTT data. */ void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { @@ -946,7 +946,7 @@ CopyStraight: * Stores a specified number of characters in SEGGER RTT * control block inside a buffer. * SEGGER_RTT_WriteDownBufferNoLock does not lock the application. -* Used to do the same operation that J-Link does, to transfer +* Used to do the same operation that J-Link does, to transfer * RTT data from other channels, such as TCP/IP or UART. * * Parameters @@ -1116,7 +1116,7 @@ unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsig * This function must not be called when J-Link might also do RTT. * This function locks against all other RTT operations. I.e. during * the write operation, writing from the application is also locked. -* If only one consumer writes to the down buffer, +* If only one consumer writes to the down buffer, * call SEGGER_RTT_WriteDownBufferNoLock() instead. */ unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT.h b/lib/SEGGER_RTT/RTT/SEGGER_RTT.h index 3c04df55f..07eb4f39e 100644 --- a/lib/SEGGER_RTT/RTT/SEGGER_RTT.h +++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT.h @@ -44,7 +44,7 @@ ---------------------------END-OF-HEADER------------------------------ File : SEGGER_RTT.h Purpose : Implementation of SEGGER real-time transfer which allows - real-time communication on targets which support debugger + real-time communication on targets which support debugger memory accesses while the CPU is running. Revision: $Rev: 17697 $ ---------------------------------------------------------------------- diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S b/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S index 78cde4d75..aec372eec 100644 --- a/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S +++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S @@ -36,9 +36,9 @@ Additional information: #define _THUMB_CODE .code 16 #define _WORD .word #define _SECTION(Sect, Type, AlignExp) .section Sect ##, "ax" - #define _ALIGN(Exp) .align Exp + #define _ALIGN(Exp) .align Exp #define _PLACE_LITS .ltorg - #define _DATA_SECT_START + #define _DATA_SECT_START #define _C_STARTUP _start #define _STACK_END __stack_end__ #define _RAMFUNC @@ -58,7 +58,7 @@ Additional information: #define _THUMB_CODE THUMB #define _WORD DCD #define _SECTION(Sect, Type, AlignExp) SECTION Sect ## : ## Type ## :REORDER:NOROOT ## (AlignExp) - #define _ALIGN(Exp) alignrom Exp + #define _ALIGN(Exp) alignrom Exp #define _PLACE_LITS #define _DATA_SECT_START DATA #define _C_STARTUP __iar_program_start diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h b/lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h index 5e79d7e67..fda5a5f51 100644 --- a/lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h +++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h @@ -91,12 +91,12 @@ Revision: $Rev: 18601 $ * * RTT memcpy configuration * -* memcpy() is good for large amounts of data, +* memcpy() is good for large amounts of data, * but the overhead is big for small amounts, which are usually stored via RTT. * With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. * * SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. -* This is may be required with memory access restrictions, +* This is may be required with memory access restrictions, * such as on Cortex-A devices with MMU. */ #ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP @@ -105,7 +105,7 @@ Revision: $Rev: 18601 $ // // Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets // -//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) +//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) // #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) //#endif @@ -204,7 +204,7 @@ Revision: $Rev: 18601 $ : \ : \ ); - + #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ "or %0, %0, a1 \n\t" \ "csrs mstatus, %0 \n\t" \ @@ -345,8 +345,8 @@ Revision: $Rev: 18601 $ #define SEGGER_RTT_LOCK() { \ unsigned long LockState; \ LockState = get_psw() & 0x010000; \ - clrpsw_i(); - + clrpsw_i(); + #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | LockState); \ } #endif diff --git a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c index da4a4b5f5..6bf670a02 100644 --- a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c +++ b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c @@ -44,7 +44,7 @@ ---------------------------END-OF-HEADER------------------------------ File : SEGGER_RTT_Syscalls_GCC.c Purpose : Low-level functions for using printf() via RTT in GCC. - To use RTT for printf output, include this file in your + To use RTT for printf output, include this file in your application. Revision: $Rev: 17697 $ ---------------------------------------------------------------------- @@ -62,7 +62,7 @@ Revision: $Rev: 17697 $ ********************************************************************** */ // -// If necessary define the _reent struct +// If necessary define the _reent struct // to match the one passed by the used standard library. // struct _reent; diff --git a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c index f7f5aed48..ba9772d3e 100644 --- a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c +++ b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c @@ -110,7 +110,7 @@ const char __stderr_name[] = "STDERR"; * * Parameters: * c - character to output -* +* */ void _ttywrch(int c) { fputc(c, stdout); // stdout @@ -127,9 +127,9 @@ void _ttywrch(int c) { * Parameters: * sName - sName of the device/file to open * OpenMode - This parameter is currently ignored -* +* * Return value: -* != 0 - Handle to the object to open, otherwise +* != 0 - Handle to the object to open, otherwise * == 0 -"device" is not handled by this module * */ @@ -153,7 +153,7 @@ FILEHANDLE _sys_open(const char * sName, int OpenMode) { * * Parameters: * hFile - Handle to a file opened via _sys_open -* +* * Return value: * 0 - device/file closed * @@ -176,7 +176,7 @@ int _sys_close(FILEHANDLE hFile) { * pBuffer - Pointer to the data that shall be written * NumBytes - Number of bytes to write * Mode - The Mode that shall be used -* +* * Return value: * Number of bytes *not* written to the file/device * @@ -205,7 +205,7 @@ int _sys_write(FILEHANDLE hFile, const unsigned char * pBuffer, unsigned NumByte * pBuffer - Pointer to buffer to store the read data * NumBytes - Number of bytes to read * Mode - The Mode that shall be used -* +* * Return value: * Number of bytes read from the file/device * @@ -223,12 +223,12 @@ int _sys_read(FILEHANDLE hFile, unsigned char * pBuffer, unsigned NumBytes, int * _sys_istty * * Function description: -* This function shall return whether the opened file +* This function shall return whether the opened file * is a console device or not. * * Parameters: * hFile - Handle to a file opened via _sys_open -* +* * Return value: * 1 - Device is a console * 0 - Device is not a console @@ -250,10 +250,10 @@ int _sys_istty(FILEHANDLE hFile) { * * Parameters: * hFile - Handle to a file opened via _sys_open -* Pos - -* +* Pos - +* * Return value: -* int - +* int - * */ int _sys_seek(FILEHANDLE hFile, long Pos) { @@ -267,13 +267,13 @@ int _sys_seek(FILEHANDLE hFile, long Pos) { * _sys_ensure * * Function description: -* +* * * Parameters: * hFile - Handle to a file opened via _sys_open -* +* * Return value: -* int - +* int - * */ int _sys_ensure(FILEHANDLE hFile) { @@ -290,7 +290,7 @@ int _sys_ensure(FILEHANDLE hFile) { * * Parameters: * hFile - Handle to a file opened via _sys_open -* +* * Return value: * Length of the file * @@ -305,17 +305,17 @@ long _sys_flen(FILEHANDLE hFile) { * _sys_tmpnam * * Function description: -* This function converts the file number fileno for a temporary +* This function converts the file number fileno for a temporary * file to a unique filename, for example, tmp0001. * * Parameters: * pBuffer - Pointer to a buffer to store the name * FileNum - file number to convert * MaxLen - Size of the buffer -* +* * Return value: * 1 - Error -* 0 - Success +* 0 - Success * */ int _sys_tmpnam(char * pBuffer, int FileNum, unsigned MaxLen) { @@ -335,7 +335,7 @@ int _sys_tmpnam(char * pBuffer, int FileNum, unsigned MaxLen) { * Parameters: * cmd - Pointer to the command string * len - Length of the string -* +* * Return value: * == NULL - Command was not successfully executed * == sCmd - Command was passed successfully @@ -355,7 +355,7 @@ char * _sys_command_string(char * cmd, int len) { * * Parameters: * ReturnCode - Return code from the main function -* +* * */ void _sys_exit(int ReturnCode) { @@ -373,7 +373,7 @@ void _sys_exit(int ReturnCode) { * * Parameters: * ch - Character to output -* +* * */ int stdout_putchar(int ch) { diff --git a/lib/fatfs/source/00history.txt b/lib/fatfs/source/00history.txt index 7a153a229..f7898cbd9 100644 --- a/lib/fatfs/source/00history.txt +++ b/lib/fatfs/source/00history.txt @@ -366,4 +366,3 @@ R0.15 (November 6, 2022) Fixed f_mkfs() creates broken exFAT volume when the size of volume is >= 2^32 sectors. Fixed string functions cannot write the unicode characters not in BMP when FF_LFN_UNICODE == 2 (UTF-8). Fixed a compatibility issue in identification of GPT header. - diff --git a/lib/fatfs/source/00readme.txt b/lib/fatfs/source/00readme.txt index 3de3aeaa2..48c02a42d 100644 --- a/lib/fatfs/source/00readme.txt +++ b/lib/fatfs/source/00readme.txt @@ -18,4 +18,3 @@ FILES module is only a generic file system layer and it does not depend on any specific storage device. You need to provide a low level disk I/O module written to control the storage device that attached to the target system. - diff --git a/lib/fatfs/source/diskio.c b/lib/fatfs/source/diskio.c index 179e387a2..3cb423db3 100644 --- a/lib/fatfs/source/diskio.c +++ b/lib/fatfs/source/diskio.c @@ -226,4 +226,3 @@ DRESULT disk_ioctl ( return RES_PARERR; } - diff --git a/lib/fatfs/source/ff.c b/lib/fatfs/source/ff.c index 6d412fa0e..05ca02f0a 100644 --- a/lib/fatfs/source/ff.c +++ b/lib/fatfs/source/ff.c @@ -7081,4 +7081,3 @@ FRESULT f_setcp ( return FR_OK; } #endif /* FF_CODE_PAGE == 0 */ - diff --git a/lib/fatfs/source/ffsystem.c b/lib/fatfs/source/ffsystem.c index d5c5134bf..bc0047dce 100644 --- a/lib/fatfs/source/ffsystem.c +++ b/lib/fatfs/source/ffsystem.c @@ -205,4 +205,3 @@ void ff_mutex_give ( } #endif /* FF_FS_REENTRANT */ - diff --git a/lib/networking/dhserver.c b/lib/networking/dhserver.c index 8cd22ddb9..2f14f7a09 100644 --- a/lib/networking/dhserver.c +++ b/lib/networking/dhserver.c @@ -2,17 +2,17 @@ * The MIT License (MIT) * * Copyright (c) 2015 by Sergey Fetisov - * + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE @@ -267,7 +267,7 @@ static void udp_recv_proc(void *arg, struct udp_pcb *upcb, struct pbuf *p, const DHCP_OFFER, config->domain, config->dns, - entry->lease, + entry->lease, *netif_ip4_addr(netif), config->router, *netif_ip4_netmask(netif)); @@ -309,7 +309,7 @@ static void udp_recv_proc(void *arg, struct udp_pcb *upcb, struct pbuf *p, const DHCP_ACK, config->domain, config->dns, - entry->lease, + entry->lease, *netif_ip4_addr(netif), config->router, *netif_ip4_netmask(netif)); diff --git a/lib/networking/dhserver.h b/lib/networking/dhserver.h index 2a0b15854..b3642459a 100644 --- a/lib/networking/dhserver.h +++ b/lib/networking/dhserver.h @@ -2,17 +2,17 @@ * The MIT License (MIT) * * Copyright (c) 2015 by Sergey Fetisov - * + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE diff --git a/lib/networking/dnserver.c b/lib/networking/dnserver.c index 539cc2cea..6d15fee02 100644 --- a/lib/networking/dnserver.c +++ b/lib/networking/dnserver.c @@ -2,17 +2,17 @@ * The MIT License (MIT) * * Copyright (c) 2015 by Sergey Fetisov - * + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE @@ -165,7 +165,7 @@ static void udp_recv_proc(void *arg, struct udp_pcb *upcb, struct pbuf *p, const answer->ttl = htonl(32); answer->len = htons(4); answer->addr = host_addr.addr; - + udp_sendto(upcb, out, addr, port); pbuf_free(out); diff --git a/lib/networking/dnserver.h b/lib/networking/dnserver.h index a062e3aa7..50b29be89 100644 --- a/lib/networking/dnserver.h +++ b/lib/networking/dnserver.h @@ -2,17 +2,17 @@ * The MIT License (MIT) * * Copyright (c) 2015 by Sergey Fetisov - * + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE diff --git a/lib/networking/ndis.h b/lib/networking/ndis.h index 06258e6bb..29b07749c 100644 --- a/lib/networking/ndis.h +++ b/lib/networking/ndis.h @@ -16,14 +16,14 @@ */ /* - * ndis.h - * + * ndis.h + * * Modified by Colin O'Flynn * ntddndis.h modified by Benedikt Spranger - * - * Thanks to the cygwin development team, + * + * Thanks to the cygwin development team, * especially to Casper S. Hornstrup - * + * * THIS SOFTWARE IS NOT COPYRIGHTED * * This source code is offered for use in the public domain. You may diff --git a/lib/networking/rndis_protocol.h b/lib/networking/rndis_protocol.h index b45860eeb..3d07d6fa3 100644 --- a/lib/networking/rndis_protocol.h +++ b/lib/networking/rndis_protocol.h @@ -39,7 +39,7 @@ #ifndef _RNDIS_H #define _RNDIS_H -/** +/** \addtogroup RNDIS @{ */ @@ -112,7 +112,7 @@ typedef struct{ rndis_MinorVersion_t MinorVersion; rndis_MaxTransferSize_t MaxTransferSize; } rndis_initialize_msg_t; - + /* Response: */ typedef struct{ rndis_MessageType_t MessageType; @@ -129,7 +129,7 @@ typedef struct{ rndis_AfListOffset_t AfListOffset; rndis_AfListSize_t AfListSize; } rndis_initialize_cmplt_t; - + /*** Remote NDIS Halt Message ***/ typedef struct{ @@ -137,7 +137,7 @@ typedef struct{ rndis_MessageLength_t MessageLength; rndis_RequestId_t RequestId; } rndis_halt_msg_t; - + typedef uint32_t rndis_Oid_t; typedef uint32_t rndis_InformationBufferLength_t; typedef uint32_t rndis_InformationBufferOffset_t; @@ -153,7 +153,7 @@ typedef struct{ rndis_InformationBufferOffset_t InformationBufferOffset; rndis_DeviceVcHandle_t DeviceVcHandle; } rndis_query_msg_t; - + /* Response: */ typedef struct{ @@ -164,7 +164,7 @@ typedef struct{ rndis_InformationBufferLength_t InformationBufferLength; rndis_InformationBufferOffset_t InformationBufferOffset; } rndis_query_cmplt_t; - + /*** Remote NDIS Set Message ***/ typedef struct{ rndis_MessageType_t MessageType; @@ -175,7 +175,7 @@ typedef struct{ rndis_InformationBufferOffset_t InformationBufferOffset; rndis_DeviceVcHandle_t DeviceVcHandle; } rndis_set_msg_t; - + /* Response */ typedef struct{ rndis_MessageType_t MessageType; @@ -199,9 +199,9 @@ typedef struct{ rndis_ParameterNameLength_t ParameterNameLength; rndis_ParameterType_t ParameterType; rndis_ParameterValueOffset_t ParameterValueOffset; - rndis_ParameterValueLength_t ParameterValueLength; + rndis_ParameterValueLength_t ParameterValueLength; }rndis_config_parameter_t; - + typedef uint32_t rndis_Reserved_t; /*** Remote NDIS Soft Reset Message ***/ @@ -210,7 +210,7 @@ typedef struct{ rndis_MessageLength_t MessageLength; rndis_Reserved_t Reserved; } rndis_reset_msg_t; - + typedef uint32_t rndis_AddressingReset_t; /* Response: */ @@ -220,7 +220,7 @@ typedef struct{ rndis_Status_t Status; rndis_AddressingReset_t AddressingReset; } rndis_reset_cmplt_t; - + /*** Remote NDIS Indicate Status Message ***/ typedef struct{ rndis_MessageType_t MessageType; @@ -229,7 +229,7 @@ typedef struct{ rndis_Status_t StatusBufferLength; rndis_Status_t StatusBufferOffset; } rndis_indicate_status_t; - + typedef uint32_t rndis_DiagStatus_t; typedef uint32_t rndis_ErrorOffset_t; @@ -237,14 +237,14 @@ typedef struct { rndis_DiagStatus_t DiagStatus; rndis_ErrorOffset_t ErrorOffset; }rndis_diagnostic_info_t; - + /*** Remote NDIS Keepalive Message */ typedef struct{ rndis_MessageType_t MessageType; rndis_MessageLength_t MessageLength; rndis_RequestId_t RequestId; }rndis_keepalive_msg_t; - + /* Response: */ typedef struct{ rndis_MessageType_t MessageType; diff --git a/lib/networking/rndis_reports.c b/lib/networking/rndis_reports.c index d129466c8..cc14f174c 100644 --- a/lib/networking/rndis_reports.c +++ b/lib/networking/rndis_reports.c @@ -7,17 +7,17 @@ * The MIT License (MIT) * * Copyright (c) 2015 by Sergey Fetisov - * + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE @@ -45,7 +45,7 @@ static rndis_state_t rndis_state; CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t ndis_report[8] = { 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }; -static const uint32_t OIDSupportedList[] = +static const uint32_t OIDSupportedList[] = { OID_GEN_SUPPORTED_LIST, OID_GEN_HARDWARE_STATUS, @@ -203,8 +203,8 @@ static void rndis_handle_set_msg(void) { rndis_packetFilter(oid_packet_filter); rndis_state = rndis_data_initialized; - } - else + } + else { rndis_state = rndis_initialized; } @@ -266,7 +266,7 @@ void rndis_class_set_handler(uint8_t *data, int size) case REMOTE_NDIS_QUERY_MSG: rndis_query(); break; - + case REMOTE_NDIS_SET_MSG: rndis_handle_set_msg(); break; diff --git a/src/class/audio/audio.h b/src/class/audio/audio.h index ba497906b..70d431282 100644 --- a/src/class/audio/audio.h +++ b/src/class/audio/audio.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -824,10 +824,10 @@ typedef struct TU_ATTR_PACKED uint8_t type : 2; ///< Request type tusb_request_type_t. uint8_t direction : 1; ///< Direction type. tusb_dir_t } bmRequestType_bit; - + uint8_t bmRequestType; }; - + uint8_t bRequest; ///< Request type audio_cs_req_t uint8_t bChannelNumber; uint8_t bControlSelector; diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index f21dfee64..32ba5761e 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Reinhard Panhuber, Jerzy Kasenberg @@ -1525,7 +1525,7 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin #endif } } - + } } p_desc = tu_desc_next(p_desc); @@ -2124,7 +2124,7 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3 { if (tud_audio_fb_done_cb) tud_audio_fb_done_cb(func_id); - // Schedule a transmit with the new value if EP is not busy + // Schedule a transmit with the new value if EP is not busy if (!usbd_edpt_busy(rhport, audio->ep_fb)) { // Schedule next transmission - value is changed bytud_audio_n_fb_set() in the meantime or the old value gets sent diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h index 0ef100fa4..7c88b99fc 100644 --- a/src/class/audio/audio_device.h +++ b/src/class/audio/audio_device.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Ha Thach (tinyusb.org) @@ -473,7 +473,7 @@ TU_ATTR_WEAK void tud_audio_fb_done_cb(uint8_t func_id); // the choice of format is left to the caller and feedback argument is sent as-is. If CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION is set, then tinyusb // expects 16.16 format and handles the conversion to 10.14 on FS. // -// Note that due to a bug in its USB Audio 2.0 driver, Windows currently requires 16.16 format for _all_ USB 2.0 devices. On Linux and macOS it seems the +// Note that due to a bug in its USB Audio 2.0 driver, Windows currently requires 16.16 format for _all_ USB 2.0 devices. On Linux and macOS it seems the // driver can work with either format. So a good compromise is to keep format correction disabled and stick to 16.16 format. // Feedback value can be determined from within the SOF ISR of the audio driver. This should reduce jitter. If the feature is used, the user can not set the feedback value. diff --git a/src/class/bth/bth_device.h b/src/class/bth/bth_device.h index 1b90d0915..921bd7a1a 100755 --- a/src/class/bth/bth_device.h +++ b/src/class/bth/bth_device.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Jerzy Kasenberg diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index f372fe462..a82ef1d62 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -386,7 +386,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t bool const rts = tu_bit_test(request->wValue, 1); p_cdc->line_state = (uint8_t) request->wValue; - + // Disable fifo overwriting if DTR bit is set tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr); @@ -433,7 +433,7 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_ if ( ep_addr == p_cdc->ep_out ) { tu_fifo_write_n(&p_cdc->rx_ff, p_cdc->epout_buf, (uint16_t) xferred_bytes); - + // Check for wanted char and invoke callback if needed if ( tud_cdc_rx_wanted_cb && (((signed char) p_cdc->wanted_char) != -1) ) { @@ -445,14 +445,14 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_ } } } - + // invoke receive callback (if there is still data) if (tud_cdc_rx_cb && !tu_fifo_empty(&p_cdc->rx_ff) ) tud_cdc_rx_cb(itf); - + // prepare for OUT transaction _prep_out_transaction(p_cdc); } - + // Data sent to host, we continue to fetch from tx fifo to send. // Note: This will cause incorrect baudrate set in line coding. // Though maybe the baudrate is not really important !!! diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h index f8a004df4..a6e07aa5c 100644 --- a/src/class/cdc/cdc_device.h +++ b/src/class/cdc/cdc_device.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index c759527e6..4090d0e9f 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/class/cdc/cdc_rndis.h b/src/class/cdc/cdc_rndis.h index e0f129fe3..ad153e0ac 100644 --- a/src/class/cdc/cdc_rndis.h +++ b/src/class/cdc/cdc_rndis.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/class/cdc/cdc_rndis_host.c b/src/class/cdc/cdc_rndis_host.c index 44de85b45..41d21bbad 100644 --- a/src/class/cdc/cdc_rndis_host.c +++ b/src/class/cdc/cdc_rndis_host.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/class/cdc/cdc_rndis_host.h b/src/class/cdc/cdc_rndis_host.h index 447cc4e97..bb431ec1f 100644 --- a/src/class/cdc/cdc_rndis_host.h +++ b/src/class/cdc/cdc_rndis_host.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h index d9b0ead10..fbd3eef38 100644 --- a/src/class/hid/hid.h +++ b/src/class/hid/hid.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/class/midi/midi.h b/src/class/midi/midi.h index 74dc41749..8b78c6555 100644 --- a/src/class/midi/midi.h +++ b/src/class/midi/midi.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c index 5dea43431..e3e7826da 100644 --- a/src/class/midi/midi_device.c +++ b/src/class/midi/midi_device.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/class/midi/midi_device.h b/src/class/midi/midi_device.h index 211edc8d1..1c6f996be 100644 --- a/src/class/midi/midi_device.h +++ b/src/class/midi/midi_device.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/class/msc/msc.h b/src/class/msc/msc.h index 84b6e4d79..7f25a29ba 100644 --- a/src/class/msc/msc.h +++ b/src/class/msc/msc.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/class/msc/msc_device.h b/src/class/msc/msc_device.h index 5839b168d..72f95be06 100644 --- a/src/class/msc/msc_device.h +++ b/src/class/msc/msc_device.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c index 6724e486c..2fddeb818 100644 --- a/src/class/msc/msc_host.c +++ b/src/class/msc/msc_host.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -232,23 +232,23 @@ bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, msc_cbw_t cbw; cbw_init(&cbw, lun); - + cbw.total_bytes = block_count*p_msc->capacity[lun].block_size; cbw.dir = TUSB_DIR_IN_MASK; cbw.cmd_len = sizeof(scsi_read10_t); - + scsi_read10_t const cmd_read10 = { .cmd_code = SCSI_CMD_READ_10, .lba = tu_htonl(lba), .block_count = tu_htons(block_count) }; - + memcpy(cbw.command, &cmd_read10, cbw.cmd_len); - + return tuh_msc_scsi_command(dev_addr, &cbw, buffer, complete_cb, arg); } - + bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) { msch_interface_t* p_msc = get_itf(dev_addr); diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h index 5134b63c2..6c0e5c9dd 100644 --- a/src/class/msc/msc_host.h +++ b/src/class/msc/msc_host.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c index a072bfd79..8ac7cbd01 100644 --- a/src/class/net/ecm_rndis_device.c +++ b/src/class/net/ecm_rndis_device.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Peter Lawrence diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c index aa13c9535..9e9580249 100644 --- a/src/class/net/ncm_device.c +++ b/src/class/net/ncm_device.c @@ -430,7 +430,7 @@ static void handle_incoming_datagram(uint32_t len) { ncm_interface.num_datagrams++; } - + tud_network_recv_renew(); } diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h index 6e294465b..133689deb 100644 --- a/src/class/net/net_device.h +++ b/src/class/net/net_device.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Peter Lawrence diff --git a/src/class/usbtmc/usbtmc.h b/src/class/usbtmc/usbtmc.h index fd52d766e..3c5e86d4c 100644 --- a/src/class/usbtmc/usbtmc.h +++ b/src/class/usbtmc/usbtmc.h @@ -316,4 +316,3 @@ typedef struct TU_ATTR_PACKED TU_VERIFY_STATIC(sizeof(usbtmc_read_stb_interrupt_488_t) == 2u, "struct wrong length"); #endif - diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index a4e6eaeb3..8dbda14c5 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -83,7 +83,7 @@ tu_static char logMsg[150]; // Buffer size must be an exact multiple of the max packet size for both // bulk (up to 64 bytes for FS, 512 bytes for HS). In addation, this driver -// imposes a minimum buffer size of 32 bytes. +// imposes a minimum buffer size of 32 bytes. #define USBTMCD_BUFFER_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) /* @@ -598,7 +598,7 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request uint32_t ep_addr = (request->wIndex); // At this point, a transfer MAY be in progress. Based on USB spec, when clearing bulk EP HALT, - // the EP transfer buffer needs to be cleared and DTOG needs to be reset, even if + // the EP transfer buffer needs to be cleared and DTOG needs to be reset, even if // the EP is not halted. The only USBD API interface to do this is to stall and then un-stall the EP. if(ep_addr == usbtmc_state.ep_bulk_out) { diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h index 2bb6afa67..9abafda50 100644 --- a/src/class/vendor/vendor_device.h +++ b/src/class/vendor/vendor_device.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/class/vendor/vendor_host.c b/src/class/vendor/vendor_host.c index dbea1228d..e66c5007f 100644 --- a/src/class/vendor/vendor_host.c +++ b/src/class/vendor/vendor_host.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/class/vendor/vendor_host.h b/src/class/vendor/vendor_host.h index 65223fbca..acfebe7a4 100644 --- a/src/class/vendor/vendor_host.h +++ b/src/class/vendor/vendor_host.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 02a490aee..d6e98602b 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021 Koji KITAYAMA diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index 30478ba6d..1057d7ca3 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -239,7 +239,7 @@ #define TU_BSWAP16(u16) ((unsigned short)_builtin_revw((unsigned long)u16)) #define TU_BSWAP32(u32) (_builtin_revl(u32)) -#else +#else #error "Compiler attribute porting is required" #endif diff --git a/src/common/tusb_timeout.h b/src/common/tusb_timeout.h index ce53955f0..533e67ab8 100644 --- a/src/common/tusb_timeout.h +++ b/src/common/tusb_timeout.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h index a52a6d269..12355e8be 100644 --- a/src/common/tusb_verify.h +++ b/src/common/tusb_verify.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/device/dcd.h b/src/device/dcd.h index 93170732f..00419ff05 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/device/usbd.c b/src/device/usbd.c index 7733cc2e2..0fb236a88 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1398,11 +1398,11 @@ bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep uint8_t const epnum = tu_edpt_number(desc_ep->bEndpointAddress); uint8_t const dir = tu_edpt_dir(desc_ep->bEndpointAddress); - + TU_ASSERT(dcd_edpt_iso_activate); TU_ASSERT(epnum < CFG_TUD_ENDPPOINT_MAX); TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed)); - + _usbd_dev.ep_status[epnum][dir].stalled = false; _usbd_dev.ep_status[epnum][dir].busy = false; _usbd_dev.ep_status[epnum][dir].claimed = false; diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h index f860ab0a1..8393d3469 100644 --- a/src/device/usbd_pvt.h +++ b/src/device/usbd_pvt.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/host/hcd.h b/src/host/hcd.h index a400626e4..623c12a12 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/host/hub.c b/src/host/hub.c index 3da5358b2..b84042fb6 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -202,7 +202,7 @@ bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer, 0); - + TU_ASSERT(tuh_edpt_open(dev_addr, desc_ep)); hub_interface_t* p_hub = get_itf(dev_addr); diff --git a/src/host/usbh.h b/src/host/usbh.h index 37de7093c..7942de5c2 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/osal/osal.h b/src/osal/osal.h index afa3826fc..f092e8ffb 100644 --- a/src/osal/osal.h +++ b/src/osal/osal.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index 9393d1f26..477f64892 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h index 2e2b3c7ce..5f407378e 100644 --- a/src/osal/osal_none.h +++ b/src/osal/osal_none.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/osal/osal_pico.h b/src/osal/osal_pico.h index 8b428d642..e6efa0968 100644 --- a/src/osal/osal_pico.h +++ b/src/osal/osal_pico.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. diff --git a/src/osal/osal_rtx4.h b/src/osal/osal_rtx4.h index dea1c12c8..e443135e0 100644 --- a/src/osal/osal_rtx4.h +++ b/src/osal/osal_rtx4.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021 Tian Yunhao (t123yh) @@ -115,7 +115,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd os_mbx_declare(_name##__mbox, _depth); \ _declare_box(_name##__pool, sizeof(_type), _depth); \ osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .pool = _name##__pool, .mbox = _name##__mbox }; - + typedef struct { diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c index efca5bdcb..95dfda49c 100644 --- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c +++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright 2021 Bridgetek Pte Ltd @@ -24,15 +24,15 @@ * This file is part of the TinyUSB stack. */ -/* - * Contains code adapted from Bridgetek Pte Ltd via license terms stated +/* + * Contains code adapted from Bridgetek Pte Ltd via license terms stated * in https://brtchip.com/BRTSourceCodeLicenseAgreement */ #include "tusb_option.h" #if CFG_TUD_ENABLED && \ - (CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X) + (CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X) #include #include @@ -58,7 +58,7 @@ struct ft9xx_xfer_state { volatile uint8_t ready; // OUT Transfer has been received and waiting for transfer. volatile uint8_t valid; // Transfer is pending and total_size, remain_size, and buff_ptr are valid. - + int16_t total_size; // Total transfer size in bytes for this transfer. int16_t remain_size; // Total remaining in transfer. uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to. @@ -92,7 +92,7 @@ static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len // Manage an OUT transfer from the host. // This can be up-to the maximum packet size of the endpoint. -// Continuation of a transfer beyond the maximum packet size is performed +// Continuation of a transfer beyond the maximum packet size is performed // by the interrupt handler. static uint16_t _ft9xx_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes) { @@ -125,7 +125,7 @@ static uint16_t _ft9xx_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_ // Manage an IN transfer to the host. // This can be up-to the maximum packet size of the endpoint. -// Continuation of a transfer beyond the maximum packet size is performed +// Continuation of a transfer beyond the maximum packet size is performed // by the interrupt handler. static uint16_t _ft9xx_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes) { @@ -196,7 +196,7 @@ static uint16_t _ft9xx_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t return xfer_bytes; } -// Reset all non-control endpoints to a default state. +// Reset all non-control endpoints to a default state. // Control endpoint is always enabled and ready. All others disabled. static void _ft9xx_reset_edpts(void) { @@ -208,7 +208,7 @@ static void _ft9xx_reset_edpts(void) // Disable hardware. USBD_EP_CR_REG(i) = 0; } - + // Enable interrupts from USB device control. USBD_REG(cmie) = MASK_USBD_CMIE_ALL; } @@ -319,7 +319,7 @@ static void _dcd_ft9xx_detach(void) } // Determine the speed of the USB to which we are connected. -// Set the speed of the PHY accordingly. +// Set the speed of the PHY accordingly. // High speed can be disabled through CFG_TUSB_RHPORT0_MODE or CFG_TUD_MAX_SPEED settings. static void _ft9xx_usb_speed(void) { @@ -379,16 +379,16 @@ static void _ft9xx_usb_speed(void) } // Send a buffer to the USB IN FIFO. -// When the macro USBD_USE_STREAMS is defined this will stream a buffer of data +// When the macro USBD_USE_STREAMS is defined this will stream a buffer of data // to the FIFO using the most efficient MCU streamout combination. -// If streaming is disabled then it will send each byte of the buffer in turn +// If streaming is disabled then it will send each byte of the buffer in turn // to the FIFO. The is no reason to not stream. // The total number of bytes sent to the FIFO is returned. static uint16_t _ft9xx_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length) { uint16_t bytes_read = 0; uint16_t buff_size = length; - + #ifdef USBD_USE_STREAMS volatile uint8_t *data_reg; @@ -423,7 +423,7 @@ static uint16_t _ft9xx_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_ bytes_read = buff_size; } #else // USBD_USE_STREAMS - + bytes_read = buff_size; while (buff_size--) { @@ -438,7 +438,7 @@ static uint16_t _ft9xx_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_ // Receive a buffer from the USB OUT FIFO. // When the macro USBD_USE_STREAMS is defined this will stream from the FIFO // to a buffer of data using the most efficient MCU streamin combination. -// If streaming is disabled then it will receive each byte from the FIFO in turn +// If streaming is disabled then it will receive each byte from the FIFO in turn // to the buffer. The is no reason to not stream. // The total number of bytes received from the FIFO is returned. static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length) @@ -448,7 +448,7 @@ static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len #endif // USBD_USE_STREAMS uint16_t bytes_read = 0; uint16_t buff_size = length; - + if (length > 0) { if (ep_number == USBD_EP_0) @@ -596,7 +596,7 @@ void dcd_remote_wakeup(uint8_t rhport) SYS->MSC0CFG = SYS->MSC0CFG | MASK_SYS_MSC0CFG_DEV_RMWAKEUP; // At least 2 ms of delay needed for RESUME Data K state. - delayms(2); + delayms(2); SYS->MSC0CFG &= ~MASK_SYS_MSC0CFG_DEV_RMWAKEUP; @@ -621,7 +621,7 @@ void dcd_connect(uint8_t rhport) // Determine bus speed and signal speed to tusb. _ft9xx_usb_speed(); } - + // Setup the control endpoint only. #if CFG_TUD_ENDPOINT0_SIZE == 64 USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_64 << BIT_USBD_EP0_MAX_SIZE); @@ -702,7 +702,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) TU_LOG1("FT9xx endpoint size not valid: requested %d max 1024\r\n", ep_size); return false; } - // Calculate actual amount of buffer RAM used by this endpoint. This may be more than the + // Calculate actual amount of buffer RAM used by this endpoint. This may be more than the // requested size. ep_buff_size = 8 << ep_reg_size; @@ -714,7 +714,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) if (ep_xfer[ep_number].type != USBD_EP_TYPE_DISABLED) { // This could be because an endpoint has been assigned with the same number. - // On FT9xx, IN and OUT endpoints may not have the same number. e.g. There + // On FT9xx, IN and OUT endpoints may not have the same number. e.g. There // cannot been an 0x81 and 0x01 endpoint. TU_LOG1("FT9xx endpoint %d already assigned\r\n", ep_number); return false; @@ -723,7 +723,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) // Check that there is enough buffer RAM to allocate to this new endpoint. // Available buffer RAM depends on the device revision. // The IN and OUT buffer RAM should be the same size. - if (ep_dir == USBD_DIR_IN) + if (ep_dir == USBD_DIR_IN) total_ram = USBD_RAMTOTAL_IN; else total_ram = USBD_RAMTOTAL_OUT; @@ -753,7 +753,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) if (total_ram < ep_buff_size) { TU_LOG1("FT9xx insufficient buffer RAM for endpoint %d\r\n", ep_number); - return false; + return false; } // Set the type of this endpoint in the control register. @@ -827,7 +827,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to ep_xfer[ep_number].total_size = total_bytes; ep_xfer[ep_number].remain_size = total_bytes; ep_xfer[ep_number].buff_ptr = buffer; - + if (ep_number == USBD_EP_0) { ep_xfer[USBD_EP_0].dir = ep_dir; @@ -876,7 +876,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to // then report the transfer complete with dcd_event_xfer_complete. ep_xfer[ep_number].valid = 1; } - } + } status = true; } else @@ -922,7 +922,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) CRITICAL_SECTION_END } -// Clear stall (non-control endpoint), data toggle is also reset to DATA0 +// Clear stall (non-control endpoint), data toggle is also reset to DATA0 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { uint8_t ep_number = tu_edpt_number(ep_addr); @@ -1025,7 +1025,7 @@ void dcd_int_handler(uint8_t rhport) // Host has sent a SETUP packet. Receive this into the SETUP packet store. _ft9xx_dusb_out(USBD_EP_0, (uint8_t *)_ft9xx_setup_packet, sizeof(USB_device_request)); - + // Send the packet to tinyusb. dcd_event_setup_received(BOARD_TUD_RHPORT, _ft9xx_setup_packet, true); @@ -1046,13 +1046,13 @@ void dcd_int_handler(uint8_t rhport) { xfer_bytes = (uint16_t)ep_xfer[USBD_EP_0].total_size; - // Transfer incoming data from an OUT packet to the buffer supplied. + // Transfer incoming data from an OUT packet to the buffer supplied. if (ep_xfer[USBD_EP_0].dir == TUSB_DIR_OUT) { xfer_bytes = _ft9xx_edpt_xfer_out(USBD_EP_0, ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes); } // Now signal completion of data packet. - dcd_event_xfer_complete(BOARD_TUD_RHPORT, USBD_EP_0 | (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0), + dcd_event_xfer_complete(BOARD_TUD_RHPORT, USBD_EP_0 | (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0), xfer_bytes, XFER_RESULT_SUCCESS, true); // Incoming FIFO has been cleared. @@ -1097,13 +1097,13 @@ void dcd_int_handler(uint8_t rhport) // Start or continue an OUT transfer. if (ep_xfer[ep_number].dir == TUSB_DIR_OUT) { - xfer_bytes = _ft9xx_edpt_xfer_out(ep_number, - ep_xfer[ep_number].buff_ptr, + xfer_bytes = _ft9xx_edpt_xfer_out(ep_number, + ep_xfer[ep_number].buff_ptr, (uint16_t)ep_xfer[ep_number].remain_size); // Report each OUT packet received to the stack. - dcd_event_xfer_complete(BOARD_TUD_RHPORT, - ep_number /* | TUSB_DIR_OUT_MASK */, + dcd_event_xfer_complete(BOARD_TUD_RHPORT, + ep_number /* | TUSB_DIR_OUT_MASK */, xfer_bytes, XFER_RESULT_SUCCESS, true); ep_xfer[ep_number].buff_ptr += xfer_bytes; @@ -1114,8 +1114,8 @@ void dcd_int_handler(uint8_t rhport) { if (ep_xfer[ep_number].remain_size > 0) { - xfer_bytes = _ft9xx_edpt_xfer_in(ep_number, - ep_xfer[ep_number].buff_ptr, + xfer_bytes = _ft9xx_edpt_xfer_in(ep_number, + ep_xfer[ep_number].buff_ptr, (uint16_t)ep_xfer[ep_number].remain_size); ep_xfer[ep_number].buff_ptr += xfer_bytes; @@ -1124,8 +1124,8 @@ void dcd_int_handler(uint8_t rhport) if (ep_xfer[ep_number].remain_size == 0) { - dcd_event_xfer_complete(BOARD_TUD_RHPORT, - ep_number | TUSB_DIR_IN_MASK, + dcd_event_xfer_complete(BOARD_TUD_RHPORT, + ep_number | TUSB_DIR_IN_MASK, ep_xfer[ep_number].total_size, XFER_RESULT_SUCCESS, true); } } @@ -1151,7 +1151,7 @@ void dcd_int_handler(uint8_t rhport) // once the transfer is initiated. // Strictly this should not happen for a non-control endpoint. Interrupts // are disabled when there are no transfers setup for an endpoint. - ep_xfer[ep_number].ready = 1; + ep_xfer[ep_number].ready = 1; } } } @@ -1159,13 +1159,13 @@ void dcd_int_handler(uint8_t rhport) } } -// Power management interrupt handler. +// Power management interrupt handler. // This handles USB device related power management interrupts only. void ft9xx_usbd_pm_ISR(void) { uint16_t pmcfg = SYS->PMCFG_H; - // Main interrupt handler is responible for + // Main interrupt handler is responible for if (pmcfg & MASK_SYS_PMCFG_DEV_CONN_DEV) { // Signal connection interrupt diff --git a/src/portable/chipidea/ci_hs/ci_hs_type.h b/src/portable/chipidea/ci_hs/ci_hs_type.h index 728a86b86..31b5a012d 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_type.h +++ b/src/portable/chipidea/ci_hs/ci_hs_type.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021, Ha Thach (tinyusb.org) diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 5bccf81a7..bc6736cf2 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -545,7 +545,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes); } } - + // only number of bytes in the IOC qtd dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true); } diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index d0396daea..d607627b4 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 7140897a1..ee9dfb11f 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -566,7 +566,7 @@ static void period_list_xfer_complete_isr(uint8_t hostid, uint32_t interval_ms) case EHCI_QTYPE_ITD: // TODO support hs/fs ISO case EHCI_QTYPE_SITD: case EHCI_QTYPE_FSTN: - + default: break; } @@ -683,7 +683,7 @@ void hcd_int_handler(uint8_t rhport) uint32_t int_status = regs->status; int_status &= regs->inten; - + regs->status = int_status; // Acknowledge handled interrupt if (int_status == 0) return; diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c index 41240f737..1fcfb6241 100644 --- a/src/portable/espressif/esp32sx/dcd_esp32sx.c +++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c @@ -874,4 +874,3 @@ void dcd_int_disable (uint8_t rhport) } #endif // #if OPT_MCU_ESP32S2 || OPT_MCU_ESP32S3 - diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 0ba53d4d0..487761847 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021 Koji KITAYAMA @@ -572,7 +572,7 @@ static void process_bus_reset(uint8_t rhport) _dcd.pipe0.buf = NULL; USB0->TXIE = 1; /* Enable only EP0 */ - USB0->RXIE = 0; + USB0->RXIE = 0; /* Clear FIFO settings */ for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { @@ -722,7 +722,7 @@ void dcd_edpt_close_all(uint8_t rhport) unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); NVIC_DisableIRQ(USB0_IRQn); USB0->TXIE = 1; /* Enable only EP0 */ - USB0->RXIE = 0; + USB0->RXIE = 0; for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { regs->TXMAXP = 0; regs->TXCSRH = 0; @@ -854,7 +854,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) if (tu_edpt_dir(ep_addr)) { /* IN */ regs->TXCSRL = USB_TXCSRL1_CLRDT; } else { /* OUT */ - regs->RXCSRL = USB_RXCSRL1_CLRDT; + regs->RXCSRL = USB_RXCSRL1_CLRDT; } if (ie) NVIC_EnableIRQ(USB0_IRQn); } diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c index 85e18e3aa..9eb2e005e 100644 --- a/src/portable/mentor/musb/hcd_musb.c +++ b/src/portable/mentor/musb/hcd_musb.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021 Koji KITAYAMA @@ -588,7 +588,7 @@ void hcd_int_disable(uint8_t rhport) uint32_t hcd_frame_number(uint8_t rhport) { (void)rhport; - /* The device must be reset at least once after connection + /* The device must be reset at least once after connection * in order to start the frame counter. */ if (_hcd.need_reset) hcd_port_reset(rhport); return USB0->FRAME; diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c index 6cf0e6285..6986c8317 100644 --- a/src/portable/microchip/pic/dcd_pic.c +++ b/src/portable/microchip/pic/dcd_pic.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Koji Kitayama @@ -486,7 +486,7 @@ void dcd_init(uint8_t rhport) #else U1PWRCbits.USBPWR = 1; #endif - + #if TU_PIC_INT_SIZE == 4 uint32_t bdt_phys = KVA_TO_PA((uintptr_t)_dcd.bdt); diff --git a/src/portable/microchip/pic32mz/usbhs_registers.h b/src/portable/microchip/pic32mz/usbhs_registers.h index 93b552322..03fe78bbd 100644 --- a/src/portable/microchip/pic32mz/usbhs_registers.h +++ b/src/portable/microchip/pic32mz/usbhs_registers.h @@ -21,7 +21,7 @@ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. *******************************************************************************/ /******************************************************************************* - USBHS Peripheral Library Register Definitions + USBHS Peripheral Library Register Definitions File Name: usbhs_registers.h @@ -50,16 +50,16 @@ #define USBHS_REG_INTRRX 0x004 #define USBHS_REG_INTRTXE 0x006 #define USBHS_REG_INTRRXE 0x008 -#define USBHS_REG_INTRUSB 0x00A -#define USBHS_REG_INTRUSBE 0x00B +#define USBHS_REG_INTRUSB 0x00A +#define USBHS_REG_INTRUSBE 0x00B #define USBHS_REG_FRAME 0x00C #define USBHS_REG_INDEX 0x00E #define USBHS_REG_TESTMODE 0x00F /******************************************************* - * Endpoint Control Status Registers (CSR). These values + * Endpoint Control Status Registers (CSR). These values * should be added to either the 0x10 to access the - * register through Indexed CSR. To access the actual + * register through Indexed CSR. To access the actual * CSR, see ahead in this header file. ******************************************************/ @@ -99,20 +99,20 @@ #define USBHS_EP_DEVICE_RX_SEND_STALL 0x20 /* FADDR - Device Function Address */ -typedef union +typedef union { - struct __attribute__((packed)) + struct __attribute__((packed)) { unsigned FUNC:7; unsigned :1; }; - uint8_t w; + uint8_t w; } __USBHS_FADDR_t; /* POWER - Control Resume and Suspend signalling */ -typedef union +typedef union { struct __attribute__((packed)) { @@ -126,14 +126,14 @@ typedef union unsigned ISOUPD:1; }; struct - { + { uint8_t w; }; } __USBHS_POWER_t; /* INTRTXE - Transmit endpoint interrupt enable */ -typedef union +typedef union { struct __attribute__((packed)) { @@ -155,7 +155,7 @@ typedef union } __USBHS_INTRTXE_t; /* INTRRXE - Receive endpoint interrupt enable */ -typedef union +typedef union { struct __attribute__((packed)) { @@ -198,7 +198,7 @@ typedef union } __USBHS_INTRUSBE_t; /* FRAME - Frame number */ -typedef union +typedef union { struct __attribute__((packed)) { @@ -213,7 +213,7 @@ typedef union } __USBHS_FRAME_t; /* INDEX - Endpoint index */ -typedef union +typedef union { struct __attribute__((packed)) { @@ -228,7 +228,7 @@ typedef union } __USBHS_INDEX_t; /* TESTMODE - Test mode register */ -typedef union +typedef union { struct __attribute__((packed)) { @@ -248,7 +248,7 @@ typedef union } __USBHS_TESTMODE_t; -/* COUNT0 - Indicates the amount of data received in endpoint 0 */ +/* COUNT0 - Indicates the amount of data received in endpoint 0 */ typedef union { struct __attribute__((packed)) @@ -627,7 +627,7 @@ typedef union }; uint16_t w; -} __USBHS_TXMAXP_t; +} __USBHS_TXMAXP_t; /* TXFIFOSZ - Size of the transmit endpoint FIFO */ typedef struct __attribute__((packed)) @@ -781,7 +781,7 @@ typedef union } __USBHS_DMACNTL_t; -/* Endpoint Control and Status Register Set */ +/* Endpoint Control and Status Register Set */ typedef struct __attribute__((packed)) { volatile __USBHS_TXMAXP_t TXMAXPbits; @@ -906,7 +906,7 @@ typedef struct __attribute__((aligned(4),packed)) volatile __USBHS_TXFIFOADD_t TXFIFOADDbits; volatile __USBHS_RXFIFOADD_t RXFIFOADDbits; - + volatile uint32_t VCONTROL; volatile uint16_t HWVERS; volatile uint8_t padding1[10]; @@ -923,7 +923,7 @@ typedef struct __attribute__((aligned(4),packed)) volatile __USBHS_TARGET_ADDR_t TADDR[16]; volatile __USBHS_EPCSR_t EPCSR[16]; volatile uint32_t DMA_INTR; - volatile __USBHS_DMA_CHANNEL_t DMA_CHANNEL[8]; + volatile __USBHS_DMA_CHANNEL_t DMA_CHANNEL[8]; volatile uint32_t RQPKTXOUNT[16]; } usbhs_registers_t; diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c index 814e680fb..e3fa51e31 100644 --- a/src/portable/microchip/samg/dcd_samg.c +++ b/src/portable/microchip/samg/dcd_samg.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2018, hathach (tinyusb.org) diff --git a/src/portable/microchip/samx7x/common_usb_regs.h b/src/portable/microchip/samx7x/common_usb_regs.h index d232f0bcb..db4a81e0e 100644 --- a/src/portable/microchip/samx7x/common_usb_regs.h +++ b/src/portable/microchip/samx7x/common_usb_regs.h @@ -2007,7 +2007,7 @@ /** \brief DEVDMA hardware registers */ typedef struct -{ +{ __IO uint32_t DEVDMANXTDSC; /**< (DEVDMA Offset: 0x00) Device DMA Channel Next Descriptor Address Register */ __IO uint32_t DEVDMAADDRESS; /**< (DEVDMA Offset: 0x04) Device DMA Channel Address Register */ __IO uint32_t DEVDMACONTROL; /**< (DEVDMA Offset: 0x08) Device DMA Channel Control Register */ @@ -2016,7 +2016,7 @@ typedef struct /** \brief HSTDMA hardware registers */ typedef struct -{ +{ __IO uint32_t HSTDMANXTDSC; /**< (HSTDMA Offset: 0x00) Host DMA Channel Next Descriptor Address Register */ __IO uint32_t HSTDMAADDRESS; /**< (HSTDMA Offset: 0x04) Host DMA Channel Address Register */ __IO uint32_t HSTDMACONTROL; /**< (HSTDMA Offset: 0x08) Host DMA Channel Control Register */ @@ -2025,7 +2025,7 @@ typedef struct /** \brief USBHS hardware registers */ typedef struct -{ +{ __IO uint32_t DEVCTRL; /**< (USBHS Offset: 0x00) Device General Control Register */ __I uint32_t DEVISR; /**< (USBHS Offset: 0x04) Device Global Interrupt Status Register */ __O uint32_t DEVICR; /**< (USBHS Offset: 0x08) Device Global Interrupt Clear Register */ diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c index 24657872b..2bbb345d6 100644 --- a/src/portable/microchip/samx7x/dcd_samx7x.c +++ b/src/portable/microchip/samx7x/dcd_samx7x.c @@ -241,7 +241,7 @@ static void dcd_ep_handler(uint8_t ep_ix) if (int_status & DEVEPTISR_RXOUTI) { uint8_t *ptr = EP_GET_FIFO_PTR(0,8); - + if (count && xfer->total_len) { uint16_t remain = xfer->total_len - xfer->queued_len; @@ -252,7 +252,7 @@ static void dcd_ep_handler(uint8_t ep_ix) if (xfer->buffer) { memcpy(xfer->buffer + xfer->queued_len, ptr, count); - } else + } else { tu_fifo_write_n(xfer->fifo, ptr, count); } @@ -281,7 +281,7 @@ static void dcd_ep_handler(uint8_t ep_ix) { // TX not complete dcd_transmit_packet(xfer, 0); - } else + } else { // TX complete dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true); @@ -292,7 +292,7 @@ static void dcd_ep_handler(uint8_t ep_ix) } } } - } else + } else { if (int_status & DEVEPTISR_RXOUTI) { @@ -333,7 +333,7 @@ static void dcd_ep_handler(uint8_t ep_ix) { // TX not complete dcd_transmit_packet(xfer, ep_ix); - } else + } else { // TX complete dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true); @@ -359,7 +359,7 @@ static void dcd_dma_handler(uint8_t ep_ix) if(USB_REG->DEVEPTCFG[ep_ix] & DEVEPTCFG_EPDIR) { dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true); - } else + } else { dcd_event_xfer_complete(0, ep_ix, count, XFER_RESULT_SUCCESS, true); } @@ -507,12 +507,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) // Enable Endpoint 0 Interrupts USB_REG->DEVIER = DEVIER_PEP_0; return true; - } else + } else { // Endpoint configuration is not successful return false; } - } else + } else { // Enable the endpoint USB_REG->DEVEPT |= ((0x01 << epnum) << DEVEPT_EPEN0_Pos); @@ -544,7 +544,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { USB_REG->DEVIER = ((0x01 << epnum) << DEVIER_PEP_0_Pos); return true; - } else + } else { // Endpoint configuration is not successful return false; @@ -583,7 +583,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix) { memcpy(ptr, xfer->buffer + xfer->queued_len, len); } - else + else { tu_fifo_read_n(xfer->fifo, ptr, len); } @@ -595,7 +595,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix) { // Control endpoint: clear the interrupt flag to send the data USB_REG->DEVEPTICR[0] = DEVEPTICR_TXINIC; - } else + } else { // Other endpoint types: clear the FIFO control flag to send the data USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC; @@ -616,7 +616,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t xfer->total_len = total_bytes; xfer->queued_len = 0; xfer->fifo = NULL; - + if (EP_DMA_SUPPORT(epnum) && total_bytes != 0) { // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the @@ -648,12 +648,12 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t // and the DMA transfer must be not started. // It is the end of transfer return false; - } else + } else { if (dir == TUSB_DIR_OUT) { USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES; - } else + } else { dcd_transmit_packet(xfer,epnum); } @@ -701,20 +701,20 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 // Clean invalidate cache of linear part CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_lin, 4), info.len_lin + 31); - + USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)info.ptr_lin; if (info.len_wrap) { // Clean invalidate cache of wrapped part CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_wrap, 4), info.len_wrap + 31); - + dma_desc[epnum - 1].next_desc = 0; dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap; dma_desc[epnum - 1].chnl_ctrl = udd_dma_ctrl_wrap | (info.len_wrap << DEVDMACONTROL_BUFF_LENGTH_Pos); // Clean cache of wrapped DMA descriptor CleanInValidateCache((uint32_t*)&dma_desc[epnum - 1], sizeof(dma_desc_t)); - + udd_dma_ctrl_lin |= DEVDMASTATUS_DESC_LDST; USB_REG->DEVDMA[epnum - 1].DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1]; } else { @@ -743,7 +743,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 if (dir == TUSB_DIR_OUT) { USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES; - } else + } else { dcd_transmit_packet(xfer,epnum); } diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index 4aeb85fc0..eee5686f4 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/portable/nuvoton/nuc120/dcd_nuc120.c b/src/portable/nuvoton/nuc120/dcd_nuc120.c index 2fdc05f36..fb12122e0 100644 --- a/src/portable/nuvoton/nuc120/dcd_nuc120.c +++ b/src/portable/nuvoton/nuc120/dcd_nuc120.c @@ -27,9 +27,9 @@ /* Theory of operation: - The NUC100/NUC120 USBD peripheral has six "EP"s, but each is simplex, - so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to - implement USB EP0. PERIPH_EP0 and PERIPH_EP1 are used by this driver for + The NUC100/NUC120 USBD peripheral has six "EP"s, but each is simplex, + so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to + implement USB EP0. PERIPH_EP0 and PERIPH_EP1 are used by this driver for EP0_IN and EP0_OUT respectively. This leaves up to four for user usage. */ diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c index a56b5f8e8..873b1b7ef 100644 --- a/src/portable/nuvoton/nuc121/dcd_nuc121.c +++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c @@ -27,9 +27,9 @@ /* Theory of operation: - The NUC121/NUC125/NUC126 USBD peripheral has eight "EP"s, but each is simplex, - so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to - implement USB EP0. PERIPH_EP0 and PERIPH_EP1 are used by this driver for + The NUC121/NUC125/NUC126 USBD peripheral has eight "EP"s, but each is simplex, + so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to + implement USB EP0. PERIPH_EP0 and PERIPH_EP1 are used by this driver for EP0_IN and EP0_OUT respectively. This leaves up to six for user usage. */ diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c index 3fa7c1ec1..3a92c9794 100644 --- a/src/portable/nuvoton/nuc505/dcd_nuc505.c +++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c @@ -27,9 +27,9 @@ /* Theory of operation: - The NUC505 USBD peripheral has twelve "EP"s, where each is simplex, in addition + The NUC505 USBD peripheral has twelve "EP"s, where each is simplex, in addition to dedicated support for the control endpoint (EP0). The non-user endpoints - are referred to as "user" EPs in this code, and follow the datasheet + are referred to as "user" EPs in this code, and follow the datasheet nomenclature of EPA through EPL. */ @@ -389,7 +389,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to while (total_bytes < USBD->CEPRXCNT); for (int count = 0; count < total_bytes; count++) *buffer++ = USBD->CEPDAT_BYTE; - + dcd_event_xfer_complete(0, ep_addr, total_bytes, XFER_RESULT_SUCCESS, true); } } diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 13eb105cd..b6daec3de 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Koji Kitayama @@ -296,7 +296,7 @@ void dcd_int_disable(uint8_t rhport) void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { - _dcd.addr = dev_addr & 0x7F; + _dcd.addr = dev_addr & 0x7F; /* Response with status first before changing device address */ dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); } @@ -528,7 +528,7 @@ void dcd_int_handler(uint8_t rhport) if (is & USB_ISTAT_SLEEP_MASK) { // TU_LOG2("Suspend: "); TU_LOG2_HEX(is); - // Note Host usually has extra delay after bus reset (without SOF), which could falsely + // Note Host usually has extra delay after bus reset (without SOF), which could falsely // detected as Sleep event. Though usbd has debouncing logic so we are good KHCI->ISTAT = USB_ISTAT_SLEEP_MASK; process_bus_sleep(rhport); diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index 0f5fa6275..35763f121 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021 Koji Kitayama @@ -414,7 +414,7 @@ void hcd_int_disable(uint8_t rhport) uint32_t hcd_frame_number(uint8_t rhport) { (void)rhport; - /* The device must be reset at least once after connection + /* The device must be reset at least once after connection * in order to start the frame counter. */ if (_hcd.need_reset) hcd_port_reset(rhport); uint32_t frmnum = KHCI->FRMNUML; diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c index 0894a5eeb..86149afd8 100644 --- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c +++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.h b/src/portable/nxp/lpc17_40/dcd_lpc17_40.h index 07daa32e4..654b80866 100644 --- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.h +++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c index ad9ed59b4..372dcf51f 100644 --- a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c +++ b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, Ha Thach (tinyusb.org) @@ -44,4 +44,3 @@ void hcd_int_disable(uint8_t rhport) } #endif - diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c index 124656307..5368ef868 100644 --- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c +++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -373,7 +373,7 @@ void dcd_edpt_close_all (uint8_t rhport) void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { (void) rhport; - + uint8_t ep_id = ep_addr2id(ep_addr); _dcd.ep[ep_id][0].cmd_sts.active = _dcd.ep[ep_id][0].cmd_sts.active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual) _dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1; @@ -426,7 +426,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to static void bus_reset(uint8_t rhport) { tu_memclr(&_dcd, sizeof(dcd_data_t)); - edpt_reset_all(rhport); + edpt_reset_all(rhport); // disable all endpoints as specified by LPC55S69 UM Table 778 for(uint8_t ep_id = 0; ep_id < 2*MAX_EP_PAIRS; ep_id++) @@ -575,4 +575,3 @@ void dcd_int_handler(uint8_t rhport) } #endif - diff --git a/src/portable/nxp/transdimension/common_transdimension.h b/src/portable/nxp/transdimension/common_transdimension.h index 69074de41..95ae1903e 100644 --- a/src/portable/nxp/transdimension/common_transdimension.h +++ b/src/portable/nxp/transdimension/common_transdimension.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2021, Ha Thach (tinyusb.org) diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index 1f27a6872..983d7cfcf 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -569,7 +569,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes); } } - + // only number of bytes in the IOC qtd dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true); } diff --git a/src/portable/nxp/transdimension/hcd_transdimension.c b/src/portable/nxp/transdimension/hcd_transdimension.c index 392764ff6..0b3e9e4ef 100644 --- a/src/portable/nxp/transdimension/hcd_transdimension.c +++ b/src/portable/nxp/transdimension/hcd_transdimension.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index b615743b8..260804d3d 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -715,4 +715,3 @@ void hcd_int_handler(uint8_t hostid) #endif - diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c index 1bc5594d8..e6daf6827 100644 --- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2018, hathach (tinyusb.org) diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h index a06407f23..9f8e58d42 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.h +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h @@ -47,7 +47,7 @@ typedef struct hw_endpoint { // Is this a valid struct bool configured; - + // Transfer direction (i.e. IN is rx for host but tx for device) // allows us to common up transfer functions bool rx; diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index e49c0b52e..1677cfa12 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Nathan Conrad @@ -181,7 +181,7 @@ static void dcd_handle_bus_reset(void); static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix); static void dcd_ep_ctr_handler(void); -// PMA allocation/access +// PMA allocation/access static uint8_t open_ep_count; static uint16_t ep_buf_ptr; ///< Points to first free memory location static void dcd_pma_alloc_reset(void); @@ -249,7 +249,7 @@ void dcd_init (uint8_t rhport) asm("NOP"); } USB->CNTR = 0; // Enable USB - + USB->BTABLE = DCD_STM32_BTABLE_BASE; USB->ISTR = 0; // Clear pending interrupts @@ -263,7 +263,7 @@ void dcd_init (uint8_t rhport) USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM; dcd_handle_bus_reset(); - + // Enable pull-up if supported if ( dcd_connect ) dcd_connect(rhport); } @@ -464,12 +464,12 @@ static void dcd_handle_bus_reset(void) //__IO uint16_t * const epreg = &(EPREG(0)); USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag - + for(uint32_t i=0; iep_idx = ep_idx; pcd_set_eptype(USB, ep_idx, USB_EP_ISOCHRONOUS); - + *pcd_ep_tx_address_ptr(USB, ep_idx) = pma_addr; *pcd_ep_rx_address_ptr(USB, ep_idx) = pma_addr; - + return true; } @@ -1035,7 +1035,7 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpo { pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS); } - + pcd_set_ep_address(USB, ep_idx, tu_edpt_number(p_endpoint_desc->bEndpointAddress)); // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint) // or being double-buffered (bulk endpoints) @@ -1250,11 +1250,11 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN { // Since we copy from a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies tu_fifo_buffer_info_t info; - tu_fifo_get_read_info(ff, &info); - + tu_fifo_get_read_info(ff, &info); + uint16_t cnt_lin = TU_MIN(wNBytes, info.len_lin); uint16_t cnt_wrap = TU_MIN(wNBytes - cnt_lin, info.len_wrap); - + // We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part, // last lin byte will be combined with wrapped part // To ensure PMA is always access 16bit aligned (dst aligned to 16 bit) @@ -1352,7 +1352,7 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB // Copy last linear byte & first wrapped byte uint16_t tmp; dcd_read_packet_memory(&tmp, src, 2); - + ((uint8_t*)info.ptr_lin)[cnt_lin - 1] = (uint8_t)tmp; ((uint8_t*)info.ptr_wrap)[0] = (uint8_t)(tmp >> 8U); src += 2; @@ -1379,4 +1379,3 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB } #endif - diff --git a/src/portable/st/synopsys/synopsys_common.h b/src/portable/st/synopsys/synopsys_common.h index 6f0602fe9..ce3195b23 100644 --- a/src/portable/st/synopsys/synopsys_common.h +++ b/src/portable/st/synopsys/synopsys_common.h @@ -2,15 +2,15 @@ ****************************************************************************** * @file synopsys_common.h * @author MCD Application Team - * @brief CMSIS Cortex-M3 Device USB OTG peripheral Header File. - * This file contains the USB OTG peripheral register's definitions, bits + * @brief CMSIS Cortex-M3 Device USB OTG peripheral Header File. + * This file contains the USB OTG peripheral register's definitions, bits * definitions and memory mapping for STM32F1xx devices. - * + * * This file contains: * - Data structures and the address mapping for the USB OTG peripheral * - The Peripheral's registers declarations and bits definition * - Macros to access the peripheral's registers hardware - * + * ****************************************************************************** * @attention * @@ -40,7 +40,7 @@ #define __OM volatile #define __IOM volatile -/** +/** * @brief __USB_OTG_Core_register */ @@ -66,11 +66,11 @@ typedef struct __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */ } USB_OTG_GlobalTypeDef; -/** +/** * @brief __device_Registers */ -typedef struct +typedef struct { __IO uint32_t DCFG; /*!< dev Configuration Register Address offset: 800h*/ __IO uint32_t DCTL; /*!< dev Control Register Address offset: 804h*/ @@ -87,18 +87,18 @@ typedef struct __IO uint32_t DTHRCTL; /*!< dev thr Address offset: 830h*/ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset: 834h*/ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset: 838h*/ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset: 83Ch*/ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset: 83Ch*/ uint32_t Reserved40; /*!< dedicated EP mask Address offset: 840h*/ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset: 844h*/ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch*/ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset: 884h*/ } USB_OTG_DeviceTypeDef; -/** +/** * @brief __IN_Endpoint-Specific_Register */ -typedef struct +typedef struct { __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h*/ @@ -110,11 +110,11 @@ typedef struct uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ } USB_OTG_INEndpointTypeDef; -/** +/** * @brief __OUT_Endpoint-Specific_Registers */ -typedef struct +typedef struct { __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h*/ @@ -125,11 +125,11 @@ typedef struct uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ } USB_OTG_OUTEndpointTypeDef; -/** +/** * @brief __Host_Mode_Register_Structures */ -typedef struct +typedef struct { __IO uint32_t HCFG; /*!< Host Configuration Register 400h*/ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h*/ @@ -140,7 +140,7 @@ typedef struct __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h*/ } USB_OTG_HostTypeDef; -/** +/** * @brief __Host_Channel_Specific_Registers */ @@ -177,60 +177,60 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for USB_OTG_GOTGCTL register ***********/ -#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) +#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ -#define USB_OTG_GOTGCTL_SRQ_Pos (1U) +#define USB_OTG_GOTGCTL_SRQ_Pos (1U) #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ -#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) +#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ -#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) +#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ -#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) +#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ -#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) +#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ -#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ -#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ -#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ -#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ /******************** Bit definition for USB_OTG_HCFG register ********************/ -#define USB_OTG_HCFG_FSLSPCS_Pos (0U) +#define USB_OTG_HCFG_FSLSPCS_Pos (0U) #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ -#define USB_OTG_HCFG_FSLSS_Pos (2U) +#define USB_OTG_HCFG_FSLSS_Pos (2U) #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ /******************** Bit definition for USB_OTG_DCFG register ********************/ -#define USB_OTG_DCFG_DSPD_Pos (0U) +#define USB_OTG_DCFG_DSPD_Pos (0U) #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ -#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) +#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ -#define USB_OTG_DCFG_DAD_Pos (4U) +#define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ @@ -241,120 +241,120 @@ typedef struct #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ -#define USB_OTG_DCFG_PFIVL_Pos (11U) +#define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ -#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) +#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ /******************** Bit definition for USB_OTG_PCGCR register ********************/ -#define USB_OTG_PCGCR_STPPCLK_Pos (0U) +#define USB_OTG_PCGCR_STPPCLK_Pos (0U) #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ -#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) +#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ -#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) +#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ /******************** Bit definition for USB_OTG_GOTGINT register ********************/ -#define USB_OTG_GOTGINT_SEDET_Pos (2U) +#define USB_OTG_GOTGINT_SEDET_Pos (2U) #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ -#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) +#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ -#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) +#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ -#define USB_OTG_GOTGINT_HNGDET_Pos (17U) +#define USB_OTG_GOTGINT_HNGDET_Pos (17U) #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ -#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) +#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ -#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) +#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ /******************** Bit definition for USB_OTG_DCTL register ********************/ -#define USB_OTG_DCTL_RWUSIG_Pos (0U) +#define USB_OTG_DCTL_RWUSIG_Pos (0U) #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ -#define USB_OTG_DCTL_SDIS_Pos (1U) +#define USB_OTG_DCTL_SDIS_Pos (1U) #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ -#define USB_OTG_DCTL_GINSTS_Pos (2U) +#define USB_OTG_DCTL_GINSTS_Pos (2U) #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ -#define USB_OTG_DCTL_GONSTS_Pos (3U) +#define USB_OTG_DCTL_GONSTS_Pos (3U) #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ -#define USB_OTG_DCTL_TCTL_Pos (4U) +#define USB_OTG_DCTL_TCTL_Pos (4U) #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ -#define USB_OTG_DCTL_SGINAK_Pos (7U) +#define USB_OTG_DCTL_SGINAK_Pos (7U) #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ -#define USB_OTG_DCTL_CGINAK_Pos (8U) +#define USB_OTG_DCTL_CGINAK_Pos (8U) #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ -#define USB_OTG_DCTL_SGONAK_Pos (9U) +#define USB_OTG_DCTL_SGONAK_Pos (9U) #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ -#define USB_OTG_DCTL_CGONAK_Pos (10U) +#define USB_OTG_DCTL_CGONAK_Pos (10U) #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ -#define USB_OTG_DCTL_POPRGDNE_Pos (11U) +#define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ /******************** Bit definition for USB_OTG_HFIR register ********************/ -#define USB_OTG_HFIR_FRIVL_Pos (0U) +#define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ -#define USB_OTG_HFNUM_FRNUM_Pos (0U) +#define USB_OTG_HFNUM_FRNUM_Pos (0U) #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ -#define USB_OTG_HFNUM_FTREM_Pos (16U) +#define USB_OTG_HFNUM_FTREM_Pos (16U) #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ /******************** Bit definition for USB_OTG_DSTS register ********************/ -#define USB_OTG_DSTS_SUSPSTS_Pos (0U) +#define USB_OTG_DSTS_SUSPSTS_Pos (0U) #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ -#define USB_OTG_DSTS_ENUMSPD_Pos (1U) +#define USB_OTG_DSTS_ENUMSPD_Pos (1U) #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ -#define USB_OTG_DSTS_EERR_Pos (3U) +#define USB_OTG_DSTS_EERR_Pos (3U) #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ -#define USB_OTG_DSTS_FNSOF_Pos (8U) +#define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) +#define USB_OTG_GAHBCFG_GINT_Pos (0U) #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ -#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) +#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ @@ -362,99 +362,99 @@ typedef struct #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ -#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) +#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ -#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) +#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ -#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) +#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ /******************** Bit definition for USB_OTG_GUSBCFG register ********************/ -#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) +#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ -#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) +#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ -#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) +#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ -#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) +#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ -#define USB_OTG_GUSBCFG_TRDT_Pos (10U) +#define USB_OTG_GUSBCFG_TRDT_Pos (10U) #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ -#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) +#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ -#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) +#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ -#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) +#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ -#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ -#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ -#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) +#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ -#define USB_OTG_GUSBCFG_PCCI_Pos (23U) +#define USB_OTG_GUSBCFG_PCCI_Pos (23U) #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ -#define USB_OTG_GUSBCFG_PTCI_Pos (24U) +#define USB_OTG_GUSBCFG_PTCI_Pos (24U) #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ -#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) +#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ -#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) +#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ -#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) +#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ -#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) +#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ /******************** Bit definition for USB_OTG_GRSTCTL register ********************/ -#define USB_OTG_GRSTCTL_CSRST_Pos (0U) +#define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) +#define USB_OTG_GRSTCTL_HSRST_Pos (1U) #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ -#define USB_OTG_GRSTCTL_FCRST_Pos (2U) +#define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ -#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) +#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ -#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) +#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ -#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) +#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ @@ -462,44 +462,44 @@ typedef struct #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ -#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) +#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ -#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) +#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ /******************** Bit definition for USB_OTG_DIEPMSK register ********************/ -#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DIEPMSK_EPDM_Pos (1U) +#define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DIEPMSK_TOM_Pos (3U) +#define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ -#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ -#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) +#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ -#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) +#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ -#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) +#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ -#define USB_OTG_DIEPMSK_BIM_Pos (9U) +#define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ -#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) +#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ -#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) +#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ @@ -511,7 +511,7 @@ typedef struct #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) +#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ @@ -524,36 +524,36 @@ typedef struct #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ /******************** Bit definition for USB_OTG_HAINT register ********************/ -#define USB_OTG_HAINT_HAINT_Pos (0U) +#define USB_OTG_HAINT_HAINT_Pos (0U) #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ /******************** Bit definition for USB_OTG_DOEPMSK register ********************/ -#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DOEPMSK_EPDM_Pos (1U) +#define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ -#define USB_OTG_DOEPMSK_STUPM_Pos (3U) +#define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ -#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) +#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ -#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) +#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ -#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) +#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) +#define USB_OTG_DOEPMSK_OPEM_Pos (8U) #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ -#define USB_OTG_DOEPMSK_BOIM_Pos (9U) +#define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ #define USB_OTG_DOEPMSK_BERRM_Pos (12U) @@ -566,235 +566,235 @@ typedef struct #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ -#define USB_OTG_GINTSTS_CMOD_Pos (0U) +#define USB_OTG_GINTSTS_CMOD_Pos (0U) #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ -#define USB_OTG_GINTSTS_MMIS_Pos (1U) +#define USB_OTG_GINTSTS_MMIS_Pos (1U) #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ -#define USB_OTG_GINTSTS_OTGINT_Pos (2U) +#define USB_OTG_GINTSTS_OTGINT_Pos (2U) #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ -#define USB_OTG_GINTSTS_SOF_Pos (3U) +#define USB_OTG_GINTSTS_SOF_Pos (3U) #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ -#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) +#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ -#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) +#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ -#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) +#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ -#define USB_OTG_GINTSTS_ESUSP_Pos (10U) +#define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ -#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) +#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ -#define USB_OTG_GINTSTS_USBRST_Pos (12U) +#define USB_OTG_GINTSTS_USBRST_Pos (12U) #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ -#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) +#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ -#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) +#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ -#define USB_OTG_GINTSTS_EOPF_Pos (15U) +#define USB_OTG_GINTSTS_EOPF_Pos (15U) #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ -#define USB_OTG_GINTSTS_IEPINT_Pos (18U) +#define USB_OTG_GINTSTS_IEPINT_Pos (18U) #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ -#define USB_OTG_GINTSTS_OEPINT_Pos (19U) +#define USB_OTG_GINTSTS_OEPINT_Pos (19U) #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ -#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) +#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ -#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ -#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) +#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ -#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) +#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ -#define USB_OTG_GINTSTS_HCINT_Pos (25U) +#define USB_OTG_GINTSTS_HCINT_Pos (25U) #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ -#define USB_OTG_GINTSTS_PTXFE_Pos (26U) +#define USB_OTG_GINTSTS_PTXFE_Pos (26U) #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ -#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) +#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ -#define USB_OTG_GINTSTS_DISCINT_Pos (29U) +#define USB_OTG_GINTSTS_DISCINT_Pos (29U) #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ -#define USB_OTG_GINTSTS_SRQINT_Pos (30U) +#define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUINT_Pos (31U) #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ -#define USB_OTG_GINTMSK_MMISM_Pos (1U) +#define USB_OTG_GINTMSK_MMISM_Pos (1U) #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ -#define USB_OTG_GINTMSK_OTGINT_Pos (2U) +#define USB_OTG_GINTMSK_OTGINT_Pos (2U) #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ -#define USB_OTG_GINTMSK_SOFM_Pos (3U) +#define USB_OTG_GINTMSK_SOFM_Pos (3U) #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ -#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) +#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ -#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) +#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ -#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) +#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ -#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) +#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ -#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) +#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ -#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) +#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ -#define USB_OTG_GINTMSK_USBRST_Pos (12U) +#define USB_OTG_GINTMSK_USBRST_Pos (12U) #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ -#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) +#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ -#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) +#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ -#define USB_OTG_GINTMSK_EOPFM_Pos (15U) +#define USB_OTG_GINTMSK_EOPFM_Pos (15U) #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ -#define USB_OTG_GINTMSK_EPMISM_Pos (17U) +#define USB_OTG_GINTMSK_EPMISM_Pos (17U) #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ -#define USB_OTG_GINTMSK_IEPINT_Pos (18U) +#define USB_OTG_GINTMSK_IEPINT_Pos (18U) #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ -#define USB_OTG_GINTMSK_OEPINT_Pos (19U) +#define USB_OTG_GINTMSK_OEPINT_Pos (19U) #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ -#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) +#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ -#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) +#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ -#define USB_OTG_GINTMSK_PRTIM_Pos (24U) +#define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ -#define USB_OTG_GINTMSK_HCIM_Pos (25U) +#define USB_OTG_GINTMSK_HCIM_Pos (25U) #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ -#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) +#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ -#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) +#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ -#define USB_OTG_GINTMSK_DISCINT_Pos (29U) +#define USB_OTG_GINTMSK_DISCINT_Pos (29U) #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ -#define USB_OTG_GINTMSK_SRQIM_Pos (30U) +#define USB_OTG_GINTMSK_SRQIM_Pos (30U) #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ -#define USB_OTG_GINTMSK_WUIM_Pos (31U) +#define USB_OTG_GINTMSK_WUIM_Pos (31U) #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ /******************** Bit definition for USB_OTG_DAINT register ********************/ -#define USB_OTG_DAINT_IEPINT_Pos (0U) +#define USB_OTG_DAINT_IEPINT_Pos (0U) #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ -#define USB_OTG_DAINT_OEPINT_Pos (16U) +#define USB_OTG_DAINT_OEPINT_Pos (16U) #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ /******************** Bit definition for USB_OTG_HAINTMSK register ********************/ -#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) +#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_BCNT_Pos (4U) +#define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_DPID_Pos (15U) +#define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ -#define USB_OTG_DAINTMSK_IEPM_Pos (0U) +#define USB_OTG_DAINTMSK_IEPM_Pos (0U) #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ -#define USB_OTG_DAINTMSK_OEPM_Pos (16U) +#define USB_OTG_DAINTMSK_OEPM_Pos (16U) #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ -#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) +#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ -#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) +#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ /******************** Bit definition for OTG register ********************/ -#define USB_OTG_NPTXFSA_Pos (0U) +#define USB_OTG_NPTXFSA_Pos (0U) #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ -#define USB_OTG_NPTXFD_Pos (16U) +#define USB_OTG_NPTXFD_Pos (16U) #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ -#define USB_OTG_TX0FSA_Pos (0U) +#define USB_OTG_TX0FSA_Pos (0U) #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ -#define USB_OTG_TX0FD_Pos (16U) +#define USB_OTG_TX0FD_Pos (16U) #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/ -#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) +#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ -#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) +#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) +#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ @@ -806,7 +806,7 @@ typedef struct #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) +#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ @@ -818,14 +818,14 @@ typedef struct #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ /******************** Bit definition for USB_OTG_DTHRCTL register ********************/ -#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) +#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ -#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) +#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ -#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) +#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ @@ -837,11 +837,11 @@ typedef struct #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ -#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) +#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ -#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) +#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ @@ -853,118 +853,118 @@ typedef struct #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) +#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ -#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ /******************** Bit definition for USB_OTG_DEACHINT register ********************/ -#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) +#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ -#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) +#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ /******************** Bit definition for USB_OTG_GCCFG register ********************/ -#define USB_OTG_GCCFG_PWRDWN_Pos (16U) +#define USB_OTG_GCCFG_PWRDWN_Pos (16U) #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ -#define USB_OTG_GCCFG_VBUSASEN_Pos (18U) +#define USB_OTG_GCCFG_VBUSASEN_Pos (18U) #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */ #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */ -#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) +#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */ #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */ -#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) +#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */ #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */ /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/ -#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) +#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ -#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) +#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ /******************** Bit definition for USB_OTG_CID register ********************/ -#define USB_OTG_CID_PRODUCT_ID_Pos (0U) +#define USB_OTG_CID_PRODUCT_ID_Pos (0U) #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ -#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ -#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ -#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ -#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ -#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ -#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ -#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPRT register ********************/ -#define USB_OTG_HPRT_PCSTS_Pos (0U) +#define USB_OTG_HPRT_PCSTS_Pos (0U) #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ -#define USB_OTG_HPRT_PCDET_Pos (1U) +#define USB_OTG_HPRT_PCDET_Pos (1U) #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ -#define USB_OTG_HPRT_PENA_Pos (2U) +#define USB_OTG_HPRT_PENA_Pos (2U) #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ -#define USB_OTG_HPRT_PENCHNG_Pos (3U) +#define USB_OTG_HPRT_PENCHNG_Pos (3U) #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ -#define USB_OTG_HPRT_POCA_Pos (4U) +#define USB_OTG_HPRT_POCA_Pos (4U) #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ -#define USB_OTG_HPRT_POCCHNG_Pos (5U) +#define USB_OTG_HPRT_POCCHNG_Pos (5U) #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ -#define USB_OTG_HPRT_PRES_Pos (6U) +#define USB_OTG_HPRT_PRES_Pos (6U) #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ -#define USB_OTG_HPRT_PSUSP_Pos (7U) +#define USB_OTG_HPRT_PSUSP_Pos (7U) #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ -#define USB_OTG_HPRT_PRST_Pos (8U) +#define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ -#define USB_OTG_HPRT_PLSTS_Pos (10U) +#define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ -#define USB_OTG_HPRT_PPWR_Pos (12U) +#define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ -#define USB_OTG_HPRT_PTCTL_Pos (13U) +#define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ @@ -972,136 +972,136 @@ typedef struct #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ -#define USB_OTG_HPRT_PSPD_Pos (17U) +#define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ -#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ -#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ -#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ -#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ -#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ -#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) +#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) +#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ -#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) +#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ -#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ -#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) +#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ -#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) +#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ -#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) +#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) +#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ -#define USB_OTG_DIEPCTL_STALL_Pos (21U) +#define USB_OTG_DIEPCTL_STALL_Pos (21U) #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ -#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) +#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ -#define USB_OTG_DIEPCTL_CNAK_Pos (26U) +#define USB_OTG_DIEPCTL_CNAK_Pos (26U) #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ -#define USB_OTG_DIEPCTL_SNAK_Pos (27U) +#define USB_OTG_DIEPCTL_SNAK_Pos (27U) #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ -#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) +#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ -#define USB_OTG_DIEPCTL_EPENA_Pos (31U) +#define USB_OTG_DIEPCTL_EPENA_Pos (31U) #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ /******************** Bit definition for USB_OTG_HCCHAR register ********************/ -#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) +#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ -#define USB_OTG_HCCHAR_EPNUM_Pos (11U) +#define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ -#define USB_OTG_HCCHAR_EPDIR_Pos (15U) +#define USB_OTG_HCCHAR_EPDIR_Pos (15U) #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ -#define USB_OTG_HCCHAR_LSDEV_Pos (17U) +#define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ -#define USB_OTG_HCCHAR_EPTYP_Pos (18U) +#define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) + +#define USB_OTG_HCCHAR_MC_Pos (20U) #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ -#define USB_OTG_HCCHAR_DAD_Pos (22U) +#define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ @@ -1111,19 +1111,19 @@ typedef struct #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ -#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) +#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ -#define USB_OTG_HCCHAR_CHDIS_Pos (30U) +#define USB_OTG_HCCHAR_CHDIS_Pos (30U) #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ -#define USB_OTG_HCCHAR_CHENA_Pos (31U) +#define USB_OTG_HCCHAR_CHENA_Pos (31U) #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ /******************** Bit definition for USB_OTG_HCSPLT register ********************/ -#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) +#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ @@ -1134,7 +1134,7 @@ typedef struct #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ -#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) +#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ @@ -1145,240 +1145,240 @@ typedef struct #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ -#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) +#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ -#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) +#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ -#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) +#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ /******************** Bit definition for USB_OTG_HCINT register ********************/ -#define USB_OTG_HCINT_XFRC_Pos (0U) +#define USB_OTG_HCINT_XFRC_Pos (0U) #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ -#define USB_OTG_HCINT_CHH_Pos (1U) +#define USB_OTG_HCINT_CHH_Pos (1U) #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ -#define USB_OTG_HCINT_AHBERR_Pos (2U) +#define USB_OTG_HCINT_AHBERR_Pos (2U) #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ -#define USB_OTG_HCINT_STALL_Pos (3U) +#define USB_OTG_HCINT_STALL_Pos (3U) #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ -#define USB_OTG_HCINT_NAK_Pos (4U) +#define USB_OTG_HCINT_NAK_Pos (4U) #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ -#define USB_OTG_HCINT_ACK_Pos (5U) +#define USB_OTG_HCINT_ACK_Pos (5U) #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ -#define USB_OTG_HCINT_NYET_Pos (6U) +#define USB_OTG_HCINT_NYET_Pos (6U) #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ -#define USB_OTG_HCINT_TXERR_Pos (7U) +#define USB_OTG_HCINT_TXERR_Pos (7U) #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ -#define USB_OTG_HCINT_BBERR_Pos (8U) +#define USB_OTG_HCINT_BBERR_Pos (8U) #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ -#define USB_OTG_HCINT_FRMOR_Pos (9U) +#define USB_OTG_HCINT_FRMOR_Pos (9U) #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ -#define USB_OTG_HCINT_DTERR_Pos (10U) +#define USB_OTG_HCINT_DTERR_Pos (10U) #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ /******************** Bit definition for USB_OTG_DIEPINT register ********************/ -#define USB_OTG_DIEPINT_XFRC_Pos (0U) +#define USB_OTG_DIEPINT_XFRC_Pos (0U) #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ -#define USB_OTG_DIEPINT_EPDISD_Pos (1U) +#define USB_OTG_DIEPINT_EPDISD_Pos (1U) #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ #define USB_OTG_DIEPINT_AHBERR_Pos (2U) #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ -#define USB_OTG_DIEPINT_TOC_Pos (3U) +#define USB_OTG_DIEPINT_TOC_Pos (3U) #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ -#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) +#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ #define USB_OTG_DIEPINT_INEPNM_Pos (5U) #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */ #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ -#define USB_OTG_DIEPINT_INEPNE_Pos (6U) +#define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ -#define USB_OTG_DIEPINT_TXFE_Pos (7U) +#define USB_OTG_DIEPINT_TXFE_Pos (7U) #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ -#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) +#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ -#define USB_OTG_DIEPINT_BNA_Pos (9U) +#define USB_OTG_DIEPINT_BNA_Pos (9U) #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ -#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) +#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ -#define USB_OTG_DIEPINT_BERR_Pos (12U) +#define USB_OTG_DIEPINT_BERR_Pos (12U) #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ -#define USB_OTG_DIEPINT_NAK_Pos (13U) +#define USB_OTG_DIEPINT_NAK_Pos (13U) #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ /******************** Bit definition for USB_OTG_HCINTMSK register ********************/ -#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) +#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ -#define USB_OTG_HCINTMSK_CHHM_Pos (1U) +#define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ -#define USB_OTG_HCINTMSK_STALLM_Pos (3U) +#define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ -#define USB_OTG_HCINTMSK_NAKM_Pos (4U) +#define USB_OTG_HCINTMSK_NAKM_Pos (4U) #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ -#define USB_OTG_HCINTMSK_ACKM_Pos (5U) +#define USB_OTG_HCINTMSK_ACKM_Pos (5U) #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ -#define USB_OTG_HCINTMSK_NYET_Pos (6U) +#define USB_OTG_HCINTMSK_NYET_Pos (6U) #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ -#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) +#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ -#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) +#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ -#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) +#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ -#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) +#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ -#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ -#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ -#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ -#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) +#define USB_OTG_HCTSIZ_DOPING_Pos (31U) #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ -#define USB_OTG_HCTSIZ_DPID_Pos (29U) +#define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ -#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) +#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ /******************** Bit definition for USB_OTG_HCDMA register ********************/ -#define USB_OTG_HCDMA_DMAADDR_Pos (0U) +#define USB_OTG_HCDMA_DMAADDR_Pos (0U) #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ /******************** Bit definition for USB_OTG_DTXFSTS register ********************/ -#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) +#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ /******************** Bit definition for USB_OTG_DIEPTXF register ********************/ -#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) +#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ -#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) +#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ /******************** Bit definition for USB_OTG_DOEPCTL register ********************/ -#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!queued_len += short_packet_size; - + EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer; USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum); EP_TX_LEN(epnum) = short_packet_size; @@ -366,7 +366,7 @@ void dcd_int_handler(uint8_t rhport) { } else if (intflag & USBHS_SETUP_FLAG) { USBHS_Dev_Endp0_Tog = 1; dcd_event_setup_received(0, EP0_DatabufHD, true); - + USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */ } else if (intflag & USBHS_DETECT_FLAG) { USBHS_Dev_Endp0_Tog = 1; diff --git a/test/fuzz/dcd_fuzz.cc b/test/fuzz/dcd_fuzz.cc index 6403015dd..06ddddc4a 100644 --- a/test/fuzz/dcd_fuzz.cc +++ b/test/fuzz/dcd_fuzz.cc @@ -185,7 +185,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, /* TODO: implement a fuzzed version of this. bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, - uint16_t total_bytes) {} + uint16_t total_bytes) {} */ // Stall endpoint, any queuing transfer should be removed from endpoint @@ -205,4 +205,4 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { UNUSED(ep_addr); return; } -} \ No newline at end of file +} diff --git a/test/fuzz/device/cdc/CMakeLists.txt b/test/fuzz/device/cdc/CMakeLists.txt index fa6e83b7e..8e4db9d29 100644 --- a/test/fuzz/device/cdc/CMakeLists.txt +++ b/test/fuzz/device/cdc/CMakeLists.txt @@ -26,4 +26,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/test/fuzz/device/cdc/src/fuzz.cc b/test/fuzz/device/cdc/src/fuzz.cc index d40483ca6..0560e8621 100644 --- a/test/fuzz/device/cdc/src/fuzz.cc +++ b/test/fuzz/device/cdc/src/fuzz.cc @@ -143,7 +143,7 @@ void cdc_task(FuzzedDataProvider *provider) { // TODO: Fuzz interface number (void)tud_cdc_n_write(0, buffer.data(), buffer.size()); } break; - + case kCdcNWriteChar: // TODO: Fuzz interface number (void)tud_cdc_n_write_char(0, provider->ConsumeIntegral()); @@ -171,4 +171,4 @@ case kMaxValue: break; } } -} \ No newline at end of file +} diff --git a/test/fuzz/device/msc/CMakeLists.txt b/test/fuzz/device/msc/CMakeLists.txt index fa6e83b7e..8e4db9d29 100644 --- a/test/fuzz/device/msc/CMakeLists.txt +++ b/test/fuzz/device/msc/CMakeLists.txt @@ -26,4 +26,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/test/fuzz/device/msc/src/fuzz.cc b/test/fuzz/device/msc/src/fuzz.cc index 568900452..371d49882 100644 --- a/test/fuzz/device/msc/src/fuzz.cc +++ b/test/fuzz/device/msc/src/fuzz.cc @@ -59,4 +59,3 @@ extern "C" int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) { return 0; } - diff --git a/test/fuzz/device/net/CMakeLists.txt b/test/fuzz/device/net/CMakeLists.txt index fa6e83b7e..8e4db9d29 100644 --- a/test/fuzz/device/net/CMakeLists.txt +++ b/test/fuzz/device/net/CMakeLists.txt @@ -26,4 +26,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) \ No newline at end of file +family_configure_device_example(${PROJECT}) diff --git a/test/fuzz/device/net/src/arch/cc.h b/test/fuzz/device/net/src/arch/cc.h index 56a0cacf7..9f30b91cb 100644 --- a/test/fuzz/device/net/src/arch/cc.h +++ b/test/fuzz/device/net/src/arch/cc.h @@ -1,8 +1,8 @@ /* * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, @@ -11,21 +11,21 @@ * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. + * derived from this software without specific prior written permission. * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY * OF SUCH DAMAGE. * * This file is part of the lwIP TCP/IP stack. - * + * * Author: Adam Dunkels * */ @@ -42,7 +42,7 @@ typedef int sys_prot_t; #if defined (__ICCARM__) #define PACK_STRUCT_BEGIN -#define PACK_STRUCT_STRUCT +#define PACK_STRUCT_STRUCT #define PACK_STRUCT_END #define PACK_STRUCT_FIELD(x) x #define PACK_STRUCT_USE_INCLUDES @@ -50,7 +50,7 @@ typedef int sys_prot_t; #elif defined (__CC_ARM) #define PACK_STRUCT_BEGIN __packed -#define PACK_STRUCT_STRUCT +#define PACK_STRUCT_STRUCT #define PACK_STRUCT_END #define PACK_STRUCT_FIELD(x) x diff --git a/test/fuzz/device/net/src/fuzz.cc b/test/fuzz/device/net/src/fuzz.cc index ea4943665..a6935928a 100644 --- a/test/fuzz/device/net/src/fuzz.cc +++ b/test/fuzz/device/net/src/fuzz.cc @@ -81,7 +81,7 @@ void net_task(FuzzedDataProvider *provider) { assert(provider != NULL); switch (provider->ConsumeEnum()) { - + case kNetworkRecvRenew: tud_network_recv_renew(); break; diff --git a/test/fuzz/device/net/src/lwipopts.h b/test/fuzz/device/net/src/lwipopts.h index a215017c7..336c9243d 100644 --- a/test/fuzz/device/net/src/lwipopts.h +++ b/test/fuzz/device/net/src/lwipopts.h @@ -1,8 +1,8 @@ /* * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, @@ -11,21 +11,21 @@ * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. + * derived from this software without specific prior written permission. * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY * OF SUCH DAMAGE. * * This file is part of the lwIP TCP/IP stack. - * + * * Author: Simon Goldschmidt * */ diff --git a/test/fuzz/dicts/cdc.dict b/test/fuzz/dicts/cdc.dict index 138775cdc..421eb8ed9 100644 --- a/test/fuzz/dicts/cdc.dict +++ b/test/fuzz/dicts/cdc.dict @@ -71,4 +71,3 @@ RNDIS_PACKET_TYPE_FUNCTIONAL="\x00\x00\x40\x00" # NIC driver frames that a Token Ring NIC receives. RNDIS_PACKET_TYPE_MAC_FRAME="\x00\x00\x80\x00" RNDIS_PACKET_TYPE_NO_LOCAL="\x00\x01\x00\x00" - diff --git a/test/fuzz/make.mk b/test/fuzz/make.mk index 934819665..b7b6d6a75 100644 --- a/test/fuzz/make.mk +++ b/test/fuzz/make.mk @@ -114,7 +114,7 @@ CXXFLAGS += \ # conversion is too strict for most mcu driver, may be disable sign/int/arith-conversion # -Wconversion - + # Debugging/Optimization ifeq ($(DEBUG), 1) CFLAGS += -Og @@ -132,4 +132,3 @@ endif ifneq ($(LOGGER),) CMAKE_DEFSYM += -DLOGGER=$(LOGGER) endif - diff --git a/test/fuzz/msc_fuzz.cc b/test/fuzz/msc_fuzz.cc index e906ca971..6e838a682 100644 --- a/test/fuzz/msc_fuzz.cc +++ b/test/fuzz/msc_fuzz.cc @@ -159,4 +159,4 @@ int32_t tud_msc_scsi_cb(uint8_t lun, uint8_t const scsi_cmd[16], void *buffer, } } -#endif \ No newline at end of file +#endif diff --git a/test/fuzz/net_fuzz.cc b/test/fuzz/net_fuzz.cc index 8467d6d8e..3158e74ef 100644 --- a/test/fuzz/net_fuzz.cc +++ b/test/fuzz/net_fuzz.cc @@ -79,4 +79,4 @@ void tud_network_link_state_cb(bool state) { } } -#endif \ No newline at end of file +#endif diff --git a/test/fuzz/rules.mk b/test/fuzz/rules.mk index d9c2a1a77..825abddc5 100644 --- a/test/fuzz/rules.mk +++ b/test/fuzz/rules.mk @@ -89,7 +89,7 @@ endif # Rules # --------------------------------------- -all: $(BUILD)/$(PROJECT) +all: $(BUILD)/$(PROJECT) OBJ_DIRS = $(sort $(dir $(OBJ))) $(OBJ): | $(OBJ_DIRS) @@ -111,7 +111,7 @@ vpath %.c . $(TOP) $(BUILD)/obj/%.o: %.c @echo CC $(notdir $@) @$(CC) $(CFLAGS) -c -MD -o $@ $< - + # All cpp srcs vpath %.cc . $(TOP) $(BUILD)/obj/%_cxx.o: %.cc @@ -158,4 +158,4 @@ linkermap: $(BUILD)/$(PROJECT) # Print out the value of a make variable. # https://stackoverflow.com/questions/16467718/how-to-print-out-a-variable-in-makefile print-%: - @echo $* = $($*) \ No newline at end of file + @echo $* = $($*) diff --git a/test/unit-test/test/device/msc/test_msc_device.c b/test/unit-test/test/device/msc/test_msc_device.c index 63684e76a..c757cdcfa 100644 --- a/test/unit-test/test/device/msc/test_msc_device.c +++ b/test/unit-test/test/device/msc/test_msc_device.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, hathach (tinyusb.org) diff --git a/test/unit-test/test/device/usbd/test_usbd.c b/test/unit-test/test/device/usbd/test_usbd.c index ad95eb47a..dcded605a 100644 --- a/test/unit-test/test/device/usbd/test_usbd.c +++ b/test/unit-test/test/device/usbd/test_usbd.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019, Ha Thach (tinyusb.org) diff --git a/test/unit-test/test/test_fifo.c b/test/unit-test/test/test_fifo.c index 28be6d8fc..3b4deb33e 100644 --- a/test/unit-test/test/test_fifo.c +++ b/test/unit-test/test/test_fifo.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) diff --git a/test/unit-test/vendor/ceedling/lib/ceedling.rb b/test/unit-test/vendor/ceedling/lib/ceedling.rb index 7f3400236..6c57fb48d 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling.rb @@ -96,4 +96,3 @@ module Ceedling DEFAULT_CEEDLING_CONFIG[:plugins][:load_paths] << gem_dir end end - diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb b/test/unit-test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb index 5727bcabc..31abe6d99 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb @@ -5,7 +5,7 @@ require 'ceedling/constants' class BuildInvokerUtils constructor :configurator, :streaminator - + ## # Processes exceptions and tries to display a useful message for the user. # @@ -13,27 +13,27 @@ class BuildInvokerUtils # # * _exception_: The exception given by a rescue statement. # * _context_: A symbol representing where in the build the exception - # occurs. + # occurs. # * _test_build_: A bool to signify if the exception occurred while building # from test or source. # def process_exception(exception, context, test_build=true) if (exception.message =~ /Don't know how to build task '(.+)'/i) error_header = "ERROR: Rake could not find file referenced in source" - error_header += " or test" if (test_build) + error_header += " or test" if (test_build) error_header += ": '#{$1}'. Possible stale dependency." - + @streaminator.stderr_puts( error_header ) if (@configurator.project_use_deep_dependencies) - help_message = "Try fixing #include statements or adding missing file. Then run '#{REFRESH_TASK_ROOT}#{context.to_s}' task and try again." + help_message = "Try fixing #include statements or adding missing file. Then run '#{REFRESH_TASK_ROOT}#{context.to_s}' task and try again." @streaminator.stderr_puts( help_message ) end - + raise '' else raise exception end end - + end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator.rb index 519a4aab4..fd7451fa7 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator.rb @@ -2,7 +2,7 @@ class Cacheinator constructor :cacheinator_helper, :file_path_utils, :file_wrapper, :yaml_wrapper - + def cache_test_config(hash) @yaml_wrapper.dump( @file_path_utils.form_test_build_cache_path( INPUT_CONFIGURATION_CACHE_FILE), hash ) end @@ -11,15 +11,15 @@ class Cacheinator @yaml_wrapper.dump( @file_path_utils.form_release_build_cache_path( INPUT_CONFIGURATION_CACHE_FILE ), hash ) end - + def diff_cached_test_file( filepath ) cached_filepath = @file_path_utils.form_test_build_cache_path( filepath ) - + if (@file_wrapper.exist?( cached_filepath ) and (!@file_wrapper.compare( filepath, cached_filepath ))) @file_wrapper.cp(filepath, cached_filepath, {:preserve => false}) return filepath elsif (!@file_wrapper.exist?( cached_filepath )) - @file_wrapper.cp(filepath, cached_filepath, {:preserve => false}) + @file_wrapper.cp(filepath, cached_filepath, {:preserve => false}) return filepath end @@ -43,5 +43,5 @@ class Cacheinator return @cacheinator_helper.diff_cached_config?( cached_filepath, hash ) end - + end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb index 14e8a6ef0..b7fa5863f 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb @@ -2,7 +2,7 @@ class CacheinatorHelper constructor :file_wrapper, :yaml_wrapper - + def diff_cached_config?(cached_filepath, hash) return false if ( not @file_wrapper.exist?(cached_filepath) ) return true if (@yaml_wrapper.load(cached_filepath) != hash) diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/cmock_builder.rb b/test/unit-test/vendor/ceedling/lib/ceedling/cmock_builder.rb index 4a74aa842..82ef96135 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/cmock_builder.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/cmock_builder.rb @@ -1,13 +1,13 @@ require 'cmock' class CmockBuilder - + attr_accessor :cmock - - def setup + + def setup @cmock = nil end - + def manufacture(cmock_config) @cmock = CMock.new(cmock_config) end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/configurator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/configurator.rb index 0ae4d04a8..8dc11aa5a 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/configurator.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/configurator.rb @@ -379,4 +379,3 @@ class Configurator end - diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/configurator_plugins.rb b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_plugins.rb index 75bcd982d..c2e198597 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/configurator_plugins.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_plugins.rb @@ -109,7 +109,7 @@ class ConfiguratorPlugins return defaults_with_path end - # gather up and return + # gather up and return def find_plugin_hash_defaults(config, plugin_paths) defaults_hash= [] diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/configurator_setup.rb b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_setup.rb index c43bb5c12..cba88df3c 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/configurator_setup.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_setup.rb @@ -79,7 +79,7 @@ class ConfiguratorSetup if config[:cmock][:unity_helper] config[:cmock][:unity_helper].each do |path| - validation << @configurator_validator.validate_filepath_simple( path, :cmock, :unity_helper ) + validation << @configurator_validator.validate_filepath_simple( path, :cmock, :unity_helper ) end end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/configurator_validator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_validator.rb index fc0210124..fc2950e0b 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/configurator_validator.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_validator.rb @@ -6,7 +6,7 @@ require 'ceedling/file_path_utils' # for glob handling class methods class ConfiguratorValidator - + constructor :file_wrapper, :stream_wrapper, :system_wrapper # walk into config hash verify existence of data at key depth @@ -16,9 +16,9 @@ class ConfiguratorValidator if (not exist) # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator - @stream_wrapper.stderr_puts("ERROR: Required config file entry #{format_key_sequence(keys, hash[:depth])} does not exist.") + @stream_wrapper.stderr_puts("ERROR: Required config file entry #{format_key_sequence(keys, hash[:depth])} does not exist.") end - + return exist end @@ -33,39 +33,39 @@ class ConfiguratorValidator path_list = [] exist = true - + case list when String then path_list << list when Array then path_list = list end - + path_list.each do |path| base_path = FilePathUtils::extract_path(path) # lop off add/subtract notation & glob specifiers - + if (not @file_wrapper.exist?(base_path)) # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator - @stream_wrapper.stderr_puts("ERROR: Config path #{format_key_sequence(keys, hash[:depth])}['#{base_path}'] does not exist on disk.") + @stream_wrapper.stderr_puts("ERROR: Config path #{format_key_sequence(keys, hash[:depth])}['#{base_path}'] does not exist on disk.") exist = false - end + end end - + return exist end - + # simple path verification def validate_filepath_simple(path, *keys) validate_path = path - + if (not @file_wrapper.exist?(validate_path)) # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator - @stream_wrapper.stderr_puts("ERROR: Config path '#{validate_path}' associated with #{format_key_sequence(keys, keys.size)} does not exist on disk.") + @stream_wrapper.stderr_puts("ERROR: Config path '#{validate_path}' associated with #{format_key_sequence(keys, keys.size)} does not exist on disk.") return false - end - + end + return true end - + # walk into config hash. verify specified file exists. def validate_filepath(config, *keys) hash = retrieve_value(config, keys) @@ -76,21 +76,21 @@ class ConfiguratorValidator # skip everything if we've got an argument replacement pattern return true if (filepath =~ TOOL_EXECUTOR_ARGUMENT_REPLACEMENT_PATTERN) - + if (not @file_wrapper.exist?(filepath)) # See if we can deal with it internally. - if GENERATED_DIR_PATH.include?(filepath) + if GENERATED_DIR_PATH.include?(filepath) # we already made this directory before let's make it again. FileUtils.mkdir_p File.join(File.dirname(__FILE__), filepath) - @stream_wrapper.stderr_puts("WARNING: Generated filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist on disk. Recreating") - + @stream_wrapper.stderr_puts("WARNING: Generated filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist on disk. Recreating") + else # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator @stream_wrapper.stderr_puts("ERROR: Config filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist on disk.") return false end - end + end return true end @@ -106,17 +106,17 @@ class ConfiguratorValidator # skip everything if we've got an argument replacement pattern return true if (filepath =~ TOOL_EXECUTOR_ARGUMENT_REPLACEMENT_PATTERN) - + # if there's no path included, verify file exists somewhere in system search paths if (not filepath.include?('/')) exists = false - + @system_wrapper.search_paths.each do |path| if (@file_wrapper.exist?( File.join(path, filepath)) ) exists = true break end - + if (@file_wrapper.exist?( (File.join(path, filepath)).ext( exe_extension ) )) exists = true break @@ -125,25 +125,25 @@ class ConfiguratorValidator break end end - + if (not exists) # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator - @stream_wrapper.stderr_puts("ERROR: Config filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist in system search paths.") - return false + @stream_wrapper.stderr_puts("ERROR: Config filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist in system search paths.") + return false end - + # if there is a path included, check that explicit filepath exists else if (not @file_wrapper.exist?(filepath)) # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator - @stream_wrapper.stderr_puts("ERROR: Config filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist on disk.") + @stream_wrapper.stderr_puts("ERROR: Config filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist on disk.") return false - end + end end return true end - + def validate_tool_stderr_redirect(config, tools, tool) redirect = config[tools][tool][:stderr_redirect] if (redirect.class == Symbol) @@ -151,17 +151,17 @@ class ConfiguratorValidator if (not StdErrRedirect.constants.map{|constant| constant.to_s}.include?(redirect.to_s.upcase)) error = "ERROR: [:#{tools}][:#{tool}][:stderr_redirect][:#{redirect}] is not a recognized option " + "{#{StdErrRedirect.constants.map{|constant| ':' + constant.to_s.downcase}.join(', ')}}." - @stream_wrapper.stderr_puts(error) - return false + @stream_wrapper.stderr_puts(error) + return false end end - + return true end - + private ######################################### - - + + def retrieve_value(config, keys) value = nil hash = config @@ -178,7 +178,7 @@ class ConfiguratorValidator break end end - + return {:value => value, :depth => depth} end @@ -186,8 +186,8 @@ class ConfiguratorValidator def format_key_sequence(keys, depth) walked_keys = keys.slice(0, depth) formatted_keys = walked_keys.map{|key| "[:#{key.to_s}]"} - + return formatted_keys.join end - + end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/erb_wrapper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/erb_wrapper.rb index 8d70b6d28..dab8d736b 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/erb_wrapper.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/erb_wrapper.rb @@ -6,4 +6,4 @@ class ErbWrapper f << ERB.new(template, 0, "<>").result(binding) end end -end \ No newline at end of file +end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/file_finder.rb b/test/unit-test/vendor/ceedling/lib/ceedling/file_finder.rb index 53775b7bb..4a1064c52 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/file_finder.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/file_finder.rb @@ -146,4 +146,3 @@ class FileFinder return @file_finder_helper.find_file_in_collection(file_path, file_list, complain) end end - diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/file_finder_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/file_finder_helper.rb index a168e5cb5..f2d6a5e91 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/file_finder_helper.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/file_finder_helper.rb @@ -4,11 +4,11 @@ require 'ceedling/constants' # for Verbosity enumeration class FileFinderHelper constructor :streaminator - - + + def find_file_in_collection(file_name, file_list, complain, extra_message="") file_to_find = nil - + file_list.each do |item| base_file = File.basename(item) @@ -22,29 +22,29 @@ class FileFinderHelper blow_up(file_name, "However, a filename having different capitalization was found: '#{item}'.") end end - + end - + if file_to_find.nil? case (complain) - when :error then blow_up(file_name, extra_message) + when :error then blow_up(file_name, extra_message) when :warn then gripe(file_name, extra_message) - #when :ignore then + #when :ignore then end end - + return file_to_find end private - + def blow_up(file_name, extra_message="") error = "ERROR: Found no file '#{file_name}' in search paths." error += ' ' if (extra_message.length > 0) @streaminator.stderr_puts(error + extra_message, Verbosity::ERRORS) raise end - + def gripe(file_name, extra_message="") warning = "WARNING: Found no file '#{file_name}' in search paths." warning += ' ' if (extra_message.length > 0) @@ -52,5 +52,3 @@ class FileFinderHelper end end - - diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/file_system_utils.rb b/test/unit-test/vendor/ceedling/lib/ceedling/file_system_utils.rb index 97e5856fb..245d8f826 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/file_system_utils.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/file_system_utils.rb @@ -6,7 +6,7 @@ require 'ceedling/file_path_utils' class FileSystemUtils - + constructor :file_wrapper # build up path list from input of one or more strings or arrays of (+/-) paths & globs @@ -14,7 +14,7 @@ class FileSystemUtils raw = [] # all paths and globs plus = Set.new # all paths to expand and add minus = Set.new # all paths to remove from plus set - + # assemble all globs and simple paths, reforming our glob notation to ruby globs paths.each do |paths_container| case (paths_container) @@ -26,29 +26,29 @@ class FileSystemUtils # iterate through each path and glob raw.each do |path| - + dirs = [] # container for only (expanded) paths - + # if a glob, expand it and slurp up all non-file paths if path.include?('*') # grab base directory only if globs are snug up to final path separator if (path =~ /\/\*+$/) dirs << FilePathUtils.extract_path(path) end - + # grab expanded sub-directory globs expanded = @file_wrapper.directory_listing( FilePathUtils.extract_path_no_aggregation_operators(path) ) expanded.each do |entry| dirs << entry if @file_wrapper.directory?(entry) end - + # else just grab simple path # note: we could just run this through glob expansion but such an # approach doesn't handle a path not yet on disk) else dirs << FilePathUtils.extract_path_no_aggregation_operators(path) end - + # add dirs to the appropriate set based on path aggregation modifier if present FilePathUtils.add_path?(path) ? plus.merge(dirs) : minus.merge(dirs) end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/file_system_wrapper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/file_system_wrapper.rb index 807cbd23f..1bb2883ee 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/file_system_wrapper.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/file_system_wrapper.rb @@ -7,4 +7,4 @@ class FileSystemWrapper end end -end \ No newline at end of file +end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/flaginator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/flaginator.rb index 31d62c46a..175b3c5ac 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/flaginator.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/flaginator.rb @@ -29,25 +29,25 @@ class Flaginator def get_flag(hash, file_name) file_key = file_name.to_sym - + # 1. try literals - literals, magic = partition(hash) { |k, v| k.to_s =~ /^\w+$/ } + literals, magic = partition(hash) { |k, v| k.to_s =~ /^\w+$/ } return literals[file_key] if literals.include?(file_key) - + any, regex = partition(magic) { |k, v| (k == :'*') || (k == :'.*') } # glob or regex wild card - + # 2. try regexes find_res = regex.find { |k, v| file_name =~ /^#{k.to_s}$/ } return find_res[1] if find_res - + # 3. try anything find_res = any.find { |k, v| file_name =~ /.*/ } return find_res[1] if find_res - + # 4. well, we've tried return [] end - + def flag_down( operation, context, file ) # create configurator accessor method accessor = ('flags_' + context.to_s).to_sym diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/generator_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/generator_helper.rb index 343156092..a6682c275 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/generator_helper.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/generator_helper.rb @@ -9,7 +9,7 @@ class GeneratorHelper def test_results_error_handler(executable, shell_result) notice = '' error = false - + if (shell_result[:output].nil? or shell_result[:output].strip.empty?) error = true # mirror style of generic tool_executor failure output @@ -24,7 +24,7 @@ class GeneratorHelper "> Produced no final test result counts in $stdout:\n" + "#{shell_result[:output].strip}\n" end - + if (error) # since we told the tool executor to ignore the exit code, handle it explicitly here notice += "> And exited with status: [#{shell_result[:exit_code]}] (count of failed tests).\n" if (shell_result[:exit_code] != nil) @@ -33,8 +33,8 @@ class GeneratorHelper notice += "> This is often a symptom of a bad memory access in source or test code.\n\n" @streaminator.stderr_puts(notice, Verbosity::COMPLAIN) - raise + raise end end - + end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results.rb b/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results.rb index 3af2d720a..2cd96478c 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results.rb @@ -77,7 +77,7 @@ class GeneratorTestResults # handle anything preceding filename in line as extra output to be collected stdout = nil stdout_regex = /(.+)#{Regexp.escape(filename)}.+/i - unity_test_time = 0 + unity_test_time = 0 if (line =~ stdout_regex) stdout = $1.clone diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb b/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb index 0b518325b..1d193c844 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb @@ -6,34 +6,34 @@ require 'ceedling/constants' class GeneratorTestResultsSanityChecker constructor :configurator, :streaminator - + def verify(results, unity_exit_code) - + # do no sanity checking if it's disabled return if (@configurator.sanity_checks == TestResultsSanityChecks::NONE) raise "results nil or empty" if results.nil? || results.empty? - ceedling_ignores_count = results[:ignores].size + ceedling_ignores_count = results[:ignores].size ceedling_failures_count = results[:failures].size ceedling_tests_summation = (ceedling_ignores_count + ceedling_failures_count + results[:successes].size) - # Exit code handling is not a sanity check that can always be performed because + # Exit code handling is not a sanity check that can always be performed because # command line simulators may or may not pass through Unity's exit code if (@configurator.sanity_checks >= TestResultsSanityChecks::THOROUGH) # many platforms limit exit codes to a maximum of 255 if ((ceedling_failures_count != unity_exit_code) and (unity_exit_code < 255)) sanity_check_warning(results[:source][:file], "Unity's exit code (#{unity_exit_code}) does not match Ceedling's summation of failed test cases (#{ceedling_failures_count}).") end - + if ((ceedling_failures_count < 255) and (unity_exit_code == 255)) sanity_check_warning(results[:source][:file], "Ceedling's summation of failed test cases (#{ceedling_failures_count}) is less than Unity's exit code (255 or more).") end end - + if (ceedling_ignores_count != results[:counts][:ignored]) sanity_check_warning(results[:source][:file], "Unity's final ignore count (#{results[:counts][:ignored]}) does not match Ceedling's summation of ignored test cases (#{ceedling_ignores_count}).") end - + if (ceedling_failures_count != results[:counts][:failed]) sanity_check_warning(results[:source][:file], "Unity's final fail count (#{results[:counts][:failed]}) does not match Ceedling's summation of failed test cases (#{ceedling_failures_count}).") end @@ -41,14 +41,14 @@ class GeneratorTestResultsSanityChecker if (ceedling_tests_summation != results[:counts][:total]) sanity_check_warning(results[:source][:file], "Unity's final test count (#{results[:counts][:total]}) does not match Ceedling's summation of all test cases (#{ceedling_tests_summation}).") end - + end private - + def sanity_check_warning(file, message) unless defined?(CEEDLING_IGNORE_SANITY_CHECK) - notice = "\n" + + notice = "\n" + "ERROR: Internal sanity check for test fixture '#{file.ext(@configurator.extension_executable)}' finds that #{message}\n" + " Possible causes:\n" + " 1. Your test + source dereferenced a null pointer.\n" + @@ -56,7 +56,7 @@ class GeneratorTestResultsSanityChecker " 3. Your test + source committed a memory access violation.\n" + " 4. Your test fixture produced an exit code of 0 despite execution ending prematurely.\n" + " Sanity check failures of test results are usually a symptom of interrupted test execution.\n\n" - + @streaminator.stderr_puts( notice ) raise end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/loginator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/loginator.rb index 92276e1df..38147b322 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/loginator.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/loginator.rb @@ -11,7 +11,7 @@ class Loginator config_files.concat( @project_config_manager.options_files ) config_files.compact! config_files.map! { |file| file.ext('') } - + log_name = config_files.join( '_' ) @project_log_filepath = File.join( @configurator.project_log_path, log_name.ext('.log') ) @@ -20,12 +20,12 @@ class Loginator def log(string, heading=nil) return if (not @configurator.project_logging) - + output = "\n[#{@system_wrapper.time_now}]" output += " :: #{heading}" if (not heading.nil?) output += "\n#{string.strip}\n" @file_wrapper.write(@project_log_filepath, output, 'a') end - + end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/makefile.rb b/test/unit-test/vendor/ceedling/lib/ceedling/makefile.rb index c3d7496d2..9ad894ea0 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/makefile.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/makefile.rb @@ -1,6 +1,6 @@ # modified version of Rake's provided make-style dependency loader -# customizations: +# customizations: # (1) handles windows drives in paths -- colons don't confuse task demarcation # (2) handles spaces in directory paths @@ -29,7 +29,7 @@ module Rake file_tasks, args = line.split(/:\s/) return if args.nil? - + # split at non-escaped space boundary between files (i.e. escaped spaces in paths are left alone) dependents = args.split(/\b\s+/) # replace escaped spaces and clean up any extra whitespace diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/objects.yml b/test/unit-test/vendor/ceedling/lib/ceedling/objects.yml index 43bbc066c..d73987f7c 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/objects.yml +++ b/test/unit-test/vendor/ceedling/lib/ceedling/objects.yml @@ -223,7 +223,7 @@ dependinator: - configurator - project_config_manager - test_includes_extractor - - file_path_utils + - file_path_utils - rake_wrapper - file_wrapper diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/par_map.rb b/test/unit-test/vendor/ceedling/lib/ceedling/par_map.rb index 98198a2ce..250b5ad30 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/par_map.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/par_map.rb @@ -16,4 +16,3 @@ def par_map(n, things, &block) end threads.each { |t| t.join } end - diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/plugin.rb b/test/unit-test/vendor/ceedling/lib/ceedling/plugin.rb index f20b3a3b2..835c08c52 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/plugin.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/plugin.rb @@ -5,7 +5,7 @@ class String def left_margin(margin=0) non_whitespace_column = 0 new_lines = [] - + # find first line with non-whitespace and count left columns of whitespace self.each_line do |line| if (line =~ /^\s*\S/) @@ -13,7 +13,7 @@ class String break end end - + # iterate through each line, chopping off leftmost whitespace columns and add back the desired whitespace margin self.each_line do |line| columns = [] @@ -25,7 +25,7 @@ class String new_lines << "\n" end end - + return new_lines.join end end @@ -74,7 +74,7 @@ class Plugin # whole shebang (any use of Ceedling) def pre_build; end def post_build; end - + def summary; end end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/plugin_builder.rb b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_builder.rb index 1269141f1..a010e1d0f 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/plugin_builder.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_builder.rb @@ -23,7 +23,7 @@ class PluginBuilder end private - + def camelize(underscored_name) return underscored_name.gsub(/(_|^)([a-z0-9])/) {$2.upcase} end @@ -50,4 +50,4 @@ class PluginBuilder end end -end \ No newline at end of file +end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator.rb index 8d83727ba..afc54494b 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator.rb @@ -2,46 +2,46 @@ require 'ceedling/constants' require 'ceedling/defaults' class PluginReportinator - + constructor :plugin_reportinator_helper, :plugin_manager, :reportinator def setup @test_results_template = nil end - - + + def set_system_objects(system_objects) @plugin_reportinator_helper.ceedling = system_objects end - - + + def fetch_results(results_path, test, options={:boom => false}) return @plugin_reportinator_helper.fetch_results( File.join(results_path, test), options ) end - + def generate_banner(message) return @reportinator.generate_banner(message) end - + def assemble_test_results(results_list, options={:boom => false}) aggregated_results = get_results_structure - - results_list.each do |result_path| + + results_list.each do |result_path| results = @plugin_reportinator_helper.fetch_results( result_path, options ) @plugin_reportinator_helper.process_results(aggregated_results, results) end return aggregated_results end - - + + def register_test_results_template(template) @test_results_template = template if (@test_results_template.nil?) end - - + + def run_test_results_report(hash, verbosity=Verbosity::NORMAL, &block) run_report( $stdout, ((@test_results_template.nil?) ? DEFAULT_TESTS_RESULTS_REPORT_TEMPLATE : @test_results_template), @@ -49,19 +49,19 @@ class PluginReportinator verbosity, &block ) end - - + + def run_report(stream, template, hash=nil, verbosity=Verbosity::NORMAL) failure = nil failure = yield() if block_given? - + @plugin_manager.register_build_failure( failure ) - + @plugin_reportinator_helper.run_report( stream, template, hash, verbosity ) end - + private ############################### - + def get_results_structure return { :successes => [], @@ -72,5 +72,5 @@ class PluginReportinator :time => 0.0 } end - + end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb index 322a530b5..783158797 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb @@ -4,11 +4,11 @@ require 'rake' # for ext() require 'ceedling/constants' class PluginReportinatorHelper - + attr_writer :ceedling - + constructor :configurator, :streaminator, :yaml_wrapper, :file_wrapper - + def fetch_results(results_path, options) pass_path = File.join(results_path.ext( @configurator.extension_testpass )) fail_path = File.join(results_path.ext( @configurator.extension_testfail )) @@ -23,7 +23,7 @@ class PluginReportinatorHelper raise end end - + return {} end @@ -47,5 +47,5 @@ class PluginReportinatorHelper output = ERB.new(template, 0, "%<>") @streaminator.stream_puts(stream, output.result(binding()), verbosity) end - + end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb b/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb index 8b89c0b3a..916d31332 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb @@ -94,7 +94,7 @@ class PreprocessinatorIncludesHandler target_file = make_rule.split[0].gsub(':', '').gsub('\\','/') base = File.basename(target_file, File.extname(target_file)) make_rule_dependencies = make_rule.gsub(/.*\b#{Regexp.escape(base)}\S*/, '').gsub(/\\$/, '') - + # Extract the headers dependencies from the make rule hdr_ext = @configurator.extension_header headers_dependencies = make_rule_dependencies.split.find_all {|path| path.end_with?(hdr_ext) }.uniq diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/project_config_manager.rb b/test/unit-test/vendor/ceedling/lib/ceedling/project_config_manager.rb index ed7a73b8c..b1d455127 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/project_config_manager.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/project_config_manager.rb @@ -20,7 +20,7 @@ class ProjectConfigManager def merge_options(config_hash, option_filepath) @options_files << File.basename( option_filepath ) config_hash.deep_merge!( @yaml_wrapper.load( option_filepath ) ) - end + end def filter_internal_sources(sources) diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/rake_utils.rb b/test/unit-test/vendor/ceedling/lib/ceedling/rake_utils.rb index 3f667c852..b13749738 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/rake_utils.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/rake_utils.rb @@ -1,6 +1,6 @@ class RakeUtils - + constructor :rake_wrapper def task_invoked?(task_regex) diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/reportinator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/reportinator.rb index 0f583d06d..fcb5286b9 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/reportinator.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/reportinator.rb @@ -14,8 +14,8 @@ class Reportinator # ==== Examples # # rp = Reportinator.new - # rp.generate_banner("Hello world!") => "------------\nHello world!\n------------\n" - # rp.generate_banner("Hello world!", 3) => "---\nHello world!\n---\n" + # rp.generate_banner("Hello world!") => "------------\nHello world!\n------------\n" + # rp.generate_banner("Hello world!", 3) => "---\nHello world!\n---\n" # # def generate_banner(message, width=nil) diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/rules_cmock.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_cmock.rake index 70ddcbc2e..51485d3a8 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/rules_cmock.rake +++ b/test/unit-test/vendor/ceedling/lib/ceedling/rules_cmock.rake @@ -3,7 +3,7 @@ rule(/#{CMOCK_MOCK_PREFIX}[^\/\\]+#{'\\'+EXTENSION_SOURCE}$/ => [ proc do |task_name| @ceedling[:file_finder].find_header_input_for_mock_file(task_name) - end + end ]) do |mock| @ceedling[:generator].generate_mock(TEST_SYM, mock.source) end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/rules_preprocess.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_preprocess.rake index c29111272..936961ce8 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/rules_preprocess.rake +++ b/test/unit-test/vendor/ceedling/lib/ceedling/rules_preprocess.rake @@ -6,7 +6,7 @@ rule(/#{PROJECT_TEST_PREPROCESS_FILES_PATH}\/.+/ => [ proc do |task_name| @ceedling[:file_finder].find_test_or_source_or_header_file(task_name) - end + end ]) do |file| if (not @ceedling[:configurator].project_use_deep_dependencies) raise 'ERROR: Ceedling preprocessing rule invoked though neccessary auxiliary dependency support not enabled.' @@ -19,8 +19,7 @@ end rule(/#{PROJECT_TEST_PREPROCESS_INCLUDES_PATH}\/.+/ => [ proc do |task_name| @ceedling[:file_finder].find_test_or_source_or_header_file(task_name) - end + end ]) do |file| @ceedling[:generator].generate_shallow_includes_list(TEST_SYM, file.source) end - diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/rules_release.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_release.rake index 4a583bd6c..47eec858f 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/rules_release.rake +++ b/test/unit-test/vendor/ceedling/lib/ceedling/rules_release.rake @@ -96,4 +96,3 @@ namespace RELEASE_SYM do end end - diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake index 9550783cc..bf944de25 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake +++ b/test/unit-test/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake @@ -3,7 +3,7 @@ rule(/#{PROJECT_RELEASE_DEPENDENCIES_PATH}\/#{'.+\\'+EXTENSION_DEPENDENCIES}$/ => [ proc do |task_name| @ceedling[:file_finder].find_compilation_input_file(task_name, :error, true) - end + end ]) do |dep| @ceedling[:generator].generate_dependencies_file( TOOLS_RELEASE_DEPENDENCIES_GENERATOR, @@ -12,4 +12,3 @@ rule(/#{PROJECT_RELEASE_DEPENDENCIES_PATH}\/#{'.+\\'+EXTENSION_DEPENDENCIES}$/ = @ceedling[:file_path_utils].form_release_build_c_object_filepath(dep.source), dep.name) end - diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests.rake index 61e15e2cc..3ab80f3a9 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests.rake +++ b/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests.rake @@ -70,4 +70,3 @@ namespace TEST_SYM do @ceedling[:test_invoker].setup_and_invoke([test.source]) end end - diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake index 7175ee3f2..a8dfd296e 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake +++ b/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake @@ -12,4 +12,3 @@ rule(/#{PROJECT_TEST_DEPENDENCIES_PATH}\/#{'.+\\'+EXTENSION_DEPENDENCIES}$/ => [ @ceedling[:file_path_utils].form_test_build_c_object_filepath(dep.source), dep.name) end - diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/setupinator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/setupinator.rb index ea78fd97e..cf9922f07 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/setupinator.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/setupinator.rb @@ -18,7 +18,7 @@ class Setupinator @config_hash = config_hash # load up all the constants and accessors our rake files, objects, & external scripts will need; - # note: configurator modifies the cmock section of the hash with a couple defaults to tie + # note: configurator modifies the cmock section of the hash with a couple defaults to tie # project together - the modified hash is used to build cmock object @ceedling[:configurator].populate_defaults( config_hash ) @ceedling[:configurator].populate_unity_defaults( config_hash ) @@ -31,16 +31,16 @@ class Setupinator @ceedling[:configurator].standardize_paths( config_hash ) @ceedling[:configurator].validate( config_hash ) @ceedling[:configurator].build( config_hash, :environment ) - + @ceedling[:configurator].insert_rake_plugins( @ceedling[:configurator].rake_plugins ) @ceedling[:configurator].tools_supplement_arguments( config_hash ) - + # merge in any environment variables plugins specify, after the main build @ceedling[:plugin_manager].load_plugin_scripts( @ceedling[:configurator].script_plugins, @ceedling ) do |env| @ceedling[:configurator].eval_environment_variables( env ) @ceedling[:configurator].build_supplement( config_hash, env ) end - + @ceedling[:plugin_reportinator].set_system_objects( @ceedling ) @ceedling[:file_finder].prepare_search_sources @ceedling[:loginator].setup_log_filepath diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/stream_wrapper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/stream_wrapper.rb index 7e160527f..2cee58d3e 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/stream_wrapper.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/stream_wrapper.rb @@ -16,7 +16,7 @@ class StreamWrapper def stdout_flush $stdout.flush end - + def stderr_puts(string) $stderr.puts(string) end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/streaminator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/streaminator.rb index b8dcd070f..e30440c7d 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/streaminator.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/streaminator.rb @@ -12,7 +12,7 @@ class Streaminator @stream_wrapper.stdout_puts(string) @stream_wrapper.stdout_flush end - + # write to log as though Verbosity::OBNOXIOUS @loginator.log( string, @streaminator_helper.extract_name($stdout) ) end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/streaminator_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/streaminator_helper.rb index 9fb5cc0b7..cbaef7c92 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/streaminator_helper.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/streaminator_helper.rb @@ -8,7 +8,7 @@ class StreaminatorHelper when 2 then '#' else stream.inspect end - + return name end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/system_utils.rb b/test/unit-test/vendor/ceedling/lib/ceedling/system_utils.rb index 477aba4f1..81bb7bc54 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/system_utils.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/system_utils.rb @@ -13,7 +13,7 @@ class SystemUtils constructor :system_wrapper ## - # Sets up the class. + # Sets up the class. def setup @tcsh_shell = nil end @@ -23,7 +23,7 @@ class SystemUtils def tcsh_shell? # once run a single time, return state determined at that execution return @tcsh_shell if not @tcsh_shell.nil? - + result = @system_wrapper.shell_backticks('echo $version') if ((result[:exit_code] == 0) and (result[:output].strip =~ /^tcsh/)) @@ -31,7 +31,7 @@ class SystemUtils else @tcsh_shell = false end - + return @tcsh_shell end end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/task_invoker.rb b/test/unit-test/vendor/ceedling/lib/ceedling/task_invoker.rb index 7bfabbb12..35f92ae03 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/task_invoker.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/task_invoker.rb @@ -11,7 +11,7 @@ class TaskInvoker @release_regexs = [/^#{RELEASE_ROOT_NAME}(:|$)/] @first_run = true end - + def add_test_task_regex(regex) @test_regexs << regex end @@ -19,26 +19,26 @@ class TaskInvoker def add_release_task_regex(regex) @release_regexs << regex end - + def test_invoked? invoked = false - + @test_regexs.each do |regex| invoked = true if (@rake_utils.task_invoked?(regex)) break if invoked end - + return invoked end - + def release_invoked? invoked = false - + @release_regexs.each do |regex| invoked = true if (@rake_utils.task_invoked?(regex)) break if invoked end - + return invoked end @@ -60,7 +60,7 @@ class TaskInvoker @rake_wrapper[mock].invoke } end - + def invoke_test_runner(runner) @dependinator.enhance_runner_dependencies( runner ) reset_rake_task_for_changed_defines( runner ) @@ -112,11 +112,11 @@ class TaskInvoker @rake_wrapper[file].invoke end end - + def invoke_release_objects(objects) par_map(PROJECT_COMPILE_THREADS, objects) do |object| @rake_wrapper[object].invoke end end - + end diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_base.rake b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_base.rake index a35cde75e..67a3b503a 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_base.rake +++ b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_base.rake @@ -113,4 +113,3 @@ task :summary do puts "\nNOTE: Summaries may be out of date with project sources.\n\n" end end - diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_filesystem.rake b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_filesystem.rake index 7b950ca0b..8263955fa 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_filesystem.rake +++ b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_filesystem.rake @@ -109,5 +109,3 @@ namespace :files do end end - - diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_release.rake b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_release.rake index b313b2f53..9d3a59c53 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_release.rake +++ b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_release.rake @@ -5,8 +5,8 @@ require 'ceedling/file_path_utils' desc "Build release target." task RELEASE_SYM => [:directories] do header = "Release build '#{File.basename(PROJECT_RELEASE_BUILD_TARGET)}'" - @ceedling[:streaminator].stdout_puts("\n\n#{header}\n#{'-' * header.length}") - + @ceedling[:streaminator].stdout_puts("\n\n#{header}\n#{'-' * header.length}") + begin @ceedling[:plugin_manager].pre_release @@ -15,16 +15,15 @@ task RELEASE_SYM => [:directories] do @ceedling[:project_config_manager].process_release_config_change core_objects.concat( @ceedling[:release_invoker].setup_and_invoke_c_objects( COLLECTION_ALL_SOURCE ) ) - + # if assembler use isn't enabled, COLLECTION_ALL_ASSEMBLY is empty array & nothing happens core_objects.concat( @ceedling[:release_invoker].setup_and_invoke_asm_objects( COLLECTION_ALL_ASSEMBLY ) ) - + # if we're using libraries, we need to add those to our collection as well library_objects = (defined? LIBRARIES_RELEASE && !LIBRARIES_RELEASE.empty?) ? LIBRARIES_RELEASE.flatten.compact : [] file( PROJECT_RELEASE_BUILD_TARGET => (core_objects + extra_objects + library_objects) ) Rake::Task[PROJECT_RELEASE_BUILD_TARGET].invoke ensure - @ceedling[:plugin_manager].post_release + @ceedling[:plugin_manager].post_release end end - diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_tests.rake b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_tests.rake index 6c51ebcc9..5c1006b36 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_tests.rake +++ b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_tests.rake @@ -59,4 +59,3 @@ namespace TEST_SYM do end end - diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/test_invoker_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/test_invoker_helper.rb index 403d93e3e..a48edf9f9 100644 --- a/test/unit-test/vendor/ceedling/lib/ceedling/test_invoker_helper.rb +++ b/test/unit-test/vendor/ceedling/lib/ceedling/test_invoker_helper.rb @@ -19,14 +19,14 @@ class TestInvokerHelper yield( dependencies_list ) if block_given? end - + def extract_sources(test) sources = [] includes = @test_includes_extractor.lookup_includes_list(test) - + includes.each { |include| sources << @file_finder.find_compilation_input_file(include, :ignore) } - + return sources.compact end - + end diff --git a/test/unit-test/vendor/ceedling/plugins/beep/lib/beep.rb b/test/unit-test/vendor/ceedling/plugins/beep/lib/beep.rb index 6a6d01ab2..cbc5e3e38 100644 --- a/test/unit-test/vendor/ceedling/plugins/beep/lib/beep.rb +++ b/test/unit-test/vendor/ceedling/plugins/beep/lib/beep.rb @@ -37,4 +37,3 @@ class Beep < Plugin end end end - diff --git a/test/unit-test/vendor/ceedling/plugins/bullseye/README.md b/test/unit-test/vendor/ceedling/plugins/bullseye/README.md index ab0b53b45..aad449204 100644 --- a/test/unit-test/vendor/ceedling/plugins/bullseye/README.md +++ b/test/unit-test/vendor/ceedling/plugins/bullseye/README.md @@ -5,7 +5,7 @@ ceedling-bullseye Plugin for integrating Bullseye code coverage tool into Ceedling projects. This plugin requires a working license to Bullseye code coverage tools. The tools -must be within the path or the path should be added to the environment in the +must be within the path or the path should be added to the environment in the `project.yml file`. ## Configuration diff --git a/test/unit-test/vendor/ceedling/plugins/bullseye/assets/template.erb b/test/unit-test/vendor/ceedling/plugins/bullseye/assets/template.erb index 504f85583..e1ef9874b 100644 --- a/test/unit-test/vendor/ceedling/plugins/bullseye/assets/template.erb +++ b/test/unit-test/vendor/ceedling/plugins/bullseye/assets/template.erb @@ -12,4 +12,3 @@ BRANCHES: <%=sprintf(format_string, hash[:coverage][:branches])%>% % else BRANCHES: none % end - diff --git a/test/unit-test/vendor/ceedling/plugins/bullseye/lib/bullseye.rb b/test/unit-test/vendor/ceedling/plugins/bullseye/lib/bullseye.rb index ffa444ac7..3e7622006 100644 --- a/test/unit-test/vendor/ceedling/plugins/bullseye/lib/bullseye.rb +++ b/test/unit-test/vendor/ceedling/plugins/bullseye/lib/bullseye.rb @@ -38,7 +38,7 @@ class Bullseye < Plugin @ceedling[:plugin_manager].pre_compile_execute(arg_hash) @ceedling[:streaminator].stdout_puts("Compiling #{File.basename(source)} with coverage...") - compile_command = + compile_command = @ceedling[:tool_executor].build_command_line( TOOLS_BULLSEYE_COMPILER, @ceedling[:flaginator].flag_down( OPERATION_COMPILE_SYM, BULLSEYE_SYM, source ), @@ -48,14 +48,14 @@ class Bullseye < Plugin coverage_command = @ceedling[:tool_executor].build_command_line(TOOLS_BULLSEYE_INSTRUMENTATION, [], compile_command[:line] ) shell_result = @ceedling[:tool_executor].exec( coverage_command[:line], coverage_command[:options] ) - + arg_hash[:shell_result] = shell_result @ceedling[:plugin_manager].post_compile_execute(arg_hash) end def post_test_fixture_execute(arg_hash) result_file = arg_hash[:result_file] - + if ((result_file =~ /#{BULLSEYE_RESULTS_PATH}/) and (not @result_list.include?(result_file))) @result_list << arg_hash[:result_file] end @@ -70,13 +70,13 @@ class Bullseye < Plugin :header => BULLSEYE_ROOT_NAME.upcase, :results => results } - + @ceedling[:plugin_reportinator].run_test_results_report(hash) do message = '' message = 'Unit test failures.' if (results[:counts][:failed] > 0) message end - + # coverage results return if (verify_coverage_file() == false) if (@ceedling[:task_invoker].invoked?(/^#{BULLSEYE_TASK_ROOT}(all|delta)/)) @@ -100,13 +100,13 @@ class Bullseye < Plugin } @ceedling[:plugin_reportinator].run_test_results_report(hash) - + # coverage results command = @ceedling[:tool_executor].build_command_line(TOOLS_BULLSEYE_REPORT_COVSRC) shell_result = @ceedling[:tool_executor].exec(command[:line], command[:options]) report_coverage_results_all(shell_result[:output]) end - + def enableBullseye(enable) if BULLSEYE_AUTO_LICENSE if (enable) @@ -117,14 +117,14 @@ class Bullseye < Plugin @ceedling[:streaminator].stdout_puts("Reverting Bullseye to previous state") end - args.each do |arg| + args.each do |arg| command = @ceedling[:tool_executor].build_command_line(TOOLS_BULLSEYE_BUILD_ENABLE_DISABLE, [], arg) shell_result = @ceedling[:tool_executor].exec(command[:line], command[:options]) end end end - + private ################################### def report_coverage_results_all(coverage) @@ -139,7 +139,7 @@ class Bullseye < Plugin if (coverage =~ /^Total.*?=\s+([0-9]+)\%/) results[:coverage][:functions] = $1.to_i end - + if (coverage =~ /^Total.*=\s+([0-9]+)\%\s*$/) results[:coverage][:branches] = $1.to_i end @@ -177,10 +177,10 @@ class Bullseye < Plugin banner = @ceedling[:plugin_reportinator].generate_banner( "#{BULLSEYE_ROOT_NAME.upcase}: CODE COVERAGE SUMMARY" ) @ceedling[:streaminator].stdout_puts "\n" + banner + "\nNo coverage file.\n\n" end - + return exist end - + end @@ -188,7 +188,7 @@ end END { # cache our input configurations to use in comparison upon next execution if (@ceedling[:task_invoker].invoked?(/^#{BULLSEYE_TASK_ROOT}/)) - @ceedling[:cacheinator].cache_test_config( @ceedling[:setupinator].config_hash ) + @ceedling[:cacheinator].cache_test_config( @ceedling[:setupinator].config_hash ) @ceedling[BULLSEYE_SYM].enableBullseye(false) end } diff --git a/test/unit-test/vendor/ceedling/plugins/colour_report/README.md b/test/unit-test/vendor/ceedling/plugins/colour_report/README.md index 4e0fcd45e..5f4ff77b1 100644 --- a/test/unit-test/vendor/ceedling/plugins/colour_report/README.md +++ b/test/unit-test/vendor/ceedling/plugins/colour_report/README.md @@ -3,7 +3,7 @@ ceedling-colour-report ## Overview -The colour_report replaces the normal ceedling "pretty" output with +The colour_report replaces the normal ceedling "pretty" output with a colorized variant, in order to make the results easier to read from a standard command line. This is very useful on developer machines, but can occasionally cause problems with parsing on CI servers. diff --git a/test/unit-test/vendor/ceedling/plugins/command_hooks/lib/command_hooks.rb b/test/unit-test/vendor/ceedling/plugins/command_hooks/lib/command_hooks.rb index 4bf8b5312..67e94f935 100644 --- a/test/unit-test/vendor/ceedling/plugins/command_hooks/lib/command_hooks.rb +++ b/test/unit-test/vendor/ceedling/plugins/command_hooks/lib/command_hooks.rb @@ -89,4 +89,3 @@ class CommandHooks < Plugin end end end - diff --git a/test/unit-test/vendor/ceedling/plugins/compile_commands_json/README.md b/test/unit-test/vendor/ceedling/plugins/compile_commands_json/README.md index ea80b7397..7e3846e56 100644 --- a/test/unit-test/vendor/ceedling/plugins/compile_commands_json/README.md +++ b/test/unit-test/vendor/ceedling/plugins/compile_commands_json/README.md @@ -9,7 +9,7 @@ In June of 2016, Microsoft with Red Hat and Codenvy got together to create a sta For C and C++ projects, many people use the `clangd` backend. So that it can do things like "go to definition", `clangd` needs to know how to build the project so that it can figure out all the pieces to the puzzle. There are manual tools such as `bear` which can be run with `gcc` or `clang` to extract this information it has a big limitation in that if run with `ceedling release` you won't get any auto completion for Unity and you'll also get error messages reported by your IDE because of what it perceives as missing headers. If you do the same with `ceedling test` now you get Unity but you might miss things that are only seen in the release build. -This plugin resolves that issue. As it is run by Ceedling, it has access to all the build information it needs to create the perfect `compile_commands.json`. Once enabled, this plugin will generate that file and place it in `./build/artifacts/compile_commands.json`. `clangd` will search your project for this file, but it is easier to symlink it into the root directory (for example `ln -s ./build/artifacts/compile_commands.json`. +This plugin resolves that issue. As it is run by Ceedling, it has access to all the build information it needs to create the perfect `compile_commands.json`. Once enabled, this plugin will generate that file and place it in `./build/artifacts/compile_commands.json`. `clangd` will search your project for this file, but it is easier to symlink it into the root directory (for example `ln -s ./build/artifacts/compile_commands.json`. For more information on LSP and to find out if your editor supports it, check out https://langserver.org/ diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/Rakefile b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/Rakefile index bc5594110..2fd9f859f 100644 --- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/Rakefile +++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/Rakefile @@ -16,4 +16,4 @@ task :integration_test do end end -task :default => [:spec, :integration_test] \ No newline at end of file +task :default => [:spec, :integration_test] diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml index 6bda22291..00e395d0c 100644 --- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml +++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml @@ -28,7 +28,7 @@ :source: - src/** :support: - + :defines: # in order to add common defines: # 1) remove the trailing [] from the :common: section diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.c b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.c index 2f03449b0..797d46878 100644 --- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.c +++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.c @@ -4,4 +4,4 @@ void display_turnOffStatusLed(void) { printf("Display: Status LED off"); -} \ No newline at end of file +} diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/lib/fff_mock_generator.rb b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/lib/fff_mock_generator.rb index 9dc03a653..d439a8d7f 100644 --- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/lib/fff_mock_generator.rb +++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/lib/fff_mock_generator.rb @@ -90,7 +90,7 @@ class FffMockGenerator # In the init function, reset the FFF globals. These are used for things # like the call history. output.puts " FFF_RESET_HISTORY();" - + # Also, reset all of the fakes. if parsed_header[:functions] parsed_header[:functions].each do |function| diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_header_generator_spec.rb b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_header_generator_spec.rb index e6ac11dd0..09d317551 100644 --- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_header_generator_spec.rb +++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_header_generator_spec.rb @@ -254,7 +254,7 @@ describe "FffMockGenerator.create_mock_header" do ) end end - + context "when there is a function that returns a const int" do let(:mock_header){ parsed_header = {} diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_source_generator_spec.rb b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_source_generator_spec.rb index 364f8521e..7b7f04f58 100644 --- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_source_generator_spec.rb +++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_source_generator_spec.rb @@ -146,4 +146,4 @@ describe "FffMockGenerator.create_mock_source" do ) end end -end \ No newline at end of file +end diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/header_generator.rb b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/header_generator.rb index cda278440..3b6fa7120 100644 --- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/header_generator.rb +++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/header_generator.rb @@ -48,4 +48,4 @@ def create_cmock_style_parsed_header(functions, typedefs = nil) end end parsed_header -end \ No newline at end of file +end diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/src/fff_unity_helper.h b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/src/fff_unity_helper.h index de3db44aa..970ecbb35 100644 --- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/src/fff_unity_helper.h +++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/src/fff_unity_helper.h @@ -30,4 +30,4 @@ fff.call_history[order_], \ "Function " #function_ " not called in order " #order_ ) -#endif \ No newline at end of file +#endif diff --git a/test/unit-test/vendor/ceedling/plugins/gcov/assets/template.erb b/test/unit-test/vendor/ceedling/plugins/gcov/assets/template.erb index 5e5a1742b..266750497 100644 --- a/test/unit-test/vendor/ceedling/plugins/gcov/assets/template.erb +++ b/test/unit-test/vendor/ceedling/plugins/gcov/assets/template.erb @@ -12,4 +12,3 @@ BRANCHES: <%=sprintf(format_string, hash[:coverage][:branches])%>% % else BRANCHES: none % end - diff --git a/test/unit-test/vendor/ceedling/plugins/gcov/lib/reportinator_helper.rb b/test/unit-test/vendor/ceedling/plugins/gcov/lib/reportinator_helper.rb index 92617fba5..10a0a6c5c 100644 --- a/test/unit-test/vendor/ceedling/plugins/gcov/lib/reportinator_helper.rb +++ b/test/unit-test/vendor/ceedling/plugins/gcov/lib/reportinator_helper.rb @@ -5,7 +5,7 @@ class ReportinatorHelper def print_shell_result(shell_result) if !(shell_result.nil?) puts "Done in %.3f seconds." % shell_result[:time] - + if !(shell_result[:output].nil?) && (shell_result[:output].length > 0) puts shell_result[:output] end diff --git a/test/unit-test/vendor/ceedling/plugins/json_tests_report/README.md b/test/unit-test/vendor/ceedling/plugins/json_tests_report/README.md index 8e5a1e571..b383492e2 100644 --- a/test/unit-test/vendor/ceedling/plugins/json_tests_report/README.md +++ b/test/unit-test/vendor/ceedling/plugins/json_tests_report/README.md @@ -3,8 +3,8 @@ json_tests_report ## Overview -The json_tests_report plugin creates a JSON file of test results, which is -handy for Continuous Integration build servers or as input into other +The json_tests_report plugin creates a JSON file of test results, which is +handy for Continuous Integration build servers or as input into other reporting tools. The JSON file is output to the appropriate `/artifacts/` directory (e.g. `artifacts/test/` for test tasks, `artifacts/gcov/` for gcov, or `artifacts/bullseye/` for bullseye runs). diff --git a/test/unit-test/vendor/ceedling/plugins/json_tests_report/lib/json_tests_report.rb b/test/unit-test/vendor/ceedling/plugins/json_tests_report/lib/json_tests_report.rb index e7023db7b..f09339ee2 100644 --- a/test/unit-test/vendor/ceedling/plugins/json_tests_report/lib/json_tests_report.rb +++ b/test/unit-test/vendor/ceedling/plugins/json_tests_report/lib/json_tests_report.rb @@ -33,7 +33,7 @@ class JsonTestsReport < Plugin "IgnoredTests" => write_tests(results[:ignores]), "Summary" => write_statistics(results[:counts]) } - + f << JSON.pretty_generate(json) end end @@ -62,7 +62,7 @@ class JsonTestsReport < Plugin results.each do |result| result[:collection].each do |item| @test_counter += 1 - retval << { + retval << { "file" => File.join(result[:source][:path], result[:source][:file]), "test" => item[:test] } diff --git a/test/unit-test/vendor/ceedling/plugins/module_generator/README.md b/test/unit-test/vendor/ceedling/plugins/module_generator/README.md index a3c2c7ad9..61cf45bd6 100644 --- a/test/unit-test/vendor/ceedling/plugins/module_generator/README.md +++ b/test/unit-test/vendor/ceedling/plugins/module_generator/README.md @@ -96,7 +96,7 @@ put that corporate copyright notice (or maybe a copyleft notice, if that's your ### Test Defines You can specify the "#ifdef TEST" at the top of the test files with a custom define. -This example will put a "#ifdef CEEDLING_TEST" at the top of the test files. +This example will put a "#ifdef CEEDLING_TEST" at the top of the test files. ``` :module_generator: @@ -115,5 +115,3 @@ Your options are as follows: - `:camel` - camelFilesAreSimilarButStartLow - `:snake` - snake_case_is_all_lower_and_uses_underscores - `:caps` - CAPS_FEELS_LIKE_YOU_ARE_SCREAMING - - diff --git a/test/unit-test/vendor/ceedling/plugins/module_generator/config/module_generator.yml b/test/unit-test/vendor/ceedling/plugins/module_generator/config/module_generator.yml index cdb2da2eb..b90afd0ff 100644 --- a/test/unit-test/vendor/ceedling/plugins/module_generator/config/module_generator.yml +++ b/test/unit-test/vendor/ceedling/plugins/module_generator/config/module_generator.yml @@ -1,4 +1,4 @@ :module_generator: :project_root: ./ :source_root: src/ - :test_root: test/ \ No newline at end of file + :test_root: test/ diff --git a/test/unit-test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/README.md b/test/unit-test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/README.md index 9ab60847e..e95106ed1 100644 --- a/test/unit-test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/README.md +++ b/test/unit-test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/README.md @@ -3,8 +3,8 @@ ceedling-stdout-gtestlike-tests-report ## Overview -The stdout_gtestlike_tests_report replaces the normal ceedling "pretty" output with -a variant that resembles the output of gtest. This is most helpful when trying to +The stdout_gtestlike_tests_report replaces the normal ceedling "pretty" output with +a variant that resembles the output of gtest. This is most helpful when trying to integrate into an IDE or CI that is meant to work with google test. ## Setup diff --git a/test/unit-test/vendor/ceedling/plugins/stdout_ide_tests_report/README.md b/test/unit-test/vendor/ceedling/plugins/stdout_ide_tests_report/README.md index ed6c65582..da04d1c14 100644 --- a/test/unit-test/vendor/ceedling/plugins/stdout_ide_tests_report/README.md +++ b/test/unit-test/vendor/ceedling/plugins/stdout_ide_tests_report/README.md @@ -3,7 +3,7 @@ ceedling-stdout-ide-tests-report ## Overview -The stdout_ide_tests_report replaces the normal ceedling "pretty" output with +The stdout_ide_tests_report replaces the normal ceedling "pretty" output with a simplified variant intended to be easily parseable. ## Setup diff --git a/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/README.md b/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/README.md index 7e1be2382..358aa93ab 100644 --- a/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/README.md +++ b/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/README.md @@ -5,7 +5,7 @@ ceedling-pretty-tests-report The stdout_pretty_tests_report is the default output of ceedling. Instead of showing most of the raw output of CMock, Ceedling, etc., it shows a simplified -view. It also creates a nice summary at the end of execution which groups the +view. It also creates a nice summary at the end of execution which groups the results into ignored and failed tests. ## Setup diff --git a/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/assets/template.erb b/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/assets/template.erb index 52b29f7f0..1c025bf1b 100644 --- a/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/assets/template.erb +++ b/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/assets/template.erb @@ -56,4 +56,3 @@ IGNORED: <%=sprintf(format_string, ignored)%> No tests executed. % end - diff --git a/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/lib/stdout_pretty_tests_report.rb b/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/lib/stdout_pretty_tests_report.rb index 018388fc1..fd9589183 100644 --- a/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/lib/stdout_pretty_tests_report.rb +++ b/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/lib/stdout_pretty_tests_report.rb @@ -2,20 +2,20 @@ require 'ceedling/plugin' require 'ceedling/defaults' class StdoutPrettyTestsReport < Plugin - + def setup @result_list = [] @plugin_root = File.expand_path(File.join(File.dirname(__FILE__), '..')) template = @ceedling[:file_wrapper].read(File.join(@plugin_root, 'assets/template.erb')) @ceedling[:plugin_reportinator].register_test_results_template( template ) end - + def post_test_fixture_execute(arg_hash) return if not (arg_hash[:context] == TEST_SYM) - + @result_list << arg_hash[:result_file] end - + def post_build return if not (@ceedling[:task_invoker].test_invoked?) diff --git a/test/unit-test/vendor/ceedling/plugins/subprojects/README.md b/test/unit-test/vendor/ceedling/plugins/subprojects/README.md index e51a4e60e..ef4caa57b 100644 --- a/test/unit-test/vendor/ceedling/plugins/subprojects/README.md +++ b/test/unit-test/vendor/ceedling/plugins/subprojects/README.md @@ -1,9 +1,9 @@ ceedling-subprojects ==================== -Plugin for supporting subprojects that are built as static libraries. It continues to support -dependency tracking, without getting confused between your main project files and your -subproject files. It accepts different compiler flags and linker flags, allowing you to +Plugin for supporting subprojects that are built as static libraries. It continues to support +dependency tracking, without getting confused between your main project files and your +subproject files. It accepts different compiler flags and linker flags, allowing you to optimize for your situation. First, you're going to want to add the extension to your list of known extensions: @@ -13,12 +13,12 @@ First, you're going to want to add the extension to your list of known extension :subprojects: '.a' ``` -Define a new section called :subprojects. There, you can list as many subprojects -as you may need under the :paths key. For each, you specify a unique place to build +Define a new section called :subprojects. There, you can list as many subprojects +as you may need under the :paths key. For each, you specify a unique place to build and a unique name. ``` -:subprojects: +:subprojects: :paths: - :name: libprojectA :source: @@ -27,7 +27,7 @@ and a unique name. :include: - ./subprojectA/include/dir :build_root: ./subprojectA/build/dir - :defines: + :defines: - DEFINE_JUST_FOR_THIS_FILE - AND_ANOTHER - :name: libprojectB diff --git a/test/unit-test/vendor/ceedling/plugins/subprojects/subprojects.rake b/test/unit-test/vendor/ceedling/plugins/subprojects/subprojects.rake index 0025c3ecd..f80c812f3 100644 --- a/test/unit-test/vendor/ceedling/plugins/subprojects/subprojects.rake +++ b/test/unit-test/vendor/ceedling/plugins/subprojects/subprojects.rake @@ -73,6 +73,5 @@ SUBPROJECTS_PATHS.each do |subproj| task :directories => subproj_directories.clone # Finally, add the static library to our RELEASE build dependency list - task RELEASE_SYM => ["#{subproj_build_root}/#{subproj_name}#{EXTENSION_SUBPROJECTS}"] + task RELEASE_SYM => ["#{subproj_build_root}/#{subproj_name}#{EXTENSION_SUBPROJECTS}"] end - diff --git a/test/unit-test/vendor/ceedling/plugins/teamcity_tests_report/README.md b/test/unit-test/vendor/ceedling/plugins/teamcity_tests_report/README.md index 9fcda7d5b..2467ebe99 100644 --- a/test/unit-test/vendor/ceedling/plugins/teamcity_tests_report/README.md +++ b/test/unit-test/vendor/ceedling/plugins/teamcity_tests_report/README.md @@ -3,7 +3,7 @@ ceedling-teamcity-tests-report ## Overview -The teamcity_tests_report replaces the normal ceedling "pretty" output with +The teamcity_tests_report replaces the normal ceedling "pretty" output with a version that has results tagged to be consumed with the teamcity CI server. ## Setup diff --git a/test/unit-test/vendor/ceedling/vendor/c_exception/lib/CException.c b/test/unit-test/vendor/ceedling/vendor/c_exception/lib/CException.c index fdff8f475..24b3b09e8 100644 --- a/test/unit-test/vendor/ceedling/vendor/c_exception/lib/CException.c +++ b/test/unit-test/vendor/ceedling/vendor/c_exception/lib/CException.c @@ -43,4 +43,3 @@ void Throw(CEXCEPTION_T ExceptionID) } <- finish off that local scope we created to have our own variables if (CExceptionFrames[CEXCEPTION_GET_ID].Exception != CEXCEPTION_NONE) <- start the actual 'catch' processing if we have an exception id saved away */ - diff --git a/test/unit-test/vendor/ceedling/vendor/c_exception/lib/meson.build b/test/unit-test/vendor/ceedling/vendor/c_exception/lib/meson.build index 2770122af..9694e51c7 100644 --- a/test/unit-test/vendor/ceedling/vendor/c_exception/lib/meson.build +++ b/test/unit-test/vendor/ceedling/vendor/c_exception/lib/meson.build @@ -6,6 +6,6 @@ # cexception_dir = include_directories('.') -cexception_lib = static_library(meson.project_name(), +cexception_lib = static_library(meson.project_name(), files('CException.c'), include_directories : cexception_dir) diff --git a/test/unit-test/vendor/ceedling/vendor/cmock/src/cmock.c b/test/unit-test/vendor/ceedling/vendor/cmock/src/cmock.c index 88f2c2b25..d8bdb1369 100644 --- a/test/unit-test/vendor/ceedling/vendor/cmock/src/cmock.c +++ b/test/unit-test/vendor/ceedling/vendor/cmock/src/cmock.c @@ -213,4 +213,3 @@ void CMock_Guts_MemFreeFinal(void) } #endif } - diff --git a/test/unit-test/vendor/ceedling/vendor/cmock/src/meson.build b/test/unit-test/vendor/ceedling/vendor/cmock/src/meson.build index c03c4e5bb..b3145c02e 100644 --- a/test/unit-test/vendor/ceedling/vendor/cmock/src/meson.build +++ b/test/unit-test/vendor/ceedling/vendor/cmock/src/meson.build @@ -6,7 +6,7 @@ # cmock_dir = include_directories('.') -cmock_lib = static_library(meson.project_name(), +cmock_lib = static_library(meson.project_name(), files('cmock.c'), dependencies: [unity_dep], include_directories: cmock_dir) diff --git a/test/unit-test/vendor/ceedling/vendor/diy/lib/diy.rb b/test/unit-test/vendor/ceedling/vendor/diy/lib/diy.rb index 581afc7e6..cbeb8267a 100644 --- a/test/unit-test/vendor/ceedling/vendor/diy/lib/diy.rb +++ b/test/unit-test/vendor/ceedling/vendor/diy/lib/diy.rb @@ -18,8 +18,8 @@ module DIY #:nodoc:# raise "Nil context hash" unless context_hash raise "Need a hash" unless context_hash.kind_of?(Hash) [ "[]", "keys" ].each do |mname| - unless extra_inputs.respond_to?(mname) - raise "Extra inputs must respond to hash-like [] operator and methods #keys and #each" + unless extra_inputs.respond_to?(mname) + raise "Extra inputs must respond to hash-like [] operator and methods #keys and #each" end end @@ -37,7 +37,7 @@ module DIY #:nodoc:# @cache = {} @cache['this_context'] = self end - + # Convenience: create a new DIY::Context by loading from a String (or open file handle.) def self.from_yaml(io_or_string, extra_inputs={}) @@ -51,7 +51,7 @@ module DIY #:nodoc:# self.from_yaml(File.read(fname), extra_inputs) end - # Return a reference to the object named. If necessary, the object will + # Return a reference to the object named. If necessary, the object will # be instantiated on first use. If the object is non-singleton, a new # object will be produced each time. def get_object(obj_name) @@ -77,7 +77,7 @@ module DIY #:nodoc:# end alias :[] :get_object - # Inject a named object into the Context. This must be done before the Context has instantiated the + # Inject a named object into the Context. This must be done before the Context has instantiated the # object in question. def set_object(obj_name,obj) key = obj_name.to_s @@ -108,9 +108,9 @@ module DIY #:nodoc:# @defs.keys.member?(key) or extra_inputs_has(key) end - # Every top level object in the Context is instantiated. This is especially useful for + # Every top level object in the Context is instantiated. This is especially useful for # systems that have "floating observers"... objects that are never directly accessed, who - # would thus never be instantiated by coincedence. This does not build any subcontexts + # would thus never be instantiated by coincedence. This does not build any subcontexts # that may exist. def build_everything @defs.keys.each { |k| self[k] } @@ -131,7 +131,7 @@ module DIY #:nodoc:# # we modify the info hash below so it's important to have a new # instance to play with info = info.dup if info - + # see if we are building a factory if info and info.has_key?('builds') unless info.has_key?('auto_require') @@ -150,21 +150,21 @@ module DIY #:nodoc:# name = name.to_s case name - when /^\+/ + when /^\+/ # subcontext @sub_context_defs[name.gsub(/^\+/,'')] = info - + when /^using_namespace/ # namespace: use a module(s) prefix for the classname of contained object defs # NOTE: namespacing is NOT scope... it's just a convenient way to setup class names for a group of objects. get_defs_from info, parse_namespace(name) when /^method\s/ key_name = name.gsub(/^method\s/, "") - @defs[key_name] = MethodDef.new(:name => key_name, - :object => info['object'], + @defs[key_name] = MethodDef.new(:name => key_name, + :object => info['object'], :method => info['method'], :attach => info['attach']) - else + else # Normal object def info ||= {} if extra_inputs_has(name) @@ -173,14 +173,14 @@ module DIY #:nodoc:# unless info.has_key?('auto_require') info['auto_require'] = self.class.auto_require end - if namespace + if namespace if info['class'] info['class'] = namespace.build_classname(info['class']) else info['class'] = namespace.build_classname(name) end end - + @defs[name] = ObjectDef.new(:name => name, :info => info) end @@ -191,10 +191,10 @@ module DIY #:nodoc:# method_definition = @defs[key] object = get_object(method_definition.object) method = object.method(method_definition.method) - + unless method_definition.attach.nil? instance_var_name = "@__diy_#{method_definition.object}" - + method_definition.attach.each do |object_key| get_object(object_key).instance_eval do instance_variable_set(instance_var_name, object) @@ -202,14 +202,14 @@ module DIY #:nodoc:# #{instance_var_name}.#{method_definition.method}(*args) end| end - end + end end - + return method rescue Exception => oops build_and_raise_construction_error(key, oops) end - + def construct_object(key) # Find the object definition obj_def = @defs[key] @@ -242,13 +242,13 @@ module DIY #:nodoc:# rescue Exception => oops build_and_raise_construction_error(key, oops) end - + def build_and_raise_construction_error(key, oops) cerr = ConstructionError.new(key,oops) cerr.set_backtrace(oops.backtrace) raise cerr end - + def get_class_for_name_with_module_delimeters(class_name) class_name.split(/::/).inject(Object) do |mod,const_name| mod.const_get(const_name) end end @@ -264,7 +264,7 @@ module DIY #:nodoc:# Namespace.new(str) end end - + class Namespace #:nodoc:# def initialize(str) # 'using_namespace Animal Reptile' @@ -292,15 +292,15 @@ module DIY #:nodoc:# @name = obj_name end end - + class MethodDef #:nodoc: attr_accessor :name, :object, :method, :attach - + def initialize(opts) @name, @object, @method, @attach = opts[:name], opts[:object], opts[:method], opts[:attach] end end - + class ObjectDef #:nodoc: attr_accessor :name, :class_name, :library, :components def initialize(opts) @@ -330,7 +330,7 @@ module DIY #:nodoc:# # Use Class Directly @use_class_directly = info.delete 'use_class_directly' - + # Auto-compose compose = info.delete 'compose' if compose @@ -380,7 +380,7 @@ module DIY #:nodoc:# object_name = object_name cause = cause m = "Failed to construct '#{object_name}'" - if cause + if cause m << "\n ...caused by:\n >>> #{cause}" end super m @@ -388,11 +388,11 @@ module DIY #:nodoc:# end class NamespaceError < RuntimeError #:nodoc:# - end + end module Infl #:nodoc:# # Ganked this from Inflector: - def self.camelize(lower_case_and_underscored_word) + def self.camelize(lower_case_and_underscored_word) lower_case_and_underscored_word.to_s.gsub(/\/(.?)/) { "::" + $1.upcase }.gsub(/(^|_)(.)/) { $2.upcase } end # Ganked this from Inflector: diff --git a/test/unit-test/vendor/ceedling/vendor/diy/lib/diy/factory.rb b/test/unit-test/vendor/ceedling/vendor/diy/lib/diy/factory.rb index d2566c5d1..8f00e5e45 100644 --- a/test/unit-test/vendor/ceedling/vendor/diy/lib/diy/factory.rb +++ b/test/unit-test/vendor/ceedling/vendor/diy/lib/diy/factory.rb @@ -1,7 +1,7 @@ module DIY #:nodoc:# class FactoryDef #:nodoc: attr_accessor :name, :target, :class_name, :library - + def initialize(opts) @name, @target, @library, @auto_require = opts[:name], opts[:target], opts[:library], opts[:auto_require] @@ -10,7 +10,7 @@ module DIY #:nodoc:# @library ||= Infl.underscore(@class_name) if @auto_require end end - + class Context def construct_factory(key) factory_def = @defs[key] @@ -33,4 +33,3 @@ module DIY #:nodoc:# end end end - diff --git a/test/unit-test/vendor/ceedling/vendor/unity/auto/generate_config.yml b/test/unit-test/vendor/ceedling/vendor/unity/auto/generate_config.yml index 4a5e47424..c7679aefc 100644 --- a/test/unit-test/vendor/ceedling/vendor/unity/auto/generate_config.yml +++ b/test/unit-test/vendor/ceedling/vendor/unity/auto/generate_config.yml @@ -18,7 +18,7 @@ - Defs.h - Board.h - Exception.h - :boilerplates: + :boilerplates: #these are inserted at the top of generated files. #just comment out or remove if not desired. #use %1$s where you would like the file name to appear (path/extension not included) diff --git a/test/unit-test/vendor/ceedling/vendor/unity/src/meson.build b/test/unit-test/vendor/ceedling/vendor/unity/src/meson.build index 1c7b426ff..5acd51a9b 100644 --- a/test/unit-test/vendor/ceedling/vendor/unity/src/meson.build +++ b/test/unit-test/vendor/ceedling/vendor/unity/src/meson.build @@ -6,6 +6,6 @@ # unity_dir = include_directories('.') -unity_lib = static_library(meson.project_name(), +unity_lib = static_library(meson.project_name(), files('unity.c'), include_directories: unity_dir) diff --git a/tools/build_board.py b/tools/build_board.py index 4593dafa5..13376d126 100644 --- a/tools/build_board.py +++ b/tools/build_board.py @@ -56,7 +56,7 @@ if __name__ == '__main__': result = pool.starmap(build_utils.build_example, pool_args) # sum all element of same index (column sum) result = list(map(sum, list(zip(*result)))) - + # add to total result total_result = list(map(lambda x, y: x + y, total_result, result)) diff --git a/tools/build_utils.py b/tools/build_utils.py index de9052d2d..d0ef52717 100644 --- a/tools/build_utils.py +++ b/tools/build_utils.py @@ -124,4 +124,4 @@ def build_size(make_cmd): sram_size = int(size_list[1]) + int(size_list[2]) return (flash_size, sram_size) - return (0, 0) \ No newline at end of file + return (0, 0) diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf index ba54fe057..d243aab0a 100644 --- a/tools/iar_template.ipcf +++ b/tools/iar_template.ipcf @@ -141,5 +141,5 @@ $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - + diff --git a/tools/mksunxi.py b/tools/mksunxi.py index 04786f429..fd8557cfc 100644 --- a/tools/mksunxi.py +++ b/tools/mksunxi.py @@ -45,4 +45,4 @@ if __name__ == "__main__": if len(sys.argv) != 3: print("Usage: mksunxi.py input.bin output.bin") exit(1) - exit(process_file(sys.argv[1], sys.argv[2])) \ No newline at end of file + exit(process_file(sys.argv[1], sys.argv[2])) diff --git a/tools/pcapng_to_corpus.py b/tools/pcapng_to_corpus.py index 78b1f77a2..9c31365eb 100755 --- a/tools/pcapng_to_corpus.py +++ b/tools/pcapng_to_corpus.py @@ -16,7 +16,7 @@ def extract_packets(pcap_file): def build_corpus_zip(zip_file_output, packets): """Builds a zip file with a file per packet - + The structure of this zip corpus is a simple content addressable storage i.e. seed_file_name == sha256_digest(packet). """ @@ -25,7 +25,7 @@ def build_corpus_zip(zip_file_output, packets): hash = hashlib.sha256(packet).hexdigest() if hash not in out.namelist(): out.writestr(hash, packet) - + def main(pcap_file, output_zip_file): packets = extract_packets(pcap_file) @@ -35,12 +35,10 @@ if __name__ == "__main__": parser = argparse.ArgumentParser( prog = "pcapng_to_corpus.py", description="""Converts a wireshark capture to a zip of binary packet - files suitable for an oss-fuzz corpus. In the case the - zip corpus already exists, this script will modify + files suitable for an oss-fuzz corpus. In the case the + zip corpus already exists, this script will modify the zip file in place adding seed entries.""") parser.add_argument('pcapng_capture_file') parser.add_argument('oss_fuzz_corpus_zip') args = parser.parse_args() main(args.pcapng_capture_file, args.oss_fuzz_corpus_zip) - - diff --git a/tools/usb_drivers/tinyusb_win_usbser.inf b/tools/usb_drivers/tinyusb_win_usbser.inf index e7f7a9b22..659f048ae 100644 --- a/tools/usb_drivers/tinyusb_win_usbser.inf +++ b/tools/usb_drivers/tinyusb_win_usbser.inf @@ -105,4 +105,4 @@ DRIVERFILENAME ="usbser" MFGNAME="tinyusb.org" INSTDISK="tinyusb CDC Driver" DESCRIPTION="tinyusb Serial" -SERVICE="USB RS-232 Emulation Driver" \ No newline at end of file +SERVICE="USB RS-232 Emulation Driver" -- cgit v1.3.1 From d919f107c71021b2dfa20cd9bfe252c4f544422f Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 18 Mar 2023 11:22:44 +0700 Subject: minor clean up --- examples/device/uac2_headset/src/usb_descriptors.h | 8 ++++---- examples/device/usbtmc/src/usbtmc_app.c | 1 - src/class/video/video.h | 2 +- src/common/tusb_compiler.h | 2 +- src/device/usbd.h | 8 ++++---- 5 files changed, 10 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h index 2069cc975..457e69882 100644 --- a/examples/device/uac2_headset/src/usb_descriptors.h +++ b/examples/device/uac2_headset/src/usb_descriptors.h @@ -114,7 +114,7 @@ enum /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\ /* Interface 1, Alternate 2 - alternate interface for data streaming */\ @@ -124,7 +124,7 @@ enum /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\ /* Standard AS Interface Descriptor(4.9.1) */\ @@ -138,7 +138,7 @@ enum /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\ /* Interface 2, Alternate 2 - alternate interface for data streaming */\ @@ -148,7 +148,7 @@ enum /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000) diff --git a/examples/device/usbtmc/src/usbtmc_app.c b/examples/device/usbtmc/src/usbtmc_app.c index f1596f6d0..72989b4fe 100644 --- a/examples/device/usbtmc/src/usbtmc_app.c +++ b/examples/device/usbtmc/src/usbtmc_app.c @@ -242,7 +242,6 @@ void usbtmc_app_task_iter(void) { break; default: TU_ASSERT(false,); - return; } } diff --git a/src/class/video/video.h b/src/class/video/video.h index 40dae4c1a..c0088c4f6 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -549,7 +549,7 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c /* 3.10.1.1 */ #define TUD_VIDEO_DESC_EP_ISO(_ep, _epsize, _ep_interval) \ - 7, TUSB_DESC_ENDPOINT, _ep, (uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS,\ + 7, TUSB_DESC_ENDPOINT, _ep, (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS),\ U16_TO_U8S_LE(_epsize), _ep_interval /* 3.10.1.2 */ diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index cea876413..713bbb8d4 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -196,7 +196,7 @@ #define TU_ATTR_DEPRECATED(mess) __attribute__ ((deprecated(mess))) // warn if function with this attribute is used #define TU_ATTR_UNUSED __attribute__ ((unused)) // Function/Variable is meant to be possibly unused #define TU_ATTR_USED __attribute__ ((used)) // Function/Variable is meant to be used - #define TU_ATTR_FALLTHROUGH + #define TU_ATTR_FALLTHROUGH do {} while (0) /* fallthrough */ #define TU_ATTR_PACKED_BEGIN #define TU_ATTR_PACKED_END diff --git a/src/device/usbd.h b/src/device/usbd.h index 7bb9f916b..255e5a844 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -420,7 +420,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */ #define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN 7 #define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(_ep, _interval) \ - TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_NO_SYNC | TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval + TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_NO_SYNC | TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval // AUDIO simple descriptor (UAC2) for 1 microphone input // - 1 Input Terminal, 1 Feature Unit (Mute and Volume Control), 1 Output Terminal, 1 Clock Source @@ -467,7 +467,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000) @@ -516,7 +516,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000) @@ -564,7 +564,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\ /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\ -- cgit v1.3.1 From 9f54cc1eb725e7d77a5b275b209d8257b180d7ed Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 18 Mar 2023 11:43:47 +0700 Subject: more clean up --- src/class/usbtmc/usbtmc_device.c | 7 +++++++ src/portable/raspberrypi/rp2040/rp2040_usb.h | 4 ++-- 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index 8dbda14c5..4e320a778 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -154,7 +154,10 @@ TU_VERIFY_STATIC(USBTMCD_BUFFER_SIZE >= 32u,"USBTMC dev buffer size too small"); static bool handle_devMsgOutStart(uint8_t rhport, void *data, size_t len); static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t packetLen); +#ifndef NDEBUG tu_static uint8_t termChar; +#endif + tu_static uint8_t termCharRequested = false; #if OSAL_MUTEX_REQUIRED @@ -442,7 +445,10 @@ static bool handle_devMsgIn(void *data, size_t len) usbtmc_state.transfer_size_sent = 0u; termCharRequested = msg->bmTransferAttributes.TermCharEnabled; + +#ifndef NDEBUG termChar = msg->TermChar; +#endif if(termCharRequested) TU_VERIFY(usbtmc_state.capabilities->bmDevCapabilities.canEndBulkInOnTermChar); @@ -511,6 +517,7 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint return true; case STATE_ABORTING_BULK_OUT: + // Should be stalled by now, shouldn't have received a packet. return false; case STATE_TX_REQUESTED: diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h index 79af0204b..5d3d792cb 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.h +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h @@ -36,8 +36,8 @@ #define __tusb_irq_path_func(x) x #endif -#define usb_hw_set hw_set_alias(usb_hw) -#define usb_hw_clear hw_clear_alias(usb_hw) +#define usb_hw_set ((usb_hw_t *) hw_set_alias(usb_hw)) +#define usb_hw_clear ((usb_hw_t *) hw_clear_alias(usb_hw)) #define pico_info(...) TU_LOG(2, __VA_ARGS__) #define pico_trace(...) TU_LOG(3, __VA_ARGS__) -- cgit v1.3.1 From f9b8a0667a2cc42a6c6521c51bba695ca8e9e28f Mon Sep 17 00:00:00 2001 From: Bob Paddock Date: Mon, 16 Jan 2023 15:05:31 -0500 Subject: Add support for NXP FRDM_K32L2A4S eval board. --- hw/bsp/board_mcu.h | 2 +- hw/bsp/frdm_k32l2a4s/README.rst | 51 +++++++++++ hw/bsp/frdm_k32l2a4s/board.h | 58 ++++++++++++ hw/bsp/frdm_k32l2a4s/board.mk | 80 ++++++++++++++++ hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c | 171 +++++++++++++++++++++++++++++++++++ src/common/tusb_mcu.h | 2 +- src/portable/nxp/khci/dcd_khci.c | 9 +- src/portable/nxp/khci/hcd_khci.c | 9 +- src/tusb_option.h | 1 + 9 files changed, 375 insertions(+), 8 deletions(-) create mode 100644 hw/bsp/frdm_k32l2a4s/README.rst create mode 100644 hw/bsp/frdm_k32l2a4s/board.h create mode 100644 hw/bsp/frdm_k32l2a4s/board.mk create mode 100644 hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c (limited to 'src') diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index b34197e6c..920e7d0d9 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -47,7 +47,7 @@ #elif CFG_TUSB_MCU == OPT_MCU_LPC51UXX || CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \ CFG_TUSB_MCU == OPT_MCU_LPC55XX || CFG_TUSB_MCU == OPT_MCU_MKL25ZXX || \ - CFG_TUSB_MCU == OPT_MCU_K32L2BXX + CFG_TUSB_MCU == OPT_MCU_K32L2AXX || OPT_MCU_K32L2BXX #include "fsl_device_registers.h" #elif CFG_TUSB_MCU == OPT_MCU_NRF5X diff --git a/hw/bsp/frdm_k32l2a4s/README.rst b/hw/bsp/frdm_k32l2a4s/README.rst new file mode 100644 index 000000000..68ab409c3 --- /dev/null +++ b/hw/bsp/frdm_k32l2a4s/README.rst @@ -0,0 +1,51 @@ +Jan/13/2023 13:04 + +The FRDM-K32L2B3 Freedom development board provides a platform for +evaluation and development of the K32 L2B MCU Family. - +https://www.nxp.com/part/FRDM-K32L2B3#/ + +TinyUSB does not include the board specific drivers. Those drivers +need to be extracted from the MCUXpresso IDE and SDK. + +Install MCUXPresso version 11.6 or later and SDK 2.12 or later. Then +build the example project "frdmk32l2b_hellow_worldvirual_com". + +From the frdmk32l2b_hellow_worldvirual_com project copy these files to +this directory structure, in this directory: + +hw/mcu/nxp/mcux-sdk/devices/K32L2B31A + +CMSIS/ +config/ +drivers/ +gcc/ +fsl_device_registers.h +K32L2B31A_features.h +K32L2B31A.h + +./CMSIS: +cmsis_armcc.h cmsis_armclang_ltm.h cmsis_gcc.h cmsis_version.h mpu_armv7.h +cmsis_armclang.h cmsis_compiler.h cmsis_iccarm.h core_cm0plus.h + +./config: +clock_config.c clock_config.h system_K32L2B31A.c system_K32L2B31A.h + +./drivers: +fsl_clock.c fsl_common_arm.h fsl_gpio.c fsl_lpuart.h fsl_smc.h +fsl_clock.h fsl_common.c fsl_gpio.h fsl_port.h fsl_uart.c +fsl_common_arm.c fsl_common.h fsl_lpuart.c fsl_smc.c fsl_uart.h + +./gcc: +frdmk32l2b.ld startup_k32l2b31a.c +frdmk32l2b_library.ld frdmk32l2b_memory.ld + +The linker files have been renamed and the #include directive edited +to match. + +Then to build a test project change to the directory +examples/devices/cdc_msc and do: + +make BOARD=frdm_k32l2b + +The resulting .hex file will be found in the _build directory, copy +that will to the FRDM board to run the demo. diff --git a/hw/bsp/frdm_k32l2a4s/board.h b/hw/bsp/frdm_k32l2a4s/board.h new file mode 100644 index 000000000..14eefda17 --- /dev/null +++ b/hw/bsp/frdm_k32l2a4s/board.h @@ -0,0 +1,58 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "fsl_device_registers.h" + +// LED +// The Red LED is on PTE29. +// The Green LED is on PTC4. +// The Blue LED is on PTE31. +#define LED_PIN_CLOCK kCLOCK_PortC +#define LED_GPIO GPIOC +#define LED_PORT PORTC +#define LED_PIN 4 +#define LED_STATE_ON 0 + +// SW3 button1 +#define BUTTON_PIN_CLOCK kCLOCK_PortE +#define BUTTON_GPIO GPIOE +#define BUTTON_PORT PORTE +#define BUTTON_PIN 4 +#define BUTTON_STATE_ACTIVE 0 + +// UART +#define UART_PORT LPUART0 +#define UART_PIN_CLOCK kCLOCK_PortB +#define UART_PIN_GPIO GPIOB +#define UART_PIN_PORT PORTB +#define UART_PIN_RX 16u +#define UART_PIN_TX 17u + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/frdm_k32l2a4s/board.mk b/hw/bsp/frdm_k32l2a4s/board.mk new file mode 100644 index 000000000..e9e606fe6 --- /dev/null +++ b/hw/bsp/frdm_k32l2a4s/board.mk @@ -0,0 +1,80 @@ + +# Default to a less-verbose build. If you want all the gory compiler output, +# "VERBOSE=1" to the make command line. +ifndef VERBOSE +.SILENT: +$(info Non-Verbose Output) +else +$(info Verbose Output) +endif + +SDK_DIR = hw/mcu/nxp/mcux-sdk +MCU_DIR = $(SDK_DIR)/devices/K32L2A4S + +ifdef VERBOSE +$(info TOP='$(TOP)') +$(info ) + +$(info BSP='$(TOP)/hw/bsp/$(BOARD)') +$(info ) + +$(info TOP/SDK_DIR='$(TOP)/$(SDK_DIR)') +$(info ) + +$(info MCU_DIR='$(MCU_DIR)') +$(info ) +endif + +DEPS_SUBMODULES += $(SDK_DIR) + +CFLAGS += \ + -mthumb \ + -mabi=aapcs \ + -mcpu=cortex-m0plus \ + -DCPU_K32L2A41VLH1A \ + -DCFG_TUSB_MCU=OPT_MCU_K32L2AXX + +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual + +# All source paths should be relative to the top level. + +LD_FILE = $(MCU_DIR)/gcc/frdmk32l2a4s.ld +LDFLAGS += -L$(TOP)/$(MCU_DIR)/gcc + +# Define Recursive Depth wildcard: +rwildcard=$(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d)) + +SRC_C += \ + src/portable/nxp/khci/dcd_khci.c \ + $(MCU_DIR)/gcc/startup_k32l2a41a.c + +SRC_C += $(call rwildcard,$(TOP)/$(MCU_DIR)/config,*.c) +SRC_C += $(call rwildcard,$(TOP)/$(MCU_DIR)/drivers,*.c) + +INC += \ + $(TOP)/hw/bsp/$(BOARD) \ + $(TOP)/$(MCU_DIR)/CMSIS/ \ + $(TOP)/$(MCU_DIR) \ + $(TOP)/$(MCU_DIR)/config \ + $(TOP)/$(MCU_DIR)/drivers + +ifdef VERBOSE +$(info INC = '$(strip $(INC))') +$(info ) + +$(info SRC_C = '$(sort $(strip $(SRC_C)))') +$(info ) +endif + +# For freeRTOS port source +FREERTOS_PORT = ARM_CM0 + +# For flash-jlink target +#JLINK_DEVICE = ? + +# For flash-pyocd target +PYOCD_TARGET = K32L2A + +# flash using pyocd +flash: flash-pyocd diff --git a/hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c b/hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c new file mode 100644 index 000000000..47dd0c8ec --- /dev/null +++ b/hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c @@ -0,0 +1,171 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2018, hathach (tinyusb.org) + * Copyright (c) 2020, Koji Kitayama + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "../board.h" +#include "board.h" +#include "fsl_gpio.h" +#include "fsl_port.h" +#include "fsl_clock.h" +#include "fsl_lpuart.h" + +#include "clock_config.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB0_IRQHandler(void) +{ + tud_int_handler(0); +} + +void board_init(void) +{ + /* Enable port clocks for UART/LED/Button pins */ + CLOCK_EnableClock(UART_PIN_CLOCK); + CLOCK_EnableClock(LED_PIN_CLOCK); + CLOCK_EnableClock(BUTTON_PIN_CLOCK); + + gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; + GPIO_PinInit(LED_GPIO, LED_PIN, &led_config); + PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio); + + gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); + const port_pin_config_t BUTTON_CFG = { + kPORT_PullUp, + kPORT_FastSlewRate, + kPORT_PassiveFilterDisable, + kPORT_OpenDrainDisable, + kPORT_LowDriveStrength, + kPORT_MuxAsGpio, + kPORT_UnlockRegister + }; + PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); + + /* + Enable LPUART0 clock and configure port pins. + FIR clock is being used so the USB examples work. + */ + PCC_LPUART0 = 0U; /* Clock must be off to set PCS */ + PCC_LPUART0 = PCC_CLKCFG_PCS( 3U ); /* Select the clock. 1:OSCCLK/Bus Clock, 2:Slow IRC, 3: Fast IRC, 6: System PLL */ + PCC_LPUART0 |= PCC_CLKCFG_CGC( 1U ); /* Enable LPUART */ + + /* PORTB16 (pin 62) is configured as LPUART0_RX */ + gpio_pin_config_t const lpuart_config_rx = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(UART_PIN_GPIO, UART_PIN_RX, &lpuart_config_rx); + const port_pin_config_t UART_CFG = { + kPORT_PullUp, + kPORT_FastSlewRate, + kPORT_PassiveFilterDisable, + kPORT_OpenDrainDisable, + kPORT_LowDriveStrength, + kPORT_MuxAsGpio, + kPORT_UnlockRegister + }; + PORT_SetPinConfig(UART_PIN_PORT, UART_PIN_RX, &UART_CFG); + PORT_SetPinMux( UART_PIN_PORT, UART_PIN_RX, kPORT_MuxAlt3); + + /* PORTB17 (pin 63) is configured as LPUART0_TX */ + gpio_pin_config_t const lpuart_config_tx = { kGPIO_DigitalOutput, 0 }; + GPIO_PinInit( UART_PIN_GPIO, UART_PIN_TX, &lpuart_config_tx); + PORT_SetPinMux( UART_PIN_PORT, UART_PIN_TX, kPORT_MuxAlt3); + + BOARD_BootClockRUN(); + SystemCoreClockUpdate(); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + lpuart_config_t uart_config; + LPUART_GetDefaultConfig(&uart_config); + uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; + uart_config.enableTx = true; + uart_config.enableRx = true; + LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_ScgFircClk)); + + // USB + CLOCK_EnableUsbfs0Clock(kCLOCK_IpSrcFircAsync, 48000000U); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); +} + +int board_uart_read(uint8_t* buf, int len) +{ +#if 0 /* + Use this version if want the LED to blink during BOARD=board_test, + without having to hit a key. + */ + if( 0U != (kLPUART_RxDataRegFullFlag & LPUART_GetStatusFlags( UART_PORT )) ) + { + LPUART_ReadBlocking(UART_PORT, buf, len); + return len; + } + + return( 0 ); +#else /* Wait for 'len' characters to come in */ + + LPUART_ReadBlocking(UART_PORT, buf, len); + return len; + +#endif +} + +int board_uart_write(void const * buf, int len) +{ + LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 1d27f47af..18e40e1b1 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -85,7 +85,7 @@ #define TUP_DCD_ENDPOINT_MAX 8 #define TUP_RHPORT_HIGHSPEED 1 // Port0 HS, Port1 HS -#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2BXX) +#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2AXX, OPT_MCU_K32L2BXX) #define TUP_DCD_ENDPOINT_MAX 16 #elif TU_CHECK_MCU(OPT_MCU_MM32F327X) diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index b6daec3de..2678cdca1 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -26,9 +26,12 @@ #include "tusb_option.h" -#if CFG_TUD_ENABLED && ( \ - ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX ) \ - ) +#if CFG_TUD_ENABLED && \ + ( \ + ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || \ + ( CFG_TUSB_MCU == OPT_MCU_K32L2AXX ) || \ + ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX ) \ + ) #include "fsl_device_registers.h" #define KHCI USB0 diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index 35763f121..8ff1feff7 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -26,9 +26,12 @@ #include "tusb_option.h" -#if CFG_TUH_ENABLED && ( \ - ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX ) \ - ) +#if CFG_TUD_ENABLED && \ + ( \ + ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || \ + ( CFG_TUSB_MCU == OPT_MCU_K32L2AXX ) || \ + ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX ) \ + ) #include "fsl_device_registers.h" #define KHCI USB0 diff --git a/src/tusb_option.h b/src/tusb_option.h index c019b0ba4..5a234e357 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -119,6 +119,7 @@ // NXP Kinetis #define OPT_MCU_MKL25ZXX 1200 ///< NXP MKL25Zxx #define OPT_MCU_K32L2BXX 1201 ///< NXP K32L2Bxx +#define OPT_MCU_K32L2AXX 1202 ///< NXP K32L2Axx // Silabs #define OPT_MCU_EFM32GG 1300 ///< Silabs EFM32GG -- cgit v1.3.1 From 2d187777c0eb625ad7c63c21dd881ca7362363fc Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 18 Mar 2023 18:30:51 +0700 Subject: merge kinetis into its own family in bsp --- hw/bsp/frdm_k32l2a4s/README.rst | 51 ------ hw/bsp/frdm_k32l2a4s/board.h | 58 ------- hw/bsp/frdm_k32l2a4s/board.mk | 80 ---------- hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c | 171 -------------------- hw/bsp/frdm_k32l2b/board.h | 56 ------- hw/bsp/frdm_k32l2b/board.mk | 51 ------ hw/bsp/frdm_k32l2b/frdm_k32l2b.c | 140 ---------------- hw/bsp/frdm_kl25z/board.mk | 52 ------ hw/bsp/frdm_kl25z/frdm_kl25z.c | 176 --------------------- hw/bsp/kinetis/boards/frdm_k32l2a4s/board.h | 58 +++++++ hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk | 26 +++ .../kinetis/boards/frdm_k32l2a4s/frdm_k32l2a4s.c | 171 ++++++++++++++++++++ hw/bsp/kinetis/boards/frdm_k32l2b/board.h | 56 +++++++ hw/bsp/kinetis/boards/frdm_k32l2b/board.mk | 26 +++ hw/bsp/kinetis/boards/frdm_k32l2b/frdm_k32l2b.c | 140 ++++++++++++++++ hw/bsp/kinetis/boards/frdm_kl25z/board.mk | 31 ++++ hw/bsp/kinetis/boards/frdm_kl25z/frdm_kl25z.c | 176 +++++++++++++++++++++ hw/bsp/kinetis/family.mk | 46 ++++++ src/common/tusb_mcu.h | 2 + src/portable/nxp/khci/dcd_khci.c | 17 +- src/portable/nxp/khci/hcd_khci.c | 2 +- 21 files changed, 741 insertions(+), 845 deletions(-) delete mode 100644 hw/bsp/frdm_k32l2a4s/README.rst delete mode 100644 hw/bsp/frdm_k32l2a4s/board.h delete mode 100644 hw/bsp/frdm_k32l2a4s/board.mk delete mode 100644 hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c delete mode 100644 hw/bsp/frdm_k32l2b/board.h delete mode 100644 hw/bsp/frdm_k32l2b/board.mk delete mode 100644 hw/bsp/frdm_k32l2b/frdm_k32l2b.c delete mode 100644 hw/bsp/frdm_kl25z/board.mk delete mode 100644 hw/bsp/frdm_kl25z/frdm_kl25z.c create mode 100644 hw/bsp/kinetis/boards/frdm_k32l2a4s/board.h create mode 100644 hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk create mode 100644 hw/bsp/kinetis/boards/frdm_k32l2a4s/frdm_k32l2a4s.c create mode 100644 hw/bsp/kinetis/boards/frdm_k32l2b/board.h create mode 100644 hw/bsp/kinetis/boards/frdm_k32l2b/board.mk create mode 100644 hw/bsp/kinetis/boards/frdm_k32l2b/frdm_k32l2b.c create mode 100644 hw/bsp/kinetis/boards/frdm_kl25z/board.mk create mode 100644 hw/bsp/kinetis/boards/frdm_kl25z/frdm_kl25z.c create mode 100644 hw/bsp/kinetis/family.mk (limited to 'src') diff --git a/hw/bsp/frdm_k32l2a4s/README.rst b/hw/bsp/frdm_k32l2a4s/README.rst deleted file mode 100644 index 68ab409c3..000000000 --- a/hw/bsp/frdm_k32l2a4s/README.rst +++ /dev/null @@ -1,51 +0,0 @@ -Jan/13/2023 13:04 - -The FRDM-K32L2B3 Freedom development board provides a platform for -evaluation and development of the K32 L2B MCU Family. - -https://www.nxp.com/part/FRDM-K32L2B3#/ - -TinyUSB does not include the board specific drivers. Those drivers -need to be extracted from the MCUXpresso IDE and SDK. - -Install MCUXPresso version 11.6 or later and SDK 2.12 or later. Then -build the example project "frdmk32l2b_hellow_worldvirual_com". - -From the frdmk32l2b_hellow_worldvirual_com project copy these files to -this directory structure, in this directory: - -hw/mcu/nxp/mcux-sdk/devices/K32L2B31A - -CMSIS/ -config/ -drivers/ -gcc/ -fsl_device_registers.h -K32L2B31A_features.h -K32L2B31A.h - -./CMSIS: -cmsis_armcc.h cmsis_armclang_ltm.h cmsis_gcc.h cmsis_version.h mpu_armv7.h -cmsis_armclang.h cmsis_compiler.h cmsis_iccarm.h core_cm0plus.h - -./config: -clock_config.c clock_config.h system_K32L2B31A.c system_K32L2B31A.h - -./drivers: -fsl_clock.c fsl_common_arm.h fsl_gpio.c fsl_lpuart.h fsl_smc.h -fsl_clock.h fsl_common.c fsl_gpio.h fsl_port.h fsl_uart.c -fsl_common_arm.c fsl_common.h fsl_lpuart.c fsl_smc.c fsl_uart.h - -./gcc: -frdmk32l2b.ld startup_k32l2b31a.c -frdmk32l2b_library.ld frdmk32l2b_memory.ld - -The linker files have been renamed and the #include directive edited -to match. - -Then to build a test project change to the directory -examples/devices/cdc_msc and do: - -make BOARD=frdm_k32l2b - -The resulting .hex file will be found in the _build directory, copy -that will to the FRDM board to run the demo. diff --git a/hw/bsp/frdm_k32l2a4s/board.h b/hw/bsp/frdm_k32l2a4s/board.h deleted file mode 100644 index 14eefda17..000000000 --- a/hw/bsp/frdm_k32l2a4s/board.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "fsl_device_registers.h" - -// LED -// The Red LED is on PTE29. -// The Green LED is on PTC4. -// The Blue LED is on PTE31. -#define LED_PIN_CLOCK kCLOCK_PortC -#define LED_GPIO GPIOC -#define LED_PORT PORTC -#define LED_PIN 4 -#define LED_STATE_ON 0 - -// SW3 button1 -#define BUTTON_PIN_CLOCK kCLOCK_PortE -#define BUTTON_GPIO GPIOE -#define BUTTON_PORT PORTE -#define BUTTON_PIN 4 -#define BUTTON_STATE_ACTIVE 0 - -// UART -#define UART_PORT LPUART0 -#define UART_PIN_CLOCK kCLOCK_PortB -#define UART_PIN_GPIO GPIOB -#define UART_PIN_PORT PORTB -#define UART_PIN_RX 16u -#define UART_PIN_TX 17u - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/frdm_k32l2a4s/board.mk b/hw/bsp/frdm_k32l2a4s/board.mk deleted file mode 100644 index e9e606fe6..000000000 --- a/hw/bsp/frdm_k32l2a4s/board.mk +++ /dev/null @@ -1,80 +0,0 @@ - -# Default to a less-verbose build. If you want all the gory compiler output, -# "VERBOSE=1" to the make command line. -ifndef VERBOSE -.SILENT: -$(info Non-Verbose Output) -else -$(info Verbose Output) -endif - -SDK_DIR = hw/mcu/nxp/mcux-sdk -MCU_DIR = $(SDK_DIR)/devices/K32L2A4S - -ifdef VERBOSE -$(info TOP='$(TOP)') -$(info ) - -$(info BSP='$(TOP)/hw/bsp/$(BOARD)') -$(info ) - -$(info TOP/SDK_DIR='$(TOP)/$(SDK_DIR)') -$(info ) - -$(info MCU_DIR='$(MCU_DIR)') -$(info ) -endif - -DEPS_SUBMODULES += $(SDK_DIR) - -CFLAGS += \ - -mthumb \ - -mabi=aapcs \ - -mcpu=cortex-m0plus \ - -DCPU_K32L2A41VLH1A \ - -DCFG_TUSB_MCU=OPT_MCU_K32L2AXX - -# mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual - -# All source paths should be relative to the top level. - -LD_FILE = $(MCU_DIR)/gcc/frdmk32l2a4s.ld -LDFLAGS += -L$(TOP)/$(MCU_DIR)/gcc - -# Define Recursive Depth wildcard: -rwildcard=$(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d)) - -SRC_C += \ - src/portable/nxp/khci/dcd_khci.c \ - $(MCU_DIR)/gcc/startup_k32l2a41a.c - -SRC_C += $(call rwildcard,$(TOP)/$(MCU_DIR)/config,*.c) -SRC_C += $(call rwildcard,$(TOP)/$(MCU_DIR)/drivers,*.c) - -INC += \ - $(TOP)/hw/bsp/$(BOARD) \ - $(TOP)/$(MCU_DIR)/CMSIS/ \ - $(TOP)/$(MCU_DIR) \ - $(TOP)/$(MCU_DIR)/config \ - $(TOP)/$(MCU_DIR)/drivers - -ifdef VERBOSE -$(info INC = '$(strip $(INC))') -$(info ) - -$(info SRC_C = '$(sort $(strip $(SRC_C)))') -$(info ) -endif - -# For freeRTOS port source -FREERTOS_PORT = ARM_CM0 - -# For flash-jlink target -#JLINK_DEVICE = ? - -# For flash-pyocd target -PYOCD_TARGET = K32L2A - -# flash using pyocd -flash: flash-pyocd diff --git a/hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c b/hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c deleted file mode 100644 index 47dd0c8ec..000000000 --- a/hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2018, hathach (tinyusb.org) - * Copyright (c) 2020, Koji Kitayama - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "../board.h" -#include "board.h" -#include "fsl_gpio.h" -#include "fsl_port.h" -#include "fsl_clock.h" -#include "fsl_lpuart.h" - -#include "clock_config.h" - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB0_IRQHandler(void) -{ - tud_int_handler(0); -} - -void board_init(void) -{ - /* Enable port clocks for UART/LED/Button pins */ - CLOCK_EnableClock(UART_PIN_CLOCK); - CLOCK_EnableClock(LED_PIN_CLOCK); - CLOCK_EnableClock(BUTTON_PIN_CLOCK); - - gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; - GPIO_PinInit(LED_GPIO, LED_PIN, &led_config); - PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio); - - gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; - GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); - const port_pin_config_t BUTTON_CFG = { - kPORT_PullUp, - kPORT_FastSlewRate, - kPORT_PassiveFilterDisable, - kPORT_OpenDrainDisable, - kPORT_LowDriveStrength, - kPORT_MuxAsGpio, - kPORT_UnlockRegister - }; - PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); - - /* - Enable LPUART0 clock and configure port pins. - FIR clock is being used so the USB examples work. - */ - PCC_LPUART0 = 0U; /* Clock must be off to set PCS */ - PCC_LPUART0 = PCC_CLKCFG_PCS( 3U ); /* Select the clock. 1:OSCCLK/Bus Clock, 2:Slow IRC, 3: Fast IRC, 6: System PLL */ - PCC_LPUART0 |= PCC_CLKCFG_CGC( 1U ); /* Enable LPUART */ - - /* PORTB16 (pin 62) is configured as LPUART0_RX */ - gpio_pin_config_t const lpuart_config_rx = { kGPIO_DigitalInput, 0 }; - GPIO_PinInit(UART_PIN_GPIO, UART_PIN_RX, &lpuart_config_rx); - const port_pin_config_t UART_CFG = { - kPORT_PullUp, - kPORT_FastSlewRate, - kPORT_PassiveFilterDisable, - kPORT_OpenDrainDisable, - kPORT_LowDriveStrength, - kPORT_MuxAsGpio, - kPORT_UnlockRegister - }; - PORT_SetPinConfig(UART_PIN_PORT, UART_PIN_RX, &UART_CFG); - PORT_SetPinMux( UART_PIN_PORT, UART_PIN_RX, kPORT_MuxAlt3); - - /* PORTB17 (pin 63) is configured as LPUART0_TX */ - gpio_pin_config_t const lpuart_config_tx = { kGPIO_DigitalOutput, 0 }; - GPIO_PinInit( UART_PIN_GPIO, UART_PIN_TX, &lpuart_config_tx); - PORT_SetPinMux( UART_PIN_PORT, UART_PIN_TX, kPORT_MuxAlt3); - - BOARD_BootClockRUN(); - SystemCoreClockUpdate(); - -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); -#endif - - lpuart_config_t uart_config; - LPUART_GetDefaultConfig(&uart_config); - uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; - uart_config.enableTx = true; - uart_config.enableRx = true; - LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_ScgFircClk)); - - // USB - CLOCK_EnableUsbfs0Clock(kCLOCK_IpSrcFircAsync, 48000000U); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); -} - -uint32_t board_button_read(void) -{ - return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); -} - -int board_uart_read(uint8_t* buf, int len) -{ -#if 0 /* - Use this version if want the LED to blink during BOARD=board_test, - without having to hit a key. - */ - if( 0U != (kLPUART_RxDataRegFullFlag & LPUART_GetStatusFlags( UART_PORT )) ) - { - LPUART_ReadBlocking(UART_PORT, buf, len); - return len; - } - - return( 0 ); -#else /* Wait for 'len' characters to come in */ - - LPUART_ReadBlocking(UART_PORT, buf, len); - return len; - -#endif -} - -int board_uart_write(void const * buf, int len) -{ - LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler(void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#endif diff --git a/hw/bsp/frdm_k32l2b/board.h b/hw/bsp/frdm_k32l2b/board.h deleted file mode 100644 index 8d21fdcd4..000000000 --- a/hw/bsp/frdm_k32l2b/board.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "fsl_device_registers.h" - -// LED -#define LED_PIN_CLOCK kCLOCK_PortD -#define LED_GPIO GPIOD -#define LED_PORT PORTD -#define LED_PIN 5 -#define LED_STATE_ON 0 - -// SW3 button1 -#define BUTTON_PIN_CLOCK kCLOCK_PortC -#define BUTTON_GPIO GPIOC -#define BUTTON_PORT PORTC -#define BUTTON_PIN 3 -#define BUTTON_STATE_ACTIVE 0 - -// UART -#define UART_PORT LPUART0 -#define UART_PIN_CLOCK kCLOCK_PortA -#define UART_PIN_PORT PORTA -#define UART_PIN_RX 1u -#define UART_PIN_TX 2u -#define SOPT5_LPUART0RXSRC_LPUART_RX 0x00u /*!<@brief LPUART0 Receive Data Source Select: LPUART_RX pin */ -#define SOPT5_LPUART0TXSRC_LPUART_TX 0x00u /*!<@brief LPUART0 Transmit Data Source Select: LPUART0_TX pin */ - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/frdm_k32l2b/board.mk b/hw/bsp/frdm_k32l2b/board.mk deleted file mode 100644 index feb0a25f4..000000000 --- a/hw/bsp/frdm_k32l2b/board.mk +++ /dev/null @@ -1,51 +0,0 @@ -SDK_DIR = hw/mcu/nxp/mcux-sdk -DEPS_SUBMODULES += $(SDK_DIR) - -CFLAGS += \ - -mthumb \ - -mabi=aapcs \ - -mcpu=cortex-m0plus \ - -DCPU_K32L2B31VLH0A \ - -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX - -# mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls - -MCU_DIR = $(SDK_DIR)/devices/K32L2B31A - -# All source paths should be relative to the top level. -LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld - -SRC_C += \ - src/portable/nxp/khci/dcd_khci.c \ - $(MCU_DIR)/system_K32L2B31A.c \ - $(MCU_DIR)/project_template/clock_config.c \ - $(MCU_DIR)/drivers/fsl_clock.c \ - $(SDK_DIR)/drivers/gpio/fsl_gpio.c \ - $(SDK_DIR)/drivers/lpuart/fsl_lpuart.c - -INC += \ - $(TOP)/hw/bsp/$(BOARD) \ - $(TOP)/$(SDK_DIR)/CMSIS/Include \ - $(TOP)/$(SDK_DIR)/drivers/smc \ - $(TOP)/$(SDK_DIR)/drivers/common \ - $(TOP)/$(SDK_DIR)/drivers/gpio \ - $(TOP)/$(SDK_DIR)/drivers/port \ - $(TOP)/$(SDK_DIR)/drivers/lpuart \ - $(TOP)/$(MCU_DIR) \ - $(TOP)/$(MCU_DIR)/drivers \ - $(TOP)/$(MCU_DIR)/project_template \ - -SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S - -# For freeRTOS port source -FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 - -# For flash-jlink target -JLINK_DEVICE = MKL25Z128xxx4 - -# For flash-pyocd target -PYOCD_TARGET = K32L2B - -# flash using pyocd -flash: flash-pyocd diff --git a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/frdm_k32l2b/frdm_k32l2b.c deleted file mode 100644 index 8d2b39500..000000000 --- a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2018, hathach (tinyusb.org) - * Copyright (c) 2020, Koji Kitayama - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "../board.h" -#include "board.h" -#include "fsl_gpio.h" -#include "fsl_port.h" -#include "fsl_clock.h" -#include "fsl_lpuart.h" - -#include "clock_config.h" - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB0_IRQHandler(void) -{ - tud_int_handler(0); -} - -void board_init(void) -{ - /* Enable port clocks for UART/LED/Button pins */ - CLOCK_EnableClock(UART_PIN_CLOCK); - CLOCK_EnableClock(LED_PIN_CLOCK); - CLOCK_EnableClock(BUTTON_PIN_CLOCK); - - gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; - GPIO_PinInit(LED_GPIO, LED_PIN, &led_config); - PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio); - - gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; - GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); - const port_pin_config_t BUTTON_CFG = { - kPORT_PullUp, - kPORT_FastSlewRate, - kPORT_PassiveFilterDisable, - kPORT_LowDriveStrength, - kPORT_MuxAsGpio - }; - PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); - - /* PORTA1 (pin 23) is configured as LPUART0_RX */ - PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2); - /* PORTA2 (pin 24) is configured as LPUART0_TX */ - PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2); - - SIM->SOPT5 = ((SIM->SOPT5 & - /* Mask bits to zero which are setting */ - (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK))) - /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */ - | SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX) - /* LPUART0 Receive Data Source Select: LPUART_RX pin. */ - | SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX)); - - BOARD_BootClockRUN(); - SystemCoreClockUpdate(); - CLOCK_SetLpuart0Clock(1); - -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); -#endif - - lpuart_config_t uart_config; - LPUART_GetDefaultConfig(&uart_config); - uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; - uart_config.enableTx = true; - uart_config.enableRx = true; - LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk)); - - // USB - CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); -} - -uint32_t board_button_read(void) -{ - return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); -} - -int board_uart_read(uint8_t* buf, int len) -{ - LPUART_ReadBlocking(UART_PORT, buf, len); - return len; -} - -int board_uart_write(void const * buf, int len) -{ - LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler(void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#endif diff --git a/hw/bsp/frdm_kl25z/board.mk b/hw/bsp/frdm_kl25z/board.mk deleted file mode 100644 index fd616f7ed..000000000 --- a/hw/bsp/frdm_kl25z/board.mk +++ /dev/null @@ -1,52 +0,0 @@ -SDK_DIR = hw/mcu/nxp/nxp_sdk -DEPS_SUBMODULES += $(SDK_DIR) - -CFLAGS += \ - -mthumb \ - -mabi=aapcs \ - -mcpu=cortex-m0plus \ - -DCPU_MKL25Z128VLK4 \ - -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX \ - -DCFG_EXAMPLE_VIDEO_READONLY - -LDFLAGS += \ - -Wl,--defsym,__stack_size__=0x400 \ - -Wl,--defsym,__heap_size__=0 - -# mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=format -Wno-error=redundant-decls - -MCU_DIR = $(SDK_DIR)/devices/MKL25Z4 - -# All source paths should be relative to the top level. -LD_FILE = $(MCU_DIR)/gcc/MKL25Z128xxx4_flash.ld - -SRC_C += \ - src/portable/nxp/khci/dcd_khci.c \ - src/portable/nxp/khci/hcd_khci.c \ - $(MCU_DIR)/system_MKL25Z4.c \ - $(MCU_DIR)/project_template/clock_config.c \ - $(MCU_DIR)/drivers/fsl_clock.c \ - $(MCU_DIR)/drivers/fsl_gpio.c \ - $(MCU_DIR)/drivers/fsl_lpsci.c - -INC += \ - $(TOP)/hw/bsp/$(BOARD) \ - $(TOP)/$(SDK_DIR)/CMSIS/Include \ - $(TOP)/$(MCU_DIR) \ - $(TOP)/$(MCU_DIR)/drivers \ - $(TOP)/$(MCU_DIR)/project_template \ - -SRC_S += $(MCU_DIR)/gcc/startup_MKL25Z4.S - -# For freeRTOS port source -FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 - -# For flash-jlink target -JLINK_DEVICE = MKL25Z128xxx4 - -# For flash-pyocd target -PYOCD_TARGET = mkl25zl128 - -# flash using pyocd -flash: flash-pyocd diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/frdm_kl25z/frdm_kl25z.c deleted file mode 100644 index 46f85f6a5..000000000 --- a/hw/bsp/frdm_kl25z/frdm_kl25z.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2018, hathach (tinyusb.org) - * Copyright (c) 2020, Koji Kitayama - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "../board.h" -#include "fsl_device_registers.h" -#include "fsl_gpio.h" -#include "fsl_port.h" -#include "fsl_clock.h" -#include "fsl_lpsci.h" - -#include "clock_config.h" - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB0_IRQHandler(void) -{ -#if CFG_TUH_ENABLED - tuh_int_handler(0); -#endif -#if CFG_TUD_ENABLED - tud_int_handler(0); -#endif -} - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM DECLARATION -//--------------------------------------------------------------------+ -// LED -#define LED_PINMUX IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 -#define LED_PORT GPIOB -#define LED_PIN_CLOCK kCLOCK_PortB -#define LED_PIN_PORT PORTB -#define LED_PIN 19U -#define LED_PIN_FUNCTION kPORT_MuxAsGpio -#define LED_STATE_ON 0 - -// Button -#define BUTTON_PORT GPIOC -#define BUTTON_PIN_CLOCK kCLOCK_PortC -#define BUTTON_PIN_PORT PORTC -#define BUTTON_PIN 9U -#define BUTTON_PIN_FUNCTION kPORT_MuxAsGpio -#define BUTTON_STATE_ACTIVE 0 - -// UART -#define UART_PORT UART0 -#define UART_PIN_CLOCK kCLOCK_PortA -#define UART_PIN_PORT PORTA -#define UART_PIN_RX 1u -#define UART_PIN_TX 2u -#define UART_PIN_FUNCTION kPORT_MuxAlt2 -#define SOPT5_UART0RXSRC_UART_RX 0x00u /*!< UART0 receive data source select: UART0_RX pin */ -#define SOPT5_UART0TXSRC_UART_TX 0x00u /*!< UART0 transmit data source select: UART0_TX pin */ - -const uint8_t dcd_data[] = { 0x00 }; - -void board_init(void) -{ - BOARD_BootClockRUN(); - SystemCoreClockUpdate(); - -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); -#endif - - // LED - CLOCK_EnableClock(LED_PIN_CLOCK); - PORT_SetPinMux(LED_PIN_PORT, LED_PIN, LED_PIN_FUNCTION); - gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; - GPIO_PinInit(LED_PORT, LED_PIN, &led_config); - board_led_write(false); - -#if defined(BUTTON_PORT) && defined(BUTTON_PIN) - // Button - CLOCK_EnableClock(BUTTON_PIN_CLOCK); - port_pin_config_t button_port = { - .pullSelect = kPORT_PullUp, - .mux = BUTTON_PIN_FUNCTION, - }; - PORT_SetPinConfig(BUTTON_PIN_PORT, BUTTON_PIN, &button_port); - gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; - GPIO_PinInit(BUTTON_PORT, BUTTON_PIN, &button_config); -#endif - - // UART - CLOCK_EnableClock(UART_PIN_CLOCK); - PORT_SetPinMux(UART_PIN_PORT, UART_PIN_RX, UART_PIN_FUNCTION); - PORT_SetPinMux(UART_PIN_PORT, UART_PIN_TX, UART_PIN_FUNCTION); - SIM->SOPT5 = ((SIM->SOPT5 & - (~(SIM_SOPT5_UART0TXSRC_MASK | SIM_SOPT5_UART0RXSRC_MASK))) - | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX) - | SIM_SOPT5_UART0RXSRC(SOPT5_UART0RXSRC_UART_RX) - ); - - lpsci_config_t uart_config; - CLOCK_SetLpsci0Clock(1); - LPSCI_GetDefaultConfig(&uart_config); - uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; - uart_config.enableTx = true; - uart_config.enableRx = true; - LPSCI_Init(UART_PORT, &uart_config, CLOCK_GetPllFllSelClkFreq()); - - // USB - CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk)); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - GPIO_WritePinOutput(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); -} - -uint32_t board_button_read(void) -{ -#if defined(BUTTON_PORT) && defined(BUTTON_PIN) - return BUTTON_STATE_ACTIVE == GPIO_ReadPinInput(BUTTON_PORT, BUTTON_PIN); -#endif - return 0; -} - -int board_uart_read(uint8_t* buf, int len) -{ - LPSCI_ReadBlocking(UART_PORT, buf, len); - return len; -} - -int board_uart_write(void const * buf, int len) -{ - LPSCI_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler(void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#endif diff --git a/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.h b/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.h new file mode 100644 index 000000000..b1f38c997 --- /dev/null +++ b/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.h @@ -0,0 +1,58 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "fsl_device_registers.h" + +// LED +// The Red LED is on PTE29. +// The Green LED is on PTC4. +// The Blue LED is on PTE31. +#define LED_PIN_CLOCK kCLOCK_PortC +#define LED_GPIO GPIOC +#define LED_PORT PORTC +#define LED_PIN 4 +#define LED_STATE_ON 0 + +// SW3 button1 +#define BUTTON_PIN_CLOCK kCLOCK_PortE +#define BUTTON_GPIO GPIOE +#define BUTTON_PORT PORTE +#define BUTTON_PIN 4 +#define BUTTON_STATE_ACTIVE 0 + +// UART +#define UART_PORT LPUART0 +#define UART_PIN_CLOCK kCLOCK_PortB +#define UART_PIN_GPIO GPIOB +#define UART_PIN_PORT PORTB +#define UART_PIN_RX 16u +#define UART_PIN_TX 17u + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk new file mode 100644 index 000000000..723fb3893 --- /dev/null +++ b/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk @@ -0,0 +1,26 @@ +SDK_DIR = hw/mcu/nxp/mcux-sdk +MCU = K32L2A41A +MCU_DIR = $(SDK_DIR)/devices/$(MCU) + +CFLAGS += \ + -mcpu=cortex-m0plus \ + -DCPU_K32L2A41VLH1A \ + -DCFG_TUSB_MCU=OPT_MCU_K32L2AXX + +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual + +# All source paths should be relative to the top level. +LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld + +# For freeRTOS port source +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 + +# For flash-jlink target +JLINK_DEVICE = K32L2A41xxxxA + +# For flash-pyocd target +PYOCD_TARGET = K32L2A + +# flash using pyocd +flash: flash-pyocd diff --git a/hw/bsp/kinetis/boards/frdm_k32l2a4s/frdm_k32l2a4s.c b/hw/bsp/kinetis/boards/frdm_k32l2a4s/frdm_k32l2a4s.c new file mode 100644 index 000000000..80830163b --- /dev/null +++ b/hw/bsp/kinetis/boards/frdm_k32l2a4s/frdm_k32l2a4s.c @@ -0,0 +1,171 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2018, hathach (tinyusb.org) + * Copyright (c) 2020, Koji Kitayama + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "bsp/board.h" +#include "board.h" +#include "fsl_gpio.h" +#include "fsl_port.h" +#include "fsl_clock.h" +#include "fsl_lpuart.h" + +#include "clock_config.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB0_IRQHandler(void) +{ + tud_int_handler(0); +} + +void board_init(void) +{ + /* Enable port clocks for UART/LED/Button pins */ + CLOCK_EnableClock(UART_PIN_CLOCK); + CLOCK_EnableClock(LED_PIN_CLOCK); + CLOCK_EnableClock(BUTTON_PIN_CLOCK); + + gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; + GPIO_PinInit(LED_GPIO, LED_PIN, &led_config); + PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio); + + gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); + const port_pin_config_t BUTTON_CFG = { + kPORT_PullUp, + kPORT_FastSlewRate, + kPORT_PassiveFilterDisable, + kPORT_OpenDrainDisable, + kPORT_LowDriveStrength, + kPORT_MuxAsGpio, + kPORT_UnlockRegister + }; + PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); + + /* + Enable LPUART0 clock and configure port pins. + FIR clock is being used so the USB examples work. + */ + PCC_LPUART0 = 0U; /* Clock must be off to set PCS */ + PCC_LPUART0 = PCC_CLKCFG_PCS( 3U ); /* Select the clock. 1:OSCCLK/Bus Clock, 2:Slow IRC, 3: Fast IRC, 6: System PLL */ + PCC_LPUART0 |= PCC_CLKCFG_CGC( 1U ); /* Enable LPUART */ + + /* PORTB16 (pin 62) is configured as LPUART0_RX */ + gpio_pin_config_t const lpuart_config_rx = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(UART_PIN_GPIO, UART_PIN_RX, &lpuart_config_rx); + const port_pin_config_t UART_CFG = { + kPORT_PullUp, + kPORT_FastSlewRate, + kPORT_PassiveFilterDisable, + kPORT_OpenDrainDisable, + kPORT_LowDriveStrength, + kPORT_MuxAsGpio, + kPORT_UnlockRegister + }; + PORT_SetPinConfig(UART_PIN_PORT, UART_PIN_RX, &UART_CFG); + PORT_SetPinMux( UART_PIN_PORT, UART_PIN_RX, kPORT_MuxAlt3); + + /* PORTB17 (pin 63) is configured as LPUART0_TX */ + gpio_pin_config_t const lpuart_config_tx = { kGPIO_DigitalOutput, 0 }; + GPIO_PinInit( UART_PIN_GPIO, UART_PIN_TX, &lpuart_config_tx); + PORT_SetPinMux( UART_PIN_PORT, UART_PIN_TX, kPORT_MuxAlt3); + + BOARD_BootClockRUN(); + SystemCoreClockUpdate(); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + lpuart_config_t uart_config; + LPUART_GetDefaultConfig(&uart_config); + uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; + uart_config.enableTx = true; + uart_config.enableRx = true; + LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_ScgFircClk)); + + // USB + CLOCK_EnableUsbfs0Clock(kCLOCK_IpSrcFircAsync, 48000000U); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); +} + +int board_uart_read(uint8_t* buf, int len) +{ +#if 0 /* + Use this version if want the LED to blink during BOARD=board_test, + without having to hit a key. + */ + if( 0U != (kLPUART_RxDataRegFullFlag & LPUART_GetStatusFlags( UART_PORT )) ) + { + LPUART_ReadBlocking(UART_PORT, buf, len); + return len; + } + + return( 0 ); +#else /* Wait for 'len' characters to come in */ + + LPUART_ReadBlocking(UART_PORT, buf, len); + return len; + +#endif +} + +int board_uart_write(void const * buf, int len) +{ + LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif diff --git a/hw/bsp/kinetis/boards/frdm_k32l2b/board.h b/hw/bsp/kinetis/boards/frdm_k32l2b/board.h new file mode 100644 index 000000000..8d21fdcd4 --- /dev/null +++ b/hw/bsp/kinetis/boards/frdm_k32l2b/board.h @@ -0,0 +1,56 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "fsl_device_registers.h" + +// LED +#define LED_PIN_CLOCK kCLOCK_PortD +#define LED_GPIO GPIOD +#define LED_PORT PORTD +#define LED_PIN 5 +#define LED_STATE_ON 0 + +// SW3 button1 +#define BUTTON_PIN_CLOCK kCLOCK_PortC +#define BUTTON_GPIO GPIOC +#define BUTTON_PORT PORTC +#define BUTTON_PIN 3 +#define BUTTON_STATE_ACTIVE 0 + +// UART +#define UART_PORT LPUART0 +#define UART_PIN_CLOCK kCLOCK_PortA +#define UART_PIN_PORT PORTA +#define UART_PIN_RX 1u +#define UART_PIN_TX 2u +#define SOPT5_LPUART0RXSRC_LPUART_RX 0x00u /*!<@brief LPUART0 Receive Data Source Select: LPUART_RX pin */ +#define SOPT5_LPUART0TXSRC_LPUART_TX 0x00u /*!<@brief LPUART0 Transmit Data Source Select: LPUART0_TX pin */ + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/kinetis/boards/frdm_k32l2b/board.mk b/hw/bsp/kinetis/boards/frdm_k32l2b/board.mk new file mode 100644 index 000000000..66d408c67 --- /dev/null +++ b/hw/bsp/kinetis/boards/frdm_k32l2b/board.mk @@ -0,0 +1,26 @@ +SDK_DIR = hw/mcu/nxp/mcux-sdk +MCU = K32L2B31A +MCU_DIR = $(SDK_DIR)/devices/$(MCU) + +CFLAGS += \ + -mcpu=cortex-m0plus \ + -DCPU_K32L2B31VLH0A \ + -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX + +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls + +# All source paths should be relative to the top level. +LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld + +# For freeRTOS port source +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 + +# For flash-jlink target +JLINK_DEVICE = K32L2B31xxxxA + +# For flash-pyocd target +PYOCD_TARGET = K32L2B + +# flash using pyocd +flash: flash-pyocd diff --git a/hw/bsp/kinetis/boards/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/kinetis/boards/frdm_k32l2b/frdm_k32l2b.c new file mode 100644 index 000000000..1566b4e2e --- /dev/null +++ b/hw/bsp/kinetis/boards/frdm_k32l2b/frdm_k32l2b.c @@ -0,0 +1,140 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2018, hathach (tinyusb.org) + * Copyright (c) 2020, Koji Kitayama + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "bsp/board.h" +#include "board.h" +#include "fsl_gpio.h" +#include "fsl_port.h" +#include "fsl_clock.h" +#include "fsl_lpuart.h" + +#include "clock_config.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB0_IRQHandler(void) +{ + tud_int_handler(0); +} + +void board_init(void) +{ + /* Enable port clocks for UART/LED/Button pins */ + CLOCK_EnableClock(UART_PIN_CLOCK); + CLOCK_EnableClock(LED_PIN_CLOCK); + CLOCK_EnableClock(BUTTON_PIN_CLOCK); + + gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; + GPIO_PinInit(LED_GPIO, LED_PIN, &led_config); + PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio); + + gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); + const port_pin_config_t BUTTON_CFG = { + kPORT_PullUp, + kPORT_FastSlewRate, + kPORT_PassiveFilterDisable, + kPORT_LowDriveStrength, + kPORT_MuxAsGpio + }; + PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); + + /* PORTA1 (pin 23) is configured as LPUART0_RX */ + PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2); + /* PORTA2 (pin 24) is configured as LPUART0_TX */ + PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2); + + SIM->SOPT5 = ((SIM->SOPT5 & + /* Mask bits to zero which are setting */ + (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK))) + /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */ + | SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX) + /* LPUART0 Receive Data Source Select: LPUART_RX pin. */ + | SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX)); + + BOARD_BootClockRUN(); + SystemCoreClockUpdate(); + CLOCK_SetLpuart0Clock(1); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + lpuart_config_t uart_config; + LPUART_GetDefaultConfig(&uart_config); + uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; + uart_config.enableTx = true; + uart_config.enableRx = true; + LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk)); + + // USB + CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); +} + +int board_uart_read(uint8_t* buf, int len) +{ + LPUART_ReadBlocking(UART_PORT, buf, len); + return len; +} + +int board_uart_write(void const * buf, int len) +{ + LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif diff --git a/hw/bsp/kinetis/boards/frdm_kl25z/board.mk b/hw/bsp/kinetis/boards/frdm_kl25z/board.mk new file mode 100644 index 000000000..5ce6cd51e --- /dev/null +++ b/hw/bsp/kinetis/boards/frdm_kl25z/board.mk @@ -0,0 +1,31 @@ +SDK_DIR = hw/mcu/nxp/nxp_sdk +MCU = MKL25Z4 +MCU_DIR = $(SDK_DIR)/devices/$(MCU) + +CFLAGS += \ + -mcpu=cortex-m0plus \ + -DCPU_MKL25Z128VLK4 \ + -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX \ + -DCFG_EXAMPLE_VIDEO_READONLY + +LDFLAGS += \ + -Wl,--defsym,__stack_size__=0x400 \ + -Wl,--defsym,__heap_size__=0 + +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter -Wno-error=format -Wno-error=redundant-decls + +# All source paths should be relative to the top level. +LD_FILE = $(MCU_DIR)/gcc/MKL25Z128xxx4_flash.ld + +# For freeRTOS port source +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 + +# For flash-jlink target +JLINK_DEVICE = MKL25Z128xxx4 + +# For flash-pyocd target +PYOCD_TARGET = mkl25zl128 + +# flash using pyocd +flash: flash-jlink diff --git a/hw/bsp/kinetis/boards/frdm_kl25z/frdm_kl25z.c b/hw/bsp/kinetis/boards/frdm_kl25z/frdm_kl25z.c new file mode 100644 index 000000000..46f85f6a5 --- /dev/null +++ b/hw/bsp/kinetis/boards/frdm_kl25z/frdm_kl25z.c @@ -0,0 +1,176 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2018, hathach (tinyusb.org) + * Copyright (c) 2020, Koji Kitayama + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "../board.h" +#include "fsl_device_registers.h" +#include "fsl_gpio.h" +#include "fsl_port.h" +#include "fsl_clock.h" +#include "fsl_lpsci.h" + +#include "clock_config.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB0_IRQHandler(void) +{ +#if CFG_TUH_ENABLED + tuh_int_handler(0); +#endif +#if CFG_TUD_ENABLED + tud_int_handler(0); +#endif +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ +// LED +#define LED_PINMUX IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 +#define LED_PORT GPIOB +#define LED_PIN_CLOCK kCLOCK_PortB +#define LED_PIN_PORT PORTB +#define LED_PIN 19U +#define LED_PIN_FUNCTION kPORT_MuxAsGpio +#define LED_STATE_ON 0 + +// Button +#define BUTTON_PORT GPIOC +#define BUTTON_PIN_CLOCK kCLOCK_PortC +#define BUTTON_PIN_PORT PORTC +#define BUTTON_PIN 9U +#define BUTTON_PIN_FUNCTION kPORT_MuxAsGpio +#define BUTTON_STATE_ACTIVE 0 + +// UART +#define UART_PORT UART0 +#define UART_PIN_CLOCK kCLOCK_PortA +#define UART_PIN_PORT PORTA +#define UART_PIN_RX 1u +#define UART_PIN_TX 2u +#define UART_PIN_FUNCTION kPORT_MuxAlt2 +#define SOPT5_UART0RXSRC_UART_RX 0x00u /*!< UART0 receive data source select: UART0_RX pin */ +#define SOPT5_UART0TXSRC_UART_TX 0x00u /*!< UART0 transmit data source select: UART0_TX pin */ + +const uint8_t dcd_data[] = { 0x00 }; + +void board_init(void) +{ + BOARD_BootClockRUN(); + SystemCoreClockUpdate(); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + // LED + CLOCK_EnableClock(LED_PIN_CLOCK); + PORT_SetPinMux(LED_PIN_PORT, LED_PIN, LED_PIN_FUNCTION); + gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; + GPIO_PinInit(LED_PORT, LED_PIN, &led_config); + board_led_write(false); + +#if defined(BUTTON_PORT) && defined(BUTTON_PIN) + // Button + CLOCK_EnableClock(BUTTON_PIN_CLOCK); + port_pin_config_t button_port = { + .pullSelect = kPORT_PullUp, + .mux = BUTTON_PIN_FUNCTION, + }; + PORT_SetPinConfig(BUTTON_PIN_PORT, BUTTON_PIN, &button_port); + gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(BUTTON_PORT, BUTTON_PIN, &button_config); +#endif + + // UART + CLOCK_EnableClock(UART_PIN_CLOCK); + PORT_SetPinMux(UART_PIN_PORT, UART_PIN_RX, UART_PIN_FUNCTION); + PORT_SetPinMux(UART_PIN_PORT, UART_PIN_TX, UART_PIN_FUNCTION); + SIM->SOPT5 = ((SIM->SOPT5 & + (~(SIM_SOPT5_UART0TXSRC_MASK | SIM_SOPT5_UART0RXSRC_MASK))) + | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX) + | SIM_SOPT5_UART0RXSRC(SOPT5_UART0RXSRC_UART_RX) + ); + + lpsci_config_t uart_config; + CLOCK_SetLpsci0Clock(1); + LPSCI_GetDefaultConfig(&uart_config); + uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; + uart_config.enableTx = true; + uart_config.enableRx = true; + LPSCI_Init(UART_PORT, &uart_config, CLOCK_GetPllFllSelClkFreq()); + + // USB + CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk)); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + GPIO_WritePinOutput(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ +#if defined(BUTTON_PORT) && defined(BUTTON_PIN) + return BUTTON_STATE_ACTIVE == GPIO_ReadPinInput(BUTTON_PORT, BUTTON_PIN); +#endif + return 0; +} + +int board_uart_read(uint8_t* buf, int len) +{ + LPSCI_ReadBlocking(UART_PORT, buf, len); + return len; +} + +int board_uart_write(void const * buf, int len) +{ + LPSCI_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif diff --git a/hw/bsp/kinetis/family.mk b/hw/bsp/kinetis/family.mk new file mode 100644 index 000000000..65767988a --- /dev/null +++ b/hw/bsp/kinetis/family.mk @@ -0,0 +1,46 @@ +DEPS_SUBMODULES += hw/mcu/nxp/nxp_sdk hw/mcu/nxp/mcux-sdk + +include $(TOP)/$(BOARD_PATH)/board.mk + +CFLAGS += \ + -mthumb \ + -mabi=aapcs \ + +SRC_C += \ + src/portable/nxp/khci/dcd_khci.c \ + src/portable/nxp/khci/hcd_khci.c \ + $(MCU_DIR)/system_$(MCU).c \ + $(MCU_DIR)/project_template/clock_config.c \ + $(MCU_DIR)/drivers/fsl_clock.c \ + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(SDK_DIR)/CMSIS/Include \ + $(TOP)/$(MCU_DIR) \ + $(TOP)/$(MCU_DIR)/project_template \ + $(TOP)/$(MCU_DIR)/drivers + +# mcu-sdk has different driver layout than previous old sdk +ifeq ($(SDK_DIR),hw/mcu/nxp/mcux-sdk) + +SRC_C += \ + $(SDK_DIR)/drivers/gpio/fsl_gpio.c \ + $(SDK_DIR)/drivers/lpuart/fsl_lpuart.c + +INC += \ + $(TOP)/$(SDK_DIR)/drivers/smc \ + $(TOP)/$(SDK_DIR)/drivers/common \ + $(TOP)/$(SDK_DIR)/drivers/gpio \ + $(TOP)/$(SDK_DIR)/drivers/port \ + $(TOP)/$(SDK_DIR)/drivers/lpuart \ + +else + +SRC_C += \ + $(MCU_DIR)/drivers/fsl_gpio.c \ + $(MCU_DIR)/drivers/fsl_lpsci.c \ + $(MCU_DIR)/drivers/fsl_uart.c + +endif + +SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 18e40e1b1..a94e1877f 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -86,6 +86,8 @@ #define TUP_RHPORT_HIGHSPEED 1 // Port0 HS, Port1 HS #elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2AXX, OPT_MCU_K32L2BXX) + #define TUP_USBIP_CHIPIDEA_FS + #define TUP_USBIP_CHIPIDEA_FS_KINETIS #define TUP_DCD_ENDPOINT_MAX 16 #elif TU_CHECK_MCU(OPT_MCU_MM32F327X) diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 2678cdca1..52f4145f2 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -26,15 +26,14 @@ #include "tusb_option.h" -#if CFG_TUD_ENABLED && \ - ( \ - ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || \ - ( CFG_TUSB_MCU == OPT_MCU_K32L2AXX ) || \ - ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX ) \ - ) - -#include "fsl_device_registers.h" -#define KHCI USB0 +#if CFG_TUD_ENABLED && defined(TUP_USBIP_CHIPIDEA_FS) + +#ifdef TUP_USBIP_CHIPIDEA_FS_KINETIS + #include "fsl_device_registers.h" + #define KHCI USB0 +#else + #error "MCU is not supported" +#endif #include "device/dcd.h" diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index 8ff1feff7..27073dce7 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -26,7 +26,7 @@ #include "tusb_option.h" -#if CFG_TUD_ENABLED && \ +#if CFG_TUH_ENABLED && \ ( \ ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || \ ( CFG_TUSB_MCU == OPT_MCU_K32L2AXX ) || \ -- cgit v1.3.1 From 1fc203b085ba6ce2edef90e9dcc75ec72eaeb314 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 18 Mar 2023 19:50:24 +0700 Subject: more update to kinetis bsp --- docs/reference/supported.rst | 2 +- hw/bsp/board_mcu.h | 14 +- hw/bsp/kinetis/boards/frdm_k32l2a4s/board.h | 58 ------ hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk | 26 --- .../kinetis/boards/frdm_k32l2a4s/frdm_k32l2a4s.c | 171 ---------------- hw/bsp/kinetis/boards/frdm_k32l2b/board.h | 56 ------ hw/bsp/kinetis/boards/frdm_k32l2b/board.mk | 26 --- hw/bsp/kinetis/boards/frdm_k32l2b/frdm_k32l2b.c | 140 ------------- hw/bsp/kinetis/boards/frdm_kl25z/board.mk | 31 --- hw/bsp/kinetis/boards/frdm_kl25z/frdm_kl25z.c | 176 ----------------- hw/bsp/kinetis/family.mk | 46 ----- hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.h | 58 ++++++ hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.mk | 26 +++ .../boards/frdm_k32l2a4s/frdm_k32l2a4s.c | 171 ++++++++++++++++ hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.h | 56 ++++++ hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.mk | 26 +++ .../kinetis_k32/boards/frdm_k32l2b/frdm_k32l2b.c | 140 +++++++++++++ .../boards/kuiic/K32L2B31xxxxA_flash.ld | 216 +++++++++++++++++++++ hw/bsp/kinetis_k32/boards/kuiic/board.h | 45 +++++ hw/bsp/kinetis_k32/boards/kuiic/board.mk | 26 +++ hw/bsp/kinetis_k32/boards/kuiic/kuiic.c | 203 +++++++++++++++++++ hw/bsp/kinetis_k32/family.mk | 32 +++ hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk | 20 ++ hw/bsp/kinetis_kl/boards/frdm_kl25z/frdm_kl25z.c | 176 +++++++++++++++++ hw/bsp/kinetis_kl/family.mk | 37 ++++ hw/bsp/kuiic/K32L2B31xxxxA_flash.ld | 216 --------------------- hw/bsp/kuiic/board.h | 45 ----- hw/bsp/kuiic/board.mk | 52 ----- hw/bsp/kuiic/kuiic.c | 203 ------------------- src/common/tusb_mcu.h | 2 +- src/portable/nxp/khci/hcd_khci.c | 17 +- src/tusb_option.h | 8 +- 32 files changed, 1254 insertions(+), 1267 deletions(-) delete mode 100644 hw/bsp/kinetis/boards/frdm_k32l2a4s/board.h delete mode 100644 hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk delete mode 100644 hw/bsp/kinetis/boards/frdm_k32l2a4s/frdm_k32l2a4s.c delete mode 100644 hw/bsp/kinetis/boards/frdm_k32l2b/board.h delete mode 100644 hw/bsp/kinetis/boards/frdm_k32l2b/board.mk delete mode 100644 hw/bsp/kinetis/boards/frdm_k32l2b/frdm_k32l2b.c delete mode 100644 hw/bsp/kinetis/boards/frdm_kl25z/board.mk delete mode 100644 hw/bsp/kinetis/boards/frdm_kl25z/frdm_kl25z.c delete mode 100644 hw/bsp/kinetis/family.mk create mode 100644 hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.h create mode 100644 hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.mk create mode 100644 hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/frdm_k32l2a4s.c create mode 100644 hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.h create mode 100644 hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.mk create mode 100644 hw/bsp/kinetis_k32/boards/frdm_k32l2b/frdm_k32l2b.c create mode 100644 hw/bsp/kinetis_k32/boards/kuiic/K32L2B31xxxxA_flash.ld create mode 100644 hw/bsp/kinetis_k32/boards/kuiic/board.h create mode 100644 hw/bsp/kinetis_k32/boards/kuiic/board.mk create mode 100644 hw/bsp/kinetis_k32/boards/kuiic/kuiic.c create mode 100644 hw/bsp/kinetis_k32/family.mk create mode 100644 hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk create mode 100644 hw/bsp/kinetis_kl/boards/frdm_kl25z/frdm_kl25z.c create mode 100644 hw/bsp/kinetis_kl/family.mk delete mode 100644 hw/bsp/kuiic/K32L2B31xxxxA_flash.ld delete mode 100644 hw/bsp/kuiic/board.h delete mode 100644 hw/bsp/kuiic/board.mk delete mode 100644 hw/bsp/kuiic/kuiic.c (limited to 'src') diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index b1e0c0a68..a5d055893 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -253,7 +253,7 @@ Kinetis ^^^^^^^ - `Freedom FRDM-KL25Z `__ -- `Freedom FRDM-K32L2A `__ +- `Freedom FRDM-K32L2A4S `__ - `Freedom FRDM-K32L2B3 `__ - `KUIIC `__ diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index 920e7d0d9..cd195a19b 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -39,15 +39,15 @@ //--------------------------------------------------------------------+ // Include order follows OPT_MCU_ number -#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX || \ - CFG_TUSB_MCU == OPT_MCU_LPC15XX || CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || \ - CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC18XX || \ - CFG_TUSB_MCU == OPT_MCU_LPC40XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX +#if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX) || \ + TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC18XX) || \ + TU_CHECK_MCU(OPT_MCU_LPC40XX, OPT_MCU_LPC43XX) #include "chip.h" -#elif CFG_TUSB_MCU == OPT_MCU_LPC51UXX || CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \ - CFG_TUSB_MCU == OPT_MCU_LPC55XX || CFG_TUSB_MCU == OPT_MCU_MKL25ZXX || \ - CFG_TUSB_MCU == OPT_MCU_K32L2AXX || OPT_MCU_K32L2BXX +#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX) + #include "fsl_device_registers.h" + +#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32) #include "fsl_device_registers.h" #elif CFG_TUSB_MCU == OPT_MCU_NRF5X diff --git a/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.h b/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.h deleted file mode 100644 index b1f38c997..000000000 --- a/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "fsl_device_registers.h" - -// LED -// The Red LED is on PTE29. -// The Green LED is on PTC4. -// The Blue LED is on PTE31. -#define LED_PIN_CLOCK kCLOCK_PortC -#define LED_GPIO GPIOC -#define LED_PORT PORTC -#define LED_PIN 4 -#define LED_STATE_ON 0 - -// SW3 button1 -#define BUTTON_PIN_CLOCK kCLOCK_PortE -#define BUTTON_GPIO GPIOE -#define BUTTON_PORT PORTE -#define BUTTON_PIN 4 -#define BUTTON_STATE_ACTIVE 0 - -// UART -#define UART_PORT LPUART0 -#define UART_PIN_CLOCK kCLOCK_PortB -#define UART_PIN_GPIO GPIOB -#define UART_PIN_PORT PORTB -#define UART_PIN_RX 16u -#define UART_PIN_TX 17u - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk deleted file mode 100644 index 723fb3893..000000000 --- a/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk +++ /dev/null @@ -1,26 +0,0 @@ -SDK_DIR = hw/mcu/nxp/mcux-sdk -MCU = K32L2A41A -MCU_DIR = $(SDK_DIR)/devices/$(MCU) - -CFLAGS += \ - -mcpu=cortex-m0plus \ - -DCPU_K32L2A41VLH1A \ - -DCFG_TUSB_MCU=OPT_MCU_K32L2AXX - -# mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual - -# All source paths should be relative to the top level. -LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld - -# For freeRTOS port source -FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 - -# For flash-jlink target -JLINK_DEVICE = K32L2A41xxxxA - -# For flash-pyocd target -PYOCD_TARGET = K32L2A - -# flash using pyocd -flash: flash-pyocd diff --git a/hw/bsp/kinetis/boards/frdm_k32l2a4s/frdm_k32l2a4s.c b/hw/bsp/kinetis/boards/frdm_k32l2a4s/frdm_k32l2a4s.c deleted file mode 100644 index 80830163b..000000000 --- a/hw/bsp/kinetis/boards/frdm_k32l2a4s/frdm_k32l2a4s.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2018, hathach (tinyusb.org) - * Copyright (c) 2020, Koji Kitayama - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "bsp/board.h" -#include "board.h" -#include "fsl_gpio.h" -#include "fsl_port.h" -#include "fsl_clock.h" -#include "fsl_lpuart.h" - -#include "clock_config.h" - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB0_IRQHandler(void) -{ - tud_int_handler(0); -} - -void board_init(void) -{ - /* Enable port clocks for UART/LED/Button pins */ - CLOCK_EnableClock(UART_PIN_CLOCK); - CLOCK_EnableClock(LED_PIN_CLOCK); - CLOCK_EnableClock(BUTTON_PIN_CLOCK); - - gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; - GPIO_PinInit(LED_GPIO, LED_PIN, &led_config); - PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio); - - gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; - GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); - const port_pin_config_t BUTTON_CFG = { - kPORT_PullUp, - kPORT_FastSlewRate, - kPORT_PassiveFilterDisable, - kPORT_OpenDrainDisable, - kPORT_LowDriveStrength, - kPORT_MuxAsGpio, - kPORT_UnlockRegister - }; - PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); - - /* - Enable LPUART0 clock and configure port pins. - FIR clock is being used so the USB examples work. - */ - PCC_LPUART0 = 0U; /* Clock must be off to set PCS */ - PCC_LPUART0 = PCC_CLKCFG_PCS( 3U ); /* Select the clock. 1:OSCCLK/Bus Clock, 2:Slow IRC, 3: Fast IRC, 6: System PLL */ - PCC_LPUART0 |= PCC_CLKCFG_CGC( 1U ); /* Enable LPUART */ - - /* PORTB16 (pin 62) is configured as LPUART0_RX */ - gpio_pin_config_t const lpuart_config_rx = { kGPIO_DigitalInput, 0 }; - GPIO_PinInit(UART_PIN_GPIO, UART_PIN_RX, &lpuart_config_rx); - const port_pin_config_t UART_CFG = { - kPORT_PullUp, - kPORT_FastSlewRate, - kPORT_PassiveFilterDisable, - kPORT_OpenDrainDisable, - kPORT_LowDriveStrength, - kPORT_MuxAsGpio, - kPORT_UnlockRegister - }; - PORT_SetPinConfig(UART_PIN_PORT, UART_PIN_RX, &UART_CFG); - PORT_SetPinMux( UART_PIN_PORT, UART_PIN_RX, kPORT_MuxAlt3); - - /* PORTB17 (pin 63) is configured as LPUART0_TX */ - gpio_pin_config_t const lpuart_config_tx = { kGPIO_DigitalOutput, 0 }; - GPIO_PinInit( UART_PIN_GPIO, UART_PIN_TX, &lpuart_config_tx); - PORT_SetPinMux( UART_PIN_PORT, UART_PIN_TX, kPORT_MuxAlt3); - - BOARD_BootClockRUN(); - SystemCoreClockUpdate(); - -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); -#endif - - lpuart_config_t uart_config; - LPUART_GetDefaultConfig(&uart_config); - uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; - uart_config.enableTx = true; - uart_config.enableRx = true; - LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_ScgFircClk)); - - // USB - CLOCK_EnableUsbfs0Clock(kCLOCK_IpSrcFircAsync, 48000000U); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); -} - -uint32_t board_button_read(void) -{ - return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); -} - -int board_uart_read(uint8_t* buf, int len) -{ -#if 0 /* - Use this version if want the LED to blink during BOARD=board_test, - without having to hit a key. - */ - if( 0U != (kLPUART_RxDataRegFullFlag & LPUART_GetStatusFlags( UART_PORT )) ) - { - LPUART_ReadBlocking(UART_PORT, buf, len); - return len; - } - - return( 0 ); -#else /* Wait for 'len' characters to come in */ - - LPUART_ReadBlocking(UART_PORT, buf, len); - return len; - -#endif -} - -int board_uart_write(void const * buf, int len) -{ - LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler(void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#endif diff --git a/hw/bsp/kinetis/boards/frdm_k32l2b/board.h b/hw/bsp/kinetis/boards/frdm_k32l2b/board.h deleted file mode 100644 index 8d21fdcd4..000000000 --- a/hw/bsp/kinetis/boards/frdm_k32l2b/board.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "fsl_device_registers.h" - -// LED -#define LED_PIN_CLOCK kCLOCK_PortD -#define LED_GPIO GPIOD -#define LED_PORT PORTD -#define LED_PIN 5 -#define LED_STATE_ON 0 - -// SW3 button1 -#define BUTTON_PIN_CLOCK kCLOCK_PortC -#define BUTTON_GPIO GPIOC -#define BUTTON_PORT PORTC -#define BUTTON_PIN 3 -#define BUTTON_STATE_ACTIVE 0 - -// UART -#define UART_PORT LPUART0 -#define UART_PIN_CLOCK kCLOCK_PortA -#define UART_PIN_PORT PORTA -#define UART_PIN_RX 1u -#define UART_PIN_TX 2u -#define SOPT5_LPUART0RXSRC_LPUART_RX 0x00u /*!<@brief LPUART0 Receive Data Source Select: LPUART_RX pin */ -#define SOPT5_LPUART0TXSRC_LPUART_TX 0x00u /*!<@brief LPUART0 Transmit Data Source Select: LPUART0_TX pin */ - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/kinetis/boards/frdm_k32l2b/board.mk b/hw/bsp/kinetis/boards/frdm_k32l2b/board.mk deleted file mode 100644 index 66d408c67..000000000 --- a/hw/bsp/kinetis/boards/frdm_k32l2b/board.mk +++ /dev/null @@ -1,26 +0,0 @@ -SDK_DIR = hw/mcu/nxp/mcux-sdk -MCU = K32L2B31A -MCU_DIR = $(SDK_DIR)/devices/$(MCU) - -CFLAGS += \ - -mcpu=cortex-m0plus \ - -DCPU_K32L2B31VLH0A \ - -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX - -# mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls - -# All source paths should be relative to the top level. -LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld - -# For freeRTOS port source -FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 - -# For flash-jlink target -JLINK_DEVICE = K32L2B31xxxxA - -# For flash-pyocd target -PYOCD_TARGET = K32L2B - -# flash using pyocd -flash: flash-pyocd diff --git a/hw/bsp/kinetis/boards/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/kinetis/boards/frdm_k32l2b/frdm_k32l2b.c deleted file mode 100644 index 1566b4e2e..000000000 --- a/hw/bsp/kinetis/boards/frdm_k32l2b/frdm_k32l2b.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2018, hathach (tinyusb.org) - * Copyright (c) 2020, Koji Kitayama - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "bsp/board.h" -#include "board.h" -#include "fsl_gpio.h" -#include "fsl_port.h" -#include "fsl_clock.h" -#include "fsl_lpuart.h" - -#include "clock_config.h" - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB0_IRQHandler(void) -{ - tud_int_handler(0); -} - -void board_init(void) -{ - /* Enable port clocks for UART/LED/Button pins */ - CLOCK_EnableClock(UART_PIN_CLOCK); - CLOCK_EnableClock(LED_PIN_CLOCK); - CLOCK_EnableClock(BUTTON_PIN_CLOCK); - - gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; - GPIO_PinInit(LED_GPIO, LED_PIN, &led_config); - PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio); - - gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; - GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); - const port_pin_config_t BUTTON_CFG = { - kPORT_PullUp, - kPORT_FastSlewRate, - kPORT_PassiveFilterDisable, - kPORT_LowDriveStrength, - kPORT_MuxAsGpio - }; - PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); - - /* PORTA1 (pin 23) is configured as LPUART0_RX */ - PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2); - /* PORTA2 (pin 24) is configured as LPUART0_TX */ - PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2); - - SIM->SOPT5 = ((SIM->SOPT5 & - /* Mask bits to zero which are setting */ - (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK))) - /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */ - | SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX) - /* LPUART0 Receive Data Source Select: LPUART_RX pin. */ - | SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX)); - - BOARD_BootClockRUN(); - SystemCoreClockUpdate(); - CLOCK_SetLpuart0Clock(1); - -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); -#endif - - lpuart_config_t uart_config; - LPUART_GetDefaultConfig(&uart_config); - uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; - uart_config.enableTx = true; - uart_config.enableRx = true; - LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk)); - - // USB - CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); -} - -uint32_t board_button_read(void) -{ - return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); -} - -int board_uart_read(uint8_t* buf, int len) -{ - LPUART_ReadBlocking(UART_PORT, buf, len); - return len; -} - -int board_uart_write(void const * buf, int len) -{ - LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler(void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#endif diff --git a/hw/bsp/kinetis/boards/frdm_kl25z/board.mk b/hw/bsp/kinetis/boards/frdm_kl25z/board.mk deleted file mode 100644 index 5ce6cd51e..000000000 --- a/hw/bsp/kinetis/boards/frdm_kl25z/board.mk +++ /dev/null @@ -1,31 +0,0 @@ -SDK_DIR = hw/mcu/nxp/nxp_sdk -MCU = MKL25Z4 -MCU_DIR = $(SDK_DIR)/devices/$(MCU) - -CFLAGS += \ - -mcpu=cortex-m0plus \ - -DCPU_MKL25Z128VLK4 \ - -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX \ - -DCFG_EXAMPLE_VIDEO_READONLY - -LDFLAGS += \ - -Wl,--defsym,__stack_size__=0x400 \ - -Wl,--defsym,__heap_size__=0 - -# mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=format -Wno-error=redundant-decls - -# All source paths should be relative to the top level. -LD_FILE = $(MCU_DIR)/gcc/MKL25Z128xxx4_flash.ld - -# For freeRTOS port source -FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 - -# For flash-jlink target -JLINK_DEVICE = MKL25Z128xxx4 - -# For flash-pyocd target -PYOCD_TARGET = mkl25zl128 - -# flash using pyocd -flash: flash-jlink diff --git a/hw/bsp/kinetis/boards/frdm_kl25z/frdm_kl25z.c b/hw/bsp/kinetis/boards/frdm_kl25z/frdm_kl25z.c deleted file mode 100644 index 46f85f6a5..000000000 --- a/hw/bsp/kinetis/boards/frdm_kl25z/frdm_kl25z.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2018, hathach (tinyusb.org) - * Copyright (c) 2020, Koji Kitayama - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "../board.h" -#include "fsl_device_registers.h" -#include "fsl_gpio.h" -#include "fsl_port.h" -#include "fsl_clock.h" -#include "fsl_lpsci.h" - -#include "clock_config.h" - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB0_IRQHandler(void) -{ -#if CFG_TUH_ENABLED - tuh_int_handler(0); -#endif -#if CFG_TUD_ENABLED - tud_int_handler(0); -#endif -} - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM DECLARATION -//--------------------------------------------------------------------+ -// LED -#define LED_PINMUX IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 -#define LED_PORT GPIOB -#define LED_PIN_CLOCK kCLOCK_PortB -#define LED_PIN_PORT PORTB -#define LED_PIN 19U -#define LED_PIN_FUNCTION kPORT_MuxAsGpio -#define LED_STATE_ON 0 - -// Button -#define BUTTON_PORT GPIOC -#define BUTTON_PIN_CLOCK kCLOCK_PortC -#define BUTTON_PIN_PORT PORTC -#define BUTTON_PIN 9U -#define BUTTON_PIN_FUNCTION kPORT_MuxAsGpio -#define BUTTON_STATE_ACTIVE 0 - -// UART -#define UART_PORT UART0 -#define UART_PIN_CLOCK kCLOCK_PortA -#define UART_PIN_PORT PORTA -#define UART_PIN_RX 1u -#define UART_PIN_TX 2u -#define UART_PIN_FUNCTION kPORT_MuxAlt2 -#define SOPT5_UART0RXSRC_UART_RX 0x00u /*!< UART0 receive data source select: UART0_RX pin */ -#define SOPT5_UART0TXSRC_UART_TX 0x00u /*!< UART0 transmit data source select: UART0_TX pin */ - -const uint8_t dcd_data[] = { 0x00 }; - -void board_init(void) -{ - BOARD_BootClockRUN(); - SystemCoreClockUpdate(); - -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); -#endif - - // LED - CLOCK_EnableClock(LED_PIN_CLOCK); - PORT_SetPinMux(LED_PIN_PORT, LED_PIN, LED_PIN_FUNCTION); - gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; - GPIO_PinInit(LED_PORT, LED_PIN, &led_config); - board_led_write(false); - -#if defined(BUTTON_PORT) && defined(BUTTON_PIN) - // Button - CLOCK_EnableClock(BUTTON_PIN_CLOCK); - port_pin_config_t button_port = { - .pullSelect = kPORT_PullUp, - .mux = BUTTON_PIN_FUNCTION, - }; - PORT_SetPinConfig(BUTTON_PIN_PORT, BUTTON_PIN, &button_port); - gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; - GPIO_PinInit(BUTTON_PORT, BUTTON_PIN, &button_config); -#endif - - // UART - CLOCK_EnableClock(UART_PIN_CLOCK); - PORT_SetPinMux(UART_PIN_PORT, UART_PIN_RX, UART_PIN_FUNCTION); - PORT_SetPinMux(UART_PIN_PORT, UART_PIN_TX, UART_PIN_FUNCTION); - SIM->SOPT5 = ((SIM->SOPT5 & - (~(SIM_SOPT5_UART0TXSRC_MASK | SIM_SOPT5_UART0RXSRC_MASK))) - | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX) - | SIM_SOPT5_UART0RXSRC(SOPT5_UART0RXSRC_UART_RX) - ); - - lpsci_config_t uart_config; - CLOCK_SetLpsci0Clock(1); - LPSCI_GetDefaultConfig(&uart_config); - uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; - uart_config.enableTx = true; - uart_config.enableRx = true; - LPSCI_Init(UART_PORT, &uart_config, CLOCK_GetPllFllSelClkFreq()); - - // USB - CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk)); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - GPIO_WritePinOutput(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); -} - -uint32_t board_button_read(void) -{ -#if defined(BUTTON_PORT) && defined(BUTTON_PIN) - return BUTTON_STATE_ACTIVE == GPIO_ReadPinInput(BUTTON_PORT, BUTTON_PIN); -#endif - return 0; -} - -int board_uart_read(uint8_t* buf, int len) -{ - LPSCI_ReadBlocking(UART_PORT, buf, len); - return len; -} - -int board_uart_write(void const * buf, int len) -{ - LPSCI_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler(void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#endif diff --git a/hw/bsp/kinetis/family.mk b/hw/bsp/kinetis/family.mk deleted file mode 100644 index 65767988a..000000000 --- a/hw/bsp/kinetis/family.mk +++ /dev/null @@ -1,46 +0,0 @@ -DEPS_SUBMODULES += hw/mcu/nxp/nxp_sdk hw/mcu/nxp/mcux-sdk - -include $(TOP)/$(BOARD_PATH)/board.mk - -CFLAGS += \ - -mthumb \ - -mabi=aapcs \ - -SRC_C += \ - src/portable/nxp/khci/dcd_khci.c \ - src/portable/nxp/khci/hcd_khci.c \ - $(MCU_DIR)/system_$(MCU).c \ - $(MCU_DIR)/project_template/clock_config.c \ - $(MCU_DIR)/drivers/fsl_clock.c \ - -INC += \ - $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(SDK_DIR)/CMSIS/Include \ - $(TOP)/$(MCU_DIR) \ - $(TOP)/$(MCU_DIR)/project_template \ - $(TOP)/$(MCU_DIR)/drivers - -# mcu-sdk has different driver layout than previous old sdk -ifeq ($(SDK_DIR),hw/mcu/nxp/mcux-sdk) - -SRC_C += \ - $(SDK_DIR)/drivers/gpio/fsl_gpio.c \ - $(SDK_DIR)/drivers/lpuart/fsl_lpuart.c - -INC += \ - $(TOP)/$(SDK_DIR)/drivers/smc \ - $(TOP)/$(SDK_DIR)/drivers/common \ - $(TOP)/$(SDK_DIR)/drivers/gpio \ - $(TOP)/$(SDK_DIR)/drivers/port \ - $(TOP)/$(SDK_DIR)/drivers/lpuart \ - -else - -SRC_C += \ - $(MCU_DIR)/drivers/fsl_gpio.c \ - $(MCU_DIR)/drivers/fsl_lpsci.c \ - $(MCU_DIR)/drivers/fsl_uart.c - -endif - -SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S diff --git a/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.h b/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.h new file mode 100644 index 000000000..b1f38c997 --- /dev/null +++ b/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.h @@ -0,0 +1,58 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "fsl_device_registers.h" + +// LED +// The Red LED is on PTE29. +// The Green LED is on PTC4. +// The Blue LED is on PTE31. +#define LED_PIN_CLOCK kCLOCK_PortC +#define LED_GPIO GPIOC +#define LED_PORT PORTC +#define LED_PIN 4 +#define LED_STATE_ON 0 + +// SW3 button1 +#define BUTTON_PIN_CLOCK kCLOCK_PortE +#define BUTTON_GPIO GPIOE +#define BUTTON_PORT PORTE +#define BUTTON_PIN 4 +#define BUTTON_STATE_ACTIVE 0 + +// UART +#define UART_PORT LPUART0 +#define UART_PIN_CLOCK kCLOCK_PortB +#define UART_PIN_GPIO GPIOB +#define UART_PIN_PORT PORTB +#define UART_PIN_RX 16u +#define UART_PIN_TX 17u + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.mk new file mode 100644 index 000000000..d96ab58b8 --- /dev/null +++ b/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.mk @@ -0,0 +1,26 @@ +MCU = K32L2A41A + +CFLAGS += \ + -mcpu=cortex-m0plus \ + -DCPU_K32L2A41VLH1A \ + +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual + +# All source paths should be relative to the top level. +LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld + +SRC_C += \ + $(MCU_DIR)/project_template/clock_config.c \ + +# For freeRTOS port source +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 + +# For flash-jlink target +JLINK_DEVICE = K32L2A41xxxxA + +# For flash-pyocd target +PYOCD_TARGET = K32L2A + +# flash using pyocd +flash: flash-pyocd diff --git a/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/frdm_k32l2a4s.c b/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/frdm_k32l2a4s.c new file mode 100644 index 000000000..80830163b --- /dev/null +++ b/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/frdm_k32l2a4s.c @@ -0,0 +1,171 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2018, hathach (tinyusb.org) + * Copyright (c) 2020, Koji Kitayama + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "bsp/board.h" +#include "board.h" +#include "fsl_gpio.h" +#include "fsl_port.h" +#include "fsl_clock.h" +#include "fsl_lpuart.h" + +#include "clock_config.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB0_IRQHandler(void) +{ + tud_int_handler(0); +} + +void board_init(void) +{ + /* Enable port clocks for UART/LED/Button pins */ + CLOCK_EnableClock(UART_PIN_CLOCK); + CLOCK_EnableClock(LED_PIN_CLOCK); + CLOCK_EnableClock(BUTTON_PIN_CLOCK); + + gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; + GPIO_PinInit(LED_GPIO, LED_PIN, &led_config); + PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio); + + gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); + const port_pin_config_t BUTTON_CFG = { + kPORT_PullUp, + kPORT_FastSlewRate, + kPORT_PassiveFilterDisable, + kPORT_OpenDrainDisable, + kPORT_LowDriveStrength, + kPORT_MuxAsGpio, + kPORT_UnlockRegister + }; + PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); + + /* + Enable LPUART0 clock and configure port pins. + FIR clock is being used so the USB examples work. + */ + PCC_LPUART0 = 0U; /* Clock must be off to set PCS */ + PCC_LPUART0 = PCC_CLKCFG_PCS( 3U ); /* Select the clock. 1:OSCCLK/Bus Clock, 2:Slow IRC, 3: Fast IRC, 6: System PLL */ + PCC_LPUART0 |= PCC_CLKCFG_CGC( 1U ); /* Enable LPUART */ + + /* PORTB16 (pin 62) is configured as LPUART0_RX */ + gpio_pin_config_t const lpuart_config_rx = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(UART_PIN_GPIO, UART_PIN_RX, &lpuart_config_rx); + const port_pin_config_t UART_CFG = { + kPORT_PullUp, + kPORT_FastSlewRate, + kPORT_PassiveFilterDisable, + kPORT_OpenDrainDisable, + kPORT_LowDriveStrength, + kPORT_MuxAsGpio, + kPORT_UnlockRegister + }; + PORT_SetPinConfig(UART_PIN_PORT, UART_PIN_RX, &UART_CFG); + PORT_SetPinMux( UART_PIN_PORT, UART_PIN_RX, kPORT_MuxAlt3); + + /* PORTB17 (pin 63) is configured as LPUART0_TX */ + gpio_pin_config_t const lpuart_config_tx = { kGPIO_DigitalOutput, 0 }; + GPIO_PinInit( UART_PIN_GPIO, UART_PIN_TX, &lpuart_config_tx); + PORT_SetPinMux( UART_PIN_PORT, UART_PIN_TX, kPORT_MuxAlt3); + + BOARD_BootClockRUN(); + SystemCoreClockUpdate(); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + lpuart_config_t uart_config; + LPUART_GetDefaultConfig(&uart_config); + uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; + uart_config.enableTx = true; + uart_config.enableRx = true; + LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_ScgFircClk)); + + // USB + CLOCK_EnableUsbfs0Clock(kCLOCK_IpSrcFircAsync, 48000000U); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); +} + +int board_uart_read(uint8_t* buf, int len) +{ +#if 0 /* + Use this version if want the LED to blink during BOARD=board_test, + without having to hit a key. + */ + if( 0U != (kLPUART_RxDataRegFullFlag & LPUART_GetStatusFlags( UART_PORT )) ) + { + LPUART_ReadBlocking(UART_PORT, buf, len); + return len; + } + + return( 0 ); +#else /* Wait for 'len' characters to come in */ + + LPUART_ReadBlocking(UART_PORT, buf, len); + return len; + +#endif +} + +int board_uart_write(void const * buf, int len) +{ + LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif diff --git a/hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.h b/hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.h new file mode 100644 index 000000000..8d21fdcd4 --- /dev/null +++ b/hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.h @@ -0,0 +1,56 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "fsl_device_registers.h" + +// LED +#define LED_PIN_CLOCK kCLOCK_PortD +#define LED_GPIO GPIOD +#define LED_PORT PORTD +#define LED_PIN 5 +#define LED_STATE_ON 0 + +// SW3 button1 +#define BUTTON_PIN_CLOCK kCLOCK_PortC +#define BUTTON_GPIO GPIOC +#define BUTTON_PORT PORTC +#define BUTTON_PIN 3 +#define BUTTON_STATE_ACTIVE 0 + +// UART +#define UART_PORT LPUART0 +#define UART_PIN_CLOCK kCLOCK_PortA +#define UART_PIN_PORT PORTA +#define UART_PIN_RX 1u +#define UART_PIN_TX 2u +#define SOPT5_LPUART0RXSRC_LPUART_RX 0x00u /*!<@brief LPUART0 Receive Data Source Select: LPUART_RX pin */ +#define SOPT5_LPUART0TXSRC_LPUART_TX 0x00u /*!<@brief LPUART0 Transmit Data Source Select: LPUART0_TX pin */ + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.mk b/hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.mk new file mode 100644 index 000000000..5f8ecbfe4 --- /dev/null +++ b/hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.mk @@ -0,0 +1,26 @@ +MCU = K32L2B31A + +CFLAGS += \ + -mcpu=cortex-m0plus \ + -DCPU_K32L2B31VLH0A \ + +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls + +# All source paths should be relative to the top level. +LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld + +SRC_C += \ + $(MCU_DIR)/project_template/clock_config.c \ + +# For freeRTOS port source +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 + +# For flash-jlink target +JLINK_DEVICE = K32L2B31xxxxA + +# For flash-pyocd target +PYOCD_TARGET = K32L2B + +# flash using pyocd +flash: flash-pyocd diff --git a/hw/bsp/kinetis_k32/boards/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/kinetis_k32/boards/frdm_k32l2b/frdm_k32l2b.c new file mode 100644 index 000000000..1566b4e2e --- /dev/null +++ b/hw/bsp/kinetis_k32/boards/frdm_k32l2b/frdm_k32l2b.c @@ -0,0 +1,140 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2018, hathach (tinyusb.org) + * Copyright (c) 2020, Koji Kitayama + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "bsp/board.h" +#include "board.h" +#include "fsl_gpio.h" +#include "fsl_port.h" +#include "fsl_clock.h" +#include "fsl_lpuart.h" + +#include "clock_config.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB0_IRQHandler(void) +{ + tud_int_handler(0); +} + +void board_init(void) +{ + /* Enable port clocks for UART/LED/Button pins */ + CLOCK_EnableClock(UART_PIN_CLOCK); + CLOCK_EnableClock(LED_PIN_CLOCK); + CLOCK_EnableClock(BUTTON_PIN_CLOCK); + + gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; + GPIO_PinInit(LED_GPIO, LED_PIN, &led_config); + PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio); + + gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); + const port_pin_config_t BUTTON_CFG = { + kPORT_PullUp, + kPORT_FastSlewRate, + kPORT_PassiveFilterDisable, + kPORT_LowDriveStrength, + kPORT_MuxAsGpio + }; + PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); + + /* PORTA1 (pin 23) is configured as LPUART0_RX */ + PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2); + /* PORTA2 (pin 24) is configured as LPUART0_TX */ + PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2); + + SIM->SOPT5 = ((SIM->SOPT5 & + /* Mask bits to zero which are setting */ + (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK))) + /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */ + | SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX) + /* LPUART0 Receive Data Source Select: LPUART_RX pin. */ + | SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX)); + + BOARD_BootClockRUN(); + SystemCoreClockUpdate(); + CLOCK_SetLpuart0Clock(1); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + lpuart_config_t uart_config; + LPUART_GetDefaultConfig(&uart_config); + uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; + uart_config.enableTx = true; + uart_config.enableRx = true; + LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk)); + + // USB + CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); +} + +int board_uart_read(uint8_t* buf, int len) +{ + LPUART_ReadBlocking(UART_PORT, buf, len); + return len; +} + +int board_uart_write(void const * buf, int len) +{ + LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif diff --git a/hw/bsp/kinetis_k32/boards/kuiic/K32L2B31xxxxA_flash.ld b/hw/bsp/kinetis_k32/boards/kuiic/K32L2B31xxxxA_flash.ld new file mode 100644 index 000000000..f478a99c7 --- /dev/null +++ b/hw/bsp/kinetis_k32/boards/kuiic/K32L2B31xxxxA_flash.ld @@ -0,0 +1,216 @@ +/* +** ################################################################### +** Processors: K32L2B31VFM0A +** K32L2B31VFT0A +** K32L2B31VLH0A +** K32L2B31VMP0A +** +** Compiler: GNU C Compiler +** Reference manual: K32L2B3xRM, Rev.0, July 2019 +** Version: rev. 1.0, 2019-07-30 +** Build: b190930 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00008000, LENGTH = 0x00000200 + m_flash_config (RX) : ORIGIN = 0x00008400, LENGTH = 0x00000010 + m_text (RX) : ORIGIN = 0x00008410, LENGTH = 0x00037BF0 + m_data (RW) : ORIGIN = 0x1FFFE000, LENGTH = 0x00008000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .flash_config : + { + . = ALIGN(4); + KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_flash_config + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + /* reserve MTB memory at the beginning of m_data */ + .mtb : /* MTB buffer address as defined by the hardware */ + { + . = ALIGN(8); + _mtb_start = .; + KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */ + . = ALIGN(8); + _mtb_end = .; + } > m_data + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} diff --git a/hw/bsp/kinetis_k32/boards/kuiic/board.h b/hw/bsp/kinetis_k32/boards/kuiic/board.h new file mode 100644 index 000000000..1e2d4f18b --- /dev/null +++ b/hw/bsp/kinetis_k32/boards/kuiic/board.h @@ -0,0 +1,45 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "fsl_device_registers.h" + +// LED +#define LED_PIN_CLOCK kCLOCK_PortA +#define LED_GPIO GPIOA +#define LED_PORT PORTA +#define LED_PIN 2 +#define LED_STATE_ON 1 + +// UART +#define UART_PORT LPUART1 +#define UART_PIN_RX 3u +#define UART_PIN_TX 0u + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/kinetis_k32/boards/kuiic/board.mk b/hw/bsp/kinetis_k32/boards/kuiic/board.mk new file mode 100644 index 000000000..29a12e982 --- /dev/null +++ b/hw/bsp/kinetis_k32/boards/kuiic/board.mk @@ -0,0 +1,26 @@ +MCU = K32L2B31A + +# This board uses TinyUF2 for updates +UF2_FAMILY_ID = 0x7f83e793 + +CFLAGS += \ + -mcpu=cortex-m0plus \ + -DCPU_K32L2B31VLH0A \ + +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls + +# All source paths should be relative to the top level. +LD_FILE = $(BOARD_PATH)/K32L2B31xxxxA_flash.ld + +# For freeRTOS port source +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 + +# For flash-jlink target +JLINK_DEVICE = K32L2B31xxxxA + +# For flash-pyocd target +PYOCD_TARGET = K32L2B + +# flash using pyocd +flash: flash-pyocd diff --git a/hw/bsp/kinetis_k32/boards/kuiic/kuiic.c b/hw/bsp/kinetis_k32/boards/kuiic/kuiic.c new file mode 100644 index 000000000..f9002a6d3 --- /dev/null +++ b/hw/bsp/kinetis_k32/boards/kuiic/kuiic.c @@ -0,0 +1,203 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2018, hathach (tinyusb.org) + * Copyright (c) 2020, Koji Kitayama + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "bsp/board.h" +#include "board.h" +#include "fsl_smc.h" +#include "fsl_gpio.h" +#include "fsl_port.h" +#include "fsl_clock.h" +#include "fsl_lpuart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */ +#define SOPT5_LPUART1RXSRC_LPUART_RX 0x00u /*!<@brief LPUART1 Receive Data Source Select: LPUART_RX pin */ +#define SOPT5_LPUART1TXSRC_LPUART_TX 0x00u /*!<@brief LPUART1 Transmit Data Source Select: LPUART_TX pin */ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +// extern uint32_t SystemCoreClock; + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = { + .outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */ + .irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ + .ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock selected */ + .fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */ + .lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */ + .hircEnableInNotHircMode = true, /* HIRC source is enabled */ +}; +const sim_clock_config_t simConfig_BOARD_BootClockRUN = { + .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */ + .clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */ +}; + +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Set the system clock dividers in SIM to safe value. */ + CLOCK_SetSimSafeDivs(); + /* Set MCG to HIRC mode. */ + CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN); + /* Set the clock configuration in SIM module. */ + CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} + + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB0_IRQHandler(void) +{ + tud_int_handler(0); +} + +void board_init(void) +{ + /* Enable port clocks for GPIO pins */ + CLOCK_EnableClock(kCLOCK_PortA); + CLOCK_EnableClock(kCLOCK_PortB); + CLOCK_EnableClock(kCLOCK_PortC); + CLOCK_EnableClock(kCLOCK_PortD); + CLOCK_EnableClock(kCLOCK_PortE); + + + gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 1 }; + GPIO_PinInit(GPIOA, 1U, &led_config); + PORT_SetPinMux(PORTA, 1U, kPORT_MuxAsGpio); + led_config.outputLogic = 0; + GPIO_PinInit(GPIOA, 2U, &led_config); + PORT_SetPinMux(PORTA, 2U, kPORT_MuxAsGpio); + +#ifdef BUTTON_PIN + gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); + const port_pin_config_t BUTTON_CFG = { + kPORT_PullUp, + kPORT_FastSlewRate, + kPORT_PassiveFilterDisable, + kPORT_LowDriveStrength, + kPORT_MuxAsGpio + }; + PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); +#endif + + /* PORTC3 is configured as LPUART0_RX */ + PORT_SetPinMux(PORTC, 3U, kPORT_MuxAlt3); + /* PORTA2 (pin 24) is configured as LPUART0_TX */ + PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3); + + SIM->SOPT5 = ((SIM->SOPT5 & + /* Mask bits to zero which are setting */ + (~(SIM_SOPT5_LPUART1TXSRC_MASK | SIM_SOPT5_LPUART1RXSRC_MASK))) + /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */ + | SIM_SOPT5_LPUART1TXSRC(SOPT5_LPUART1TXSRC_LPUART_TX) + /* LPUART0 Receive Data Source Select: LPUART_RX pin. */ + | SIM_SOPT5_LPUART1RXSRC(SOPT5_LPUART1RXSRC_LPUART_RX)); + + BOARD_BootClockRUN(); + SystemCoreClockUpdate(); + CLOCK_SetLpuart1Clock(1); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + lpuart_config_t uart_config; + LPUART_GetDefaultConfig(&uart_config); + uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; + uart_config.enableTx = true; + uart_config.enableRx = true; + LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk)); + + // USB + CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + if (state) { + LED_GPIO->PDDR |= GPIO_FIT_REG((1UL << LED_PIN)); + } else { + LED_GPIO->PDDR &= GPIO_FIT_REG(~(1UL << LED_PIN)); + } +// GPIO_PinWrite(GPIOA, 1, state ? LED_STATE_ON : (1-LED_STATE_ON) ); +// GPIO_PinWrite(GPIOA, 2, state ? (1-LED_STATE_ON) : LED_STATE_ON ); +} + +uint32_t board_button_read(void) +{ +#ifdef BUTTON_PIN + return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); +#else + return 0; +#endif +} + +int board_uart_read(uint8_t* buf, int len) +{ + LPUART_ReadBlocking(UART_PORT, buf, len); + return len; +} + +int board_uart_write(void const * buf, int len) +{ + LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif diff --git a/hw/bsp/kinetis_k32/family.mk b/hw/bsp/kinetis_k32/family.mk new file mode 100644 index 000000000..f89138b72 --- /dev/null +++ b/hw/bsp/kinetis_k32/family.mk @@ -0,0 +1,32 @@ +SDK_DIR = hw/mcu/nxp/mcux-sdk +DEPS_SUBMODULES += $(SDK_DIR) + +MCU_DIR = $(SDK_DIR)/devices/$(MCU) +include $(TOP)/$(BOARD_PATH)/board.mk + +CFLAGS += \ + -mthumb \ + -mabi=aapcs \ + -DCFG_TUSB_MCU=OPT_MCU_KINETIS_K32 + +SRC_C += \ + src/portable/nxp/khci/dcd_khci.c \ + src/portable/nxp/khci/hcd_khci.c \ + $(MCU_DIR)/system_$(MCU).c \ + $(MCU_DIR)/drivers/fsl_clock.c \ + $(SDK_DIR)/drivers/gpio/fsl_gpio.c \ + $(SDK_DIR)/drivers/lpuart/fsl_lpuart.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(SDK_DIR)/CMSIS/Include \ + $(TOP)/$(MCU_DIR) \ + $(TOP)/$(MCU_DIR)/project_template \ + $(TOP)/$(MCU_DIR)/drivers \ + $(TOP)/$(SDK_DIR)/drivers/smc \ + $(TOP)/$(SDK_DIR)/drivers/common \ + $(TOP)/$(SDK_DIR)/drivers/gpio \ + $(TOP)/$(SDK_DIR)/drivers/port \ + $(TOP)/$(SDK_DIR)/drivers/lpuart \ + +SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk new file mode 100644 index 000000000..affe864fb --- /dev/null +++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk @@ -0,0 +1,20 @@ +MCU = MKL25Z4 + +CFLAGS += \ + -DCPU_MKL25Z128VLK4 \ + -DCFG_EXAMPLE_VIDEO_READONLY + +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter -Wno-error=format -Wno-error=redundant-decls + +# All source paths should be relative to the top level. +LD_FILE = $(MCU_DIR)/gcc/MKL25Z128xxx4_flash.ld + +# For flash-jlink target +JLINK_DEVICE = MKL25Z128xxx4 + +# For flash-pyocd target +PYOCD_TARGET = mkl25zl128 + +# flash using pyocd +flash: flash-jlink diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/frdm_kl25z.c b/hw/bsp/kinetis_kl/boards/frdm_kl25z/frdm_kl25z.c new file mode 100644 index 000000000..46f85f6a5 --- /dev/null +++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/frdm_kl25z.c @@ -0,0 +1,176 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2018, hathach (tinyusb.org) + * Copyright (c) 2020, Koji Kitayama + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "../board.h" +#include "fsl_device_registers.h" +#include "fsl_gpio.h" +#include "fsl_port.h" +#include "fsl_clock.h" +#include "fsl_lpsci.h" + +#include "clock_config.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB0_IRQHandler(void) +{ +#if CFG_TUH_ENABLED + tuh_int_handler(0); +#endif +#if CFG_TUD_ENABLED + tud_int_handler(0); +#endif +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ +// LED +#define LED_PINMUX IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 +#define LED_PORT GPIOB +#define LED_PIN_CLOCK kCLOCK_PortB +#define LED_PIN_PORT PORTB +#define LED_PIN 19U +#define LED_PIN_FUNCTION kPORT_MuxAsGpio +#define LED_STATE_ON 0 + +// Button +#define BUTTON_PORT GPIOC +#define BUTTON_PIN_CLOCK kCLOCK_PortC +#define BUTTON_PIN_PORT PORTC +#define BUTTON_PIN 9U +#define BUTTON_PIN_FUNCTION kPORT_MuxAsGpio +#define BUTTON_STATE_ACTIVE 0 + +// UART +#define UART_PORT UART0 +#define UART_PIN_CLOCK kCLOCK_PortA +#define UART_PIN_PORT PORTA +#define UART_PIN_RX 1u +#define UART_PIN_TX 2u +#define UART_PIN_FUNCTION kPORT_MuxAlt2 +#define SOPT5_UART0RXSRC_UART_RX 0x00u /*!< UART0 receive data source select: UART0_RX pin */ +#define SOPT5_UART0TXSRC_UART_TX 0x00u /*!< UART0 transmit data source select: UART0_TX pin */ + +const uint8_t dcd_data[] = { 0x00 }; + +void board_init(void) +{ + BOARD_BootClockRUN(); + SystemCoreClockUpdate(); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + // LED + CLOCK_EnableClock(LED_PIN_CLOCK); + PORT_SetPinMux(LED_PIN_PORT, LED_PIN, LED_PIN_FUNCTION); + gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; + GPIO_PinInit(LED_PORT, LED_PIN, &led_config); + board_led_write(false); + +#if defined(BUTTON_PORT) && defined(BUTTON_PIN) + // Button + CLOCK_EnableClock(BUTTON_PIN_CLOCK); + port_pin_config_t button_port = { + .pullSelect = kPORT_PullUp, + .mux = BUTTON_PIN_FUNCTION, + }; + PORT_SetPinConfig(BUTTON_PIN_PORT, BUTTON_PIN, &button_port); + gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(BUTTON_PORT, BUTTON_PIN, &button_config); +#endif + + // UART + CLOCK_EnableClock(UART_PIN_CLOCK); + PORT_SetPinMux(UART_PIN_PORT, UART_PIN_RX, UART_PIN_FUNCTION); + PORT_SetPinMux(UART_PIN_PORT, UART_PIN_TX, UART_PIN_FUNCTION); + SIM->SOPT5 = ((SIM->SOPT5 & + (~(SIM_SOPT5_UART0TXSRC_MASK | SIM_SOPT5_UART0RXSRC_MASK))) + | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX) + | SIM_SOPT5_UART0RXSRC(SOPT5_UART0RXSRC_UART_RX) + ); + + lpsci_config_t uart_config; + CLOCK_SetLpsci0Clock(1); + LPSCI_GetDefaultConfig(&uart_config); + uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; + uart_config.enableTx = true; + uart_config.enableRx = true; + LPSCI_Init(UART_PORT, &uart_config, CLOCK_GetPllFllSelClkFreq()); + + // USB + CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk)); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + GPIO_WritePinOutput(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ +#if defined(BUTTON_PORT) && defined(BUTTON_PIN) + return BUTTON_STATE_ACTIVE == GPIO_ReadPinInput(BUTTON_PORT, BUTTON_PIN); +#endif + return 0; +} + +int board_uart_read(uint8_t* buf, int len) +{ + LPSCI_ReadBlocking(UART_PORT, buf, len); + return len; +} + +int board_uart_write(void const * buf, int len) +{ + LPSCI_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif diff --git a/hw/bsp/kinetis_kl/family.mk b/hw/bsp/kinetis_kl/family.mk new file mode 100644 index 000000000..e805d6dae --- /dev/null +++ b/hw/bsp/kinetis_kl/family.mk @@ -0,0 +1,37 @@ +SDK_DIR = hw/mcu/nxp/nxp_sdk +DEPS_SUBMODULES += $(SDK_DIR) + +MCU_DIR = $(SDK_DIR)/devices/$(MCU) +include $(TOP)/$(BOARD_PATH)/board.mk + +CFLAGS += \ + -mthumb \ + -mabi=aapcs \ + -mcpu=cortex-m0plus \ + -DCFG_TUSB_MCU=OPT_MCU_KINETIS_KL \ + +LDFLAGS += \ + -Wl,--defsym,__stack_size__=0x400 \ + -Wl,--defsym,__heap_size__=0 + +SRC_C += \ + src/portable/nxp/khci/dcd_khci.c \ + src/portable/nxp/khci/hcd_khci.c \ + $(MCU_DIR)/system_$(MCU).c \ + $(MCU_DIR)/project_template/clock_config.c \ + $(MCU_DIR)/drivers/fsl_clock.c \ + $(MCU_DIR)/drivers/fsl_gpio.c \ + $(MCU_DIR)/drivers/fsl_lpsci.c \ + $(MCU_DIR)/drivers/fsl_uart.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(SDK_DIR)/CMSIS/Include \ + $(TOP)/$(MCU_DIR) \ + $(TOP)/$(MCU_DIR)/project_template \ + $(TOP)/$(MCU_DIR)/drivers + +SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S + +# For freeRTOS port source +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 diff --git a/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld b/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld deleted file mode 100644 index f478a99c7..000000000 --- a/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld +++ /dev/null @@ -1,216 +0,0 @@ -/* -** ################################################################### -** Processors: K32L2B31VFM0A -** K32L2B31VFT0A -** K32L2B31VLH0A -** K32L2B31VMP0A -** -** Compiler: GNU C Compiler -** Reference manual: K32L2B3xRM, Rev.0, July 2019 -** Version: rev. 1.0, 2019-07-30 -** Build: b190930 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x00008000, LENGTH = 0x00000200 - m_flash_config (RX) : ORIGIN = 0x00008400, LENGTH = 0x00000010 - m_text (RX) : ORIGIN = 0x00008410, LENGTH = 0x00037BF0 - m_data (RW) : ORIGIN = 0x1FFFE000, LENGTH = 0x00008000 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - .flash_config : - { - . = ALIGN(4); - KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ - . = ALIGN(4); - } > m_flash_config - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - /* reserve MTB memory at the beginning of m_data */ - .mtb : /* MTB buffer address as defined by the hardware */ - { - . = ALIGN(8); - _mtb_start = .; - KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */ - . = ALIGN(8); - _mtb_end = .; - } > m_data - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} diff --git a/hw/bsp/kuiic/board.h b/hw/bsp/kuiic/board.h deleted file mode 100644 index 1e2d4f18b..000000000 --- a/hw/bsp/kuiic/board.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "fsl_device_registers.h" - -// LED -#define LED_PIN_CLOCK kCLOCK_PortA -#define LED_GPIO GPIOA -#define LED_PORT PORTA -#define LED_PIN 2 -#define LED_STATE_ON 1 - -// UART -#define UART_PORT LPUART1 -#define UART_PIN_RX 3u -#define UART_PIN_TX 0u - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/kuiic/board.mk b/hw/bsp/kuiic/board.mk deleted file mode 100644 index cb3459586..000000000 --- a/hw/bsp/kuiic/board.mk +++ /dev/null @@ -1,52 +0,0 @@ -SDK_DIR = hw/mcu/nxp/mcux-sdk -DEPS_SUBMODULES += $(SDK_DIR) tools/uf2 - -# This board uses TinyUF2 for updates -UF2_FAMILY_ID = 0x7f83e793 - -CFLAGS += \ - -mthumb \ - -mabi=aapcs \ - -mcpu=cortex-m0plus \ - -DCPU_K32L2B31VLH0A \ - -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX - -# mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter - -MCU_DIR = $(SDK_DIR)/devices/K32L2B31A - -# All source paths should be relative to the top level. -LD_FILE = /hw/bsp/$(BOARD)/K32L2B31xxxxA_flash.ld - -SRC_C += \ - src/portable/nxp/khci/dcd_khci.c \ - $(MCU_DIR)/system_K32L2B31A.c \ - $(MCU_DIR)/drivers/fsl_clock.c \ - $(SDK_DIR)/drivers/gpio/fsl_gpio.c \ - $(SDK_DIR)/drivers/lpuart/fsl_lpuart.c - -INC += \ - $(TOP)/hw/bsp/$(BOARD) \ - $(TOP)/$(SDK_DIR)/CMSIS/Include \ - $(TOP)/$(SDK_DIR)/drivers/smc \ - $(TOP)/$(SDK_DIR)/drivers/common \ - $(TOP)/$(SDK_DIR)/drivers/gpio \ - $(TOP)/$(SDK_DIR)/drivers/port \ - $(TOP)/$(SDK_DIR)/drivers/lpuart \ - $(TOP)/$(MCU_DIR) \ - $(TOP)/$(MCU_DIR)/drivers - -SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S - -# For freeRTOS port source -FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 - -# For flash-jlink target -JLINK_DEVICE = MKL25Z128xxx4 - -# For flash-pyocd target -PYOCD_TARGET = K32L2B - -# flash using pyocd -flash: flash-pyocd diff --git a/hw/bsp/kuiic/kuiic.c b/hw/bsp/kuiic/kuiic.c deleted file mode 100644 index 97677d47a..000000000 --- a/hw/bsp/kuiic/kuiic.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2018, hathach (tinyusb.org) - * Copyright (c) 2020, Koji Kitayama - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "../board.h" -#include "board.h" -#include "fsl_smc.h" -#include "fsl_gpio.h" -#include "fsl_port.h" -#include "fsl_clock.h" -#include "fsl_lpuart.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */ -#define SOPT5_LPUART1RXSRC_LPUART_RX 0x00u /*!<@brief LPUART1 Receive Data Source Select: LPUART_RX pin */ -#define SOPT5_LPUART1TXSRC_LPUART_TX 0x00u /*!<@brief LPUART1 Transmit Data Source Select: LPUART_TX pin */ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -// extern uint32_t SystemCoreClock; - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = { - .outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */ - .irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ - .ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock selected */ - .fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */ - .lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */ - .hircEnableInNotHircMode = true, /* HIRC source is enabled */ -}; -const sim_clock_config_t simConfig_BOARD_BootClockRUN = { - .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */ - .clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */ -}; - -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Set the system clock dividers in SIM to safe value. */ - CLOCK_SetSimSafeDivs(); - /* Set MCG to HIRC mode. */ - CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN); - /* Set the clock configuration in SIM module. */ - CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; -} - - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB0_IRQHandler(void) -{ - tud_int_handler(0); -} - -void board_init(void) -{ - /* Enable port clocks for GPIO pins */ - CLOCK_EnableClock(kCLOCK_PortA); - CLOCK_EnableClock(kCLOCK_PortB); - CLOCK_EnableClock(kCLOCK_PortC); - CLOCK_EnableClock(kCLOCK_PortD); - CLOCK_EnableClock(kCLOCK_PortE); - - - gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 1 }; - GPIO_PinInit(GPIOA, 1U, &led_config); - PORT_SetPinMux(PORTA, 1U, kPORT_MuxAsGpio); - led_config.outputLogic = 0; - GPIO_PinInit(GPIOA, 2U, &led_config); - PORT_SetPinMux(PORTA, 2U, kPORT_MuxAsGpio); - -#ifdef BUTTON_PIN - gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; - GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); - const port_pin_config_t BUTTON_CFG = { - kPORT_PullUp, - kPORT_FastSlewRate, - kPORT_PassiveFilterDisable, - kPORT_LowDriveStrength, - kPORT_MuxAsGpio - }; - PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); -#endif - - /* PORTC3 is configured as LPUART0_RX */ - PORT_SetPinMux(PORTC, 3U, kPORT_MuxAlt3); - /* PORTA2 (pin 24) is configured as LPUART0_TX */ - PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3); - - SIM->SOPT5 = ((SIM->SOPT5 & - /* Mask bits to zero which are setting */ - (~(SIM_SOPT5_LPUART1TXSRC_MASK | SIM_SOPT5_LPUART1RXSRC_MASK))) - /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */ - | SIM_SOPT5_LPUART1TXSRC(SOPT5_LPUART1TXSRC_LPUART_TX) - /* LPUART0 Receive Data Source Select: LPUART_RX pin. */ - | SIM_SOPT5_LPUART1RXSRC(SOPT5_LPUART1RXSRC_LPUART_RX)); - - BOARD_BootClockRUN(); - SystemCoreClockUpdate(); - CLOCK_SetLpuart1Clock(1); - -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); -#endif - - lpuart_config_t uart_config; - LPUART_GetDefaultConfig(&uart_config); - uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; - uart_config.enableTx = true; - uart_config.enableRx = true; - LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk)); - - // USB - CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - if (state) { - LED_GPIO->PDDR |= GPIO_FIT_REG((1UL << LED_PIN)); - } else { - LED_GPIO->PDDR &= GPIO_FIT_REG(~(1UL << LED_PIN)); - } -// GPIO_PinWrite(GPIOA, 1, state ? LED_STATE_ON : (1-LED_STATE_ON) ); -// GPIO_PinWrite(GPIOA, 2, state ? (1-LED_STATE_ON) : LED_STATE_ON ); -} - -uint32_t board_button_read(void) -{ -#ifdef BUTTON_PIN - return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); -#else - return 0; -#endif -} - -int board_uart_read(uint8_t* buf, int len) -{ - LPUART_ReadBlocking(UART_PORT, buf, len); - return len; -} - -int board_uart_write(void const * buf, int len) -{ - LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler(void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#endif diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index a94e1877f..b903abeca 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -85,7 +85,7 @@ #define TUP_DCD_ENDPOINT_MAX 8 #define TUP_RHPORT_HIGHSPEED 1 // Port0 HS, Port1 HS -#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2AXX, OPT_MCU_K32L2BXX) +#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32) #define TUP_USBIP_CHIPIDEA_FS #define TUP_USBIP_CHIPIDEA_FS_KINETIS #define TUP_DCD_ENDPOINT_MAX 16 diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index 27073dce7..6d25cd862 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -26,15 +26,14 @@ #include "tusb_option.h" -#if CFG_TUH_ENABLED && \ - ( \ - ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || \ - ( CFG_TUSB_MCU == OPT_MCU_K32L2AXX ) || \ - ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX ) \ - ) - -#include "fsl_device_registers.h" -#define KHCI USB0 +#if CFG_TUH_ENABLED && defined(TUP_USBIP_CHIPIDEA_FS) + +#ifdef TUP_USBIP_CHIPIDEA_FS_KINETIS + #include "fsl_device_registers.h" + #define KHCI USB0 +#else + #error "MCU is not supported" +#endif #include "host/hcd.h" diff --git a/src/tusb_option.h b/src/tusb_option.h index 5a234e357..c679f2f12 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -117,9 +117,11 @@ #define OPT_MCU_RP2040 1100 ///< Raspberry Pi RP2040 // NXP Kinetis -#define OPT_MCU_MKL25ZXX 1200 ///< NXP MKL25Zxx -#define OPT_MCU_K32L2BXX 1201 ///< NXP K32L2Bxx -#define OPT_MCU_K32L2AXX 1202 ///< NXP K32L2Axx +#define OPT_MCU_KINETIS_KL 1200 ///< NXP KL series +#define OPT_MCU_KINETIS_K32 1201 ///< NXP K32 series + +#define OPT_MCU_MKL25ZXX 1200 ///< Alias to KL (obsolete) +#define OPT_MCU_K32L2BXX 1201 ///< Alias to K32 (obsolete) // Silabs #define OPT_MCU_EFM32GG 1300 ///< Silabs EFM32GG -- cgit v1.3.1 From 45202187864d6dce8c4bc1a3d698e90ae98b7855 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 20 Mar 2023 11:33:39 +0700 Subject: more compatible with IAR --- src/portable/raspberrypi/rp2040/rp2040_usb.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h index 5d3d792cb..d4d29a816 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.h +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h @@ -36,8 +36,8 @@ #define __tusb_irq_path_func(x) x #endif -#define usb_hw_set ((usb_hw_t *) hw_set_alias(usb_hw)) -#define usb_hw_clear ((usb_hw_t *) hw_clear_alias(usb_hw)) +#define usb_hw_set ((usb_hw_t *) hw_set_alias_untyped(usb_hw)) +#define usb_hw_clear ((usb_hw_t *) hw_clear_alias_untyped(usb_hw)) #define pico_info(...) TU_LOG(2, __VA_ARGS__) #define pico_trace(...) TU_LOG(3, __VA_ARGS__) -- cgit v1.3.1 From e44e461ce3295f5680ea211048ade473963ba016 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 21 Mar 2023 12:54:43 +0700 Subject: add tuh_set_interface --- src/class/cdc/cdc_host.c | 6 +++--- src/class/cdc/cdc_host.h | 2 +- src/common/tusb_common.h | 6 ------ src/common/tusb_types.h | 5 +++++ src/host/usbh.c | 50 +++++++++++++++++++++++++++++++++++++++--------- src/host/usbh.h | 5 +++++ 6 files changed, 55 insertions(+), 19 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 011ee49dc..d34662cb7 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -97,7 +97,7 @@ static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr) } } - return TU_INDEX_INVALID_8; + return TUSB_INDEX_INVALID_8; } @@ -124,7 +124,7 @@ uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num) if (p_cdc->daddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i; } - return TU_INDEX_INVALID_8; + return TUSB_INDEX_INVALID_8; } bool tuh_cdc_itf_get_info(uint8_t idx, tuh_cdc_itf_info_t* info) @@ -533,7 +533,7 @@ static void process_cdc_config(tuh_xfer_t* xfer) uintptr_t const state = xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - TU_ASSERT(idx != TU_INDEX_INVALID_8, ); + TU_ASSERT(idx != TUSB_INDEX_INVALID_8, ); switch(state) { diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 4090d0e9f..03f32e542 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -80,7 +80,7 @@ typedef struct } tuh_cdc_itf_info_t; // Get Interface index from device address + interface number -// return TUSB_INDEX_INVALID (0xFF) if not found +// return TUSB_INDEX_INVALID_8 (0xFF) if not found uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num); // Get Interface information diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index faccf8726..957491aa9 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -75,12 +75,6 @@ #include "tusb_timeout.h" // TODO remove -enum -{ - TU_INDEX_INVALID_8 = 0xFFu -}; - - //--------------------------------------------------------------------+ // Optional API implemented by application if needed // TODO move to a more ovious place/file diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index d567bd482..39a2d4564 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -273,6 +273,11 @@ enum CONTROL_STAGE_ACK }; +enum +{ + TUSB_INDEX_INVALID_8 = 0xFFu +}; + //--------------------------------------------------------------------+ // USB Descriptors //--------------------------------------------------------------------+ diff --git a/src/host/usbh.c b/src/host/usbh.c index 9ccbe7557..5a14aea5f 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -195,7 +195,7 @@ enum { CONFIG_NUM = 1 }; // default to use configuration 1 // sum of end device + hub #define TOTAL_DEVICES (CFG_TUH_DEVICE_MAX + CFG_TUH_HUB) -static uint8_t _usbh_controller = TU_INDEX_INVALID_8; +static uint8_t _usbh_controller = TUSB_INDEX_INVALID_8; // Device with address = 0 for enumeration static usbh_dev0_t _dev0; @@ -303,13 +303,13 @@ tusb_speed_t tuh_speed_get (uint8_t dev_addr) static void clear_device(usbh_device_t* dev) { tu_memclr(dev, sizeof(usbh_device_t)); - memset(dev->itf2drv, TU_INDEX_INVALID_8, sizeof(dev->itf2drv)); // invalid mapping - memset(dev->ep2drv , TU_INDEX_INVALID_8, sizeof(dev->ep2drv )); // invalid mapping + memset(dev->itf2drv, TUSB_INDEX_INVALID_8, sizeof(dev->itf2drv)); // invalid mapping + memset(dev->ep2drv , TUSB_INDEX_INVALID_8, sizeof(dev->ep2drv )); // invalid mapping } bool tuh_inited(void) { - return _usbh_controller != TU_INDEX_INVALID_8; + return _usbh_controller != TUSB_INDEX_INVALID_8; } bool tuh_init(uint8_t controller_id) @@ -1033,6 +1033,38 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, return tuh_control_xfer(&xfer); } +bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + TU_LOG_USBH("Set Interface %u Alternate %u\r\n", itf_num, itf_alt); + + tusb_control_request_t const request = + { + .bmRequestType_bit = + { + .recipient = TUSB_REQ_RCPT_DEVICE, + .type = TUSB_REQ_TYPE_STANDARD, + .direction = TUSB_DIR_OUT + }, + .bRequest = TUSB_REQ_SET_INTERFACE, + .wValue = tu_htole16(itf_alt), + .wIndex = tu_htole16(itf_num), + .wLength = 0 + }; + + tuh_xfer_t xfer = + { + .daddr = daddr, + .ep_addr = 0, + .setup = &request, + .buffer = NULL, + .complete_cb = complete_cb, + .user_data = user_data + }; + + return tuh_control_xfer(&xfer); +} + //--------------------------------------------------------------------+ // Descriptor Sync //--------------------------------------------------------------------+ @@ -1358,11 +1390,11 @@ static void process_enumeration(tuh_xfer_t* xfer) dev->configured = 1; - // Start the Set Configuration process for interfaces (itf = TU_INDEX_INVALID_8) + // Start the Set Configuration process for interfaces (itf = TUSB_INDEX_INVALID_8) // Since driver can perform control transfer within its set_config, this is done asynchronously. // The process continue with next interface when class driver complete its sequence with usbh_driver_set_config_complete() - // TODO use separated API instead of using TU_INDEX_INVALID_8 - usbh_driver_set_config_complete(daddr, TU_INDEX_INVALID_8); + // TODO use separated API instead of using TUSB_INDEX_INVALID_8 + usbh_driver_set_config_complete(daddr, TUSB_INDEX_INVALID_8); } break; @@ -1562,7 +1594,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur uint8_t const itf_num = desc_itf->bInterfaceNumber+i; // Interface number must not be used already - TU_ASSERT( TU_INDEX_INVALID_8 == dev->itf2drv[itf_num] ); + TU_ASSERT( TUSB_INDEX_INVALID_8 == dev->itf2drv[itf_num] ); dev->itf2drv[itf_num] = drv_id; } @@ -1596,7 +1628,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) // IAD binding interface such as CDCs should return itf_num + 1 when complete // with usbh_driver_set_config_complete() uint8_t const drv_id = dev->itf2drv[itf_num]; - if (drv_id != TU_INDEX_INVALID_8) + if (drv_id != TUSB_INDEX_INVALID_8) { usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id]; TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num); diff --git a/src/host/usbh.h b/src/host/usbh.h index 7942de5c2..45e6356bc 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -171,6 +171,11 @@ bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep); bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +// Set Interface (control transfer) +// true on success, false if there is on-going control transfer or incorrect parameters +bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt, + tuh_xfer_cb_t complete_cb, uintptr_t user_data); + //--------------------------------------------------------------------+ // Descriptors Asynchronous (non-blocking) //--------------------------------------------------------------------+ -- cgit v1.3.1 From 42decd94e5de3a25fd7e7702da2f756b53a6c9f9 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Tue, 21 Mar 2023 07:58:39 +0100 Subject: UAC2: fix feedback EP buffer alignment. --- src/class/audio/audio_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 32ba5761e..f487fe60e 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -312,7 +312,7 @@ typedef struct #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP struct { - uint32_t value; // Feedback value for asynchronous mode (in 16.16 format). + CFG_TUSB_MEM_ALIGN uint32_t value; // Feedback value for asynchronous mode (in 16.16 format). uint32_t min_value; // min value according to UAC2 FMT-2.0 section 2.3.1.1. uint32_t max_value; // max value according to UAC2 FMT-2.0 section 2.3.1.1. -- cgit v1.3.1 From 878f2b54fe208f717677cabda57180ef8a4bc3cd Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 21 Mar 2023 18:12:55 +0700 Subject: relax hid host enumeration, allow set protocol to be stalled --- src/class/hid/hid_host.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index e5fc86267..df220d7c3 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -465,8 +465,10 @@ bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num) static void process_set_config(tuh_xfer_t* xfer) { - // Stall is a valid response for SET_IDLE, therefore we could ignore its result - if ( xfer->setup->bRequest != HID_REQ_CONTROL_SET_IDLE ) + // Stall is a valid response for SET_IDLE, sometime SET_PROTOCOL as well + // therefore we could ignore its result + if ( !(xfer->setup->bRequest == HID_REQ_CONTROL_SET_IDLE || + xfer->setup->bRequest == HID_REQ_CONTROL_SET_PROTOCOL) ) { TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, ); } -- cgit v1.3.1 From d34508a316a2b97db749651452b8e1650e854f37 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 21 Mar 2023 18:13:25 +0700 Subject: add note for blocking tuh_configuration_set(), tuh_interface_set() --- src/host/usbh.c | 20 ++++++++++++++++++-- src/host/usbh.h | 2 ++ 2 files changed, 20 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 5a14aea5f..a3335102f 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1030,7 +1030,15 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, .user_data = user_data }; - return tuh_control_xfer(&xfer); + bool ret = tuh_control_xfer(&xfer); + + // if blocking, user_data could be pointed to xfer_result + if ( !complete_cb && user_data ) + { + *((xfer_result_t*) user_data) = xfer.result; + } + + return ret; } bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt, @@ -1062,7 +1070,15 @@ bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt, .user_data = user_data }; - return tuh_control_xfer(&xfer); + bool ret = tuh_control_xfer(&xfer); + + // if blocking, user_data could be pointed to xfer_result + if ( !complete_cb && user_data ) + { + *((xfer_result_t*) user_data) = xfer.result; + } + + return ret; } //--------------------------------------------------------------------+ diff --git a/src/host/usbh.h b/src/host/usbh.h index 45e6356bc..125d8f4c9 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -168,11 +168,13 @@ bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep); // Set Configuration (control transfer) // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1 // true on success, false if there is on-going control transfer or incorrect parameters +// if complete_cb == NULL i.e blocking, user_data should be pointed to xfer_reuslt_t* bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, tuh_xfer_cb_t complete_cb, uintptr_t user_data); // Set Interface (control transfer) // true on success, false if there is on-going control transfer or incorrect parameters +// if complete_cb == NULL i.e blocking, user_data should be pointed to xfer_reuslt_t* bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -- cgit v1.3.1 From 8a0b17598c14497805addbb7c670e41c9eb5c0b7 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 21 Mar 2023 18:15:45 +0700 Subject: add osal_task_delay() for control blocking --- src/host/usbh.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index a3335102f..dc347c458 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -568,6 +568,8 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) // only need to call task if not preempted RTOS #if CFG_TUSB_OS == OPT_OS_NONE || CFG_TUSB_OS == OPT_OS_PICO tuh_task(); + #else + osal_task_delay(1); // TODO maybe yield() #endif // TODO probably some timeout to prevent hanged -- cgit v1.3.1 From d22fc550c76f0d2c5d980a253161e95f1a853309 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 21 Mar 2023 21:04:06 +0700 Subject: change meaning of CFG_TUH_HID to total number of HID interfaces supported. - previously CFG_TUH_HID is max number of interfaces per device which is rather limited and consume more resources than needed. - change hid host instance in API to index --- .../dual/host_hid_to_device_cdc/src/tusb_config.h | 2 +- examples/host/cdc_msc_hid/src/tusb_config.h | 4 +- examples/host/hid_controller/src/tusb_config.h | 2 +- src/class/hid/hid_host.c | 353 +++++++++++---------- src/class/hid/hid_host.h | 44 ++- 5 files changed, 217 insertions(+), 188 deletions(-) (limited to 'src') diff --git a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h index f749bd712..72ec8d654 100644 --- a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h +++ b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h @@ -132,7 +132,7 @@ // max device support (excluding hub device) #define CFG_TUH_DEVICE_MAX (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports -#define CFG_TUH_HID 4 +#define CFG_TUH_HID (4*CFG_TUH_DEVICE_MAX) #define CFG_TUH_HID_EPIN_BUFSIZE 64 #define CFG_TUH_HID_EPOUT_BUFSIZE 64 diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index 4b50f2096..a0a740c6e 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -36,7 +36,7 @@ #if CFG_TUSB_MCU == OPT_MCU_RP2040 // change to 1 if using pico-pio-usb as host controller for raspberry rp2040 -#define CFG_TUH_RPI_PIO_USB 0 +#define CFG_TUH_RPI_PIO_USB 1 #define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_USB #endif @@ -97,7 +97,7 @@ #define CFG_TUH_HUB 1 // number of supported hubs #define CFG_TUH_CDC 1 -#define CFG_TUH_HID 4 // typical keyboard + mouse device can have 3-4 HID interfaces +#define CFG_TUH_HID (4*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces #define CFG_TUH_MSC 1 #define CFG_TUH_VENDOR 0 diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h index 2e0dd0dbe..f4ddc1b81 100644 --- a/examples/host/hid_controller/src/tusb_config.h +++ b/examples/host/hid_controller/src/tusb_config.h @@ -97,7 +97,7 @@ #define CFG_TUH_HUB 0 #define CFG_TUH_CDC 0 -#define CFG_TUH_HID 4 // typical keyboard + mouse device can have 3-4 HID interfaces +#define CFG_TUH_HID (4*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces #define CFG_TUH_MSC 0 #define CFG_TUH_VENDOR 0 diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index df220d7c3..f65b2dc20 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -39,6 +39,8 @@ typedef struct { + uint8_t daddr; + uint8_t itf_num; uint8_t ep_in; uint8_t ep_out; @@ -56,74 +58,131 @@ typedef struct uint8_t epout_buf[CFG_TUH_HID_EPOUT_BUFSIZE]; } hidh_interface_t; -typedef struct +CFG_TUSB_MEM_SECTION +tu_static hidh_interface_t _hidh_itf[CFG_TUH_HID]; + +//--------------------------------------------------------------------+ +// Helper +//--------------------------------------------------------------------+ + +TU_ATTR_ALWAYS_INLINE static inline +hidh_interface_t* get_hid_itf(uint8_t daddr, uint8_t idx) { - uint8_t inst_count; - hidh_interface_t instances[CFG_TUH_HID]; -} hidh_device_t; + TU_ASSERT(daddr && idx < CFG_TUH_HID, NULL); + hidh_interface_t* p_hid = &_hidh_itf[idx]; + return (p_hid->daddr == daddr) ? p_hid : NULL; +} -CFG_TUSB_MEM_SECTION -static hidh_device_t _hidh_dev[CFG_TUH_DEVICE_MAX]; +// Get instance ID by endpoint address +static uint8_t get_idx_by_epaddr(uint8_t daddr, uint8_t ep_addr) +{ + for ( uint8_t idx = 0; idx < CFG_TUH_HID; idx++ ) + { + hidh_interface_t const * p_hid = &_hidh_itf[idx]; + + if ( p_hid->daddr == daddr && + (p_hid->ep_in == ep_addr || p_hid->ep_out == ep_addr) ) + { + return idx; + } + } -//------------- Internal prototypes -------------// + return TUSB_INDEX_INVALID_8; +} + +static hidh_interface_t* find_new_itf(void) +{ + for(uint8_t i=0; iinst_count; + hidh_interface_t* p_hid = get_hid_itf(daddr, idx); + return p_hid != NULL; } -bool tuh_hid_mounted(uint8_t dev_addr, uint8_t instance) +uint8_t tuh_hid_itf_get_index(uint8_t daddr, uint8_t itf_num) { - hidh_interface_t* hid_itf = get_instance(dev_addr, instance); - return (hid_itf->ep_in != 0) || (hid_itf->ep_out != 0); + for ( uint8_t idx = 0; idx < CFG_TUH_HID; idx++ ) + { + hidh_interface_t const * p_hid = &_hidh_itf[idx]; + + if ( p_hid->daddr == daddr && p_hid->itf_num == itf_num) return idx; + } + + return TUSB_INDEX_INVALID_8; } -uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t instance) +uint8_t tuh_hid_interface_protocol(uint8_t daddr, uint8_t idx) { - hidh_interface_t* hid_itf = get_instance(dev_addr, instance); - return hid_itf->itf_protocol; + hidh_interface_t* p_hid = get_hid_itf(daddr, idx); + return p_hid ? p_hid->itf_protocol : 0; } //--------------------------------------------------------------------+ // Control Endpoint API //--------------------------------------------------------------------+ -uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance) +uint8_t tuh_hid_get_protocol(uint8_t daddr, uint8_t idx) { - hidh_interface_t* hid_itf = get_instance(dev_addr, instance); - return hid_itf->protocol_mode; + hidh_interface_t* p_hid = get_hid_itf(daddr, idx); + return p_hid ? p_hid->protocol_mode : 0; } static void set_protocol_complete(tuh_xfer_t* xfer) { - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t const daddr = xfer->daddr; - uint8_t const instance = get_instance_id_by_itfnum(daddr, itf_num); - hidh_interface_t* hid_itf = get_instance(daddr, instance); + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + uint8_t const daddr = xfer->daddr; + uint8_t const idx = tuh_hid_itf_get_index(daddr, itf_num); + + hidh_interface_t* p_hid = get_hid_itf(daddr, idx); + TU_VERIFY(p_hid, ); if (XFER_RESULT_SUCCESS == xfer->result) { - hid_itf->protocol_mode = (uint8_t) tu_le16toh(xfer->setup->wValue); + p_hid->protocol_mode = (uint8_t) tu_le16toh(xfer->setup->wValue); } if (tuh_hid_set_protocol_complete_cb) { - tuh_hid_set_protocol_complete_cb(daddr, instance, hid_itf->protocol_mode); + tuh_hid_set_protocol_complete_cb(daddr, idx, p_hid->protocol_mode); } } - -static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protocol, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +static bool _hidh_set_protocol(uint8_t daddr, uint8_t itf_num, uint8_t protocol, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG2("HID Set Protocol = %d\r\n", protocol); @@ -143,7 +202,7 @@ static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protoc tuh_xfer_t xfer = { - .daddr = dev_addr, + .daddr = daddr, .ep_addr = 0, .setup = &request, .buffer = NULL, @@ -151,16 +210,15 @@ static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protoc .user_data = user_data }; - TU_ASSERT( tuh_control_xfer(&xfer) ); - return true; + return tuh_control_xfer(&xfer); } -bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol) +bool tuh_hid_set_protocol(uint8_t daddr, uint8_t idx, uint8_t protocol) { - hidh_interface_t* hid_itf = get_instance(dev_addr, instance); - TU_VERIFY(hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE); + hidh_interface_t* p_hid = get_hid_itf(daddr, idx); + TU_VERIFY(p_hid && p_hid->itf_protocol != HID_ITF_PROTOCOL_NONE); - return _hidh_set_protocol(dev_addr, hid_itf->itf_num, protocol, set_protocol_complete, 0); + return _hidh_set_protocol(daddr, p_hid->itf_num, protocol, set_protocol_complete, 0); } static void set_report_complete(tuh_xfer_t* xfer) @@ -169,20 +227,22 @@ static void set_report_complete(tuh_xfer_t* xfer) if (tuh_hid_set_report_complete_cb) { - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t const instance = get_instance_id_by_itfnum(xfer->daddr, itf_num); + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + uint8_t const idx = tuh_hid_itf_get_index(xfer->daddr, itf_num); uint8_t const report_type = tu_u16_high(xfer->setup->wValue); uint8_t const report_id = tu_u16_low(xfer->setup->wValue); - tuh_hid_set_report_complete_cb(xfer->daddr, instance, report_id, report_type, + tuh_hid_set_report_complete_cb(xfer->daddr, idx, report_id, report_type, (xfer->result == XFER_RESULT_SUCCESS) ? xfer->setup->wLength : 0); } } -bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t report_type, void* report, uint16_t len) +bool tuh_hid_set_report(uint8_t daddr, uint8_t idx, uint8_t report_id, uint8_t report_type, void* report, uint16_t len) { - hidh_interface_t* hid_itf = get_instance(dev_addr, instance); + hidh_interface_t* p_hid = get_hid_itf(daddr, idx); + TU_VERIFY(p_hid); + TU_LOG2("HID Set Report: id = %u, type = %u, len = %u\r\n", report_id, report_type, len); tusb_control_request_t const request = @@ -194,14 +254,14 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, u .direction = TUSB_DIR_OUT }, .bRequest = HID_REQ_CONTROL_SET_REPORT, - .wValue = tu_u16(report_type, report_id), - .wIndex = hid_itf->itf_num, + .wValue = tu_htole16(tu_u16(report_type, report_id)), + .wIndex = tu_htole16((uint16_t)p_hid->itf_num), .wLength = len }; tuh_xfer_t xfer = { - .daddr = dev_addr, + .daddr = daddr, .ep_addr = 0, .setup = &request, .buffer = report, @@ -209,14 +269,14 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, u .user_data = 0 }; - TU_ASSERT( tuh_control_xfer(&xfer) ); - return true; + return tuh_control_xfer(&xfer); } -static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +static bool _hidh_set_idle(uint8_t daddr, uint8_t itf_num, uint16_t idle_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // SET IDLE request, device can stall if not support this request TU_LOG2("HID Set Idle \r\n"); + tusb_control_request_t const request = { .bmRequestType_bit = @@ -226,14 +286,14 @@ static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate .direction = TUSB_DIR_OUT }, .bRequest = HID_REQ_CONTROL_SET_IDLE, - .wValue = idle_rate, - .wIndex = itf_num, + .wValue = tu_htole16(idle_rate), + .wIndex = tu_htole16((uint16_t)itf_num), .wLength = 0 }; tuh_xfer_t xfer = { - .daddr = dev_addr, + .daddr = daddr, .ep_addr = 0, .setup = &request, .buffer = NULL, @@ -241,25 +301,24 @@ static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate .user_data = user_data }; - TU_ASSERT( tuh_control_xfer(&xfer) ); - - return true; + return tuh_control_xfer(&xfer); } //--------------------------------------------------------------------+ // Interrupt Endpoint API //--------------------------------------------------------------------+ -bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance) +bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx) { - hidh_interface_t* hid_itf = get_instance(dev_addr, instance); + hidh_interface_t* p_hid = get_hid_itf(daddr, idx); + TU_VERIFY(p_hid); // claim endpoint - TU_VERIFY( usbh_edpt_claim(dev_addr, hid_itf->ep_in) ); + TU_VERIFY( usbh_edpt_claim(daddr, p_hid->ep_in) ); - if ( !usbh_edpt_xfer(dev_addr, hid_itf->ep_in, hid_itf->epin_buf, hid_itf->epin_size) ) + if ( !usbh_edpt_xfer(daddr, p_hid->ep_in, p_hid->epin_buf, p_hid->epin_size) ) { - usbh_edpt_release(dev_addr, hid_itf->ep_in); + usbh_edpt_release(daddr, p_hid->ep_in); return false; } @@ -274,44 +333,45 @@ bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance) // return !usbh_edpt_busy(dev_addr, hid_itf->ep_in); //} -bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, const void* report, uint16_t len) +bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len) { TU_LOG2("HID Send Report %d\r\n", report_id); - hidh_interface_t* hid_itf = get_instance(dev_addr, instance); + hidh_interface_t* p_hid = get_hid_itf(daddr, idx); + TU_VERIFY(p_hid); - if (hid_itf->ep_out == 0) + if (p_hid->ep_out == 0) { // This HID does not have an out endpoint (other than control) return false; } - else if (len > CFG_TUH_HID_EPOUT_BUFSIZE - || (report_id != 0 && len > (CFG_TUH_HID_EPOUT_BUFSIZE - 1))) + else if (len > CFG_TUH_HID_EPOUT_BUFSIZE || + (report_id != 0 && len > (CFG_TUH_HID_EPOUT_BUFSIZE - 1))) { // ep_out buffer is not large enough to hold contents return false; } // claim endpoint - TU_VERIFY( usbh_edpt_claim(dev_addr, hid_itf->ep_out) ); + TU_VERIFY( usbh_edpt_claim(daddr, p_hid->ep_out) ); if (report_id == 0) { // No report ID in transmission - memcpy(&hid_itf->epout_buf[0], report, len); + memcpy(&p_hid->epout_buf[0], report, len); } else { - hid_itf->epout_buf[0] = report_id; - memcpy(&hid_itf->epout_buf[1], report, len); + p_hid->epout_buf[0] = report_id; + memcpy(&p_hid->epout_buf[1], report, len); ++len; // 1 more byte for report_id } - TU_LOG3_MEM(hid_itf->epout_buf, len, 2); + TU_LOG3_MEM(p_hid->epout_buf, len, 2); - if ( !usbh_edpt_xfer(dev_addr, hid_itf->ep_out, hid_itf->epout_buf, len) ) + if ( !usbh_edpt_xfer(daddr, p_hid->ep_out, p_hid->epout_buf, len) ) { - usbh_edpt_release(dev_addr, hid_itf->ep_out); + usbh_edpt_release(daddr, p_hid->ep_out); return false; } @@ -323,56 +383,57 @@ bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, //--------------------------------------------------------------------+ void hidh_init(void) { - tu_memclr(_hidh_dev, sizeof(_hidh_dev)); + tu_memclr(_hidh_itf, sizeof(_hidh_itf)); } -bool hidh_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) +bool hidh_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { (void) result; uint8_t const dir = tu_edpt_dir(ep_addr); - uint8_t const instance = get_instance_id_by_epaddr(dev_addr, ep_addr); - hidh_interface_t* hid_itf = get_instance(dev_addr, instance); + uint8_t const idx = get_idx_by_epaddr(daddr, ep_addr); + + hidh_interface_t* p_hid = get_hid_itf(daddr, idx); + TU_VERIFY(p_hid); if ( dir == TUSB_DIR_IN ) { - TU_LOG2(" Get Report callback (%u, %u)\r\n", dev_addr, instance); - TU_LOG3_MEM(hid_itf->epin_buf, xferred_bytes, 2); - tuh_hid_report_received_cb(dev_addr, instance, hid_itf->epin_buf, (uint16_t) xferred_bytes); + TU_LOG2(" Get Report callback (%u, %u)\r\n", daddr, idx); + TU_LOG3_MEM(p_hid->epin_buf, xferred_bytes, 2); + tuh_hid_report_received_cb(daddr, idx, p_hid->epin_buf, (uint16_t) xferred_bytes); }else { - if (tuh_hid_report_sent_cb) tuh_hid_report_sent_cb(dev_addr, instance, hid_itf->epout_buf, (uint16_t) xferred_bytes); + if (tuh_hid_report_sent_cb) tuh_hid_report_sent_cb(daddr, idx, p_hid->epout_buf, (uint16_t) xferred_bytes); } return true; } -void hidh_close(uint8_t dev_addr) +void hidh_close(uint8_t daddr) { - TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, ); - - hidh_device_t* hid_dev = get_dev(dev_addr); - - if (tuh_hid_umount_cb) + for(uint8_t i=0; iinst_count; inst++ ) tuh_hid_umount_cb(dev_addr, inst); + hidh_interface_t* p_hid = &_hidh_itf[i]; + if (p_hid->daddr == daddr) + { + if(tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i); + p_hid->daddr = 0; + } } - - tu_memclr(hid_dev, sizeof(hidh_device_t)); } //--------------------------------------------------------------------+ // Enumeration //--------------------------------------------------------------------+ -bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len) +bool hidh_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len) { (void) rhport; (void) max_len; TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass); - TU_LOG2("[%u] HID opening Interface %u\r\n", dev_addr, desc_itf->bInterfaceNumber); + TU_LOG2("[%u] HID opening Interface %u\r\n", daddr, desc_itf->bInterfaceNumber); // len = interface + hid + n*endpoints uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + @@ -386,12 +447,9 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de tusb_hid_descriptor_hid_t const *desc_hid = (tusb_hid_descriptor_hid_t const *) p_desc; TU_ASSERT(HID_DESC_TYPE_HID == desc_hid->bDescriptorType); - // not enough interface, try to increase CFG_TUH_HID - // TODO multiple devices - hidh_device_t* hid_dev = get_dev(dev_addr); - TU_ASSERT(hid_dev->inst_count < CFG_TUH_HID, 0); - - hidh_interface_t* hid_itf = get_instance(dev_addr, hid_dev->inst_count); + hidh_interface_t* p_hid = find_new_itf(); + TU_ASSERT(p_hid); // not enough interface, try to increase CFG_TUH_HID + p_hid->daddr = daddr; //------------- Endpoint Descriptors -------------// p_desc = tu_desc_next(p_desc); @@ -400,34 +458,35 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de for(int i = 0; i < desc_itf->bNumEndpoints; i++) { TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType); - TU_ASSERT( tuh_edpt_open(dev_addr, desc_ep) ); + TU_ASSERT( tuh_edpt_open(daddr, desc_ep) ); if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { - hid_itf->ep_in = desc_ep->bEndpointAddress; - hid_itf->epin_size = tu_edpt_packet_size(desc_ep); + p_hid->ep_in = desc_ep->bEndpointAddress; + p_hid->epin_size = tu_edpt_packet_size(desc_ep); } else { - hid_itf->ep_out = desc_ep->bEndpointAddress; - hid_itf->epout_size = tu_edpt_packet_size(desc_ep); + p_hid->ep_out = desc_ep->bEndpointAddress; + p_hid->epout_size = tu_edpt_packet_size(desc_ep); } p_desc = tu_desc_next(p_desc); desc_ep = (tusb_desc_endpoint_t const *) p_desc; } - hid_dev->inst_count++; - - hid_itf->itf_num = desc_itf->bInterfaceNumber; + p_hid->itf_num = desc_itf->bInterfaceNumber; // Assume bNumDescriptors = 1 - hid_itf->report_desc_type = desc_hid->bReportType; - hid_itf->report_desc_len = tu_unaligned_read16(&desc_hid->wReportLength); + p_hid->report_desc_type = desc_hid->bReportType; + p_hid->report_desc_len = tu_unaligned_read16(&desc_hid->wReportLength); // Per HID Specs: default is Report protocol, though we will force Boot protocol when set_config - hid_itf->protocol_mode = HID_PROTOCOL_BOOT; - if ( HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass ) hid_itf->itf_protocol = desc_itf->bInterfaceProtocol; + p_hid->protocol_mode = HID_PROTOCOL_BOOT; + if ( HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass ) + { + p_hid->itf_protocol = desc_itf->bInterfaceProtocol; + } return true; } @@ -443,16 +502,16 @@ enum { CONFIG_COMPLETE }; -static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len); +static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t const* desc_report, uint16_t desc_len); static void process_set_config(tuh_xfer_t* xfer); -bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num) +bool hidh_set_config(uint8_t daddr, uint8_t itf_num) { tusb_control_request_t request; request.wIndex = tu_htole16((uint16_t) itf_num); tuh_xfer_t xfer; - xfer.daddr = dev_addr; + xfer.daddr = daddr; xfer.result = XFER_RESULT_SUCCESS; xfer.setup = &request; xfer.user_data = CONFG_SET_IDLE; @@ -477,8 +536,9 @@ static void process_set_config(tuh_xfer_t* xfer) uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t const daddr = xfer->daddr; - uint8_t const instance = get_instance_id_by_itfnum(daddr, itf_num); - hidh_interface_t* hid_itf = get_instance(daddr, instance); + uint8_t const idx = tuh_hid_itf_get_index(daddr, itf_num); + hidh_interface_t* p_hid = get_hid_itf(daddr, idx); + TU_VERIFY(p_hid, ); switch(state) { @@ -486,27 +546,27 @@ static void process_set_config(tuh_xfer_t* xfer) { // Idle rate = 0 mean only report when there is changes const uint16_t idle_rate = 0; - const uintptr_t next_state = (hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE) ? CONFIG_SET_PROTOCOL : CONFIG_GET_REPORT_DESC; + const uintptr_t next_state = (p_hid->itf_protocol != HID_ITF_PROTOCOL_NONE) ? CONFIG_SET_PROTOCOL : CONFIG_GET_REPORT_DESC; _hidh_set_idle(daddr, itf_num, idle_rate, process_set_config, next_state); } break; case CONFIG_SET_PROTOCOL: - _hidh_set_protocol(daddr, hid_itf->itf_num, HID_PROTOCOL_BOOT, process_set_config, CONFIG_GET_REPORT_DESC); + _hidh_set_protocol(daddr, p_hid->itf_num, HID_PROTOCOL_BOOT, process_set_config, CONFIG_GET_REPORT_DESC); break; case CONFIG_GET_REPORT_DESC: // Get Report Descriptor if possible // using usbh enumeration buffer since report descriptor can be very long - if( hid_itf->report_desc_len > CFG_TUH_ENUMERATION_BUFSIZE ) + if( p_hid->report_desc_len > CFG_TUH_ENUMERATION_BUFSIZE ) { - TU_LOG2("HID Skip Report Descriptor since it is too large %u bytes\r\n", hid_itf->report_desc_len); + TU_LOG2("HID Skip Report Descriptor since it is too large %u bytes\r\n", p_hid->report_desc_len); // Driver is mounted without report descriptor - config_driver_mount_complete(daddr, instance, NULL, 0); + config_driver_mount_complete(daddr, idx, NULL, 0); }else { - tuh_descriptor_get_hid_report(daddr, itf_num, hid_itf->report_desc_type, 0, usbh_get_enum_buf(), hid_itf->report_desc_len, process_set_config, CONFIG_COMPLETE); + tuh_descriptor_get_hid_report(daddr, itf_num, p_hid->report_desc_type, 0, usbh_get_enum_buf(), p_hid->report_desc_len, process_set_config, CONFIG_COMPLETE); } break; @@ -515,7 +575,7 @@ static void process_set_config(tuh_xfer_t* xfer) uint8_t const* desc_report = usbh_get_enum_buf(); uint16_t const desc_len = tu_le16toh(xfer->setup->wLength); - config_driver_mount_complete(daddr, instance, desc_report, desc_len); + config_driver_mount_complete(daddr, idx, desc_report, desc_len); } break; @@ -523,15 +583,16 @@ static void process_set_config(tuh_xfer_t* xfer) } } -static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len) +static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t const* desc_report, uint16_t desc_len) { - hidh_interface_t* hid_itf = get_instance(dev_addr, instance); + hidh_interface_t* p_hid = get_hid_itf(daddr, idx); + TU_VERIFY(p_hid, ); // enumeration is complete - tuh_hid_mount_cb(dev_addr, instance, desc_report, desc_len); + if (tuh_hid_mount_cb) tuh_hid_mount_cb(daddr, idx, desc_report, desc_len); // notify usbh that driver enumeration is complete - usbh_driver_set_config_complete(dev_addr, hid_itf->itf_num); + usbh_driver_set_config_complete(daddr, p_hid->itf_num); } //--------------------------------------------------------------------+ @@ -676,46 +737,4 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr, return report_num; } -//--------------------------------------------------------------------+ -// Helper -//--------------------------------------------------------------------+ - -// Get Device by address -TU_ATTR_ALWAYS_INLINE static inline hidh_device_t* get_dev(uint8_t dev_addr) -{ - return &_hidh_dev[dev_addr-1]; -} - -// Get Interface by instance number -TU_ATTR_ALWAYS_INLINE static inline hidh_interface_t* get_instance(uint8_t dev_addr, uint8_t instance) -{ - return &_hidh_dev[dev_addr-1].instances[instance]; -} - -// Get instance ID by interface number -static uint8_t get_instance_id_by_itfnum(uint8_t dev_addr, uint8_t itf) -{ - for ( uint8_t inst = 0; inst < CFG_TUH_HID; inst++ ) - { - hidh_interface_t *hid = get_instance(dev_addr, inst); - - if ( (hid->itf_num == itf) && (hid->ep_in || hid->ep_out) ) return inst; - } - - return 0xff; -} - -// Get instance ID by endpoint address -static uint8_t get_instance_id_by_epaddr(uint8_t dev_addr, uint8_t ep_addr) -{ - for ( uint8_t inst = 0; inst < CFG_TUH_HID; inst++ ) - { - hidh_interface_t *hid = get_instance(dev_addr, inst); - - if ( (ep_addr == hid->ep_in) || ( ep_addr == hid->ep_out) ) return inst; - } - - return 0xff; -} - #endif diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h index c152e527a..f808f36d4 100644 --- a/src/class/hid/hid_host.h +++ b/src/class/hid/hid_host.h @@ -62,14 +62,24 @@ typedef struct // Interface API //--------------------------------------------------------------------+ -// Get the number of HID instances -uint8_t tuh_hid_instance_count(uint8_t dev_addr); +// Get the number of mounted HID interfaces of a device +uint8_t tuh_hid_itf_get_count(uint8_t dev_addr); -// Check if HID instance is mounted -bool tuh_hid_mounted(uint8_t dev_addr, uint8_t instance); +// Get all mounted interfaces across devices +uint8_t tuh_hid_itf_get_total_count(void); + +// backward compatible rename +#define tuh_hid_instance_count tuh_hid_itf_get_count + +// Check if HID interface is mounted +bool tuh_hid_mounted(uint8_t dev_addr, uint8_t idx); + +// Get Interface index from device address + interface number +// return TUSB_INDEX_INVALID_8 (0xFF) if not found +uint8_t tuh_hid_itf_get_index(uint8_t daddr, uint8_t itf_num); // Get interface supported protocol (bInterfaceProtocol) check out hid_interface_protocol_enum_t for possible values -uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t instance); +uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t idx); // Parse report descriptor into array of report_info struct and return number of reports. // For complicated report, application should write its own parser. @@ -82,31 +92,31 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr, // Get current protocol: HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1) // Note: Device will be initialized in Boot protocol for simplicity. // Application can use set_protocol() to switch back to Report protocol. -uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance); +uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t idx); // Set protocol to HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1) // This function is only supported by Boot interface (tuh_n_hid_interface_protocol() != NONE) -bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol); +bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t idx, uint8_t protocol); // Set Report using control endpoint // report_type is either Input, Output or Feature, (value from hid_report_type_t) -bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t report_type, void* report, uint16_t len); +bool tuh_hid_set_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type, void* report, uint16_t len); //--------------------------------------------------------------------+ // Interrupt Endpoint API //--------------------------------------------------------------------+ // Check if the interface is ready to use -//bool tuh_n_hid_n_ready(uint8_t dev_addr, uint8_t instance); +//bool tuh_n_hid_n_ready(uint8_t dev_addr, uint8_t idx); // Try to receive next report on Interrupt Endpoint. Immediately return // - true If succeeded, tuh_hid_report_received_cb() callback will be invoked when report is available // - false if failed to queue the transfer e.g endpoint is busy -bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance); +bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t idx); // Send report using interrupt endpoint // If report_id > 0 (composite), it will be sent as 1st byte, then report contents. Otherwise only report content is sent. -bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, const void* report, uint16_t len); +bool tuh_hid_send_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len); //--------------------------------------------------------------------+ // Callbacks (Weak is optional) @@ -117,24 +127,24 @@ bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, // can be used to parse common/simple enough descriptor. // Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped // therefore report_desc = NULL, desc_len = 0 -void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report_desc, uint16_t desc_len); +TU_ATTR_WEAK void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t idx, uint8_t const* report_desc, uint16_t desc_len); // Invoked when device with hid interface is un-mounted -TU_ATTR_WEAK void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance); +TU_ATTR_WEAK void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t idx); // Invoked when received report from device via interrupt endpoint // Note: if there is report ID (composite), it is 1st byte of report -void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len); +void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t idx, uint8_t const* report, uint16_t len); // Invoked when sent report to device successfully via interrupt endpoint -TU_ATTR_WEAK void tuh_hid_report_sent_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len); +TU_ATTR_WEAK void tuh_hid_report_sent_cb(uint8_t dev_addr, uint8_t idx, uint8_t const* report, uint16_t len); // Invoked when Sent Report to device via either control endpoint // len = 0 indicate there is error in the transfer e.g stalled response -TU_ATTR_WEAK void tuh_hid_set_report_complete_cb(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t report_type, uint16_t len); +TU_ATTR_WEAK void tuh_hid_set_report_complete_cb(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type, uint16_t len); // Invoked when Set Protocol request is complete -TU_ATTR_WEAK void tuh_hid_set_protocol_complete_cb(uint8_t dev_addr, uint8_t instance, uint8_t protocol); +TU_ATTR_WEAK void tuh_hid_set_protocol_complete_cb(uint8_t dev_addr, uint8_t idx, uint8_t protocol); //--------------------------------------------------------------------+ // Internal Class Driver API -- cgit v1.3.1 From 0921edaf5924d498e8115815dc23acfb1decb7a0 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Mar 2023 09:23:11 +0700 Subject: use tud_inited() instead of tusb_inited() --- src/device/usbd.c | 4 ++-- test/unit-test/test/device/msc/test_msc_device.c | 2 +- test/unit-test/test/device/usbd/test_usbd.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index 0fb236a88..cee56af60 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -450,7 +450,7 @@ static void usbd_reset(uint8_t rhport) bool tud_task_event_ready(void) { // Skip if stack is not initialized - if ( !tusb_inited() ) return false; + if ( !tud_inited() ) return false; return !osal_queue_empty(_usbd_q); } @@ -478,7 +478,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) (void) in_isr; // not implemented yet // Skip if stack is not initialized - if ( !tusb_inited() ) return; + if ( !tud_inited() ) return; // Loop until there is no more events in the queue while (1) diff --git a/test/unit-test/test/device/msc/test_msc_device.c b/test/unit-test/test/device/msc/test_msc_device.c index c757cdcfa..a62418524 100644 --- a/test/unit-test/test/device/msc/test_msc_device.c +++ b/test/unit-test/test/device/msc/test_msc_device.c @@ -197,7 +197,7 @@ void setUp(void) dcd_int_disable_Ignore(); dcd_int_enable_Ignore(); - if ( !tusb_inited() ) + if ( !tud_inited() ) { dcd_init_Expect(rhport); tusb_init(); diff --git a/test/unit-test/test/device/usbd/test_usbd.c b/test/unit-test/test/device/usbd/test_usbd.c index dcded605a..00950c5a9 100644 --- a/test/unit-test/test/device/usbd/test_usbd.c +++ b/test/unit-test/test/device/usbd/test_usbd.c @@ -124,7 +124,7 @@ void setUp(void) dcd_int_disable_Ignore(); dcd_int_enable_Ignore(); - if ( !tusb_inited() ) + if ( !tud_inited() ) { mscd_init_Expect(); dcd_init_Expect(rhport); -- cgit v1.3.1 From f8a5cde3c7fde62c3d6bd379fea6eaa9a629ded6 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Mar 2023 09:23:44 +0700 Subject: add tuh_task_event_ready(), better implement blocking control transfer for rtos --- src/host/usbh.c | 22 +++++++++++++++------- src/host/usbh.h | 10 ++++++++++ 2 files changed, 25 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index dc347c458..3eff0830a 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -360,6 +360,14 @@ bool tuh_init(uint8_t controller_id) return true; } +bool tuh_task_event_ready(void) +{ + // Skip if stack is not initialized + if ( !tuh_inited() ) return false; + + return !osal_queue_empty(_usbh_q); +} + /* USB Host Driver task * This top level thread manages all host controller event and delegates events to class-specific drivers. * This should be called periodically within the mainloop or rtos thread. @@ -383,7 +391,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) (void) in_isr; // not implemented yet // Skip if stack is not initialized - if ( !tusb_inited() ) return; + if ( !tuh_inited() ) return; // Loop until there is no more events in the queue while (1) @@ -565,12 +573,12 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) while (result == XFER_RESULT_INVALID) { - // only need to call task if not preempted RTOS - #if CFG_TUSB_OS == OPT_OS_NONE || CFG_TUSB_OS == OPT_OS_PICO - tuh_task(); - #else - osal_task_delay(1); // TODO maybe yield() - #endif + // Note: this can be called within an callback ie. part of tuh_task() + // therefore event with RTOS tuh_task() still need to be invoked + if (tuh_task_event_ready()) + { + tuh_task(); + } // TODO probably some timeout to prevent hanged } diff --git a/src/host/usbh.h b/src/host/usbh.h index 125d8f4c9..0f969a46a 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -69,6 +69,13 @@ struct tuh_xfer_s // uint32_t timeout_ms; // place holder, not supported yet }; +// Subject to change +typedef struct +{ + uint8_t daddr; + tusb_desc_interface_t desc; +} tuh_itf_info_t; + // ConfigID for tuh_config() enum { @@ -118,6 +125,9 @@ void tuh_task(void) tuh_task_ext(UINT32_MAX, false); } +// Check if there is pending events need processing by tuh_task() +bool tuh_task_event_ready(void); + #ifndef _TUSB_HCD_H_ extern void hcd_int_handler(uint8_t rhport); #endif -- cgit v1.3.1 From f27486e19abcc020c93c0c938c71e3692c21b9f5 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Mar 2023 10:00:42 +0700 Subject: add tuh_hid_itf_get_info() and change tuh_cdc_itf_get_info() to use new tuh_itf_info_t --- .pre-commit-config.yaml | 2 +- examples/host/cdc_msc_hid/src/cdc_app.c | 8 ++++---- src/class/cdc/cdc_host.c | 20 +++++++++++++++----- src/class/cdc/cdc_host.h | 10 +--------- src/class/hid/hid_host.c | 23 +++++++++++++++++++++++ src/class/hid/hid_host.h | 7 +++++-- tools/build_family.py | 4 ++-- tools/get_deps.py | 8 +++++++- 8 files changed, 58 insertions(+), 24 deletions(-) (limited to 'src') diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 7fa6f52ee..d37c27d40 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -15,7 +15,7 @@ repos: rev: v2.2.4 hooks: - id: codespell - #args: [-w] + args: [-w] exclude: ^lib/ - repo: local diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c index b1b137e0e..7769d109e 100644 --- a/examples/host/cdc_msc_hid/src/cdc_app.c +++ b/examples/host/cdc_msc_hid/src/cdc_app.c @@ -87,10 +87,10 @@ void tuh_cdc_rx_cb(uint8_t idx) void tuh_cdc_mount_cb(uint8_t idx) { - tuh_cdc_itf_info_t itf_info = { 0 }; + tuh_itf_info_t itf_info = { 0 }; tuh_cdc_itf_get_info(idx, &itf_info); - printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber); + printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber); #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration @@ -106,8 +106,8 @@ void tuh_cdc_mount_cb(uint8_t idx) void tuh_cdc_umount_cb(uint8_t idx) { - tuh_cdc_itf_info_t itf_info = { 0 }; + tuh_itf_info_t itf_info = { 0 }; tuh_cdc_itf_get_info(idx, &itf_info); - printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber); + printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber); } diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index d34662cb7..fee314823 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -127,15 +127,25 @@ uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num) return TUSB_INDEX_INVALID_8; } -bool tuh_cdc_itf_get_info(uint8_t idx, tuh_cdc_itf_info_t* info) +bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && info); - info->daddr = p_cdc->daddr; - info->bInterfaceNumber = p_cdc->bInterfaceNumber; - info->bInterfaceSubClass = p_cdc->bInterfaceSubClass; - info->bInterfaceProtocol = p_cdc->bInterfaceProtocol; + info->daddr = p_cdc->daddr; + + // re-construct descriptor + tusb_desc_interface_t* desc = &info->desc; + desc->bLength = sizeof(tusb_desc_interface_t); + desc->bDescriptorType = TUSB_DESC_INTERFACE; + + desc->bInterfaceNumber = p_cdc->bInterfaceNumber; + desc->bAlternateSetting = 0; + desc->bNumEndpoints = 2u + (p_cdc->ep_notif ? 1u : 0u); + desc->bInterfaceClass = TUSB_CLASS_CDC; + desc->bInterfaceSubClass = p_cdc->bInterfaceSubClass; + desc->bInterfaceProtocol = p_cdc->bInterfaceProtocol; + desc->iInterface = 0; // not used yet return true; } diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 03f32e542..a1e78f158 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -71,21 +71,13 @@ // Application API //--------------------------------------------------------------------+ -typedef struct -{ - uint8_t daddr; - uint8_t bInterfaceNumber; - uint8_t bInterfaceSubClass; - uint8_t bInterfaceProtocol; -} tuh_cdc_itf_info_t; - // Get Interface index from device address + interface number // return TUSB_INDEX_INVALID_8 (0xFF) if not found uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num); // Get Interface information // return true if index is correct and interface is currently mounted -bool tuh_cdc_itf_get_info(uint8_t idx, tuh_cdc_itf_info_t* info); +bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info); // Check if a interface is mounted bool tuh_cdc_mounted(uint8_t idx); diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index f65b2dc20..20373f541 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -134,6 +134,29 @@ bool tuh_hid_mounted(uint8_t daddr, uint8_t idx) return p_hid != NULL; } +bool tuh_hid_itf_get_info(uint8_t daddr, uint8_t idx, tuh_itf_info_t* info) +{ + hidh_interface_t* p_hid = get_hid_itf(daddr, idx); + TU_VERIFY(p_hid && info); + + info->daddr = daddr; + + // re-construct descriptor + tusb_desc_interface_t* desc = &info->desc; + desc->bLength = sizeof(tusb_desc_interface_t); + desc->bDescriptorType = TUSB_DESC_INTERFACE; + + desc->bInterfaceNumber = p_hid->itf_num; + desc->bAlternateSetting = 0; + desc->bNumEndpoints = (uint8_t) ((p_hid->ep_in ? 1u : 0u) + (p_hid->ep_out ? 1u : 0u)); + desc->bInterfaceClass = TUSB_CLASS_HID; + desc->bInterfaceSubClass = (p_hid->itf_protocol ? HID_SUBCLASS_BOOT : HID_SUBCLASS_NONE); + desc->bInterfaceProtocol = p_hid->itf_protocol; + desc->iInterface = 0; // not used yet + + return true; +} + uint8_t tuh_hid_itf_get_index(uint8_t daddr, uint8_t itf_num) { for ( uint8_t idx = 0; idx < CFG_TUH_HID; idx++ ) diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h index f808f36d4..c0c727e6a 100644 --- a/src/class/hid/hid_host.h +++ b/src/class/hid/hid_host.h @@ -71,8 +71,8 @@ uint8_t tuh_hid_itf_get_total_count(void); // backward compatible rename #define tuh_hid_instance_count tuh_hid_itf_get_count -// Check if HID interface is mounted -bool tuh_hid_mounted(uint8_t dev_addr, uint8_t idx); +// Get Interface information +bool tuh_hid_itf_get_info(uint8_t daddr, uint8_t idx, tuh_itf_info_t* itf_info); // Get Interface index from device address + interface number // return TUSB_INDEX_INVALID_8 (0xFF) if not found @@ -81,6 +81,9 @@ uint8_t tuh_hid_itf_get_index(uint8_t daddr, uint8_t itf_num); // Get interface supported protocol (bInterfaceProtocol) check out hid_interface_protocol_enum_t for possible values uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t idx); +// Check if HID interface is mounted +bool tuh_hid_mounted(uint8_t dev_addr, uint8_t idx); + // Parse report descriptor into array of report_info struct and return number of reports. // For complicated report, application should write its own parser. uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr, uint8_t arr_count, uint8_t const* desc_report, uint16_t desc_len) TU_ATTR_UNUSED; diff --git a/tools/build_family.py b/tools/build_family.py index cdc099691..532938d42 100644 --- a/tools/build_family.py +++ b/tools/build_family.py @@ -34,7 +34,6 @@ def build_family(example, family, make_option): # sum all element of same index (column sum) return list(map(sum, list(zip(*result)))) - if __name__ == '__main__': # IAR CC if make_iar_option not in sys.argv: @@ -68,7 +67,8 @@ if __name__ == '__main__': print(build_separator) for family in all_families: fret = build_family(example, family, make_iar_option) - total_result = list(map(lambda x, y: x + y, total_result, fret)) + if len(fret) == len(total_result): + total_result = [total_result[i] + fret[i] for i in range(len(fret))] total_time = time.monotonic() - total_time print(build_separator) diff --git a/tools/get_deps.py b/tools/get_deps.py index 8bf56cd8d..4b81d1468 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -105,7 +105,13 @@ def get_a_dep(d): if __name__ == "__main__": status = 0 - deps = list(deps_mandatory.keys()) + sys.argv[1:] + deps = list(deps_mandatory.keys()) + # get all if executed with all as argument + if len(sys.argv) == 2 and sys.argv[1] == 'all': + deps += deps_optional + else: + deps += sys.argv[1:] + with Pool() as pool: status = sum(pool.map(get_a_dep, deps)) sys.exit(status) -- cgit v1.3.1 From c85f46c4ab8c680eb02e6a964cf3afadf2301328 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Mar 2023 16:59:57 +0700 Subject: fix bitorder in usbtmc_response_capabilities_488_t --- src/class/usbtmc/usbtmc.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/class/usbtmc/usbtmc.h b/src/class/usbtmc/usbtmc.h index 3c5e86d4c..1b3c3ab6d 100644 --- a/src/class/usbtmc/usbtmc.h +++ b/src/class/usbtmc/usbtmc.h @@ -277,17 +277,17 @@ typedef struct TU_ATTR_PACKED struct TU_ATTR_PACKED { - unsigned int is488_2 :1; - unsigned int supportsREN_GTL_LLO :1; - unsigned int supportsTrigger :1; + uint8_t supportsTrigger :1; + uint8_t supportsREN_GTL_LLO :1; + uint8_t is488_2 :1; } bmIntfcCapabilities488; struct TU_ATTR_PACKED { - unsigned int SCPI :1; - unsigned int SR1 :1; - unsigned int RL1 :1; - unsigned int DT1 :1; + uint8_t DT1 :1; + uint8_t RL1 :1; + uint8_t SR1 :1; + uint8_t SCPI :1; } bmDevCapabilities488; uint8_t _reserved3[8]; } usbtmc_response_capabilities_488_t; -- cgit v1.3.1 From 096da11e88cd9d4714db9590955fb7db62edb75e Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Mar 2023 17:01:04 +0700 Subject: more update --- src/class/usbtmc/usbtmc.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/class/usbtmc/usbtmc.h b/src/class/usbtmc/usbtmc.h index 1b3c3ab6d..090ab3c4a 100644 --- a/src/class/usbtmc/usbtmc.h +++ b/src/class/usbtmc/usbtmc.h @@ -262,14 +262,14 @@ typedef struct TU_ATTR_PACKED struct TU_ATTR_PACKED { - unsigned int listenOnly :1; - unsigned int talkOnly :1; - unsigned int supportsIndicatorPulse :1; + uint8_t listenOnly :1; + uint8_t talkOnly :1; + uint8_t supportsIndicatorPulse :1; } bmIntfcCapabilities; struct TU_ATTR_PACKED { - unsigned int canEndBulkInOnTermChar :1; + uint8_t canEndBulkInOnTermChar :1; } bmDevCapabilities; uint8_t _reserved2[6]; -- cgit v1.3.1 From 4274cab3950cfa30b387bab7d388b6a4b8480edb Mon Sep 17 00:00:00 2001 From: Matt Mills Date: Wed, 22 Mar 2023 07:18:27 -0600 Subject: Update net_device.h --- src/class/net/net_device.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h index 133689deb..399916355 100644 --- a/src/class/net/net_device.h +++ b/src/class/net/net_device.h @@ -94,7 +94,7 @@ void tud_network_init_cb(void); // client must provide this: 48-bit MAC address // TODO removed later since it is not part of tinyusb stack -extern const uint8_t tud_network_mac_address[6]; +extern uint8_t tud_network_mac_address[6]; //------------- NCM -------------// -- cgit v1.3.1 From 71fb6469d4997347f2014daa41839391cc070a74 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 24 Mar 2023 14:02:09 +0700 Subject: separate CFG_TUSB_MEM_SECTION and CFG_TUSB_MEM_ALIGN to - CFG_TUD_MEM_SECTION and CFG_TUD_MEM_ALIGN - CFG_TUH_MEM_SECTION and CFG_TUH_MEM_ALIGN - fix missing mem section and align for host --- hw/bsp/ea4088qs/board.mk | 3 ++- src/class/cdc/cdc_host.c | 6 +++--- src/class/cdc/cdc_rndis_host.c | 4 ++-- src/class/hid/hid_host.c | 6 +++--- src/class/msc/msc_host.c | 8 ++++---- src/host/hub.c | 8 ++++---- src/host/usbh.c | 8 ++++---- src/portable/ehci/ehci.c | 2 +- src/portable/nxp/khci/hcd_khci.c | 4 ++-- src/portable/ohci/ohci.c | 2 +- src/tusb_option.h | 40 +++++++++++++++++++++++++++++++++++++++- tools/build_utils.py | 2 +- tools/gen_doc.py | 2 ++ 13 files changed, 68 insertions(+), 27 deletions(-) (limited to 'src') diff --git a/hw/bsp/ea4088qs/board.mk b/hw/bsp/ea4088qs/board.mk index 376840fb1..e1e14b717 100644 --- a/hw/bsp/ea4088qs/board.mk +++ b/hw/bsp/ea4088qs/board.mk @@ -10,7 +10,8 @@ CFLAGS += \ -nostdlib \ -DCORE_M4 \ -D__USE_LPCOPEN \ - -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \ + -DCFG_TUD_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \ + -DCFG_TUH_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \ -DCFG_TUSB_MCU=OPT_MCU_LPC40XX # mcu driver cause following warnings diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index fee314823..734ddd1b8 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -62,10 +62,10 @@ typedef struct { tu_edpt_stream_t rx; uint8_t tx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t tx_ep_buf[CFG_TUH_CDC_TX_EPSIZE]; + CFG_TUH_MEM_ALIGN uint8_t tx_ep_buf[CFG_TUH_CDC_TX_EPSIZE]; uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE]; + CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE]; } stream; } cdch_interface_t; @@ -74,7 +74,7 @@ typedef struct { // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION +CFG_TUH_MEM_SECTION static cdch_interface_t cdch_data[CFG_TUH_CDC]; static inline cdch_interface_t* get_itf(uint8_t idx) diff --git a/src/class/cdc/cdc_rndis_host.c b/src/class/cdc/cdc_rndis_host.c index 41d21bbad..11a5355aa 100644 --- a/src/class/cdc/cdc_rndis_host.c +++ b/src/class/cdc/cdc_rndis_host.c @@ -50,8 +50,8 @@ //--------------------------------------------------------------------+ #define RNDIS_MSG_PAYLOAD_MAX (1024*4) -CFG_TUSB_MEM_SECTION static uint8_t msg_notification[CFG_TUH_DEVICE_MAX][8]; -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t msg_payload[RNDIS_MSG_PAYLOAD_MAX]; +CFG_TUH_MEM_SECTION static uint8_t msg_notification[CFG_TUH_DEVICE_MAX][8]; +CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static uint8_t msg_payload[RNDIS_MSG_PAYLOAD_MAX]; static rndish_data_t rndish_data[CFG_TUH_DEVICE_MAX]; diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 20373f541..a0032aeba 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -54,11 +54,11 @@ typedef struct uint16_t epin_size; uint16_t epout_size; - uint8_t epin_buf[CFG_TUH_HID_EPIN_BUFSIZE]; - uint8_t epout_buf[CFG_TUH_HID_EPOUT_BUFSIZE]; + CFG_TUH_MEM_ALIGN uint8_t epin_buf[CFG_TUH_HID_EPIN_BUFSIZE]; + CFG_TUH_MEM_ALIGN uint8_t epout_buf[CFG_TUH_HID_EPOUT_BUFSIZE]; } hidh_interface_t; -CFG_TUSB_MEM_SECTION +CFG_TUH_MEM_SECTION tu_static hidh_interface_t _hidh_itf[CFG_TUH_HID]; //--------------------------------------------------------------------+ diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c index 2fddeb818..1b48813ec 100644 --- a/src/class/msc/msc_host.c +++ b/src/class/msc/msc_host.c @@ -71,15 +71,15 @@ typedef struct tuh_msc_complete_cb_t complete_cb; uintptr_t complete_arg; - msc_cbw_t cbw; - msc_csw_t csw; + CFG_TUH_MEM_ALIGN msc_cbw_t cbw; + CFG_TUH_MEM_ALIGN msc_csw_t csw; }msch_interface_t; -CFG_TUSB_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX]; +CFG_TUH_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX]; // buffer used to read scsi information when mounted // largest response data currently is inquiry TODO Inquiry is not part of enum anymore -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) +CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static uint8_t _msch_buffer[sizeof(scsi_inquiry_resp_t)]; TU_ATTR_ALWAYS_INLINE diff --git a/src/host/hub.c b/src/host/hub.c index b84042fb6..386ad6aae 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -43,12 +43,12 @@ typedef struct uint8_t port_count; uint8_t status_change; // data from status change interrupt endpoint - hub_port_status_response_t port_status; - hub_status_response_t hub_status; + CFG_TUH_MEM_ALIGN hub_port_status_response_t port_status; + CFG_TUH_MEM_ALIGN hub_status_response_t hub_status; } hub_interface_t; -CFG_TUSB_MEM_SECTION static hub_interface_t hub_data[CFG_TUH_HUB]; -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _hub_buffer[sizeof(descriptor_hub_desc_t)]; +CFG_TUH_MEM_SECTION static hub_interface_t hub_data[CFG_TUH_HUB]; +CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static uint8_t _hub_buffer[sizeof(descriptor_hub_desc_t)]; TU_ATTR_ALWAYS_INLINE static inline hub_interface_t* get_itf(uint8_t dev_addr) diff --git a/src/host/usbh.c b/src/host/usbh.c index 3eff0830a..3be662c63 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -203,7 +203,7 @@ static usbh_dev0_t _dev0; // all devices excluding zero-address // hub address start from CFG_TUH_DEVICE_MAX+1 // TODO: hub can has its own simpler struct to save memory -CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[TOTAL_DEVICES]; +static usbh_device_t _usbh_devices[TOTAL_DEVICES]; // Mutex for claiming endpoint #if OSAL_MUTEX_REQUIRED @@ -218,15 +218,15 @@ CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[TOTAL_DEVICES]; OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t); static osal_queue_t _usbh_q; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN +CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE]; // Control transfers: since most controllers do not support multiple control transfers // on multiple devices concurrently and control transfers are not used much except for // enumeration, we will only execute control transfers one at a time. -CFG_TUSB_MEM_SECTION struct +CFG_TUH_MEM_SECTION struct { - tusb_control_request_t request TU_ATTR_ALIGNED(4); + CFG_TUH_MEM_ALIGN tusb_control_request_t request; uint8_t* buffer; tuh_xfer_cb_t complete_cb; uintptr_t user_data; diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index ee9dfb11f..9951aa5da 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -85,7 +85,7 @@ typedef struct }ehci_data_t; // Periodic frame list must be 4K alignment -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data; +CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data; //--------------------------------------------------------------------+ // PROTOTYPE diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index 6d25cd862..f6029ee0d 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -137,8 +137,8 @@ typedef struct // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ // BDT(Buffer Descriptor Table) must be 256-byte aligned -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static hcd_data_t _hcd; -//CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _rx_buf[1024]; +CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(512) static hcd_data_t _hcd; +//CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _rx_buf[1024]; int find_pipe(uint8_t dev_addr, uint8_t ep_addr) { diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 260804d3d..3f702d22c 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -145,7 +145,7 @@ enum { //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static ohci_data_t ohci_data; +CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(256) static ohci_data_t ohci_data; static ohci_ed_t * const p_ed_head[] = { diff --git a/src/tusb_option.h b/src/tusb_option.h index c679f2f12..f8ac722f4 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -289,12 +289,15 @@ #define CFG_TUSB_DEBUG 0 #endif -// place data in accessible RAM for usb controller +// TODO MEM_SECTION can be different for host and device controller +// should use CFG_TUD_MEM_SECTION, CFG_TUH_MEM_SECTION #ifndef CFG_TUSB_MEM_SECTION #define CFG_TUSB_MEM_SECTION #endif // alignment requirement of buffer used for endpoint transferring +// TODO MEM_ALIGN can be different for host and device controller +// should use CFG_TUD_MEM_ALIGN, CFG_TUH_MEM_ALIGN #ifndef CFG_TUSB_MEM_ALIGN #define CFG_TUSB_MEM_ALIGN TU_ATTR_ALIGNED(4) #endif @@ -312,6 +315,26 @@ // Device Options (Default) //-------------------------------------------------------------------- +// Attribute to place data in accessible RAM for device controller +// default to CFG_TUSB_MEM_SECTION for backward-compatible +#ifndef CFG_TUD_MEM_SECTION + #ifdef CFG_TUSB_MEM_SECTION + #define CFG_TUD_MEM_SECTION CFG_TUSB_MEM_SECTION + #else + #define CFG_TUD_MEM_SECTION + #endif +#endif + +// Attribute to align memory for device controller +// default to CFG_TUSB_MEM_ALIGN for backward-compatible +#ifndef CFG_TUD_MEM_ALIGN + #ifdef CFG_TUSB_MEM_ALIGN + #define CFG_TUD_MEM_ALIGN CFG_TUSB_MEM_ALIGN + #else + #define CFG_TUD_MEM_ALIGN TU_ATTR_ALIGNED(4) + #endif +#endif + #ifndef CFG_TUD_ENDPOINT0_SIZE #define CFG_TUD_ENDPOINT0_SIZE 64 #endif @@ -390,6 +413,21 @@ #endif #endif // CFG_TUH_ENABLED +// Attribute to place data in accessible RAM for host controller +// default to CFG_TUSB_MEM_SECTION for backward-compatible +#ifndef CFG_TUH_MEM_SECTION + #ifdef CFG_TUSB_MEM_SECTION + #define CFG_TUH_MEM_SECTION CFG_TUSB_MEM_SECTION + #else + #define CFG_TUH_MEM_SECTION + #endif +#endif + +// Attribute to align memory for host controller +#ifndef CFG_TUH_MEM_ALIGN + #define CFG_TUH_MEM_ALIGN TU_ATTR_ALIGNED(4) +#endif + //------------- CLASS -------------// #ifndef CFG_TUH_HUB diff --git a/tools/build_utils.py b/tools/build_utils.py index d0ef52717..905d06a86 100644 --- a/tools/build_utils.py +++ b/tools/build_utils.py @@ -93,7 +93,7 @@ def build_example(example, board, make_option): ret[2] = 1 print(build_format.format(example, board, status, '-', flash_size, sram_size)) else: - subprocess.run(make_cmd + " clean", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) + #subprocess.run(make_cmd + " clean", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) build_result = subprocess.run(make_cmd + " all", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) if build_result.returncode == 0: diff --git a/tools/gen_doc.py b/tools/gen_doc.py index db11e2cfb..9078299cc 100644 --- a/tools/gen_doc.py +++ b/tools/gen_doc.py @@ -6,9 +6,11 @@ from get_deps import deps_all # TOP is tinyusb root dir TOP = Path(__file__).parent.parent.resolve() + ########################################### # Dependencies ########################################### + def gen_deps_doc(): deps_rst = Path(TOP) / "docs/reference/dependencies.rst" df = pd.DataFrame.from_dict(deps_all, orient='index', columns=['Commit', 'Project']) -- cgit v1.3.1 From b05422978004f076de665f5101e5cc1bac34175c Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 24 Mar 2023 17:26:30 +0700 Subject: fix cdc host enumeration issue when device does not support line request --- src/class/cdc/cdc_host.c | 39 +++++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 16 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 734ddd1b8..08b82416d 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -323,7 +323,8 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c .user_data = user_data }; - return tuh_control_xfer(&xfer); + TU_ASSERT(tuh_control_xfer(&xfer)); + return true; } bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) @@ -363,7 +364,8 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, .user_data = user_data }; - return tuh_control_xfer(&xfer); + TU_ASSERT(tuh_control_xfer(&xfer)); + return true; } //--------------------------------------------------------------------+ @@ -543,26 +545,31 @@ static void process_cdc_config(tuh_xfer_t* xfer) uintptr_t const state = xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - TU_ASSERT(idx != TUSB_INDEX_INVALID_8, ); + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc, ); switch(state) { case CONFIG_SET_CONTROL_LINE_STATE: - #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - TU_ASSERT( tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cdc_config, CONFIG_SET_LINE_CODING), ); - break; - #endif - TU_ATTR_FALLTHROUGH; + #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + if (p_cdc->acm_capability.support_line_request) + { + TU_ASSERT( tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cdc_config, CONFIG_SET_LINE_CODING), ); + break; + } + #endif + TU_ATTR_FALLTHROUGH; case CONFIG_SET_LINE_CODING: - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - { - cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, CONFIG_COMPLETE), ); - break; - } - #endif - TU_ATTR_FALLTHROUGH; + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + if (p_cdc->acm_capability.support_line_request) + { + cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, CONFIG_COMPLETE), ); + break; + } + #endif + TU_ATTR_FALLTHROUGH; case CONFIG_COMPLETE: if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx); -- cgit v1.3.1 From df5f60b6d67400891c5887afe29fcac5644cc668 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 24 Mar 2023 17:36:29 +0700 Subject: fix shadow warning --- src/class/cdc/cdc_host.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 08b82416d..c0cc41adf 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -575,7 +575,6 @@ static void process_cdc_config(tuh_xfer_t* xfer) if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx); // Prepare for incoming data - cdch_interface_t* p_cdc = get_itf(idx); tu_edpt_stream_read_xfer(&p_cdc->stream.rx); // notify usbh that driver enumeration is complete -- cgit v1.3.1 From 97f9321e1d94ddb4904dba0a472790a1189e53f2 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Fri, 3 Mar 2023 22:06:57 +0900 Subject: Add handling for bulk EPs --- src/class/video/video_device.c | 39 ++++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 15 deletions(-) (limited to 'src') diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index d6e98602b..e03ca6b1f 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -680,24 +680,30 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint (video_probe_and_commit_control_t *)&stm->ep_buf; tu_memclr(param, sizeof(*param)); TU_LOG2(" done 0\n"); - return _update_streaming_parameters(stm, param); + if (!_update_streaming_parameters(stm, param)) + return false; + /* Open bulk endpoint if present. */ + for (i = 0, cur = tu_desc_next(cur); i < numeps; ++i, cur = tu_desc_next(cur)) { + cur = _find_desc_ep(cur, end); + TU_ASSERT(cur < end); + tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)cur; + TU_VERIFY(TUSB_XFER_BULK == ep->bmAttributes.xfer); + TU_ASSERT(usbd_edpt_open(rhport, ep)); + stm->desc.ep[i] = (uint16_t)(cur - desc); + TU_LOG2(" open EP%02x\n", _desc_ep_addr(cur)); + } + return true; } - /* Open endpoints of the new settings. */ + /* Open isochronous endpoints of the new settings. */ for (i = 0, cur = tu_desc_next(cur); i < numeps; ++i, cur = tu_desc_next(cur)) { cur = _find_desc_ep(cur, end); TU_ASSERT(cur < end); tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)cur; - if (!stm->max_payload_transfer_size) { - video_probe_and_commit_control_t const *param = (video_probe_and_commit_control_t const*)&stm->ep_buf; - uint_fast32_t max_size = param->dwMaxPayloadTransferSize; - if ((TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer) && - (tu_edpt_packet_size(ep) < max_size)) - { - /* FS must be less than or equal to max packet size */ - return false; - } - /* Set the negotiated value */ - stm->max_payload_transfer_size = max_size; + uint_fast32_t max_size = stm->max_payload_transfer_size; + if ((TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer) && + (tu_edpt_packet_size(ep) < max_size)) { + /* FS must be less than or equal to max packet size */ + return false; } TU_ASSERT(usbd_edpt_open(rhport, ep)); stm->desc.ep[i] = (uint16_t) (cur - desc); @@ -982,9 +988,12 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, TU_VERIFY(sizeof(video_probe_and_commit_control_t) >= request->wLength, VIDEO_ERROR_UNKNOWN); TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); } else if (stage == CONTROL_STAGE_DATA) { - TU_VERIFY(_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); + video_probe_and_commit_control_t *param = (video_probe_and_commit_control_t*)self->ep_buf; + TU_VERIFY(_update_streaming_parameters(self, param), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); + /* Set the negotiated value */ + self->max_payload_transfer_size = param->dwMaxPayloadTransferSize; if (tud_video_commit_cb) { - return tud_video_commit_cb(self->index_vc, self->index_vs, (video_probe_and_commit_control_t*)self->ep_buf); + return tud_video_commit_cb(self->index_vc, self->index_vs, param); } } return VIDEO_ERROR_NONE; -- cgit v1.3.1 From 78732d6733fa75e6f8b25dc9e694d4d38e7b72ce Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Fri, 10 Mar 2023 22:51:49 +0900 Subject: Fix streaming interface handling --- src/class/video/video_device.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index e03ca6b1f..d53de2bac 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -709,11 +709,6 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint stm->desc.ep[i] = (uint16_t) (cur - desc); TU_LOG2(" open EP%02x\n", _desc_ep_addr(cur)); } - /* initialize payload header */ - tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf; - hdr->bHeaderLength = sizeof(*hdr); - hdr->bmHeaderInfo = 0; - TU_LOG2(" done\n"); return true; } @@ -992,8 +987,15 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, TU_VERIFY(_update_streaming_parameters(self, param), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); /* Set the negotiated value */ self->max_payload_transfer_size = param->dwMaxPayloadTransferSize; + int ret = VIDEO_ERROR_NONE; if (tud_video_commit_cb) { - return tud_video_commit_cb(self->index_vc, self->index_vs, param); + ret = tud_video_commit_cb(self->index_vc, self->index_vs, param); + } + if (VIDEO_ERROR_NONE == ret) { + /* initialize payload header */ + tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)self->ep_buf; + hdr->bHeaderLength = sizeof(*hdr); + hdr->bmHeaderInfo = 0; } } return VIDEO_ERROR_NONE; @@ -1166,6 +1168,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); uint_fast8_t bInCollection = vc->ctl.bInCollection; + videod_streaming_interface_t *default_stm = NULL; /* Find the end of the video interface descriptor */ void const *cur = _next_desc_itf(itf_desc, end); for (uint8_t stm_idx = 0; stm_idx < bInCollection; ++stm_idx) { @@ -1183,7 +1186,9 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin stm->desc.beg = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc); cur = _next_desc_itf(cur, end); stm->desc.end = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc); + if (!default_stm) default_stm = stm; } + TU_VERIFY(_open_vs_itf(rhport, default_stm, 0), 0); self->len = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc); return (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc); } -- cgit v1.3.1 From e508831561da46cfd03e59876e4218aadd57855c Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Mon, 13 Mar 2023 22:50:31 +0900 Subject: Update handle streaming interface --- src/class/video/video_device.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index d53de2bac..8dd39242f 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -1168,7 +1168,6 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); uint_fast8_t bInCollection = vc->ctl.bInCollection; - videod_streaming_interface_t *default_stm = NULL; /* Find the end of the video interface descriptor */ void const *cur = _next_desc_itf(itf_desc, end); for (uint8_t stm_idx = 0; stm_idx < bInCollection; ++stm_idx) { @@ -1186,9 +1185,16 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin stm->desc.beg = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc); cur = _next_desc_itf(cur, end); stm->desc.end = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc); - if (!default_stm) default_stm = stm; + if (0 == stm_idx && 1 == bInCollection) { + /* If there is only one streaming interface and no alternate settings, + * host may not issue set_interface so open the streaming interface here. */ + uint8_t const *sbeg = (uint8_t const*)itf_desc + stm->desc.beg; + uint8_t const *send = (uint8_t const*)itf_desc + stm->desc.end; + if (end == _find_desc_itf(sbeg, send, _desc_itfnum(sbeg), 1)) { + TU_VERIFY(_open_vs_itf(rhport, stm, 0), 0); + } + } } - TU_VERIFY(_open_vs_itf(rhport, default_stm, 0), 0); self->len = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc); return (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc); } @@ -1201,7 +1207,6 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ int err; TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE); uint_fast8_t itfnum = tu_u16_low(request->wIndex); - /* Identify which control interface to use */ uint_fast8_t itf; for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) { -- cgit v1.3.1 From 993b8d66861253408c1029bf98923ccba7317482 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 25 Mar 2023 22:13:20 +0900 Subject: Add state variable --- src/class/video/video_device.c | 68 ++++++++++++++++++++++++++---------------- 1 file changed, 42 insertions(+), 26 deletions(-) (limited to 'src') diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 8dd39242f..91f452afc 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -37,6 +37,10 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ +#define VS_STATE_PROBING 0 /* Configuration in progress */ +#define VS_STATE_COMMITTED 1 /* Ready for streaming or Streaming via bulk endpoint */ +#define VS_STATE_STREAMING 2 /* Streaming via isochronous endpoint */ + typedef struct { tusb_desc_interface_t std; tusb_desc_cs_video_ctl_itf_hdr_t ctl; @@ -102,6 +106,7 @@ typedef struct TU_ATTR_PACKED { uint32_t offset; /* offset for the next payload transfer */ uint32_t max_payload_transfer_size; uint8_t error_code;/* error code */ + uint8_t state; /* 0:probing 1:committed 2:streaming */ /*------------- From this point, data is not cleared by bus reset -------------*/ CFG_TUSB_MEM_ALIGN uint8_t ep_buf[CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE]; /* EP transfer buffer for streaming */ } videod_streaming_interface_t; @@ -639,6 +644,17 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t return true; } +static bool _init_vs_configuration(videod_streaming_interface_t *stm) +{ + /* initialize streaming settings */ + stm->state = VS_STATE_PROBING; + stm->max_payload_transfer_size = 0; + video_probe_and_commit_control_t *param = + (video_probe_and_commit_control_t *)&stm->ep_buf; + tu_memclr(param, sizeof(*param)); + return _update_streaming_parameters(stm, param); +} + /** Set the alternate setting to own video streaming interface. * * @param[in,out] stm Streaming interface context. @@ -672,43 +688,32 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint uint_fast8_t numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints; TU_ASSERT(numeps <= TU_ARRAY_SIZE(stm->desc.ep)); - stm->desc.cur = (uint16_t) (cur - desc); /* Save the offset of the new settings */ - if (!altnum) { - /* initialize streaming settings */ - stm->max_payload_transfer_size = 0; - video_probe_and_commit_control_t *param = - (video_probe_and_commit_control_t *)&stm->ep_buf; - tu_memclr(param, sizeof(*param)); - TU_LOG2(" done 0\n"); - if (!_update_streaming_parameters(stm, param)) - return false; - /* Open bulk endpoint if present. */ - for (i = 0, cur = tu_desc_next(cur); i < numeps; ++i, cur = tu_desc_next(cur)) { - cur = _find_desc_ep(cur, end); - TU_ASSERT(cur < end); - tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)cur; - TU_VERIFY(TUSB_XFER_BULK == ep->bmAttributes.xfer); - TU_ASSERT(usbd_edpt_open(rhport, ep)); - stm->desc.ep[i] = (uint16_t)(cur - desc); - TU_LOG2(" open EP%02x\n", _desc_ep_addr(cur)); - } - return true; + stm->desc.cur = (uint16_t)(cur - desc); /* Save the offset of the new settings */ + if (!altnum && (VS_STATE_COMMITTED != stm->state)) { + TU_VERIFY(_init_vs_configuration(stm)); } - /* Open isochronous endpoints of the new settings. */ + /* Open bulk or isochronous endpoints of the new settings. */ for (i = 0, cur = tu_desc_next(cur); i < numeps; ++i, cur = tu_desc_next(cur)) { cur = _find_desc_ep(cur, end); TU_ASSERT(cur < end); tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)cur; uint_fast32_t max_size = stm->max_payload_transfer_size; - if ((TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer) && - (tu_edpt_packet_size(ep) < max_size)) { - /* FS must be less than or equal to max packet size */ - return false; + if (altnum) { + if ((TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer) && + (tu_edpt_packet_size(ep) < max_size)) { + /* FS must be less than or equal to max packet size */ + return false; + } + } else { + TU_VERIFY(TUSB_XFER_BULK == ep->bmAttributes.xfer); } TU_ASSERT(usbd_edpt_open(rhport, ep)); stm->desc.ep[i] = (uint16_t) (cur - desc); TU_LOG2(" open EP%02x\n", _desc_ep_addr(cur)); } + if (altnum) { + stm->state = VS_STATE_STREAMING; + } TU_LOG2(" done\n"); return true; } @@ -921,6 +926,10 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, break; case VIDEO_VS_CTL_PROBE: + if (self->state != VS_STATE_PROBING) { + self->state = VS_STATE_PROBING; + _init_vs_configuration(self); + } switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: if (stage == CONTROL_STAGE_SETUP) { @@ -992,6 +1001,10 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, ret = tud_video_commit_cb(self->index_vc, self->index_vs, param); } if (VIDEO_ERROR_NONE == ret) { + self->state = VS_STATE_COMMITTED; + self->buffer = NULL; + self->bufsize = 0; + self->offset = 0; /* initialize payload header */ tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)self->ep_buf; hdr->bHeaderLength = sizeof(*hdr); @@ -1080,6 +1093,7 @@ bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) TU_ASSERT(stm_idx < CFG_TUD_VIDEO_STREAMING); videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx); if (!stm || !stm->desc.ep[0]) return false; + if (stm->state == VS_STATE_PROBING) return false; return true; } @@ -1090,6 +1104,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu if (!buffer || !bufsize) return false; videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx); if (!stm || !stm->desc.ep[0] || stm->buffer) return false; + if (stm->state == VS_STATE_PROBING) return false; /* Find EP address */ uint8_t const *desc = _videod_itf[stm->index_vc].beg; @@ -1185,6 +1200,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin stm->desc.beg = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc); cur = _next_desc_itf(cur, end); stm->desc.end = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc); + stm->state = VS_STATE_PROBING; if (0 == stm_idx && 1 == bInCollection) { /* If there is only one streaming interface and no alternate settings, * host may not issue set_interface so open the streaming interface here. */ -- cgit v1.3.1 From faaed198b48b3af7482503bacf3188040c245a1e Mon Sep 17 00:00:00 2001 From: epatstarkey <58745560+epatstarkey@users.noreply.github.com> Date: Tue, 28 Mar 2023 13:59:59 -0500 Subject: Update vendor_device.h --- src/class/vendor/vendor_device.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h index 9abafda50..ca4837d7b 100644 --- a/src/class/vendor/vendor_device.h +++ b/src/class/vendor/vendor_device.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -48,6 +48,7 @@ bool tud_vendor_n_peek (uint8_t itf, uint8_t* ui8); void tud_vendor_n_read_flush (uint8_t itf); uint32_t tud_vendor_n_write (uint8_t itf, void const* buffer, uint32_t bufsize); +uint32_t tud_vendor_n_write_flush (uint8_t itf); uint32_t tud_vendor_n_write_available (uint8_t itf); static inline uint32_t tud_vendor_n_write_str (uint8_t itf, char const* str); @@ -64,7 +65,7 @@ static inline void tud_vendor_read_flush (void); static inline uint32_t tud_vendor_write (void const* buffer, uint32_t bufsize); static inline uint32_t tud_vendor_write_str (char const* str); static inline uint32_t tud_vendor_write_available (void); -static inline uint32_t tud_vendor_flush (void); +static inline uint32_t tud_vendor_write_flush (void); //--------------------------------------------------------------------+ // Application Callback API (weak is optional) @@ -114,6 +115,11 @@ static inline uint32_t tud_vendor_write (void const* buffer, uint32_t bufsize) return tud_vendor_n_write(0, buffer, bufsize); } +static inline uint32_t tud_vendor_write_flush (void) +{ + return tud_vendor_n_write_flush(0); +} + static inline uint32_t tud_vendor_write_str (char const* str) { return tud_vendor_n_write_str(0, str); @@ -124,11 +130,6 @@ static inline uint32_t tud_vendor_write_available (void) return tud_vendor_n_write_available(0); } -static inline uint32_t tud_vendor_flush (void) -{ - return tud_vendor_n_flush(0); -} - //--------------------------------------------------------------------+ // Internal Class Driver API //--------------------------------------------------------------------+ -- cgit v1.3.1 From 876f49f6ad10ef2bca000602fe862889c3e0268f Mon Sep 17 00:00:00 2001 From: epatstarkey <58745560+epatstarkey@users.noreply.github.com> Date: Tue, 28 Mar 2023 14:00:23 -0500 Subject: Update vendor_device.c --- src/class/vendor/vendor_device.c | 65 ++++++++++++++++++++++++---------------- 1 file changed, 40 insertions(+), 25 deletions(-) (limited to 'src') diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index d07bd75ec..260da0125 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -59,7 +59,7 @@ typedef struct CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_VENDOR_EPSIZE]; } vendord_interface_t; -CFG_TUSB_MEM_SECTION tu_static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR]; +CFG_TUSB_MEM_SECTION static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR]; #define ITF_MEM_RESET_SIZE offsetof(vendord_interface_t, rx_ff) @@ -86,8 +86,8 @@ static void _prep_out_transaction (vendord_interface_t* p_itf) { uint8_t const rhport = 0; - // skip if previous transfer not complete - if ( usbd_edpt_busy(rhport, p_itf->ep_out) ) return; + // claim endpoint + TU_VERIFY(usbd_edpt_claim(rhport, p_itf->ep_out), ); // Prepare for incoming data but only allow what we can store in the ring buffer. uint16_t max_read = tu_fifo_remaining(&p_itf->rx_ff); @@ -95,6 +95,11 @@ static void _prep_out_transaction (vendord_interface_t* p_itf) { usbd_edpt_xfer(rhport, p_itf->ep_out, p_itf->epout_buf, CFG_TUD_VENDOR_EPSIZE); } + else + { + // Release endpoint since we don't make any transfer + usbd_edpt_release(rhport, p_itf->ep_out); + } } uint32_t tud_vendor_n_read (uint8_t itf, void* buffer, uint32_t bufsize) @@ -115,37 +120,47 @@ void tud_vendor_n_read_flush (uint8_t itf) //--------------------------------------------------------------------+ // Write API //--------------------------------------------------------------------+ -static uint16_t maybe_transmit(vendord_interface_t* p_itf) -{ - uint8_t const rhport = 0; - - // skip if previous transfer not complete - TU_VERIFY( !usbd_edpt_busy(rhport, p_itf->ep_in) ); - - uint16_t count = tu_fifo_read_n(&p_itf->tx_ff, p_itf->epin_buf, CFG_TUD_VENDOR_EPSIZE); - if (count > 0) - { - TU_ASSERT( usbd_edpt_xfer(rhport, p_itf->ep_in, p_itf->epin_buf, count) ); - } - return count; -} - uint32_t tud_vendor_n_write (uint8_t itf, void const* buffer, uint32_t bufsize) { vendord_interface_t* p_itf = &_vendord_itf[itf]; uint16_t ret = tu_fifo_write_n(&p_itf->tx_ff, buffer, (uint16_t) bufsize); + + // flush if queue more than packet size if (tu_fifo_count(&p_itf->tx_ff) >= CFG_TUD_VENDOR_EPSIZE) { - maybe_transmit(p_itf); + tud_vendor_n_write_flush(itf); } return ret; } -uint32_t tud_vendor_n_flush (uint8_t itf) +uint32_t tud_vendor_n_write_flush (uint8_t itf) { vendord_interface_t* p_itf = &_vendord_itf[itf]; - uint32_t ret = maybe_transmit(p_itf); - return ret; + // Skip if usb is not ready yet + TU_VERIFY( tud_ready(), 0 ); + + // No data to send + if ( !tu_fifo_count(&p_itf->tx_ff) ) return 0; + + uint8_t const rhport = 0; + + // Claim the endpoint + TU_VERIFY( usbd_edpt_claim(rhport, p_itf->ep_in), 0 ); + + // Pull data from FIFO + uint16_t const count = tu_fifo_read_n(&p_itf->tx_ff, p_itf->epin_buf, sizeof(p_itf->epin_buf)); + + if ( count ) + { + TU_ASSERT( usbd_edpt_xfer(rhport, p_itf->ep_in, p_itf->epin_buf, count), 0 ); + return count; + }else + { + // Release endpoint since we don't make any transfer + // Note: data is dropped if terminal is not connected + usbd_edpt_release(rhport, p_itf->ep_in); + return 0; + } } uint32_t tud_vendor_n_write_available (uint8_t itf) @@ -225,10 +240,10 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, ui // Prepare for incoming data if ( p_vendor->ep_out ) { - TU_ASSERT(usbd_edpt_xfer(rhport, p_vendor->ep_out, p_vendor->epout_buf, sizeof(p_vendor->epout_buf)), 0); + _prep_out_transaction(p_vendor); } - if ( p_vendor->ep_in ) maybe_transmit(p_vendor); + if ( p_vendor->ep_in ) tud_vendor_n_write_flush((uint8_t)(p_vendor - _vendord_itf)); } return (uint16_t) ((uintptr_t) p_desc - (uintptr_t) desc_itf); @@ -263,7 +278,7 @@ bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint { if (tud_vendor_tx_cb) tud_vendor_tx_cb(itf, (uint16_t) xferred_bytes); // Send complete, try to send more if possible - maybe_transmit(p_itf); + tud_vendor_n_write_flush(itf); } return true; -- cgit v1.3.1 From 1fb2a2f1bd61f06dc9384df1b9df3b39aeec42cf Mon Sep 17 00:00:00 2001 From: epatstarkey <58745560+epatstarkey@users.noreply.github.com> Date: Tue, 28 Mar 2023 14:01:33 -0500 Subject: Update vendor_device.c --- src/class/vendor/vendor_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index 260da0125..93596ee33 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -59,7 +59,7 @@ typedef struct CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_VENDOR_EPSIZE]; } vendord_interface_t; -CFG_TUSB_MEM_SECTION static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR]; +CFG_TUSB_MEM_SECTION tu_static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR]; #define ITF_MEM_RESET_SIZE offsetof(vendord_interface_t, rx_ff) -- cgit v1.3.1 From 1372d4e4d55ee0ff63e07e75aa873c3df3f9e108 Mon Sep 17 00:00:00 2001 From: epatstarkey Date: Fri, 31 Mar 2023 12:58:51 -0500 Subject: Remove trailing whitespace --- src/class/vendor/vendor_device.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h index ca4837d7b..7afd49cc1 100644 --- a/src/class/vendor/vendor_device.h +++ b/src/class/vendor/vendor_device.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) -- cgit v1.3.1 From 718bcdb8bc3b9b522e9bad12ace2c7b62589cb4c Mon Sep 17 00:00:00 2001 From: John Cronin Date: Mon, 3 Apr 2023 13:56:16 +0100 Subject: Add STM32L5 support - no OTG similar to some L4s --- src/common/tusb_mcu.h | 6 ++++++ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 6 ++++++ src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 8 ++++++++ src/tusb_option.h | 1 + 4 files changed, 21 insertions(+) (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index b903abeca..ba8976a8c 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -229,6 +229,12 @@ #define TUP_USBIP_DWC2_STM32 #define TUP_DCD_ENDPOINT_MAX 6 +#elif TU_CHECK_MCU(OPT_MCU_STM32L5) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_STM32 + #define TUP_DCD_ENDPOINT_MAX 8 + + //--------------------------------------------------------------------+ // Sony //--------------------------------------------------------------------+ diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 1677cfa12..98d3d0829 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -362,6 +362,9 @@ void dcd_int_enable (uint8_t rhport) NVIC_EnableIRQ(USB_HP_IRQn); NVIC_EnableIRQ(USB_LP_IRQn); +#elif CFG_TUSB_MCU == OPT_MCU_STM32L5 + NVIC_EnableIRQ(USB_FS_IRQn); + #else #error Unknown arch in USB driver #endif @@ -409,6 +412,9 @@ void dcd_int_disable(uint8_t rhport) NVIC_DisableIRQ(USB_HP_IRQn); NVIC_DisableIRQ(USB_LP_IRQn); +#elif CFG_TUSB_MCU == OPT_MCU_STM32L5 + NVIC_DisableIRQ(USB_FS_IRQn); + #else #error Unknown arch in USB driver #endif diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 015b177cf..e3fc8aeb5 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -93,6 +93,14 @@ #include "stm32l4xx.h" #define PMA_LENGTH (1024u) +#elif CFG_TUSB_MCU == OPT_MCU_STM32L5 + #include "stm32l5xx.h" + #define PMA_LENGTH (1024u) + + #ifndef USB_PMAADDR + #define USB_PMAADDR (USB_BASE + (USB_PMAADDR_NS - USB_BASE_NS)) + #endif + #else #error You are using an untested or unimplemented STM32 variant. Please update the driver. // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4 diff --git a/src/tusb_option.h b/src/tusb_option.h index f8ac722f4..44d036ea4 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -82,6 +82,7 @@ #define OPT_MCU_STM32G4 311 ///< ST G4 #define OPT_MCU_STM32WB 312 ///< ST WB #define OPT_MCU_STM32U5 313 ///< ST U5 +#define OPT_MCU_STM32L5 314 ///< ST L5 // Sony #define OPT_MCU_CXD56 400 ///< SONY CXD56 -- cgit v1.3.1 From 106084289dec0146c117fad69925696b388509be Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 6 Apr 2023 11:15:57 +0700 Subject: add define for vendor_flush() to write_flush() for backward compatible --- src/class/vendor/vendor_device.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h index 7afd49cc1..d239406b4 100644 --- a/src/class/vendor/vendor_device.h +++ b/src/class/vendor/vendor_device.h @@ -52,7 +52,9 @@ uint32_t tud_vendor_n_write_flush (uint8_t itf); uint32_t tud_vendor_n_write_available (uint8_t itf); static inline uint32_t tud_vendor_n_write_str (uint8_t itf, char const* str); -uint32_t tud_vendor_n_flush (uint8_t itf); + +// backward compatible +#define tud_vendor_n_flush(itf) tud_vendor_n_write_flush(itf) //--------------------------------------------------------------------+ // Application API (Single Port) @@ -67,6 +69,9 @@ static inline uint32_t tud_vendor_write_str (char const* str); static inline uint32_t tud_vendor_write_available (void); static inline uint32_t tud_vendor_write_flush (void); +// backward compatible +#define tud_vendor_flush() tud_vendor_write_flush() + //--------------------------------------------------------------------+ // Application Callback API (weak is optional) //--------------------------------------------------------------------+ -- cgit v1.3.1 From 6db24e0dbae248c865ec3ed0e5febcf341b489d4 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 6 Apr 2023 11:16:28 +0700 Subject: implement tuh_hid_receive_ready() and tuh_hid_send_ready() --- src/class/hid/hid_host.c | 23 ++++++++++++++++------- src/class/hid/hid_host.h | 9 ++++++--- 2 files changed, 22 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index a0032aeba..d95d3ef35 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -331,6 +331,15 @@ static bool _hidh_set_idle(uint8_t daddr, uint8_t itf_num, uint16_t idle_rate, t // Interrupt Endpoint API //--------------------------------------------------------------------+ +// Check if HID interface is ready to receive report +bool tuh_hid_receive_ready(uint8_t dev_addr, uint8_t idx) +{ + hidh_interface_t* p_hid = get_hid_itf(dev_addr, idx); + TU_VERIFY(p_hid); + + return !usbh_edpt_busy(dev_addr, p_hid->ep_in); +} + bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx) { hidh_interface_t* p_hid = get_hid_itf(daddr, idx); @@ -348,13 +357,13 @@ bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx) return true; } -//bool tuh_n_hid_n_ready(uint8_t dev_addr, uint8_t instance) -//{ -// TU_VERIFY(tuh_n_hid_n_mounted(dev_addr, instance)); -// -// hidh_interface_t* hid_itf = get_instance(dev_addr, instance); -// return !usbh_edpt_busy(dev_addr, hid_itf->ep_in); -//} +bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx) +{ + hidh_interface_t* p_hid = get_hid_itf(dev_addr, idx); + TU_VERIFY(p_hid); + + return !usbh_edpt_busy(dev_addr, p_hid->ep_out); +} bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len) { diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h index c0c727e6a..08ad421d2 100644 --- a/src/class/hid/hid_host.h +++ b/src/class/hid/hid_host.h @@ -62,7 +62,7 @@ typedef struct // Interface API //--------------------------------------------------------------------+ -// Get the number of mounted HID interfaces of a device +// Get the total number of mounted HID interfaces of a device uint8_t tuh_hid_itf_get_count(uint8_t dev_addr); // Get all mounted interfaces across devices @@ -109,14 +109,17 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_ // Interrupt Endpoint API //--------------------------------------------------------------------+ -// Check if the interface is ready to use -//bool tuh_n_hid_n_ready(uint8_t dev_addr, uint8_t idx); +// Check if HID interface is ready to receive report +bool tuh_hid_receive_ready(uint8_t dev_addr, uint8_t idx); // Try to receive next report on Interrupt Endpoint. Immediately return // - true If succeeded, tuh_hid_report_received_cb() callback will be invoked when report is available // - false if failed to queue the transfer e.g endpoint is busy bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t idx); +// Check if HID interface is ready to send report +bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx); + // Send report using interrupt endpoint // If report_id > 0 (composite), it will be sent as 1st byte, then report contents. Otherwise only report content is sent. bool tuh_hid_send_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len); -- cgit v1.3.1 From 2cda9b60c99894db9a4610f80fc6f974f0499622 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Thu, 6 Apr 2023 15:45:23 -0700 Subject: Handle iMX RT 1042 usb naming --- src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src') diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h index 2de0d9cb4..607926a65 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h +++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h @@ -37,6 +37,11 @@ #define USB2_BASE USB_OTG2_BASE #endif +// RT1040 calls its only USB USB_OTG (no 1) +#if defined(MIMXRT1042_SERIES) +#define USB_OTG1_IRQn USB_OTG_IRQn +#endif + static const ci_hs_controller_t _ci_controller[] = { // RT1010 and RT1020 only has 1 USB controller -- cgit v1.3.1 From 413b0a7da5b9ef1e519e4087a577bfc6d6681d97 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 14 Apr 2023 17:12:47 +0200 Subject: Use PLL clock. --- hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h | 38 +++++++++++---------------- hw/bsp/stm32g0/family.c | 14 +++------- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 1 + 3 files changed, 21 insertions(+), 32 deletions(-) (limited to 'src') diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h index 3f5bc60b7..60357d1e8 100644 --- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h +++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h @@ -62,7 +62,7 @@ static inline void board_clock_init(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_CRSInitTypeDef pInit = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 }; /** Tick priority is used in HAL_RCC_OscConfig, so we need to enable it now */ @@ -75,38 +75,32 @@ static inline void board_clock_init(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI48; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; - RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; + RCC_OscInitStruct.PLL.PLLN = 12; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; HAL_RCC_OscConfig(&RCC_OscInitStruct); + /* Select HSI48 as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); - /** Enable the SYSCFG APB clock - */ - __HAL_RCC_CRS_CLK_ENABLE(); - - /** Configures CRS - */ - pInit.Prescaler = RCC_CRS_SYNC_DIV1; - pInit.Source = RCC_CRS_SYNC_SOURCE_USB; - pInit.Polarity = RCC_CRS_SYNC_POLARITY_RISING; - pInit.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000); - pInit.ErrorLimitValue = 34; - pInit.HSI48CalibrationValue = 32; - - HAL_RCCEx_CRSConfig(&pInit); } #ifdef __cplusplus diff --git a/hw/bsp/stm32g0/family.c b/hw/bsp/stm32g0/family.c index 585398974..be356efe9 100644 --- a/hw/bsp/stm32g0/family.c +++ b/hw/bsp/stm32g0/family.c @@ -53,6 +53,9 @@ void board_init(void) __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + UART_CLK_EN(); #if CFG_TUSB_OS == OPT_OS_NONE @@ -119,16 +122,7 @@ void board_init(void) __HAL_RCC_USB_CLK_ENABLE(); /* Enable VDDUSB */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - HAL_PWREx_EnableVddUSB(); - __HAL_RCC_PWR_CLK_DISABLE(); - } - else - { - HAL_PWREx_EnableVddUSB(); - } + HAL_PWREx_EnableVddUSB(); } //--------------------------------------------------------------------+ diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 36b9133be..23b328b49 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -44,6 +44,7 @@ * L0x2, L0x3 1024 byte buffer * L1 512 byte buffer * L4x2, L4x3 1024 byte buffer + * G0 2048 byte buffer * * To use this driver, you must: * - If you are using a device with crystal-less USB, set up the clock recovery system (CRS) -- cgit v1.3.1 From 2f2c8ce9ec4a567603cbd5e0420fc3dcaffbdfb6 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 14 Apr 2023 17:54:25 +0200 Subject: Fix GCC build. --- hw/bsp/board_mcu.h | 3 +++ hw/bsp/stm32g0/family.mk | 2 +- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 12 ++++++++++-- src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 11 +++++++++++ 4 files changed, 25 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index cd195a19b..6d40aa0d1 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -101,6 +101,9 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32U5 #include "stm32u5xx.h" +#elif CFG_TUSB_MCU == OPT_MCU_STM32G0 + #include "stm32g0xx.h" + #elif CFG_TUSB_MCU == OPT_MCU_CXD56 // no header needed diff --git a/hw/bsp/stm32g0/family.mk b/hw/bsp/stm32g0/family.mk index faf92dca9..76f59fc34 100644 --- a/hw/bsp/stm32g0/family.mk +++ b/hw/bsp/stm32g0/family.mk @@ -51,7 +51,7 @@ INC += \ $(TOP)/$(ST_HAL_DRIVER)/Inc # For freeRTOS port source -FREERTOS_PORT = ARM_CM0 +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 # flash target using on-board stlink flash: flash-stlink diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 23b328b49..32bab2bed 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -367,7 +367,11 @@ void dcd_int_enable (uint8_t rhport) NVIC_EnableIRQ(USBWakeUp_IRQn); #elif CFG_TUSB_MCU == OPT_MCU_STM32G0 - NVIC_EnableIRQ(USB_UCPD1_2_IRQn); + #ifdef STM32G0B0xx + NVIC_EnableIRQ(USB_IRQn); + #else + NVIC_EnableIRQ(USB_UCPD1_2_IRQn); + #endif #elif CFG_TUSB_MCU == OPT_MCU_STM32WB NVIC_EnableIRQ(USB_HP_IRQn); @@ -420,7 +424,11 @@ void dcd_int_disable(uint8_t rhport) NVIC_DisableIRQ(USBWakeUp_IRQn); #elif CFG_TUSB_MCU == OPT_MCU_STM32G0 - NVIC_DisableIRQ(USB_UCPD1_2_IRQn); + #ifdef STM32G0B0xx + NVIC_DisableIRQ(USB_IRQn); + #else + NVIC_DisableIRQ(USB_UCPD1_2_IRQn); + #endif #elif CFG_TUSB_MCU == OPT_MCU_STM32WB NVIC_DisableIRQ(USB_HP_IRQn); diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index c0f923c8f..32f715e6e 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -184,6 +184,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t si TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue) { #ifdef PMA_32BIT_ACCESS + (void) USBx; __O uint32_t *reg = (__O uint32_t *)(USB_DRD_BASE + bEpIdx*4); *reg = wRegValue; #else @@ -195,6 +196,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, ui /* GetENDPOINT */ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) { #ifdef PMA_32BIT_ACCESS + (void) USBx; __I uint32_t *reg = (__I uint32_t *)(USB_DRD_BASE + bEpIdx*4); #else __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpIdx*2u); @@ -249,6 +251,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) { #ifdef PMA_32BIT_ACCESS + (void) USBx; return (pma32[2*bEpIdx] & 0x03FF0000) >> 16; #else __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpIdx); @@ -259,6 +262,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USB TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) { #ifdef PMA_32BIT_ACCESS + (void) USBx; return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16; #else __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx); @@ -285,6 +289,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx, TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx) { #ifdef PMA_32BIT_ACCESS + (void) USBx; return pma32[2*bEpIdx] & 0x0000FFFFu ; #else return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u); @@ -294,6 +299,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx) { #ifdef PMA_32BIT_ACCESS + (void) USBx; return pma32[2*bEpIdx + 1] & 0x0000FFFFu; #else return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u); @@ -303,6 +309,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) { #ifdef PMA_32BIT_ACCESS + (void) USBx; pma32[2*bEpIdx] = (pma32[2*bEpIdx] & 0xFFFF0000u) | (addr & 0x0000FFFCu); #else *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u) = addr; @@ -312,6 +319,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USB TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) { #ifdef PMA_32BIT_ACCESS + (void) USBx; pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & 0xFFFF0000u) | (addr & 0x0000FFFCu); #else *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u) = addr; @@ -321,6 +329,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USB TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { #ifdef PMA_32BIT_ACCESS + (void) USBx; pma32[2*bEpIdx] = (pma32[2*bEpIdx] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16); #else __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpIdx); @@ -331,6 +340,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, u TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { #ifdef PMA_32BIT_ACCESS + (void) USBx; pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16); #else __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpIdx); @@ -342,6 +352,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDe { /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */ #ifdef PMA_32BIT_ACCESS + (void) USBx; pma32[rxtx_idx] = (pma32[rxtx_idx] & 0x0000FFFFu) | (blocksize << 31) | ((numblocks - blocksize) << 26); #else __IO uint16_t *pdwReg = pcd_btable_word_ptr(USBx, rxtx_idx*2u + 1u); -- cgit v1.3.1 From 818bda18c23e17c08c689b543d77ecc944681dea Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 14 Apr 2023 23:34:20 +0200 Subject: Fix FIFO transfer and buffer alignment. --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 166 +++++++++++++++++---- .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 2 +- 2 files changed, 142 insertions(+), 26 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 32bab2bed..b8d04331a 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -186,12 +186,12 @@ static void dcd_ep_ctr_handler(void); static uint8_t open_ep_count; static uint16_t ep_buf_ptr; ///< Points to first free memory location static void dcd_pma_alloc_reset(void); -static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length); +static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length); static void dcd_pma_free(uint8_t ep_addr); static void dcd_ep_free(uint8_t ep_addr); static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type); -static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes); -static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes); +static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes); +static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes); static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wNBytes); static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNBytes); @@ -792,7 +792,7 @@ static void dcd_pma_alloc_reset(void) * * During failure, TU_ASSERT is used. If this happens, rework/reallocate memory manually. */ -static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length) +static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length) { xfer_ctl_t* epXferCtl = xfer_ctl_ptr(ep_addr); @@ -804,6 +804,13 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length) return epXferCtl->pma_ptr; } + // Ensure allocated buffer is aligned +#ifdef PMA_32BIT_ACCESS + length = (length + 3) & ~0x03; +#else + length = (length + 1) & ~0x01; +#endif + open_ep_count++; uint16_t addr = ep_buf_ptr; @@ -814,7 +821,7 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length) epXferCtl->pma_ptr = addr; epXferCtl->pma_alloc_size = length; - //TU_LOG2("dcd_pma_alloc(%x,%x)=%x\r\n",ep_addr,length,addr); + //TU_LOG1("dcd_pma_alloc(%x,%x)=%x\r\n",ep_addr,length,addr); return addr; } @@ -1240,15 +1247,36 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) } #ifdef PMA_32BIT_ACCESS -static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes) +static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes) { - // FIXME original function uses byte-access to source memory (to support non-aligned buffers) - const uint32_t* src32 = (const uint32_t*)(src); + const uint8_t* srcVal = src; volatile uint32_t* dst32 = (volatile uint32_t*)(USB_PMAADDR + dst); - for (unsigned n=wNBytes/4; n>0; --n) { - *dst32++ = *src32++; + + for (uint32_t n = wNBytes / 4; n > 0; --n) { + *dst32++ = tu_unaligned_read32(srcVal); + srcVal += 4; + } + + wNBytes = wNBytes & 0x03; + if (wNBytes) + { + uint32_t wrVal = *srcVal; + wNBytes--; + + if (wNBytes) + { + wrVal |= *++srcVal << 8; + wNBytes--; + + if (wNBytes) + { + wrVal |= *++srcVal << 16; + } + } + + *dst32 = wrVal; } - *dst32 = (*src32) & ((1<<8*(wNBytes % 4)) - 1); + return true; } #else @@ -1263,7 +1291,7 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si * @param wNBytes no. of bytes to be copied. * @retval None */ -static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes) +static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes) { uint32_t n = (uint32_t)wNBytes >> 1U; uint16_t temp1, temp2; @@ -1286,7 +1314,7 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si srcVal++; } - if (wNBytes & 0x01) + if (wNBytes) { temp1 = *srcVal; *pdwVal = temp1; @@ -1313,7 +1341,37 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN // We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part, // last lin byte will be combined with wrapped part - // To ensure PMA is always access 16bit aligned (dst aligned to 16 bit) + // To ensure PMA is always access aligned (dst aligned to 16 or 32 bit) +#ifdef PMA_32BIT_ACCESS + if((cnt_lin & 0x03) && cnt_wrap) + { + // Copy first linear part + dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin &~0x03); + dst += cnt_lin &~0x03; + + // Copy last linear bytes & first wrapped bytes to buffer + uint32_t i; + uint8_t tmp[4]; + for (i = 0; i < (cnt_lin & 0x03); i++) + { + tmp[i] = ((uint8_t*)info.ptr_lin)[(cnt_lin &~0x03) + i]; + } + uint32_t wCnt = cnt_wrap; + for (; i < 4 && wCnt > 0; i++, wCnt--) + { + tmp[i] = *(uint8_t*)info.ptr_wrap; + info.ptr_wrap = (uint8_t*)info.ptr_wrap + 1; + } + + // Write unaligned buffer + dcd_write_packet_memory(dst, &tmp, 4); + dst += 4; + + // Copy rest of wrapped byte + if (wCnt) + dcd_write_packet_memory(dst, info.ptr_wrap, wCnt); + } +#else if((cnt_lin & 0x01) && cnt_wrap) { // Copy first linear part @@ -1328,6 +1386,7 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN // Copy rest of wrapped byte dcd_write_packet_memory(dst, ((uint8_t*)info.ptr_wrap) + 1, cnt_wrap - 1); } +#endif else { // Copy linear part @@ -1347,11 +1406,37 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN } #ifdef PMA_32BIT_ACCESS -static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes) +static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes) { - // FIXME this should probably be modified for possible unaligned access? - memcpy(dst, (void*)(USB_PMAADDR+src), wNBytes); - return true; + uint8_t* dstVal = dst; + volatile uint32_t* src32 = (volatile uint32_t*)(USB_PMAADDR + src); + + for (uint32_t n = wNBytes / 4; n > 0; --n) { + tu_unaligned_write32(dstVal, *src32++); + dstVal += 4; + } + + wNBytes = wNBytes & 0x03; + if (wNBytes) + { + uint32_t rdVal = *src32; + + *dstVal = tu_u32_byte0(rdVal); + wNBytes--; + + if (wNBytes) + { + *++dstVal = tu_u32_byte1(rdVal); + wNBytes--; + + if (wNBytes) + { + *++dstVal = tu_u32_byte2(rdVal); + } + } + } + + return true; } #else /** @@ -1360,7 +1445,7 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN * @param wNBytes no. of bytes to be copied. * @retval None */ -static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes) +static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes) { uint32_t n = (uint32_t)wNBytes >> 1U; // The GCC optimizer will combine access to 32-bit sizes if we let it. Force @@ -1405,9 +1490,39 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB uint16_t cnt_lin = TU_MIN(wNBytes, info.len_lin); uint16_t cnt_wrap = TU_MIN(wNBytes - cnt_lin, info.len_wrap); + // We want to read from PMA and write it into the FIFO, if LIN part is ODD and has WRAPPED part, // last lin byte will be combined with wrapped part - // To ensure PMA is always access 16bit aligned (src aligned to 16 bit) + // To ensure PMA is always access aligned (src aligned to 16 or 32 bit) +#ifdef PMA_32BIT_ACCESS + if((cnt_lin & 0x03) && cnt_wrap) + { + // Copy first linear part + dcd_read_packet_memory(info.ptr_lin, src, cnt_lin &~0x03); + src += cnt_lin &~0x03; + + // Copy last linear bytes & first wrapped bytes + uint8_t tmp[4]; + dcd_read_packet_memory(tmp, src, 4); + src += 4; + + uint32_t i; + for (i = 0; i < (cnt_lin & 0x03); i++) + { + ((uint8_t*)info.ptr_lin)[(cnt_lin &~0x03) + i] = tmp[i]; + } + uint32_t wCnt = cnt_wrap; + for (; i < 4 && wCnt > 0; i++, wCnt--) + { + *(uint8_t*)info.ptr_wrap = tmp[i]; + info.ptr_wrap = (uint8_t*)info.ptr_wrap + 1; + } + + // Copy rest of wrapped byte + if (wCnt) + dcd_read_packet_memory(info.ptr_wrap, src, wCnt); + } +#else if((cnt_lin & 0x01) && cnt_wrap) { // Copy first linear part @@ -1415,16 +1530,17 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB src += cnt_lin &~0x01; // Copy last linear byte & first wrapped byte - uint16_t tmp; - dcd_read_packet_memory(&tmp, src, 2); - - ((uint8_t*)info.ptr_lin)[cnt_lin - 1] = (uint8_t)tmp; - ((uint8_t*)info.ptr_wrap)[0] = (uint8_t)(tmp >> 8U); + uint8_t tmp[2]; + dcd_read_packet_memory(tmp, src, 2); src += 2; + ((uint8_t*)info.ptr_lin)[cnt_lin - 1] = tmp[0]; + ((uint8_t*)info.ptr_wrap)[0] = tmp[1]; + // Copy rest of wrapped byte dcd_read_packet_memory(((uint8_t*)info.ptr_wrap) + 1, src, cnt_wrap - 1); } +#endif else { // Copy linear part diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 32f715e6e..e6649de5a 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -85,7 +85,7 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32G0 #include "stm32g0xx.h" #define PMA_32BIT_ACCESS - #define PMA_LENGTH (1024u) // FIXME it is 2048, really + #define PMA_LENGTH (2048u) #undef USB_PMAADDR #define USB_PMAADDR USB_DRD_PMAADDR #define USB_TypeDef USB_DRD_TypeDef -- cgit v1.3.1 From d97b6d57de0b2586624dec51b37ccd699a0314a6 Mon Sep 17 00:00:00 2001 From: Reimu NotMoe Date: Mon, 17 Apr 2023 20:20:22 +0800 Subject: Fix compatibility with the latest Microchip XC16 compiler --- src/common/tusb_compiler.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index 713bbb8d4..a1794584d 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -138,10 +138,14 @@ #define TU_ATTR_BIT_FIELD_ORDER_BEGIN #define TU_ATTR_BIT_FIELD_ORDER_END - #if __has_attribute(__fallthrough__) - #define TU_ATTR_FALLTHROUGH __attribute__((fallthrough)) - #else + #if defined(__XC16) #define TU_ATTR_FALLTHROUGH do {} while (0) /* fallthrough */ + #else + #if __has_attribute(__fallthrough__) + #define TU_ATTR_FALLTHROUGH __attribute__((fallthrough)) + #else + #define TU_ATTR_FALLTHROUGH do {} while (0) /* fallthrough */ + #endif #endif // Endian conversion use well-known host to network (big endian) naming -- cgit v1.3.1 From fa8f3731c1b2e069dd07d30e86ea4a3af18c34dc Mon Sep 17 00:00:00 2001 From: Reimu NotMoe Date: Mon, 17 Apr 2023 21:02:12 +0800 Subject: Implement TU_BSWAP{16,32} correctly for Microchip XC16 --- src/common/tusb_compiler.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index a1794584d..dce32e92b 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -155,8 +155,17 @@ #define TU_BYTE_ORDER TU_BIG_ENDIAN #endif - #define TU_BSWAP16(u16) (__builtin_bswap16(u16)) - #define TU_BSWAP32(u32) (__builtin_bswap32(u32)) + // Unfortunately XC16 doesn't provide builtins for 32bit endian conversion + #if defined(__XC16) + #define TU_BSWAP16(u16) (__builtin_swap(u16)) + #define TU_BSWAP32(u32) ((((u32) & 0xff000000) >> 24) | \ + (((u32) & 0x00ff0000) >> 8) | \ + (((u32) & 0x0000ff00) << 8) | \ + (((u32) & 0x000000ff) << 24)) + #else + #define TU_BSWAP16(u16) (__builtin_bswap16(u16)) + #define TU_BSWAP32(u32) (__builtin_bswap32(u32)) + #endif #ifndef __ARMCC_VERSION // List of obsolete callback function that is renamed and should not be defined. -- cgit v1.3.1 From 412b557a080526fbfe7b42dd8aa07468c16413cc Mon Sep 17 00:00:00 2001 From: Mengsk Date: Mon, 17 Apr 2023 15:34:20 +0200 Subject: Cleanup unnecessary code for 16bit access. --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 39 +++++---------------------- 1 file changed, 7 insertions(+), 32 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index b8d04331a..14cabaf8d 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -210,17 +210,6 @@ TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr) return &xfer_status[epnum][dir]; } -// Using a function due to better type checks -// This seems better than having to do type casts everywhere else -TU_ATTR_ALWAYS_INLINE static inline void reg16_clear_bits(__IO uint16_t *reg, uint16_t mask) { - *reg = (uint16_t)(*reg & ~mask); -} - -// Bits in ISTR are cleared upon writing 0 -TU_ATTR_ALWAYS_INLINE static inline void clear_istr_bits(uint32_t mask) { - USB->ISTR = ~mask; -} - //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ @@ -244,11 +233,7 @@ void dcd_init (uint8_t rhport) asm("NOP"); } -#ifdef PMA_32BIT_ACCESS // CNTR register is 32bits on STM32G0, 16bit on older versions USB->CNTR &= ~USB_CNTR_PDWN; -#else - reg16_clear_bits(&USB->CNTR, USB_CNTR_PDWN);// Remove powerdown -#endif // Wait startup time, for F042 and F070, this is <= 1 us. for(uint32_t i = 0; i<200; i++) // should be a few us @@ -492,7 +477,6 @@ static void dcd_handle_bus_reset(void) //__IO uint16_t * const epreg = &(EPREG(0)); USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag - for(uint32_t i=0; iISTR &=~USB_ISTR_SOF; dcd_event_sof(0, USB->FNR & USB_FNR_FN, true); } if(int_status & USB_ISTR_RESET) { // USBRST is start of reset. - clear_istr_bits(USB_ISTR_RESET); + USB->ISTR &=~USB_ISTR_RESET; dcd_handle_bus_reset(); dcd_event_bus_reset(0, TUSB_SPEED_FULL, true); return; // Don't do the rest of the things here; perhaps they've been cleared? @@ -704,14 +688,10 @@ void dcd_int_handler(uint8_t rhport) { if (int_status & USB_ISTR_WKUP) { -#ifdef PMA_32BIT_ACCESS // CNTR register is 32bits on STM32G0, 16bit on older versions USB->CNTR &= ~USB_CNTR_LPMODE; USB->CNTR &= ~USB_CNTR_FSUSP; -#else - reg16_clear_bits(&USB->CNTR, USB_CNTR_LPMODE); - reg16_clear_bits(&USB->CNTR, USB_CNTR_FSUSP); -#endif - clear_istr_bits(USB_ISTR_WKUP); + + USB->ISTR &=~USB_ISTR_WKUP; dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); } @@ -725,7 +705,7 @@ void dcd_int_handler(uint8_t rhport) { USB->CNTR |= USB_CNTR_LPMODE; /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - clear_istr_bits(USB_ISTR_SUSP); + USB->ISTR &=~USB_ISTR_SUSP; dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); } @@ -738,7 +718,7 @@ void dcd_int_handler(uint8_t rhport) { { remoteWakeCountdown--; } - clear_istr_bits(USB_ISTR_ESOF); + USB->ISTR &=~USB_ISTR_ESOF; } } @@ -759,13 +739,8 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re uint8_t const dev_addr = (uint8_t) request->wValue; // Setting new address after the whole request is complete -#ifdef PMA_32BIT_ACCESS USB->DADDR &= ~USB_DADDR_ADD; - USB->DADDR = (USB->DADDR & ~USB_DADDR_ADD_Msk) | dev_addr; // leave the enable bit set -#else - reg16_clear_bits(&USB->DADDR, USB_DADDR_ADD); - USB->DADDR = (uint16_t)(USB->DADDR | dev_addr); // leave the enable bit set -#endif + USB->DADDR |= dev_addr; // leave the enable bit set } } -- cgit v1.3.1 From 9002dc706711741b6db2c53de4e5b94b02322f37 Mon Sep 17 00:00:00 2001 From: Reimu NotMoe Date: Tue, 18 Apr 2023 17:27:42 +0800 Subject: Use __GNUC__ macro to determine if __has_attribute is supported --- src/common/tusb_compiler.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index dce32e92b..5ab56e145 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -138,7 +138,7 @@ #define TU_ATTR_BIT_FIELD_ORDER_BEGIN #define TU_ATTR_BIT_FIELD_ORDER_END - #if defined(__XC16) + #if __GNUC__ < 5 #define TU_ATTR_FALLTHROUGH do {} while (0) /* fallthrough */ #else #if __has_attribute(__fallthrough__) -- cgit v1.3.1 From 9bf97e3e52c09e2f7279ee37a86ec0b38275c494 Mon Sep 17 00:00:00 2001 From: Jacek Fedorynski Date: Thu, 13 Apr 2023 20:04:04 +0200 Subject: [rp2040] Make writes to SIE_CTRL aware of concurrent access This commit makes it so that when setting the START_TRANS bit in the SIE_CTRL register, along with some other bits, we first set all the other bits, then wait some cycles, and then set the START_TRANS bit. Doing so protects against a situation where the USB controller is reading the register at the same time and gets an incorrect value. This mirrors the procedure already applied to buffer control registers. --- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 661255cf6..02f9968a7 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -562,6 +562,11 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | SIE_CTRL_BASE | (ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS) | (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0); + // START_TRANS bit on SIE_CTRL seems to exhibit the same behavior as the AVAILABLE bit + // described in RP2040 Datasheet, release 2.1, section "4.1.2.5.1. Concurrent access". + // We write everything except the START_TRANS bit first, then wait some cycles. + usb_hw->sie_ctrl = flags & ~USB_SIE_CTRL_START_TRANS_BITS; + busy_wait_at_least_cycles(12); usb_hw->sie_ctrl = flags; }else { @@ -602,6 +607,11 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet uint32_t const flags = SIE_CTRL_BASE | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS | (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0); + // START_TRANS bit on SIE_CTRL seems to exhibit the same behavior as the AVAILABLE bit + // described in RP2040 Datasheet, release 2.1, section "4.1.2.5.1. Concurrent access". + // We write everything except the START_TRANS bit first, then wait some cycles. + usb_hw->sie_ctrl = flags & ~USB_SIE_CTRL_START_TRANS_BITS; + busy_wait_at_least_cycles(12); usb_hw->sie_ctrl = flags; return true; -- cgit v1.3.1 From 0afe1b36842c1542293e2133212aa0cfca9608c8 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 21 Apr 2023 18:10:28 +0700 Subject: example run well with cmake for imxrt --- examples/device/board_test/CMakeLists.txt | 39 +++------------------- examples/device/cdc_msc/CMakeLists.txt | 2 +- examples/device/msc_dual_lun/CMakeLists.txt | 21 +++++++----- hw/bsp/imxrt/family.cmake | 50 ++++++++++++++++++----------- src/CMakeLists.txt | 25 +++++++++++++++ 5 files changed, 74 insertions(+), 63 deletions(-) create mode 100644 src/CMakeLists.txt (limited to 'src') diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt index 835d15488..c48efdaa5 100644 --- a/examples/device/board_test/CMakeLists.txt +++ b/examples/device/board_test/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.13) +cmake_minimum_required(VERSION 3.17) include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) @@ -27,37 +27,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -if(FAMILY STREQUAL "rp2040") - # Configure compilation flags and libraries for the example... see the corresponding function - # in hw/bsp/FAMILY/family.cmake for details. - family_configure_device_example(${PROJECT}) -else () - # TOP is absolute path to root directory of TinyUSB git repo - set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..") - get_filename_component(TOP "${TOP}" REALPATH) - - # re-include family.cmake - include(${TOP}/hw/bsp/${FAMILY}/family.cmake) - - target_sources(${PROJECT} PUBLIC - ${TOP}/src/device/usbd.c - ${TOP}/src/device/usbd_control.c - ${TOP}/src/class/audio/audio_device.c - ${TOP}/src/class/cdc/cdc_device.c - ${TOP}/src/class/dfu/dfu_device.c - ${TOP}/src/class/dfu/dfu_rt_device.c - ${TOP}/src/class/hid/hid_device.c - ${TOP}/src/class/midi/midi_device.c - ${TOP}/src/class/msc/msc_device.c - ${TOP}/src/class/net/ecm_rndis_device.c - ${TOP}/src/class/net/ncm_device.c - ${TOP}/src/class/usbtmc/usbtmc_device.c - ${TOP}/src/class/vendor/vendor_device.c - ${TOP}/src/class/video/video_device.c - ) - - target_include_directories(${PROJECT} PUBLIC - ${TOP}/hw - ${TOP}/src - ) -endif () +# Configure compilation flags and libraries for the example... see the corresponding function +# in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT}) diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt index 43b81ce23..7eddc2422 100644 --- a/examples/device/cdc_msc/CMakeLists.txt +++ b/examples/device/cdc_msc/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.13) +cmake_minimum_required(VERSION 3.17) include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) diff --git a/examples/device/msc_dual_lun/CMakeLists.txt b/examples/device/msc_dual_lun/CMakeLists.txt index 9188ab06c..dc8d5512c 100644 --- a/examples/device/msc_dual_lun/CMakeLists.txt +++ b/examples/device/msc_dual_lun/CMakeLists.txt @@ -1,28 +1,33 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.17) include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) # gets PROJECT name for the example (e.g. -) family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) -project(${PROJECT}) +project(${PROJECT} C CXX ASM) # Checks this example is valid for the family and initializes the project family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) +# Espressif has its own cmake build system +if(FAMILY STREQUAL "espressif") + return() +endif() + add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk_dual.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk_dual.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c + ) # Example include target_include_directories(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 7da81dfb6..d1d28d4eb 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -1,23 +1,27 @@ +# toolchain set up +set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../cmake/toolchain/arm_${TOOLCHAIN}.cmake) - -if (NOT TARGET ${PROJECT}) - # toolchain set up, include before project() - set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor") - set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../cmake/toolchain/arm_${TOOLCHAIN}.cmake) -else () +function(family_configure_target TARGET) if (NOT BOARD) message(FATAL_ERROR "BOARD not specified") endif () + # set output name to .elf + set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf) + + # TOP is absolute path to root directory of TinyUSB git repo + set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..") + get_filename_component(TOP "${TOP}" REALPATH) + set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk) set(DEPS_SUBMODULES ${SDK_DIR}) - # include basic family CMake functionality - #set(FAMILY_MCUS RP2040) + include(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board.cmake) - include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + cmake_print_variables(TOP CMAKE_CURRENT_FUNCTION_LIST_DIR) - target_compile_definitions(${PROJECT} PUBLIC + target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_MCU=OPT_MCU_MIMXRT __ARMVFP__=0 __ARMFPV5__=0 @@ -25,18 +29,18 @@ else () XIP_BOOT_HEADER_ENABLE=1 ) - target_link_options(${PROJECT} PUBLIC + target_link_options(${TARGET} PUBLIC --specs=nosys.specs --specs=nano.specs ) - target_sources(${PROJECT} PUBLIC + target_sources(${TARGET} PUBLIC # TinyUSB ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c ${TOP}/src/portable/ehci/ehci.c # BSP - ${CMAKE_CURRENT_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${SDK_DIR}/drivers/common/fsl_common.c ${SDK_DIR}/drivers/igpio/fsl_gpio.c ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c @@ -47,18 +51,19 @@ else () ) if (TOOLCHAIN STREQUAL "gcc") - target_sources(${PROJECT} PUBLIC + target_sources(${TARGET} PUBLIC ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S ) - target_link_options(${PROJECT} PUBLIC + target_link_options(${TARGET} PUBLIC "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld" ) endif () - target_include_directories(${PROJECT} PUBLIC - ${CMAKE_CURRENT_LIST_DIR} - ${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD} + target_include_directories(${TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ${SDK_DIR}/CMSIS/Include ${SDK_DIR}/devices/${MCU_VARIANT} ${SDK_DIR}/devices/${MCU_VARIANT}/project_template @@ -67,4 +72,11 @@ else () ${SDK_DIR}/drivers/igpio ${SDK_DIR}/drivers/lpuart ) -endif () + + # include tinyusb cmake + include(${TOP}/src/CMakeLists.txt) +endfunction() + +function(family_configure_device_example TARGET) + family_configure_target(${TARGET}) +endfunction() diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt new file mode 100644 index 000000000..ade4c2c85 --- /dev/null +++ b/src/CMakeLists.txt @@ -0,0 +1,25 @@ +# cmake_minimum_required(VERSION 3.17) +# TODO make tinyusb as library that depends on 'tusb_config' interface that exposes the tusb_config.h file + +target_sources(${PROJECT} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/tusb.c + ${CMAKE_CURRENT_LIST_DIR}/common/tusb_fifo.c + ${CMAKE_CURRENT_LIST_DIR}/device/usbd.c + ${CMAKE_CURRENT_LIST_DIR}/device/usbd_control.c + ${CMAKE_CURRENT_LIST_DIR}/class/audio/audio_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/cdc/cdc_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_rt_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/hid/hid_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/midi/midi_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/msc/msc_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/net/ecm_rndis_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/net/ncm_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/usbtmc/usbtmc_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/vendor/vendor_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/video/video_device.c + ) + +target_include_directories(${PROJECT} PUBLIC + ${CMAKE_CURRENT_LIST_DIR} + ) -- cgit v1.3.1 From 5254202b203ee58e2fdb319c85e2ae1a87518140 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 24 Apr 2023 11:54:58 +0700 Subject: minor update --- cmake/toolchain/arm_gcc.cmake | 35 +++++++++++++++++++++++++++++ cmake/toolchain/set_flags.cmake | 36 ++++++++++++++--------------- hw/bsp/imxrt/family.cmake | 4 ++-- src/CMakeLists.txt | 50 ++++++++++++++++++++++++----------------- 4 files changed, 83 insertions(+), 42 deletions(-) (limited to 'src') diff --git a/cmake/toolchain/arm_gcc.cmake b/cmake/toolchain/arm_gcc.cmake index 44683118e..c5937192e 100644 --- a/cmake/toolchain/arm_gcc.cmake +++ b/cmake/toolchain/arm_gcc.cmake @@ -16,4 +16,39 @@ set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) set(CMAKE_TRY_COMPILE_PLATFORM_VARIABLES CMAKE_SYSTEM_PROCESSOR) include(${CMAKE_CURRENT_LIST_DIR}/../cpu/${CMAKE_SYSTEM_PROCESSOR}.cmake) + +# enable all possible warnings for building examples +list(APPEND TOOLCHAIN_COMMON_FLAGS + -fdata-sections + -ffunction-sections + -fsingle-precision-constant + -fno-strict-aliasing + ) + +set(TOOLCHAIN_WARNING_FLAGS + -Wall + -Wextra + -Werror + -Wfatal-errors + -Wdouble-promotion + -Wstrict-prototypes + -Wstrict-overflow + -Werror-implicit-function-declaration + -Wfloat-equal + -Wundef + -Wshadow + -Wwrite-strings + -Wsign-compare + -Wmissing-format-attribute + -Wunreachable-code + -Wcast-align + -Wcast-function-type + -Wcast-qual + -Wnull-dereference + -Wuninitialized + -Wunused + -Wreturn-type + -Wredundant-decls + ) + include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake) diff --git a/cmake/toolchain/set_flags.cmake b/cmake/toolchain/set_flags.cmake index e6c7b6feb..da381c254 100644 --- a/cmake/toolchain/set_flags.cmake +++ b/cmake/toolchain/set_flags.cmake @@ -1,22 +1,20 @@ -get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE) - -# join the toolchain flags into a single string -list(JOIN TOOLCHAIN_COMMON_FLAGS " " TOOLCHAIN_COMMON_FLAGS) - +include(CMakePrintHelpers) foreach(LANG IN ITEMS C CXX ASM) - set(CMAKE_${LANG}_FLAGS_INIT "${TOOLCHAIN_COMMON_FLAGS}") - if (PICO_DEOPTIMIZED_DEBUG) - set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-O0") - else() - set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-Og") - endif() - set(CMAKE_${LANG}_LINK_FLAGS "-Wl,--build-id=none") + # join the toolchain flags into a single string + list(APPEND TOOLCHAIN_${LANG}_FLAGS ${TOOLCHAIN_COMMON_FLAGS}) + list(JOIN TOOLCHAIN_${LANG}_FLAGS " " TOOLCHAIN_${LANG}_FLAGS) + set(CMAKE_${LANG}_FLAGS_INIT "${TOOLCHAIN_${LANG}_FLAGS}") - # try_compile is where the feature testing is done, and at that point, - # pico_standard_link is not ready to be linked in to provide essential - # functions like _exit. So pass -nostdlib so it doesn't link in an exit() - # function at all. - if(IS_IN_TRY_COMPILE) - set(CMAKE_${LANG}_LINK_FLAGS "${CMAKE_${LANG}_LINK_FLAGS} -nostdlib") - endif() + #cmake_print_variables(CMAKE_${LANG}_FLAGS_INIT) + + # optimization flags + set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-Og") endforeach() + +# try_compile is cmake test compiling its own example, +# pass -nostdlib to skip stdlib linking +get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE) +if(IS_IN_TRY_COMPILE) + set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib") + set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib") +endif() diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 40b8ab974..e36adaf5a 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -19,8 +19,6 @@ function(family_configure_target TARGET) include(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board.cmake) - cmake_print_variables(TOP CMAKE_CURRENT_FUNCTION_LIST_DIR) - target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_MCU=OPT_MCU_MIMXRT __ARMVFP__=0 @@ -77,6 +75,8 @@ function(family_configure_target TARGET) # include tinyusb cmake include(${TOP}/src/CMakeLists.txt) + add_tinyusb(${TARGET}) + endfunction() function(family_add_freertos_config TARGET) diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index ade4c2c85..00755df95 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -1,25 +1,33 @@ # cmake_minimum_required(VERSION 3.17) # TODO make tinyusb as library that depends on 'tusb_config' interface that exposes the tusb_config.h file -target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_LIST_DIR}/tusb.c - ${CMAKE_CURRENT_LIST_DIR}/common/tusb_fifo.c - ${CMAKE_CURRENT_LIST_DIR}/device/usbd.c - ${CMAKE_CURRENT_LIST_DIR}/device/usbd_control.c - ${CMAKE_CURRENT_LIST_DIR}/class/audio/audio_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/cdc/cdc_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_rt_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/hid/hid_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/midi/midi_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/msc/msc_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/net/ecm_rndis_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/net/ncm_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/usbtmc/usbtmc_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/vendor/vendor_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/video/video_device.c - ) +function(add_tinyusb TARGET) + target_sources(${TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/common/tusb_fifo.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd_control.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/audio/audio_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/cdc/cdc_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_rt_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/midi/midi_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ecm_rndis_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ncm_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/usbtmc/usbtmc_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/video/video_device.c + ) -target_include_directories(${PROJECT} PUBLIC - ${CMAKE_CURRENT_LIST_DIR} - ) + target_include_directories(${TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ) + + # enable all possible warnings + target_compile_options(${TARGET} PUBLIC + + ) + +endfunction() -- cgit v1.3.1 From a4d5d515493187437731eae830cb4b173fd11c02 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 24 Apr 2023 16:24:06 +0700 Subject: add wip note --- .idea/runConfigurations/cdc_msc.xml | 10 ---------- .idea/runConfigurations/hid_composite.xml | 10 ---------- .idea/runConfigurations/msc_dual_lun.xml | 10 ---------- .idea/runConfigurations/rt1010.xml | 10 ---------- src/CMakeLists.txt | 4 +++- 5 files changed, 3 insertions(+), 41 deletions(-) delete mode 100644 .idea/runConfigurations/cdc_msc.xml delete mode 100644 .idea/runConfigurations/hid_composite.xml delete mode 100644 .idea/runConfigurations/msc_dual_lun.xml delete mode 100644 .idea/runConfigurations/rt1010.xml (limited to 'src') diff --git a/.idea/runConfigurations/cdc_msc.xml b/.idea/runConfigurations/cdc_msc.xml deleted file mode 100644 index fbeb4ae05..000000000 --- a/.idea/runConfigurations/cdc_msc.xml +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - \ No newline at end of file diff --git a/.idea/runConfigurations/hid_composite.xml b/.idea/runConfigurations/hid_composite.xml deleted file mode 100644 index b9f1d1a72..000000000 --- a/.idea/runConfigurations/hid_composite.xml +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - \ No newline at end of file diff --git a/.idea/runConfigurations/msc_dual_lun.xml b/.idea/runConfigurations/msc_dual_lun.xml deleted file mode 100644 index 5c1ea270b..000000000 --- a/.idea/runConfigurations/msc_dual_lun.xml +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - \ No newline at end of file diff --git a/.idea/runConfigurations/rt1010.xml b/.idea/runConfigurations/rt1010.xml deleted file mode 100644 index 50659c95c..000000000 --- a/.idea/runConfigurations/rt1010.xml +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - \ No newline at end of file diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 00755df95..a270ea8b7 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -1,5 +1,7 @@ -# cmake_minimum_required(VERSION 3.17) # TODO make tinyusb as library that depends on 'tusb_config' interface that exposes the tusb_config.h file +# This file is WIP and should not used yet + +cmake_minimum_required(VERSION 3.17) function(add_tinyusb TARGET) target_sources(${TARGET} PUBLIC -- cgit v1.3.1 From 45169d833d05ec8b64d0ce11a5ff1efbea0b7917 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 26 Apr 2023 12:43:46 +0700 Subject: hacky, but ftdi work with hard code baudrate = 9600 --- .codespell/ignore-words.txt | 1 + src/class/cdc/cdc_host.c | 366 ++++++++++++++++++++++++++++++--------- src/class/cdc/serial/ftdi_host.h | 258 +++++++++++++++++++++++++++ src/host/usbh.c | 2 +- src/tusb_option.h | 5 + 5 files changed, 549 insertions(+), 83 deletions(-) create mode 100644 src/class/cdc/serial/ftdi_host.h (limited to 'src') diff --git a/.codespell/ignore-words.txt b/.codespell/ignore-words.txt index 5c89bae1c..2513691cb 100644 --- a/.codespell/ignore-words.txt +++ b/.codespell/ignore-words.txt @@ -1,6 +1,7 @@ synopsys sie tre +thre hsi fro dout diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index c0cc41adf..7949ff8d3 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -33,6 +33,10 @@ #include "cdc_host.h" +#if CFG_TUH_CDC_FTDI + #include "serial/ftdi_host.h" +#endif + // Debug level, TUSB_CFG_DEBUG must be at least this level for debug message #define CDCH_DEBUG 2 @@ -43,12 +47,18 @@ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ +enum { + SERIAL_PROTOCOL_ACM = 0, + SERIAL_PROTOCOL_FTDI = 1, +}; + typedef struct { uint8_t daddr; uint8_t bInterfaceNumber; uint8_t bInterfaceSubClass; uint8_t bInterfaceProtocol; + uint8_t serial_protocol; cdc_acm_capability_t acm_capability; uint8_t ep_notif; @@ -111,6 +121,11 @@ static cdch_interface_t* find_new_itf(void) return NULL; } +static inline bool support_line_request(cdch_interface_t const* p_cdc) { + return (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM && p_cdc->acm_capability.support_line_request) || + (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI); +} + //--------------------------------------------------------------------+ // APPLICATION API //--------------------------------------------------------------------+ @@ -270,21 +285,32 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) if (xfer->result == XFER_RESULT_SUCCESS) { - switch(xfer->setup->bRequest) - { - case CDC_REQUEST_SET_CONTROL_LINE_STATE: - p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue); - break; - - case CDC_REQUEST_SET_LINE_CODING: - { - uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength)); - memcpy(&p_cdc->line_coding, xfer->buffer, len); + if (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM) { + switch (xfer->setup->bRequest) { + case CDC_REQUEST_SET_CONTROL_LINE_STATE: + p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue); + break; + + case CDC_REQUEST_SET_LINE_CODING: { + uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength)); + memcpy(&p_cdc->line_coding, xfer->buffer, len); + } + break; + + default: break; + } + } + #if CFG_TUH_CDC_FTDI + else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) { + switch (xfer->setup->bRequest) { + case FTDI_SIO_MODEM_CTRL: + p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff); + break; + + default: break; } - break; - - default: break; } + #endif } xfer->complete_cb = p_cdc->user_control_cb; @@ -294,27 +320,51 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc && p_cdc->acm_capability.support_line_request); + TU_VERIFY(p_cdc && support_line_request(p_cdc)); TU_LOG_CDCH("CDC Set Control Line State\r\n"); - tusb_control_request_t const request = - { - .bmRequestType_bit = - { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_CLASS, - .direction = TUSB_DIR_OUT - }, - .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE, - .wValue = tu_htole16(line_state), - .wIndex = tu_htole16((uint16_t) p_cdc->bInterfaceNumber), - .wLength = 0 - }; + tusb_control_request_t request; + + if(p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM ) { + tusb_control_request_t const acm_request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_CLASS, + .direction = TUSB_DIR_OUT + }, + .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE, + .wValue = tu_htole16(line_state), + .wIndex = tu_htole16((uint16_t) p_cdc->bInterfaceNumber), + .wLength = 0 + }; + + request = acm_request; + } + #if CFG_TUH_CDC_FTDI + else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) { + // FTDI use vendor specific request to set control line state + tusb_control_request_t const ftdi_request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_VENDOR, + .direction = TUSB_DIR_OUT + }, + .bRequest = FTDI_SIO_MODEM_CTRL, + .wValue = tu_htole16(0x0300 | line_state), // 0x0300 is DTR and RTS enable + .wIndex = 0, // port + .wLength = 0 + }; + + request = ftdi_request; + } + #endif + else { + return false; + } p_cdc->user_control_cb = complete_cb; - tuh_xfer_t xfer = - { + tuh_xfer_t xfer = { .daddr = p_cdc->daddr, .ep_addr = 0, .setup = &request, @@ -324,34 +374,60 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c }; TU_ASSERT(tuh_control_xfer(&xfer)); + return true; } bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc && p_cdc->acm_capability.support_line_request); + TU_VERIFY(p_cdc && support_line_request(p_cdc)); TU_LOG_CDCH("CDC Set Line Conding\r\n"); - tusb_control_request_t const request = - { - .bmRequestType_bit = - { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_CLASS, - .direction = TUSB_DIR_OUT - }, - .bRequest = CDC_REQUEST_SET_LINE_CODING, - .wValue = 0, - .wIndex = tu_htole16(p_cdc->bInterfaceNumber), - .wLength = tu_htole16(sizeof(cdc_line_coding_t)) - }; - - // use usbh enum buf to hold line coding since user line_coding variable may not live long enough - // for the transfer to complete - uint8_t* enum_buf = usbh_get_enum_buf(); - memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t)); + tusb_control_request_t request; + uint8_t* enum_buf = NULL; + + if (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM) { + tusb_control_request_t const acm_request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_CLASS, + .direction = TUSB_DIR_OUT + }, + .bRequest = CDC_REQUEST_SET_LINE_CODING, + .wValue = 0, + .wIndex = tu_htole16(p_cdc->bInterfaceNumber), + .wLength = tu_htole16(sizeof(cdc_line_coding_t)) + }; + + request = acm_request; + + // use usbh enum buf to hold line coding since user line_coding variable does not live long enough + enum_buf = usbh_get_enum_buf(); + memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t)); + } + #if CFG_TUH_CDC_FTDI + else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) { + // FTDI need to set baud rate and data bits, parity, stop bits separately + tusb_control_request_t const ftdi_request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_VENDOR, + .direction = TUSB_DIR_OUT + }, + .bRequest = FTDI_SIO_SET_BAUD_RATE, + .wValue = 0x4138, // FIXME hardcoded to 9600 baud + .wIndex = 0, // port + .wLength = tu_htole16(sizeof(cdc_line_coding_t)) + }; + + request = ftdi_request; + } + #endif + else { + return false; + } p_cdc->user_control_cb = complete_cb; tuh_xfer_t xfer = @@ -434,8 +510,17 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t { tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes); + #if CFG_TUH_CDC_FTDI + // FTDI reserve 2 bytes for status + if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) { + uint8_t status[2]; + tu_edpt_stream_read(&p_cdc->stream.rx, status, 2); + (void) status; // TODO handle status + } + #endif + // invoke receive callback - if (tuh_cdc_rx_cb) tuh_cdc_rx_cb(idx); + if (tuh_cdc_rx_cb) tuh_cdc_rx_cb(idx); // prepare for next transfer if needed tu_edpt_stream_read_xfer(&p_cdc->stream.rx); @@ -453,17 +538,99 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t //--------------------------------------------------------------------+ // Enumeration //--------------------------------------------------------------------+ +enum +{ + // ACM + CONFIG_SET_CONTROL_LINE_STATE, + CONFIG_SET_LINE_CODING, + CONFIG_COMPLETE, -bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) + // FTDI + CONFIG_FTDI_RESET +}; + +static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep) { - (void) rhport; + for(size_t i=0; i<2; i++) + { + TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && + TUSB_XFER_BULK == desc_ep->bmAttributes.xfer); - // Only support ACM subclass - // Protocol 0xFF can be RNDIS device for windows XP - TU_VERIFY( TUSB_CLASS_CDC == itf_desc->bInterfaceClass && - CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass && - 0xFF != itf_desc->bInterfaceProtocol); + TU_ASSERT(tuh_edpt_open(p_cdc->daddr, desc_ep)); + + if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN ) + { + tu_edpt_stream_open(&p_cdc->stream.rx, p_cdc->daddr, desc_ep); + }else + { + tu_edpt_stream_open(&p_cdc->stream.tx, p_cdc->daddr, desc_ep); + } + + desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(desc_ep); + } + + return true; +} + +#if CFG_TUH_CDC_FTDI +bool ftdih_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { + // FTDI configuration includes 1 vendor interface + 2 bulk endpoints + TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2); + TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); + + cdch_interface_t * p_cdc = find_new_itf(); + TU_VERIFY(p_cdc); + + p_cdc->daddr = daddr; + p_cdc->bInterfaceNumber = itf_desc->bInterfaceNumber; + p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass; + p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol; + p_cdc->line_state = 0; + p_cdc->serial_protocol = SERIAL_PROTOCOL_FTDI; + + // endpoint pair + tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); + + // data endpoints expected to be in pairs + TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep)); + + return true; +} + +static bool ftdih_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_DEVICE, + .type = TUSB_REQ_TYPE_VENDOR, + .direction = TUSB_DIR_OUT + }, + .bRequest = FTDI_SIO_RESET, + .wValue = tu_htole16(FTDI_SIO_RESET_SIO), + .wIndex = 0, + .wLength = 0 + }; + + p_cdc->user_control_cb = complete_cb; + + tuh_xfer_t xfer = { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request, + .buffer = NULL, + .complete_cb = complete_cb, + .user_data = user_data + }; + + TU_ASSERT(tuh_control_xfer(&xfer)); + return true; +} +#endif + + +static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) +{ uint8_t const * p_desc_end = ((uint8_t const*) itf_desc) + max_len; cdch_interface_t * p_cdc = find_new_itf(); @@ -474,6 +641,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass; p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol; p_cdc->line_state = 0; + p_cdc->serial_protocol = SERIAL_PROTOCOL_ACM; //------------- Control Interface -------------// uint8_t const * p_desc = tu_desc_next(itf_desc); @@ -510,36 +678,46 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d p_desc = tu_desc_next(p_desc); // data endpoints expected to be in pairs - for(uint32_t i=0; i<2; i++) - { - tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc; - TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && - TUSB_XFER_BULK == desc_ep->bmAttributes.xfer); + TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const *) p_desc)); + } - TU_ASSERT(tuh_edpt_open(daddr, desc_ep)); + return true; +} - if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN ) - { - tu_edpt_stream_open(&p_cdc->stream.rx, daddr, desc_ep); - }else - { - tu_edpt_stream_open(&p_cdc->stream.tx, daddr, desc_ep); - } - p_desc = tu_desc_next(p_desc); +bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) +{ + (void) rhport; + + // Only support ACM subclass + // Note: Protocol 0xFF can be RNDIS device + if ( TUSB_CLASS_CDC == itf_desc->bInterfaceClass && + CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) + { + return acm_open(daddr, itf_desc, max_len); + } + else if ( 0xff == itf_desc->bInterfaceClass ) + { + uint16_t vid, pid; + TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid)); + +#if CFG_TUH_CDC_FTDI + if (TU_FTDI_VID == vid) { + uint16_t const ftdi_pids[] = {TU_FTDI_PID_LIST}; + enum { FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0]) }; + + for (size_t i = 0; i < FTDI_PID_COUNT; i++) { + if (ftdi_pids[i] == pid) { + return ftdih_open(daddr, itf_desc, max_len); + } + } } +#endif } - return true; + return false; } -enum -{ - CONFIG_SET_CONTROL_LINE_STATE, - CONFIG_SET_LINE_CODING, - CONFIG_COMPLETE -}; - static void process_cdc_config(tuh_xfer_t* xfer) { uintptr_t const state = xfer->user_data; @@ -550,9 +728,16 @@ static void process_cdc_config(tuh_xfer_t* xfer) switch(state) { + #if CFG_TUH_CDC_FTDI + // Note may need to read FTDI eeprom + case CONFIG_FTDI_RESET: + TU_ASSERT(ftdih_sio_reset(p_cdc, process_cdc_config, CONFIG_SET_CONTROL_LINE_STATE), ); + break; + #endif + case CONFIG_SET_CONTROL_LINE_STATE: #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - if (p_cdc->acm_capability.support_line_request) + if (support_line_request(p_cdc)) { TU_ASSERT( tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cdc_config, CONFIG_SET_LINE_CODING), ); break; @@ -562,7 +747,7 @@ static void process_cdc_config(tuh_xfer_t* xfer) case CONFIG_SET_LINE_CODING: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - if (p_cdc->acm_capability.support_line_request) + if (support_line_request(p_cdc)) { cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, CONFIG_COMPLETE), ); @@ -588,7 +773,6 @@ static void process_cdc_config(tuh_xfer_t* xfer) bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { - // fake transfer to kick-off process tusb_control_request_t request; request.wIndex = tu_htole16((uint16_t) itf_num); @@ -596,7 +780,25 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) xfer.daddr = daddr; xfer.result = XFER_RESULT_SUCCESS; xfer.setup = &request; - xfer.user_data = CONFIG_SET_CONTROL_LINE_STATE; + + // fake transfer to kick-off process + uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num); + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc); + + switch (p_cdc->serial_protocol) { + case SERIAL_PROTOCOL_ACM: + xfer.user_data = CONFIG_SET_CONTROL_LINE_STATE; + break; + + #if CFG_TUH_CDC_FTDI + case SERIAL_PROTOCOL_FTDI: + xfer.user_data = CONFIG_FTDI_RESET; + break; + #endif + + default: return false; + } process_cdc_config(&xfer); diff --git a/src/class/cdc/serial/ftdi_host.h b/src/class/cdc/serial/ftdi_host.h new file mode 100644 index 000000000..4276d374e --- /dev/null +++ b/src/class/cdc/serial/ftdi_host.h @@ -0,0 +1,258 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (thach@tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef TUSB_FTDI_HOST_H +#define TUSB_FTDI_HOST_H + +// VID/PID for matching FTDI devices +#define TU_FTDI_VID 0x0403 +#define TU_FTDI_PID_LIST \ + 0x6001, 0x6006, 0x6010, 0x6011, 0x6014, 0x6015, 0x8372, 0xFBFA, \ + 0xcd18 + +// Commands +#define FTDI_SIO_RESET 0 /* Reset the port */ +#define FTDI_SIO_MODEM_CTRL 1 /* Set the modem control register */ +#define FTDI_SIO_SET_FLOW_CTRL 2 /* Set flow control register */ +#define FTDI_SIO_SET_BAUD_RATE 3 /* Set baud rate */ +#define FTDI_SIO_SET_DATA 4 /* Set the data characteristics of the port */ +#define FTDI_SIO_GET_MODEM_STATUS 5 /* Retrieve current value of modem status register */ +#define FTDI_SIO_SET_EVENT_CHAR 6 /* Set the event character */ +#define FTDI_SIO_SET_ERROR_CHAR 7 /* Set the error character */ +#define FTDI_SIO_SET_LATENCY_TIMER 9 /* Set the latency timer */ +#define FTDI_SIO_GET_LATENCY_TIMER 0x0a /* Get the latency timer */ +#define FTDI_SIO_SET_BITMODE 0x0b /* Set bitbang mode */ +#define FTDI_SIO_READ_PINS 0x0c /* Read immediate value of pins */ +#define FTDI_SIO_READ_EEPROM 0x90 /* Read EEPROM */ + +/* FTDI_SIO_RESET */ +#define FTDI_SIO_RESET_SIO 0 +#define FTDI_SIO_RESET_PURGE_RX 1 +#define FTDI_SIO_RESET_PURGE_TX 2 + +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_RESET + * wValue: Control Value + * 0 = Reset SIO + * 1 = Purge RX buffer + * 2 = Purge TX buffer + * wIndex: Port + * wLength: 0 + * Data: None + * + * The Reset SIO command has this effect: + * + * Sets flow control set to 'none' + * Event char = $0D + * Event trigger = disabled + * Purge RX buffer + * Purge TX buffer + * Clear DTR + * Clear RTS + * baud and data format not reset + * + * The Purge RX and TX buffer commands affect nothing except the buffers + * + */ + +/* FTDI_SIO_MODEM_CTRL */ +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_MODEM_CTRL + * wValue: ControlValue (see below) + * wIndex: Port + * wLength: 0 + * Data: None + * + * NOTE: If the device is in RTS/CTS flow control, the RTS set by this + * command will be IGNORED without an error being returned + * Also - you can not set DTR and RTS with one control message + */ + +#define FTDI_SIO_SET_DTR_MASK 0x1 +#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1) +#define FTDI_SIO_SET_DTR_LOW ((FTDI_SIO_SET_DTR_MASK << 8) | 0) +#define FTDI_SIO_SET_RTS_MASK 0x2 +#define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2) +#define FTDI_SIO_SET_RTS_LOW ((FTDI_SIO_SET_RTS_MASK << 8) | 0) + +/* + * ControlValue + * B0 DTR state + * 0 = reset + * 1 = set + * B1 RTS state + * 0 = reset + * 1 = set + * B2..7 Reserved + * B8 DTR state enable + * 0 = ignore + * 1 = use DTR state + * B9 RTS state enable + * 0 = ignore + * 1 = use RTS state + * B10..15 Reserved + */ + +/* FTDI_SIO_SET_FLOW_CTRL */ +#define FTDI_SIO_DISABLE_FLOW_CTRL 0x0 +#define FTDI_SIO_RTS_CTS_HS (0x1 << 8) +#define FTDI_SIO_DTR_DSR_HS (0x2 << 8) +#define FTDI_SIO_XON_XOFF_HS (0x4 << 8) + +/* + * BmRequestType: 0100 0000b + * bRequest: FTDI_SIO_SET_FLOW_CTRL + * wValue: Xoff/Xon + * wIndex: Protocol/Port - hIndex is protocol / lIndex is port + * wLength: 0 + * Data: None + * + * hIndex protocol is: + * B0 Output handshaking using RTS/CTS + * 0 = disabled + * 1 = enabled + * B1 Output handshaking using DTR/DSR + * 0 = disabled + * 1 = enabled + * B2 Xon/Xoff handshaking + * 0 = disabled + * 1 = enabled + * + * A value of zero in the hIndex field disables handshaking + * + * If Xon/Xoff handshaking is specified, the hValue field should contain the + * XOFF character and the lValue field contains the XON character. + */ + +/* FTDI_SIO_SET_BAUD_RATE */ +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_SET_BAUDRATE + * wValue: BaudDivisor value - see below + * wIndex: Port + * wLength: 0 + * Data: None + * The BaudDivisor values are calculated as follows (too complicated): + */ + +/* FTDI_SIO_SET_DATA */ +#define FTDI_SIO_SET_DATA_PARITY_NONE (0x0 << 8) +#define FTDI_SIO_SET_DATA_PARITY_ODD (0x1 << 8) +#define FTDI_SIO_SET_DATA_PARITY_EVEN (0x2 << 8) +#define FTDI_SIO_SET_DATA_PARITY_MARK (0x3 << 8) +#define FTDI_SIO_SET_DATA_PARITY_SPACE (0x4 << 8) +#define FTDI_SIO_SET_DATA_STOP_BITS_1 (0x0 << 11) +#define FTDI_SIO_SET_DATA_STOP_BITS_15 (0x1 << 11) +#define FTDI_SIO_SET_DATA_STOP_BITS_2 (0x2 << 11) +#define FTDI_SIO_SET_BREAK (0x1 << 14) + +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_SET_DATA + * wValue: Data characteristics (see below) + * wIndex: Port + * wLength: 0 + * Data: No + * + * Data characteristics + * + * B0..7 Number of data bits + * B8..10 Parity + * 0 = None + * 1 = Odd + * 2 = Even + * 3 = Mark + * 4 = Space + * B11..13 Stop Bits + * 0 = 1 + * 1 = 1.5 + * 2 = 2 + * B14 + * 1 = TX ON (break) + * 0 = TX OFF (normal state) + * B15 Reserved + * + */ + +/* +* DATA FORMAT +* +* IN Endpoint +* +* The device reserves the first two bytes of data on this endpoint to contain +* the current values of the modem and line status registers. In the absence of +* data, the device generates a message consisting of these two status bytes + * every 40 ms + * + * Byte 0: Modem Status +* +* Offset Description +* B0 Reserved - must be 1 +* B1 Reserved - must be 0 +* B2 Reserved - must be 0 +* B3 Reserved - must be 0 +* B4 Clear to Send (CTS) +* B5 Data Set Ready (DSR) +* B6 Ring Indicator (RI) +* B7 Receive Line Signal Detect (RLSD) +* +* Byte 1: Line Status +* +* Offset Description +* B0 Data Ready (DR) +* B1 Overrun Error (OE) +* B2 Parity Error (PE) +* B3 Framing Error (FE) +* B4 Break Interrupt (BI) +* B5 Transmitter Holding Register (THRE) +* B6 Transmitter Empty (TEMT) +* B7 Error in RCVR FIFO +* +*/ +#define FTDI_RS0_CTS (1 << 4) +#define FTDI_RS0_DSR (1 << 5) +#define FTDI_RS0_RI (1 << 6) +#define FTDI_RS0_RLSD (1 << 7) + +#define FTDI_RS_DR 1 +#define FTDI_RS_OE (1<<1) +#define FTDI_RS_PE (1<<2) +#define FTDI_RS_FE (1<<3) +#define FTDI_RS_BI (1<<4) +#define FTDI_RS_THRE (1<<5) +#define FTDI_RS_TEMT (1<<6) +#define FTDI_RS_FIFO (1<<7) + +//--------------------------------------------------------------------+ +// Internal Class Driver API +//--------------------------------------------------------------------+ +void ftdih_init (void); +bool ftdih_open (uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); +bool ftdih_set_config (uint8_t daddr, uint8_t itf_num); +bool ftdih_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes); +void ftdih_close (uint8_t daddr); + +#endif //TUSB_FTDI_HOST_H diff --git a/src/host/usbh.c b/src/host/usbh.c index 3be662c63..3953d5b21 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -286,7 +286,7 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid) *vid = *pid = 0; usbh_device_t const* dev = get_device(dev_addr); - TU_VERIFY(dev && dev->configured); + TU_VERIFY(dev && dev->addressed && dev->vid != 0); *vid = dev->vid; *pid = dev->pid; diff --git a/src/tusb_option.h b/src/tusb_option.h index 44d036ea4..a372e9950 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -439,6 +439,11 @@ #define CFG_TUH_CDC 0 #endif +#ifndef CFG_TUH_CDC_FTDI + // FTDI is not part of CDC class, CDC is used for Serial-over-USB here + #define CFG_TUH_CDC_FTDI 0 +#endif + #ifndef CFG_TUH_HID #define CFG_TUH_HID 0 #endif -- cgit v1.3.1 From 293a6222f81ac1085f8b34730f1907f899ce17cf Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 27 Apr 2023 11:08:42 +0700 Subject: rename ftdi_host to ftdi_sio --- examples/host/cdc_msc_hid/CMakeLists.txt | 2 +- src/class/cdc/cdc_host.c | 2 +- src/class/cdc/serial/ftdi_host.h | 258 ------------------------------- src/class/cdc/serial/ftdi_sio.h | 249 +++++++++++++++++++++++++++++ 4 files changed, 251 insertions(+), 260 deletions(-) delete mode 100644 src/class/cdc/serial/ftdi_host.h create mode 100644 src/class/cdc/serial/ftdi_sio.h (limited to 'src') diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt index d7d1a54d7..b66ff2382 100644 --- a/examples/host/cdc_msc_hid/CMakeLists.txt +++ b/examples/host/cdc_msc_hid/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.17) include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 7949ff8d3..d33f31f1a 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -34,7 +34,7 @@ #include "cdc_host.h" #if CFG_TUH_CDC_FTDI - #include "serial/ftdi_host.h" + #include "serial/ftdi_sio.h" #endif diff --git a/src/class/cdc/serial/ftdi_host.h b/src/class/cdc/serial/ftdi_host.h deleted file mode 100644 index 4276d374e..000000000 --- a/src/class/cdc/serial/ftdi_host.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2023 Ha Thach (thach@tinyusb.org) for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef TUSB_FTDI_HOST_H -#define TUSB_FTDI_HOST_H - -// VID/PID for matching FTDI devices -#define TU_FTDI_VID 0x0403 -#define TU_FTDI_PID_LIST \ - 0x6001, 0x6006, 0x6010, 0x6011, 0x6014, 0x6015, 0x8372, 0xFBFA, \ - 0xcd18 - -// Commands -#define FTDI_SIO_RESET 0 /* Reset the port */ -#define FTDI_SIO_MODEM_CTRL 1 /* Set the modem control register */ -#define FTDI_SIO_SET_FLOW_CTRL 2 /* Set flow control register */ -#define FTDI_SIO_SET_BAUD_RATE 3 /* Set baud rate */ -#define FTDI_SIO_SET_DATA 4 /* Set the data characteristics of the port */ -#define FTDI_SIO_GET_MODEM_STATUS 5 /* Retrieve current value of modem status register */ -#define FTDI_SIO_SET_EVENT_CHAR 6 /* Set the event character */ -#define FTDI_SIO_SET_ERROR_CHAR 7 /* Set the error character */ -#define FTDI_SIO_SET_LATENCY_TIMER 9 /* Set the latency timer */ -#define FTDI_SIO_GET_LATENCY_TIMER 0x0a /* Get the latency timer */ -#define FTDI_SIO_SET_BITMODE 0x0b /* Set bitbang mode */ -#define FTDI_SIO_READ_PINS 0x0c /* Read immediate value of pins */ -#define FTDI_SIO_READ_EEPROM 0x90 /* Read EEPROM */ - -/* FTDI_SIO_RESET */ -#define FTDI_SIO_RESET_SIO 0 -#define FTDI_SIO_RESET_PURGE_RX 1 -#define FTDI_SIO_RESET_PURGE_TX 2 - -/* - * BmRequestType: 0100 0000B - * bRequest: FTDI_SIO_RESET - * wValue: Control Value - * 0 = Reset SIO - * 1 = Purge RX buffer - * 2 = Purge TX buffer - * wIndex: Port - * wLength: 0 - * Data: None - * - * The Reset SIO command has this effect: - * - * Sets flow control set to 'none' - * Event char = $0D - * Event trigger = disabled - * Purge RX buffer - * Purge TX buffer - * Clear DTR - * Clear RTS - * baud and data format not reset - * - * The Purge RX and TX buffer commands affect nothing except the buffers - * - */ - -/* FTDI_SIO_MODEM_CTRL */ -/* - * BmRequestType: 0100 0000B - * bRequest: FTDI_SIO_MODEM_CTRL - * wValue: ControlValue (see below) - * wIndex: Port - * wLength: 0 - * Data: None - * - * NOTE: If the device is in RTS/CTS flow control, the RTS set by this - * command will be IGNORED without an error being returned - * Also - you can not set DTR and RTS with one control message - */ - -#define FTDI_SIO_SET_DTR_MASK 0x1 -#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1) -#define FTDI_SIO_SET_DTR_LOW ((FTDI_SIO_SET_DTR_MASK << 8) | 0) -#define FTDI_SIO_SET_RTS_MASK 0x2 -#define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2) -#define FTDI_SIO_SET_RTS_LOW ((FTDI_SIO_SET_RTS_MASK << 8) | 0) - -/* - * ControlValue - * B0 DTR state - * 0 = reset - * 1 = set - * B1 RTS state - * 0 = reset - * 1 = set - * B2..7 Reserved - * B8 DTR state enable - * 0 = ignore - * 1 = use DTR state - * B9 RTS state enable - * 0 = ignore - * 1 = use RTS state - * B10..15 Reserved - */ - -/* FTDI_SIO_SET_FLOW_CTRL */ -#define FTDI_SIO_DISABLE_FLOW_CTRL 0x0 -#define FTDI_SIO_RTS_CTS_HS (0x1 << 8) -#define FTDI_SIO_DTR_DSR_HS (0x2 << 8) -#define FTDI_SIO_XON_XOFF_HS (0x4 << 8) - -/* - * BmRequestType: 0100 0000b - * bRequest: FTDI_SIO_SET_FLOW_CTRL - * wValue: Xoff/Xon - * wIndex: Protocol/Port - hIndex is protocol / lIndex is port - * wLength: 0 - * Data: None - * - * hIndex protocol is: - * B0 Output handshaking using RTS/CTS - * 0 = disabled - * 1 = enabled - * B1 Output handshaking using DTR/DSR - * 0 = disabled - * 1 = enabled - * B2 Xon/Xoff handshaking - * 0 = disabled - * 1 = enabled - * - * A value of zero in the hIndex field disables handshaking - * - * If Xon/Xoff handshaking is specified, the hValue field should contain the - * XOFF character and the lValue field contains the XON character. - */ - -/* FTDI_SIO_SET_BAUD_RATE */ -/* - * BmRequestType: 0100 0000B - * bRequest: FTDI_SIO_SET_BAUDRATE - * wValue: BaudDivisor value - see below - * wIndex: Port - * wLength: 0 - * Data: None - * The BaudDivisor values are calculated as follows (too complicated): - */ - -/* FTDI_SIO_SET_DATA */ -#define FTDI_SIO_SET_DATA_PARITY_NONE (0x0 << 8) -#define FTDI_SIO_SET_DATA_PARITY_ODD (0x1 << 8) -#define FTDI_SIO_SET_DATA_PARITY_EVEN (0x2 << 8) -#define FTDI_SIO_SET_DATA_PARITY_MARK (0x3 << 8) -#define FTDI_SIO_SET_DATA_PARITY_SPACE (0x4 << 8) -#define FTDI_SIO_SET_DATA_STOP_BITS_1 (0x0 << 11) -#define FTDI_SIO_SET_DATA_STOP_BITS_15 (0x1 << 11) -#define FTDI_SIO_SET_DATA_STOP_BITS_2 (0x2 << 11) -#define FTDI_SIO_SET_BREAK (0x1 << 14) - -/* - * BmRequestType: 0100 0000B - * bRequest: FTDI_SIO_SET_DATA - * wValue: Data characteristics (see below) - * wIndex: Port - * wLength: 0 - * Data: No - * - * Data characteristics - * - * B0..7 Number of data bits - * B8..10 Parity - * 0 = None - * 1 = Odd - * 2 = Even - * 3 = Mark - * 4 = Space - * B11..13 Stop Bits - * 0 = 1 - * 1 = 1.5 - * 2 = 2 - * B14 - * 1 = TX ON (break) - * 0 = TX OFF (normal state) - * B15 Reserved - * - */ - -/* -* DATA FORMAT -* -* IN Endpoint -* -* The device reserves the first two bytes of data on this endpoint to contain -* the current values of the modem and line status registers. In the absence of -* data, the device generates a message consisting of these two status bytes - * every 40 ms - * - * Byte 0: Modem Status -* -* Offset Description -* B0 Reserved - must be 1 -* B1 Reserved - must be 0 -* B2 Reserved - must be 0 -* B3 Reserved - must be 0 -* B4 Clear to Send (CTS) -* B5 Data Set Ready (DSR) -* B6 Ring Indicator (RI) -* B7 Receive Line Signal Detect (RLSD) -* -* Byte 1: Line Status -* -* Offset Description -* B0 Data Ready (DR) -* B1 Overrun Error (OE) -* B2 Parity Error (PE) -* B3 Framing Error (FE) -* B4 Break Interrupt (BI) -* B5 Transmitter Holding Register (THRE) -* B6 Transmitter Empty (TEMT) -* B7 Error in RCVR FIFO -* -*/ -#define FTDI_RS0_CTS (1 << 4) -#define FTDI_RS0_DSR (1 << 5) -#define FTDI_RS0_RI (1 << 6) -#define FTDI_RS0_RLSD (1 << 7) - -#define FTDI_RS_DR 1 -#define FTDI_RS_OE (1<<1) -#define FTDI_RS_PE (1<<2) -#define FTDI_RS_FE (1<<3) -#define FTDI_RS_BI (1<<4) -#define FTDI_RS_THRE (1<<5) -#define FTDI_RS_TEMT (1<<6) -#define FTDI_RS_FIFO (1<<7) - -//--------------------------------------------------------------------+ -// Internal Class Driver API -//--------------------------------------------------------------------+ -void ftdih_init (void); -bool ftdih_open (uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); -bool ftdih_set_config (uint8_t daddr, uint8_t itf_num); -bool ftdih_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes); -void ftdih_close (uint8_t daddr); - -#endif //TUSB_FTDI_HOST_H diff --git a/src/class/cdc/serial/ftdi_sio.h b/src/class/cdc/serial/ftdi_sio.h new file mode 100644 index 000000000..6916e4031 --- /dev/null +++ b/src/class/cdc/serial/ftdi_sio.h @@ -0,0 +1,249 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (thach@tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef TUSB_FTDI_SIO_H +#define TUSB_FTDI_SIO_H + +// VID/PID for matching FTDI devices +#define TU_FTDI_VID 0x0403 +#define TU_FTDI_PID_LIST \ + 0x6001, 0x6006, 0x6010, 0x6011, 0x6014, 0x6015, 0x8372, 0xFBFA, \ + 0xcd18 + +// Commands +#define FTDI_SIO_RESET 0 /* Reset the port */ +#define FTDI_SIO_MODEM_CTRL 1 /* Set the modem control register */ +#define FTDI_SIO_SET_FLOW_CTRL 2 /* Set flow control register */ +#define FTDI_SIO_SET_BAUD_RATE 3 /* Set baud rate */ +#define FTDI_SIO_SET_DATA 4 /* Set the data characteristics of the port */ +#define FTDI_SIO_GET_MODEM_STATUS 5 /* Retrieve current value of modem status register */ +#define FTDI_SIO_SET_EVENT_CHAR 6 /* Set the event character */ +#define FTDI_SIO_SET_ERROR_CHAR 7 /* Set the error character */ +#define FTDI_SIO_SET_LATENCY_TIMER 9 /* Set the latency timer */ +#define FTDI_SIO_GET_LATENCY_TIMER 0x0a /* Get the latency timer */ +#define FTDI_SIO_SET_BITMODE 0x0b /* Set bitbang mode */ +#define FTDI_SIO_READ_PINS 0x0c /* Read immediate value of pins */ +#define FTDI_SIO_READ_EEPROM 0x90 /* Read EEPROM */ + +/* FTDI_SIO_RESET */ +#define FTDI_SIO_RESET_SIO 0 +#define FTDI_SIO_RESET_PURGE_RX 1 +#define FTDI_SIO_RESET_PURGE_TX 2 + +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_RESET + * wValue: Control Value + * 0 = Reset SIO + * 1 = Purge RX buffer + * 2 = Purge TX buffer + * wIndex: Port + * wLength: 0 + * Data: None + * + * The Reset SIO command has this effect: + * + * Sets flow control set to 'none' + * Event char = $0D + * Event trigger = disabled + * Purge RX buffer + * Purge TX buffer + * Clear DTR + * Clear RTS + * baud and data format not reset + * + * The Purge RX and TX buffer commands affect nothing except the buffers + * + */ + +/* FTDI_SIO_MODEM_CTRL */ +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_MODEM_CTRL + * wValue: ControlValue (see below) + * wIndex: Port + * wLength: 0 + * Data: None + * + * NOTE: If the device is in RTS/CTS flow control, the RTS set by this + * command will be IGNORED without an error being returned + * Also - you can not set DTR and RTS with one control message + */ + +#define FTDI_SIO_SET_DTR_MASK 0x1 +#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1) +#define FTDI_SIO_SET_DTR_LOW ((FTDI_SIO_SET_DTR_MASK << 8) | 0) +#define FTDI_SIO_SET_RTS_MASK 0x2 +#define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2) +#define FTDI_SIO_SET_RTS_LOW ((FTDI_SIO_SET_RTS_MASK << 8) | 0) + +/* + * ControlValue + * B0 DTR state + * 0 = reset + * 1 = set + * B1 RTS state + * 0 = reset + * 1 = set + * B2..7 Reserved + * B8 DTR state enable + * 0 = ignore + * 1 = use DTR state + * B9 RTS state enable + * 0 = ignore + * 1 = use RTS state + * B10..15 Reserved + */ + +/* FTDI_SIO_SET_FLOW_CTRL */ +#define FTDI_SIO_DISABLE_FLOW_CTRL 0x0 +#define FTDI_SIO_RTS_CTS_HS (0x1 << 8) +#define FTDI_SIO_DTR_DSR_HS (0x2 << 8) +#define FTDI_SIO_XON_XOFF_HS (0x4 << 8) + +/* + * BmRequestType: 0100 0000b + * bRequest: FTDI_SIO_SET_FLOW_CTRL + * wValue: Xoff/Xon + * wIndex: Protocol/Port - hIndex is protocol / lIndex is port + * wLength: 0 + * Data: None + * + * hIndex protocol is: + * B0 Output handshaking using RTS/CTS + * 0 = disabled + * 1 = enabled + * B1 Output handshaking using DTR/DSR + * 0 = disabled + * 1 = enabled + * B2 Xon/Xoff handshaking + * 0 = disabled + * 1 = enabled + * + * A value of zero in the hIndex field disables handshaking + * + * If Xon/Xoff handshaking is specified, the hValue field should contain the + * XOFF character and the lValue field contains the XON character. + */ + +/* FTDI_SIO_SET_BAUD_RATE */ +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_SET_BAUDRATE + * wValue: BaudDivisor value - see below + * wIndex: Port + * wLength: 0 + * Data: None + * The BaudDivisor values are calculated as follows (too complicated): + */ + +/* FTDI_SIO_SET_DATA */ +#define FTDI_SIO_SET_DATA_PARITY_NONE (0x0 << 8) +#define FTDI_SIO_SET_DATA_PARITY_ODD (0x1 << 8) +#define FTDI_SIO_SET_DATA_PARITY_EVEN (0x2 << 8) +#define FTDI_SIO_SET_DATA_PARITY_MARK (0x3 << 8) +#define FTDI_SIO_SET_DATA_PARITY_SPACE (0x4 << 8) +#define FTDI_SIO_SET_DATA_STOP_BITS_1 (0x0 << 11) +#define FTDI_SIO_SET_DATA_STOP_BITS_15 (0x1 << 11) +#define FTDI_SIO_SET_DATA_STOP_BITS_2 (0x2 << 11) +#define FTDI_SIO_SET_BREAK (0x1 << 14) + +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_SET_DATA + * wValue: Data characteristics (see below) + * wIndex: Port + * wLength: 0 + * Data: No + * + * Data characteristics + * + * B0..7 Number of data bits + * B8..10 Parity + * 0 = None + * 1 = Odd + * 2 = Even + * 3 = Mark + * 4 = Space + * B11..13 Stop Bits + * 0 = 1 + * 1 = 1.5 + * 2 = 2 + * B14 + * 1 = TX ON (break) + * 0 = TX OFF (normal state) + * B15 Reserved + * + */ + +/* +* DATA FORMAT +* +* IN Endpoint +* +* The device reserves the first two bytes of data on this endpoint to contain +* the current values of the modem and line status registers. In the absence of +* data, the device generates a message consisting of these two status bytes + * every 40 ms + * + * Byte 0: Modem Status +* +* Offset Description +* B0 Reserved - must be 1 +* B1 Reserved - must be 0 +* B2 Reserved - must be 0 +* B3 Reserved - must be 0 +* B4 Clear to Send (CTS) +* B5 Data Set Ready (DSR) +* B6 Ring Indicator (RI) +* B7 Receive Line Signal Detect (RLSD) +* +* Byte 1: Line Status +* +* Offset Description +* B0 Data Ready (DR) +* B1 Overrun Error (OE) +* B2 Parity Error (PE) +* B3 Framing Error (FE) +* B4 Break Interrupt (BI) +* B5 Transmitter Holding Register (THRE) +* B6 Transmitter Empty (TEMT) +* B7 Error in RCVR FIFO +* +*/ +#define FTDI_RS0_CTS (1 << 4) +#define FTDI_RS0_DSR (1 << 5) +#define FTDI_RS0_RI (1 << 6) +#define FTDI_RS0_RLSD (1 << 7) + +#define FTDI_RS_DR 1 +#define FTDI_RS_OE (1<<1) +#define FTDI_RS_PE (1<<2) +#define FTDI_RS_FE (1<<3) +#define FTDI_RS_BI (1<<4) +#define FTDI_RS_THRE (1<<5) +#define FTDI_RS_TEMT (1<<6) +#define FTDI_RS_FIFO (1<<7) + +#endif //TUSB_FTDI_SIO_H -- cgit v1.3.1 From 85d9925d24feb41bd355a9248207acaf853b70ff Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 27 Apr 2023 15:20:04 +0700 Subject: refactor ftdi driver --- src/class/cdc/cdc_host.c | 463 ++++++++++++++++++++++++++++++----------------- src/tusb_option.h | 7 +- 2 files changed, 307 insertions(+), 163 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index d33f31f1a..fc7a7a038 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -37,6 +37,9 @@ #include "serial/ftdi_sio.h" #endif +#if CFG_TUH_CDC_CP210X + #include "serial/cp210x.h" +#endif // Debug level, TUSB_CFG_DEBUG must be at least this level for debug message #define CDCH_DEBUG 2 @@ -48,8 +51,9 @@ //--------------------------------------------------------------------+ enum { - SERIAL_PROTOCOL_ACM = 0, - SERIAL_PROTOCOL_FTDI = 1, + SERIAL_PROTOCOL_ACM = 0, + SERIAL_PROTOCOL_FTDI, + SERIAL_PROTOCOL_CP210X, }; typedef struct { @@ -111,11 +115,20 @@ static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr) } -static cdch_interface_t* find_new_itf(void) +static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const *itf_desc) { for(uint8_t i=0; idaddr = daddr; + p_cdc->bInterfaceNumber = itf_desc->bInterfaceNumber; + p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass; + p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol; + p_cdc->line_state = 0; + return p_cdc; + } } return NULL; @@ -126,6 +139,221 @@ static inline bool support_line_request(cdch_interface_t const* p_cdc) { (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI); } +static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep); +static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num); +static void cdch_internal_control_complete(tuh_xfer_t* xfer); + +//--------------------------------------------------------------------+ +// FTDI +//--------------------------------------------------------------------+ +#if CFG_TUH_CDC_FTDI + +static uint16_t const ftdi_pids[] = { TU_FTDI_PID_LIST }; +enum { + FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0]) +}; + +enum { + CONFIG_FTDI_RESET, + CONFIG_FTDI_MODEM_CTRL, + CONFIG_FTDI_SET_BAUDRATE, + CONFIG_FTDI_SET_DATA, + CONFIG_FTDI_COMPLETE +}; + +static bool ftdih_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { + // FTDI Interface includes 1 vendor interface + 2 bulk endpoints + TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2); + TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); + + cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); + TU_VERIFY(p_cdc); + + p_cdc->serial_protocol = SERIAL_PROTOCOL_FTDI; + + // endpoint pair + tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); + + // data endpoints expected to be in pairs + return open_ep_stream_pair(p_cdc, desc_ep); +} + +static bool ftdih_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_DEVICE, + .type = TUSB_REQ_TYPE_VENDOR, + .direction = TUSB_DIR_OUT + }, + .bRequest = FTDI_SIO_RESET, + .wValue = tu_htole16(FTDI_SIO_RESET_SIO), + .wIndex = 0, + .wLength = 0 + }; + + p_cdc->user_control_cb = complete_cb; + + tuh_xfer_t xfer = { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request, + .buffer = NULL, + .complete_cb = complete_cb, + .user_data = user_data + }; + + TU_ASSERT(tuh_control_xfer(&xfer)); + return true; +} + +static bool ftdi_sio_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_VENDOR, + .direction = TUSB_DIR_OUT + }, + .bRequest = FTDI_SIO_MODEM_CTRL, + .wValue = tu_htole16(0x0300 | line_state), // 0x0300 is DTR and RTS enable + .wIndex = 0, // port + .wLength = 0 + }; + + p_cdc->user_control_cb = complete_cb; + + tuh_xfer_t xfer = { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request, + .buffer = NULL, + .complete_cb = cdch_internal_control_complete, + .user_data = user_data + }; + + TU_ASSERT(tuh_control_xfer(&xfer)); + return true; +} + +static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + // TODO baudrate to baud divisor + (void) baudrate; + + uint16_t divisor = 0x4138; // FIXME hardcoded to 9600 baud + + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_VENDOR, + .direction = TUSB_DIR_OUT + }, + .bRequest = FTDI_SIO_SET_BAUD_RATE, + .wValue = tu_htole16(divisor), + .wIndex = 0, // port + .wLength = 0 + }; + + p_cdc->user_control_cb = complete_cb; + + tuh_xfer_t xfer = { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request, + .buffer = NULL, + .complete_cb = cdch_internal_control_complete, + .user_data = user_data + }; + + TU_ASSERT(tuh_control_xfer(&xfer)); + return true; +} + +static void process_ftdi_config(tuh_xfer_t* xfer) { + uintptr_t const state = xfer->user_data; + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc, ); + + switch(state) { + // Note may need to read FTDI eeprom + case CONFIG_FTDI_RESET: + TU_ASSERT(ftdih_sio_reset(p_cdc, process_ftdi_config, CONFIG_FTDI_MODEM_CTRL),); + break; + + case CONFIG_FTDI_MODEM_CTRL: + #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + TU_ASSERT(ftdi_sio_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_ftdi_config, CONFIG_FTDI_SET_BAUDRATE),); + break; + #else + TU_ATTR_FALLTHROUGH; + #endif + + case CONFIG_FTDI_SET_BAUDRATE: { + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT(ftdi_sio_set_baudrate(p_cdc, line_coding.bit_rate, process_ftdi_config, CONFIG_FTDI_SET_DATA),); + break; + #else + TU_ATTR_FALLTHROUGH; + #endif + } + + case CONFIG_FTDI_SET_DATA: { + #if 0 // TODO set data format + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT(ftdi_sio_set_data(p_cdc, process_ftdi_config, CONFIG_FTDI_COMPLETE),); + break; + #endif + #endif + + TU_ATTR_FALLTHROUGH; + } + + case CONFIG_FTDI_COMPLETE: + set_config_complete(p_cdc, idx, itf_num); + break; + + default: + break; + } +} + +#endif + +//--------------------------------------------------------------------+ +// CP210x +//--------------------------------------------------------------------+ + +#if CFG_TUH_CDC_CP210X + +static uint16_t const cp210x_pids[] = { TU_CP210X_PID_LIST }; +enum { + CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0]) +}; + +static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { + // CP210x Interface includes 1 vendor interface + 2 bulk endpoints + TU_VERIFY(itf_desc->bInterfaceSubClass == 0 && itf_desc->bInterfaceProtocol == 0 && itf_desc->bNumEndpoints == 2); + TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); + + cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); + TU_VERIFY(p_cdc); + + p_cdc->serial_protocol = SERIAL_PROTOCOL_CP210X; + + // endpoint pair + tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); + + // data endpoints expected to be in pairs + return open_ep_stream_pair(p_cdc, desc_ep); +} + +#endif + //--------------------------------------------------------------------+ // APPLICATION API //--------------------------------------------------------------------+ @@ -324,10 +552,8 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c TU_LOG_CDCH("CDC Set Control Line State\r\n"); - tusb_control_request_t request; - if(p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM ) { - tusb_control_request_t const acm_request = { + tusb_control_request_t const request = { .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, .type = TUSB_REQ_TYPE_CLASS, @@ -339,43 +565,27 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c .wLength = 0 }; - request = acm_request; + p_cdc->user_control_cb = complete_cb; + tuh_xfer_t xfer = { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request, + .buffer = NULL, + .complete_cb = cdch_internal_control_complete, + .user_data = user_data + }; + + TU_ASSERT(tuh_control_xfer(&xfer)); + return true; } #if CFG_TUH_CDC_FTDI else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) { - // FTDI use vendor specific request to set control line state - tusb_control_request_t const ftdi_request = { - .bmRequestType_bit = { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_VENDOR, - .direction = TUSB_DIR_OUT - }, - .bRequest = FTDI_SIO_MODEM_CTRL, - .wValue = tu_htole16(0x0300 | line_state), // 0x0300 is DTR and RTS enable - .wIndex = 0, // port - .wLength = 0 - }; - - request = ftdi_request; + return ftdi_sio_modem_ctrl(p_cdc, line_state, complete_cb, user_data); } #endif else { return false; } - - p_cdc->user_control_cb = complete_cb; - tuh_xfer_t xfer = { - .daddr = p_cdc->daddr, - .ep_addr = 0, - .setup = &request, - .buffer = NULL, - .complete_cb = cdch_internal_control_complete, - .user_data = user_data - }; - - TU_ASSERT(tuh_control_xfer(&xfer)); - - return true; } bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) @@ -385,11 +595,8 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, TU_LOG_CDCH("CDC Set Line Conding\r\n"); - tusb_control_request_t request; - uint8_t* enum_buf = NULL; - if (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM) { - tusb_control_request_t const acm_request = { + tusb_control_request_t const request = { .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, .type = TUSB_REQ_TYPE_CLASS, @@ -401,47 +608,32 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, .wLength = tu_htole16(sizeof(cdc_line_coding_t)) }; - request = acm_request; - // use usbh enum buf to hold line coding since user line_coding variable does not live long enough - enum_buf = usbh_get_enum_buf(); + uint8_t* enum_buf = usbh_get_enum_buf(); memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t)); + + p_cdc->user_control_cb = complete_cb; + tuh_xfer_t xfer = { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request, + .buffer = enum_buf, + .complete_cb = cdch_internal_control_complete, + .user_data = user_data + }; + + TU_ASSERT(tuh_control_xfer(&xfer)); + return true; } #if CFG_TUH_CDC_FTDI else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) { // FTDI need to set baud rate and data bits, parity, stop bits separately - tusb_control_request_t const ftdi_request = { - .bmRequestType_bit = { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_VENDOR, - .direction = TUSB_DIR_OUT - }, - .bRequest = FTDI_SIO_SET_BAUD_RATE, - .wValue = 0x4138, // FIXME hardcoded to 9600 baud - .wIndex = 0, // port - .wLength = tu_htole16(sizeof(cdc_line_coding_t)) - }; - - request = ftdi_request; + return ftdi_sio_set_baudrate(p_cdc, line_coding->bit_rate, complete_cb, user_data); } #endif else { return false; } - - p_cdc->user_control_cb = complete_cb; - tuh_xfer_t xfer = - { - .daddr = p_cdc->daddr, - .ep_addr = 0, - .setup = &request, - .buffer = enum_buf, - .complete_cb = cdch_internal_control_complete, - .user_data = user_data - }; - - TU_ASSERT(tuh_control_xfer(&xfer)); - return true; } //--------------------------------------------------------------------+ @@ -544,9 +736,6 @@ enum CONFIG_SET_CONTROL_LINE_STATE, CONFIG_SET_LINE_CODING, CONFIG_COMPLETE, - - // FTDI - CONFIG_FTDI_RESET }; static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep) @@ -572,76 +761,14 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t c return true; } -#if CFG_TUH_CDC_FTDI -bool ftdih_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { - // FTDI configuration includes 1 vendor interface + 2 bulk endpoints - TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2); - TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); - - cdch_interface_t * p_cdc = find_new_itf(); - TU_VERIFY(p_cdc); - - p_cdc->daddr = daddr; - p_cdc->bInterfaceNumber = itf_desc->bInterfaceNumber; - p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass; - p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol; - p_cdc->line_state = 0; - p_cdc->serial_protocol = SERIAL_PROTOCOL_FTDI; - - // endpoint pair - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); - - // data endpoints expected to be in pairs - TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep)); - - return true; -} - -static bool ftdih_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ - tusb_control_request_t const request = { - .bmRequestType_bit = { - .recipient = TUSB_REQ_RCPT_DEVICE, - .type = TUSB_REQ_TYPE_VENDOR, - .direction = TUSB_DIR_OUT - }, - .bRequest = FTDI_SIO_RESET, - .wValue = tu_htole16(FTDI_SIO_RESET_SIO), - .wIndex = 0, - .wLength = 0 - }; - - p_cdc->user_control_cb = complete_cb; - - tuh_xfer_t xfer = { - .daddr = p_cdc->daddr, - .ep_addr = 0, - .setup = &request, - .buffer = NULL, - .complete_cb = complete_cb, - .user_data = user_data - }; - - TU_ASSERT(tuh_control_xfer(&xfer)); - return true; -} - -#endif - - static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { uint8_t const * p_desc_end = ((uint8_t const*) itf_desc) + max_len; - cdch_interface_t * p_cdc = find_new_itf(); + cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY(p_cdc); - p_cdc->daddr = daddr; - p_cdc->bInterfaceNumber = itf_desc->bInterfaceNumber; - p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass; - p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol; - p_cdc->line_state = 0; - p_cdc->serial_protocol = SERIAL_PROTOCOL_ACM; + p_cdc->serial_protocol = SERIAL_PROTOCOL_ACM; //------------- Control Interface -------------// uint8_t const * p_desc = tu_desc_next(itf_desc); @@ -696,28 +823,47 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d { return acm_open(daddr, itf_desc, max_len); } + #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X else if ( 0xff == itf_desc->bInterfaceClass ) { uint16_t vid, pid; TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid)); -#if CFG_TUH_CDC_FTDI + #if CFG_TUH_CDC_FTDI if (TU_FTDI_VID == vid) { - uint16_t const ftdi_pids[] = {TU_FTDI_PID_LIST}; - enum { FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0]) }; - for (size_t i = 0; i < FTDI_PID_COUNT; i++) { if (ftdi_pids[i] == pid) { return ftdih_open(daddr, itf_desc, max_len); } } } -#endif + #endif + + #if CFG_TUH_CDC_CP210X + if (TU_CP210X_VID == vid) { + for (size_t i = 0; i < CP210X_PID_COUNT; i++) { + if (cp210x_pids[i] == pid) { + return cp210x_open(daddr, itf_desc, max_len); + } + } + } + #endif } + #endif return false; } +static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num) { + if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx); + + // Prepare for incoming data + tu_edpt_stream_read_xfer(&p_cdc->stream.rx); + + // notify usbh that driver enumeration is complete + usbh_driver_set_config_complete(p_cdc->daddr, itf_num); +} + static void process_cdc_config(tuh_xfer_t* xfer) { uintptr_t const state = xfer->user_data; @@ -728,16 +874,9 @@ static void process_cdc_config(tuh_xfer_t* xfer) switch(state) { - #if CFG_TUH_CDC_FTDI - // Note may need to read FTDI eeprom - case CONFIG_FTDI_RESET: - TU_ASSERT(ftdih_sio_reset(p_cdc, process_cdc_config, CONFIG_SET_CONTROL_LINE_STATE), ); - break; - #endif - case CONFIG_SET_CONTROL_LINE_STATE: #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - if (support_line_request(p_cdc)) + if (p_cdc->acm_capability.support_line_request) { TU_ASSERT( tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cdc_config, CONFIG_SET_LINE_CODING), ); break; @@ -747,7 +886,7 @@ static void process_cdc_config(tuh_xfer_t* xfer) case CONFIG_SET_LINE_CODING: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - if (support_line_request(p_cdc)) + if (p_cdc->acm_capability.support_line_request) { cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, CONFIG_COMPLETE), ); @@ -757,14 +896,8 @@ static void process_cdc_config(tuh_xfer_t* xfer) TU_ATTR_FALLTHROUGH; case CONFIG_COMPLETE: - if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx); - - // Prepare for incoming data - tu_edpt_stream_read_xfer(&p_cdc->stream.rx); - - // notify usbh that driver enumeration is complete // itf_num+1 to account for data interface as well - usbh_driver_set_config_complete(xfer->daddr, itf_num+1); + set_config_complete(p_cdc, idx, itf_num+1); break; default: break; @@ -789,19 +922,25 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) switch (p_cdc->serial_protocol) { case SERIAL_PROTOCOL_ACM: xfer.user_data = CONFIG_SET_CONTROL_LINE_STATE; + process_cdc_config(&xfer); break; - #if CFG_TUH_CDC_FTDI + #if CFG_TUH_CDC_FTDI case SERIAL_PROTOCOL_FTDI: xfer.user_data = CONFIG_FTDI_RESET; + process_ftdi_config(&xfer); break; - #endif + #endif + + #if CFG_TUH_CDC_CP210X + case SERIAL_PROTOCOL_CP210X: + //xfer.user_data = CONFIG_SET_CONTROL_LINE_STATE; + break; + #endif default: return false; } - process_cdc_config(&xfer); - return true; } diff --git a/src/tusb_option.h b/src/tusb_option.h index a372e9950..4f3f3a985 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -440,10 +440,15 @@ #endif #ifndef CFG_TUH_CDC_FTDI - // FTDI is not part of CDC class, CDC is used for Serial-over-USB here + // FTDI is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_CDC_FTDI 0 #endif +#ifndef CFG_TUH_CDC_CP210X + // CP210X is not part of CDC class, only to re-use CDC driver API + #define CFG_TUH_CDC_CP210X 0 +#endif + #ifndef CFG_TUH_HID #define CFG_TUH_HID 0 #endif -- cgit v1.3.1 From 9698a088db7616eb628b47457f717574221c9153 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 27 Apr 2023 15:29:44 +0700 Subject: refactor acm function --- src/class/cdc/cdc_host.c | 138 +++++++++++++++++++++++++---------------------- 1 file changed, 73 insertions(+), 65 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index fc7a7a038..00a86888c 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -545,38 +545,42 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) xfer->complete_cb(xfer); } +static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_CLASS, + .direction = TUSB_DIR_OUT + }, + .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE, + .wValue = tu_htole16(line_state), + .wIndex = tu_htole16((uint16_t) p_cdc->bInterfaceNumber), + .wLength = 0 + }; + + p_cdc->user_control_cb = complete_cb; + + tuh_xfer_t xfer = { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request, + .buffer = NULL, + .complete_cb = cdch_internal_control_complete, + .user_data = user_data + }; + + TU_ASSERT(tuh_control_xfer(&xfer)); + return true; +} + bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && support_line_request(p_cdc)); - TU_LOG_CDCH("CDC Set Control Line State\r\n"); if(p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM ) { - tusb_control_request_t const request = { - .bmRequestType_bit = { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_CLASS, - .direction = TUSB_DIR_OUT - }, - .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE, - .wValue = tu_htole16(line_state), - .wIndex = tu_htole16((uint16_t) p_cdc->bInterfaceNumber), - .wLength = 0 - }; - - p_cdc->user_control_cb = complete_cb; - tuh_xfer_t xfer = { - .daddr = p_cdc->daddr, - .ep_addr = 0, - .setup = &request, - .buffer = NULL, - .complete_cb = cdch_internal_control_complete, - .user_data = user_data - }; - - TU_ASSERT(tuh_control_xfer(&xfer)); - return true; + return acm_set_control_line_state(p_cdc, line_state, complete_cb, user_data); } #if CFG_TUH_CDC_FTDI else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) { @@ -588,42 +592,45 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c } } +bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_CLASS, + .direction = TUSB_DIR_OUT + }, + .bRequest = CDC_REQUEST_SET_LINE_CODING, + .wValue = 0, + .wIndex = tu_htole16(p_cdc->bInterfaceNumber), + .wLength = tu_htole16(sizeof(cdc_line_coding_t)) + }; + + // use usbh enum buf to hold line coding since user line_coding variable does not live long enough + uint8_t* enum_buf = usbh_get_enum_buf(); + memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t)); + + p_cdc->user_control_cb = complete_cb; + tuh_xfer_t xfer = { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request, + .buffer = enum_buf, + .complete_cb = cdch_internal_control_complete, + .user_data = user_data + }; + + TU_ASSERT(tuh_control_xfer(&xfer)); + return true; +} + bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && support_line_request(p_cdc)); - TU_LOG_CDCH("CDC Set Line Conding\r\n"); if (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM) { - tusb_control_request_t const request = { - .bmRequestType_bit = { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_CLASS, - .direction = TUSB_DIR_OUT - }, - .bRequest = CDC_REQUEST_SET_LINE_CODING, - .wValue = 0, - .wIndex = tu_htole16(p_cdc->bInterfaceNumber), - .wLength = tu_htole16(sizeof(cdc_line_coding_t)) - }; - - // use usbh enum buf to hold line coding since user line_coding variable does not live long enough - uint8_t* enum_buf = usbh_get_enum_buf(); - memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t)); - - p_cdc->user_control_cb = complete_cb; - tuh_xfer_t xfer = { - .daddr = p_cdc->daddr, - .ep_addr = 0, - .setup = &request, - .buffer = enum_buf, - .complete_cb = cdch_internal_control_complete, - .user_data = user_data - }; - - TU_ASSERT(tuh_control_xfer(&xfer)); - return true; + return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data); } #if CFG_TUH_CDC_FTDI else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) { @@ -733,9 +740,9 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t enum { // ACM - CONFIG_SET_CONTROL_LINE_STATE, - CONFIG_SET_LINE_CODING, - CONFIG_COMPLETE, + CONFIG_ACM_SET_CONTROL_LINE_STATE, + CONFIG_ACM_SET_LINE_CODING, + CONFIG_ACM_COMPLETE, }; static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep) @@ -864,7 +871,7 @@ static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t i usbh_driver_set_config_complete(p_cdc->daddr, itf_num); } -static void process_cdc_config(tuh_xfer_t* xfer) +static void process_acm_config(tuh_xfer_t* xfer) { uintptr_t const state = xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); @@ -874,28 +881,29 @@ static void process_cdc_config(tuh_xfer_t* xfer) switch(state) { - case CONFIG_SET_CONTROL_LINE_STATE: + case CONFIG_ACM_SET_CONTROL_LINE_STATE: #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM if (p_cdc->acm_capability.support_line_request) { - TU_ASSERT( tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cdc_config, CONFIG_SET_LINE_CODING), ); + TU_ASSERT(tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_acm_config, + CONFIG_ACM_SET_LINE_CODING), ); break; } #endif TU_ATTR_FALLTHROUGH; - case CONFIG_SET_LINE_CODING: + case CONFIG_ACM_SET_LINE_CODING: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM if (p_cdc->acm_capability.support_line_request) { cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, CONFIG_COMPLETE), ); + TU_ASSERT(tuh_cdc_set_line_coding(idx, &line_coding, process_acm_config, CONFIG_ACM_COMPLETE), ); break; } #endif TU_ATTR_FALLTHROUGH; - case CONFIG_COMPLETE: + case CONFIG_ACM_COMPLETE: // itf_num+1 to account for data interface as well set_config_complete(p_cdc, idx, itf_num+1); break; @@ -921,8 +929,8 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) switch (p_cdc->serial_protocol) { case SERIAL_PROTOCOL_ACM: - xfer.user_data = CONFIG_SET_CONTROL_LINE_STATE; - process_cdc_config(&xfer); + xfer.user_data = CONFIG_ACM_SET_CONTROL_LINE_STATE; + process_acm_config(&xfer); break; #if CFG_TUH_CDC_FTDI -- cgit v1.3.1 From a32ef1cde124251d86696ed980a87eb25739c6a8 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 27 Apr 2023 16:32:42 +0700 Subject: more host serial refactor --- src/class/cdc/cdc_host.c | 112 ++++++++++++++++++++--------------------------- 1 file changed, 47 insertions(+), 65 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 00a86888c..c25ed48b0 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -154,14 +154,14 @@ enum { }; enum { - CONFIG_FTDI_RESET, + CONFIG_FTDI_RESET = 0, CONFIG_FTDI_MODEM_CTRL, CONFIG_FTDI_SET_BAUDRATE, CONFIG_FTDI_SET_DATA, CONFIG_FTDI_COMPLETE }; -static bool ftdih_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { +static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len) { // FTDI Interface includes 1 vendor interface + 2 bulk endpoints TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2); TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); @@ -169,6 +169,8 @@ static bool ftdih_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uin cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY(p_cdc); + TU_LOG_CDCH("FTDI opened\r\n"); + p_cdc->serial_protocol = SERIAL_PROTOCOL_FTDI; // endpoint pair @@ -178,22 +180,19 @@ static bool ftdih_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uin return open_ep_stream_pair(p_cdc, desc_ep); } -static bool ftdih_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { tusb_control_request_t const request = { .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_DEVICE, .type = TUSB_REQ_TYPE_VENDOR, .direction = TUSB_DIR_OUT }, - .bRequest = FTDI_SIO_RESET, - .wValue = tu_htole16(FTDI_SIO_RESET_SIO), + .bRequest = command, + .wValue = tu_htole16(value), .wIndex = 0, .wLength = 0 }; - p_cdc->user_control_cb = complete_cb; - tuh_xfer_t xfer = { .daddr = p_cdc->daddr, .ep_addr = 0, @@ -203,36 +202,19 @@ static bool ftdih_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, .user_data = user_data }; - TU_ASSERT(tuh_control_xfer(&xfer)); + return tuh_control_xfer(&xfer); +} + +static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data)); return true; } static bool ftdi_sio_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - tusb_control_request_t const request = { - .bmRequestType_bit = { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_VENDOR, - .direction = TUSB_DIR_OUT - }, - .bRequest = FTDI_SIO_MODEM_CTRL, - .wValue = tu_htole16(0x0300 | line_state), // 0x0300 is DTR and RTS enable - .wIndex = 0, // port - .wLength = 0 - }; - p_cdc->user_control_cb = complete_cb; - - tuh_xfer_t xfer = { - .daddr = p_cdc->daddr, - .ep_addr = 0, - .setup = &request, - .buffer = NULL, - .complete_cb = cdch_internal_control_complete, - .user_data = user_data - }; - - TU_ASSERT(tuh_control_xfer(&xfer)); + TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, cdch_internal_control_complete, user_data)); return true; } @@ -240,33 +222,10 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu { // TODO baudrate to baud divisor (void) baudrate; - uint16_t divisor = 0x4138; // FIXME hardcoded to 9600 baud - tusb_control_request_t const request = { - .bmRequestType_bit = { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_VENDOR, - .direction = TUSB_DIR_OUT - }, - .bRequest = FTDI_SIO_SET_BAUD_RATE, - .wValue = tu_htole16(divisor), - .wIndex = 0, // port - .wLength = 0 - }; - p_cdc->user_control_cb = complete_cb; - - tuh_xfer_t xfer = { - .daddr = p_cdc->daddr, - .ep_addr = 0, - .setup = &request, - .buffer = NULL, - .complete_cb = cdch_internal_control_complete, - .user_data = user_data - }; - - TU_ASSERT(tuh_control_xfer(&xfer)); + TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, cdch_internal_control_complete, user_data)); return true; } @@ -280,7 +239,7 @@ static void process_ftdi_config(tuh_xfer_t* xfer) { switch(state) { // Note may need to read FTDI eeprom case CONFIG_FTDI_RESET: - TU_ASSERT(ftdih_sio_reset(p_cdc, process_ftdi_config, CONFIG_FTDI_MODEM_CTRL),); + TU_ASSERT(ftdi_sio_reset(p_cdc, process_ftdi_config, CONFIG_FTDI_MODEM_CTRL),); break; case CONFIG_FTDI_MODEM_CTRL: @@ -335,6 +294,13 @@ enum { CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0]) }; +enum { + CONFIG_CP210X_IFC_ENABLE = 0, + CONFIG_CP210X_SET_BAUDRATE, + CONFIG_CP210X_SET_LINE_CTL, + CONFIG_CP210X_SET_MHS +}; + static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { // CP210x Interface includes 1 vendor interface + 2 bulk endpoints TU_VERIFY(itf_desc->bInterfaceSubClass == 0 && itf_desc->bInterfaceProtocol == 0 && itf_desc->bNumEndpoints == 2); @@ -343,6 +309,7 @@ static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY(p_cdc); + TU_LOG_CDCH("CP210x opened\r\n"); p_cdc->serial_protocol = SERIAL_PROTOCOL_CP210X; // endpoint pair @@ -352,6 +319,22 @@ static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui return open_ep_stream_pair(p_cdc, desc_ep); } +static void process_cp210x_config(tuh_xfer_t* xfer) { + uintptr_t const state = xfer->user_data; + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t *p_cdc = get_itf(idx); + TU_ASSERT(p_cdc,); + + switch (state) { + case CONFIG_CP210X_IFC_ENABLE: + + break; + + default: break; + } +} + #endif //--------------------------------------------------------------------+ @@ -740,7 +723,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t enum { // ACM - CONFIG_ACM_SET_CONTROL_LINE_STATE, + CONFIG_ACM_SET_CONTROL_LINE_STATE = 0, CONFIG_ACM_SET_LINE_CODING, CONFIG_ACM_COMPLETE, }; @@ -840,7 +823,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d if (TU_FTDI_VID == vid) { for (size_t i = 0; i < FTDI_PID_COUNT; i++) { if (ftdi_pids[i] == pid) { - return ftdih_open(daddr, itf_desc, max_len); + return ftdi_open(daddr, itf_desc, max_len); } } } @@ -918,9 +901,10 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) request.wIndex = tu_htole16((uint16_t) itf_num); tuh_xfer_t xfer; - xfer.daddr = daddr; - xfer.result = XFER_RESULT_SUCCESS; - xfer.setup = &request; + xfer.daddr = daddr; + xfer.result = XFER_RESULT_SUCCESS; + xfer.setup = &request; + xfer.user_data = 0; // fake transfer to kick-off process uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num); @@ -929,20 +913,18 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) switch (p_cdc->serial_protocol) { case SERIAL_PROTOCOL_ACM: - xfer.user_data = CONFIG_ACM_SET_CONTROL_LINE_STATE; process_acm_config(&xfer); break; #if CFG_TUH_CDC_FTDI case SERIAL_PROTOCOL_FTDI: - xfer.user_data = CONFIG_FTDI_RESET; process_ftdi_config(&xfer); break; #endif #if CFG_TUH_CDC_CP210X case SERIAL_PROTOCOL_CP210X: - //xfer.user_data = CONFIG_SET_CONTROL_LINE_STATE; + process_cp210x_config(&xfer); break; #endif -- cgit v1.3.1 From 86f6fd17edec73c6c7f19ece19fe1dba8575985a Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 27 Apr 2023 17:09:21 +0700 Subject: cp210x seems to work well --- examples/host/cdc_msc_hid/src/tusb_config.h | 3 +- src/class/cdc/cdc_host.c | 93 +++++++++++++++++++++++++++-- 2 files changed, 89 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index 2baf2b1ac..cc3775a76 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -97,7 +97,8 @@ #define CFG_TUH_HUB 1 // number of supported hubs #define CFG_TUH_CDC 1 // CDC ACM -#define CFG_TUH_CDC_FTDI 1 // FTDI UART +#define CFG_TUH_CDC_FTDI 1 // FTDI Serial +#define CFG_TUH_CDC_CP210X 1 // CP210x Serial #define CFG_TUH_HID (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces #define CFG_TUH_MSC 1 #define CFG_TUH_VENDOR 0 diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index c25ed48b0..a19f66181 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -180,6 +180,7 @@ static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint return open_ep_stream_pair(p_cdc, desc_ep); } +// set request without data static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { tusb_control_request_t const request = { .bmRequestType_bit = { @@ -207,11 +208,10 @@ static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint1 static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data)); - return true; + return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data); } -static bool ftdi_sio_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, cdch_internal_control_complete, user_data)); @@ -244,7 +244,8 @@ static void process_ftdi_config(tuh_xfer_t* xfer) { case CONFIG_FTDI_MODEM_CTRL: #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - TU_ASSERT(ftdi_sio_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_ftdi_config, CONFIG_FTDI_SET_BAUDRATE),); + TU_ASSERT( + ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_ftdi_config, CONFIG_FTDI_SET_BAUDRATE),); break; #else TU_ATTR_FALLTHROUGH; @@ -298,7 +299,8 @@ enum { CONFIG_CP210X_IFC_ENABLE = 0, CONFIG_CP210X_SET_BAUDRATE, CONFIG_CP210X_SET_LINE_CTL, - CONFIG_CP210X_SET_MHS + CONFIG_CP210X_SET_DTR_RTS, + CONFIG_CP210X_COMPLETE }; static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { @@ -319,6 +321,54 @@ static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui return open_ep_stream_pair(p_cdc, desc_ep); } +static bool cp210x_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_VENDOR, + .direction = TUSB_DIR_OUT + }, + .bRequest = command, + .wValue = tu_htole16(value), + .wIndex = p_cdc->bInterfaceNumber, + .wLength = tu_htole16(length) + }; + + // use usbh enum buf since application variable does not live long enough + uint8_t* enum_buf = NULL; + + if (buffer && length > 0) { + enum_buf = usbh_get_enum_buf(); + tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length); + } + + tuh_xfer_t xfer = { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request, + .buffer = enum_buf, + .complete_cb = complete_cb, + .user_data = user_data + }; + + return tuh_control_xfer(&xfer); +} + +static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + return cp210x_set_request(p_cdc, CP210X_IFC_ENABLE, enabled, NULL, 0, complete_cb, user_data); +} + +static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + baudrate = tu_htole32(baudrate); + return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baudrate, 4, complete_cb, user_data); +} + +static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + p_cdc->user_control_cb = complete_cb; + return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, cdch_internal_control_complete, user_data); +} + static void process_cp210x_config(tuh_xfer_t* xfer) { uintptr_t const state = xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); @@ -328,7 +378,38 @@ static void process_cp210x_config(tuh_xfer_t* xfer) { switch (state) { case CONFIG_CP210X_IFC_ENABLE: + TU_ASSERT(cp210x_ifc_enable(p_cdc, 1, process_cp210x_config, CONFIG_CP210X_SET_BAUDRATE),); + break; + + case CONFIG_CP210X_SET_BAUDRATE: { + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT(cp210x_set_baudrate(p_cdc, line_coding.bit_rate, process_cp210x_config, CONFIG_CP210X_SET_LINE_CTL),); + break; + #else + TU_ATTR_FALLTHROUGH; + #endif + } + case CONFIG_CP210X_SET_LINE_CTL: { + #if defined(CFG_TUH_CDC_LINE_CODING_ON_ENUM) && 0 // skip for now + cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; + break; + #else + TU_ATTR_FALLTHROUGH; + #endif + } + + case CONFIG_CP210X_SET_DTR_RTS: + #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cp210x_config, CONFIG_CP210X_COMPLETE),); + break; + #else + TU_ATTR_FALLTHROUGH; + #endif + + case CONFIG_CP210X_COMPLETE: + set_config_complete(p_cdc, idx, itf_num); break; default: break; @@ -567,7 +648,7 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c } #if CFG_TUH_CDC_FTDI else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) { - return ftdi_sio_modem_ctrl(p_cdc, line_state, complete_cb, user_data); + return ftdi_sio_set_modem_ctrl(p_cdc, line_state, complete_cb, user_data); } #endif else { -- cgit v1.3.1 From 438387be8c308c3bfed1ca952f5908a51a97b5c2 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 27 Apr 2023 17:32:56 +0700 Subject: more refactor --- examples/host/cdc_msc_hid/src/tusb_config.h | 4 +- src/class/cdc/cdc_host.c | 821 +++++++++++++++------------- 2 files changed, 430 insertions(+), 395 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index cc3775a76..abb75f068 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -97,8 +97,8 @@ #define CFG_TUH_HUB 1 // number of supported hubs #define CFG_TUH_CDC 1 // CDC ACM -#define CFG_TUH_CDC_FTDI 1 // FTDI Serial -#define CFG_TUH_CDC_CP210X 1 // CP210x Serial +#define CFG_TUH_CDC_FTDI 1 // FTDI Serial. FTDI is not part of CDC class, only to re-use CDC driver API +#define CFG_TUH_CDC_CP210X 1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_HID (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces #define CFG_TUH_MSC 1 #define CFG_TUH_VENDOR 0 diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index a19f66181..f47ac4f10 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -143,429 +143,183 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t c static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num); static void cdch_internal_control_complete(tuh_xfer_t* xfer); -//--------------------------------------------------------------------+ -// FTDI -//--------------------------------------------------------------------+ +//------------- FTDI prototypes -------------// #if CFG_TUH_CDC_FTDI - static uint16_t const ftdi_pids[] = { TU_FTDI_PID_LIST }; enum { FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0]) }; +static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len); +static void process_ftdi_config(tuh_xfer_t* xfer); + +static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +#endif + +//------------- CP210X prototypes -------------// +#if CFG_TUH_CDC_CP210X +static uint16_t const cp210x_pids[] = { TU_CP210X_PID_LIST }; enum { - CONFIG_FTDI_RESET = 0, - CONFIG_FTDI_MODEM_CTRL, - CONFIG_FTDI_SET_BAUDRATE, - CONFIG_FTDI_SET_DATA, - CONFIG_FTDI_COMPLETE + CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0]) }; -static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len) { - // FTDI Interface includes 1 vendor interface + 2 bulk endpoints - TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2); - TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); +static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); +static void process_cp210x_config(tuh_xfer_t* xfer); - cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); - TU_VERIFY(p_cdc); +static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +#endif - TU_LOG_CDCH("FTDI opened\r\n"); - p_cdc->serial_protocol = SERIAL_PROTOCOL_FTDI; +//--------------------------------------------------------------------+ +// APPLICATION API +//--------------------------------------------------------------------+ - // endpoint pair - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); +uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num) +{ + for(uint8_t i=0; idaddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i; + } + + return TUSB_INDEX_INVALID_8; } -// set request without data -static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - tusb_control_request_t const request = { - .bmRequestType_bit = { - .recipient = TUSB_REQ_RCPT_DEVICE, - .type = TUSB_REQ_TYPE_VENDOR, - .direction = TUSB_DIR_OUT - }, - .bRequest = command, - .wValue = tu_htole16(value), - .wIndex = 0, - .wLength = 0 - }; +bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc && info); - tuh_xfer_t xfer = { - .daddr = p_cdc->daddr, - .ep_addr = 0, - .setup = &request, - .buffer = NULL, - .complete_cb = complete_cb, - .user_data = user_data - }; + info->daddr = p_cdc->daddr; - return tuh_control_xfer(&xfer); + // re-construct descriptor + tusb_desc_interface_t* desc = &info->desc; + desc->bLength = sizeof(tusb_desc_interface_t); + desc->bDescriptorType = TUSB_DESC_INTERFACE; + + desc->bInterfaceNumber = p_cdc->bInterfaceNumber; + desc->bAlternateSetting = 0; + desc->bNumEndpoints = 2u + (p_cdc->ep_notif ? 1u : 0u); + desc->bInterfaceClass = TUSB_CLASS_CDC; + desc->bInterfaceSubClass = p_cdc->bInterfaceSubClass; + desc->bInterfaceProtocol = p_cdc->bInterfaceProtocol; + desc->iInterface = 0; // not used yet + + return true; } -static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +bool tuh_cdc_mounted(uint8_t idx) { - return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data); + cdch_interface_t* p_cdc = get_itf(idx); + return p_cdc != NULL; } -static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +bool tuh_cdc_get_dtr(uint8_t idx) { - p_cdc->user_control_cb = complete_cb; - TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, cdch_internal_control_complete, user_data)); - return true; + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); + + return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR) ? true : false; } -static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +bool tuh_cdc_get_rts(uint8_t idx) { - // TODO baudrate to baud divisor - (void) baudrate; - uint16_t divisor = 0x4138; // FIXME hardcoded to 9600 baud + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); - p_cdc->user_control_cb = complete_cb; - TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, cdch_internal_control_complete, user_data)); - return true; + return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false; } -static void process_ftdi_config(tuh_xfer_t* xfer) { - uintptr_t const state = xfer->user_data; - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT(p_cdc, ); +bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); - switch(state) { - // Note may need to read FTDI eeprom - case CONFIG_FTDI_RESET: - TU_ASSERT(ftdi_sio_reset(p_cdc, process_ftdi_config, CONFIG_FTDI_MODEM_CTRL),); - break; + *line_coding = p_cdc->line_coding; - case CONFIG_FTDI_MODEM_CTRL: - #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - TU_ASSERT( - ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_ftdi_config, CONFIG_FTDI_SET_BAUDRATE),); - break; - #else - TU_ATTR_FALLTHROUGH; - #endif + return true; +} - case CONFIG_FTDI_SET_BAUDRATE: { - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(ftdi_sio_set_baudrate(p_cdc, line_coding.bit_rate, process_ftdi_config, CONFIG_FTDI_SET_DATA),); - break; - #else - TU_ATTR_FALLTHROUGH; - #endif - } +//--------------------------------------------------------------------+ +// Write +//--------------------------------------------------------------------+ - case CONFIG_FTDI_SET_DATA: { - #if 0 // TODO set data format - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(ftdi_sio_set_data(p_cdc, process_ftdi_config, CONFIG_FTDI_COMPLETE),); - break; - #endif - #endif +uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); - TU_ATTR_FALLTHROUGH; - } + return tu_edpt_stream_write(&p_cdc->stream.tx, buffer, bufsize); +} - case CONFIG_FTDI_COMPLETE: - set_config_complete(p_cdc, idx, itf_num); - break; +uint32_t tuh_cdc_write_flush(uint8_t idx) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); - default: - break; - } + return tu_edpt_stream_write_xfer(&p_cdc->stream.tx); } -#endif +bool tuh_cdc_write_clear(uint8_t idx) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); + + return tu_edpt_stream_clear(&p_cdc->stream.tx); +} + +uint32_t tuh_cdc_write_available(uint8_t idx) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); + + return tu_edpt_stream_write_available(&p_cdc->stream.tx); +} //--------------------------------------------------------------------+ -// CP210x +// Read //--------------------------------------------------------------------+ -#if CFG_TUH_CDC_CP210X +uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); -static uint16_t const cp210x_pids[] = { TU_CP210X_PID_LIST }; -enum { - CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0]) -}; + return tu_edpt_stream_read(&p_cdc->stream.rx, buffer, bufsize); +} -enum { - CONFIG_CP210X_IFC_ENABLE = 0, - CONFIG_CP210X_SET_BAUDRATE, - CONFIG_CP210X_SET_LINE_CTL, - CONFIG_CP210X_SET_DTR_RTS, - CONFIG_CP210X_COMPLETE -}; +uint32_t tuh_cdc_read_available(uint8_t idx) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); -static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { - // CP210x Interface includes 1 vendor interface + 2 bulk endpoints - TU_VERIFY(itf_desc->bInterfaceSubClass == 0 && itf_desc->bInterfaceProtocol == 0 && itf_desc->bNumEndpoints == 2); - TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); + return tu_edpt_stream_read_available(&p_cdc->stream.rx); +} - cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); +bool tuh_cdc_peek(uint8_t idx, uint8_t* ch) +{ + cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - TU_LOG_CDCH("CP210x opened\r\n"); - p_cdc->serial_protocol = SERIAL_PROTOCOL_CP210X; + return tu_edpt_stream_peek(&p_cdc->stream.rx, ch); +} - // endpoint pair - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); +bool tuh_cdc_read_clear (uint8_t idx) +{ + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); - // data endpoints expected to be in pairs - return open_ep_stream_pair(p_cdc, desc_ep); + bool ret = tu_edpt_stream_clear(&p_cdc->stream.rx); + tu_edpt_stream_read_xfer(&p_cdc->stream.rx); + return ret; } -static bool cp210x_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - tusb_control_request_t const request = { - .bmRequestType_bit = { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_VENDOR, - .direction = TUSB_DIR_OUT - }, - .bRequest = command, - .wValue = tu_htole16(value), - .wIndex = p_cdc->bInterfaceNumber, - .wLength = tu_htole16(length) - }; - - // use usbh enum buf since application variable does not live long enough - uint8_t* enum_buf = NULL; - - if (buffer && length > 0) { - enum_buf = usbh_get_enum_buf(); - tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length); - } - - tuh_xfer_t xfer = { - .daddr = p_cdc->daddr, - .ep_addr = 0, - .setup = &request, - .buffer = enum_buf, - .complete_cb = complete_cb, - .user_data = user_data - }; - - return tuh_control_xfer(&xfer); -} - -static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - return cp210x_set_request(p_cdc, CP210X_IFC_ENABLE, enabled, NULL, 0, complete_cb, user_data); -} - -static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - baudrate = tu_htole32(baudrate); - return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baudrate, 4, complete_cb, user_data); -} - -static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ - p_cdc->user_control_cb = complete_cb; - return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, cdch_internal_control_complete, user_data); -} - -static void process_cp210x_config(tuh_xfer_t* xfer) { - uintptr_t const state = xfer->user_data; - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t *p_cdc = get_itf(idx); - TU_ASSERT(p_cdc,); - - switch (state) { - case CONFIG_CP210X_IFC_ENABLE: - TU_ASSERT(cp210x_ifc_enable(p_cdc, 1, process_cp210x_config, CONFIG_CP210X_SET_BAUDRATE),); - break; - - case CONFIG_CP210X_SET_BAUDRATE: { - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(cp210x_set_baudrate(p_cdc, line_coding.bit_rate, process_cp210x_config, CONFIG_CP210X_SET_LINE_CTL),); - break; - #else - TU_ATTR_FALLTHROUGH; - #endif - } - - case CONFIG_CP210X_SET_LINE_CTL: { - #if defined(CFG_TUH_CDC_LINE_CODING_ON_ENUM) && 0 // skip for now - cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - break; - #else - TU_ATTR_FALLTHROUGH; - #endif - } - - case CONFIG_CP210X_SET_DTR_RTS: - #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cp210x_config, CONFIG_CP210X_COMPLETE),); - break; - #else - TU_ATTR_FALLTHROUGH; - #endif - - case CONFIG_CP210X_COMPLETE: - set_config_complete(p_cdc, idx, itf_num); - break; - - default: break; - } -} - -#endif - -//--------------------------------------------------------------------+ -// APPLICATION API -//--------------------------------------------------------------------+ - -uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num) -{ - for(uint8_t i=0; idaddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i; - } - - return TUSB_INDEX_INVALID_8; -} - -bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) -{ - cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc && info); - - info->daddr = p_cdc->daddr; - - // re-construct descriptor - tusb_desc_interface_t* desc = &info->desc; - desc->bLength = sizeof(tusb_desc_interface_t); - desc->bDescriptorType = TUSB_DESC_INTERFACE; - - desc->bInterfaceNumber = p_cdc->bInterfaceNumber; - desc->bAlternateSetting = 0; - desc->bNumEndpoints = 2u + (p_cdc->ep_notif ? 1u : 0u); - desc->bInterfaceClass = TUSB_CLASS_CDC; - desc->bInterfaceSubClass = p_cdc->bInterfaceSubClass; - desc->bInterfaceProtocol = p_cdc->bInterfaceProtocol; - desc->iInterface = 0; // not used yet - - return true; -} - -bool tuh_cdc_mounted(uint8_t idx) -{ - cdch_interface_t* p_cdc = get_itf(idx); - return p_cdc != NULL; -} - -bool tuh_cdc_get_dtr(uint8_t idx) -{ - cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc); - - return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR) ? true : false; -} - -bool tuh_cdc_get_rts(uint8_t idx) -{ - cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc); - - return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false; -} - -bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding) -{ - cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc); - - *line_coding = p_cdc->line_coding; - - return true; -} - -//--------------------------------------------------------------------+ -// Write -//--------------------------------------------------------------------+ - -uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize) -{ - cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc); - - return tu_edpt_stream_write(&p_cdc->stream.tx, buffer, bufsize); -} - -uint32_t tuh_cdc_write_flush(uint8_t idx) -{ - cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc); - - return tu_edpt_stream_write_xfer(&p_cdc->stream.tx); -} - -bool tuh_cdc_write_clear(uint8_t idx) -{ - cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc); - - return tu_edpt_stream_clear(&p_cdc->stream.tx); -} - -uint32_t tuh_cdc_write_available(uint8_t idx) -{ - cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc); - - return tu_edpt_stream_write_available(&p_cdc->stream.tx); -} - -//--------------------------------------------------------------------+ -// Read -//--------------------------------------------------------------------+ - -uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) -{ - cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc); - - return tu_edpt_stream_read(&p_cdc->stream.rx, buffer, bufsize); -} - -uint32_t tuh_cdc_read_available(uint8_t idx) -{ - cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc); - - return tu_edpt_stream_read_available(&p_cdc->stream.rx); -} - -bool tuh_cdc_peek(uint8_t idx, uint8_t* ch) -{ - cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc); - - return tu_edpt_stream_peek(&p_cdc->stream.rx, ch); -} - -bool tuh_cdc_read_clear (uint8_t idx) -{ - cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc); - - bool ret = tu_edpt_stream_clear(&p_cdc->stream.rx); - tu_edpt_stream_read_xfer(&p_cdc->stream.rx); - return ret; -} - -//--------------------------------------------------------------------+ -// Control Endpoint API -//--------------------------------------------------------------------+ +//--------------------------------------------------------------------+ +// Control Endpoint API +//--------------------------------------------------------------------+ // internal control complete to update state such as line state, encoding static void cdch_internal_control_complete(tuh_xfer_t* xfer) @@ -610,6 +364,7 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) } static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + TU_LOG_CDCH("CDC ACM Set Control Line State\r\n"); tusb_control_request_t const request = { .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, @@ -641,18 +396,23 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && support_line_request(p_cdc)); - TU_LOG_CDCH("CDC Set Control Line State\r\n"); - if(p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM ) { - return acm_set_control_line_state(p_cdc, line_state, complete_cb, user_data); - } - #if CFG_TUH_CDC_FTDI - else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) { - return ftdi_sio_set_modem_ctrl(p_cdc, line_state, complete_cb, user_data); - } - #endif - else { - return false; + switch(p_cdc->serial_protocol) { + case SERIAL_PROTOCOL_ACM: + return acm_set_control_line_state(p_cdc, line_state, complete_cb, user_data); + + #if CFG_TUH_CDC_FTDI + case SERIAL_PROTOCOL_FTDI: + return ftdi_sio_set_modem_ctrl(p_cdc, line_state, complete_cb, user_data); + #endif + + #if CFG_TUH_CDC_CP210X + case SERIAL_PROTOCOL_CP210X: + return ftdi_sio_set_modem_ctrl(p_cdc, line_state, complete_cb, user_data); + #endif + + default: + return false; } } @@ -693,17 +453,22 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, TU_VERIFY(p_cdc && support_line_request(p_cdc)); TU_LOG_CDCH("CDC Set Line Conding\r\n"); - if (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM) { - return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data); - } - #if CFG_TUH_CDC_FTDI - else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) { - // FTDI need to set baud rate and data bits, parity, stop bits separately - return ftdi_sio_set_baudrate(p_cdc, line_coding->bit_rate, complete_cb, user_data); - } - #endif - else { - return false; + switch(p_cdc->serial_protocol) { + case SERIAL_PROTOCOL_ACM: + return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data); + + #if CFG_TUH_CDC_FTDI + case SERIAL_PROTOCOL_FTDI: + // FTDI need to set baud rate and data bits, parity, stop bits separately + return ftdi_sio_set_baudrate(p_cdc, line_coding->bit_rate, complete_cb, user_data); + #endif + + #if CFG_TUH_CDC_CP210X + case SERIAL_PROTOCOL_CP210X: + return cp210x_set_baudrate(p_cdc, line_coding->bit_rate, complete_cb, user_data); + #endif + + default: return false; } } @@ -949,7 +714,7 @@ static void process_acm_config(tuh_xfer_t* xfer) #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM if (p_cdc->acm_capability.support_line_request) { - TU_ASSERT(tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_acm_config, + TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_acm_config, CONFIG_ACM_SET_LINE_CODING), ); break; } @@ -1015,4 +780,274 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) return true; } +//--------------------------------------------------------------------+ +// FTDI +//--------------------------------------------------------------------+ +#if CFG_TUH_CDC_FTDI + +enum { + CONFIG_FTDI_RESET = 0, + CONFIG_FTDI_MODEM_CTRL, + CONFIG_FTDI_SET_BAUDRATE, + CONFIG_FTDI_SET_DATA, + CONFIG_FTDI_COMPLETE +}; + +static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len) { + // FTDI Interface includes 1 vendor interface + 2 bulk endpoints + TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2); + TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); + + cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); + TU_VERIFY(p_cdc); + + TU_LOG_CDCH("FTDI opened\r\n"); + + p_cdc->serial_protocol = SERIAL_PROTOCOL_FTDI; + + // endpoint pair + tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); + + // data endpoints expected to be in pairs + return open_ep_stream_pair(p_cdc, desc_ep); +} + +// set request without data +static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_DEVICE, + .type = TUSB_REQ_TYPE_VENDOR, + .direction = TUSB_DIR_OUT + }, + .bRequest = command, + .wValue = tu_htole16(value), + .wIndex = 0, + .wLength = 0 + }; + + tuh_xfer_t xfer = { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request, + .buffer = NULL, + .complete_cb = complete_cb, + .user_data = user_data + }; + + return tuh_control_xfer(&xfer); +} + +static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data); +} + +static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + TU_LOG_CDCH("CDC FTDI Set Control Line State\r\n"); + p_cdc->user_control_cb = complete_cb; + TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, cdch_internal_control_complete, user_data)); + return true; +} + +static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + // TODO baudrate to baud divisor + (void) baudrate; + uint16_t divisor = 0x4138; // FIXME hardcoded to 9600 baud + + TU_LOG_CDCH("CDC FTDI Set BaudRate = %u, divisor = %u\n", baudrate, divisor); + + p_cdc->user_control_cb = complete_cb; + TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, cdch_internal_control_complete, user_data)); + return true; +} + +static void process_ftdi_config(tuh_xfer_t* xfer) { + uintptr_t const state = xfer->user_data; + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc, ); + + switch(state) { + // Note may need to read FTDI eeprom + case CONFIG_FTDI_RESET: + TU_ASSERT(ftdi_sio_reset(p_cdc, process_ftdi_config, CONFIG_FTDI_MODEM_CTRL),); + break; + + case CONFIG_FTDI_MODEM_CTRL: + #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + TU_ASSERT( + ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_ftdi_config, CONFIG_FTDI_SET_BAUDRATE),); + break; + #else + TU_ATTR_FALLTHROUGH; + #endif + + case CONFIG_FTDI_SET_BAUDRATE: { + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT(ftdi_sio_set_baudrate(p_cdc, line_coding.bit_rate, process_ftdi_config, CONFIG_FTDI_SET_DATA),); + break; + #else + TU_ATTR_FALLTHROUGH; + #endif + } + + case CONFIG_FTDI_SET_DATA: { + #if 0 // TODO set data format + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT(ftdi_sio_set_data(p_cdc, process_ftdi_config, CONFIG_FTDI_COMPLETE),); + break; + #endif + #endif + + TU_ATTR_FALLTHROUGH; + } + + case CONFIG_FTDI_COMPLETE: + set_config_complete(p_cdc, idx, itf_num); + break; + + default: + break; + } +} + +#endif + +//--------------------------------------------------------------------+ +// CP210x +//--------------------------------------------------------------------+ + +#if CFG_TUH_CDC_CP210X + +enum { + CONFIG_CP210X_IFC_ENABLE = 0, + CONFIG_CP210X_SET_BAUDRATE, + CONFIG_CP210X_SET_LINE_CTL, + CONFIG_CP210X_SET_DTR_RTS, + CONFIG_CP210X_COMPLETE +}; + +static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { + // CP210x Interface includes 1 vendor interface + 2 bulk endpoints + TU_VERIFY(itf_desc->bInterfaceSubClass == 0 && itf_desc->bInterfaceProtocol == 0 && itf_desc->bNumEndpoints == 2); + TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); + + cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); + TU_VERIFY(p_cdc); + + TU_LOG_CDCH("CP210x opened\r\n"); + p_cdc->serial_protocol = SERIAL_PROTOCOL_CP210X; + + // endpoint pair + tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); + + // data endpoints expected to be in pairs + return open_ep_stream_pair(p_cdc, desc_ep); +} + +static bool cp210x_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_VENDOR, + .direction = TUSB_DIR_OUT + }, + .bRequest = command, + .wValue = tu_htole16(value), + .wIndex = p_cdc->bInterfaceNumber, + .wLength = tu_htole16(length) + }; + + // use usbh enum buf since application variable does not live long enough + uint8_t* enum_buf = NULL; + + if (buffer && length > 0) { + enum_buf = usbh_get_enum_buf(); + tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length); + } + + tuh_xfer_t xfer = { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request, + .buffer = enum_buf, + .complete_cb = complete_cb, + .user_data = user_data + }; + + return tuh_control_xfer(&xfer); +} + +static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + return cp210x_set_request(p_cdc, CP210X_IFC_ENABLE, enabled, NULL, 0, complete_cb, user_data); +} + +static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + TU_LOG_CDCH("CDC CP210x Set BaudRate = %u\n", baudrate); + baudrate = tu_htole32(baudrate); + return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baudrate, 4, complete_cb, user_data); +} + +static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + TU_LOG_CDCH("CDC CP210x Set Control Line State\r\n"); + p_cdc->user_control_cb = complete_cb; + return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, cdch_internal_control_complete, user_data); +} + +static void process_cp210x_config(tuh_xfer_t* xfer) { + uintptr_t const state = xfer->user_data; + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t *p_cdc = get_itf(idx); + TU_ASSERT(p_cdc,); + + switch (state) { + case CONFIG_CP210X_IFC_ENABLE: + TU_ASSERT(cp210x_ifc_enable(p_cdc, 1, process_cp210x_config, CONFIG_CP210X_SET_BAUDRATE),); + break; + + case CONFIG_CP210X_SET_BAUDRATE: { + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT(cp210x_set_baudrate(p_cdc, line_coding.bit_rate, process_cp210x_config, CONFIG_CP210X_SET_LINE_CTL),); + break; + #else + TU_ATTR_FALLTHROUGH; + #endif + } + + case CONFIG_CP210X_SET_LINE_CTL: { + #if defined(CFG_TUH_CDC_LINE_CODING_ON_ENUM) && 0 // skip for now + cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; + break; + #else + TU_ATTR_FALLTHROUGH; + #endif + } + + case CONFIG_CP210X_SET_DTR_RTS: + #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cp210x_config, CONFIG_CP210X_COMPLETE),); + break; + #else + TU_ATTR_FALLTHROUGH; + #endif + + case CONFIG_CP210X_COMPLETE: + set_config_complete(p_cdc, idx, itf_num); + break; + + default: break; + } +} + +#endif + #endif -- cgit v1.3.1 From c10f52b2375de8cca153beffb7852877d4cd7e58 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 27 Apr 2023 17:39:02 +0700 Subject: forgot to add cp210x header --- src/class/cdc/serial/cp210x.h | 64 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 src/class/cdc/serial/cp210x.h (limited to 'src') diff --git a/src/class/cdc/serial/cp210x.h b/src/class/cdc/serial/cp210x.h new file mode 100644 index 000000000..b01417092 --- /dev/null +++ b/src/class/cdc/serial/cp210x.h @@ -0,0 +1,64 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (thach@tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef TUSB_CP210X_H +#define TUSB_CP210X_H + +// Protocol details can be found at AN571: CP210x Virtual COM Port Interface +// https://www.silabs.com/documents/public/application-notes/AN571.pdf + +#define TU_CP210X_VID 0x10C4 +#define TU_CP210X_PID_LIST \ + 0xEA60, 0xEA70 + +/* Config request codes */ +#define CP210X_IFC_ENABLE 0x00 +#define CP210X_SET_BAUDDIV 0x01 +#define CP210X_GET_BAUDDIV 0x02 +#define CP210X_SET_LINE_CTL 0x03 // Set parity, data bits, stop bits +#define CP210X_GET_LINE_CTL 0x04 +#define CP210X_SET_BREAK 0x05 +#define CP210X_IMM_CHAR 0x06 +#define CP210X_SET_MHS 0x07 // Set DTR, RTS +#define CP210X_GET_MDMSTS 0x08 // Get modem status (DTR, RTS, CTS, DSR, RI, DCD) +#define CP210X_SET_XON 0x09 +#define CP210X_SET_XOFF 0x0A +#define CP210X_SET_EVENTMASK 0x0B +#define CP210X_GET_EVENTMASK 0x0C +#define CP210X_SET_CHAR 0x0D +#define CP210X_GET_CHARS 0x0E +#define CP210X_GET_PROPS 0x0F +#define CP210X_GET_COMM_STATUS 0x10 +#define CP210X_RESET 0x11 +#define CP210X_PURGE 0x12 +#define CP210X_SET_FLOW 0x13 +#define CP210X_GET_FLOW 0x14 +#define CP210X_EMBED_EVENTS 0x15 +#define CP210X_GET_EVENTSTATE 0x16 +#define CP210X_SET_CHARS 0x19 +#define CP210X_GET_BAUDRATE 0x1D +#define CP210X_SET_BAUDRATE 0x1E +#define CP210X_VENDOR_SPECIFIC 0xFF // GPIO, Recipient must be Device + +#endif //TUSB_CP210X_H -- cgit v1.3.1 From 8214f0f497271116d07e874f2e5f764f1e8ebd47 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 27 Apr 2023 17:40:08 +0700 Subject: clean up --- src/class/cdc/cdc_host.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index f47ac4f10..ab1a10427 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -33,14 +33,6 @@ #include "cdc_host.h" -#if CFG_TUH_CDC_FTDI - #include "serial/ftdi_sio.h" -#endif - -#if CFG_TUH_CDC_CP210X - #include "serial/cp210x.h" -#endif - // Debug level, TUSB_CFG_DEBUG must be at least this level for debug message #define CDCH_DEBUG 2 @@ -145,6 +137,8 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer); //------------- FTDI prototypes -------------// #if CFG_TUH_CDC_FTDI +#include "serial/ftdi_sio.h" + static uint16_t const ftdi_pids[] = { TU_FTDI_PID_LIST }; enum { FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0]) @@ -159,6 +153,8 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu //------------- CP210X prototypes -------------// #if CFG_TUH_CDC_CP210X +#include "serial/cp210x.h" + static uint16_t const cp210x_pids[] = { TU_CP210X_PID_LIST }; enum { CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0]) -- cgit v1.3.1 From ee58278ed2502a6e9b6d2625f2fe1bf453038716 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 27 Apr 2023 23:08:25 +0700 Subject: add code to calculate divisor from baudrate for ftdi --- src/class/cdc/cdc_host.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index ab1a10427..132b1ef09 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -847,13 +847,36 @@ static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state return true; } -static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base) +{ + const uint8_t divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 }; + uint32_t divisor; + + /* divisor shifted 3 bits to the left */ + uint32_t divisor3 = base / (2 * baud); + divisor = (divisor3 >> 3); + divisor |= (uint32_t) divfrac[divisor3 & 0x7] << 14; + + /* Deal with special cases for highest baud rates. */ + if (divisor == 1) { /* 1.0 */ + divisor = 0; + } + else if (divisor == 0x4001) { /* 1.5 */ + divisor = 1; + } + + return divisor; +} + +static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) { - // TODO baudrate to baud divisor - (void) baudrate; - uint16_t divisor = 0x4138; // FIXME hardcoded to 9600 baud + return ftdi_232bm_baud_base_to_divisor(baud, 48000000u); +} - TU_LOG_CDCH("CDC FTDI Set BaudRate = %u, divisor = %u\n", baudrate, divisor); +static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate); + TU_LOG_CDCH("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\n", baudrate, divisor); p_cdc->user_control_cb = complete_cb; TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, cdch_internal_control_complete, user_data)); @@ -985,7 +1008,7 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe } static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG_CDCH("CDC CP210x Set BaudRate = %u\n", baudrate); + TU_LOG_CDCH("CDC CP210x Set BaudRate = %lu\n", baudrate); baudrate = tu_htole32(baudrate); return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baudrate, 4, complete_cb, user_data); } -- cgit v1.3.1 From 732686cc109aea9527d3133c3b8e61dc045dc233 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 27 Apr 2023 23:22:10 +0700 Subject: add tuh_cdc_set_baudrate() --- src/class/cdc/cdc_host.c | 43 ++++++++++++++++++++++++++++++++++--------- src/class/cdc/cdc_host.h | 13 +++++++++---- 2 files changed, 43 insertions(+), 13 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 132b1ef09..4c87ff1ad 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -126,11 +126,6 @@ static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const return NULL; } -static inline bool support_line_request(cdch_interface_t const* p_cdc) { - return (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM && p_cdc->acm_capability.support_line_request) || - (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI); -} - static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep); static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num); static void cdch_internal_control_complete(tuh_xfer_t* xfer); @@ -391,10 +386,11 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_st bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc && support_line_request(p_cdc)); + TU_VERIFY(p_cdc); switch(p_cdc->serial_protocol) { case SERIAL_PROTOCOL_ACM: + TU_VERIFY(p_cdc->acm_capability.support_line_request); return acm_set_control_line_state(p_cdc, line_state, complete_cb, user_data); #if CFG_TUH_CDC_FTDI @@ -413,6 +409,8 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c } bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + TU_LOG_CDCH("CDC ACM Set Line Conding\r\n"); + tusb_control_request_t const request = { .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, @@ -446,11 +444,11 @@ bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc && support_line_request(p_cdc)); - TU_LOG_CDCH("CDC Set Line Conding\r\n"); + TU_VERIFY(p_cdc); switch(p_cdc->serial_protocol) { case SERIAL_PROTOCOL_ACM: + TU_VERIFY(p_cdc->acm_capability.support_line_request); return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data); #if CFG_TUH_CDC_FTDI @@ -468,6 +466,33 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, } } +bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc); + + switch(p_cdc->serial_protocol) { + case SERIAL_PROTOCOL_ACM: { + TU_VERIFY(p_cdc->acm_capability.support_line_request); + cdc_line_coding_t line_coding = p_cdc->line_coding; + line_coding.bit_rate = baudrate; + return acm_set_line_coding(p_cdc, &line_coding, complete_cb, user_data); + } + + #if CFG_TUH_CDC_FTDI + case SERIAL_PROTOCOL_FTDI: + // FTDI need to set baud rate and data bits, parity, stop bits separately + return ftdi_sio_set_baudrate(p_cdc, baudrate, complete_cb, user_data); + #endif + + #if CFG_TUH_CDC_CP210X + case SERIAL_PROTOCOL_CP210X: + return cp210x_set_baudrate(p_cdc, baudrate, complete_cb, user_data); + #endif + + default: return false; + } +} + //--------------------------------------------------------------------+ // CLASS-USBH API //--------------------------------------------------------------------+ @@ -722,7 +747,7 @@ static void process_acm_config(tuh_xfer_t* xfer) if (p_cdc->acm_capability.support_line_request) { cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(tuh_cdc_set_line_coding(idx, &line_coding, process_acm_config, CONFIG_ACM_COMPLETE), ); + TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, process_acm_config, CONFIG_ACM_COMPLETE), ); break; } #endif diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index a1e78f158..971ebe2ae 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -140,22 +140,27 @@ bool tuh_cdc_read_clear (uint8_t idx); // Request to Set Control Line State: DTR (bit 0), RTS (bit 1) bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -// Request to Set Line Coding +// Request to set baudrate +bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + +// Request to Set Line Coding (ACM only) bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -// Request to Get Line Coding +// Request to Get Line Coding (ACM only) // Should only use if tuh_cdc_set_line_coding() / tuh_cdc_get_line_coding() never got invoked and // CFG_TUH_CDC_LINE_CODING_ON_ENUM is not defined // bool tuh_cdc_get_line_coding(uint8_t idx, cdc_line_coding_t* coding); // Connect by set both DTR, RTS -static inline bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +TU_ATTR_ALWAYS_INLINE static inline +bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return tuh_cdc_set_control_line_state(idx, CDC_CONTROL_LINE_STATE_DTR | CDC_CONTROL_LINE_STATE_RTS, complete_cb, user_data); } // Disconnect by clear both DTR, RTS -static inline bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +TU_ATTR_ALWAYS_INLINE static inline +bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return tuh_cdc_set_control_line_state(idx, 0x00, complete_cb, user_data); } -- cgit v1.3.1 From 8f4797663902cd445994ed48f2cd093161af68f2 Mon Sep 17 00:00:00 2001 From: Jean-Baptiste Theou Date: Thu, 27 Apr 2023 15:48:15 -1000 Subject: cdc: fix line_coding aligment While calling tud_cdc_n_get_line_coding, the structure is copied into the destination. Dump of assembler code for function tud_cdc_n_get_line_coding: 0x000193f4 <+0>: mov.w r2, #2112 @ 0x840 0x000193f8 <+4>: ldr r3, [pc, #20] @ (0x19410 ) 0x000193fa <+6>: mla r0, r2, r0, r3 => 0x000193fe <+10>: ldr.w r3, [r0, #6] 0x00019402 <+14>: str r3, [r1, #0] On some platform (tested on LPC55S28), the address needs to be 4-bytes aligned. Without this, the address is (gdb) p &_cdcd_itf.line_coding $3 = (cdc_line_coding_t *) 0x40100006 <_cdcd_itf+6> which leads to a HardFault. With this fix (gdb) p &_cdcd_itf.line_coding $5 = (cdc_line_coding_t *) 0x40100008 <_cdcd_itf+8> and the function can be called properly Signed-off-by: Jean-Baptiste Theou --- src/class/cdc/cdc_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index a82ef1d62..bf15d0d97 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -53,7 +53,7 @@ typedef struct /*------------- From this point, data is not cleared by bus reset -------------*/ char wanted_char; - cdc_line_coding_t line_coding; + CFG_TUSB_MEM_ALIGN cdc_line_coding_t line_coding; // FIFO tu_fifo_t rx_ff; -- cgit v1.3.1 From 190acc1fb0579d3e097ba2b0b96033740ecee26e Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 28 Apr 2023 11:12:03 +0700 Subject: add aligned(4) for cdc_line_coding_t --- src/class/cdc/cdc_device.c | 2 +- src/class/cdc/cdc_host.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index bf15d0d97..5adce521d 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -53,7 +53,7 @@ typedef struct /*------------- From this point, data is not cleared by bus reset -------------*/ char wanted_char; - CFG_TUSB_MEM_ALIGN cdc_line_coding_t line_coding; + TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; // FIFO tu_fifo_t rx_ff; diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 4c87ff1ad..e2447d033 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -58,8 +58,8 @@ typedef struct { cdc_acm_capability_t acm_capability; uint8_t ep_notif; - cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width - uint8_t line_state; // DTR (bit0), RTS (bit1) + uint8_t line_state; // DTR (bit0), RTS (bit1) + TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width tuh_xfer_cb_t user_control_cb; -- cgit v1.3.1 From 0a43a7b418dc9ba510505eef6abbc2da6f9151e5 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 28 Apr 2023 19:06:08 +0700 Subject: improve host serial drivers - tuh_control_xfer() update xfer result to user_data if complete callback = NULL (sync/blocking) - refactor host serial driver for acm/ftdi/cp210x --- src/class/cdc/cdc_host.c | 630 ++++++++++++++++++++++++----------------------- src/class/cdc/cdc_host.h | 6 +- src/host/usbh.c | 56 +---- 3 files changed, 343 insertions(+), 349 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index e2447d033..b25bc5512 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -39,22 +39,16 @@ #define TU_LOG_CDCH(...) TU_LOG(CDCH_DEBUG, __VA_ARGS__) //--------------------------------------------------------------------+ -// MACRO CONSTANT TYPEDEF +// Host CDC Interface //--------------------------------------------------------------------+ -enum { - SERIAL_PROTOCOL_ACM = 0, - SERIAL_PROTOCOL_FTDI, - SERIAL_PROTOCOL_CP210X, -}; - typedef struct { uint8_t daddr; uint8_t bInterfaceNumber; uint8_t bInterfaceSubClass; uint8_t bInterfaceProtocol; - uint8_t serial_protocol; + uint8_t serial_drid; // Serial Driver ID cdc_acm_capability_t acm_capability; uint8_t ep_notif; @@ -76,12 +70,102 @@ typedef struct { } cdch_interface_t; +CFG_TUH_MEM_SECTION +static cdch_interface_t cdch_data[CFG_TUH_CDC]; + //--------------------------------------------------------------------+ -// INTERNAL OBJECT & FUNCTION DECLARATION +// Serial Driver //--------------------------------------------------------------------+ -CFG_TUH_MEM_SECTION -static cdch_interface_t cdch_data[CFG_TUH_CDC]; +//------------- ACM prototypes -------------// +static void acm_process_config(tuh_xfer_t* xfer); + +static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + +//------------- FTDI prototypes -------------// +#if CFG_TUH_CDC_FTDI +#include "serial/ftdi_sio.h" + +static uint16_t const ftdi_pids[] = { TU_FTDI_PID_LIST }; +enum { + FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0]) +}; + +// Store last request baudrate since divisor to baudrate is not easy +static uint32_t _ftdi_requested_baud; + +static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len); +static void ftdi_process_config(tuh_xfer_t* xfer); + +static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +#endif + +//------------- CP210X prototypes -------------// +#if CFG_TUH_CDC_CP210X +#include "serial/cp210x.h" + +static uint16_t const cp210x_pids[] = { TU_CP210X_PID_LIST }; +enum { + CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0]) +}; + +static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); +static void cp210x_process_config(tuh_xfer_t* xfer); + +static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +#endif + +enum { + SERIAL_DRIVER_ACM = 0, + +#if CFG_TUH_CDC_FTDI + SERIAL_DRIVER_FTDI, +#endif + +#if CFG_TUH_CDC_CP210X + SERIAL_DRIVER_CP210X, +#endif +}; + +typedef struct { + void (*const process_set_config)(tuh_xfer_t* xfer); + bool (*const set_control_line_state)(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + bool (*const set_baudrate)(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +} cdch_serial_driver_t; + +// Note driver list must be in the same order as SERIAL_DRIVER enum +static const cdch_serial_driver_t serial_drivers[] = { + { .process_set_config = acm_process_config, + .set_control_line_state = acm_set_control_line_state, + .set_baudrate = acm_set_baudrate + }, + + #if CFG_TUH_CDC_FTDI + { .process_set_config = ftdi_process_config, + .set_control_line_state = ftdi_sio_set_modem_ctrl, + .set_baudrate = ftdi_sio_set_baudrate + }, + #endif + + #if CFG_TUH_CDC_CP210X + { .process_set_config = cp210x_process_config, + .set_control_line_state = cp210x_set_modem_ctrl, + .set_baudrate = cp210x_set_baudrate + }, + #endif +}; + +enum { + SERIAL_DRIVER_COUNT = sizeof(serial_drivers) / sizeof(serial_drivers[0]) +}; + +//--------------------------------------------------------------------+ +// INTERNAL OBJECT & FUNCTION DECLARATION +//--------------------------------------------------------------------+ static inline cdch_interface_t* get_itf(uint8_t idx) { @@ -130,39 +214,6 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t c static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num); static void cdch_internal_control_complete(tuh_xfer_t* xfer); -//------------- FTDI prototypes -------------// -#if CFG_TUH_CDC_FTDI -#include "serial/ftdi_sio.h" - -static uint16_t const ftdi_pids[] = { TU_FTDI_PID_LIST }; -enum { - FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0]) -}; - -static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len); -static void process_ftdi_config(tuh_xfer_t* xfer); - -static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -#endif - -//------------- CP210X prototypes -------------// -#if CFG_TUH_CDC_CP210X -#include "serial/cp210x.h" - -static uint16_t const cp210x_pids[] = { TU_CP210X_PID_LIST }; -enum { - CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0]) -}; - -static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); -static void process_cp210x_config(tuh_xfer_t* xfer); - -static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -#endif - - //--------------------------------------------------------------------+ // APPLICATION API //--------------------------------------------------------------------+ @@ -322,175 +373,86 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) if (xfer->result == XFER_RESULT_SUCCESS) { - if (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM) { - switch (xfer->setup->bRequest) { - case CDC_REQUEST_SET_CONTROL_LINE_STATE: - p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue); - break; - - case CDC_REQUEST_SET_LINE_CODING: { - uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength)); - memcpy(&p_cdc->line_coding, xfer->buffer, len); + switch (p_cdc->serial_drid) { + case SERIAL_DRIVER_ACM: + switch (xfer->setup->bRequest) { + case CDC_REQUEST_SET_CONTROL_LINE_STATE: + p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue); + break; + + case CDC_REQUEST_SET_LINE_CODING: { + uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength)); + memcpy(&p_cdc->line_coding, xfer->buffer, len); + } + break; + + default: break; } - break; + break; - default: break; - } - } - #if CFG_TUH_CDC_FTDI - else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) { - switch (xfer->setup->bRequest) { - case FTDI_SIO_MODEM_CTRL: - p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff); - break; + #if CFG_TUH_CDC_FTDI + case SERIAL_DRIVER_FTDI: + switch (xfer->setup->bRequest) { + case FTDI_SIO_MODEM_CTRL: + p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff); + break; - default: break; - } - } - #endif - } - - xfer->complete_cb = p_cdc->user_control_cb; - xfer->complete_cb(xfer); -} + case FTDI_SIO_SET_BAUD_RATE: + // convert from divisor to baudrate is not supported + p_cdc->line_coding.bit_rate = _ftdi_requested_baud; + break; -static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG_CDCH("CDC ACM Set Control Line State\r\n"); - tusb_control_request_t const request = { - .bmRequestType_bit = { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_CLASS, - .direction = TUSB_DIR_OUT - }, - .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE, - .wValue = tu_htole16(line_state), - .wIndex = tu_htole16((uint16_t) p_cdc->bInterfaceNumber), - .wLength = 0 - }; + default: break; + } + break; + #endif - p_cdc->user_control_cb = complete_cb; + #if CFG_TUH_CDC_CP210X + case SERIAL_DRIVER_CP210X: + switch(xfer->setup->bRequest) { + case CP210X_SET_MHS: + p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff); + break; + + case CP210X_SET_BAUDRATE: { + uint32_t baudrate; + memcpy(&baudrate, xfer->buffer, sizeof(uint32_t)); + p_cdc->line_coding.bit_rate = tu_le32toh(baudrate); + } + break; + } + break; + #endif - tuh_xfer_t xfer = { - .daddr = p_cdc->daddr, - .ep_addr = 0, - .setup = &request, - .buffer = NULL, - .complete_cb = cdch_internal_control_complete, - .user_data = user_data - }; + default: break; + } + } - TU_ASSERT(tuh_control_xfer(&xfer)); - return true; + xfer->complete_cb = p_cdc->user_control_cb; + if (xfer->complete_cb) { + xfer->complete_cb(xfer); + } } -bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc); - - switch(p_cdc->serial_protocol) { - case SERIAL_PROTOCOL_ACM: - TU_VERIFY(p_cdc->acm_capability.support_line_request); - return acm_set_control_line_state(p_cdc, line_state, complete_cb, user_data); - - #if CFG_TUH_CDC_FTDI - case SERIAL_PROTOCOL_FTDI: - return ftdi_sio_set_modem_ctrl(p_cdc, line_state, complete_cb, user_data); - #endif - - #if CFG_TUH_CDC_CP210X - case SERIAL_PROTOCOL_CP210X: - return ftdi_sio_set_modem_ctrl(p_cdc, line_state, complete_cb, user_data); - #endif - - default: - return false; - } + TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); + return serial_drivers[p_cdc->serial_drid].set_control_line_state(p_cdc, line_state, complete_cb, user_data); } -bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG_CDCH("CDC ACM Set Line Conding\r\n"); - - tusb_control_request_t const request = { - .bmRequestType_bit = { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_CLASS, - .direction = TUSB_DIR_OUT - }, - .bRequest = CDC_REQUEST_SET_LINE_CODING, - .wValue = 0, - .wIndex = tu_htole16(p_cdc->bInterfaceNumber), - .wLength = tu_htole16(sizeof(cdc_line_coding_t)) - }; - - // use usbh enum buf to hold line coding since user line_coding variable does not live long enough - uint8_t* enum_buf = usbh_get_enum_buf(); - memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t)); - - p_cdc->user_control_cb = complete_cb; - tuh_xfer_t xfer = { - .daddr = p_cdc->daddr, - .ep_addr = 0, - .setup = &request, - .buffer = enum_buf, - .complete_cb = cdch_internal_control_complete, - .user_data = user_data - }; - - TU_ASSERT(tuh_control_xfer(&xfer)); - return true; +bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); + return serial_drivers[p_cdc->serial_drid].set_baudrate(p_cdc, baudrate, complete_cb, user_data); } bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - - switch(p_cdc->serial_protocol) { - case SERIAL_PROTOCOL_ACM: - TU_VERIFY(p_cdc->acm_capability.support_line_request); - return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data); - - #if CFG_TUH_CDC_FTDI - case SERIAL_PROTOCOL_FTDI: - // FTDI need to set baud rate and data bits, parity, stop bits separately - return ftdi_sio_set_baudrate(p_cdc, line_coding->bit_rate, complete_cb, user_data); - #endif - - #if CFG_TUH_CDC_CP210X - case SERIAL_PROTOCOL_CP210X: - return cp210x_set_baudrate(p_cdc, line_coding->bit_rate, complete_cb, user_data); - #endif - - default: return false; - } -} - -bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc); - - switch(p_cdc->serial_protocol) { - case SERIAL_PROTOCOL_ACM: { - TU_VERIFY(p_cdc->acm_capability.support_line_request); - cdc_line_coding_t line_coding = p_cdc->line_coding; - line_coding.bit_rate = baudrate; - return acm_set_line_coding(p_cdc, &line_coding, complete_cb, user_data); - } - - #if CFG_TUH_CDC_FTDI - case SERIAL_PROTOCOL_FTDI: - // FTDI need to set baud rate and data bits, parity, stop bits separately - return ftdi_sio_set_baudrate(p_cdc, baudrate, complete_cb, user_data); - #endif - - #if CFG_TUH_CDC_CP210X - case SERIAL_PROTOCOL_CP210X: - return cp210x_set_baudrate(p_cdc, baudrate, complete_cb, user_data); - #endif - - default: return false; - } + // only ACM support this set line coding request + TU_VERIFY(p_cdc->serial_drid == SERIAL_DRIVER_ACM && p_cdc->acm_capability.support_line_request); + return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data); } //--------------------------------------------------------------------+ @@ -561,7 +523,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t #if CFG_TUH_CDC_FTDI // FTDI reserve 2 bytes for status - if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) { + if (p_cdc->serial_drid == SERIAL_DRIVER_FTDI) { uint8_t status[2]; tu_edpt_stream_read(&p_cdc->stream.rx, status, 2); (void) status; // TODO handle status @@ -587,15 +549,10 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t //--------------------------------------------------------------------+ // Enumeration //--------------------------------------------------------------------+ -enum -{ - // ACM - CONFIG_ACM_SET_CONTROL_LINE_STATE = 0, - CONFIG_ACM_SET_LINE_CODING, - CONFIG_ACM_COMPLETE, -}; -static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep) +static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); + +static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const *desc_ep) { for(size_t i=0; i<2; i++) { @@ -618,57 +575,6 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t c return true; } -static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) -{ - uint8_t const * p_desc_end = ((uint8_t const*) itf_desc) + max_len; - - cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); - TU_VERIFY(p_cdc); - - p_cdc->serial_protocol = SERIAL_PROTOCOL_ACM; - - //------------- Control Interface -------------// - uint8_t const * p_desc = tu_desc_next(itf_desc); - - // Communication Functional Descriptors - while( (p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc)) ) - { - if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) ) - { - // save ACM bmCapabilities - p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities; - } - - p_desc = tu_desc_next(p_desc); - } - - // Open notification endpoint of control interface if any - if (itf_desc->bNumEndpoints == 1) - { - TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)); - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc; - - TU_ASSERT( tuh_edpt_open(daddr, desc_ep) ); - p_cdc->ep_notif = desc_ep->bEndpointAddress; - - p_desc = tu_desc_next(p_desc); - } - - //------------- Data Interface (if any) -------------// - if ( (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && - (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) ) - { - // next to endpoint descriptor - p_desc = tu_desc_next(p_desc); - - // data endpoints expected to be in pairs - TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const *) p_desc)); - } - - return true; -} - - bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { (void) rhport; @@ -721,7 +627,88 @@ static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t i usbh_driver_set_config_complete(p_cdc->daddr, itf_num); } -static void process_acm_config(tuh_xfer_t* xfer) + +bool cdch_set_config(uint8_t daddr, uint8_t itf_num) +{ + tusb_control_request_t request; + request.wIndex = tu_htole16((uint16_t) itf_num); + + // fake transfer to kick-off process + tuh_xfer_t xfer; + xfer.daddr = daddr; + xfer.result = XFER_RESULT_SUCCESS; + xfer.setup = &request; + xfer.user_data = 0; // initial state + + uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num); + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); + + serial_drivers[p_cdc->serial_drid].process_set_config(&xfer); + return true; +} + +//--------------------------------------------------------------------+ +// ACM +//--------------------------------------------------------------------+ + +enum { + CONFIG_ACM_SET_CONTROL_LINE_STATE = 0, + CONFIG_ACM_SET_LINE_CODING, + CONFIG_ACM_COMPLETE, +}; + +static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) +{ + uint8_t const * p_desc_end = ((uint8_t const*) itf_desc) + max_len; + + cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); + TU_VERIFY(p_cdc); + + p_cdc->serial_drid = SERIAL_DRIVER_ACM; + + //------------- Control Interface -------------// + uint8_t const * p_desc = tu_desc_next(itf_desc); + + // Communication Functional Descriptors + while( (p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc)) ) + { + if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) ) + { + // save ACM bmCapabilities + p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities; + } + + p_desc = tu_desc_next(p_desc); + } + + // Open notification endpoint of control interface if any + if (itf_desc->bNumEndpoints == 1) + { + TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)); + tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc; + + TU_ASSERT( tuh_edpt_open(daddr, desc_ep) ); + p_cdc->ep_notif = desc_ep->bEndpointAddress; + + p_desc = tu_desc_next(p_desc); + } + + //------------- Data Interface (if any) -------------// + if ( (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && + (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) ) + { + // next to endpoint descriptor + p_desc = tu_desc_next(p_desc); + + // data endpoints expected to be in pairs + TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const *) p_desc)); + } + + return true; +} + +static void acm_process_config(tuh_xfer_t* xfer) { uintptr_t const state = xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); @@ -735,72 +722,103 @@ static void process_acm_config(tuh_xfer_t* xfer) #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM if (p_cdc->acm_capability.support_line_request) { - TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_acm_config, - CONFIG_ACM_SET_LINE_CODING), ); + TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config, + CONFIG_ACM_SET_LINE_CODING), ); break; } - #endif + #endif TU_ATTR_FALLTHROUGH; case CONFIG_ACM_SET_LINE_CODING: - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM if (p_cdc->acm_capability.support_line_request) { cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, process_acm_config, CONFIG_ACM_COMPLETE), ); + TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE), ); break; } - #endif + #endif TU_ATTR_FALLTHROUGH; case CONFIG_ACM_COMPLETE: // itf_num+1 to account for data interface as well set_config_complete(p_cdc, idx, itf_num+1); - break; + break; default: break; } } -bool cdch_set_config(uint8_t daddr, uint8_t itf_num) -{ - tusb_control_request_t request; - request.wIndex = tu_htole16((uint16_t) itf_num); +static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + TU_VERIFY(p_cdc->acm_capability.support_line_request); + TU_LOG_CDCH("CDC ACM Set Control Line State\r\n"); + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_CLASS, + .direction = TUSB_DIR_OUT + }, + .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE, + .wValue = tu_htole16(line_state), + .wIndex = tu_htole16((uint16_t) p_cdc->bInterfaceNumber), + .wLength = 0 + }; - tuh_xfer_t xfer; - xfer.daddr = daddr; - xfer.result = XFER_RESULT_SUCCESS; - xfer.setup = &request; - xfer.user_data = 0; + p_cdc->user_control_cb = complete_cb; - // fake transfer to kick-off process - uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT(p_cdc); + tuh_xfer_t xfer = { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request, + .buffer = NULL, + .complete_cb = cdch_internal_control_complete, + .user_data = user_data + }; - switch (p_cdc->serial_protocol) { - case SERIAL_PROTOCOL_ACM: - process_acm_config(&xfer); - break; + TU_ASSERT(tuh_control_xfer(&xfer)); + return true; +} - #if CFG_TUH_CDC_FTDI - case SERIAL_PROTOCOL_FTDI: - process_ftdi_config(&xfer); - break; - #endif +static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + TU_LOG_CDCH("CDC ACM Set Line Conding\r\n"); - #if CFG_TUH_CDC_CP210X - case SERIAL_PROTOCOL_CP210X: - process_cp210x_config(&xfer); - break; - #endif + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_CLASS, + .direction = TUSB_DIR_OUT + }, + .bRequest = CDC_REQUEST_SET_LINE_CODING, + .wValue = 0, + .wIndex = tu_htole16(p_cdc->bInterfaceNumber), + .wLength = tu_htole16(sizeof(cdc_line_coding_t)) + }; - default: return false; - } + // use usbh enum buf to hold line coding since user line_coding variable does not live long enough + uint8_t* enum_buf = usbh_get_enum_buf(); + memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t)); + + p_cdc->user_control_cb = complete_cb; + tuh_xfer_t xfer = { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request, + .buffer = enum_buf, + .complete_cb = cdch_internal_control_complete, + .user_data = user_data + }; + TU_ASSERT(tuh_control_xfer(&xfer)); return true; } +static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + TU_VERIFY(p_cdc->acm_capability.support_line_request); + cdc_line_coding_t line_coding = p_cdc->line_coding; + line_coding.bit_rate = baudrate; + return acm_set_line_coding(p_cdc, &line_coding, complete_cb, user_data); +} + //--------------------------------------------------------------------+ // FTDI //--------------------------------------------------------------------+ @@ -824,7 +842,7 @@ static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint TU_LOG_CDCH("FTDI opened\r\n"); - p_cdc->serial_protocol = SERIAL_PROTOCOL_FTDI; + p_cdc->serial_drid = SERIAL_DRIVER_FTDI; // endpoint pair tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); @@ -904,11 +922,13 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu TU_LOG_CDCH("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\n", baudrate, divisor); p_cdc->user_control_cb = complete_cb; + _ftdi_requested_baud = baudrate; TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, cdch_internal_control_complete, user_data)); + return true; } -static void process_ftdi_config(tuh_xfer_t* xfer) { +static void ftdi_process_config(tuh_xfer_t* xfer) { uintptr_t const state = xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); @@ -918,13 +938,13 @@ static void process_ftdi_config(tuh_xfer_t* xfer) { switch(state) { // Note may need to read FTDI eeprom case CONFIG_FTDI_RESET: - TU_ASSERT(ftdi_sio_reset(p_cdc, process_ftdi_config, CONFIG_FTDI_MODEM_CTRL),); + TU_ASSERT(ftdi_sio_reset(p_cdc, ftdi_process_config, CONFIG_FTDI_MODEM_CTRL),); break; case CONFIG_FTDI_MODEM_CTRL: #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM TU_ASSERT( - ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_ftdi_config, CONFIG_FTDI_SET_BAUDRATE),); + ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),); break; #else TU_ATTR_FALLTHROUGH; @@ -933,7 +953,7 @@ static void process_ftdi_config(tuh_xfer_t* xfer) { case CONFIG_FTDI_SET_BAUDRATE: { #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(ftdi_sio_set_baudrate(p_cdc, line_coding.bit_rate, process_ftdi_config, CONFIG_FTDI_SET_DATA),); + TU_ASSERT(ftdi_sio_set_baudrate(p_cdc, line_coding.bit_rate, ftdi_process_config, CONFIG_FTDI_SET_DATA),); break; #else TU_ATTR_FALLTHROUGH; @@ -986,7 +1006,7 @@ static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui TU_VERIFY(p_cdc); TU_LOG_CDCH("CP210x opened\r\n"); - p_cdc->serial_protocol = SERIAL_PROTOCOL_CP210X; + p_cdc->serial_drid = SERIAL_DRIVER_CP210X; // endpoint pair tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); @@ -1034,8 +1054,9 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_CDCH("CDC CP210x Set BaudRate = %lu\n", baudrate); - baudrate = tu_htole32(baudrate); - return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baudrate, 4, complete_cb, user_data); + uint32_t baud_le = tu_htole32(baudrate); + p_cdc->user_control_cb = complete_cb; + return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, cdch_internal_control_complete, user_data); } static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) @@ -1045,7 +1066,7 @@ static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, cdch_internal_control_complete, user_data); } -static void process_cp210x_config(tuh_xfer_t* xfer) { +static void cp210x_process_config(tuh_xfer_t* xfer) { uintptr_t const state = xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); @@ -1054,13 +1075,13 @@ static void process_cp210x_config(tuh_xfer_t* xfer) { switch (state) { case CONFIG_CP210X_IFC_ENABLE: - TU_ASSERT(cp210x_ifc_enable(p_cdc, 1, process_cp210x_config, CONFIG_CP210X_SET_BAUDRATE),); + TU_ASSERT(cp210x_ifc_enable(p_cdc, 1, cp210x_process_config, CONFIG_CP210X_SET_BAUDRATE),); break; case CONFIG_CP210X_SET_BAUDRATE: { #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(cp210x_set_baudrate(p_cdc, line_coding.bit_rate, process_cp210x_config, CONFIG_CP210X_SET_LINE_CTL),); + TU_ASSERT(cp210x_set_baudrate(p_cdc, line_coding.bit_rate, cp210x_process_config, CONFIG_CP210X_SET_LINE_CTL),); break; #else TU_ATTR_FALLTHROUGH; @@ -1078,7 +1099,8 @@ static void process_cp210x_config(tuh_xfer_t* xfer) { case CONFIG_CP210X_SET_DTR_RTS: #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cp210x_config, CONFIG_CP210X_COMPLETE),); + TU_ASSERT( + cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, cp210x_process_config, CONFIG_CP210X_COMPLETE),); break; #else TU_ATTR_FALLTHROUGH; diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 971ebe2ae..f6cc3812f 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -134,7 +134,11 @@ bool tuh_cdc_read_clear (uint8_t idx); //--------------------------------------------------------------------+ // Control Endpoint (Request) API -// Each Function will make a USB transfer request to/from device +// Each Function will make a USB control transfer request to/from device +// - If complete_cb is provided, the function will return immediately and invoke +// the callback when request is complete. +// - If complete_cb is NULL, the function will block until request is complete. +// In this case, user_data should be pointed to xfer_result_t to hold the transfer result. //--------------------------------------------------------------------+ // Request to Set Control Line State: DTR (bit 0), RTS (bit 1) diff --git a/src/host/usbh.c b/src/host/usbh.c index 3953d5b21..24ce47a7f 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -571,19 +571,19 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) ); - while (result == XFER_RESULT_INVALID) - { + while (result == XFER_RESULT_INVALID) { // Note: this can be called within an callback ie. part of tuh_task() // therefore event with RTOS tuh_task() still need to be invoked - if (tuh_task_event_ready()) - { + if (tuh_task_event_ready()) { tuh_task(); } - // TODO probably some timeout to prevent hanged } - // update transfer result + // update transfer result, user_data is expected to point to xfer_result_t + if (xfer->user_data != 0) { + *((xfer_result_t*) xfer->user_data) = result; + } xfer->result = result; xfer->actual_len = _ctrl_xfer.actual_len; } @@ -877,7 +877,7 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) //--------------------------------------------------------------------+ // generic helper to get a descriptor -// if blocking, user_data could be pointed to xfer_result +// if blocking, user_data is pointed to xfer_result static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t language_id, void* buffer, uint16_t len, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { @@ -905,15 +905,7 @@ static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t .user_data = user_data }; - bool const ret = tuh_control_xfer(&xfer); - - // if blocking, user_data could be pointed to xfer_result - if ( !complete_cb && user_data ) - { - *((xfer_result_t*) user_data) = xfer.result; - } - - return ret; + return tuh_control_xfer(&xfer); } bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len, @@ -971,7 +963,7 @@ bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* } // Get HID report descriptor -// if blocking, user_data could be pointed to xfer_result +// if blocking, user_data is pointed to xfer_result bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { @@ -1000,15 +992,7 @@ bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_ .user_data = user_data }; - bool const ret = tuh_control_xfer(&xfer); - - // if blocking, user_data could be pointed to xfer_result - if ( !complete_cb && user_data ) - { - *((xfer_result_t*) user_data) = xfer.result; - } - - return ret; + return tuh_control_xfer(&xfer); } bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, @@ -1040,15 +1024,7 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, .user_data = user_data }; - bool ret = tuh_control_xfer(&xfer); - - // if blocking, user_data could be pointed to xfer_result - if ( !complete_cb && user_data ) - { - *((xfer_result_t*) user_data) = xfer.result; - } - - return ret; + return tuh_control_xfer(&xfer); } bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt, @@ -1080,15 +1056,7 @@ bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt, .user_data = user_data }; - bool ret = tuh_control_xfer(&xfer); - - // if blocking, user_data could be pointed to xfer_result - if ( !complete_cb && user_data ) - { - *((xfer_result_t*) user_data) = xfer.result; - } - - return ret; + return tuh_control_xfer(&xfer); } //--------------------------------------------------------------------+ -- cgit v1.3.1 From fb5fe3360fb29a5d937cb6d6f1baa7695c04c361 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 28 Apr 2023 21:50:54 +0700 Subject: allow call tuh cdc with blocking (callback = NULL) - tuh_cdc_set_control_line_state() - tuh_cdc_set_baudrate() - tuh_cdc_set_line_coding() --- src/class/cdc/cdc_host.c | 83 +++++++++++++++++++++++++++++++++++++++++------- src/class/cdc/cdc_host.h | 1 + 2 files changed, 73 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index b25bc5512..858fdd9a7 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -437,22 +437,78 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - return serial_drivers[p_cdc->serial_drid].set_control_line_state(p_cdc, line_state, complete_cb, user_data); + cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; + + if ( complete_cb ) { + return driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data); + }else { + // blocking + xfer_result_t result; + bool ret = driver->set_control_line_state(p_cdc, line_state, complete_cb, (uintptr_t) &result); + + if (user_data) { + // user_data is not NULL, return result via user_data + *((xfer_result_t*) user_data) = result; + } + + if (result == XFER_RESULT_SUCCESS) { + p_cdc->line_state = (uint8_t) line_state; + } + + return ret; + } } bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - return serial_drivers[p_cdc->serial_drid].set_baudrate(p_cdc, baudrate, complete_cb, user_data); + cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; + + if ( complete_cb ) { + return driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data); + }else { + // blocking + xfer_result_t result; + bool ret = driver->set_baudrate(p_cdc, baudrate, complete_cb, (uintptr_t) &result); + + if (user_data) { + // user_data is not NULL, return result via user_data + *((xfer_result_t*) user_data) = result; + } + + if (result == XFER_RESULT_SUCCESS) { + p_cdc->line_coding.bit_rate = baudrate; + } + + return ret; + } } bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc); // only ACM support this set line coding request - TU_VERIFY(p_cdc->serial_drid == SERIAL_DRIVER_ACM && p_cdc->acm_capability.support_line_request); - return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data); + TU_VERIFY(p_cdc && p_cdc->serial_drid == SERIAL_DRIVER_ACM); + TU_VERIFY(p_cdc->acm_capability.support_line_request); + + if ( complete_cb ) { + return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data); + }else { + // blocking + xfer_result_t result; + bool ret = acm_set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result); + + if (user_data) { + // user_data is not NULL, return result via user_data + *((xfer_result_t*) user_data) = result; + } + + if (result == XFER_RESULT_SUCCESS) { + p_cdc->line_coding = *line_coding; + } + + return ret; + } } //--------------------------------------------------------------------+ @@ -752,6 +808,7 @@ static void acm_process_config(tuh_xfer_t* xfer) static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->acm_capability.support_line_request); TU_LOG_CDCH("CDC ACM Set Control Line State\r\n"); + tusb_control_request_t const request = { .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, @@ -771,7 +828,7 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_st .ep_addr = 0, .setup = &request, .buffer = NULL, - .complete_cb = cdch_internal_control_complete, + .complete_cb = complete_cb ? cdch_internal_control_complete : NULL, // complete_cb is NULL for sync call .user_data = user_data }; @@ -804,7 +861,7 @@ static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const .ep_addr = 0, .setup = &request, .buffer = enum_buf, - .complete_cb = cdch_internal_control_complete, + .complete_cb = complete_cb ? cdch_internal_control_complete : NULL, // complete_cb is NULL for sync call .user_data = user_data }; @@ -886,7 +943,8 @@ static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state { TU_LOG_CDCH("CDC FTDI Set Control Line State\r\n"); p_cdc->user_control_cb = complete_cb; - TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, cdch_internal_control_complete, user_data)); + TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, + complete_cb ? cdch_internal_control_complete : NULL, user_data)); return true; } @@ -923,7 +981,8 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu p_cdc->user_control_cb = complete_cb; _ftdi_requested_baud = baudrate; - TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, cdch_internal_control_complete, user_data)); + TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, + complete_cb ? cdch_internal_control_complete : NULL, user_data)); return true; } @@ -1056,14 +1115,16 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_ TU_LOG_CDCH("CDC CP210x Set BaudRate = %lu\n", baudrate); uint32_t baud_le = tu_htole32(baudrate); p_cdc->user_control_cb = complete_cb; - return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, cdch_internal_control_complete, user_data); + return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, + complete_cb ? cdch_internal_control_complete : NULL, user_data); } static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_CDCH("CDC CP210x Set Control Line State\r\n"); p_cdc->user_control_cb = complete_cb; - return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, cdch_internal_control_complete, user_data); + return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, + complete_cb ? cdch_internal_control_complete : NULL, user_data); } static void cp210x_process_config(tuh_xfer_t* xfer) { diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index f6cc3812f..8544ff740 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -148,6 +148,7 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); // Request to Set Line Coding (ACM only) +// Should only use if you don't work with serial devices such as FTDI/CP210x bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); // Request to Get Line Coding (ACM only) -- cgit v1.3.1 From 1763eede4839d0131cda077e2dd9631f315ce115 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 28 Apr 2023 22:14:14 +0700 Subject: more update to host serial API --- src/class/cdc/cdc_host.c | 27 ++++++++++++--------------- src/class/cdc/cdc_host.h | 3 ++- 2 files changed, 14 insertions(+), 16 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 858fdd9a7..fe3691bf4 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -443,7 +443,7 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c return driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data); }else { // blocking - xfer_result_t result; + xfer_result_t result = XFER_RESULT_INVALID; bool ret = driver->set_control_line_state(p_cdc, line_state, complete_cb, (uintptr_t) &result); if (user_data) { @@ -451,11 +451,10 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c *((xfer_result_t*) user_data) = result; } - if (result == XFER_RESULT_SUCCESS) { - p_cdc->line_state = (uint8_t) line_state; - } + TU_VERIFY(ret && result == XFER_RESULT_SUCCESS); - return ret; + p_cdc->line_state = (uint8_t) line_state; + return true; } } @@ -468,7 +467,7 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete return driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data); }else { // blocking - xfer_result_t result; + xfer_result_t result = XFER_RESULT_INVALID; bool ret = driver->set_baudrate(p_cdc, baudrate, complete_cb, (uintptr_t) &result); if (user_data) { @@ -476,11 +475,10 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete *((xfer_result_t*) user_data) = result; } - if (result == XFER_RESULT_SUCCESS) { - p_cdc->line_coding.bit_rate = baudrate; - } + TU_VERIFY(ret && result == XFER_RESULT_SUCCESS); - return ret; + p_cdc->line_coding.bit_rate = baudrate; + return true; } } @@ -495,7 +493,7 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data); }else { // blocking - xfer_result_t result; + xfer_result_t result = XFER_RESULT_INVALID; bool ret = acm_set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result); if (user_data) { @@ -503,11 +501,10 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, *((xfer_result_t*) user_data) = result; } - if (result == XFER_RESULT_SUCCESS) { - p_cdc->line_coding = *line_coding; - } + TU_VERIFY(ret && result == XFER_RESULT_SUCCESS); - return ret; + p_cdc->line_coding = *line_coding; + return true; } } diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 8544ff740..19552f1ee 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -138,7 +138,8 @@ bool tuh_cdc_read_clear (uint8_t idx); // - If complete_cb is provided, the function will return immediately and invoke // the callback when request is complete. // - If complete_cb is NULL, the function will block until request is complete. -// In this case, user_data should be pointed to xfer_result_t to hold the transfer result. +// - In this case, user_data should be pointed to xfer_result_t to hold the transfer result. +// - The function will return true if transfer is successful, false otherwise. //--------------------------------------------------------------------+ // Request to Set Control Line State: DTR (bit 0), RTS (bit 1) -- cgit v1.3.1 From be54870c3b2f7f1c14b0f5527f4928c8a4a4a7ae Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 3 May 2023 10:02:24 +0200 Subject: renesas_ra: add support for HS port --- hw/bsp/ra/family.mk | 2 + src/portable/renesas/rusb2/dcd_rusb2.c | 76 ++++++++++++++++++++++++++++------ src/portable/renesas/rusb2/hcd_rusb2.c | 46 ++++++++++++++------ src/portable/renesas/rusb2/rusb2_ra.c | 16 +++++++ src/portable/renesas/rusb2/rusb2_ra.h | 37 ++++++++++++++--- 5 files changed, 147 insertions(+), 30 deletions(-) create mode 100644 src/portable/renesas/rusb2/rusb2_ra.c (limited to 'src') diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index d48272e61..3ed17f79f 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -22,6 +22,7 @@ CFLAGS += \ SRC_C += \ src/portable/renesas/rusb2/dcd_rusb2.c \ src/portable/renesas/rusb2/hcd_rusb2.c \ + src/portable/renesas/rusb2/rusb2_ra.c \ hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c \ hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c \ hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_clocks.c \ @@ -47,6 +48,7 @@ INC += \ $(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc \ $(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/api \ $(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/instances \ + $(TOP)/hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all \ $(TOP)/$(FSP_MCU_DIR) \ $(TOP)/$(FSP_BOARD_DIR) diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 78584125f..9ae36e253 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -52,8 +52,10 @@ /* LINK core registers */ #if defined(__CCRX__) #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE) +#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) + #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE) #else - #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE) + #define RUSB2 ((R_USB_FS0_Type*)R_USB_FS0_BASE) #endif /* Start of definition of packed structs (used by the CCRX toolchain) */ @@ -81,6 +83,18 @@ typedef union TU_ATTR_PACKED { volatile uint16_t u16; } hw_fifo_t; +typedef union TU_ATTR_PACKED { + struct { + volatile uint32_t : 24; + volatile uint32_t u8: 8; + }; + struct { + volatile uint32_t : 16; + volatile uint32_t u16: 16; + }; + volatile uint32_t u32; +} hw_fifo32_t; + typedef struct TU_ATTR_PACKED { void *buf; /* the start address of a transfer data buffer */ @@ -185,14 +199,18 @@ static inline void pipe_wait_for_ready(unsigned num) static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { +#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) + volatile hw_fifo32_t *reg = (volatile hw_fifo32_t*) fifo; +#else volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo; +#endif uintptr_t addr = (uintptr_t)buf; while (len >= 2) { reg->u16 = *(const uint16_t *)addr; addr += 2; len -= 2; } - if (len) { + if (len > 0) { reg->u8 = *(const uint8_t *)addr; ++addr; } @@ -519,12 +537,17 @@ static void process_bus_reset(uint8_t rhport) ++ctr; } tu_varclr(&_dcd); + +#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) + dcd_event_bus_reset(rhport, TUSB_SPEED_HIGH, true); +#else dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); +#endif } static void process_set_address(uint8_t rhport) { - const uint32_t addr = RUSB2->USBADDR_b.USBADDR; + const uint32_t addr = RUSB2->USBADDR & 0xFF; if (!addr) return; const tusb_control_request_t setup_packet = { #if defined(__CCRX__) @@ -572,34 +595,53 @@ void dcd_init(uint8_t rhport) { (void)rhport; -#if 0 // previously present in the rx driver before generalization - uint32_t pswi = disable_interrupt(); - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; - MSTP(USB0) = 0; - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; - enable_interrupt(pswi); -#endif - +#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) + RUSB2->SYSCFG_b.HSE = 1; + RUSB2->PHYSET_b.DIRPD = 0; + R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS); + RUSB2->PHYSET_b.PLLRESET = 0; + //RUSB2->PHYSET_b.REPSTART = 1; + RUSB2->SYSCFG_b.DRPD = 0; + RUSB2->SYSCFG_b.USBE = 1; + RUSB2->LPSTS_b.SUSPENDM = 1; + while (!RUSB2->PLLSTA_b.PLLLOCK); + //RUSB2->BUSWAIT |= 0x0F00U; + //RUSB2->PHYSET_b.REPSEL = 1; + RUSB2->CFIFOSEL_b.MBW = 1; + RUSB2->D0FIFOSEL_b.MBW = 1; + RUSB2->D1FIFOSEL_b.MBW = 1; + RUSB2->INTSTS0 = 0; +#else RUSB2->SYSCFG_b.SCKE = 1; while (!RUSB2->SYSCFG_b.SCKE) ; RUSB2->SYSCFG_b.DRPD = 0; RUSB2->SYSCFG_b.DCFM = 0; RUSB2->SYSCFG_b.USBE = 1; +#endif // MCU specific PHY init rusb2_phy_init(); +#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE) RUSB2->PHYSLEW = 0x5; RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */ + #define USB_VDCEN (0x0080U) /* b7: Regulator ON/OFF control */ + RUSB2->USBMC = (uint16_t) (RUSB2->USBMC | (USB_VDCEN)); +#endif + /* Setup default control pipe */ RUSB2->DCPMAXP_b.MXPS = 64; RUSB2->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk | RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) | - RUSB2_INTSTS0_RESM_Msk; + RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk; RUSB2->BEMPENB = 1; RUSB2->BRDYENB = 1; +#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE) + RUSB2->SYSCFG_b.DPRPU = 1; /* necessary in this position */ +#endif + if (RUSB2->INTSTS0_b.VBSTS) { dcd_connect(rhport); } @@ -630,6 +672,10 @@ void dcd_remote_wakeup(uint8_t rhport) void dcd_connect(uint8_t rhport) { (void)rhport; + #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) + RUSB2->SYSCFG_b.CNEN = 1; + R_BSP_SoftwareDelay((uint32_t) 10, BSP_DELAY_UNITS_MILLISECONDS); + #endif RUSB2->SYSCFG_b.DPRPU = 1; } @@ -672,6 +718,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) /* setup pipe */ dcd_int_disable(rhport); + #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) + RUSB2->PIPEBUF = 0x7C08; + #endif RUSB2->PIPESEL = num; RUSB2->PIPEMAXP = mps; volatile uint16_t *ctr = get_pipectr(num); @@ -826,6 +875,9 @@ void dcd_int_handler(uint8_t rhport) break; } } + if (is0 & RUSB2_INTSTS0_NRDY_Msk) { + RUSB2->NRDYSTS = 0; + } if (is0 & RUSB2_INTSTS0_CTRT_Msk) { if (is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA) { /* A setup packet has been received. */ diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index e4743223e..03811d63f 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -48,8 +48,10 @@ /* LINK core registers */ #if defined(__CCRX__) #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE) +#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) + #define RUSB2 ((R_USB_HS0_Type*) R_USB_HS0_BASE) #else - #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE) + #define RUSB2 ((R_USB_FS0_Type*) R_USB_FS0_BASE) #endif TU_ATTR_PACKED_BEGIN @@ -477,31 +479,49 @@ bool hcd_init(uint8_t rhport) { (void)rhport; -#if 0 // previously present in the rx driver before generalization - uint32_t pswi = disable_interrupt(); - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1; - MSTP(USB0) = 0; - SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY; - enable_interrupt(pswi); -#endif - - RUSB2->SYSCFG_b.SCKE = 1; - while (!RUSB2->SYSCFG_b.SCKE) ; - RUSB2->SYSCFG_b.DPRPU = 0; - RUSB2->SYSCFG_b.DRPD = 0; +#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) + RUSB2->SYSCFG_b.HSE = 1; + RUSB2->PHYSET_b.HSEB = 0; + RUSB2->PHYSET_b.DIRPD = 0; + R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS); + RUSB2->PHYSET_b.PLLRESET = 0; + RUSB2->LPSTS_b.SUSPENDM = 1; + while (!RUSB2->PLLSTA_b.PLLLOCK); + RUSB2->SYSCFG_b.DRPD = 1; RUSB2->SYSCFG_b.DCFM = 1; + RUSB2->SYSCFG_b.DPRPU = 0; + RUSB2->SYSCFG_b.CNEN = 1; + RUSB2->BUSWAIT |= 0x0F00U; + RUSB2->SOFCFG_b.INTL = 1; + RUSB2->DVSTCTR0_b.VBUSEN = 1; + RUSB2->CFIFOSEL_b.MBW = 1; + RUSB2->D0FIFOSEL_b.MBW = 1; + RUSB2->D1FIFOSEL_b.MBW = 1; + RUSB2->INTSTS0 = 0; + for (volatile int i = 0; i < 30000; ++i) ; + RUSB2->SYSCFG_b.USBE = 1; +#else + /* HOST DEVICE Full SPEED */ + RUSB2->SYSCFG_b.SCKE = 1; /* USB Clock enable */ + while (!RUSB2->SYSCFG_b.SCKE) ; + RUSB2->SYSCFG_b.DPRPU = 0; /* D+ pull up enable - 0/disable in host mode */ + RUSB2->SYSCFG_b.DRPD = 1; /* D+/D- pull down - 1/in Host mode (pag.834)*/ + RUSB2->SYSCFG_b.DCFM = 1; /* HOST or Device - 1/HOST */ RUSB2->DVSTCTR0_b.VBUSEN = 1; RUSB2->SYSCFG_b.DRPD = 1; for (volatile int i = 0; i < 30000; ++i) ; RUSB2->SYSCFG_b.USBE = 1; +#endif // MCU specific PHY init rusb2_phy_init(); +#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST) RUSB2->PHYSLEW = 0x5; RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */ +#endif /* Setup default control pipe */ RUSB2->DCPCFG = RUSB2_PIPECFG_SHTNAK_Msk; diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c new file mode 100644 index 000000000..2b6ce7b2f --- /dev/null +++ b/src/portable/renesas/rusb2/rusb2_ra.c @@ -0,0 +1,16 @@ +#include "tusb_option.h" +#include "rusb2_ra.h" + +#ifdef CFG_TUSB_RHPORT0_MODE +IRQn_Type _usb_fs_irqn = USBFS_INT_IRQn; +void tud_set_irq_usbfs(IRQn_Type q) { + _usb_fs_irqn = q; +} +#endif + +#ifdef CFG_TUSB_RHPORT1_MODE +IRQn_Type _usb_hs_irqn = USBHS_USB_INT_RESUME_IRQn; +void tud_set_irq_usbhs(IRQn_Type q) { + _usb_hs_irqn = q; +} +#endif \ No newline at end of file diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 5785850cc..b18b506e5 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -34,18 +34,45 @@ extern "C" { /* renesas fsp api */ #include "bsp_api.h" -#define RUSB2_REG_BASE (0x40090000) +extern IRQn_Type _usb_fs_irqn; +extern IRQn_Type _usb_hs_irqn; TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) { - (void) rhport; - NVIC_EnableIRQ(TU_IRQn); +#ifdef CFG_TUSB_RHPORT1_MODE +#if (CFG_TUSB_RHPORT1_MODE != 0) + if (rhport == 1) { + NVIC_EnableIRQ(_usb_hs_irqn); + } +#endif +#endif + +#ifdef CFG_TUSB_RHPORT0_MODE +#if (CFG_TUSB_RHPORT0_MODE != 0) + if (rhport == 0) { + NVIC_EnableIRQ(_usb_fs_irqn); + } +#endif +#endif } TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) { - (void) rhport; - NVIC_DisableIRQ(TU_IRQn); +#ifdef CFG_TUSB_RHPORT1_MODE +#if (CFG_TUSB_RHPORT1_MODE != 0) + if (rhport == 1) { + NVIC_DisableIRQ(_usb_hs_irqn); + } +#endif +#endif + +#ifdef CFG_TUSB_RHPORT0_MODE +#if (CFG_TUSB_RHPORT0_MODE != 0) + if (rhport == 0) { + NVIC_DisableIRQ(_usb_fs_irqn); + } +#endif +#endif } // MCU specific PHY init -- cgit v1.3.1 From 4afed62646d18dd96eef619d7d21b47a2422672f Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 3 May 2023 10:05:29 +0200 Subject: renesas_ra: host: handle retry on attach() --- src/portable/renesas/rusb2/hcd_rusb2.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 03811d63f..9dd4f0a48 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -759,9 +759,10 @@ void hcd_int_handler(uint8_t rhport) 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5, 20, 8, 19, 18}; #endif - + static unsigned char attach_attempt = 0; unsigned is1 = RUSB2->INTSTS1; unsigned is0 = RUSB2->INTSTS0; + /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1); RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0); @@ -772,12 +773,21 @@ void hcd_int_handler(uint8_t rhport) if (is1 & RUSB2_INTSTS1_SACK_Msk) { /* Set DATA1 in advance for the next transfer. */ RUSB2->DCPCTR_b.SQSET = 1; + attach_attempt = 0; hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); } if (is1 & RUSB2_INTSTS1_SIGN_Msk) { hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); + if(attach_attempt > 0) { + RUSB2->DVSTCTR0_b.UACT = 1; + _hcd.need_reset = true; + RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; + hcd_event_device_attach(rhport, true); + } + attach_attempt--; } if (is1 & RUSB2_INTSTS1_ATTCH_Msk) { + attach_attempt = 10; RUSB2->DVSTCTR0_b.UACT = 1; _hcd.need_reset = true; RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; -- cgit v1.3.1 From 5f7e7b4b0a9f65a401c679d5045b96b4b56755df Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 3 May 2023 10:06:13 +0200 Subject: renesas_ra: support RA2A1 (FS only) --- src/portable/renesas/rusb2/dcd_rusb2.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 9ae36e253..f3bda5205 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -41,6 +41,15 @@ #include "rusb2_rx.h" #elif TU_CHECK_MCU(OPT_MCU_RAXXX) #include "rusb2_ra.h" + #if defined(RENESAS_CORTEX_M23) + #define D0FIFO CFIFO + #define D0FIFOSEL CFIFOSEL + #define D0FIFOSEL_b CFIFOSEL_b + #define D1FIFOSEL CFIFOSEL + #define D1FIFOSEL_b CFIFOSEL_b + #define D0FIFOCTR CFIFOCTR + #define D0FIFOCTR_b CFIFOCTR_b + #endif #else #error "Unsupported MCU" #endif @@ -121,6 +130,10 @@ typedef struct //--------------------------------------------------------------------+ static dcd_data_t _dcd; +#ifndef FIRST_BULK_PIPE +#define FIRST_BULK_PIPE 3 +#endif + static unsigned find_pipe(unsigned xfer) { switch (xfer) { @@ -130,7 +143,7 @@ static unsigned find_pipe(unsigned xfer) } break; case TUSB_XFER_BULK: - for (int i = 3; i <= 5; ++i) { + for (int i = FIRST_BULK_PIPE; i <= 5; ++i) { if (0 == _dcd.pipe[i].ep) return i; } for (int i = 1; i <= 1; ++i) { -- cgit v1.3.1 From 6ff62c0fe85e825d077d7d803c657181769e542f Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 3 May 2023 11:47:41 +0200 Subject: renesas: add fallback for targets not defining CFG_TUSB_RHPORT*_MODE --- src/portable/renesas/rusb2/dcd_rusb2.c | 5 +++++ src/portable/renesas/rusb2/hcd_rusb2.c | 5 +++++ src/portable/renesas/rusb2/rusb2_ra.h | 5 +++++ 3 files changed, 15 insertions(+) (limited to 'src') diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index f3bda5205..f509dcc56 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -37,6 +37,11 @@ #include "device/dcd.h" #include "rusb2_type.h" +#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) +// fallback +#define CFG_TUSB_RHPORT0_MODE OPT_MODE_DEVICE +#endif + #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #include "rusb2_rx.h" #elif TU_CHECK_MCU(OPT_MCU_RAXXX) diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 9dd4f0a48..1ec25f1e2 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -33,6 +33,11 @@ #include "host/hcd.h" #include "rusb2_type.h" +#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) +// fallback +#define CFG_TUSB_RHPORT0_MODE OPT_MODE_HOST +#endif + #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #include "rusb2_rx.h" #elif TU_CHECK_MCU(OPT_MCU_RAXXX) diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index b18b506e5..874492304 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -37,6 +37,11 @@ extern "C" { extern IRQn_Type _usb_fs_irqn; extern IRQn_Type _usb_hs_irqn; +#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) +// fallback +#define CFG_TUSB_RHPORT0_MODE ( CFG_TUD_ENABLED ? OPT_MODE_DEVICE : OPT_MODE_HOST ) +#endif + TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) { #ifdef CFG_TUSB_RHPORT1_MODE -- cgit v1.3.1 From 8a9d2b4b759990f9609a33c313b154cc7314bec7 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 4 May 2023 23:29:37 +0700 Subject: wip --- examples/device/cdc_msc/CMakeLists.txt | 7 +++++++ hw/bsp/imxrt/family.cmake | 17 +++++++++++++++-- src/CMakeLists.txt | 31 +++++++++++++++++++++++++++++++ 3 files changed, 53 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt index 7eddc2422..1115f51d1 100644 --- a/examples/device/cdc_msc/CMakeLists.txt +++ b/examples/device/cdc_msc/CMakeLists.txt @@ -29,6 +29,13 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) +# define tinyusb_config target +add_library(tinyusb_config INTERFACE) + +target_include_directories(tinyusb_config INTERFACE + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) + # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. family_configure_device_example(${PROJECT}) diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 95c4c0415..c18fb01ab 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -73,9 +73,22 @@ function(family_configure_target TARGET) ${SDK_DIR}/drivers/lpuart ) + # define tinyusb_config target + + #target_include_directories(tinyusb_config INTERFACE + # ) + + target_compile_definitions(tinyusb_config PUBLIC + ) + # include tinyusb cmake - include(${TOP}/src/CMakeLists.txt) - add_tinyusb(${TARGET}) + add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) + target_link_libraries(${TARGET} PUBLIC + tinyusb + ) + + #include(${TOP}/src/CMakeLists.txt) + #add_tinyusb(${TARGET}) endfunction() diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index a270ea8b7..ec7fe32c4 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -3,6 +3,37 @@ cmake_minimum_required(VERSION 3.17) +if (NOT TARGET tinyusb_config) + message(FATAL_ERROR "tinyusb_config target is not defined") +endif() + +add_library(tinyusb STATIC + ${CMAKE_CURRENT_LIST_DIR}/tusb.c + ${CMAKE_CURRENT_LIST_DIR}/common/tusb_fifo.c + ${CMAKE_CURRENT_LIST_DIR}/device/usbd.c + ${CMAKE_CURRENT_LIST_DIR}/device/usbd_control.c + ${CMAKE_CURRENT_LIST_DIR}/class/audio/audio_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/cdc/cdc_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_rt_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/hid/hid_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/midi/midi_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/msc/msc_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/net/ecm_rndis_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/net/ncm_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/usbtmc/usbtmc_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/vendor/vendor_device.c + ${CMAKE_CURRENT_LIST_DIR}/class/video/video_device.c + ) + +target_include_directories(tinyusb PUBLIC + ${CMAKE_CURRENT_LIST_DIR} + ) + +target_link_libraries(tinyusb PUBLIC + tinyusb_config + ) + function(add_tinyusb TARGET) target_sources(${TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c -- cgit v1.3.1 From cda5ab8b259522be962840a49a448648d3f5d308 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 5 May 2023 19:15:19 +0700 Subject: more temp work --- hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake | 4 +- hw/bsp/imxrt/family.cmake | 48 +++++++++++++-------- src/CMakeLists.txt | 58 +++++++++++++------------- 3 files changed, 60 insertions(+), 50 deletions(-) (limited to 'src') diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake index 52d1846ea..c43de5ba4 100644 --- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake @@ -1,10 +1,10 @@ set(MCU_VARIANT MIMXRT1011) -target_sources(${PROJECT} PUBLIC +target_sources(bsp PUBLIC ${CMAKE_CURRENT_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c ) -target_compile_definitions(${PROJECT} PUBLIC +target_compile_definitions(bsp PUBLIC CPU_MIMXRT1011DAE5A CFG_EXAMPLE_VIDEO_READONLY ) diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index c18fb01ab..53df88c47 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -2,6 +2,7 @@ set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../examples/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + function(family_configure_target TARGET) if (NOT BOARD) message(FATAL_ERROR "BOARD not specified") @@ -17,9 +18,14 @@ function(family_configure_target TARGET) set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk) set(DEPS_SUBMODULES ${SDK_DIR}) + # define BSP target + add_library(bsp STATIC + ) + + # include board specific cmake include(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board.cmake) - target_compile_definitions(${TARGET} PUBLIC + target_compile_definitions(bsp PUBLIC CFG_TUSB_MCU=OPT_MCU_MIMXRT __ARMVFP__=0 __ARMFPV5__=0 @@ -32,11 +38,11 @@ function(family_configure_target TARGET) --specs=nano.specs ) - target_sources(${TARGET} PUBLIC + target_sources(bsp PUBLIC # TinyUSB - ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c - ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c - ${TOP}/src/portable/ehci/ehci.c +# ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c +# ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c +# ${TOP}/src/portable/ehci/ehci.c # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${SDK_DIR}/drivers/common/fsl_common.c @@ -49,18 +55,18 @@ function(family_configure_target TARGET) ) if (TOOLCHAIN STREQUAL "gcc") - target_sources(${TARGET} PUBLIC + target_sources(bsp PUBLIC ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S ) - target_link_options(${TARGET} PUBLIC + target_link_options(bsp PUBLIC "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld" ) else () # TODO support IAR endif () - target_include_directories(${TARGET} PUBLIC + target_include_directories(bsp PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} @@ -73,25 +79,31 @@ function(family_configure_target TARGET) ${SDK_DIR}/drivers/lpuart ) - # define tinyusb_config target - - #target_include_directories(tinyusb_config INTERFACE - # ) + if(NOT TARGET tinyusb_config) + message(FATAL_ERROR "tinyusb_config target not found") + endif() - target_compile_definitions(tinyusb_config PUBLIC + target_compile_definitions(tinyusb_config INTERFACE + CFG_TUSB_MCU=OPT_MCU_MIMXRT ) - # include tinyusb cmake + # include tinyusb CMakeList.txt for tinyusb target add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) - target_link_libraries(${TARGET} PUBLIC - tinyusb + + add_library(tinyusb_port STATIC + ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c + ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c + ${TOP}/src/portable/ehci/ehci.c ) - #include(${TOP}/src/CMakeLists.txt) - #add_tinyusb(${TARGET}) + target_link_libraries(${TARGET} PUBLIC + tinyusb + bsp + ) endfunction() + function(family_add_freertos_config TARGET) add_library(freertos_config INTERFACE) diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index ec7fe32c4..e7e3125a2 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -34,33 +34,31 @@ target_link_libraries(tinyusb PUBLIC tinyusb_config ) -function(add_tinyusb TARGET) - target_sources(${TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/common/tusb_fifo.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd_control.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/audio/audio_device.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/cdc/cdc_device.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_device.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_rt_device.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_device.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/midi/midi_device.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_device.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ecm_rndis_device.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ncm_device.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/usbtmc/usbtmc_device.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_device.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/video/video_device.c - ) - - target_include_directories(${TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ) - - # enable all possible warnings - target_compile_options(${TARGET} PUBLIC - - ) - -endfunction() +#function(add_tinyusb TARGET) +# target_sources(${TARGET} PUBLIC +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/common/tusb_fifo.c +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd.c +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd_control.c +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/audio/audio_device.c +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/cdc/cdc_device.c +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_device.c +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_rt_device.c +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_device.c +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/midi/midi_device.c +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_device.c +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ecm_rndis_device.c +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ncm_device.c +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/usbtmc/usbtmc_device.c +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_device.c +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/video/video_device.c +# ) +# +# target_include_directories(${TARGET} PUBLIC +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR} +# ) +# +# # enable all possible warnings +# target_compile_options(${TARGET} PUBLIC +# ) +#endfunction() -- cgit v1.3.1 From f15f79df5d242fdeff06dff14a9550905f29d514 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 6 May 2023 15:14:54 +0700 Subject: cmake work well with imxrt --- examples/CMakeLists.txt | 6 +- examples/device/CMakeLists.txt | 2 +- examples/device/audio_test/CMakeLists.txt | 4 +- .../device/audio_test_multi_rate/CMakeLists.txt | 4 +- examples/device/board_test/CMakeLists.txt | 8 +- examples/device/cdc_dual_ports/CMakeLists.txt | 10 +- examples/device/cdc_msc/CMakeLists.txt | 15 +-- examples/device/cdc_msc_freertos/CMakeLists.txt | 2 +- .../device/hid_composite_freertos/CMakeLists.txt | 2 +- examples/host/cdc_msc_hid/CMakeLists.txt | 2 +- hw/bsp/family_support.cmake | 4 +- hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake | 17 +-- hw/bsp/imxrt/family.cmake | 145 +++++++++++---------- src/CMakeLists.txt | 104 +++++++-------- 14 files changed, 163 insertions(+), 162 deletions(-) (limited to 'src') diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt index d91d8ca62..a23b4ed62 100644 --- a/examples/CMakeLists.txt +++ b/examples/CMakeLists.txt @@ -3,8 +3,8 @@ cmake_minimum_required(VERSION 3.5) #set(CMAKE_EXPORT_COMPILE_COMMANDS ON) include(${CMAKE_CURRENT_SOURCE_DIR}/../hw/bsp/family_support.cmake) -project(tinyusb_examples) +project(tinyusb_examples C CXX ASM) add_subdirectory(device) -add_subdirectory(dual) -add_subdirectory(host) +#add_subdirectory(dual) +#add_subdirectory(host) diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt index 5520209e0..ac1bbf161 100644 --- a/examples/device/CMakeLists.txt +++ b/examples/device/CMakeLists.txt @@ -2,7 +2,7 @@ cmake_minimum_required(VERSION 3.5) include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake) -project(tinyusb_device_examples) +project(tinyusb_device_examples C CXX ASM) family_initialize_project(tinyusb_device_examples ${CMAKE_CURRENT_LIST_DIR}) # family_add_subdirectory will filter what to actually add based on selected FAMILY diff --git a/examples/device/audio_test/CMakeLists.txt b/examples/device/audio_test/CMakeLists.txt index b0889285c..87b7d07d4 100644 --- a/examples/device/audio_test/CMakeLists.txt +++ b/examples/device/audio_test/CMakeLists.txt @@ -21,12 +21,12 @@ add_executable(${PROJECT}) target_sources(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c -) + ) # Example include target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src -) + ) # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. diff --git a/examples/device/audio_test_multi_rate/CMakeLists.txt b/examples/device/audio_test_multi_rate/CMakeLists.txt index b0889285c..87b7d07d4 100644 --- a/examples/device/audio_test_multi_rate/CMakeLists.txt +++ b/examples/device/audio_test_multi_rate/CMakeLists.txt @@ -21,12 +21,12 @@ add_executable(${PROJECT}) target_sources(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c -) + ) # Example include target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src -) + ) # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt index c48efdaa5..4ab8d5a65 100644 --- a/examples/device/board_test/CMakeLists.txt +++ b/examples/device/board_test/CMakeLists.txt @@ -19,13 +19,13 @@ add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ) # Example include target_include_directories(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. diff --git a/examples/device/cdc_dual_ports/CMakeLists.txt b/examples/device/cdc_dual_ports/CMakeLists.txt index d142e9c04..87b7d07d4 100644 --- a/examples/device/cdc_dual_ports/CMakeLists.txt +++ b/examples/device/cdc_dual_ports/CMakeLists.txt @@ -19,14 +19,14 @@ add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c + ) # Example include target_include_directories(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt index 1115f51d1..63030e733 100644 --- a/examples/device/cdc_msc/CMakeLists.txt +++ b/examples/device/cdc_msc/CMakeLists.txt @@ -19,20 +19,13 @@ add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c + ) # Example include target_include_directories(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) - -# define tinyusb_config target -add_library(tinyusb_config INTERFACE) - -target_include_directories(tinyusb_config INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/src ) diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt index 699860223..75ec33145 100644 --- a/examples/device/cdc_msc_freertos/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/CMakeLists.txt @@ -35,7 +35,7 @@ target_include_directories(${PROJECT} PUBLIC family_configure_device_example(${PROJECT}) if (NOT TARGET freertos_kernel) -family_add_freertos_config(${PROJECT}) +family_configure_freertos_example(${PROJECT}) add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/../../../lib/FreeRTOS-Kernel lib/FreeRTOS-Kernel) endif() diff --git a/examples/device/hid_composite_freertos/CMakeLists.txt b/examples/device/hid_composite_freertos/CMakeLists.txt index 9b0ffa4b6..30729f438 100644 --- a/examples/device/hid_composite_freertos/CMakeLists.txt +++ b/examples/device/hid_composite_freertos/CMakeLists.txt @@ -34,7 +34,7 @@ target_include_directories(${PROJECT} PUBLIC family_configure_device_example(${PROJECT}) if (NOT TARGET freertos_kernel) -family_add_freertos_config(${PROJECT}) +family_configure_freertos_example(${PROJECT}) add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/../../../lib/FreeRTOS-Kernel lib/FreeRTOS-Kernel) endif() diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt index b66ff2382..42dac5be7 100644 --- a/examples/host/cdc_msc_hid/CMakeLists.txt +++ b/examples/host/cdc_msc_hid/CMakeLists.txt @@ -5,7 +5,7 @@ include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) # gets PROJECT name for the example (e.g. -) family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) -project(${PROJECT}) +project(${PROJECT} C CXX ASM) # Checks this example is valid for the family and initializes the project family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index cc95dde9e..26baa6365 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -1,4 +1,6 @@ if (NOT TARGET _family_support_marker) + add_library(_family_support_marker INTERFACE) + include(CMakePrintHelpers) # Default to gcc @@ -6,8 +8,6 @@ if (NOT TARGET _family_support_marker) set(TOOLCHAIN gcc) endif() - add_library(_family_support_marker INTERFACE) - if (NOT FAMILY) message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, eps32s2, esp32s3). You can do this via -DFAMILY=xxx on the cmake command line") endif() diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake index c43de5ba4..d4015e488 100644 --- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake @@ -1,10 +1,11 @@ set(MCU_VARIANT MIMXRT1011) -target_sources(bsp PUBLIC - ${CMAKE_CURRENT_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c - ) - -target_compile_definitions(bsp PUBLIC - CPU_MIMXRT1011DAE5A - CFG_EXAMPLE_VIDEO_READONLY - ) +function(update_board TARGET) + target_sources(${TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c + ) + target_compile_definitions(${TARGET} PUBLIC + CPU_MIMXRT1011DAE5A + CFG_EXAMPLE_VIDEO_READONLY + ) +endfunction() diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 53df88c47..1731d9e60 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -1,50 +1,34 @@ +if (TARGET _imxrt_family_inclusion_marker) + return() +endif () + +add_library(_imxrt_family_inclusion_marker INTERFACE) + +if (NOT BOARD) + message(FATAL_ERROR "BOARD not specified") +endif () + # toolchain set up set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../examples/cmake/toolchain/arm_${TOOLCHAIN}.cmake) +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) -function(family_configure_target TARGET) - if (NOT BOARD) - message(FATAL_ERROR "BOARD not specified") - endif () - # set output name to .elf - set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf) - - # TOP is absolute path to root directory of TinyUSB git repo - set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..") - get_filename_component(TOP "${TOP}" REALPATH) +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +set(BOARD_TARGET board_${BOARD}) +if (NOT TARGET ${BOARD_TARGET}) + # TOP is path to root directory + set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..") set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk) - set(DEPS_SUBMODULES ${SDK_DIR}) + set(CMSIS_DIR ${TOP}/lib/CMSIS_5) - # define BSP target - add_library(bsp STATIC - ) - - # include board specific cmake - include(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board.cmake) - - target_compile_definitions(bsp PUBLIC - CFG_TUSB_MCU=OPT_MCU_MIMXRT - __ARMVFP__=0 - __ARMFPV5__=0 - XIP_EXTERNAL_FLASH=1 - XIP_BOOT_HEADER_ENABLE=1 - ) - - target_link_options(${TARGET} PUBLIC - --specs=nosys.specs - --specs=nano.specs - ) - - target_sources(bsp PUBLIC - # TinyUSB -# ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c -# ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c -# ${TOP}/src/portable/ehci/ehci.c - # BSP - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + add_library(${BOARD_TARGET} STATIC ${SDK_DIR}/drivers/common/fsl_common.c ${SDK_DIR}/drivers/igpio/fsl_gpio.c ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c @@ -53,58 +37,87 @@ function(family_configure_target TARGET) ${SDK_DIR}/devices/${MCU_VARIANT}/project_template/clock_config.c ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + CFG_TUSB_MCU=OPT_MCU_MIMXRT + __ARMVFP__=0 + __ARMFPV5__=0 + XIP_EXTERNAL_FLASH=1 + XIP_BOOT_HEADER_ENABLE=1 + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMSIS_DIR}/CMSIS/Core/Include + ${SDK_DIR}/devices/${MCU_VARIANT} + ${SDK_DIR}/devices/${MCU_VARIANT}/project_template + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers + ${SDK_DIR}/drivers/common + ${SDK_DIR}/drivers/igpio + ${SDK_DIR}/drivers/lpuart + ) + update_board(${BOARD_TARGET}) if (TOOLCHAIN STREQUAL "gcc") - target_sources(bsp PUBLIC + target_sources(${BOARD_TARGET} PUBLIC ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S ) - - target_link_options(bsp PUBLIC + target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld" + --specs=nosys.specs + --specs=nano.specs ) else () # TODO support IAR endif () +endif () # BOARD_TARGET + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_target TARGET) + # set output name to .elf + set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf) + + # TOP is path to root directory + set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..") - target_include_directories(bsp PUBLIC + #---------- BSP_TARGET ---------- + # BSP_TARGET is built for each example since it depends on example's tusb_config.h + set(BSP_TARGET "${TARGET}_bsp_${BOARD}") + add_library(${BSP_TARGET} STATIC + # TinyUSB + ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c + ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c + ${TOP}/src/portable/ehci/ehci.c + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ) + target_include_directories(${BSP_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} - ${SDK_DIR}/CMSIS/Include - ${SDK_DIR}/devices/${MCU_VARIANT} - ${SDK_DIR}/devices/${MCU_VARIANT}/project_template - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers - ${SDK_DIR}/drivers/common - ${SDK_DIR}/drivers/igpio - ${SDK_DIR}/drivers/lpuart ) - if(NOT TARGET tinyusb_config) - message(FATAL_ERROR "tinyusb_config target not found") - endif() + #---------- TinyUSB ---------- + # tinyusb target is built for each example since it depends on example's tusb_config.h + set(TINYUSB_TARGET_PREFIX ${TARGET}) + add_library(${TARGET}_tinyusb_config INTERFACE) - target_compile_definitions(tinyusb_config INTERFACE + target_include_directories(${TARGET}_tinyusb_config INTERFACE + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) + target_compile_definitions(${TARGET}_tinyusb_config INTERFACE CFG_TUSB_MCU=OPT_MCU_MIMXRT ) - # include tinyusb CMakeList.txt for tinyusb target + # tinyusb's CMakeList.txt add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) - add_library(tinyusb_port STATIC - ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c - ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c - ${TOP}/src/portable/ehci/ehci.c - ) - - - target_link_libraries(${TARGET} PUBLIC - tinyusb - bsp - ) + # Link dependencies + target_link_libraries(${BSP_TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}_tinyusb) + target_link_libraries(${TARGET} PUBLIC ${BSP_TARGET} ${TARGET}_tinyusb) endfunction() -function(family_add_freertos_config TARGET) +function(family_configure_freertos_example TARGET) add_library(freertos_config INTERFACE) # add path to FreeRTOSConfig.h diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index e7e3125a2..21aa23d54 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -3,62 +3,56 @@ cmake_minimum_required(VERSION 3.17) -if (NOT TARGET tinyusb_config) - message(FATAL_ERROR "tinyusb_config target is not defined") -endif() +# Add tinyusb to a target +function(add_tinyusb TARGET) + target_sources(${TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/common/tusb_fifo.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd_control.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/audio/audio_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/cdc/cdc_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_rt_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/midi/midi_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ecm_rndis_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ncm_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/usbtmc/usbtmc_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/video/video_device.c + ) + target_include_directories(${TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ) + # enable all possible warnings + target_compile_options(${TARGET} PUBLIC + ) +endfunction() -add_library(tinyusb STATIC - ${CMAKE_CURRENT_LIST_DIR}/tusb.c - ${CMAKE_CURRENT_LIST_DIR}/common/tusb_fifo.c - ${CMAKE_CURRENT_LIST_DIR}/device/usbd.c - ${CMAKE_CURRENT_LIST_DIR}/device/usbd_control.c - ${CMAKE_CURRENT_LIST_DIR}/class/audio/audio_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/cdc/cdc_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_rt_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/hid/hid_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/midi/midi_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/msc/msc_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/net/ecm_rndis_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/net/ncm_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/usbtmc/usbtmc_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/vendor/vendor_device.c - ${CMAKE_CURRENT_LIST_DIR}/class/video/video_device.c - ) +set(TINYUSB_TARGET "tinyusb") +set(TINYUSB_CONFIG_TARGET "tinyusb_config") -target_include_directories(tinyusb PUBLIC - ${CMAKE_CURRENT_LIST_DIR} - ) +if (DEFINED TINYUSB_TARGET_PREFIX) + set(TINYUSB_TARGET "${TINYUSB_TARGET_PREFIX}_${TINYUSB_TARGET}") + set(TINYUSB_CONFIG_TARGET "${TINYUSB_TARGET_PREFIX}_${TINYUSB_CONFIG_TARGET}") +endif () -target_link_libraries(tinyusb PUBLIC - tinyusb_config - ) +if (DEFINED TINYUSB_TARGET_SUFFIX) + set(TINYUSB_TARGET "${TINYUSB_TARGET}_${TINYUSB_TARGET_SUFFIX}") + set(TINYUSB_CONFIG_TARGET "${TINYUSB_CONFIG_TARGET}_${TINYUSB_TARGET_SUFFIX}") +endif () + +add_library(${TINYUSB_TARGET} STATIC) +add_tinyusb(${TINYUSB_TARGET}) -#function(add_tinyusb TARGET) -# target_sources(${TARGET} PUBLIC -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/common/tusb_fifo.c -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd.c -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd_control.c -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/audio/audio_device.c -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/cdc/cdc_device.c -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_device.c -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_rt_device.c -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_device.c -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/midi/midi_device.c -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_device.c -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ecm_rndis_device.c -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ncm_device.c -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/usbtmc/usbtmc_device.c -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_device.c -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/video/video_device.c -# ) -# -# target_include_directories(${TARGET} PUBLIC -# ${CMAKE_CURRENT_FUNCTION_LIST_DIR} -# ) -# -# # enable all possible warnings -# target_compile_options(${TARGET} PUBLIC -# ) -#endfunction() +# Link with tinyusb_config target + +if (NOT TARGET ${TINYUSB_CONFIG_TARGET}) + message(FATAL_ERROR "${TINYUSB_CONFIG_TARGET} target is not defined") +endif() + +target_link_libraries(${TINYUSB_TARGET} PUBLIC + ${TINYUSB_CONFIG_TARGET} + ) -- cgit v1.3.1 From 6945c594d53ca6a35f1f0bb120b5a652c6ce9e84 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 7 May 2023 22:09:08 +0700 Subject: update all device cmake example for imx --- .idea/runConfigurations/rt10xx_pyocd.xml | 7 --- examples/CMakeLists.txt | 6 +-- examples/cmake/cpu/cortex-m7.cmake | 18 +++++--- examples/device/CMakeLists.txt | 2 +- examples/device/cdc_msc_freertos/CMakeLists.txt | 10 +---- .../device/hid_composite_freertos/CMakeLists.txt | 10 +---- examples/dual/CMakeLists.txt | 4 +- .../dual/host_hid_to_device_cdc/CMakeLists.txt | 4 +- examples/host/CMakeLists.txt | 4 +- examples/host/bare_api/CMakeLists.txt | 4 +- examples/host/hid_controller/CMakeLists.txt | 4 +- examples/host/msc_file_explorer/CMakeLists.txt | 4 +- hw/bsp/imxrt/FreeRTOSConfig/CMakeLists.txt | 8 ++++ hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake | 3 ++ hw/bsp/imxrt/family.cmake | 52 ++++++++++++++-------- src/CMakeLists.txt | 8 ++-- 16 files changed, 81 insertions(+), 67 deletions(-) delete mode 100644 .idea/runConfigurations/rt10xx_pyocd.xml create mode 100644 hw/bsp/imxrt/FreeRTOSConfig/CMakeLists.txt (limited to 'src') diff --git a/.idea/runConfigurations/rt10xx_pyocd.xml b/.idea/runConfigurations/rt10xx_pyocd.xml deleted file mode 100644 index f5c142690..000000000 --- a/.idea/runConfigurations/rt10xx_pyocd.xml +++ /dev/null @@ -1,7 +0,0 @@ - - - - - - \ No newline at end of file diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt index a23b4ed62..91c9fb098 100644 --- a/examples/CMakeLists.txt +++ b/examples/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.17) #set(CMAKE_EXPORT_COMPILE_COMMANDS ON) include(${CMAKE_CURRENT_SOURCE_DIR}/../hw/bsp/family_support.cmake) @@ -6,5 +6,5 @@ include(${CMAKE_CURRENT_SOURCE_DIR}/../hw/bsp/family_support.cmake) project(tinyusb_examples C CXX ASM) add_subdirectory(device) -#add_subdirectory(dual) -#add_subdirectory(host) +add_subdirectory(dual) +add_subdirectory(host) diff --git a/examples/cmake/cpu/cortex-m7.cmake b/examples/cmake/cpu/cortex-m7.cmake index 2b258726f..458d8b438 100644 --- a/examples/cmake/cpu/cortex-m7.cmake +++ b/examples/cmake/cpu/cortex-m7.cmake @@ -1,6 +1,12 @@ -set(TOOLCHAIN_COMMON_FLAGS - -mthumb - -mcpu=cortex-m7 - -mfloat-abi=hard - -mfpu=fpv5-d16 - ) +if (TOOLCHAIN STREQUAL "gcc") + set(TOOLCHAIN_COMMON_FLAGS + -mthumb + -mcpu=cortex-m7 + -mfloat-abi=hard + -mfpu=fpv5-d16 + ) + + set(FREERTOS_PORT GCC_ARM_CM7 CACHE INTERNAL "") +else () + # TODO support IAR +endif () diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt index ac1bbf161..5b077a5e1 100644 --- a/examples/device/CMakeLists.txt +++ b/examples/device/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.17) include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake) diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt index 75ec33145..319ad0356 100644 --- a/examples/device/cdc_msc_freertos/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/CMakeLists.txt @@ -34,11 +34,5 @@ target_include_directories(${PROJECT} PUBLIC # in hw/bsp/FAMILY/family.cmake for details. family_configure_device_example(${PROJECT}) -if (NOT TARGET freertos_kernel) -family_configure_freertos_example(${PROJECT}) -add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/../../../lib/FreeRTOS-Kernel lib/FreeRTOS-Kernel) -endif() - -target_link_libraries(${PROJECT} PUBLIC - freertos_kernel - ) +# Add FreeRTOS for this example +family_add_freertos(${PROJECT}) diff --git a/examples/device/hid_composite_freertos/CMakeLists.txt b/examples/device/hid_composite_freertos/CMakeLists.txt index 30729f438..211904cf9 100644 --- a/examples/device/hid_composite_freertos/CMakeLists.txt +++ b/examples/device/hid_composite_freertos/CMakeLists.txt @@ -33,11 +33,5 @@ target_include_directories(${PROJECT} PUBLIC # in hw/bsp/FAMILY/family.cmake for details. family_configure_device_example(${PROJECT}) -if (NOT TARGET freertos_kernel) -family_configure_freertos_example(${PROJECT}) -add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/../../../lib/FreeRTOS-Kernel lib/FreeRTOS-Kernel) -endif() - -target_link_libraries(${PROJECT} PUBLIC - freertos_kernel - ) +# Add FreeRTOS for this example +family_add_freertos(${PROJECT}) diff --git a/examples/dual/CMakeLists.txt b/examples/dual/CMakeLists.txt index d2f9a42f0..d211c8b83 100644 --- a/examples/dual/CMakeLists.txt +++ b/examples/dual/CMakeLists.txt @@ -1,8 +1,8 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.17) include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake) -project(tinyusb_dual_examples) +project(tinyusb_dual_examples C CXX ASM) family_initialize_project(tinyusb_dual_examples ${CMAKE_CURRENT_LIST_DIR}) if (FAMILY STREQUAL "rp2040" AND NOT TARGET tinyusb_pico_pio_usb) message("Skipping dual host/device mode examples as Pico-PIO-USB is not available") diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt index 724d1e119..3505d39eb 100644 --- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt +++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt @@ -1,11 +1,11 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.17) include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) # gets PROJECT name for the example (e.g. -) family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) -project(${PROJECT}) +project(${PROJECT} C CXX ASM) # Checks this example is valid for the family and initializes the project family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) diff --git a/examples/host/CMakeLists.txt b/examples/host/CMakeLists.txt index 758973ab2..bedd2220b 100644 --- a/examples/host/CMakeLists.txt +++ b/examples/host/CMakeLists.txt @@ -1,8 +1,8 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.17) include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake) -project(tinyusb_host_examples) +project(tinyusb_host_examples C CXX ASM) family_initialize_project(tinyusb_host_examples ${CMAKE_CURRENT_LIST_DIR}) # family_add_subdirectory will filter what to actually add based on selected FAMILY diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt index 616edd4ac..b6d8c9c89 100644 --- a/examples/host/bare_api/CMakeLists.txt +++ b/examples/host/bare_api/CMakeLists.txt @@ -1,11 +1,11 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.17) include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) # gets PROJECT name for the example family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) -project(${PROJECT}) +project(${PROJECT} C CXX ASM) # Checks this example is valid for the family and initializes the project family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt index ac3070b82..e1d2f1642 100644 --- a/examples/host/hid_controller/CMakeLists.txt +++ b/examples/host/hid_controller/CMakeLists.txt @@ -1,11 +1,11 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.17) include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) # gets PROJECT name for the example (e.g. -) family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) -project(${PROJECT}) +project(${PROJECT} C CXX ASM) # Checks this example is valid for the family and initializes the project family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt index 7955b3078..2ab0aa881 100644 --- a/examples/host/msc_file_explorer/CMakeLists.txt +++ b/examples/host/msc_file_explorer/CMakeLists.txt @@ -1,11 +1,11 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.17) include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) # gets PROJECT name for the example (e.g. -) family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) -project(${PROJECT}) +project(${PROJECT} C CXX ASM) # Checks this example is valid for the family and initializes the project family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) diff --git a/hw/bsp/imxrt/FreeRTOSConfig/CMakeLists.txt b/hw/bsp/imxrt/FreeRTOSConfig/CMakeLists.txt new file mode 100644 index 000000000..0bacaf824 --- /dev/null +++ b/hw/bsp/imxrt/FreeRTOSConfig/CMakeLists.txt @@ -0,0 +1,8 @@ +if (NOT TARGET freertos_config) + add_library(freertos_config INTERFACE) + + # add path to FreeRTOSConfig.h + target_include_directories(freertos_config SYSTEM INTERFACE + ${CMAKE_CURRENT_LIST_DIR} + ) +endif() diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake index d4015e488..02955e356 100644 --- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake @@ -1,5 +1,8 @@ set(MCU_VARIANT MIMXRT1011) +set(JLINK_DEVICE MIMXRT1011DAE5A) +set(PYOCD_TARGET mimxrt1010) + function(update_board TARGET) target_sources(${TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 1731d9e60..653885bb2 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -81,7 +81,7 @@ function(family_configure_target TARGET) #---------- BSP_TARGET ---------- # BSP_TARGET is built for each example since it depends on example's tusb_config.h - set(BSP_TARGET "${TARGET}_bsp_${BOARD}") + set(BSP_TARGET "${TARGET}-bsp") add_library(${BSP_TARGET} STATIC # TinyUSB ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -98,13 +98,13 @@ function(family_configure_target TARGET) #---------- TinyUSB ---------- # tinyusb target is built for each example since it depends on example's tusb_config.h - set(TINYUSB_TARGET_PREFIX ${TARGET}) - add_library(${TARGET}_tinyusb_config INTERFACE) + set(TINYUSB_TARGET_PREFIX ${TARGET}-) + add_library(${TARGET}-tinyusb_config INTERFACE) - target_include_directories(${TARGET}_tinyusb_config INTERFACE + target_include_directories(${TARGET}-tinyusb_config INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/src ) - target_compile_definitions(${TARGET}_tinyusb_config INTERFACE + target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_MCU=OPT_MCU_MIMXRT ) @@ -112,25 +112,41 @@ function(family_configure_target TARGET) add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) # Link dependencies - target_link_libraries(${BSP_TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}_tinyusb) - target_link_libraries(${TARGET} PUBLIC ${BSP_TARGET} ${TARGET}_tinyusb) + target_link_libraries(${BSP_TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb) + target_link_libraries(${TARGET} PUBLIC ${BSP_TARGET} ${TARGET}-tinyusb) + + # Flash Target + add_custom_target(${TARGET}-pyocd + COMMAND pyocd flash -t ${PYOCD_TARGET} $ + ) endfunction() -function(family_configure_freertos_example TARGET) - add_library(freertos_config INTERFACE) +function(family_add_freertos TARGET) + # freertos_config + add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig ${CMAKE_CURRENT_BINARY_DIR}/freertos_config) + + ## freertos + if (NOT TARGET freertos_kernel) + add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../lib/FreeRTOS-Kernel ${CMAKE_CURRENT_BINARY_DIR}/freertos_kernel) + endif () - # add path to FreeRTOSConfig.h - target_include_directories(freertos_config SYSTEM INTERFACE - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig + # Add FreeRTOS option to tinyusb_config + target_compile_definitions(${TARGET}-tinyusb_config INTERFACE + CFG_TUSB_OS=OPT_OS_FREERTOS + ) + # tinyusb need to be linked with freeRTOS kernel + target_link_libraries(${TARGET}-tinyusb PUBLIC + freertos_kernel ) - # select freertos port - if (TOOLCHAIN STREQUAL "gcc") - set(FREERTOS_PORT "GCC_ARM_CM7" CACHE INTERNAL "") - else () - # TODO support IAR - endif () + target_link_libraries(${TARGET}-tinyusb PUBLIC + freertos_kernel + ) + + target_link_libraries(${TARGET} PUBLIC + freertos_kernel + ) endfunction() function(family_configure_device_example TARGET) diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 21aa23d54..02f962f44 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -35,13 +35,13 @@ set(TINYUSB_TARGET "tinyusb") set(TINYUSB_CONFIG_TARGET "tinyusb_config") if (DEFINED TINYUSB_TARGET_PREFIX) - set(TINYUSB_TARGET "${TINYUSB_TARGET_PREFIX}_${TINYUSB_TARGET}") - set(TINYUSB_CONFIG_TARGET "${TINYUSB_TARGET_PREFIX}_${TINYUSB_CONFIG_TARGET}") + set(TINYUSB_TARGET "${TINYUSB_TARGET_PREFIX}${TINYUSB_TARGET}") + set(TINYUSB_CONFIG_TARGET "${TINYUSB_TARGET_PREFIX}${TINYUSB_CONFIG_TARGET}") endif () if (DEFINED TINYUSB_TARGET_SUFFIX) - set(TINYUSB_TARGET "${TINYUSB_TARGET}_${TINYUSB_TARGET_SUFFIX}") - set(TINYUSB_CONFIG_TARGET "${TINYUSB_CONFIG_TARGET}_${TINYUSB_TARGET_SUFFIX}") + set(TINYUSB_TARGET "${TINYUSB_TARGET}${TINYUSB_TARGET_SUFFIX}") + set(TINYUSB_CONFIG_TARGET "${TINYUSB_CONFIG_TARGET}${TINYUSB_TARGET_SUFFIX}") endif () add_library(${TINYUSB_TARGET} STATIC) -- cgit v1.3.1 From 654f1821769f50c44f786032bedfe417a9ad4d0f Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 8 May 2023 00:24:48 +0700 Subject: build host examples with imx --- examples/host/cdc_msc_hid/CMakeLists.txt | 14 ++++---- examples/host/hid_controller/CMakeLists.txt | 10 +++--- examples/host/msc_file_explorer/CMakeLists.txt | 20 +++++------ hw/bsp/board.c | 49 -------------------------- hw/bsp/imxrt/family.cmake | 7 ++++ src/CMakeLists.txt | 9 +++++ 6 files changed, 38 insertions(+), 71 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt index 42dac5be7..68b52e274 100644 --- a/examples/host/cdc_msc_hid/CMakeLists.txt +++ b/examples/host/cdc_msc_hid/CMakeLists.txt @@ -14,16 +14,16 @@ add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c + ) # Example include target_include_directories(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt index e1d2f1642..e27f83c53 100644 --- a/examples/host/hid_controller/CMakeLists.txt +++ b/examples/host/hid_controller/CMakeLists.txt @@ -14,14 +14,14 @@ add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ) # Example include target_include_directories(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt index 2ab0aa881..2d5600059 100644 --- a/examples/host/msc_file_explorer/CMakeLists.txt +++ b/examples/host/msc_file_explorer/CMakeLists.txt @@ -14,19 +14,19 @@ add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c - ${TOP}/lib/fatfs/source/ff.c - ${TOP}/lib/fatfs/source/ffsystem.c - ${TOP}/lib/fatfs/source/ffunicode.c - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c + ${TOP}/lib/fatfs/source/ff.c + ${TOP}/lib/fatfs/source/ffsystem.c + ${TOP}/lib/fatfs/source/ffunicode.c + ) # Example include target_include_directories(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src - ${TOP}/lib/fatfs/source - ${TOP}/lib/embedded-cli - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src + ${TOP}/lib/fatfs/source + ${TOP}/lib/embedded-cli + ) # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. diff --git a/hw/bsp/board.c b/hw/bsp/board.c index e715bdf2e..66ffcb199 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -25,55 +25,6 @@ #include "board.h" -#if 0 -#define LED_PHASE_MAX 8 - -static struct -{ - uint32_t phase[LED_PHASE_MAX]; - uint8_t phase_count; - - bool led_state; - uint8_t current_phase; - uint32_t current_ms; -}led_pattern; - -void board_led_pattern(uint32_t const phase_ms[], uint8_t count) -{ - memcpy(led_pattern.phase, phase_ms, 4*count); - led_pattern.phase_count = count; - - // reset with 1st phase is on - led_pattern.current_ms = board_millis(); - led_pattern.current_phase = 0; - led_pattern.led_state = true; - board_led_on(); -} - -void board_led_task(void) -{ - if ( led_pattern.phase_count == 0 ) return; - - uint32_t const duration = led_pattern.phase[led_pattern.current_phase]; - - // return if not enough time - if (board_millis() - led_pattern.current_ms < duration) return; - - led_pattern.led_state = !led_pattern.led_state; - board_led_write(led_pattern.led_state); - - led_pattern.current_ms += duration; - led_pattern.current_phase++; - - if (led_pattern.current_phase == led_pattern.phase_count) - { - led_pattern.current_phase = 0; - led_pattern.led_state = true; - board_led_on(); - } -} -#endif - //--------------------------------------------------------------------+ // newlib read()/write() retarget //--------------------------------------------------------------------+ diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 653885bb2..b180f725e 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -12,6 +12,8 @@ endif () set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../examples/cmake/toolchain/arm_${TOOLCHAIN}.cmake) +set(FAMILY_MCUS MIMXRT CACHE INTERNAL "") + # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) @@ -89,6 +91,7 @@ function(family_configure_target TARGET) ${TOP}/src/portable/ehci/ehci.c # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c ) target_include_directories(${BSP_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} @@ -152,3 +155,7 @@ endfunction() function(family_configure_device_example TARGET) family_configure_target(${TARGET}) endfunction() + +function(family_configure_host_example TARGET) + family_configure_target(${TARGET}) +endfunction() diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 02f962f44..0b99d8919 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -6,8 +6,10 @@ cmake_minimum_required(VERSION 3.17) # Add tinyusb to a target function(add_tinyusb TARGET) target_sources(${TARGET} PUBLIC + # common ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/common/tusb_fifo.c + # device ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd_control.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/audio/audio_device.c @@ -22,6 +24,13 @@ function(add_tinyusb TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/usbtmc/usbtmc_device.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_device.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/video/video_device.c + # host + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/host/usbh.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/host/hub.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/cdc/cdc_host.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_host.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_host.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_host.c ) target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} -- cgit v1.3.1 From 77f0726361c66bf2783c1ce68e0f00bdd5f58229 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 9 May 2023 17:32:14 +0700 Subject: fix ehci issue with portsc when enable port power and port reset fix attached device not regconized if attached before power on --- .idea/runConfigurations/rt1060_redlink.xml | 10 ++ hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake | 1 + hw/bsp/imxrt/family.cmake | 19 +++- src/portable/ehci/ehci.c | 90 ++++++++++------- src/portable/ehci/ehci.h | 132 +++++++++++++++++-------- 5 files changed, 171 insertions(+), 81 deletions(-) create mode 100644 .idea/runConfigurations/rt1060_redlink.xml (limited to 'src') diff --git a/.idea/runConfigurations/rt1060_redlink.xml b/.idea/runConfigurations/rt1060_redlink.xml new file mode 100644 index 000000000..a6f345fac --- /dev/null +++ b/.idea/runConfigurations/rt1060_redlink.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake index 033f9fcf9..171d427de 100644 --- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake @@ -2,6 +2,7 @@ set(MCU_VARIANT MIMXRT1062) set(JLINK_DEVICE MIMXRT1062xxx6A) set(PYOCD_TARGET mimxrt1060) +set(NXPLS_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060) function(update_board TARGET) target_sources(${TARGET} PUBLIC diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index e9615a1f4..e38bcf4b1 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -121,15 +121,26 @@ function(family_configure_target TARGET) # Link dependencies target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb) - # Flash Target + # group target (not yet supported by clion) + set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config + PROPERTIES FOLDER ${TARGET}_sub + ) + + #---------- Flash ---------- + # Flash using pyocd add_custom_target(${TARGET}-pyocd COMMAND pyocd flash -t ${PYOCD_TARGET} $ ) - # group target - set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config - PROPERTIES FOLDER ${TARGET}_sub + # Flash using NXP LinkServer (redlink) + # https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/linkserver-for-microcontrollers:LINKERSERVER + # LinkServer has a bug that can only execute with full path otherwise it throws: + # realpath error: No such file or directory + execute_process(COMMAND which LinkServer OUTPUT_VARIABLE LINKSERVER_PATH OUTPUT_STRIP_TRAILING_WHITESPACE) + add_custom_target(${TARGET}-redlink + COMMAND ${LINKSERVER_PATH} flash ${NXPLS_DEVICE} load $ ) + endfunction() diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 9951aa5da..494e2e50f 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -79,7 +79,8 @@ typedef struct ehci_qhd_t qhd_pool[QHD_MAX]; ehci_qtd_t qtd_pool[QTD_MAX] TU_ATTR_ALIGNED(32); - ehci_registers_t* regs; + ehci_registers_t* regs; // operational register + ehci_cap_registers_t* cap_regs; // capability register volatile uint32_t uframe_number; }ehci_data_t; @@ -87,6 +88,26 @@ typedef struct // Periodic frame list must be 4K alignment CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data; +//--------------------------------------------------------------------+ +// Debug +//--------------------------------------------------------------------+ +#if CFG_TUSB_DEBUG >= EHCI_DBG +static inline void print_portsc(ehci_registers_t* regs) +{ + TU_LOG_HEX(EHCI_DBG, regs->portsc); + TU_LOG(EHCI_DBG, " Current Connect Status: %u\r\n", regs->portsc_bm.current_connect_status); + TU_LOG(EHCI_DBG, " Connect Status Change : %u\r\n", regs->portsc_bm.connect_status_change); + TU_LOG(EHCI_DBG, " Port Enabled : %u\r\n", regs->portsc_bm.port_enabled); + TU_LOG(EHCI_DBG, " Port Enabled Change : %u\r\n", regs->portsc_bm.port_enable_change); + + TU_LOG(EHCI_DBG, " Port Reset : %u\r\n", regs->portsc_bm.port_reset); + TU_LOG(EHCI_DBG, " Port Power : %u\r\n", regs->portsc_bm.port_power); +} + +#else +#define print_portsc(_reg) +#endif + //--------------------------------------------------------------------+ // PROTOTYPE //--------------------------------------------------------------------+ @@ -152,11 +173,11 @@ void hcd_port_reset(uint8_t rhport) ehci_registers_t* regs = ehci_data.regs; -// regs->portsc_bm.port_enabled = 0; // disable port before reset -// regs->portsc_bm.port_reset = 1; - - uint32_t portsc = regs->portsc; + // mask out all change bits since they are Write 1 to clear + uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL; + // EHCI Table 2-16 PortSC + // when software writes Port Reset bit to a one, it must also write a zero to the Port Enable bit. portsc &= ~(EHCI_PORTSC_MASK_PORT_EANBLED); portsc |= EHCI_PORTSC_MASK_PORT_RESET; @@ -167,9 +188,14 @@ void hcd_port_reset_end(uint8_t rhport) { (void) rhport; -#if 0 +#if 0 // TODO check if this is necessary ehci_registers_t* regs = ehci_data.regs; - regs->portsc_bm.port_reset = 0; + + // mask out all change bits since they are Write 1 to clear + uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL; + portsc &= ~(EHCI_PORTSC_MASK_PORT_RESET); + + regs->portsc = portsc; #endif } @@ -240,19 +266,26 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) { - (void) capability_reg; // not used yet - tu_memclr(&ehci_data, sizeof(ehci_data_t)); - ehci_data.regs = (ehci_registers_t* ) operatial_reg; + ehci_data.regs = (ehci_registers_t*) operatial_reg; + ehci_data.cap_regs = (ehci_cap_registers_t*) capability_reg; ehci_registers_t* regs = ehci_data.regs; + // EHCI 4.1 Host Controller Initialization + //------------- CTRLDSSEGMENT Register (skip) -------------// + //------------- USB INT Register -------------// - regs->inten = 0; // 1. disable all the interrupt - regs->status = EHCI_INT_MASK_ALL; // 2. clear all status + // disable all the interrupt + regs->inten = 0; + + // clear all status except port change since device maybe connected before this driver is initialized + regs->status = (EHCI_INT_MASK_ALL & ~EHCI_INT_MASK_PORT_CHANGE); + + // Enable interrupts regs->inten = EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE | EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_PERIODIC | EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_FRAMELIST_ROLLOVER; @@ -316,7 +349,16 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) FRAMELIST_SIZE_USBCMD_VALUE; //------------- ConfigFlag Register (skip) -------------// - regs->portsc_bm.port_power = 1; // enable port power + + // enable port power bit in portsc. The function of this bit depends on the value of the Port + // Power Control (PPC) field in the HCSPARAMS register. + if (ehci_data.cap_regs->hcsparams_bm.port_power_control) { + // mask out all change bits since they are Write 1 to clear + uint32_t portsc = (regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL); + portsc |= ECHI_PORTSC_MASK_PORT_POWER; + + regs->portsc = portsc; + } return true; } @@ -656,26 +698,6 @@ static void xfer_error_isr(uint8_t hostid) } } -#if CFG_TUSB_DEBUG >= EHCI_DBG - -static inline void print_portsc(ehci_registers_t* regs) -{ - TU_LOG_HEX(EHCI_DBG, regs->portsc); - TU_LOG(EHCI_DBG, " Current Connect Status: %u\r\n", regs->portsc_bm.current_connect_status); - TU_LOG(EHCI_DBG, " Connect Status Change : %u\r\n", regs->portsc_bm.connect_status_change); - TU_LOG(EHCI_DBG, " Port Enabled : %u\r\n", regs->portsc_bm.port_enabled); - TU_LOG(EHCI_DBG, " Port Enabled Change : %u\r\n", regs->portsc_bm.port_enable_change); - - TU_LOG(EHCI_DBG, " Port Reset : %u\r\n", regs->portsc_bm.port_reset); - TU_LOG(EHCI_DBG, " Port Power : %u\r\n", regs->portsc_bm.port_power); -} - -#else - -#define print_portsc(_reg) - -#endif - //------------- Host Controller Driver's Interrupt Handler -------------// void hcd_int_handler(uint8_t rhport) { @@ -695,7 +717,7 @@ void hcd_int_handler(uint8_t rhport) if (int_status & EHCI_INT_MASK_PORT_CHANGE) { - uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_ALL; + uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_CHANGE_ALL; print_portsc(regs); if (regs->portsc_bm.connect_status_change) diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h index 36f8649be..dd090cb36 100644 --- a/src/portable/ehci/ehci.h +++ b/src/portable/ehci/ehci.h @@ -267,16 +267,15 @@ TU_VERIFY_STATIC( sizeof(ehci_sitd_t) == 32, "size is not correct" ); //--------------------------------------------------------------------+ // EHCI Operational Register //--------------------------------------------------------------------+ -enum ehci_interrupt_mask_{ +enum { EHCI_INT_MASK_USB = TU_BIT(0), EHCI_INT_MASK_ERROR = TU_BIT(1), EHCI_INT_MASK_PORT_CHANGE = TU_BIT(2), - EHCI_INT_MASK_FRAMELIST_ROLLOVER = TU_BIT(3), EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR = TU_BIT(4), EHCI_INT_MASK_ASYNC_ADVANCE = TU_BIT(5), - EHCI_INT_MASK_NXP_SOF = TU_BIT(7), + EHCI_INT_MASK_NXP_SOF = TU_BIT(7), EHCI_INT_MASK_NXP_ASYNC = TU_BIT(18), EHCI_INT_MASK_NXP_PERIODIC = TU_BIT(19), @@ -287,7 +286,7 @@ enum ehci_interrupt_mask_{ EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_NXP_PERIODIC }; -enum ehci_usbcmd_pos_ { +enum { EHCI_USBCMD_POS_RUN_STOP = 0, EHCI_USBCMD_POS_FRAMELIST_SIZE = 2, EHCI_USBCMD_POS_PERIOD_ENABLE = 4, @@ -296,24 +295,27 @@ enum ehci_usbcmd_pos_ { EHCI_USBCMD_POS_INTERRUPT_THRESHOLD = 16 }; -enum ehci_portsc_change_mask_{ +enum { EHCI_PORTSC_MASK_CURRENT_CONNECT_STATUS = TU_BIT(0), EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE = TU_BIT(1), EHCI_PORTSC_MASK_PORT_EANBLED = TU_BIT(2), - EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE = TU_BIT(3), + EHCI_PORTSC_MASK_PORT_ENABLE_CHANGE = TU_BIT(3), EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE = TU_BIT(5), + EHCI_PORTSC_MASK_FORCE_RESUME = TU_BIT(6), + EHCI_PORTSC_MASK_PORT_SUSPEND = TU_BIT(7), EHCI_PORTSC_MASK_PORT_RESET = TU_BIT(8), + ECHI_PORTSC_MASK_PORT_POWER = TU_BIT(12), - EHCI_PORTSC_MASK_ALL = - EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE | - EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE | - EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE + EHCI_PORTSC_MASK_CHANGE_ALL = + EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE | + EHCI_PORTSC_MASK_PORT_ENABLE_CHANGE | + EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE }; typedef volatile struct { union { - uint32_t command; + uint32_t command; // 0x00 struct { uint32_t run_stop : 1 ; ///< 1=Run. 0=Stop @@ -333,7 +335,7 @@ typedef volatile struct }; union { - uint32_t status; + uint32_t status; // 0x04 struct { uint32_t usb : 1 ; ///< qTD with IOC is retired @@ -357,7 +359,7 @@ typedef volatile struct }; union{ - uint32_t inten; + uint32_t inten; // 0x08 struct { uint32_t usb : 1 ; @@ -375,43 +377,87 @@ typedef volatile struct }inten_bm; }; - uint32_t frame_index ; ///< Micro frame counter - uint32_t ctrl_ds_seg ; ///< Control Data Structure Segment - uint32_t periodic_list_base ; ///< Beginning address of perodic frame list - uint32_t async_list_addr ; ///< Address of next async QHD to be executed + uint32_t frame_index ; ///< 0x0C Micro frame counter + uint32_t ctrl_ds_seg ; ///< 0x10 Control Data Structure Segment + uint32_t periodic_list_base ; ///< 0x14 Beginning address of perodic frame list + uint32_t async_list_addr ; ///< 0x18 Address of next async QHD to be executed uint32_t nxp_tt_control ; ///< nxp embedded transaction translator (reserved by EHCI specs) uint32_t reserved[8] ; - uint32_t config_flag ; ///< not used by NXP + uint32_t config_flag ; ///< 0x40 not used by NXP union { - uint32_t portsc ; ///< port status and control - struct { - uint32_t current_connect_status : 1; ///< 0: No device, 1: Device is present on port - uint32_t connect_status_change : 1; ///< Change in Current Connect Status - uint32_t port_enabled : 1; ///< Ports can only be enabled by HC as a part of the reset and enable. SW can write 0 to disable - uint32_t port_enable_change : 1; ///< Port Enabled has changed - uint32_t over_current_active : 1; ///< Port has an over-current condition - uint32_t over_current_change : 1; ///< Change to Over-current Active - uint32_t force_port_resume : 1; ///< Resume detected/driven on port. This functionality defined for manipulating this bit depends on the value of the Suspend bit. - uint32_t suspend : 1; ///< Port in suspend state - uint32_t port_reset : 1; ///< 1=Port is in Reset. 0=Port is not in Reset - uint32_t nxp_highspeed_status : 1; ///< NXP customized: 0=connected to the port is not in High-speed mode, 1=connected to the port is in High-speed mode - uint32_t line_status : 2; ///< D+/D- state: 00: SE0, 10: J-state, 01: K-state - uint32_t port_power : 1; ///< 0= power off, 1= power on - uint32_t port_owner : 1; ///< not used by NXP - uint32_t port_indicator_control : 2; ///< 00b: off, 01b: Amber, 10b: green, 11b: undefined - uint32_t port_test_control : 4; ///< Port test mode, not used by tinyusb - uint32_t wake_on_connect_enable : 1; ///< Enables device connects as wake-up events - uint32_t wake_on_disconnect_enable : 1; ///< Enables device disconnects as wake-up events - uint32_t wake_on_over_current_enable : 1; ///< Enables over-current conditions as wake-up events - uint32_t nxp_phy_clock_disable : 1; ///< NXP customized: the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0: enable PHY clock, 1: disable PHY clock - uint32_t nxp_port_force_fullspeed : 1; ///< NXP customized: Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allowsthe port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device. - uint32_t TU_RESERVED : 1; - uint32_t nxp_port_speed : 2; ///< NXP customized: This register field indicates the speed atwhich the port is operating. For HS mode operation in the host controllerand HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 0x0: Fullspeed, 0x1: Lowspeed, 0x2: Highspeed + // mixed with RW and R/WC bits, care should be taken when writing to this register + uint32_t portsc ; ///< 0x44 port status and control + const struct { + uint32_t current_connect_status : 1; ///< 00: 0: No device, 1: Device is present on port + uint32_t connect_status_change : 1; ///< 01: [R/WC] Change in Current Connect Status + uint32_t port_enabled : 1; ///< 02: Ports can only be enabled by HC as a part of the reset and enable. SW can write 0 to disable + uint32_t port_enable_change : 1; ///< 03: [R/WC] Port Enabled has changed + uint32_t over_current_active : 1; ///< 04: Port has an over-current condition + uint32_t over_current_change : 1; ///< 05: [R/WC] Change to Over-current Active + uint32_t force_port_resume : 1; ///< 06: Resume detected/driven on port. This functionality defined for manipulating this bit depends on the value of the Suspend bit. + uint32_t suspend : 1; ///< 07: Port in suspend state + uint32_t port_reset : 1; ///< 08: 1=Port is in Reset. 0=Port is not in Reset + uint32_t nxp_highspeed_status : 1; ///< 09: NXP customized: 0=connected to the port is not in High-speed mode, 1=connected to the port is in High-speed mode + uint32_t line_status : 2; ///< 10-11: D+/D- state: 00: SE0, 10: J-state, 01: K-state + uint32_t port_power : 1; ///< 12: 0= power off, 1= power on + uint32_t port_owner : 1; ///< 13: not used by NXP + uint32_t port_indicator_control : 2; ///< 14-15: 00b: off, 01b: Amber, 10b: green, 11b: undefined + uint32_t port_test_control : 4; ///< 16-19: Port test mode, not used by tinyusb + uint32_t wake_on_connect_enable : 1; ///< 20: Enables device connects as wake-up events + uint32_t wake_on_disconnect_enable : 1; ///< 21: Enables device disconnects as wake-up events + uint32_t wake_on_over_current_enable : 1; ///< 22: Enables over-current conditions as wake-up events + uint32_t nxp_phy_clock_disable : 1; ///< 23: NXP customized: the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0: enable PHY clock, 1: disable PHY clock + uint32_t nxp_port_force_fullspeed : 1; ///< 24: NXP customized: Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allowsthe port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device. + uint32_t TU_RESERVED : 1; ///< 25 + uint32_t nxp_port_speed : 2; ///< 26-27: NXP customized: This register field indicates the speed atwhich the port is operating. For HS mode operation in the host controllerand HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 0x0: Fullspeed, 0x1: Lowspeed, 0x2: Highspeed uint32_t TU_RESERVED : 4; }portsc_bm; }; -}ehci_registers_t; +} ehci_registers_t; + +//--------------------------------------------------------------------+ +// Capability Registers +//--------------------------------------------------------------------+ +typedef volatile struct { + uint8_t caplength; // 0x00 + uint8_t TU_RESERVED; // 0x01 + uint16_t hciversion; // 0x02 + + union { + uint32_t hcsparams; // 0x04 + struct { + uint32_t num_ports : 4; // [00:03] + uint32_t port_power_control : 1; // [04] + uint32_t TU_RESERVED : 2; // [05:06] + uint32_t port_route_rule : 1; // [07] + uint32_t n_pcc : 4; // [08:11] Number of Ports per Companion Controller + uint32_t n_cc : 4; // [12:15] Number of Companion Controllers + uint32_t port_ind : 1; // [16] Port Indicators + uint32_t TU_RESERVED : 3; // [17:19] + uint32_t n_ptt : 4; // [20:23] ChipIdea: Number of Ports per Transaction Translator + uint32_t n_tt : 4; // [24:27] ChipIdea: Number of Transaction Translators + uint32_t TU_RESERVED : 4; // [28:31] + } hcsparams_bm; + }; + + union { + uint32_t hccparams; // 0x08 + struct { + uint32_t addr_64bit : 1; // [00] 64-bit Addressing Capability + uint32_t programmable_frame_list_flag : 1; // [01] Programmable Frame List Flag + uint32_t async_park_cap : 1; // [02] Asynchronous Schedule Park Capability + uint32_t TU_RESERVED : 1; // [03] + uint32_t iso_schedule_threshold : 4; // [4:7] Isochronous Scheduling Threshold + uint32_t eecp : 8; // [8:15] EHCI Extended Capabilities Pointer + uint32_t TU_RESERVED : 16;// [16:31] + } hccparams_bm; + }; + + uint32_t hcsp_portroute; // 0x0C HCSP Port Route Register +} ehci_cap_registers_t; + +TU_VERIFY_STATIC(sizeof(ehci_cap_registers_t) == 16, "size is not correct"); #ifdef __cplusplus } -- cgit v1.3.1 From c0e4c02b9d70240b97aa4924e6002ccb3d8057dd Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 10 May 2023 11:15:11 +0700 Subject: allow imxrt build with dual exmaples --- examples/cmake/toolchain/set_flags.cmake | 3 ++- examples/dual/CMakeLists.txt | 11 +++++---- .../dual/host_hid_to_device_cdc/CMakeLists.txt | 28 +++++++++++----------- hw/bsp/family_support.cmake | 4 ++-- hw/bsp/imxrt/family.cmake | 4 ++++ src/portable/chipidea/ci_hs/hcd_ci_hs.c | 2 ++ 6 files changed, 30 insertions(+), 22 deletions(-) (limited to 'src') diff --git a/examples/cmake/toolchain/set_flags.cmake b/examples/cmake/toolchain/set_flags.cmake index 27631abcd..3f109b59e 100644 --- a/examples/cmake/toolchain/set_flags.cmake +++ b/examples/cmake/toolchain/set_flags.cmake @@ -8,7 +8,8 @@ foreach(LANG IN ITEMS C CXX ASM) #cmake_print_variables(CMAKE_${LANG}_FLAGS_INIT) # optimization flags - set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-Og") + set(CMAKE_${LANG}_FLAGS_RELEASE_INIT "-Os") + set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-O0") endforeach() # Linker diff --git a/examples/dual/CMakeLists.txt b/examples/dual/CMakeLists.txt index d211c8b83..15081cf26 100644 --- a/examples/dual/CMakeLists.txt +++ b/examples/dual/CMakeLists.txt @@ -4,9 +4,10 @@ include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake) project(tinyusb_dual_examples C CXX ASM) family_initialize_project(tinyusb_dual_examples ${CMAKE_CURRENT_LIST_DIR}) + if (FAMILY STREQUAL "rp2040" AND NOT TARGET tinyusb_pico_pio_usb) - message("Skipping dual host/device mode examples as Pico-PIO-USB is not available") -else() - # family_add_subdirectory will filter what to actually add based on selected FAMILY - family_add_subdirectory(host_hid_to_device_cdc) -endif() + message("Skipping dual host/device mode examples as Pico-PIO-USB is not available") +else () + # family_add_subdirectory will filter what to actually add based on selected FAMILY + family_add_subdirectory(host_hid_to_device_cdc) +endif () diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt index 3505d39eb..c6d19a720 100644 --- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt +++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt @@ -14,14 +14,14 @@ add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c + ) # Example include target_include_directories(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. @@ -29,12 +29,12 @@ family_configure_dual_usb_example(${PROJECT}) # due to warnings from Pico-PIO-USB target_compile_options(${PROJECT} PUBLIC - -Wno-error=shadow - -Wno-error=cast-align - -Wno-error=cast-qual - -Wno-error=redundant-decls - -Wno-error=sign-conversion - -Wno-error=conversion - -Wno-error=sign-compare - -Wno-error=unused-function - ) + -Wno-error=shadow + -Wno-error=cast-align + -Wno-error=cast-qual + -Wno-error=redundant-decls + -Wno-error=sign-conversion + -Wno-error=conversion + -Wno-error=sign-compare + -Wno-error=unused-function + ) diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 26baa6365..01e7bb018 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -27,8 +27,8 @@ if (NOT TARGET _family_support_marker) foreach(MCU IN LISTS FAMILY_MCUS) # For each line in only.txt foreach(_line ${ONLYS_LINES}) - # If mcu:xxx exists for this mcu then include - if (${_line} STREQUAL "mcu:${MCU}") + # If mcu:xxx exists for this mcu or board:xxx then include + if (${_line} STREQUAL "mcu:${MCU}" OR ${_line} STREQUAL "board:${BOARD}") set(${RESULT} 1 PARENT_SCOPE) return() endif() diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 85ad104a0..b510c064e 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -173,3 +173,7 @@ endfunction() function(family_configure_host_example TARGET) family_configure_target(${TARGET}) endfunction() + +function(family_configure_dual_usb_example TARGET) + family_configure_target(${TARGET}) +endfunction() diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index d607627b4..b06633f30 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -76,6 +76,8 @@ bool hcd_init(uint8_t rhport) #endif // FIXME force full speed, still have issue with Highspeed enumeration + // 1. Have issue when plug/unplug devices, maybe the port is not reset properly + // 2. Also does not seems to detect disconnection hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED; return ehci_init(rhport, (uint32_t) &hcd_reg->CAPLENGTH, (uint32_t) &hcd_reg->USBCMD); -- cgit v1.3.1 From 206d63e038744b228cfa6051d701cab50b520fe6 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 11 May 2023 14:26:12 +0700 Subject: correct EHCI reporting failed xfer (instead of stalled) when device is unplugged --- src/class/cdc/cdc_host.c | 21 +++++++++++---------- src/class/hid/hid_host.c | 27 ++++++++++++++++----------- src/class/msc/msc_host.c | 10 +++++++--- src/common/tusb_debug.h | 1 + src/device/usbd_control.c | 9 ++++++--- src/host/hub.c | 9 ++++++++- src/host/usbh.c | 20 +++++++++++++------- src/portable/ehci/ehci.c | 11 ++++++++--- src/tusb.c | 4 ++++ 9 files changed, 74 insertions(+), 38 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index fe3691bf4..9ff666ed4 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -35,8 +35,7 @@ // Debug level, TUSB_CFG_DEBUG must be at least this level for debug message #define CDCH_DEBUG 2 - -#define TU_LOG_CDCH(...) TU_LOG(CDCH_DEBUG, __VA_ARGS__) +#define TU_LOG_DRV(...) TU_LOG(CDCH_DEBUG, __VA_ARGS__) //--------------------------------------------------------------------+ // Host CDC Interface @@ -537,6 +536,8 @@ void cdch_close(uint8_t daddr) cdch_interface_t* p_cdc = &cdch_data[idx]; if (p_cdc->daddr == daddr) { + TU_LOG_DRV(" CDCh close addr = %u index = %u\r\n", daddr, idx); + // Invoke application callback if (tuh_cdc_umount_cb) tuh_cdc_umount_cb(idx); @@ -804,7 +805,7 @@ static void acm_process_config(tuh_xfer_t* xfer) static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->acm_capability.support_line_request); - TU_LOG_CDCH("CDC ACM Set Control Line State\r\n"); + TU_LOG_DRV("CDC ACM Set Control Line State\r\n"); tusb_control_request_t const request = { .bmRequestType_bit = { @@ -834,7 +835,7 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_st } static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG_CDCH("CDC ACM Set Line Conding\r\n"); + TU_LOG_DRV("CDC ACM Set Line Conding\r\n"); tusb_control_request_t const request = { .bmRequestType_bit = { @@ -894,7 +895,7 @@ static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY(p_cdc); - TU_LOG_CDCH("FTDI opened\r\n"); + TU_LOG_DRV("FTDI opened\r\n"); p_cdc->serial_drid = SERIAL_DRIVER_FTDI; @@ -938,7 +939,7 @@ static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, u static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG_CDCH("CDC FTDI Set Control Line State\r\n"); + TU_LOG_DRV("CDC FTDI Set Control Line State\r\n"); p_cdc->user_control_cb = complete_cb; TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, complete_cb ? cdch_internal_control_complete : NULL, user_data)); @@ -974,7 +975,7 @@ static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate); - TU_LOG_CDCH("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\n", baudrate, divisor); + TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\n", baudrate, divisor); p_cdc->user_control_cb = complete_cb; _ftdi_requested_baud = baudrate; @@ -1061,7 +1062,7 @@ static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY(p_cdc); - TU_LOG_CDCH("CP210x opened\r\n"); + TU_LOG_DRV("CP210x opened\r\n"); p_cdc->serial_drid = SERIAL_DRIVER_CP210X; // endpoint pair @@ -1109,7 +1110,7 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe } static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG_CDCH("CDC CP210x Set BaudRate = %lu\n", baudrate); + TU_LOG_DRV("CDC CP210x Set BaudRate = %lu\n", baudrate); uint32_t baud_le = tu_htole32(baudrate); p_cdc->user_control_cb = complete_cb; return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, @@ -1118,7 +1119,7 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_ static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG_CDCH("CDC CP210x Set Control Line State\r\n"); + TU_LOG_DRV("CDC CP210x Set Control Line State\r\n"); p_cdc->user_control_cb = complete_cb; return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, complete_cb ? cdch_internal_control_complete : NULL, user_data); diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index d95d3ef35..3a491937a 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -33,6 +33,10 @@ #include "hid_host.h" +// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message +#define HIDH_DEBUG 2 +#define TU_LOG_DRV(...) TU_LOG(HIDH_DEBUG, __VA_ARGS__) + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ @@ -207,7 +211,7 @@ static void set_protocol_complete(tuh_xfer_t* xfer) static bool _hidh_set_protocol(uint8_t daddr, uint8_t itf_num, uint8_t protocol, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG2("HID Set Protocol = %d\r\n", protocol); + TU_LOG_DRV("HID Set Protocol = %d\r\n", protocol); tusb_control_request_t const request = { @@ -246,7 +250,7 @@ bool tuh_hid_set_protocol(uint8_t daddr, uint8_t idx, uint8_t protocol) static void set_report_complete(tuh_xfer_t* xfer) { - TU_LOG2("HID Set Report complete\r\n"); + TU_LOG_DRV("HID Set Report complete\r\n"); if (tuh_hid_set_report_complete_cb) { @@ -266,7 +270,7 @@ bool tuh_hid_set_report(uint8_t daddr, uint8_t idx, uint8_t report_id, uint8_t r hidh_interface_t* p_hid = get_hid_itf(daddr, idx); TU_VERIFY(p_hid); - TU_LOG2("HID Set Report: id = %u, type = %u, len = %u\r\n", report_id, report_type, len); + TU_LOG_DRV("HID Set Report: id = %u, type = %u, len = %u\r\n", report_id, report_type, len); tusb_control_request_t const request = { @@ -298,7 +302,7 @@ bool tuh_hid_set_report(uint8_t daddr, uint8_t idx, uint8_t report_id, uint8_t r static bool _hidh_set_idle(uint8_t daddr, uint8_t itf_num, uint16_t idle_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // SET IDLE request, device can stall if not support this request - TU_LOG2("HID Set Idle \r\n"); + TU_LOG_DRV("HID Set Idle \r\n"); tusb_control_request_t const request = { @@ -367,7 +371,7 @@ bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx) bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len) { - TU_LOG2("HID Send Report %d\r\n", report_id); + TU_LOG_DRV("HID Send Report %d\r\n", report_id); hidh_interface_t* p_hid = get_hid_itf(daddr, idx); TU_VERIFY(p_hid); @@ -430,7 +434,7 @@ bool hidh_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t if ( dir == TUSB_DIR_IN ) { - TU_LOG2(" Get Report callback (%u, %u)\r\n", daddr, idx); + TU_LOG_DRV(" Get Report callback (%u, %u)\r\n", daddr, idx); TU_LOG3_MEM(p_hid->epin_buf, xferred_bytes, 2); tuh_hid_report_received_cb(daddr, idx, p_hid->epin_buf, (uint16_t) xferred_bytes); }else @@ -448,8 +452,9 @@ void hidh_close(uint8_t daddr) hidh_interface_t* p_hid = &_hidh_itf[i]; if (p_hid->daddr == daddr) { - if(tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i); - p_hid->daddr = 0; + TU_LOG_DRV(" HIDh close addr = %u index = %u\r\n", daddr, i); + if(tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i); + p_hid->daddr = 0; } } } @@ -465,7 +470,7 @@ bool hidh_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *desc_ TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass); - TU_LOG2("[%u] HID opening Interface %u\r\n", daddr, desc_itf->bInterfaceNumber); + TU_LOG_DRV("[%u] HID opening Interface %u\r\n", daddr, desc_itf->bInterfaceNumber); // len = interface + hid + n*endpoints uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + @@ -592,7 +597,7 @@ static void process_set_config(tuh_xfer_t* xfer) // using usbh enumeration buffer since report descriptor can be very long if( p_hid->report_desc_len > CFG_TUH_ENUMERATION_BUFSIZE ) { - TU_LOG2("HID Skip Report Descriptor since it is too large %u bytes\r\n", p_hid->report_desc_len); + TU_LOG_DRV("HID Skip Report Descriptor since it is too large %u bytes\r\n", p_hid->report_desc_len); // Driver is mounted without report descriptor config_driver_mount_complete(daddr, idx, NULL, 0); @@ -763,7 +768,7 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr, for ( uint8_t i = 0; i < report_num; i++ ) { info = report_info_arr+i; - TU_LOG2("%u: id = %u, usage_page = %u, usage = %u\r\n", i, info->report_id, info->usage_page, info->usage); + TU_LOG_DRV("%u: id = %u, usage_page = %u, usage = %u\r\n", i, info->report_id, info->usage_page, info->usage); } return report_num; diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c index 1b48813ec..138443de4 100644 --- a/src/class/msc/msc_host.c +++ b/src/class/msc/msc_host.c @@ -35,7 +35,6 @@ // Debug level, TUSB_CFG_DEBUG must be at least this level for debug message #define MSCH_DEBUG 2 - #define TU_LOG_MSCH(...) TU_LOG(MSCH_DEBUG, __VA_ARGS__) //--------------------------------------------------------------------+ @@ -82,6 +81,7 @@ CFG_TUH_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX]; CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static uint8_t _msch_buffer[sizeof(scsi_inquiry_resp_t)]; +// FIXME potential nul reference TU_ATTR_ALWAYS_INLINE static inline msch_interface_t* get_itf(uint8_t dev_addr) { @@ -305,11 +305,15 @@ void msch_init(void) void msch_close(uint8_t dev_addr) { TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, ); - msch_interface_t* p_msc = get_itf(dev_addr); + TU_VERIFY(p_msc->configured, ); + + TU_LOG_MSCH(" MSCh close addr = %d\r\n", dev_addr); // invoke Application Callback - if (p_msc->mounted && tuh_msc_umount_cb) tuh_msc_umount_cb(dev_addr); + if (p_msc->mounted) { + if(tuh_msc_umount_cb) tuh_msc_umount_cb(dev_addr); + } tu_memclr(p_msc, sizeof(msch_interface_t)); } diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h index 82f682043..36507041f 100644 --- a/src/common/tusb_debug.h +++ b/src/common/tusb_debug.h @@ -46,6 +46,7 @@ #if CFG_TUSB_DEBUG >= 2 extern char const* const tu_str_speed[]; extern char const* const tu_str_std_request[]; +extern char const* const tu_str_xfer_result[]; #endif void tu_print_mem(void const *buf, uint32_t count, uint8_t indent); diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index ea8eef285..2afe967b5 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -32,7 +32,10 @@ #include "tusb.h" #include "device/usbd_pvt.h" -#if CFG_TUSB_DEBUG >= 2 +// Debug level of USBD Control +#define USBD_CONTROL_DEBUG 2 + +#if CFG_TUSB_DEBUG >= USBD_CONTROL_DEBUG extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback); #endif @@ -188,7 +191,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result { TU_VERIFY(_ctrl_xfer.buffer); memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes); - TU_LOG_MEM(2, _usbd_ctrl_buf, xferred_bytes, 2); + TU_LOG_MEM(USBD_CONTROL_DEBUG, _usbd_ctrl_buf, xferred_bytes, 2); } _ctrl_xfer.total_xferred += (uint16_t) xferred_bytes; @@ -205,7 +208,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result // callback can still stall control in status phase e.g out data does not make sense if ( _ctrl_xfer.complete_cb ) { - #if CFG_TUSB_DEBUG >= 2 + #if CFG_TUSB_DEBUG >= USBD_CONTROL_DEBUG usbd_driver_print_control_complete_name(_ctrl_xfer.complete_cb); #endif diff --git a/src/host/hub.c b/src/host/hub.c index 386ad6aae..85bf22b3e 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -33,6 +33,10 @@ #include "usbh_classdriver.h" #include "hub.h" +// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message +#define HUB_DEBUG 2 +#define TU_LOG_DRV(...) TU_LOG(HUB_DEBUG, __VA_ARGS__) + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ @@ -218,7 +222,10 @@ void hub_close(uint8_t dev_addr) TU_VERIFY(dev_addr > CFG_TUH_DEVICE_MAX, ); hub_interface_t* p_hub = get_itf(dev_addr); - if (p_hub->ep_in) tu_memclr(p_hub, sizeof( hub_interface_t)); + if (p_hub->ep_in) { + TU_LOG_DRV(" HUB close addr = %d\r\n", dev_addr); + tu_memclr(p_hub, sizeof( hub_interface_t)); + } } bool hub_edpt_status_xfer(uint8_t dev_addr) diff --git a/src/host/usbh.c b/src/host/usbh.c index 24ce47a7f..4cfc7c5c2 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -61,6 +61,8 @@ typedef struct uint8_t hub_addr; uint8_t hub_port; uint8_t speed; + + // enumeration is in progress, done when all interfaces are configured volatile uint8_t enumerating; // struct TU_ATTR_PACKED { @@ -436,7 +438,8 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const ep_dir = tu_edpt_dir(ep_addr); - TU_LOG_USBH("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len); + TU_LOG_USBH("on EP %02X with %u bytes %s\r\n", ep_addr, (unsigned int) event.xfer_complete.len, + tu_str_xfer_result[event.xfer_complete.result]); if (event.dev_addr == 0) { @@ -866,6 +869,10 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) { switch (event->event_id) { +// case HCD_EVENT_DEVICE_REMOVE: +// +// break; + default: osal_queue_send(_usbh_q, event, in_isr); break; @@ -1128,30 +1135,28 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h usbh_device_t* dev = &_usbh_devices[dev_id]; uint8_t const dev_addr = dev_id+1; - // TODO Hub multiple level if (dev->rhport == rhport && (hub_addr == 0 || dev->hub_addr == hub_addr) && // hub_addr = 0 means roothub (hub_port == 0 || dev->hub_port == hub_port) && // hub_port = 0 means all devices of downstream hub dev->connected) { - TU_LOG_USBH(" Address = %u\r\n", dev_addr); + TU_LOG_USBH("Device unplugged address = %u\r\n", dev_addr); if (is_hub_addr(dev_addr)) { - TU_LOG(USBH_DEBUG, "HUB address = %u is unmounted\r\n", dev_addr); + TU_LOG(USBH_DEBUG, " is a HUB device\r\n", dev_addr); // If the device itself is a usb hub, unplug downstream devices. // FIXME un-roll recursive calls to prevent potential stack overflow process_device_unplugged(rhport, dev_addr, 0); }else { - // Invoke callback before closing driver + // Invoke callback before closing driver (maybe call it later ?) if (tuh_umount_cb) tuh_umount_cb(dev_addr); } // Close class driver for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) { - TU_LOG_USBH("%s close\r\n", usbh_class_drivers[drv_id].name); usbh_class_drivers[drv_id].close(dev_addr); } @@ -1449,6 +1454,7 @@ static uint8_t get_new_address(bool is_hub) { uint8_t start; uint8_t end; + if ( is_hub ) { start = CFG_TUH_DEVICE_MAX; @@ -1459,7 +1465,7 @@ static uint8_t get_new_address(bool is_hub) end = start + CFG_TUH_DEVICE_MAX; } - for ( uint8_t idx = start; idx < end; idx++) + for (uint8_t idx = start; idx < end; idx++) { if (!_usbh_devices[idx].connected) return (idx+1); } diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 494e2e50f..69e59ce65 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -142,8 +142,11 @@ static inline ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr); // determine if a queue head has bus-related error static inline bool qhd_has_xact_error (ehci_qhd_t * p_qhd) { - return (p_qhd->qtd_overlay.buffer_err || p_qhd->qtd_overlay.babble_err || p_qhd->qtd_overlay.xact_err); - //p_qhd->qtd_overlay.non_hs_period_missed_uframe || p_qhd->qtd_overlay.pingstate_err TODO split transaction error + volatile ehci_qtd_t *qtd_overlay = &p_qhd->qtd_overlay; + + // Error count = 0 often occurs when device disconnected + return (qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err || qtd_overlay->xact_err); + //qtd_overlay->non_hs_period_missed_uframe || qtd_overlay->pingstate_err TODO split transaction error } static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc); @@ -630,7 +633,9 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) p_qhd->total_xferred_bytes += p_qhd->p_qtd_list_head->expected_bytes - p_qhd->p_qtd_list_head->total_bytes; -// if ( XFER_RESULT_FAILED == error_event ) TU_BREAKPOINT(); // TODO skip unplugged device +// if ( XFER_RESULT_FAILED == error_event ) { +// TU_BREAKPOINT(); // TODO skip unplugged device +// } p_qhd->p_qtd_list_head->used = 0; // free QTD qtd_remove_1st_from_qhd(p_qhd); diff --git a/src/tusb.c b/src/tusb.c index 85fe5a3cc..7327db685 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -439,6 +439,10 @@ char const* const tu_str_std_request[] = "Synch Frame" }; +char const* const tu_str_xfer_result[] = { + "OK", "Failed", "Stalled", "Timeout" +}; + #endif static void dump_str_line(uint8_t const* buf, uint16_t count) -- cgit v1.3.1 From 1c4f22a54cf60e6221995f9b64e2e765fd0a5bfe Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 11 May 2023 22:18:40 +0700 Subject: EHCI: fix xfer failed with disconnected device as stalled - change CFG_TUH_ENDPOINT_MAX to 16 (max endpoint pair per device) if not defined - change QHD_MAX for EHCI, should be user configurable and more optimized in the future --- examples/host/cdc_msc_hid/src/hid_app.c | 2 +- hw/bsp/imxrt/family.c | 5 +++- src/class/hid/hid_host.c | 2 +- src/host/hcd.h | 4 ++- src/portable/ehci/ehci.c | 48 +++++++++++++-------------------- 5 files changed, 27 insertions(+), 34 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/hid_app.c b/examples/host/cdc_msc_hid/src/hid_app.c index ed53c502d..87e110ab2 100644 --- a/examples/host/cdc_msc_hid/src/hid_app.c +++ b/examples/host/cdc_msc_hid/src/hid_app.c @@ -263,7 +263,7 @@ static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t c if (!rpt_info) { - printf("Couldn't find the report info for this report !\r\n"); + printf("Couldn't find report info !\r\n"); return; } diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index 52d3bb91b..46adabf0a 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -131,7 +131,10 @@ void board_init(void) freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); } - LPUART_Init(UART_PORT, &uart_config, freq); + if ( kStatus_Success != LPUART_Init(UART_PORT, &uart_config, freq) ) { + // failed to init uart, probably baudrate is not supported + // TU_BREAKPOINT(); + } //------------- USB -------------// // Note: RT105x RT106x and later have dual USB controllers. diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 3a491937a..6abe298e5 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -72,7 +72,7 @@ tu_static hidh_interface_t _hidh_itf[CFG_TUH_HID]; TU_ATTR_ALWAYS_INLINE static inline hidh_interface_t* get_hid_itf(uint8_t daddr, uint8_t idx) { - TU_ASSERT(daddr && idx < CFG_TUH_HID, NULL); + TU_ASSERT(daddr > 0 && idx < CFG_TUH_HID, NULL); hidh_interface_t* p_hid = &_hidh_itf[idx]; return (p_hid->daddr == daddr) ? p_hid : NULL; } diff --git a/src/host/hcd.h b/src/host/hcd.h index 623c12a12..f4e76f9ef 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -39,8 +39,10 @@ // Configuration //--------------------------------------------------------------------+ +// Max number of endpoints per device +// TODO optimize memory usage #ifndef CFG_TUH_ENDPOINT_MAX - #define CFG_TUH_ENDPOINT_MAX (CFG_TUH_HUB + CFG_TUH_HID*2 + CFG_TUH_MSC*2 + CFG_TUH_CDC*3) + #define CFG_TUH_ENDPOINT_MAX 16 // #ifdef TUP_HCD_ENDPOINT_MAX // #define CFG_TUH_ENDPPOINT_MAX TUP_HCD_ENDPOINT_MAX // #else diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 69e59ce65..080ee9bbc 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -58,7 +58,8 @@ #define FRAMELIST_SIZE (1024 >> FRAMELIST_SIZE_BIT_VALUE) -#define QHD_MAX (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX) +// Total queue head pool. TODO should be user configurable and more optimize memory usage in the future +#define QHD_MAX (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX + CFG_TUH_HUB) #define QTD_MAX QHD_MAX typedef struct @@ -138,17 +139,6 @@ static inline ehci_qtd_t* qtd_control(uint8_t dev_addr) static inline ehci_qhd_t* qhd_next (ehci_qhd_t const * p_qhd); static inline ehci_qhd_t* qhd_find_free (void); static inline ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr); - -// determine if a queue head has bus-related error -static inline bool qhd_has_xact_error (ehci_qhd_t * p_qhd) -{ - volatile ehci_qtd_t *qtd_overlay = &p_qhd->qtd_overlay; - - // Error count = 0 often occurs when device disconnected - return (qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err || qtd_overlay->xact_err); - //qtd_overlay->non_hs_period_missed_uframe || qtd_overlay->pingstate_err TODO split transaction error -} - static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc); static inline ehci_qtd_t* qtd_find_free (void); @@ -392,15 +382,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const TU_ASSERT (ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS); //------------- Prepare Queue Head -------------// - ehci_qhd_t * p_qhd; - - if ( ep_desc->bEndpointAddress == 0 ) - { - p_qhd = qhd_control(dev_addr); - }else - { - p_qhd = qhd_find_free(); - } + ehci_qhd_t *p_qhd = (ep_desc->bEndpointAddress == 0) ? qhd_control(dev_addr) : qhd_find_free(); TU_ASSERT(p_qhd); qhd_init(p_qhd, dev_addr, ep_desc); @@ -622,18 +604,23 @@ static void period_list_xfer_complete_isr(uint8_t hostid, uint32_t interval_ms) static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) { - if ( (p_qhd->dev_addr != 0 && p_qhd->qtd_overlay.halted) || // addr0 cannot be protocol STALL - qhd_has_xact_error(p_qhd) ) - { - // current qhd has error in transaction - xfer_result_t error_event; + volatile ehci_qtd_t *qtd_overlay = &p_qhd->qtd_overlay; + + // TD has error + if (qtd_overlay->halted) { + xfer_result_t xfer_result; - // no error bits are set, endpoint is halted due to STALL - error_event = qhd_has_xact_error(p_qhd) ? XFER_RESULT_FAILED : XFER_RESULT_STALLED; + if (qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err || qtd_overlay->xact_err) { + // Error count = 0 often occurs when device disconnected, or other bus-related error + xfer_result = XFER_RESULT_FAILED; + }else { + // no error bits are set, endpoint is halted due to STALL + xfer_result = XFER_RESULT_STALLED; + } p_qhd->total_xferred_bytes += p_qhd->p_qtd_list_head->expected_bytes - p_qhd->p_qtd_list_head->total_bytes; -// if ( XFER_RESULT_FAILED == error_event ) { +// if (XFER_RESULT_FAILED == xfer_result ) { // TU_BREAKPOINT(); // TODO skip unplugged device // } @@ -655,7 +642,8 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) } // call USBH callback - hcd_event_xfer_complete(p_qhd->dev_addr, tu_edpt_addr(p_qhd->ep_number, p_qhd->pid == EHCI_PID_IN ? 1 : 0), p_qhd->total_xferred_bytes, error_event, true); + uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, p_qhd->pid == EHCI_PID_IN ? 1 : 0); + hcd_event_xfer_complete(p_qhd->dev_addr, ep_addr, p_qhd->total_xferred_bytes, xfer_result, true); p_qhd->total_xferred_bytes = 0; } -- cgit v1.3.1 From 2c48050993777c586210af503504e612f31228d8 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 11 May 2023 22:21:18 +0700 Subject: add various check for disconncted device, also fix #1511 un-roll recursive hub removal with usbh queue --- src/host/usbh.c | 124 +++++++++++++++++++++++++++++++++++++------------------- 1 file changed, 82 insertions(+), 42 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 4cfc7c5c2..c56ff9459 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -81,10 +81,12 @@ typedef struct { // Device State struct TU_ATTR_PACKED { - volatile uint8_t connected : 1; - volatile uint8_t addressed : 1; - volatile uint8_t configured : 1; - volatile uint8_t suspended : 1; + volatile uint8_t connected : 1; // After 1st transfer + volatile uint8_t addressed : 1; // After SET_ADDR + volatile uint8_t configured : 1; // After SET_CONFIG and all drivers are configured + volatile uint8_t suspended : 1; // Bus suspended + + // volatile uint8_t removing : 1; // Physically disconnected, waiting to be processed by usbh }; // Device Descriptor @@ -248,7 +250,7 @@ static inline usbh_device_t* get_device(uint8_t dev_addr) } static bool enum_new_device(hcd_event_t* event); -static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port); +static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port); static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size); static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); @@ -420,7 +422,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) case HCD_EVENT_DEVICE_REMOVE: TU_LOG_USBH("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port); - process_device_unplugged(event.rhport, event.connection.hub_addr, event.connection.hub_port); + process_removing_device(event.rhport, event.connection.hub_addr, event.connection.hub_port); #if CFG_TUH_HUB // TODO remove @@ -450,7 +452,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) else { usbh_device_t* dev = get_device(event.dev_addr); - TU_ASSERT(dev, ); + TU_VERIFY(dev && dev->connected, ); dev->ep_status[epnum][ep_dir].busy = 0; dev->ep_status[epnum][ep_dir].claimed = 0; @@ -739,29 +741,33 @@ void usbh_int_set(bool enabled) // TODO has some duplication code with device, refactor later bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr) { + // Note: addr0 only use tuh_control_xfer usbh_device_t* dev = get_device(dev_addr); - - // addr0 only use tuh_control_xfer - TU_ASSERT(dev); + TU_ASSERT(dev && dev->connected); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - return tu_edpt_claim(&dev->ep_status[epnum][dir], _usbh_mutex); + TU_VERIFY(tu_edpt_claim(&dev->ep_status[epnum][dir], _usbh_mutex)); + TU_LOG_USBH("[%u] Claimed EP 0x%02x\r\n", dev_addr, ep_addr); + + return true; } // TODO has some duplication code with device, refactor later bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr) { + // Note: addr0 only use tuh_control_xfer usbh_device_t* dev = get_device(dev_addr); - - // addr0 only use tuh_control_xfer - TU_ASSERT(dev); + TU_VERIFY(dev && dev->connected); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - return tu_edpt_release(&dev->ep_status[epnum][dir], _usbh_mutex); + TU_VERIFY(tu_edpt_release(&dev->ep_status[epnum][dir], _usbh_mutex)); + TU_LOG_USBH("[%u] Released EP 0x%02x\r\n", dev_addr, ep_addr); + + return true; } // TODO has some duplication code with device, refactor later @@ -870,7 +876,7 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) switch (event->event_id) { // case HCD_EVENT_DEVICE_REMOVE: -// +// // mark device as removing to prevent further xfer before the event is processed in usbh task // break; default: @@ -1116,7 +1122,7 @@ uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_i } //--------------------------------------------------------------------+ -// +// Detaching //--------------------------------------------------------------------+ TU_ATTR_ALWAYS_INLINE @@ -1125,45 +1131,79 @@ static inline bool is_hub_addr(uint8_t daddr) return (CFG_TUH_HUB > 0) && (daddr > CFG_TUH_DEVICE_MAX); } +//static void mark_removing_device_isr(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) { +// for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) { +// usbh_device_t *dev = &_usbh_devices[dev_id]; +// uint8_t const daddr = dev_id + 1; +// +// // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub +// if (dev->rhport == rhport && dev->connected && +// (hub_addr == 0 || dev->hub_addr == hub_addr) && +// (hub_port == 0 || dev->hub_port == hub_port)) { +// if (is_hub_addr(daddr)) { +// // If the device itself is a usb hub, mark all downstream devices. +// // FIXME recursive calls +// mark_removing_device_isr(rhport, daddr, 0); +// } +// +// dev->removing = 1; +// } +// } +//} + // a device unplugged from rhport:hub_addr:hub_port -static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) +static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) { //------------- find the all devices (star-network) under port that is unplugged -------------// // TODO mark as disconnected in ISR, also handle dev0 - for ( uint8_t dev_id = 0; dev_id < TU_ARRAY_SIZE(_usbh_devices); dev_id++ ) - { - usbh_device_t* dev = &_usbh_devices[dev_id]; - uint8_t const dev_addr = dev_id+1; - if (dev->rhport == rhport && - (hub_addr == 0 || dev->hub_addr == hub_addr) && // hub_addr = 0 means roothub - (hub_port == 0 || dev->hub_port == hub_port) && // hub_port = 0 means all devices of downstream hub - dev->connected) - { - TU_LOG_USBH("Device unplugged address = %u\r\n", dev_addr); +#if 0 + // index as hub addr, value is hub port (0xFF for invalid) + uint8_t removing_hubs[CFG_TUH_HUB]; + memset(removing_hubs, TUSB_INDEX_INVALID_8, sizeof(removing_hubs)); - if (is_hub_addr(dev_addr)) - { - TU_LOG(USBH_DEBUG, " is a HUB device\r\n", dev_addr); - // If the device itself is a usb hub, unplug downstream devices. - // FIXME un-roll recursive calls to prevent potential stack overflow - process_device_unplugged(rhport, dev_addr, 0); - }else - { + removing_hubs[hub_addr-CFG_TUH_DEVICE_MAX] = hub_port; + + // consecutive non-removing hub + uint8_t nop_count = 0; +#endif + + for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) { + usbh_device_t *dev = &_usbh_devices[dev_id]; + uint8_t const daddr = dev_id + 1; + + // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub + if (dev->rhport == rhport && dev->connected && + (hub_addr == 0 || dev->hub_addr == hub_addr) && + (hub_port == 0 || dev->hub_port == hub_port)) { + TU_LOG_USBH("Device unplugged address = %u\r\n", daddr); + + if (is_hub_addr(daddr)) { + TU_LOG(USBH_DEBUG, " is a HUB device\r\n", daddr); + + // Submit removed event If the device itself is a hub (un-rolled recursive) + // TODO a better to unroll recursrive is using array of removing_hubs and mark it here + hcd_event_t event; + event.rhport = rhport; + event.event_id = HCD_EVENT_DEVICE_REMOVE; + event.connection.hub_addr = daddr; + event.connection.hub_port = 0; + + hcd_event_handler(&event, false); + } else { // Invoke callback before closing driver (maybe call it later ?) - if (tuh_umount_cb) tuh_umount_cb(dev_addr); + if (tuh_umount_cb) tuh_umount_cb(daddr); } // Close class driver - for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) - { - usbh_class_drivers[drv_id].close(dev_addr); + for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) { + usbh_class_drivers[drv_id].close(daddr); } - hcd_device_close(rhport, dev_addr); + hcd_device_close(rhport, daddr); clear_device(dev); // abort on-going control xfer if any - if (_ctrl_xfer.daddr == dev_addr) _set_control_xfer_stage(CONTROL_STAGE_IDLE); + if (_ctrl_xfer.daddr == daddr) _set_control_xfer_stage(CONTROL_STAGE_IDLE); } } } -- cgit v1.3.1 From 1e998ce3bd1ecdf535a8a9feb6823627f3cf7c14 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 12 May 2023 10:58:42 +0700 Subject: usbd: fix control transfer issue for chipidea hs when previous status and new setup complete in the same isr frame change usbd edpt busy/stalled/claimed value to 0/1 instead of (true/false) since they are 1-bit field. --- .idea/runConfigurations/rt1010.xml | 10 -------- .idea/runConfigurations/rt1010_nxplink.xml | 10 ++++++++ src/device/usbd.c | 39 +++++++++++++++--------------- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 18 +++++++------- 4 files changed, 39 insertions(+), 38 deletions(-) delete mode 100644 .idea/runConfigurations/rt1010.xml create mode 100644 .idea/runConfigurations/rt1010_nxplink.xml (limited to 'src') diff --git a/.idea/runConfigurations/rt1010.xml b/.idea/runConfigurations/rt1010.xml deleted file mode 100644 index 700cb5732..000000000 --- a/.idea/runConfigurations/rt1010.xml +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - \ No newline at end of file diff --git a/.idea/runConfigurations/rt1010_nxplink.xml b/.idea/runConfigurations/rt1010_nxplink.xml new file mode 100644 index 000000000..cf3bf842f --- /dev/null +++ b/.idea/runConfigurations/rt1010_nxplink.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/src/device/usbd.c b/src/device/usbd.c index cee56af60..409a5ec10 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -516,9 +516,9 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) _usbd_dev.connected = 1; // mark both in & out control as free - _usbd_dev.ep_status[0][TUSB_DIR_OUT].busy = false; + _usbd_dev.ep_status[0][TUSB_DIR_OUT].busy = 0; _usbd_dev.ep_status[0][TUSB_DIR_OUT].claimed = 0; - _usbd_dev.ep_status[0][TUSB_DIR_IN ].busy = false; + _usbd_dev.ep_status[0][TUSB_DIR_IN ].busy = 0; _usbd_dev.ep_status[0][TUSB_DIR_IN ].claimed = 0; // Process control request @@ -540,12 +540,13 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) TU_LOG(USBD_DBG, "on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len); - _usbd_dev.ep_status[epnum][ep_dir].busy = false; + _usbd_dev.ep_status[epnum][ep_dir].busy = 0; _usbd_dev.ep_status[epnum][ep_dir].claimed = 0; if ( 0 == epnum ) { - usbd_control_xfer_cb(event.rhport, ep_addr, (xfer_result_t)event.xfer_complete.result, event.xfer_complete.len); + usbd_control_xfer_cb(event.rhport, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete + .len); } else { @@ -553,7 +554,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) TU_ASSERT(driver, ); TU_LOG(USBD_DBG, " %s xfer callback\r\n", driver->name); - driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t)event.xfer_complete.result, event.xfer_complete.len); + driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len); } } break; @@ -1244,7 +1245,7 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t // Set busy first since the actual transfer can be complete before dcd_edpt_xfer() // could return and USBD task can preempt and clear the busy - _usbd_dev.ep_status[epnum][dir].busy = true; + _usbd_dev.ep_status[epnum][dir].busy = 1; if ( dcd_edpt_xfer(rhport, ep_addr, buffer, total_bytes) ) { @@ -1252,7 +1253,7 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t }else { // DCD error, mark endpoint as ready to allow next transfer - _usbd_dev.ep_status[epnum][dir].busy = false; + _usbd_dev.ep_status[epnum][dir].busy = 0; _usbd_dev.ep_status[epnum][dir].claimed = 0; TU_LOG(USBD_DBG, "FAILED\r\n"); TU_BREAKPOINT(); @@ -1278,7 +1279,7 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 // Set busy first since the actual transfer can be complete before dcd_edpt_xfer() could return // and usbd task can preempt and clear the busy - _usbd_dev.ep_status[epnum][dir].busy = true; + _usbd_dev.ep_status[epnum][dir].busy = 1; if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes)) { @@ -1287,7 +1288,7 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 }else { // DCD error, mark endpoint as ready to allow next transfer - _usbd_dev.ep_status[epnum][dir].busy = false; + _usbd_dev.ep_status[epnum][dir].busy = 0; _usbd_dev.ep_status[epnum][dir].claimed = 0; TU_LOG(USBD_DBG, "failed\r\n"); TU_BREAKPOINT(); @@ -1317,8 +1318,8 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { TU_LOG(USBD_DBG, " Stall EP %02X\r\n", ep_addr); dcd_edpt_stall(rhport, ep_addr); - _usbd_dev.ep_status[epnum][dir].stalled = true; - _usbd_dev.ep_status[epnum][dir].busy = true; + _usbd_dev.ep_status[epnum][dir].stalled = 1; + _usbd_dev.ep_status[epnum][dir].busy = 1; } } @@ -1334,8 +1335,8 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { TU_LOG(USBD_DBG, " Clear Stall EP %02X\r\n", ep_addr); dcd_edpt_clear_stall(rhport, ep_addr); - _usbd_dev.ep_status[epnum][dir].stalled = false; - _usbd_dev.ep_status[epnum][dir].busy = false; + _usbd_dev.ep_status[epnum][dir].stalled = 0; + _usbd_dev.ep_status[epnum][dir].busy = 0; } } @@ -1366,9 +1367,9 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr) uint8_t const dir = tu_edpt_dir(ep_addr); dcd_edpt_close(rhport, ep_addr); - _usbd_dev.ep_status[epnum][dir].stalled = false; - _usbd_dev.ep_status[epnum][dir].busy = false; - _usbd_dev.ep_status[epnum][dir].claimed = false; + _usbd_dev.ep_status[epnum][dir].stalled = 0; + _usbd_dev.ep_status[epnum][dir].busy = 0; + _usbd_dev.ep_status[epnum][dir].claimed = 0; return; } @@ -1403,9 +1404,9 @@ bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep TU_ASSERT(epnum < CFG_TUD_ENDPPOINT_MAX); TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed)); - _usbd_dev.ep_status[epnum][dir].stalled = false; - _usbd_dev.ep_status[epnum][dir].busy = false; - _usbd_dev.ep_status[epnum][dir].claimed = false; + _usbd_dev.ep_status[epnum][dir].stalled = 0; + _usbd_dev.ep_status[epnum][dir].busy = 0; + _usbd_dev.ep_status[epnum][dir].claimed = 0; return dcd_edpt_iso_activate(rhport, desc_ep); } diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index bc6736cf2..9be79a2f1 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -616,15 +616,6 @@ void dcd_int_handler(uint8_t rhport) uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE; dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge - if (dcd_reg->ENDPTSETUPSTAT) - { - //------------- Set up Received -------------// - // 23.10.10.2 Operational model for setup transfers - dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT; - - dcd_event_setup_received(rhport, (uint8_t*)(uintptr_t) &_dcd_data.qhd[0][0].setup_request, true); - } - // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set // nothing to do, we will submit xfer as error to usbd // if (int_status & INTR_ERROR) { } @@ -637,6 +628,15 @@ void dcd_int_handler(uint8_t rhport) if ( tu_bit_test(edpt_complete, epnum+16) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_IN); } } + + // Set up Received + // 23.10.10.2 Operational model for setup transfers + // Must be after normal transfer complete since it is possible to have both previous control status + new setup + // in the same frame and we should handle previous status first. + if (dcd_reg->ENDPTSETUPSTAT) { + dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT; + dcd_event_setup_received(rhport, (uint8_t *) (uintptr_t) &_dcd_data.qhd[0][0].setup_request, true); + } } if (int_status & INTR_SOF) -- cgit v1.3.1 From a9aa0e3a1a9323df16c91d7705aad480033f962a Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 13 May 2023 13:20:09 +0700 Subject: fix error on EHCI causes xfer error in non-queued qhd which cause memory fault --- .idea/cmake.xml | 2 + .../dual/host_hid_to_device_cdc/src/tusb_config.h | 6 +-- src/portable/ehci/ehci.c | 46 ++++++++++++++++------ src/portable/ehci/ehci.h | 2 +- 4 files changed, 37 insertions(+), 19 deletions(-) (limited to 'src') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index bbef86164..7dacd0003 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -2,6 +2,7 @@ + @@ -27,6 +28,7 @@ + \ No newline at end of file diff --git a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h index 2185cd1f1..8133ed418 100644 --- a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h +++ b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h @@ -84,10 +84,6 @@ #define CFG_TUH_RPI_PIO_USB 1 #endif - -// CFG_TUSB_DEBUG is defined by compiler in DEBUG build -// #define CFG_TUSB_DEBUG 0 - /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. * Tinyusb use follows macros to declare transferring memory so that they can be put * into those specific section. @@ -133,7 +129,7 @@ #endif #ifndef CFG_TUH_MEM_ALIGN -#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4))) +#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4))) #endif #define CFG_TUH_HUB 1 diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 080ee9bbc..8203b0f06 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -93,16 +93,30 @@ CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data; // Debug //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= EHCI_DBG -static inline void print_portsc(ehci_registers_t* regs) -{ +static inline void print_portsc(ehci_registers_t* regs) { TU_LOG_HEX(EHCI_DBG, regs->portsc); - TU_LOG(EHCI_DBG, " Current Connect Status: %u\r\n", regs->portsc_bm.current_connect_status); - TU_LOG(EHCI_DBG, " Connect Status Change : %u\r\n", regs->portsc_bm.connect_status_change); - TU_LOG(EHCI_DBG, " Port Enabled : %u\r\n", regs->portsc_bm.port_enabled); - TU_LOG(EHCI_DBG, " Port Enabled Change : %u\r\n", regs->portsc_bm.port_enable_change); - - TU_LOG(EHCI_DBG, " Port Reset : %u\r\n", regs->portsc_bm.port_reset); - TU_LOG(EHCI_DBG, " Port Power : %u\r\n", regs->portsc_bm.port_power); + TU_LOG(EHCI_DBG, " Connect Status : %u\r\n", regs->portsc_bm.current_connect_status); + TU_LOG(EHCI_DBG, " Connect Change : %u\r\n", regs->portsc_bm.connect_status_change); + TU_LOG(EHCI_DBG, " Enabled : %u\r\n", regs->portsc_bm.port_enabled); + TU_LOG(EHCI_DBG, " Enabled Change : %u\r\n", regs->portsc_bm.port_enable_change); + + TU_LOG(EHCI_DBG, " OverCurr Change: %u\r\n", regs->portsc_bm.over_current_change); + TU_LOG(EHCI_DBG, " Force Resume : %u\r\n", regs->portsc_bm.force_port_resume); + TU_LOG(EHCI_DBG, " Suspend : %u\r\n", regs->portsc_bm.suspend); + TU_LOG(EHCI_DBG, " Reset : %u\r\n", regs->portsc_bm.port_reset); + TU_LOG(EHCI_DBG, " Power : %u\r\n", regs->portsc_bm.port_power); +} + +static inline void print_intr(uint32_t intr) { + TU_LOG_HEX(EHCI_DBG, intr); + TU_LOG(EHCI_DBG, " USB Interrupt : %u\r\n", (intr & EHCI_INT_MASK_USB) ? 1 : 0); + TU_LOG(EHCI_DBG, " USB Error : %u\r\n", (intr & EHCI_INT_MASK_ERROR) ? 1 : 0); + TU_LOG(EHCI_DBG, " Port Change Detect : %u\r\n", (intr & EHCI_INT_MASK_PORT_CHANGE) ? 1 : 0); + TU_LOG(EHCI_DBG, " Frame List Rollover: %u\r\n", (intr & EHCI_INT_MASK_FRAMELIST_ROLLOVER) ? 1 : 0); + TU_LOG(EHCI_DBG, " Host System Error : %u\r\n", (intr & EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR) ? 1 : 0); + TU_LOG(EHCI_DBG, " Async Advance : %u\r\n", (intr & EHCI_INT_MASK_ASYNC_ADVANCE) ? 1 : 0); +// TU_LOG(EHCI_DBG, " Interrupt on Async: %u\r\n", (intr & EHCI_INT_MASK_NXP_ASYNC)); +// TU_LOG(EHCI_DBG, " Periodic Schedule : %u\r\n", (intr & EHCI_INT_MASK_NXP_PERIODIC)); } #else @@ -166,8 +180,8 @@ void hcd_port_reset(uint8_t rhport) ehci_registers_t* regs = ehci_data.regs; - // mask out all change bits since they are Write 1 to clear - uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL; + // mask out Write-1-to-Clear bits + uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_W1C; // EHCI Table 2-16 PortSC // when software writes Port Reset bit to a one, it must also write a zero to the Port Enable bit. @@ -347,7 +361,7 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) // Power Control (PPC) field in the HCSPARAMS register. if (ehci_data.cap_regs->hcsparams_bm.port_power_control) { // mask out all change bits since they are Write 1 to clear - uint32_t portsc = (regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL); + uint32_t portsc = (regs->portsc & ~EHCI_PORTSC_MASK_W1C); portsc |= ECHI_PORTSC_MASK_PORT_POWER; regs->portsc = portsc; @@ -621,9 +635,14 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) p_qhd->total_xferred_bytes += p_qhd->p_qtd_list_head->expected_bytes - p_qhd->p_qtd_list_head->total_bytes; // if (XFER_RESULT_FAILED == xfer_result ) { +// TU_LOG1(" QHD xfer err count: %d\n", qtd_overlay->err_count); // TU_BREAKPOINT(); // TODO skip unplugged device +// while(1){} // } + // No TD, probably an signal noise ? + TU_VERIFY(p_qhd->p_qtd_list_head, ); + p_qhd->p_qtd_list_head->used = 0; // free QTD qtd_remove_1st_from_qhd(p_qhd); @@ -710,7 +729,8 @@ void hcd_int_handler(uint8_t rhport) if (int_status & EHCI_INT_MASK_PORT_CHANGE) { - uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_CHANGE_ALL; + // Including: Force port resume, over-current change, enable/disable change and connect status change. + uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_W1C; print_portsc(regs); if (regs->portsc_bm.connect_status_change) diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h index dd090cb36..a73e43707 100644 --- a/src/portable/ehci/ehci.h +++ b/src/portable/ehci/ehci.h @@ -306,7 +306,7 @@ enum { EHCI_PORTSC_MASK_PORT_RESET = TU_BIT(8), ECHI_PORTSC_MASK_PORT_POWER = TU_BIT(12), - EHCI_PORTSC_MASK_CHANGE_ALL = + EHCI_PORTSC_MASK_W1C = EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE | EHCI_PORTSC_MASK_PORT_ENABLE_CHANGE | EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE -- cgit v1.3.1 From eb89df411540cb8cf5323991516a45590fa0b81d Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 17 May 2023 16:14:35 +0700 Subject: adding hcd_dcache_clean/hcd_dcache_invalidate --- hw/bsp/imxrt/family.cmake | 15 +++++++++++++++ src/host/hcd.h | 10 ++++++++++ src/portable/chipidea/ci_hs/hcd_ci_hs.c | 9 +++++++++ src/portable/ehci/ehci.h | 7 +++++++ 4 files changed, 41 insertions(+) (limited to 'src') diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 77ac05c87..4628abc34 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -144,6 +144,21 @@ function(family_configure_target TARGET) COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $ ) + # Flash using jlink + set(JLINKEXE JLinkExe) + file(GENERATE + OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink + CONTENT "halt +loadfile $ +r +go +exit" + ) + add_custom_target(${TARGET}-jlink + DEPENDS ${TARGET} + COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if swd -JTAGConf -1,-1 -speed auto -CommandFile ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink + ) + endfunction() diff --git a/src/host/hcd.h b/src/host/hcd.h index f4e76f9ef..38c89a1d2 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -104,6 +104,16 @@ typedef struct uint8_t speed; } hcd_devtree_info_t; +//--------------------------------------------------------------------+ +// Memory API +//--------------------------------------------------------------------+ + +// clean/flush data cache: write cache -> memory +void hcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK; + +// invalidate data cache: mark cache as invalid, next read will read from memory +void hcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; + //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index b06633f30..56ca01f85 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -41,6 +41,15 @@ #if CFG_TUSB_MCU == OPT_MCU_MIMXRT #include "ci_hs_imxrt.h" + + void hcd_dcache_clean(void* addr, uint32_t data_size) { + SCB_CleanDCache_by_Addr((uint32_t*) addr, (int32_t) data_size); + } + + void hcd_dcache_invalidate(void* addr, uint32_t data_size) { + SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size); + } + #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) #include "ci_hs_lpc18_43.h" #else diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h index a73e43707..56befd306 100644 --- a/src/portable/ehci/ehci.h +++ b/src/portable/ehci/ehci.h @@ -268,6 +268,7 @@ TU_VERIFY_STATIC( sizeof(ehci_sitd_t) == 32, "size is not correct" ); // EHCI Operational Register //--------------------------------------------------------------------+ enum { + // Bit 0-5 has maskable in interrupt enabled register EHCI_INT_MASK_USB = TU_BIT(0), EHCI_INT_MASK_ERROR = TU_BIT(1), EHCI_INT_MASK_PORT_CHANGE = TU_BIT(2), @@ -276,6 +277,12 @@ enum { EHCI_INT_MASK_ASYNC_ADVANCE = TU_BIT(5), EHCI_INT_MASK_NXP_SOF = TU_BIT(7), + + EHCI_INT_MASK_HC_HALTED = TU_BIT(12), + EHCI_INT_MASK_RECLAIMATION = TU_BIT(13), + EHCI_INT_MASK_PERIODIC_SCHED_STATUS = TU_BIT(14), + EHCI_INT_MASK_ASYNC_SCHED_STATUS = TU_BIT(15), + EHCI_INT_MASK_NXP_ASYNC = TU_BIT(18), EHCI_INT_MASK_NXP_PERIODIC = TU_BIT(19), -- cgit v1.3.1 From 32f9f452afc4d431d51cb16a02f99d76c88f7fb9 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 17 May 2023 12:13:25 +0200 Subject: renesas: provide default for CFG_TUSB_RHPORT1_MODE Should fix CI failure for Renesas RX family --- src/portable/renesas/rusb2/dcd_rusb2.c | 1 + src/portable/renesas/rusb2/hcd_rusb2.c | 1 + src/portable/renesas/rusb2/rusb2_ra.h | 1 + 3 files changed, 3 insertions(+) (limited to 'src') diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index f509dcc56..2653d0da6 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -40,6 +40,7 @@ #if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) // fallback #define CFG_TUSB_RHPORT0_MODE OPT_MODE_DEVICE +#define CFG_TUSB_RHPORT1_MODE 0 #endif #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 1ec25f1e2..1e26c931d 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -36,6 +36,7 @@ #if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) // fallback #define CFG_TUSB_RHPORT0_MODE OPT_MODE_HOST +#define CFG_TUSB_RHPORT1_MODE 0 #endif #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 874492304..a1c58abe5 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -40,6 +40,7 @@ extern IRQn_Type _usb_hs_irqn; #if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) // fallback #define CFG_TUSB_RHPORT0_MODE ( CFG_TUD_ENABLED ? OPT_MODE_DEVICE : OPT_MODE_HOST ) +#define CFG_TUSB_RHPORT1_MODE 0 #endif TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) -- cgit v1.3.1 From a3e017bfd2923dcb1ce86d395606a24e2285e54a Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 18 May 2023 10:04:48 +0700 Subject: EHCI adding dcahe support, passing enumertaion --- src/host/hcd.h | 10 +- src/portable/chipidea/ci_hs/hcd_ci_hs.c | 4 + src/portable/ehci/ehci.c | 167 ++++++++++++++++++++------------ src/portable/ehci/ehci.h | 1 + 4 files changed, 117 insertions(+), 65 deletions(-) (limited to 'src') diff --git a/src/host/hcd.h b/src/host/hcd.h index 38c89a1d2..c6fde2adc 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -108,12 +108,18 @@ typedef struct // Memory API //--------------------------------------------------------------------+ -// clean/flush data cache: write cache -> memory +// clean/flush data cache: write cache -> memory. +// Required before an DMA TX transfer to make sure data is in memory void hcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK; // invalidate data cache: mark cache as invalid, next read will read from memory +// Required BOTH before and after an DMA RX transfer void hcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; +// clean and invalidate data cache +// Required before an DMA transfer where memory is both read/write by DMA +void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; + //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ @@ -194,6 +200,7 @@ void hcd_event_device_attach(uint8_t rhport, bool in_isr) event.event_id = HCD_EVENT_DEVICE_ATTACH; event.connection.hub_addr = 0; event.connection.hub_port = 0; + hcd_event_handler(&event, in_isr); } @@ -224,7 +231,6 @@ void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred event.xfer_complete.result = result; event.xfer_complete.len = xferred_bytes; - hcd_event_handler(&event, in_isr); } diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index 56ca01f85..ecb1a621c 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -50,6 +50,10 @@ SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size); } +void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { + SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size); + } + #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) #include "ci_hs_lpc18_43.h" #else diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 8203b0f06..9023e4b35 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -92,7 +92,7 @@ CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data; //--------------------------------------------------------------------+ // Debug //--------------------------------------------------------------------+ -#if CFG_TUSB_DEBUG >= EHCI_DBG +#if CFG_TUSB_DEBUG >= (EHCI_DBG + 1) static inline void print_portsc(ehci_registers_t* regs) { TU_LOG_HEX(EHCI_DBG, regs->portsc); TU_LOG(EHCI_DBG, " Connect Status : %u\r\n", regs->portsc_bm.current_connect_status); @@ -159,7 +159,7 @@ static inline ehci_qtd_t* qtd_find_free (void); static inline ehci_qtd_t* qtd_next (ehci_qtd_t const * p_qtd); static inline void qtd_insert_to_qhd (ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new); static inline void qtd_remove_1st_from_qhd (ehci_qhd_t *p_qhd); -static void qtd_init (ehci_qtd_t* p_qtd, void const* buffer, uint16_t total_bytes); +static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes); static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type); static inline ehci_link_t* list_next (ehci_link_t *p_link_pointer); @@ -325,28 +325,27 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) // 3 --> period_head_arr[3] (8ms) // TODO EHCI_FRAMELIST_SIZE with other size than 8 - for(uint32_t i=0; iterminate = 1; regs->periodic_list_base = (uint32_t) framelist; + if(hcd_dcache_clean) { + hcd_dcache_clean(&ehci_data, sizeof(ehci_data_t)); + } + //------------- TT Control (NXP only) -------------// regs->nxp_tt_control = 0; @@ -430,6 +429,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const // TODO might need to disable async/period list list_insert(list_head, (ehci_link_t*) p_qhd, EHCI_QTYPE_QHD); + if(hcd_dcache_clean) { + hcd_dcache_clean(p_qhd, sizeof(ehci_qhd_t)); + hcd_dcache_clean(list_head, sizeof(ehci_link_t)); + } + return true; } @@ -441,9 +445,12 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet ehci_qtd_t* td = &ehci_data.control[dev_addr].qtd; qtd_init(td, setup_packet, 8); - td->pid = EHCI_PID_SETUP; - td->int_on_complete = 1; - td->next.terminate = 1; + td->pid = EHCI_PID_SETUP; + + if (hcd_dcache_clean && hcd_dcache_clean_invalidate) { + hcd_dcache_clean((void *) setup_packet, 8); + hcd_dcache_clean_invalidate(td, sizeof(ehci_qtd_t)); + } // sw region qhd->p_qtd_list_head = td; @@ -452,6 +459,10 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet // attach TD qhd->qtd_overlay.next.address = (uint32_t) td; + if (hcd_dcache_clean_invalidate) { + hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); + } + return true; } @@ -462,41 +473,48 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); + ehci_qhd_t* qhd; + ehci_qtd_t* qtd; + if ( epnum == 0 ) { - ehci_qhd_t* qhd = qhd_control(dev_addr); - ehci_qtd_t* qtd = qtd_control(dev_addr); + qhd = qhd_control(dev_addr); + qtd = qtd_control(dev_addr); qtd_init(qtd, buffer, buflen); // first first data toggle is always 1 (data & setup stage) qtd->data_toggle = 1; qtd->pid = dir ? EHCI_PID_IN : EHCI_PID_OUT; - qtd->int_on_complete = 1; - qtd->next.terminate = 1; - - // sw region - qhd->p_qtd_list_head = qtd; - qhd->p_qtd_list_tail = qtd; - - // attach TD - qhd->qtd_overlay.next.address = (uint32_t) qtd; }else { - ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr); - ehci_qtd_t *p_qtd = qtd_find_free(); - TU_ASSERT(p_qtd); + qhd = qhd_get_from_addr(dev_addr, ep_addr); + qtd = qtd_find_free(); + TU_ASSERT(qtd); + + qtd_init(qtd, buffer, buflen); + qtd->pid = qhd->pid; + } - qtd_init(p_qtd, buffer, buflen); - p_qtd->pid = p_qhd->pid; + if (hcd_dcache_clean && hcd_dcache_clean_invalidate) { + // IN transfer: invalidate buffer, OUT transfer: clean buffer + if (dir) { + hcd_dcache_invalidate(buffer, buflen); + }else { + hcd_dcache_clean(buffer, buflen); + } + hcd_dcache_clean_invalidate(qtd, sizeof(ehci_qtd_t)); + } - // Insert TD to QH - qtd_insert_to_qhd(p_qhd, p_qtd); + // Software: assign TD to QHD + qhd->p_qtd_list_head = qtd; + qhd->p_qtd_list_tail = qtd; - p_qhd->p_qtd_list_tail->int_on_complete = 1; + // attach TD to QHD start transferring + qhd->qtd_overlay.next.address = (uint32_t) qtd; - // attach head QTD to QHD start transferring - p_qhd->qtd_overlay.next.address = (uint32_t) p_qhd->p_qtd_list_head; + if (hcd_dcache_clean_invalidate) { + hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); } return true; @@ -551,6 +569,11 @@ static void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd) while(p_qhd->p_qtd_list_head != NULL && !p_qhd->p_qtd_list_head->active) { ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_qtd_list_head; + + if (hcd_dcache_invalidate) { + hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); + } + bool const is_ioc = (qtd->int_on_complete != 0); uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, qtd->pid == EHCI_PID_IN ? 1 : 0); @@ -573,8 +596,12 @@ static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head) ehci_qhd_t *p_qhd = async_head; do { - if ( !p_qhd->qtd_overlay.halted ) // halted or error is processed in error isr - { + if (hcd_dcache_invalidate) { + hcd_dcache_invalidate(p_qhd, sizeof(ehci_qhd_t)); + } + + // halted or error is processed in error isr + if ( !p_qhd->qtd_overlay.halted ) { qhd_xfer_complete_isr(p_qhd); } p_qhd = qhd_next(p_qhd); @@ -640,8 +667,8 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) // while(1){} // } - // No TD, probably an signal noise ? - TU_VERIFY(p_qhd->p_qtd_list_head, ); + // No TD yet, it is probably the probably an signal noise ? + TU_ASSERT(p_qhd->p_qtd_list_head, ); p_qhd->p_qtd_list_head->used = 0; // free QTD qtd_remove_1st_from_qhd(p_qhd); @@ -714,17 +741,19 @@ static void xfer_error_isr(uint8_t hostid) void hcd_int_handler(uint8_t rhport) { ehci_registers_t* regs = ehci_data.regs; + uint32_t const int_status = regs->status; - uint32_t int_status = regs->status; - int_status &= regs->inten; - - regs->status = int_status; // Acknowledge handled interrupt - - if (int_status == 0) return; + if (int_status & EHCI_INT_MASK_HC_HALTED) { + // something seriously wrong, maybe forget to flush/invalidate cache + TU_BREAKPOINT(); + TU_LOG1(" HC halted\n"); + return; + } if (int_status & EHCI_INT_MASK_FRAMELIST_ROLLOVER) { ehci_data.uframe_number += (FRAMELIST_SIZE << 3); + regs->status = EHCI_INT_MASK_FRAMELIST_ROLLOVER; // Acknowledge } if (int_status & EHCI_INT_MASK_PORT_CHANGE) @@ -739,31 +768,41 @@ void hcd_int_handler(uint8_t rhport) } regs->portsc |= port_status; // Acknowledge change bits in portsc + regs->status = EHCI_INT_MASK_PORT_CHANGE; // Acknowledge } if (int_status & EHCI_INT_MASK_ERROR) { xfer_error_isr(rhport); + regs->status = EHCI_INT_MASK_ERROR; // Acknowledge } //------------- some QTD/SITD/ITD with IOC set is completed -------------// if (int_status & EHCI_INT_MASK_NXP_ASYNC) { - async_list_xfer_complete_isr( qhd_async_head(rhport) ); + async_list_xfer_complete_isr(qhd_async_head(rhport)); + regs->status = EHCI_INT_MASK_NXP_ASYNC; // Acknowledge } if (int_status & EHCI_INT_MASK_NXP_PERIODIC) { for (uint32_t i=1; i <= FRAMELIST_SIZE; i *= 2) { - period_list_xfer_complete_isr( rhport, i ); + period_list_xfer_complete_isr(rhport, i); } + regs->status = EHCI_INT_MASK_NXP_PERIODIC; // Acknowledge + } + + if (int_status & EHCI_INT_MASK_USB) { + // TODO standard EHCI xfer complete + regs->status = EHCI_INT_MASK_USB; // Acknowledge } //------------- There is some removed async previously -------------// - if (int_status & EHCI_INT_MASK_ASYNC_ADVANCE) // need to place after EHCI_INT_MASK_NXP_ASYNC - { + // need to place after EHCI_INT_MASK_NXP_ASYNC + if (int_status & EHCI_INT_MASK_ASYNC_ADVANCE) { async_advance_isr(rhport); + regs->status = EHCI_INT_MASK_ASYNC_ADVANCE; // Acknowledge } } @@ -918,28 +957,30 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c } } -static void qtd_init(ehci_qtd_t* p_qtd, void const* buffer, uint16_t total_bytes) +static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes) { - tu_memclr(p_qtd, sizeof(ehci_qtd_t)); + tu_memclr(qtd, sizeof(ehci_qtd_t)); + qtd->used = 1; - p_qtd->used = 1; + qtd->next.terminate = 1; // init to null + qtd->alternate.terminate = 1; // not used, always set to terminated + qtd->active = 1; + qtd->err_count = 3; // TODO 3 consecutive errors tolerance + qtd->data_toggle = 0; + qtd->int_on_complete = 1; + qtd->total_bytes = total_bytes; + qtd->expected_bytes = total_bytes; - p_qtd->next.terminate = 1; // init to null - p_qtd->alternate.terminate = 1; // not used, always set to terminated - p_qtd->active = 1; - p_qtd->err_count = 3; // TODO 3 consecutive errors tolerance - p_qtd->data_toggle = 0; - p_qtd->total_bytes = total_bytes; - p_qtd->expected_bytes = total_bytes; - - p_qtd->buffer[0] = (uint32_t) buffer; + qtd->buffer[0] = (uint32_t) buffer; for(uint8_t i=1; i<5; i++) { - p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096; + qtd->buffer[i] |= tu_align4k(qtd->buffer[i - 1] ) + 4096; } } //------------- List Managing Helper -------------// + +// insert at head static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type) { new->address = current->address; diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h index 56befd306..e76a59401 100644 --- a/src/portable/ehci/ehci.h +++ b/src/portable/ehci/ehci.h @@ -165,6 +165,7 @@ typedef struct TU_ATTR_ALIGNED(32) uint16_t total_xferred_bytes; // number of bytes xferred until a qtd with ioc bit set uint8_t reserved2[2]; + // TODO USBH will only queue 1 TD per QHD, thus we can remove the list ehci_qtd_t * volatile p_qtd_list_head; // head of the scheduled TD list ehci_qtd_t * volatile p_qtd_list_tail; // tail of the scheduled TD list } ehci_qhd_t; -- cgit v1.3.1 From e4f4ad5bc3a24f619b9cf6c542aaa3ff8cb37ec4 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 18 May 2023 10:21:11 +0700 Subject: use weak local for dcache function to skip if() --- src/portable/ehci/ehci.c | 65 +++++++++++++++++++++++++----------------------- 1 file changed, 34 insertions(+), 31 deletions(-) (limited to 'src') diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 9023e4b35..ac715aa60 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -164,6 +164,25 @@ static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes) static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type); static inline ehci_link_t* list_next (ehci_link_t *p_link_pointer); +TU_ATTR_WEAK void hcd_dcache_clean(void* addr, uint32_t data_size) { + (void) addr; + (void) data_size; +} + +// invalidate data cache: mark cache as invalid, next read will read from memory +// Required BOTH before and after an DMA RX transfer +TU_ATTR_WEAK void hcd_dcache_invalidate(void* addr, uint32_t data_size) { + (void) addr; + (void) data_size; +} + +// clean and invalidate data cache +// Required before an DMA transfer where memory is both read/write by DMA +TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { + (void) addr; + (void) data_size; +} + //--------------------------------------------------------------------+ // HCD API //--------------------------------------------------------------------+ @@ -342,9 +361,7 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) regs->periodic_list_base = (uint32_t) framelist; - if(hcd_dcache_clean) { - hcd_dcache_clean(&ehci_data, sizeof(ehci_data_t)); - } + hcd_dcache_clean(&ehci_data, sizeof(ehci_data_t)); //------------- TT Control (NXP only) -------------// regs->nxp_tt_control = 0; @@ -429,10 +446,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const // TODO might need to disable async/period list list_insert(list_head, (ehci_link_t*) p_qhd, EHCI_QTYPE_QHD); - if(hcd_dcache_clean) { - hcd_dcache_clean(p_qhd, sizeof(ehci_qhd_t)); - hcd_dcache_clean(list_head, sizeof(ehci_link_t)); - } + hcd_dcache_clean(p_qhd, sizeof(ehci_qhd_t)); + hcd_dcache_clean(list_head, sizeof(ehci_link_t)); return true; } @@ -447,10 +462,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet qtd_init(td, setup_packet, 8); td->pid = EHCI_PID_SETUP; - if (hcd_dcache_clean && hcd_dcache_clean_invalidate) { - hcd_dcache_clean((void *) setup_packet, 8); - hcd_dcache_clean_invalidate(td, sizeof(ehci_qtd_t)); - } + hcd_dcache_clean((void *) setup_packet, 8); + hcd_dcache_clean_invalidate(td, sizeof(ehci_qtd_t)); // sw region qhd->p_qtd_list_head = td; @@ -459,9 +472,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet // attach TD qhd->qtd_overlay.next.address = (uint32_t) td; - if (hcd_dcache_clean_invalidate) { - hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); - } + hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); return true; } @@ -496,15 +507,13 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * qtd->pid = qhd->pid; } - if (hcd_dcache_clean && hcd_dcache_clean_invalidate) { - // IN transfer: invalidate buffer, OUT transfer: clean buffer - if (dir) { - hcd_dcache_invalidate(buffer, buflen); - }else { - hcd_dcache_clean(buffer, buflen); - } - hcd_dcache_clean_invalidate(qtd, sizeof(ehci_qtd_t)); + // IN transfer: invalidate buffer, OUT transfer: clean buffer + if (dir) { + hcd_dcache_invalidate(buffer, buflen); + }else { + hcd_dcache_clean(buffer, buflen); } + hcd_dcache_clean_invalidate(qtd, sizeof(ehci_qtd_t)); // Software: assign TD to QHD qhd->p_qtd_list_head = qtd; @@ -513,9 +522,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * // attach TD to QHD start transferring qhd->qtd_overlay.next.address = (uint32_t) qtd; - if (hcd_dcache_clean_invalidate) { - hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); - } + hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); return true; } @@ -570,9 +577,7 @@ static void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd) { ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_qtd_list_head; - if (hcd_dcache_invalidate) { - hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); - } + hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); bool const is_ioc = (qtd->int_on_complete != 0); uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, qtd->pid == EHCI_PID_IN ? 1 : 0); @@ -596,9 +601,7 @@ static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head) ehci_qhd_t *p_qhd = async_head; do { - if (hcd_dcache_invalidate) { - hcd_dcache_invalidate(p_qhd, sizeof(ehci_qhd_t)); - } + hcd_dcache_invalidate(p_qhd, sizeof(ehci_qhd_t)); // halted or error is processed in error isr if ( !p_qhd->qtd_overlay.halted ) { -- cgit v1.3.1 From a0aea52a117246f246529459f9203ce36d2fcd81 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 18 May 2023 12:39:53 +0700 Subject: more cache, fix an similar issue with OHCI when removing an queue head --- src/portable/ehci/ehci.c | 50 ++++++++++++++++++++++++++---------------------- src/portable/ehci/ehci.h | 2 ++ 2 files changed, 29 insertions(+), 23 deletions(-) (limited to 'src') diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index ac715aa60..0b4202788 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -162,7 +162,7 @@ static inline void qtd_remove_1st_from_qhd (ehci_qhd_t *p_qhd); static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes); static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type); -static inline ehci_link_t* list_next (ehci_link_t *p_link_pointer); +static inline ehci_link_t* list_next (ehci_link_t const *p_link); TU_ATTR_WEAK void hcd_dcache_clean(void* addr, uint32_t data_size) { (void) addr; @@ -237,24 +237,22 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport) return (tusb_speed_t) ehci_data.regs->portsc_bm.nxp_port_speed; // NXP specific port speed } -static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr) -{ - for(ehci_link_t* prev = list_head; - !prev->terminate && (tu_align32(prev->address) != (uint32_t) list_head) && prev != NULL; - prev = list_next(prev) ) - { - // TODO check type for ISO iTD and siTD - // TODO Suppress cast-align warning - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wcast-align" - ehci_qhd_t* qhd = (ehci_qhd_t*) list_next(prev); - #pragma GCC diagnostic pop - if ( qhd->dev_addr == dev_addr ) - { +static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr) { + ehci_link_t* prev = list_head; + + while (prev && !prev->terminate) { + ehci_qhd_t* qhd = (ehci_qhd_t*) (uintptr_t) list_next(prev); + + // done if loop back to head + if ( (uintptr_t) qhd == (uintptr_t) list_head) { + break; + } + + if ( qhd->dev_addr == dev_addr ) { // TODO deactivate all TD, wait for QHD to inactive before removal prev->address = qhd->next.address; - // EHCI 4.8.2 link the removed qhd to async head (which always reachable by Host Controller) + // EHCI 4.8.2 link the removed qhd's next to async head (which always reachable by Host Controller) qhd->next.address = ((uint32_t) list_head) | (EHCI_QTYPE_QHD << 1); if ( qhd->int_smask ) @@ -267,6 +265,11 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr) // mark as removing, will completely re-usable when async advance isr occurs qhd->removing = 1; } + + hcd_dcache_clean(qhd, sizeof(ehci_qhd_t)); + hcd_dcache_clean(prev, sizeof(ehci_qhd_t)); + }else { + prev = list_next(prev); } } } @@ -275,15 +278,16 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr) void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { // skip dev0 - if (dev_addr == 0) return; + if (dev_addr == 0) { + return; + } // Remove from async list - list_remove_qhd_by_addr( (ehci_link_t*) qhd_async_head(rhport), dev_addr ); + list_remove_qhd_by_daddr((ehci_link_t *) qhd_async_head(rhport), dev_addr); // Remove from all interval period list - for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) - { - list_remove_qhd_by_addr( (ehci_link_t*) &ehci_data.period_head_arr[i], dev_addr); + for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) { + list_remove_qhd_by_daddr((ehci_link_t *) &ehci_data.period_head_arr[i], dev_addr); } // Async doorbell (EHCI 4.8.2 for operational details) @@ -990,9 +994,9 @@ static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t n current->address = ((uint32_t) new) | (new_type << 1); } -static inline ehci_link_t* list_next(ehci_link_t *p_link_pointer) +static inline ehci_link_t* list_next(ehci_link_t const *p_link) { - return (ehci_link_t*) tu_align32(p_link_pointer->address); + return (ehci_link_t*) tu_align32(p_link->address); } #endif diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h index e76a59401..d7d37d627 100644 --- a/src/portable/ehci/ehci.h +++ b/src/portable/ehci/ehci.h @@ -81,6 +81,8 @@ typedef union { }; }ehci_link_t; +TU_VERIFY_STATIC( sizeof(ehci_link_t) == 4, "size is not correct" ); + /// Queue Element Transfer Descriptor /// Qtd is used to declare overlay in ehci_qhd_t -> cannot be declared with TU_ATTR_ALIGNED(32) typedef struct -- cgit v1.3.1 From 49e2aabc819f761284dd490fd4f1c5d4ad5c3695 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 18 May 2023 13:45:38 +0700 Subject: EHCI more improvement - more dcache clean/invalidate - extract init_periodic_list() - improve isr list handling --- src/host/hcd.h | 2 +- src/portable/ehci/ehci.c | 196 +++++++++++++++++++++++++---------------------- 2 files changed, 105 insertions(+), 93 deletions(-) (limited to 'src') diff --git a/src/host/hcd.h b/src/host/hcd.h index c6fde2adc..5a3b0a087 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -175,7 +175,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]); // clear stall, data toggle is also reset to DATA0 -bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr); +bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr); //--------------------------------------------------------------------+ // USBH implemented API diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 0b4202788..0b45d7b93 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -294,6 +294,40 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) ehci_data.regs->command_bm.async_adv_doorbell = 1; } +static void init_periodic_list(uint8_t rhport) { + // Build the polling interval tree with 1 ms, 2 ms, 4 ms and 8 ms (framesize) only + for ( uint32_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++ ) { + ehci_data.period_head_arr[i].int_smask = 1; // queue head in period list must have smask non-zero + ehci_data.period_head_arr[i].qtd_overlay.halted = 1; // dummy node, always inactive + } + + ehci_link_t * const framelist = ehci_data.period_framelist; + ehci_link_t * const period_1ms = get_period_head(rhport, 1u); + + // all links --> period_head_arr[0] (1ms) + // 0, 2, 4, 6 etc --> period_head_arr[1] (2ms) + // 1, 5 --> period_head_arr[2] (4ms) + // 3 --> period_head_arr[3] (8ms) + + // TODO EHCI_FRAMELIST_SIZE with other size than 8 + for (uint32_t i = 0; i < FRAMELIST_SIZE; i++) { + framelist[i].address = (uint32_t) period_1ms; + framelist[i].type = EHCI_QTYPE_QHD; + } + + for (uint32_t i = 0; i < FRAMELIST_SIZE; i += 2) { + list_insert(framelist + i, get_period_head(rhport, 2u), EHCI_QTYPE_QHD); + } + + for (uint32_t i = 1; i < FRAMELIST_SIZE; i += 4) { + list_insert(framelist + i, get_period_head(rhport, 4u), EHCI_QTYPE_QHD); + } + + list_insert(framelist + 3, get_period_head(rhport, 8u), EHCI_QTYPE_QHD); + + period_1ms->terminate = 1; +} + bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) { tu_memclr(&ehci_data, sizeof(ehci_data_t)); @@ -332,38 +366,8 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) regs->async_list_addr = (uint32_t) async_head; //------------- Periodic List -------------// - // Build the polling interval tree with 1 ms, 2 ms, 4 ms and 8 ms (framesize) only - for ( uint32_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++ ) - { - ehci_data.period_head_arr[i].int_smask = 1; // queue head in period list must have smask non-zero - ehci_data.period_head_arr[i].qtd_overlay.halted = 1; // dummy node, always inactive - } - - ehci_link_t * const framelist = ehci_data.period_framelist; - ehci_link_t * const period_1ms = get_period_head(rhport, 1u); - - // all links --> period_head_arr[0] (1ms) - // 0, 2, 4, 6 etc --> period_head_arr[1] (2ms) - // 1, 5 --> period_head_arr[2] (4ms) - // 3 --> period_head_arr[3] (8ms) - - // TODO EHCI_FRAMELIST_SIZE with other size than 8 - for (uint32_t i = 0; i < FRAMELIST_SIZE; i++) { - framelist[i].address = (uint32_t) period_1ms; - framelist[i].type = EHCI_QTYPE_QHD; - } - - for (uint32_t i = 0; i < FRAMELIST_SIZE; i += 2) { - list_insert(framelist + i, get_period_head(rhport, 2u), EHCI_QTYPE_QHD); - } - - for (uint32_t i = 1; i < FRAMELIST_SIZE; i += 4) { - list_insert(framelist + i, get_period_head(rhport, 4u), EHCI_QTYPE_QHD); - } - list_insert(framelist + 3, get_period_head(rhport, 8u), EHCI_QTYPE_QHD); - period_1ms->terminate = 1; - - regs->periodic_list_base = (uint32_t) framelist; + init_periodic_list(rhport); + regs->periodic_list_base = (uint32_t) ehci_data.period_framelist; hcd_dcache_clean(&ehci_data, sizeof(ehci_data_t)); @@ -491,8 +495,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * ehci_qhd_t* qhd; ehci_qtd_t* qtd; - if ( epnum == 0 ) - { + if (epnum == 0) { qhd = qhd_control(dev_addr); qtd = qtd_control(dev_addr); @@ -501,8 +504,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * // first first data toggle is always 1 (data & setup stage) qtd->data_toggle = 1; qtd->pid = dir ? EHCI_PID_IN : EHCI_PID_OUT; - }else - { + } else { qhd = qhd_get_from_addr(dev_addr, ep_addr); qtd = qtd_find_free(); TU_ASSERT(qtd); @@ -531,10 +533,11 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * return true; } -bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) +bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr) { - ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr); - p_qhd->qtd_overlay.halted = 0; + ehci_qhd_t *qhd = qhd_get_from_addr(daddr, ep_addr); + qhd->qtd_overlay.halted = 0; + hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); // TODO reset data toggle ? return true; } @@ -546,22 +549,22 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) // async_advance is handshake between usb stack & ehci controller. // This isr mean it is safe to modify previously removed queue head from async list. // In tinyusb, queue head is only removed when device is unplugged. -static void async_advance_isr(uint8_t rhport) +TU_ATTR_ALWAYS_INLINE static inline +void async_advance_isr(uint8_t rhport) { (void) rhport; - ehci_qhd_t* qhd_pool = ehci_data.qhd_pool; - for(uint32_t i = 0; i < QHD_MAX; i++) - { - if ( qhd_pool[i].removing ) - { + ehci_qhd_t *qhd_pool = ehci_data.qhd_pool; + for (uint32_t i = 0; i < QHD_MAX; i++) { + if (qhd_pool[i].removing) { qhd_pool[i].removing = 0; - qhd_pool[i].used = 0; + qhd_pool[i].used = 0; } } } -static void port_connect_status_change_isr(uint8_t rhport) +TU_ATTR_ALWAYS_INLINE static inline +void port_connect_status_change_isr(uint8_t rhport) { // NOTE There is an sequence plug->unplug->…..-> plug if device is powering with pre-plugged device if (ehci_data.regs->portsc_bm.current_connect_status) @@ -574,13 +577,13 @@ static void port_connect_status_change_isr(uint8_t rhport) } } -static void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd) +TU_ATTR_ALWAYS_INLINE static inline +void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd) { // free all TDs from the head td to the first active TD while(p_qhd->p_qtd_list_head != NULL && !p_qhd->p_qtd_list_head->active) { ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_qtd_list_head; - hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); bool const is_ioc = (qtd->int_on_complete != 0); @@ -600,7 +603,8 @@ static void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd) } } -static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head) +TU_ATTR_ALWAYS_INLINE static inline +void async_list_xfer_complete_isr(ehci_qhd_t * const async_head) { ehci_qhd_t *p_qhd = async_head; do @@ -611,46 +615,55 @@ static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head) if ( !p_qhd->qtd_overlay.halted ) { qhd_xfer_complete_isr(p_qhd); } + p_qhd = qhd_next(p_qhd); }while(p_qhd != async_head); // async list traversal, stop if loop around } -static void period_list_xfer_complete_isr(uint8_t hostid, uint32_t interval_ms) +TU_ATTR_ALWAYS_INLINE static inline +void period_list_xfer_complete_isr(uint8_t rhport, uint32_t interval_ms) { - uint16_t max_loop = 0; - uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1u); - ehci_link_t next_item = * get_period_head(hostid, interval_ms); + uint32_t const period_1ms_addr = (uint32_t) get_period_head(rhport, 1u); + ehci_link_t next_link = * get_period_head(rhport, interval_ms); - // TODO abstract max loop guard for period - while( !next_item.terminate && - !(interval_ms > 1 && period_1ms_addr == tu_align32(next_item.address)) && - max_loop < (QHD_MAX + EHCI_MAX_ITD + EHCI_MAX_SITD)*CFG_TUH_DEVICE_MAX) - { - switch ( next_item.type ) - { - case EHCI_QTYPE_QHD: - { - ehci_qhd_t *p_qhd_int = (ehci_qhd_t *) tu_align32(next_item.address); - if ( !p_qhd_int->qtd_overlay.halted ) - { - qhd_xfer_complete_isr(p_qhd_int); + while (!next_link.terminate) { + if (interval_ms > 1 && period_1ms_addr == tu_align32(next_link.address)) { + // 1ms period list is end of list for all larger interval + break; + } + + uintptr_t const entry_addr = tu_align32(next_link.address); + + switch (next_link.type) { + case EHCI_QTYPE_QHD: { + ehci_qhd_t *qhd = (ehci_qhd_t *) entry_addr; + hcd_dcache_invalidate(qhd, sizeof(ehci_qhd_t)); + + if (!qhd->qtd_overlay.halted) { + qhd_xfer_complete_isr(qhd); } } - break; + break; + + case EHCI_QTYPE_ITD: + // TODO support hs ISO + break; - case EHCI_QTYPE_ITD: // TODO support hs/fs ISO case EHCI_QTYPE_SITD: - case EHCI_QTYPE_FSTN: + // TODO support split ISO + break; - default: break; + case EHCI_QTYPE_FSTN: + default: + break; } - next_item = *list_next(&next_item); - max_loop++; + next_link = *list_next(&next_link); } } -static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) +TU_ATTR_ALWAYS_INLINE static inline +void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) { volatile ehci_qtd_t *qtd_overlay = &p_qhd->qtd_overlay; @@ -666,22 +679,22 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) xfer_result = XFER_RESULT_STALLED; } - p_qhd->total_xferred_bytes += p_qhd->p_qtd_list_head->expected_bytes - p_qhd->p_qtd_list_head->total_bytes; - // if (XFER_RESULT_FAILED == xfer_result ) { // TU_LOG1(" QHD xfer err count: %d\n", qtd_overlay->err_count); // TU_BREAKPOINT(); // TODO skip unplugged device // while(1){} // } - // No TD yet, it is probably the probably an signal noise ? - TU_ASSERT(p_qhd->p_qtd_list_head, ); + ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_qtd_list_head; + TU_ASSERT(qtd, ); // No TD yet, probably a race condition or cache issue !? - p_qhd->p_qtd_list_head->used = 0; // free QTD + hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); + p_qhd->total_xferred_bytes += qtd->expected_bytes - qtd->total_bytes; + + qtd->used = 0; // free QTD qtd_remove_1st_from_qhd(p_qhd); - if ( 0 == p_qhd->ep_number ) - { + if ( 0 == p_qhd->ep_number ) { // control cannot be halted --> clear all qtd list p_qhd->p_qtd_list_head = NULL; p_qhd->p_qtd_list_tail = NULL; @@ -702,13 +715,15 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) } } -static void xfer_error_isr(uint8_t hostid) +TU_ATTR_ALWAYS_INLINE static inline +void xfer_error_isr(uint8_t hostid) { //------------- async list -------------// ehci_qhd_t * const async_head = qhd_async_head(hostid); ehci_qhd_t *p_qhd = async_head; do { + hcd_dcache_invalidate(p_qhd, sizeof(ehci_qhd_t)); qhd_xfer_error_isr( p_qhd ); p_qhd = qhd_next(p_qhd); }while(p_qhd != async_head); // async list traversal, stop if loop around @@ -728,6 +743,8 @@ static void xfer_error_isr(uint8_t hostid) case EHCI_QTYPE_QHD: { ehci_qhd_t *p_qhd_int = (ehci_qhd_t *) tu_align32(next_item.address); + hcd_dcache_invalidate(p_qhd_int, sizeof(ehci_qhd_t)); + qhd_xfer_error_isr(p_qhd_int); } break; @@ -757,20 +774,17 @@ void hcd_int_handler(uint8_t rhport) return; } - if (int_status & EHCI_INT_MASK_FRAMELIST_ROLLOVER) - { + if (int_status & EHCI_INT_MASK_FRAMELIST_ROLLOVER) { ehci_data.uframe_number += (FRAMELIST_SIZE << 3); regs->status = EHCI_INT_MASK_FRAMELIST_ROLLOVER; // Acknowledge } - if (int_status & EHCI_INT_MASK_PORT_CHANGE) - { + if (int_status & EHCI_INT_MASK_PORT_CHANGE) { // Including: Force port resume, over-current change, enable/disable change and connect status change. uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_W1C; print_portsc(regs); - if (regs->portsc_bm.connect_status_change) - { + if (regs->portsc_bm.connect_status_change) { port_connect_status_change_isr(rhport); } @@ -778,15 +792,13 @@ void hcd_int_handler(uint8_t rhport) regs->status = EHCI_INT_MASK_PORT_CHANGE; // Acknowledge } - if (int_status & EHCI_INT_MASK_ERROR) - { + if (int_status & EHCI_INT_MASK_ERROR) { xfer_error_isr(rhport); regs->status = EHCI_INT_MASK_ERROR; // Acknowledge } //------------- some QTD/SITD/ITD with IOC set is completed -------------// - if (int_status & EHCI_INT_MASK_NXP_ASYNC) - { + if (int_status & EHCI_INT_MASK_NXP_ASYNC) { async_list_xfer_complete_isr(qhd_async_head(rhport)); regs->status = EHCI_INT_MASK_NXP_ASYNC; // Acknowledge } -- cgit v1.3.1 From 27acaa013bd8af8ac29e966d7dc145b33dd6bc73 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 18 May 2023 15:44:08 +0700 Subject: refactor ehci, since usbh only queue 1 TD per queue head --- src/portable/ehci/ehci.c | 113 ++++++++++++++--------------------------------- src/portable/ehci/ehci.h | 16 ++----- 2 files changed, 37 insertions(+), 92 deletions(-) (limited to 'src') diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 0b45d7b93..a08731667 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -156,9 +156,6 @@ static inline ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr); static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc); static inline ehci_qtd_t* qtd_find_free (void); -static inline ehci_qtd_t* qtd_next (ehci_qtd_t const * p_qtd); -static inline void qtd_insert_to_qhd (ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new); -static inline void qtd_remove_1st_from_qhd (ehci_qhd_t *p_qhd); static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes); static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type); @@ -473,11 +470,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet hcd_dcache_clean((void *) setup_packet, 8); hcd_dcache_clean_invalidate(td, sizeof(ehci_qtd_t)); - // sw region - qhd->p_qtd_list_head = td; - qhd->p_qtd_list_tail = td; - // attach TD + qhd->p_attached_qtd = td; // software management qhd->qtd_overlay.next.address = (uint32_t) td; hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); @@ -501,7 +495,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * qtd_init(qtd, buffer, buflen); - // first first data toggle is always 1 (data & setup stage) + // first data toggle is always 1 (data & setup stage) qtd->data_toggle = 1; qtd->pid = dir ? EHCI_PID_IN : EHCI_PID_OUT; } else { @@ -521,11 +515,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * } hcd_dcache_clean_invalidate(qtd, sizeof(ehci_qtd_t)); - // Software: assign TD to QHD - qhd->p_qtd_list_head = qtd; - qhd->p_qtd_list_tail = qtd; - // attach TD to QHD start transferring + qhd->p_attached_qtd = qtd; // software management qhd->qtd_overlay.next.address = (uint32_t) qtd; hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); @@ -580,27 +571,25 @@ void port_connect_status_change_isr(uint8_t rhport) TU_ATTR_ALWAYS_INLINE static inline void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd) { - // free all TDs from the head td to the first active TD - while(p_qhd->p_qtd_list_head != NULL && !p_qhd->p_qtd_list_head->active) - { - ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_qtd_list_head; - hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); + // examine TD attached to queue head + ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_attached_qtd; + if (qtd == NULL) return; // no TD attached + hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); - bool const is_ioc = (qtd->int_on_complete != 0); - uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, qtd->pid == EHCI_PID_IN ? 1 : 0); + // TD is still active, no need to process + if (qtd->active) { + return; + } - p_qhd->total_xferred_bytes += qtd->expected_bytes - qtd->total_bytes; + uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes; + uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, qtd->pid == EHCI_PID_IN ? 1 : 0); - // TD need to be freed and removed from qhd, before invoking callback - qtd->used = 0; // free QTD - qtd_remove_1st_from_qhd(p_qhd); + // remove and free TD before invoking callback + p_qhd->p_attached_qtd = NULL; + qtd->used = 0; // free QTD - if (is_ioc) - { - hcd_event_xfer_complete(p_qhd->dev_addr, ep_addr, p_qhd->total_xferred_bytes, XFER_RESULT_SUCCESS, true); - p_qhd->total_xferred_bytes = 0; - } - } + // IOC is always set + hcd_event_xfer_complete(p_qhd->dev_addr, ep_addr, xferred_bytes, XFER_RESULT_SUCCESS, true); } TU_ATTR_ALWAYS_INLINE static inline @@ -685,20 +674,17 @@ void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) // while(1){} // } - ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_qtd_list_head; + ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_attached_qtd; TU_ASSERT(qtd, ); // No TD yet, probably a race condition or cache issue !? hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); - p_qhd->total_xferred_bytes += qtd->expected_bytes - qtd->total_bytes; + uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes; + p_qhd->p_attached_qtd = NULL; qtd->used = 0; // free QTD - qtd_remove_1st_from_qhd(p_qhd); if ( 0 == p_qhd->ep_number ) { - // control cannot be halted --> clear all qtd list - p_qhd->p_qtd_list_head = NULL; - p_qhd->p_qtd_list_tail = NULL; - + // control cannot be halted p_qhd->qtd_overlay.next.terminate = 1; p_qhd->qtd_overlay.alternate.terminate = 1; p_qhd->qtd_overlay.halted = 0; @@ -707,19 +693,17 @@ void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) p_setup->used = 0; } - // call USBH callback + // notify usbh uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, p_qhd->pid == EHCI_PID_IN ? 1 : 0); - hcd_event_xfer_complete(p_qhd->dev_addr, ep_addr, p_qhd->total_xferred_bytes, xfer_result, true); - - p_qhd->total_xferred_bytes = 0; + hcd_event_xfer_complete(p_qhd->dev_addr, ep_addr, xferred_bytes, xfer_result, true); } } TU_ATTR_ALWAYS_INLINE static inline -void xfer_error_isr(uint8_t hostid) +void xfer_error_isr(uint8_t rhport) { //------------- async list -------------// - ehci_qhd_t * const async_head = qhd_async_head(hostid); + ehci_qhd_t * const async_head = qhd_async_head(rhport); ehci_qhd_t *p_qhd = async_head; do { @@ -729,10 +713,10 @@ void xfer_error_isr(uint8_t hostid) }while(p_qhd != async_head); // async list traversal, stop if loop around //------------- TODO refractor period list -------------// - uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1u); + uint32_t const period_1ms_addr = (uint32_t) get_period_head(rhport, 1u); for (uint32_t interval_ms=1; interval_ms <= FRAMELIST_SIZE; interval_ms *= 2) { - ehci_link_t next_item = * get_period_head(hostid, interval_ms); + ehci_link_t next_item = * get_period_head(rhport, interval_ms); // TODO abstract max loop guard for period while( !next_item.terminate && @@ -873,34 +857,6 @@ static inline ehci_qtd_t* qtd_find_free(void) return NULL; } -static inline ehci_qtd_t* qtd_next(ehci_qtd_t const * p_qtd ) -{ - return (ehci_qtd_t*) tu_align32(p_qtd->next.address); -} - -static inline void qtd_remove_1st_from_qhd(ehci_qhd_t *p_qhd) -{ - if (p_qhd->p_qtd_list_head == p_qhd->p_qtd_list_tail) // last TD --> make it NULL - { - p_qhd->p_qtd_list_head = p_qhd->p_qtd_list_tail = NULL; - }else - { - p_qhd->p_qtd_list_head = qtd_next( p_qhd->p_qtd_list_head ); - } -} - -static inline void qtd_insert_to_qhd(ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new) -{ - if (p_qhd->p_qtd_list_head == NULL) // empty list - { - p_qhd->p_qtd_list_head = p_qhd->p_qtd_list_tail = p_qtd_new; - }else - { - p_qhd->p_qtd_list_tail->next.address = (uint32_t) p_qtd_new; - p_qhd->p_qtd_list_tail = p_qtd_new; - } -} - static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { // address 0 is used as async head, which always on the list --> cannot be cleared (ehci halted otherwise) @@ -955,15 +911,14 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c p_qhd->int_smask = p_qhd->fl_int_cmask = 0; } - p_qhd->fl_hub_addr = devtree_info.hub_addr; - p_qhd->fl_hub_port = devtree_info.hub_port; - p_qhd->mult = 1; // TODO not use high bandwidth/park mode yet + p_qhd->fl_hub_addr = devtree_info.hub_addr; + p_qhd->fl_hub_port = devtree_info.hub_port; + p_qhd->mult = 1; // TODO not use high bandwidth/park mode yet //------------- HCD Management Data -------------// - p_qhd->used = 1; - p_qhd->removing = 0; - p_qhd->p_qtd_list_head = NULL; - p_qhd->p_qtd_list_tail = NULL; + p_qhd->used = 1; + p_qhd->removing = 0; + p_qhd->p_attached_qtd = NULL; p_qhd->pid = tu_edpt_dir(ep_desc->bEndpointAddress) ? EHCI_PID_IN : EHCI_PID_OUT; // PID for TD under this endpoint //------------- active, but no TD list -------------// diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h index d7d37d627..b525131c6 100644 --- a/src/portable/ehci/ehci.h +++ b/src/portable/ehci/ehci.h @@ -164,12 +164,10 @@ typedef struct TU_ATTR_ALIGNED(32) uint8_t pid; uint8_t interval_ms; // polling interval in frames (or millisecond) - uint16_t total_xferred_bytes; // number of bytes xferred until a qtd with ioc bit set - uint8_t reserved2[2]; + uint8_t TU_RESERVED[8]; - // TODO USBH will only queue 1 TD per QHD, thus we can remove the list - ehci_qtd_t * volatile p_qtd_list_head; // head of the scheduled TD list - ehci_qtd_t * volatile p_qtd_list_tail; // tail of the scheduled TD list + // usbh will only queue 1 TD per QHD + ehci_qtd_t * volatile p_attached_qtd; } ehci_qhd_t; TU_VERIFY_STATIC( sizeof(ehci_qhd_t) == 64, "size is not correct" ); @@ -248,14 +246,6 @@ typedef struct TU_ATTR_ALIGNED(32) /// Word 4-5: Buffer Pointer List uint32_t buffer[2]; // buffer[1] TP: Transaction Position - T-Count: Transaction Count -// union{ -// uint32_t BufferPointer1; -// struct { -// volatile uint32_t TCount : 3; -// volatile uint32_t TPosition : 2; -// }; -// }; - /*---------- Word 6 ----------*/ ehci_link_t back; -- cgit v1.3.1 From ec4bd39a9209f37b02edac2f6a1ea2ef27f6b785 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 18 May 2023 16:41:06 +0700 Subject: refactor ehci: add attached_buffer for dcache invalidate for IN transfer --- src/portable/ehci/ehci.c | 116 +++++++++++++++++++++++++++-------------------- src/portable/ehci/ehci.h | 8 ++-- 2 files changed, 72 insertions(+), 52 deletions(-) (limited to 'src') diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index a08731667..cc825d549 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -154,6 +154,7 @@ static inline ehci_qhd_t* qhd_next (ehci_qhd_t const * p_qhd); static inline ehci_qhd_t* qhd_find_free (void); static inline ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr); static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc); +static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd); static inline ehci_qtd_t* qtd_find_free (void); static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes); @@ -468,13 +469,9 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet td->pid = EHCI_PID_SETUP; hcd_dcache_clean((void *) setup_packet, 8); - hcd_dcache_clean_invalidate(td, sizeof(ehci_qtd_t)); - // attach TD - qhd->p_attached_qtd = td; // software management - qhd->qtd_overlay.next.address = (uint32_t) td; - - hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); + // attach TD to QHD -> start transferring + qhd_attach_qtd(qhd, td); return true; } @@ -513,13 +510,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * }else { hcd_dcache_clean(buffer, buflen); } - hcd_dcache_clean_invalidate(qtd, sizeof(ehci_qtd_t)); - // attach TD to QHD start transferring - qhd->p_attached_qtd = qtd; // software management - qhd->qtd_overlay.next.address = (uint32_t) qtd; - - hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); + // attach TD to QHD -> start transferring + qhd_attach_qtd(qhd, qtd); return true; } @@ -569,10 +562,9 @@ void port_connect_status_change_isr(uint8_t rhport) } TU_ATTR_ALWAYS_INLINE static inline -void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd) -{ +void qhd_xfer_complete_isr(ehci_qhd_t * qhd) { // examine TD attached to queue head - ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_attached_qtd; + ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) qhd->attached_qtd; if (qtd == NULL) return; // no TD attached hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); @@ -581,15 +573,22 @@ void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd) return; } + uint8_t dir = (qtd->pid == EHCI_PID_IN) ? 1 : 0; uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes; - uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, qtd->pid == EHCI_PID_IN ? 1 : 0); + + // invalidate dcache if IN transfer + if (dir == 1 && qhd->attached_buffer != 0) { + hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes); + } // remove and free TD before invoking callback - p_qhd->p_attached_qtd = NULL; + qhd->attached_qtd = NULL; + qhd->attached_buffer = 0; qtd->used = 0; // free QTD - // IOC is always set - hcd_event_xfer_complete(p_qhd->dev_addr, ep_addr, xferred_bytes, XFER_RESULT_SUCCESS, true); + // notify usbh + uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir); + hcd_event_xfer_complete(qhd->dev_addr, ep_addr, xferred_bytes, XFER_RESULT_SUCCESS, true); } TU_ATTR_ALWAYS_INLINE static inline @@ -651,10 +650,11 @@ void period_list_xfer_complete_isr(uint8_t rhport, uint32_t interval_ms) } } +// TODO merge with qhd_xfer_complete_isr() TU_ATTR_ALWAYS_INLINE static inline -void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) +void qhd_xfer_error_isr(ehci_qhd_t * qhd) { - volatile ehci_qtd_t *qtd_overlay = &p_qhd->qtd_overlay; + volatile ehci_qtd_t *qtd_overlay = &qhd->qtd_overlay; // TD has error if (qtd_overlay->halted) { @@ -674,28 +674,37 @@ void qhd_xfer_error_isr(ehci_qhd_t * p_qhd) // while(1){} // } - ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_attached_qtd; + ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) qhd->attached_qtd; TU_ASSERT(qtd, ); // No TD yet, probably a race condition or cache issue !? hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); + + uint8_t dir = (qtd->pid == EHCI_PID_IN) ? 1 : 0; uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes; - p_qhd->p_attached_qtd = NULL; + // invalidate dcache if IN transfer + if (dir == 1 && qhd->attached_buffer != 0) { + hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes); + } + + // remove and free TD before invoking callback + qhd->attached_qtd = NULL; + qhd->attached_buffer = 0; qtd->used = 0; // free QTD - if ( 0 == p_qhd->ep_number ) { + if (0 == qhd->ep_number ) { // control cannot be halted - p_qhd->qtd_overlay.next.terminate = 1; - p_qhd->qtd_overlay.alternate.terminate = 1; - p_qhd->qtd_overlay.halted = 0; + qhd->qtd_overlay.next.terminate = 1; + qhd->qtd_overlay.alternate.terminate = 1; + qhd->qtd_overlay.halted = 0; - ehci_qtd_t *p_setup = qtd_control(p_qhd->dev_addr); + ehci_qtd_t *p_setup = qtd_control(qhd->dev_addr); p_setup->used = 0; } // notify usbh - uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, p_qhd->pid == EHCI_PID_IN ? 1 : 0); - hcd_event_xfer_complete(p_qhd->dev_addr, ep_addr, xferred_bytes, xfer_result, true); + uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir); + hcd_event_xfer_complete(qhd->dev_addr, ep_addr, xferred_bytes, xfer_result, true); } } @@ -846,22 +855,10 @@ static inline ehci_qhd_t* qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) return NULL; } -//------------- TD helper -------------// -static inline ehci_qtd_t* qtd_find_free(void) -{ - for (uint32_t i=0; i cannot be cleared (ehci halted otherwise) - if (dev_addr != 0) - { + if (dev_addr != 0) { tu_memclr(p_qhd, sizeof(ehci_qhd_t)); } @@ -911,26 +908,47 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c p_qhd->int_smask = p_qhd->fl_int_cmask = 0; } - p_qhd->fl_hub_addr = devtree_info.hub_addr; - p_qhd->fl_hub_port = devtree_info.hub_port; - p_qhd->mult = 1; // TODO not use high bandwidth/park mode yet + p_qhd->fl_hub_addr = devtree_info.hub_addr; + p_qhd->fl_hub_port = devtree_info.hub_port; + p_qhd->mult = 1; // TODO not use high bandwidth/park mode yet //------------- HCD Management Data -------------// - p_qhd->used = 1; - p_qhd->removing = 0; - p_qhd->p_attached_qtd = NULL; + p_qhd->used = 1; + p_qhd->removing = 0; + p_qhd->attached_qtd = NULL; p_qhd->pid = tu_edpt_dir(ep_desc->bEndpointAddress) ? EHCI_PID_IN : EHCI_PID_OUT; // PID for TD under this endpoint //------------- active, but no TD list -------------// p_qhd->qtd_overlay.halted = 0; p_qhd->qtd_overlay.next.terminate = 1; p_qhd->qtd_overlay.alternate.terminate = 1; + if (TUSB_XFER_BULK == xfer_type && p_qhd->ep_speed == TUSB_SPEED_HIGH && p_qhd->pid == EHCI_PID_OUT) { p_qhd->qtd_overlay.ping_err = 1; // do PING for Highspeed Bulk OUT, EHCI section 4.11 } } +static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd) { + qhd->attached_qtd = qtd; + qhd->attached_buffer = qtd->buffer[0]; + + // clean and invalidate cache before physically write + hcd_dcache_clean_invalidate(qtd, sizeof(ehci_qtd_t)); + + qhd->qtd_overlay.next.address = (uint32_t) qtd; + hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); +} + + +//------------- TD helper -------------// +static inline ehci_qtd_t *qtd_find_free(void) { + for (uint32_t i = 0; i < QTD_MAX; i++) { + if (!ehci_data.qtd_pool[i].used) return &ehci_data.qtd_pool[i]; + } + return NULL; +} + static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes) { tu_memclr(qtd, sizeof(ehci_qtd_t)); diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h index b525131c6..8338fb419 100644 --- a/src/portable/ehci/ehci.h +++ b/src/portable/ehci/ehci.h @@ -164,10 +164,12 @@ typedef struct TU_ATTR_ALIGNED(32) uint8_t pid; uint8_t interval_ms; // polling interval in frames (or millisecond) - uint8_t TU_RESERVED[8]; + uint8_t TU_RESERVED[4]; - // usbh will only queue 1 TD per QHD - ehci_qtd_t * volatile p_attached_qtd; + // Attached TD management, note usbh will only queue 1 TD per QHD. + // buffer for dcache invalidate since td's buffer is modified by HC and finding initial buffer address is not trivial + uint32_t attached_buffer; + ehci_qtd_t * volatile attached_qtd; } ehci_qhd_t; TU_VERIFY_STATIC( sizeof(ehci_qhd_t) == 64, "size is not correct" ); -- cgit v1.3.1 From f26a93908ef9dcde6818c9b271727ed6c77e87d8 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 19 May 2023 10:56:52 +0700 Subject: only clean/invalidate dcache on imxrt if memory is not in DTCM --- src/portable/chipidea/ci_hs/hcd_ci_hs.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index ecb1a621c..ab6a42e11 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -42,17 +42,28 @@ #if CFG_TUSB_MCU == OPT_MCU_MIMXRT #include "ci_hs_imxrt.h" + // check if memory is cacheable i.e not in DTCM + TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uint32_t addr) { + return !(0x20000000 <= addr && addr < 0x20100000); + } + void hcd_dcache_clean(void* addr, uint32_t data_size) { - SCB_CleanDCache_by_Addr((uint32_t*) addr, (int32_t) data_size); + if (is_cache_mem((uint32_t) addr)) { + SCB_CleanDCache_by_Addr((uint32_t *) addr, (int32_t) data_size); + } } void hcd_dcache_invalidate(void* addr, uint32_t data_size) { - SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size); + if (is_cache_mem((uint32_t) addr)) { + SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size); + } } void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { + if (is_cache_mem((uint32_t) addr)) { SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size); } +} #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) #include "ci_hs_lpc18_43.h" -- cgit v1.3.1 From 5dae5e12928ba789cd7e248edd9fa91376902925 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 19 May 2023 13:32:49 +0700 Subject: ehci fix dcache clean when control endpoint failed --- hw/bsp/imxrt/family.cmake | 6 +++++- src/host/usbh.c | 3 ++- src/portable/ehci/ehci.c | 10 ++++------ src/tusb.c | 2 +- 4 files changed, 12 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 4628abc34..a475b4721 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -57,12 +57,16 @@ if (NOT TARGET ${BOARD_TARGET}) ) update_board(${BOARD_TARGET}) + if (NOT DEFINED LD_FILE_${TOOLCHAIN}) + set(LD_FILE_gcc ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld) + endif () + if (TOOLCHAIN STREQUAL "gcc") target_sources(${BOARD_TARGET} PUBLIC ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S ) target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld" + "LINKER:--script=${LD_FILE_gcc}" "LINKER:-Map=$>,$,$>${CMAKE_EXECUTABLE_SUFFIX}.map" # nanolib --specs=nosys.specs diff --git a/src/host/usbh.c b/src/host/usbh.c index c56ff9459..7b265c742 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -440,7 +440,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const ep_dir = tu_edpt_dir(ep_addr); - TU_LOG_USBH("on EP %02X with %u bytes %s\r\n", ep_addr, (unsigned int) event.xfer_complete.len, + TU_LOG_USBH("on EP %02X with %u bytes: %s\r\n", ep_addr, (unsigned int) event.xfer_complete.len, tu_str_xfer_result[event.xfer_complete.result]); if (event.dev_addr == 0) @@ -1255,6 +1255,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { failed_count++; osal_task_delay(ATTEMPT_DELAY_MS); // delay a bit + TU_LOG1("Enumeration attempt %u\r\n", failed_count); TU_ASSERT(tuh_control_xfer(xfer), ); }else { diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index cc825d549..10e2db7b5 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -577,7 +577,7 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) { uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes; // invalidate dcache if IN transfer - if (dir == 1 && qhd->attached_buffer != 0) { + if (dir == 1 && qhd->attached_buffer != 0 && xferred_bytes > 0) { hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes); } @@ -660,7 +660,7 @@ void qhd_xfer_error_isr(ehci_qhd_t * qhd) if (qtd_overlay->halted) { xfer_result_t xfer_result; - if (qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err || qtd_overlay->xact_err) { + if (qtd_overlay->xact_err || qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err) { // Error count = 0 often occurs when device disconnected, or other bus-related error xfer_result = XFER_RESULT_FAILED; }else { @@ -671,7 +671,6 @@ void qhd_xfer_error_isr(ehci_qhd_t * qhd) // if (XFER_RESULT_FAILED == xfer_result ) { // TU_LOG1(" QHD xfer err count: %d\n", qtd_overlay->err_count); // TU_BREAKPOINT(); // TODO skip unplugged device -// while(1){} // } ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) qhd->attached_qtd; @@ -683,7 +682,7 @@ void qhd_xfer_error_isr(ehci_qhd_t * qhd) uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes; // invalidate dcache if IN transfer - if (dir == 1 && qhd->attached_buffer != 0) { + if (dir == 1 && qhd->attached_buffer != 0 && xferred_bytes > 0) { hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes); } @@ -698,8 +697,7 @@ void qhd_xfer_error_isr(ehci_qhd_t * qhd) qhd->qtd_overlay.alternate.terminate = 1; qhd->qtd_overlay.halted = 0; - ehci_qtd_t *p_setup = qtd_control(qhd->dev_addr); - p_setup->used = 0; + hcd_dcache_clean(qhd, sizeof(ehci_qhd_t)); } // notify usbh diff --git a/src/tusb.c b/src/tusb.c index 7327db685..465b608b0 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -440,7 +440,7 @@ char const* const tu_str_std_request[] = }; char const* const tu_str_xfer_result[] = { - "OK", "Failed", "Stalled", "Timeout" + "OK", "FAILED", "STALLED", "TIMEOUT" }; #endif -- cgit v1.3.1 From 7211dd18b46affdf027522e34ff3aa3b5d8d5df5 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 19 May 2023 13:42:26 +0700 Subject: more dcache fix --- src/portable/ehci/ehci.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 10e2db7b5..852e7f4fe 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -273,19 +273,19 @@ static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr) { } // Close all opened endpoint belong to this device -void hcd_device_close(uint8_t rhport, uint8_t dev_addr) +void hcd_device_close(uint8_t rhport, uint8_t daddr) { // skip dev0 - if (dev_addr == 0) { + if (daddr == 0) { return; } // Remove from async list - list_remove_qhd_by_daddr((ehci_link_t *) qhd_async_head(rhport), dev_addr); + list_remove_qhd_by_daddr((ehci_link_t *) qhd_async_head(rhport), daddr); // Remove from all interval period list for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) { - list_remove_qhd_by_daddr((ehci_link_t *) &ehci_data.period_head_arr[i], dev_addr); + list_remove_qhd_by_daddr((ehci_link_t *) &ehci_data.period_head_arr[i], daddr); } // Async doorbell (EHCI 4.8.2 for operational details) @@ -453,7 +453,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const list_insert(list_head, (ehci_link_t*) p_qhd, EHCI_QTYPE_QHD); hcd_dcache_clean(p_qhd, sizeof(ehci_qhd_t)); - hcd_dcache_clean(list_head, sizeof(ehci_link_t)); + hcd_dcache_clean(list_head, sizeof(ehci_qhd_t)); return true; } -- cgit v1.3.1 From 1ef820ecfe569e181b8f20cb936f632e51d8257e Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Tue, 23 May 2023 21:45:00 +0700 Subject: Enhance chipidea (#2075) * update chipidea dcd, remove manual ep_count and use DCCPARAMS to get number of endpoint instead * add dcd dcache for chipidea * add cmake for lpc18 * add makefile build for mcx * use fork of mcu sdk * fix ci build with nrf * flash rp2040 with openocd --- .github/workflows/build_arm.yml | 3 +- .github/workflows/cmake_arm.yml | 1 + .idea/cmake.xml | 7 +- .idea/runConfigurations/rt1010_jlink.xml | 10 + .idea/runConfigurations/rt1010_nxplink.xml | 10 - .idea/runConfigurations/rt1060_nxplink.xml | 10 - .pre-commit-config.yaml | 16 +- examples/device/CMakeLists.txt | 2 +- hw/bsp/board_mcu.h | 2 +- hw/bsp/family_support.cmake | 7 + hw/bsp/imxrt/family.cmake | 11 +- hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake | 11 + hw/bsp/lpc18/boards/mcb1800/board.cmake | 11 + hw/bsp/lpc18/family.cmake | 155 +++++++++++ hw/bsp/lpc55/family.cmake | 6 +- hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h | 166 ++++++++++++ hw/bsp/mcx/boards/mcxn947brk/board.cmake | 18 ++ hw/bsp/mcx/boards/mcxn947brk/board.h | 66 +++++ hw/bsp/mcx/boards/mcxn947brk/board.mk | 11 + hw/bsp/mcx/boards/mcxn947brk/clock_config.c | 338 ++++++++++++++++++++++++ hw/bsp/mcx/boards/mcxn947brk/clock_config.h | 177 +++++++++++++ hw/bsp/mcx/boards/mcxn947brk/pin_mux.c | 141 ++++++++++ hw/bsp/mcx/boards/mcxn947brk/pin_mux.h | 51 ++++ hw/bsp/mcx/family.c | 262 ++++++++++++++++++ hw/bsp/mcx/family.cmake | 179 +++++++++++++ hw/bsp/mcx/family.mk | 48 ++++ hw/bsp/nrf/family.cmake | 11 +- src/common/tusb_mcu.h | 26 +- src/device/dcd.h | 16 ++ src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 32 ++- src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h | 6 +- src/portable/chipidea/ci_hs/ci_hs_mcx.h | 52 ++++ src/portable/chipidea/ci_hs/ci_hs_type.h | 14 +- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 96 +++++-- src/portable/chipidea/ci_hs/hcd_ci_hs.c | 21 +- src/portable/ehci/ehci.c | 13 +- src/tusb_option.h | 6 +- tools/cmake/cpu/cortex-m3.cmake | 10 + tools/cmake/cpu/cortex-m33.cmake | 5 +- tools/cmake/toolchain/arm_gcc.cmake | 2 + tools/get_deps.py | 2 +- tools/make/cpu/cortex-m33.mk | 4 +- 42 files changed, 1914 insertions(+), 121 deletions(-) create mode 100644 .idea/runConfigurations/rt1010_jlink.xml delete mode 100644 .idea/runConfigurations/rt1010_nxplink.xml delete mode 100644 .idea/runConfigurations/rt1060_nxplink.xml create mode 100644 hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake create mode 100644 hw/bsp/lpc18/boards/mcb1800/board.cmake create mode 100644 hw/bsp/lpc18/family.cmake create mode 100644 hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/mcx/boards/mcxn947brk/board.cmake create mode 100644 hw/bsp/mcx/boards/mcxn947brk/board.h create mode 100644 hw/bsp/mcx/boards/mcxn947brk/board.mk create mode 100644 hw/bsp/mcx/boards/mcxn947brk/clock_config.c create mode 100644 hw/bsp/mcx/boards/mcxn947brk/clock_config.h create mode 100644 hw/bsp/mcx/boards/mcxn947brk/pin_mux.c create mode 100644 hw/bsp/mcx/boards/mcxn947brk/pin_mux.h create mode 100644 hw/bsp/mcx/family.c create mode 100644 hw/bsp/mcx/family.cmake create mode 100644 hw/bsp/mcx/family.mk create mode 100644 src/portable/chipidea/ci_hs/ci_hs_mcx.h create mode 100644 tools/cmake/cpu/cortex-m3.cmake (limited to 'src') diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml index f0b01b43d..917c83d74 100644 --- a/.github/workflows/build_arm.yml +++ b/.github/workflows/build_arm.yml @@ -142,8 +142,7 @@ jobs: - name: Create flash.sh run: | - #echo > flash.sh 'cmdout=$(openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1 reset exit")' - echo > flash.sh 'pyocd flash -t rp2040 $1' + echo > flash.sh 'cmdout=$(openocd -f "interface/cmsis-dap.cfg" -f "target/rp2040.cfg" -c "adapter speed 5000" -c "program $1 reset exit")' echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi' chmod +x flash.sh diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml index 844a03443..12173fb63 100644 --- a/.github/workflows/cmake_arm.yml +++ b/.github/workflows/cmake_arm.yml @@ -32,6 +32,7 @@ jobs: matrix: family: # Alphabetical order + - 'mcx' - 'imxrt' steps: - name: Setup Python diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 7dacd0003..a80ebed3c 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -2,8 +2,9 @@ - - + + + @@ -29,6 +30,8 @@ + + \ No newline at end of file diff --git a/.idea/runConfigurations/rt1010_jlink.xml b/.idea/runConfigurations/rt1010_jlink.xml new file mode 100644 index 000000000..70cfeea53 --- /dev/null +++ b/.idea/runConfigurations/rt1010_jlink.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/rt1010_nxplink.xml b/.idea/runConfigurations/rt1010_nxplink.xml deleted file mode 100644 index cf3bf842f..000000000 --- a/.idea/runConfigurations/rt1010_nxplink.xml +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - \ No newline at end of file diff --git a/.idea/runConfigurations/rt1060_nxplink.xml b/.idea/runConfigurations/rt1060_nxplink.xml deleted file mode 100644 index d3303bdb6..000000000 --- a/.idea/runConfigurations/rt1060_nxplink.xml +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - \ No newline at end of file diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 6fb98afb8..4071ec326 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -8,8 +8,16 @@ repos: hooks: - id: check-yaml - id: trailing-whitespace + exclude: | + (?x)^( + hw/bsp/mcx/sdk/ + ) - id: end-of-file-fixer - exclude: ^.idea/ + exclude: | + (?x)^( + .idea/| + hw/bsp/mcx/sdk/ + ) - id: forbid-submodules - repo: https://github.com/codespell-project/codespell @@ -17,7 +25,11 @@ repos: hooks: - id: codespell args: [-w] - exclude: ^lib/ + exclude: | + (?x)^( + lib/| + hw/bsp/mcx/sdk/ + ) - repo: local hooks: diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt index 10a1f4c26..89cfceeeb 100644 --- a/examples/device/CMakeLists.txt +++ b/examples/device/CMakeLists.txt @@ -24,7 +24,7 @@ family_add_subdirectory(midi_test) family_add_subdirectory(msc_dual_lun) # FIXME temp skip net_lwip_webserver for imxrt for now -if (NOT ${FAMILY} STREQUAL "imxrt") +if (NOT ${FAMILY} STREQUAL "imxrt" AND NOT ${FAMILY} STREQUAL "mcx") family_add_subdirectory(net_lwip_webserver) endif() diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index cd195a19b..35210dbae 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -44,7 +44,7 @@ TU_CHECK_MCU(OPT_MCU_LPC40XX, OPT_MCU_LPC43XX) #include "chip.h" -#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX) +#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX, OPT_MCU_MCXN9) #include "fsl_device_registers.h" #elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32) diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 442aba955..d2d675332 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -135,6 +135,13 @@ function(family_add_default_example_warnings TARGET) endif() endfunction() + +# add_custom_command(TARGET ${TARGET} POST_BUILD +# COMMAND ${CMAKE_OBJCOPY} -O ihex $ ${TARGET}.hex +# COMMAND ${CMAKE_OBJCOPY} -O binary $ ${TARGET}.bin +# COMMENT "Creating ${TARGET}.hex and ${TARGET}.bin" +# ) + # Add flash jlink target function(family_flash_jlink TARGET) if (NOT DEFINED JLINKEXE) diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 5261e5810..ade744aa5 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -1,8 +1,4 @@ -if (TARGET _imxrt_family_inclusion_marker) - return() -endif () - -add_library(_imxrt_family_inclusion_marker INTERFACE) +include_guard() if (NOT BOARD) message(FATAL_ERROR "BOARD not specified") @@ -87,6 +83,11 @@ function(family_configure_target TARGET) # set output name to .elf set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf) + # run size after build + add_custom_command(TARGET ${TARGET} POST_BUILD + COMMAND ${TOOLCHAIN_SIZE} $ + ) + # TOP is path to root directory set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..") diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake new file mode 100644 index 000000000..b540012a4 --- /dev/null +++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake @@ -0,0 +1,11 @@ +set(MCU_VARIANT LPC18S37) + +set(JLINK_DEVICE LPC18S37) +set(PYOCD_TARGET LPC18S37) +set(NXPLINK_DEVICE LPC18S37:LPCXPRESSO18S37) + +set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/lpc1837.ld) + +function(update_board TARGET) + # nothing to do +endfunction() diff --git a/hw/bsp/lpc18/boards/mcb1800/board.cmake b/hw/bsp/lpc18/boards/mcb1800/board.cmake new file mode 100644 index 000000000..1efeafd12 --- /dev/null +++ b/hw/bsp/lpc18/boards/mcb1800/board.cmake @@ -0,0 +1,11 @@ +set(MCU_VARIANT LPC1857) + +set(JLINK_DEVICE LPC1857) +set(PYOCD_TARGET LPC1857) +set(NXPLINK_DEVICE LPC1857:MCB1857) + +set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/lpc1857.ld) + +function(update_board TARGET) + # nothing to do +endfunction() diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake new file mode 100644 index 000000000..059408fe9 --- /dev/null +++ b/hw/bsp/lpc18/family.cmake @@ -0,0 +1,155 @@ +include_guard() + +if (NOT BOARD) + message(FATAL_ERROR "BOARD not specified") +endif () + +# TOP is path to root directory +set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..") +set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx) + +# toolchain set up +set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS LPC18XX CACHE INTERNAL "") + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +set(BOARD_TARGET board_${BOARD}) +if (NOT TARGET ${BOARD_TARGET}) + add_library(${BOARD_TARGET} STATIC + ${SDK_DIR}/../gcc/cr_startup_lpc18xx.c + ${SDK_DIR}/src/chip_18xx_43xx.c + ${SDK_DIR}/src/clock_18xx_43xx.c + ${SDK_DIR}/src/gpio_18xx_43xx.c + ${SDK_DIR}/src/sysinit_18xx_43xx.c + ${SDK_DIR}/src/uart_18xx_43xx.c + ) + target_compile_options(${BOARD_TARGET} PUBLIC + -nostdlib + ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + __USE_LPCOPEN + CORE_M3 + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${SDK_DIR}/inc + ${SDK_DIR}/inc/config_18xx + ) + update_board(${BOARD_TARGET}) + + if (NOT DEFINED LD_FILE_${TOOLCHAIN}) + MESSAGE(FATAL_ERROR "LD_FILE_${TOOLCHAIN} not defined") + endif () + + if (TOOLCHAIN STREQUAL "gcc") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_gcc}" + "LINKER:-Map=$>,$,$>${CMAKE_EXECUTABLE_SUFFIX}.map" + # nanolib + --specs=nosys.specs + --specs=nano.specs + ) + else () + # TODO support IAR + endif () +endif () # BOARD_TARGET + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_target TARGET) + # set output name to .elf + set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf) + + # run size after build + add_custom_command(TARGET ${TARGET} POST_BUILD + COMMAND ${TOOLCHAIN_SIZE} $ + ) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # TinyUSB Port + ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c + ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c + ${TOP}/src/portable/ehci/ehci.c + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + #---------- TinyUSB ---------- + # tinyusb target is built for each example since it depends on example's tusb_config.h + set(TINYUSB_TARGET_PREFIX ${TARGET}-) + add_library(${TARGET}-tinyusb_config INTERFACE) + + target_include_directories(${TARGET}-tinyusb_config INTERFACE + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) + target_compile_definitions(${TARGET}-tinyusb_config INTERFACE + CFG_TUSB_MCU=OPT_MCU_LPC18XX + ) + + # tinyusb's CMakeList.txt + add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) + + # Link dependencies + target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb) + + # group target (not yet supported by clion) + set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config + PROPERTIES FOLDER ${TARGET}_sub + ) + + #---------- Flash ---------- + family_flash_jlink(${TARGET}) +endfunction() + + +function(family_add_freertos TARGET) + # freertos_config + add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig ${CMAKE_CURRENT_BINARY_DIR}/freertos_config) + + ## freertos + if (NOT TARGET freertos_kernel) + add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../lib/FreeRTOS-Kernel ${CMAKE_CURRENT_BINARY_DIR}/freertos_kernel) + endif () + + # Add FreeRTOS option to tinyusb_config + target_compile_definitions(${TARGET}-tinyusb_config INTERFACE + CFG_TUSB_OS=OPT_OS_FREERTOS + ) + # link tinyusb with freeRTOS kernel + target_link_libraries(${TARGET}-tinyusb PUBLIC + freertos_kernel + ) + target_link_libraries(${TARGET} PUBLIC + freertos_kernel + ) +endfunction() + +function(family_configure_device_example TARGET) + family_configure_target(${TARGET}) +endfunction() + +function(family_configure_host_example TARGET) + family_configure_target(${TARGET}) +endfunction() + +function(family_configure_dual_usb_example TARGET) + family_configure_target(${TARGET}) +endfunction() diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake index 611c88eb5..3aeda5b2d 100644 --- a/hw/bsp/lpc55/family.cmake +++ b/hw/bsp/lpc55/family.cmake @@ -1,8 +1,4 @@ -if (TARGET _lpc55_family_inclusion_marker) - return() -endif () - -add_library(_lpc55_family_inclusion_marker INTERFACE) +include_guard() if (NOT BOARD) message(FATAL_ERROR "BOARD not specified") diff --git a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..4c6058d27 --- /dev/null +++ b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,166 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// IAR assembler have limited preprocessor support and it only need following macros: +#ifndef __IASMARM__ +// FIXME cause redundant-decls warnings +extern uint32_t SystemCoreClock; +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 2 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* Define to trap errors during development. */ +// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) + #define configASSERT(_exp) \ + do {\ + if ( !(_exp) ) { \ + volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ + if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \ + taskDISABLE_INTERRUPTS(); \ + __asm("BKPT #0\n"); \ + }\ + }\ + } while(0) +#else + #define configASSERT( x ) +#endif + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS 3 + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK; + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); + CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); + + /*According to reference manual, device mode setting has to be set by access usb host register */ + CLOCK_EnableClock(kCLOCK_Usbhsl0); // enable usb0 host clock + USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK; + CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock + + /* enable USB Device clock */ + CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); +#endif + +#if PORT_SUPPORT_DEVICE(1) + // Port1 is High Speed + + // Power + SPC0->ACTIVE_VDELAY = 0x0500; + /* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default, CORELDO is 1.0V) */ + SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK; + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) | + SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u); + /* Wait until it is done */ + while (SPC0->SC & SPC_SC_BUSY_MASK) {} + if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) { + SCG0->TRIM_LOCK = 0x5a5a0001U; + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + /* wait LDO ready */ + while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK)); + } + SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK; + SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK); + /* xtal = 20 ~ 30MHz */ + SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT); + SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK; + while (1) { + if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) { + break; + } + } + + // Clock + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK; + CLOCK_EnableClock(kCLOCK_UsbHs); + CLOCK_EnableClock(kCLOCK_UsbHsPhy); + CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, 24000000U); + CLOCK_EnableUsbhsClock(); + + // USB PHY +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + USBPHY->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ +#endif + + // Enable PHY support for Low speed device + LS via FS Hub + USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; + + // Enable all power for normal operation + USBPHY->PWD = 0; + + // TX Timing + uint32_t phytx = USBPHY->TX; + phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK); + phytx |= USBPHY_TX_D_CAL(0x04) | USBPHY_TX_TXCAL45DP(0x07) | USBPHY_TX_TXCAL45DM(0x07); + //phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06); + USBPHY->TX = phytx; +#endif +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); + +#ifdef NEOPIXEL_PIN + if (state) { + sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000); + sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010); + } else { + sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000); + sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010); + } + sctpix_show(); +#endif +} + +uint32_t board_button_read(void) +{ +#ifdef BUTTON_GPIO + return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); +#endif +} + +int board_uart_read(uint8_t* buf, int len) +{ + (void) buf; (void) len; + return 0; +} + +int board_uart_write(void const * buf, int len) +{ +#ifdef UART_DEV + LPUART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len); + return len; +#else + (void) buf; (void) len; + return 0; +#endif +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake new file mode 100644 index 000000000..e4bc11be5 --- /dev/null +++ b/hw/bsp/mcx/family.cmake @@ -0,0 +1,179 @@ +include_guard() + +if (NOT BOARD) + message(FATAL_ERROR "BOARD not specified") +endif () + +# TOP is path to root directory +set(TOP ${CMAKE_CURRENT_LIST_DIR}/../../..) +set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk) +set(CMSIS_DIR ${TOP}/lib/CMSIS_5) + +# toolchain set up +set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS LPC55XX CACHE INTERNAL "") + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +set(BOARD_TARGET board_${BOARD}) +if (NOT TARGET ${BOARD_TARGET}) + add_library(${BOARD_TARGET} STATIC + # external driver + #lib/sct_neopixel/sct_neopixel.c + + # driver + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c + # mcu + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c + ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c + ) +# target_compile_definitions(${BOARD_TARGET} PUBLIC +# ) + target_include_directories(${BOARD_TARGET} PUBLIC + # driver + # mcu + ${CMSIS_DIR}/CMSIS/Core/Include + ${SDK_DIR}/devices/${MCU_VARIANT} + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers + ) + update_board(${BOARD_TARGET}) + + if (TOOLCHAIN STREQUAL "gcc") + target_sources(${BOARD_TARGET} PUBLIC + ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S + ) + target_link_options(${BOARD_TARGET} PUBLIC + # linker file + "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld" + # link map + "LINKER:-Map=$>,$,$>${CMAKE_EXECUTABLE_SUFFIX}.map" + # nanolib + --specs=nosys.specs + --specs=nano.specs + ) + else () + # TODO support IAR + endif () +endif () # BOARD_TARGET + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_target TARGET) + # set output name to .elf + set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf) + + # run size after build + add_custom_command(TARGET ${TARGET} POST_BUILD + COMMAND ${TOOLCHAIN_SIZE} $ + ) + + # TOP is path to root directory + set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..") + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # TinyUSB Port + ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + #---------- TinyUSB ---------- + # tinyusb target is built for each example since it depends on example's tusb_config.h + set(TINYUSB_TARGET_PREFIX ${TARGET}-) + add_library(${TARGET}-tinyusb_config INTERFACE) + + target_include_directories(${TARGET}-tinyusb_config INTERFACE + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) + target_compile_definitions(${TARGET}-tinyusb_config INTERFACE + CFG_TUSB_MCU=OPT_MCU_MCXN9 + ) + + # tinyusb's CMakeList.txt + add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) + + # Link dependencies + target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb) + + # group target (not yet supported by clion) + set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config + PROPERTIES FOLDER ${TARGET}_sub + ) + + #---------- Flash ---------- + # use MCUXpresso GUI Flash Tool to flash the elf + +# set(REDLINK_EXE /usr/local/LinkServer/binaries/crt_emu_cm_redlink) +# add_custom_target(${TARGET}-redlink +# DEPENDS ${TARGET} +# COMMAND ${REDLINK_EXE} --flash-load-exec $ --vendor NXP -p MCXN947 --bootromstall +# 0x50000040 -CoreIndex=0 --flash-driver= -x ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/flash --flash-dir +# ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/flash --flash-hashing +# ) + + #family_flash_jlink(${TARGET}) + #family_flash_nxplink(${TARGET}) + #family_flash_pyocd(${TARGET}) +endfunction() + + +function(family_add_freertos TARGET) + # freertos_config + if (NOT TARGET freertos_config) + add_library(freertos_config INTERFACE) + target_include_directories(freertos_config SYSTEM INTERFACE + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig + ) + endif() + + ## freertos + if (NOT TARGET freertos_kernel) + add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../lib/FreeRTOS-Kernel ${CMAKE_CURRENT_BINARY_DIR}/freertos_kernel) + endif () + + # Add FreeRTOS option to tinyusb_config + target_compile_definitions(${TARGET}-tinyusb_config INTERFACE + CFG_TUSB_OS=OPT_OS_FREERTOS + ) + # link tinyusb with freeRTOS kernel + target_link_libraries(${TARGET}-tinyusb PUBLIC + freertos_kernel + ) + target_link_libraries(${TARGET} PUBLIC + freertos_kernel + ) +endfunction() + +function(family_configure_device_example TARGET) + family_configure_target(${TARGET}) +endfunction() + +function(family_configure_host_example TARGET) + family_configure_target(${TARGET}) +endfunction() + +function(family_configure_dual_usb_example TARGET) + family_configure_target(${TARGET}) +endfunction() diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk new file mode 100644 index 000000000..2cd4c2448 --- /dev/null +++ b/hw/bsp/mcx/family.mk @@ -0,0 +1,48 @@ +UF2_FAMILY_ID = 0x2abc77ec +SDK_DIR = hw/mcu/nxp/mcux-sdk + +DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5 + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m33 +include $(TOP)/tools/make/cpu/$(CPU_CORE).mk + +# Default to Highspeed PORT1 +PORT ?= 1 + +CFLAGS += \ + -flto \ + -DCFG_TUSB_MCU=OPT_MCU_MCXN9 \ + -DBOARD_TUD_RHPORT=$(PORT) \ + +ifeq ($(PORT), 1) + $(info "PORT1 High Speed") + CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED +else + $(info "PORT0 Full Speed") +endif + +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration + +# All source paths should be relative to the top level. +LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld + +SRC_C += \ + src/portable/chipidea/ci_hs/dcd_ci_hs.c \ + $(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \ + $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \ + $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \ + $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \ + $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \ + $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c \ + $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \ + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \ + $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \ + +SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 9c43478e8..1156a171b 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -1,8 +1,4 @@ -if (TARGET _nrf_family_inclusion_marker) - return() -endif () - -add_library(_nrf_family_inclusion_marker INTERFACE) +include_guard() if (NOT BOARD) message(FATAL_ERROR "BOARD not specified") @@ -89,6 +85,11 @@ function(family_configure_target TARGET) # set output name to .elf set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf) + # run size after build + add_custom_command(TARGET ${TARGET} POST_BUILD + COMMAND ${TOOLCHAIN_SIZE} $ + ) + # TOP is path to root directory set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..") diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index ba8976a8c..9c2933983 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -59,14 +59,6 @@ #define TUP_USBIP_OHCI #define TUP_OHCI_RHPORTS 2 -#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) - // TODO USB0 has 6, USB1 has 4 - #define TUP_USBIP_CHIPIDEA_HS - #define TUP_USBIP_EHCI - - #define TUP_DCD_ENDPOINT_MAX 6 - #define TUP_RHPORT_HIGHSPEED 1 // Port0 HS, Port1 FS - #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX) #define TUP_DCD_ENDPOINT_MAX 5 @@ -78,12 +70,28 @@ // TODO USB0 has 5, USB1 has 6 #define TUP_DCD_ENDPOINT_MAX 6 +#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) + // USB0 has 6 with HS PHY, USB1 has 4 only FS + #define TUP_USBIP_CHIPIDEA_HS + #define TUP_USBIP_EHCI + + #define TUP_DCD_ENDPOINT_MAX 6 + #define TUP_RHPORT_HIGHSPEED 1 + +#elif TU_CHECK_MCU(OPT_MCU_MCXN9) + // NOTE: MCXN943 port 1 use chipidea HS, port 0 use chipidea FS + #define TUP_USBIP_CHIPIDEA_HS + #define TUP_USBIP_EHCI + + #define TUP_DCD_ENDPOINT_MAX 8 + #define TUP_RHPORT_HIGHSPEED 1 + #elif TU_CHECK_MCU(OPT_MCU_MIMXRT) #define TUP_USBIP_CHIPIDEA_HS #define TUP_USBIP_EHCI #define TUP_DCD_ENDPOINT_MAX 8 - #define TUP_RHPORT_HIGHSPEED 1 // Port0 HS, Port1 HS + #define TUP_RHPORT_HIGHSPEED 1 #elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32) #define TUP_USBIP_CHIPIDEA_FS diff --git a/src/device/dcd.h b/src/device/dcd.h index 00419ff05..f82b8633d 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -102,6 +102,22 @@ typedef struct TU_ATTR_ALIGNED(4) //TU_VERIFY_STATIC(sizeof(dcd_event_t) <= 12, "size is not correct"); +//--------------------------------------------------------------------+ +// Memory API +//--------------------------------------------------------------------+ + +// clean/flush data cache: write cache -> memory. +// Required before an DMA TX transfer to make sure data is in memory +void dcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK; + +// invalidate data cache: mark cache as invalid, next read will read from memory +// Required BOTH before and after an DMA RX transfer +void dcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; + +// clean and invalidate data cache +// Required before an DMA transfer where memory is both read/write by DMA +void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; + //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h index 607926a65..ceff893bd 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h +++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h @@ -46,18 +46,44 @@ static const ci_hs_controller_t _ci_controller[] = { // RT1010 and RT1020 only has 1 USB controller #if FSL_FEATURE_SOC_USBHS_COUNT == 1 - { .reg_base = USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 } + { .reg_base = USB_BASE , .irqnum = USB_OTG1_IRQn } #else - { .reg_base = USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 }, - { .reg_base = USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 } + { .reg_base = USB1_BASE, .irqnum = USB_OTG1_IRQn}, + { .reg_base = USB2_BASE, .irqnum = USB_OTG2_IRQn} #endif }; +#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base) + +//------------- DCD -------------// #define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum) #define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) +//------------- HCD -------------// #define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum) #define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) +//------------- DCache -------------// +TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uint32_t addr) { + return !(0x20000000 <= addr && addr < 0x20100000); +} + +TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean(void* addr, uint32_t data_size) { + if (imxrt_is_cache_mem((uint32_t) addr)) { + SCB_CleanDCache_by_Addr((uint32_t *) addr, (int32_t) data_size); + } +} + +TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_invalidate(void* addr, uint32_t data_size) { + if (imxrt_is_cache_mem((uint32_t) addr)) { + SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size); + } +} + +TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean_invalidate(void* addr, uint32_t data_size) { + if (imxrt_is_cache_mem((uint32_t) addr)) { + SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size); + } +} #endif diff --git a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h index 8c2e7dfa6..2e84c93e7 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h +++ b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h @@ -32,10 +32,12 @@ static const ci_hs_controller_t _ci_controller[] = { - { .reg_base = LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 }, - { .reg_base = LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 } + { .reg_base = LPC_USB0_BASE, .irqnum = USB0_IRQn }, + { .reg_base = LPC_USB1_BASE, .irqnum = USB1_IRQn } }; +#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base) + #define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum) #define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) diff --git a/src/portable/chipidea/ci_hs/ci_hs_mcx.h b/src/portable/chipidea/ci_hs/ci_hs_mcx.h new file mode 100644 index 000000000..f940f4a9d --- /dev/null +++ b/src/portable/chipidea/ci_hs/ci_hs_mcx.h @@ -0,0 +1,52 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _CI_HS_MCX_H_ +#define _CI_HS_MCX_H_ + +#include "fsl_device_registers.h" + +// NOTE: MCX N9 has 2 different USB Controller +// - USB0 is KHCI FullSpeed +// - USB1 is ChipIdea HighSpeed, therefore rhport = 1 is actually index 0 + +static const ci_hs_controller_t _ci_controller[] = { + {.reg_base = USBHS1__USBC_BASE, .irqnum = USB1_HS_IRQn} +}; + +TU_ATTR_ALWAYS_INLINE static inline ci_hs_regs_t* CI_HS_REG(uint8_t port) { + (void) port; + return ((ci_hs_regs_t*) _ci_controller[0].reg_base); +} + +#define CI_DCD_INT_ENABLE(_p) do { (void) _p; NVIC_EnableIRQ (_ci_controller[0].irqnum); } while (0) +#define CI_DCD_INT_DISABLE(_p) do { (void) _p; NVIC_DisableIRQ(_ci_controller[0].irqnum); } while (0) + +#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum) +#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) + + +#endif diff --git a/src/portable/chipidea/ci_hs/ci_hs_type.h b/src/portable/chipidea/ci_hs/ci_hs_type.h index 31b5a012d..2f3aa3694 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_type.h +++ b/src/portable/chipidea/ci_hs/ci_hs_type.h @@ -31,13 +31,21 @@ extern "C" { #endif +// DCCPARAMS +enum { + DCCPARAMS_DEN_MASK = 0x1Fu, ///< DEN bit 4:0 +}; + // USBCMD enum { USBCMD_RUN_STOP = TU_BIT(0), USBCMD_RESET = TU_BIT(1), USBCMD_SETUP_TRIPWIRE = TU_BIT(13), - USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14) ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD -// Interrupt Threshold bit 23:16 + USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14), // This bit is used as a semaphore to ensure the to proper addition of a + // new dTD to an active (primed) endpoint’s linked list. This bit is set and + // cleared by software during the process of adding a new dTD + + USBCMD_INTR_THRESHOLD_MASK = 0x00FF0000u, // Interrupt Threshold bit 23:16 }; // PORTSC1 @@ -72,6 +80,7 @@ enum { // USBMode enum { + USBMOD_CM_MASK = TU_BIT(0) | TU_BIT(1), USBMODE_CM_DEVICE = 2, USBMODE_CM_HOST = 3, @@ -134,7 +143,6 @@ typedef struct { uint32_t reg_base; uint32_t irqnum; - uint8_t ep_count; // Max bi-directional Endpoints }ci_hs_controller_t; #ifdef __cplusplus diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 9be79a2f1..850c82e43 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -28,34 +28,52 @@ #if CFG_TUD_ENABLED && defined(TUP_USBIP_CHIPIDEA_HS) -//--------------------------------------------------------------------+ -// INCLUDE -//--------------------------------------------------------------------+ #include "device/dcd.h" #include "ci_hs_type.h" #if CFG_TUSB_MCU == OPT_MCU_MIMXRT #include "ci_hs_imxrt.h" -#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) + + void dcd_dcache_clean(void* addr, uint32_t data_size) { + imxrt_dcache_clean(addr, data_size); + } + + void dcd_dcache_invalidate(void* addr, uint32_t data_size) { + imxrt_dcache_invalidate(addr, data_size); + } + + void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { + imxrt_dcache_clean_invalidate(addr, data_size); + } + +#else + +#if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) #include "ci_hs_lpc18_43.h" + +#elif TU_CHECK_MCU(OPT_MCU_MCXN9) + // MCX N9 only port 1 use this controller + #include "ci_hs_mcx.h" #else #error "Unsupported MCUs" #endif -//--------------------------------------------------------------------+ -// MACRO CONSTANT TYPEDEF -//--------------------------------------------------------------------+ + TU_ATTR_WEAK void dcd_dcache_clean(void* addr, uint32_t data_size) { + (void) addr; (void) data_size; + } -#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base) + TU_ATTR_WEAK void dcd_dcache_invalidate(void* addr, uint32_t data_size) { + (void) addr; (void) data_size; + } -// Clean means to push any cached changes to RAM and invalidate "removes" the -// entry from the cache. -#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1 - #define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr -#else - #define CleanInvalidateDCache_by_Addr(_addr, _dsize) + TU_ATTR_WEAK void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { + (void) addr; (void) data_size; + } #endif +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF +//--------------------------------------------------------------------+ // ENDPTCTRL enum { @@ -160,6 +178,16 @@ typedef struct { CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048) static dcd_data_t _dcd_data; +//--------------------------------------------------------------------+ +// Prototypes and Helper Functions +//--------------------------------------------------------------------+ + +TU_ATTR_ALWAYS_INLINE +static inline uint8_t ci_ep_count(ci_hs_regs_t const* dcd_reg) +{ + return dcd_reg->DCCPARAMS & DCCPARAMS_DEN_MASK; +} + //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ @@ -174,7 +202,8 @@ static void bus_reset(uint8_t rhport) // endpoint type of the unused direction must be changed from the control type to any other // type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior // for the data PID tracking on the active endpoint. - for( uint8_t i=1; i < _ci_controller[rhport].ep_count; i++) + uint8_t const ep_count = ci_ep_count(dcd_reg); + for( uint8_t i=1; i < ep_count; i++) { dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS)); } @@ -202,7 +231,7 @@ static void bus_reset(uint8_t rhport) _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only - CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); + dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); } void dcd_init(uint8_t rhport) @@ -211,26 +240,34 @@ void dcd_init(uint8_t rhport) ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); + TU_ASSERT(ci_ep_count(dcd_reg) <= TUP_DCD_ENDPOINT_MAX, ); + // Reset controller dcd_reg->USBCMD |= USBCMD_RESET; while( dcd_reg->USBCMD & USBCMD_RESET ) {} // Set mode to device, must be set immediately after reset - dcd_reg->USBMODE = USBMODE_CM_DEVICE; + uint32_t usbmode = dcd_reg->USBMODE & ~USBMOD_CM_MASK; + usbmode |= USBMODE_CM_DEVICE; + dcd_reg->USBMODE = usbmode; + dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION; #if !TUD_OPT_HIGH_SPEED dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED; #endif - CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); + dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment dcd_reg->USBSTS = dcd_reg->USBSTS; dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND; - dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0 - dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect + uint32_t usbcmd = dcd_reg->USBCMD; + usbcmd &= ~USBCMD_INTR_THRESHOLD_MASK; // Interrupt Threshold Interval = 0 + usbcmd |= USBCMD_RUN_STOP; // run + + dcd_reg->USBCMD = usbcmd; } void dcd_int_enable(uint8_t rhport) @@ -286,7 +323,7 @@ static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes) { // Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the // address to 32-byte boundaries. Buffer must be word aligned - CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31); + dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31); tu_memclr(p_qtd, sizeof(dcd_qtd_t)); @@ -343,8 +380,10 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); + // Must not exceed max endpoint number - TU_ASSERT( epnum < _ci_controller[rhport].ep_count ); + TU_ASSERT(epnum < ci_ep_count(dcd_reg)); //------------- Prepare Queue Head -------------// dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir]; @@ -359,11 +398,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) p_qhd->qtd_overlay.next = QTD_NEXT_INVALID; - CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); + dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); // Enable EP Control - ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); - uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET; if ( dir == TUSB_DIR_OUT ) @@ -382,7 +419,8 @@ void dcd_edpt_close_all (uint8_t rhport) ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); // Disable all non-control endpoints - for( uint8_t epnum=1; epnum < _ci_controller[rhport].ep_count; epnum++) + uint8_t const ep_count = ci_ep_count(dcd_reg); + for (uint8_t epnum = 1; epnum < ep_count; epnum++) { _dcd_data.qhd[epnum][TUSB_DIR_OUT].qtd_overlay.halted = 1; _dcd_data.qhd[epnum][TUSB_DIR_IN ].qtd_overlay.halted = 1; @@ -420,7 +458,7 @@ static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir) p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd // flush cache - CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); + dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); if ( epnum == 0 ) { @@ -498,7 +536,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 } } - CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31); + dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31); } else { @@ -611,7 +649,7 @@ void dcd_int_handler(uint8_t rhport) if (int_status & INTR_USB) { // Make sure we read the latest version of _dcd_data. - CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); + dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE; dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index ab6a42e11..8c27abbf6 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -42,28 +42,17 @@ #if CFG_TUSB_MCU == OPT_MCU_MIMXRT #include "ci_hs_imxrt.h" - // check if memory is cacheable i.e not in DTCM - TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uint32_t addr) { - return !(0x20000000 <= addr && addr < 0x20100000); - } - void hcd_dcache_clean(void* addr, uint32_t data_size) { - if (is_cache_mem((uint32_t) addr)) { - SCB_CleanDCache_by_Addr((uint32_t *) addr, (int32_t) data_size); - } + imxrt_dcache_clean(addr, data_size); } void hcd_dcache_invalidate(void* addr, uint32_t data_size) { - if (is_cache_mem((uint32_t) addr)) { - SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size); - } + imxrt_dcache_invalidate(addr, data_size); } -void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { - if (is_cache_mem((uint32_t) addr)) { - SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size); + void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { + imxrt_dcache_clean_invalidate(addr, data_size); } -} #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) #include "ci_hs_lpc18_43.h" @@ -75,8 +64,6 @@ void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base) - //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 852e7f4fe..2b25eee9d 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -163,22 +163,15 @@ static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t static inline ehci_link_t* list_next (ehci_link_t const *p_link); TU_ATTR_WEAK void hcd_dcache_clean(void* addr, uint32_t data_size) { - (void) addr; - (void) data_size; + (void) addr; (void) data_size; } -// invalidate data cache: mark cache as invalid, next read will read from memory -// Required BOTH before and after an DMA RX transfer TU_ATTR_WEAK void hcd_dcache_invalidate(void* addr, uint32_t data_size) { - (void) addr; - (void) data_size; + (void) addr; (void) data_size; } -// clean and invalidate data cache -// Required before an DMA transfer where memory is both read/write by DMA TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { - (void) addr; - (void) data_size; + (void) addr; (void) data_size; } //--------------------------------------------------------------------+ diff --git a/src/tusb_option.h b/src/tusb_option.h index 4f3f3a985..948c9edf3 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -166,6 +166,10 @@ // WCH #define OPT_MCU_CH32V307 2200 ///< WCH CH32V307 + +// NXP LPC MCX +#define OPT_MCU_MCXN9 2300 ///< NXP MCX N9 Series + // Helper to check if configured MCU is one of listed // Apply _TU_CHECK_MCU with || as separator to list of input #define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m) @@ -274,7 +278,7 @@ // In case TUP_MCU_STRICT_ALIGN = 1 and TUP_ARCH_STRICT_ALIGN =0, we will not reply on compiler // to generate unaligned access code. // LPC_IP3511 Highspeed cannot access unaligned memory on USB_RAM -#if TUD_OPT_HIGH_SPEED && (CFG_TUSB_MCU == OPT_MCU_LPC54XXX || CFG_TUSB_MCU == OPT_MCU_LPC55XX) +#if TUD_OPT_HIGH_SPEED && TU_CHECK_MCU(OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX) #define TUP_MCU_STRICT_ALIGN 1 #else #define TUP_MCU_STRICT_ALIGN 0 diff --git a/tools/cmake/cpu/cortex-m3.cmake b/tools/cmake/cpu/cortex-m3.cmake new file mode 100644 index 000000000..b740ee44c --- /dev/null +++ b/tools/cmake/cpu/cortex-m3.cmake @@ -0,0 +1,10 @@ +if (TOOLCHAIN STREQUAL "gcc") + list(APPEND TOOLCHAIN_COMMON_FLAGS + -mthumb + -mcpu=cortex-m3 + ) + + set(FREERTOS_PORT GCC_ARM_CM3 CACHE INTERNAL "") +else () + # TODO support IAR +endif () diff --git a/tools/cmake/cpu/cortex-m33.cmake b/tools/cmake/cpu/cortex-m33.cmake index fbd5027b1..26c91a64f 100644 --- a/tools/cmake/cpu/cortex-m33.cmake +++ b/tools/cmake/cpu/cortex-m33.cmake @@ -3,10 +3,11 @@ if (TOOLCHAIN STREQUAL "gcc") -mthumb -mcpu=cortex-m33 -mfloat-abi=hard - -mfpu=fpv5-d16 + #-mfpu=fpv5-d16 + -mfpu=fpv5-sp-d16 ) - set(FREERTOS_PORT GCC_ARM_CM33_NONSECURE CACHE INTERNAL "") + set(FREERTOS_PORT GCC_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "") else () # TODO support IAR endif () diff --git a/tools/cmake/toolchain/arm_gcc.cmake b/tools/cmake/toolchain/arm_gcc.cmake index c7b6cff98..5f25d637b 100644 --- a/tools/cmake/toolchain/arm_gcc.cmake +++ b/tools/cmake/toolchain/arm_gcc.cmake @@ -3,6 +3,8 @@ set(CMAKE_SYSTEM_NAME Generic) set(CMAKE_ASM_COMPILER "arm-none-eabi-gcc") set(CMAKE_C_COMPILER "arm-none-eabi-gcc") set(CMAKE_CXX_COMPILER "arm-none-eabi-g++") + +set(TOOLCHAIN_SIZE "arm-none-eabi-size" CACHE INTERNAL "") set(GCC_ELF2BIN "arm-none-eabi-objcopy") set_property(GLOBAL PROPERTY ELF2BIN ${GCC_ELF2BIN}) diff --git a/tools/get_deps.py b/tools/get_deps.py index be5738dc1..f499562cb 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -24,7 +24,7 @@ deps_optional = { 'hw/mcu/nordic/nrfx' : ['2527e3c8449cfd38aee41598e8af8492f410ed15', 'https://github.com/NordicSemiconductor/nrfx.git' ], 'hw/mcu/nuvoton' : ['2204191ec76283371419fbcec207da02e1bc22fa', 'https://github.com/majbthrd/nuc_driver.git' ], 'hw/mcu/nxp/lpcopen' : ['43c45c85405a5dd114fff0ea95cca62837740c13', 'https://github.com/hathach/nxp_lpcopen.git' ], - 'hw/mcu/nxp/mcux-sdk' : ['f357a1150f6cf6c6b844f53f2d426bfb3e649850', 'https://github.com/NXPmicro/mcux-sdk.git' ], + 'hw/mcu/nxp/mcux-sdk' : ['950819b7de9b32f92c3edf396bc5ffb8d66e7009', 'https://github.com/hathach/mcux-sdk.git' ], 'hw/mcu/nxp/nxp_sdk' : ['845c8fc49b6fb660f06a5c45225494eacb06f00c', 'https://github.com/hathach/nxp_sdk.git' ], 'hw/mcu/raspberry_pi/Pico-PIO-USB' : ['c3715ce94b6f6391856de56081d4d9b3e98fa93d', 'https://github.com/sekigon-gonnoc/Pico-PIO-USB.git' ], 'hw/mcu/renesas/fsp' : ['8dc14709f2a6518b43f71efad70d900b7718d9f1', 'https://github.com/renesas/fsp.git' ], diff --git a/tools/make/cpu/cortex-m33.mk b/tools/make/cpu/cortex-m33.mk index 2ea3a0753..3d12b01fd 100644 --- a/tools/make/cpu/cortex-m33.mk +++ b/tools/make/cpu/cortex-m33.mk @@ -3,7 +3,9 @@ ifeq ($(TOOLCHAIN),gcc) -mthumb \ -mcpu=cortex-m33 \ -mfloat-abi=hard \ - -mfpu=fpv5-d16 \ + -mfpu=fpv5-sp-d16 \ + + #-mfpu=fpv5-d16 \ #set(FREERTOS_PORT GCC_ARM_CM33_NONSECURE CACHE INTERNAL "") FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure -- cgit v1.3.1 From 57d2eb603b412a6bfbfdad7fb0bac854302b4351 Mon Sep 17 00:00:00 2001 From: Aladdin Bakosh Date: Mon, 15 May 2023 18:27:45 +0200 Subject: fix(RA Host Portable): implement missing function __builtin_ctz(x) for IAR --- src/portable/renesas/rusb2/hcd_rusb2.c | 2 +- src/portable/renesas/rusb2/rusb2_ra.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index e4743223e..0e6fa1618 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -407,7 +407,7 @@ static void process_pipe0_bemp(uint8_t rhport) static void process_pipe_nrdy(uint8_t rhport, unsigned num) { (void)rhport; - unsigned result; + xfer_result_t result; uint16_t volatile *ctr = get_pipectr(num); // TU_LOG1("NRDY %d %x\n", num, *ctr); switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) { diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 5785850cc..5be9f11ce 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -36,6 +36,10 @@ extern "C" { #define RUSB2_REG_BASE (0x40090000) +#if defined(__ICCARM__) + #define __builtin_ctz(x) __iar_builtin_CLZ(__iar_builtin_RBIT(x)) +#endif + TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) { (void) rhport; -- cgit v1.3.1 From 26d05d7fc922f3715799f6049556232d5ed5c8e3 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 25 May 2023 16:53:32 +0700 Subject: fix issue with ftdi host driver with status bytes add workflow_dispatch to all ci workflow --- .github/workflows/build_aarch64.yml | 1 + .github/workflows/build_arm.yml | 1 + .github/workflows/build_esp.yml | 1 + .github/workflows/build_iar.yml | 1 + .github/workflows/build_msp430.yml | 1 + .github/workflows/build_renesas.yml | 1 + .github/workflows/build_riscv.yml | 1 + .github/workflows/build_win_mac.yml | 1 + .github/workflows/cifuzz.yml | 1 + src/class/cdc/cdc_host.c | 36 +++++++++++++++++------------------- src/common/tusb_private.h | 17 +++++++++++------ 11 files changed, 37 insertions(+), 25 deletions(-) (limited to 'src') diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml index cc8ddb070..77d3778d7 100644 --- a/.github/workflows/build_aarch64.yml +++ b/.github/workflows/build_aarch64.yml @@ -1,6 +1,7 @@ name: Build AArch64 on: + workflow_dispatch: push: paths: - 'src/**' diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml index 917c83d74..1db9586af 100644 --- a/.github/workflows/build_arm.yml +++ b/.github/workflows/build_arm.yml @@ -1,6 +1,7 @@ name: Build ARM on: + workflow_dispatch: push: paths: - 'src/**' diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml index 0a6815ea2..29585cb36 100644 --- a/.github/workflows/build_esp.yml +++ b/.github/workflows/build_esp.yml @@ -1,6 +1,7 @@ name: Build ESP on: + workflow_dispatch: push: paths: - 'src/**' diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml index a5d24892f..8c3b57e10 100644 --- a/.github/workflows/build_iar.yml +++ b/.github/workflows/build_iar.yml @@ -1,6 +1,7 @@ name: Build IAR on: + workflow_dispatch: push: paths: - 'src/**' diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml index 7cb60dceb..5424a88d6 100644 --- a/.github/workflows/build_msp430.yml +++ b/.github/workflows/build_msp430.yml @@ -1,6 +1,7 @@ name: Build MSP430 on: + workflow_dispatch: push: paths: - 'src/**' diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml index ffdeedb71..3f0a4b694 100644 --- a/.github/workflows/build_renesas.yml +++ b/.github/workflows/build_renesas.yml @@ -1,6 +1,7 @@ name: Build Renesas on: + workflow_dispatch: push: paths: - 'src/**' diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml index 87c7b522e..8682d655a 100644 --- a/.github/workflows/build_riscv.yml +++ b/.github/workflows/build_riscv.yml @@ -1,6 +1,7 @@ name: Build RISC-V on: + workflow_dispatch: push: paths: - 'src/**' diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml index 4b743a686..45fc62f78 100644 --- a/.github/workflows/build_win_mac.yml +++ b/.github/workflows/build_win_mac.yml @@ -1,6 +1,7 @@ name: Build Windows/MacOS on: + workflow_dispatch: push: paths: - 'src/**' diff --git a/.github/workflows/cifuzz.yml b/.github/workflows/cifuzz.yml index 7314fd9e6..4c4b12a6b 100644 --- a/.github/workflows/cifuzz.yml +++ b/.github/workflows/cifuzz.yml @@ -1,5 +1,6 @@ name: CIFuzz on: + workflow_dispatch: pull_request: branches: - master diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 9ff666ed4..ce9f27c33 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -550,8 +550,7 @@ void cdch_close(uint8_t daddr) } } -bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) -{ +bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) { // TODO handle stall response, retry failed transfer ... TU_ASSERT(event == XFER_RESULT_SUCCESS); @@ -559,41 +558,40 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc); - if ( ep_addr == p_cdc->stream.tx.ep_addr ) - { + if ( ep_addr == p_cdc->stream.tx.ep_addr ) { // invoke tx complete callback to possibly refill tx fifo if (tuh_cdc_tx_complete_cb) tuh_cdc_tx_complete_cb(idx); - if ( 0 == tu_edpt_stream_write_xfer(&p_cdc->stream.tx) ) - { + if ( 0 == tu_edpt_stream_write_xfer(&p_cdc->stream.tx) ) { // If there is no data left, a ZLP should be sent if: // - xferred_bytes is multiple of EP Packet size and not zero tu_edpt_stream_write_zlp_if_needed(&p_cdc->stream.tx, xferred_bytes); } } - else if ( ep_addr == p_cdc->stream.rx.ep_addr ) - { - tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes); - + else if ( ep_addr == p_cdc->stream.rx.ep_addr ) { #if CFG_TUH_CDC_FTDI - // FTDI reserve 2 bytes for status if (p_cdc->serial_drid == SERIAL_DRIVER_FTDI) { - uint8_t status[2]; - tu_edpt_stream_read(&p_cdc->stream.rx, status, 2); - (void) status; // TODO handle status - } + // FTDI reserve 2 bytes for status + // FTDI status +// uint8_t status[2] = { +// p_cdc->stream.rx.ep_buf[0], +// p_cdc->stream.rx.ep_buf[1] +// }; + tu_edpt_stream_read_xfer_complete_offset(&p_cdc->stream.rx, xferred_bytes, 2); + }else #endif + { + tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes); + } // invoke receive callback if (tuh_cdc_rx_cb) tuh_cdc_rx_cb(idx); // prepare for next transfer if needed tu_edpt_stream_read_xfer(&p_cdc->stream.rx); - }else if ( ep_addr == p_cdc->ep_notif ) - { + }else if ( ep_addr == p_cdc->ep_notif ) { // TODO handle notification endpoint - }else - { + }else { TU_ASSERT(false); } diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h index d5541856c..db1ba974d 100644 --- a/src/common/tusb_private.h +++ b/src/common/tusb_private.h @@ -148,21 +148,26 @@ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s); // Must be called in the transfer complete callback TU_ATTR_ALWAYS_INLINE static inline -void tu_edpt_stream_read_xfer_complete(tu_edpt_stream_t* s, uint32_t xferred_bytes) -{ +void tu_edpt_stream_read_xfer_complete(tu_edpt_stream_t* s, uint32_t xferred_bytes) { tu_fifo_write_n(&s->ff, s->ep_buf, (uint16_t) xferred_bytes); } +// Same as tu_edpt_stream_read_xfer_complete but skip the first n bytes +TU_ATTR_ALWAYS_INLINE static inline +void tu_edpt_stream_read_xfer_complete_offset(tu_edpt_stream_t* s, uint32_t xferred_bytes, uint32_t skip_offset) { + if (skip_offset < xferred_bytes) { + tu_fifo_write_n(&s->ff, s->ep_buf + skip_offset, (uint16_t) (xferred_bytes - skip_offset)); + } +} + // Get the number of bytes available for reading TU_ATTR_ALWAYS_INLINE static inline -uint32_t tu_edpt_stream_read_available(tu_edpt_stream_t* s) -{ +uint32_t tu_edpt_stream_read_available(tu_edpt_stream_t* s) { return (uint32_t) tu_fifo_count(&s->ff); } TU_ATTR_ALWAYS_INLINE static inline -bool tu_edpt_stream_peek(tu_edpt_stream_t* s, uint8_t* ch) -{ +bool tu_edpt_stream_peek(tu_edpt_stream_t* s, uint8_t* ch) { return tu_fifo_peek(&s->ff, ch); } -- cgit v1.3.1 From b262164a35e9e305b67cb8d0c2188353db405200 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 26 May 2023 15:16:18 +0700 Subject: fix build with net_lwip_webserver example --- examples/device/CMakeLists.txt | 7 +- examples/device/net_lwip_webserver/CMakeLists.txt | 148 +++++++++++----------- src/CMakeLists.txt | 2 + 3 files changed, 80 insertions(+), 77 deletions(-) (limited to 'src') diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt index 89cfceeeb..5b077a5e1 100644 --- a/examples/device/CMakeLists.txt +++ b/examples/device/CMakeLists.txt @@ -22,12 +22,7 @@ family_add_subdirectory(hid_generic_inout) family_add_subdirectory(hid_multiple_interface) family_add_subdirectory(midi_test) family_add_subdirectory(msc_dual_lun) - -# FIXME temp skip net_lwip_webserver for imxrt for now -if (NOT ${FAMILY} STREQUAL "imxrt" AND NOT ${FAMILY} STREQUAL "mcx") - family_add_subdirectory(net_lwip_webserver) -endif() - +family_add_subdirectory(net_lwip_webserver) family_add_subdirectory(uac2_headset) family_add_subdirectory(usbtmc) family_add_subdirectory(video_capture) diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt index e7338c809..5225f7c42 100644 --- a/examples/device/net_lwip_webserver/CMakeLists.txt +++ b/examples/device/net_lwip_webserver/CMakeLists.txt @@ -1,83 +1,89 @@ cmake_minimum_required(VERSION 3.17) -set(TOP "../../..") -get_filename_component(TOP "${TOP}" REALPATH) +include(${CMAKE_CURRENT_LIST_DIR}/../../../hw/bsp/family_support.cmake) -if (EXISTS ${TOP}/lib/lwip/src) - include(${TOP}/hw/bsp/family_support.cmake) +set(LWIP ${TOP}/lib/lwip) +if (NOT EXISTS ${LWIP}/src) + MESSAGE(WARNING "lib/lwip submodule not found, please run 'python tools/get_deps.py lib/lwip' to fetch it") + return() +endif() - # gets PROJECT name for the example (e.g. -) - family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) +# gets PROJECT name for the example (e.g. -) +family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) - project(${PROJECT} C CXX ASM) +project(${PROJECT} C CXX ASM) - # Checks this example is valid for the family and initializes the project - family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) +# Checks this example is valid for the family and initializes the project +family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) - add_executable(${PROJECT}) +add_executable(${PROJECT}) - # Example source - target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c - ) +# Example source +target_sources(${PROJECT} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/src/main.c + ${CMAKE_CURRENT_LIST_DIR}/src/usb_descriptors.c + ) - # Example include - target_include_directories(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src - ${TOP}/lib/lwip/src/include - ${TOP}/lib/lwip/src/include/ipv4 - ${TOP}/lib/lwip/src/include/lwip/apps - ${TOP}/lib/networking - ) +# Example include +target_include_directories(${PROJECT} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/src + ${LWIP}/src/include + ${LWIP}/src/include/ipv4 + ${LWIP}/src/include/lwip/apps + ${TOP}/lib/networking + ) - target_sources(${PROJECT} PUBLIC - ${TOP}/lib/lwip/src/core/altcp.c - ${TOP}/lib/lwip/src/core/altcp_alloc.c - ${TOP}/lib/lwip/src/core/altcp_tcp.c - ${TOP}/lib/lwip/src/core/def.c - ${TOP}/lib/lwip/src/core/dns.c - ${TOP}/lib/lwip/src/core/inet_chksum.c - ${TOP}/lib/lwip/src/core/init.c - ${TOP}/lib/lwip/src/core/ip.c - ${TOP}/lib/lwip/src/core/mem.c - ${TOP}/lib/lwip/src/core/memp.c - ${TOP}/lib/lwip/src/core/netif.c - ${TOP}/lib/lwip/src/core/pbuf.c - ${TOP}/lib/lwip/src/core/raw.c - ${TOP}/lib/lwip/src/core/stats.c - ${TOP}/lib/lwip/src/core/sys.c - ${TOP}/lib/lwip/src/core/tcp.c - ${TOP}/lib/lwip/src/core/tcp_in.c - ${TOP}/lib/lwip/src/core/tcp_out.c - ${TOP}/lib/lwip/src/core/timeouts.c - ${TOP}/lib/lwip/src/core/udp.c - ${TOP}/lib/lwip/src/core/ipv4/autoip.c - ${TOP}/lib/lwip/src/core/ipv4/dhcp.c - ${TOP}/lib/lwip/src/core/ipv4/etharp.c - ${TOP}/lib/lwip/src/core/ipv4/icmp.c - ${TOP}/lib/lwip/src/core/ipv4/igmp.c - ${TOP}/lib/lwip/src/core/ipv4/ip4.c - ${TOP}/lib/lwip/src/core/ipv4/ip4_addr.c - ${TOP}/lib/lwip/src/core/ipv4/ip4_frag.c - ${TOP}/lib/lwip/src/netif/ethernet.c - ${TOP}/lib/lwip/src/netif/slipif.c - ${TOP}/lib/lwip/src/apps/http/httpd.c - ${TOP}/lib/lwip/src/apps/http/fs.c - ${TOP}/lib/networking/dhserver.c - ${TOP}/lib/networking/dnserver.c - ${TOP}/lib/networking/rndis_reports.c - ) +# lib/networking sources +target_sources(${PROJECT} PUBLIC + ${TOP}/lib/networking/dhserver.c + ${TOP}/lib/networking/dnserver.c + ${TOP}/lib/networking/rndis_reports.c + ) - # due to warnings from other net source, we need to prevent error from some of the warnings options - target_compile_options(${PROJECT} PUBLIC - -Wno-error=null-dereference - -Wno-error=conversion - -Wno-error=sign-conversion - -Wno-error=sign-compare - ) +# lwip sources +target_sources(${PROJECT} PUBLIC + ${LWIP}/src/core/altcp.c + ${LWIP}/src/core/altcp_alloc.c + ${LWIP}/src/core/altcp_tcp.c + ${LWIP}/src/core/def.c + ${LWIP}/src/core/dns.c + ${LWIP}/src/core/inet_chksum.c + ${LWIP}/src/core/init.c + ${LWIP}/src/core/ip.c + ${LWIP}/src/core/mem.c + ${LWIP}/src/core/memp.c + ${LWIP}/src/core/netif.c + ${LWIP}/src/core/pbuf.c + ${LWIP}/src/core/raw.c + ${LWIP}/src/core/stats.c + ${LWIP}/src/core/sys.c + ${LWIP}/src/core/tcp.c + ${LWIP}/src/core/tcp_in.c + ${LWIP}/src/core/tcp_out.c + ${LWIP}/src/core/timeouts.c + ${LWIP}/src/core/udp.c + ${LWIP}/src/core/ipv4/autoip.c + ${LWIP}/src/core/ipv4/dhcp.c + ${LWIP}/src/core/ipv4/etharp.c + ${LWIP}/src/core/ipv4/icmp.c + ${LWIP}/src/core/ipv4/igmp.c + ${LWIP}/src/core/ipv4/ip4.c + ${LWIP}/src/core/ipv4/ip4_addr.c + ${LWIP}/src/core/ipv4/ip4_frag.c + ${LWIP}/src/netif/ethernet.c + ${LWIP}/src/netif/slipif.c + ${LWIP}/src/apps/http/httpd.c + ${LWIP}/src/apps/http/fs.c + ) - # Configure compilation flags and libraries for the example... see the corresponding function - # in hw/bsp/FAMILY/family.cmake for details. - family_configure_device_example(${PROJECT}) -endif() +# due to warnings from other net source, we need to prevent error from some of the warnings options +target_compile_options(${PROJECT} PUBLIC + -Wno-error=null-dereference + -Wno-error=conversion + -Wno-error=sign-conversion + -Wno-error=sign-compare + ) + +# Configure compilation flags and libraries for the example... see the corresponding function +# in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT}) diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 0b99d8919..0d2f0975b 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -34,6 +34,8 @@ function(add_tinyusb TARGET) ) target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + # TODO for net driver, should be removed/changed + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../lib/networking ) # enable all possible warnings target_compile_options(${TARGET} PUBLIC -- cgit v1.3.1 From 7ac85d08c7aa59f35cbbf2657dd9be68d46e1fdc Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 26 May 2023 16:37:47 +0700 Subject: move lpc18 and rp2040 to cmake workflow since rp2040 often failed randomly with make --- .github/workflows/build_arm.yml | 3 +- .github/workflows/cmake_arm.yml | 19 ++- hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h | 8 +- hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h | 166 +++++++++++++++++++++ hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h | 8 +- hw/bsp/lpc55/boards/double_m33_express/board.cmake | 16 ++ hw/bsp/lpc55/family.cmake | 14 +- hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h | 8 +- hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h | 166 +++++++++++++++++++++ hw/bsp/saml2x/family.mk | 4 +- src/CMakeLists.txt | 47 ++++-- tools/get_deps.py | 4 +- 12 files changed, 429 insertions(+), 34 deletions(-) create mode 100644 hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/lpc55/boards/double_m33_express/board.cmake create mode 100644 hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h (limited to 'src') diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml index 8fbaba4c6..42c8eb7ce 100644 --- a/.github/workflows/build_arm.yml +++ b/.github/workflows/build_arm.yml @@ -35,12 +35,11 @@ jobs: # Alphabetical order - 'broadcom_32bit' - 'kinetis_k32l kinetis_kl' - - 'lpc11 lpc13 lpc15 lpc17 lpc18' + - 'lpc11 lpc13 lpc15 lpc17' - 'lpc51 lpc54 lpc55' - 'mm32 msp432e4' - 'nrf' - 'ra' - - 'rp2040' - 'samd11 samd21' - 'samd51 same5x' - 'saml2x' diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml index e7991252d..f3989f239 100644 --- a/.github/workflows/cmake_arm.yml +++ b/.github/workflows/cmake_arm.yml @@ -32,9 +32,11 @@ jobs: fail-fast: false matrix: family: - # Alphabetical order - - 'mcx' - - 'imxrt' + # Alphabetical order + - 'lpc18' + - 'mcx' + - 'imxrt' + - 'rp2040' steps: - name: Setup Python uses: actions/setup-python@v4 @@ -52,8 +54,19 @@ jobs: - name: Checkout TinyUSB uses: actions/checkout@v3 + - name: Checkout pico-sdk for rp2040 + if: matrix.family == 'rp2040' + uses: actions/checkout@v3 + with: + repository: raspberrypi/pico-sdk + ref: develop + path: pico-sdk + - name: Get Dependencies run: python3 tools/get_deps.py ${{ matrix.family }} - name: Build run: python tools/build_cmake.py ${{ matrix.family }} + env: + # for rp2040, there is no harm if defined for other families + PICO_SDK_PATH: ${{ github.workspace }}/pico-sdk diff --git a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h index c8d94f9ed..c1928fbcd 100644 --- a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h @@ -49,10 +49,10 @@ extern uint32_t SystemCoreClock; #endif /* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 1 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) #define configUSE_PREEMPTION 1 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 diff --git a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..323c1a0a4 --- /dev/null +++ b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,166 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// IAR assembler have limited preprocessor support and it only need following macros: +#ifndef __IASMARM__ +// FIXME cause redundant-decls warnings +extern uint32_t SystemCoreClock; +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 0 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 2 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* Define to trap errors during development. */ +// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) + #define configASSERT(_exp) \ + do {\ + if ( !(_exp) ) { \ + volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ + if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \ + taskDISABLE_INTERRUPTS(); \ + __asm("BKPT #0\n"); \ + }\ + }\ + } while(0) +#else + #define configASSERT( x ) +#endif + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS 3 + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<DHCSR */ \ + if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \ + taskDISABLE_INTERRUPTS(); \ + __asm("BKPT #0\n"); \ + }\ + }\ + } while(0) +#else + #define configASSERT( x ) +#endif + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS 3 + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< Date: Sun, 28 May 2023 15:40:01 +0100 Subject: Fixes bug in tuh_msc_ready --- src/class/msc/msc_host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c index 138443de4..d32c0adb0 100644 --- a/src/class/msc/msc_host.c +++ b/src/class/msc/msc_host.c @@ -118,7 +118,7 @@ bool tuh_msc_mounted(uint8_t dev_addr) bool tuh_msc_ready(uint8_t dev_addr) { msch_interface_t* p_msc = get_itf(dev_addr); - return p_msc->mounted && !usbh_edpt_busy(dev_addr, p_msc->ep_in); + return p_msc->mounted && !usbh_edpt_busy(dev_addr, p_msc->ep_in) && !usbh_edpt_busy(dev_addr, p_msc->ep_out); } //--------------------------------------------------------------------+ -- cgit v1.3.1 From 8ad024e51bbc663678d8a357f91021bd39222246 Mon Sep 17 00:00:00 2001 From: Ivo Popov Date: Sun, 9 Apr 2023 19:10:01 -0400 Subject: Even when we get an empty "status change" interrupt from the hub, schedule another interrupt poll. During enumeration, when there are multiple devices attached to the hub as it's plugged into the Pi Pico, enumeration hangs, because we get a "status change" callback with value zero. With this patch, we retry several times on "zero" status change callbacks, until eventually we succeed. This is the cheapo hub that exhibits this behavior, but I assume it's not the only one: https://www.amazon.com/gp/product/B083RQMC7S. While debugging this, I consulted the implementation in the Linux kernel. There, hub setup explicitly checks each port individually, before starting to depend on "status change" interrupts: https://elixir.bootlin.com/linux/latest/source/drivers/usb/core/hub.c#L1133. We probably should do something like that here, but it's a much bigger change. --- src/host/hub.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src') diff --git a/src/host/hub.c b/src/host/hub.c index 85bf22b3e..5b2db547d 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -361,6 +361,13 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32 break; } } + + // The status change event was neither for the hub, nor for any of + // its ports. (For example `p_hub->status_change == 0`.) This + // shouldn't happen, but it does with some devices. Initiate the + // next interrupt poll here, because we've scheduled no other work + // whose completion can initiate it. + hub_edpt_status_xfer(dev_addr); } // NOTE: next status transfer is queued by usbh.c after handling this request -- cgit v1.3.1 From 5c428d35a61f7d877cba19d9e094bd519ae91997 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 29 May 2023 13:27:20 +0700 Subject: check status_change is not zero first --- src/host/hub.c | 42 ++++++++++++++++++------------------------ 1 file changed, 18 insertions(+), 24 deletions(-) (limited to 'src') diff --git a/src/host/hub.c b/src/host/hub.c index 5b2db547d..0807c2023 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -327,51 +327,45 @@ static void connection_clear_conn_change_complete (tuh_xfer_t* xfer); static void connection_port_reset_complete (tuh_xfer_t* xfer); // callback as response of interrupt endpoint polling -bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) -{ +bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { (void) xferred_bytes; // TODO can be more than 1 for hub with lots of ports (void) ep_addr; TU_ASSERT(result == XFER_RESULT_SUCCESS); hub_interface_t* p_hub = get_itf(dev_addr); - TU_LOG2(" Hub Status Change = 0x%02X\r\n", p_hub->status_change); + uint8_t const status_change = p_hub->status_change; + TU_LOG2(" Hub Status Change = 0x%02X\r\n", status_change); - // Hub bit 0 is for the hub device events - if (tu_bit_test(p_hub->status_change, 0)) - { - if (hub_port_get_status(dev_addr, 0, &p_hub->hub_status, hub_get_status_complete, 0) == false) - { + if ( status_change == 0 ) { + // The status change event was neither for the hub, nor for any of its ports. + // This shouldn't happen, but it does with some devices. + // Initiate the next interrupt poll here. + hub_edpt_status_xfer(dev_addr); + return true; + } + + if (tu_bit_test(status_change, 0)) { + // Hub bit 0 is for the hub device events + if (hub_port_get_status(dev_addr, 0, &p_hub->hub_status, hub_get_status_complete, 0) == false) { //Hub status control transfer failed, retry hub_edpt_status_xfer(dev_addr); } } - else - { + else { // Hub bits 1 to n are hub port events - for (uint8_t port=1; port <= p_hub->port_count; port++) - { - if ( tu_bit_test(p_hub->status_change, port) ) - { - if (hub_port_get_status(dev_addr, port, &p_hub->port_status, hub_port_get_status_complete, 0) == false) - { + for (uint8_t port=1; port <= p_hub->port_count; port++) { + if ( tu_bit_test(status_change, port) ) { + if (hub_port_get_status(dev_addr, port, &p_hub->port_status, hub_port_get_status_complete, 0) == false) { //Hub status control transfer failed, retry hub_edpt_status_xfer(dev_addr); } break; } } - - // The status change event was neither for the hub, nor for any of - // its ports. (For example `p_hub->status_change == 0`.) This - // shouldn't happen, but it does with some devices. Initiate the - // next interrupt poll here, because we've scheduled no other work - // whose completion can initiate it. - hub_edpt_status_xfer(dev_addr); } // NOTE: next status transfer is queued by usbh.c after handling this request - return true; } -- cgit v1.3.1 From 20ef6c4ef7f7fa7130352ae0c0984692a9719b35 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 29 May 2023 13:29:11 +0700 Subject: slightly clean up --- src/host/hub.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src') diff --git a/src/host/hub.c b/src/host/hub.c index 0807c2023..182bd6ce8 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -341,8 +341,7 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32 // The status change event was neither for the hub, nor for any of its ports. // This shouldn't happen, but it does with some devices. // Initiate the next interrupt poll here. - hub_edpt_status_xfer(dev_addr); - return true; + return hub_edpt_status_xfer(dev_addr); } if (tu_bit_test(status_change, 0)) { -- cgit v1.3.1 From 70a92291fe84eb57844a331749ceecb6d2f1f544 Mon Sep 17 00:00:00 2001 From: Dave Nadler Date: Thu, 1 Jun 2023 10:58:03 -0400 Subject: Fix diagnostic format string (missing %u) --- src/host/usbh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 7b265c742..6159044ab 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1179,7 +1179,7 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu TU_LOG_USBH("Device unplugged address = %u\r\n", daddr); if (is_hub_addr(daddr)) { - TU_LOG(USBH_DEBUG, " is a HUB device\r\n", daddr); + TU_LOG(USBH_DEBUG, " is a HUB device %u\r\n", daddr); // Submit removed event If the device itself is a hub (un-rolled recursive) // TODO a better to unroll recursrive is using array of removing_hubs and mark it here -- cgit v1.3.1 From e8b7f21af6e5e994ece7c989202767732f23809e Mon Sep 17 00:00:00 2001 From: Dave Nadler Date: Thu, 1 Jun 2023 12:57:44 -0400 Subject: For FreeRTOS kernel-aware debugging, when queue registry is enabled, label tinyUSB queue --- src/osal/osal_freertos.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index 477f64892..0b1b11589 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -169,11 +169,16 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) { -#if configSUPPORT_STATIC_ALLOCATION - return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq); -#else - return xQueueCreate(qdef->depth, qdef->item_sz); -#endif + osal_queue_t q; + #if configSUPPORT_STATIC_ALLOCATION + q = xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq); + #else + q = xQueueCreate(qdef->depth, qdef->item_sz); + #endif + #if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0) + vQueueAddToRegistry(q, "tinyUSB"); + #endif + return q; } TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) -- cgit v1.3.1 From e7090c75148820ff3a4ad60c718684c46c954c18 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 2 Jun 2023 11:42:17 +0700 Subject: cmake refactor --- .github/workflows/build_arm.yml | 2 +- .github/workflows/cmake_arm.yml | 9 ++-- hw/bsp/family_support.cmake | 116 +++++++++++++++++++++++++--------------- hw/bsp/imxrt/family.cmake | 26 ++------- hw/bsp/lpc18/family.cmake | 23 ++------ hw/bsp/lpc55/family.cmake | 25 ++------- hw/bsp/mcx/family.cmake | 23 ++------ hw/bsp/nrf/family.cmake | 23 ++------ hw/bsp/stm32g0/family.cmake | 23 ++------ hw/bsp/stm32g4/family.cmake | 25 ++------- src/CMakeLists.txt | 4 ++ tools/build_cmake.py | 10 ++-- 12 files changed, 112 insertions(+), 197 deletions(-) (limited to 'src') diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml index 3a2daab08..a7c7fd1e1 100644 --- a/.github/workflows/build_arm.yml +++ b/.github/workflows/build_arm.yml @@ -46,7 +46,7 @@ jobs: - 'stm32f0 stm32f1 stm32f2 stm32f3' - 'stm32f4' - 'stm32f7' - - 'stm32g4 stm32h7' + - 'stm32h7' - 'stm32l0 stm32l4 stm32u5 stm32wb' - 'tm4c123 xmc4000' steps: diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml index 2e74c304c..2ca8e32f5 100644 --- a/.github/workflows/cmake_arm.yml +++ b/.github/workflows/cmake_arm.yml @@ -38,6 +38,7 @@ jobs: - 'imxrt' - 'rp2040' - 'stm32g0' + - 'stm32g4' steps: - name: Setup Python uses: actions/setup-python@v4 @@ -75,11 +76,11 @@ jobs: # Upload binaries for hardware test with self-hosted - name: Prepare rp2040 Artifacts if: contains(matrix.family, 'rp2040') && github.repository_owner == 'hathach' - working-directory: ${{github.workspace}}/cmake-build-ci-raspberry_pi_pico + working-directory: ${{github.workspace}}/cmake-build/cmake-build-raspberry_pi_pico run: | - find device/ -name "*.elf" -exec mv {} ../ \; - # find host/ -name "*.elf" -exec mv {} ../ \; - # find dual/ -name "*.elf" -exec mv {} ../ \; + find device/ -name "*.elf" -exec mv {} ../../ \; + # find host/ -name "*.elf" -exec mv {} ../../ \; + # find dual/ -name "*.elf" -exec mv {} ../../ \; - name: Upload Artifacts for rp2040 if: contains(matrix.family,'rp2040') && github.repository_owner == 'hathach' diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index d9b8bbbe9..fdc9580ae 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -84,8 +84,8 @@ endfunction() function(family_initialize_project PROJECT DIR) - # set output suffix to .elf (skip espressif) - if(NOT FAMILY STREQUAL "espressif") + # set output suffix to .elf (skip espressif and rp2040) + if(NOT FAMILY STREQUAL "espressif" AND NOT FAMILY STREQUAL "rp2040") set(CMAKE_EXECUTABLE_SUFFIX .elf PARENT_SCOPE) endif() @@ -144,6 +144,11 @@ function(family_add_default_example_warnings TARGET) endfunction() +#------------------------------------ +# Main target configure +#------------------------------------ + +# Add common configuration to example function(family_configure_common TARGET) # run size after build add_custom_command(TARGET ${TARGET} POST_BUILD @@ -158,6 +163,66 @@ function(family_configure_common TARGET) endfunction() +# configure an executable target to link to tinyusb in device mode, and add the board implementation +function(family_configure_device_example TARGET) + # default implementation is empty, the function should be redefined in the FAMILY/family.cmake +endfunction() + + +# configure an executable target to link to tinyusb in host mode, and add the board implementation +function(family_configure_host_example TARGET) + # default implementation is empty, the function should be redefined in the FAMILY/family.cmake +endfunction() + + +# Add tinyusb to example +function(family_add_tinyusb TARGET OPT_MCU) + # tinyusb target is built for each example since it depends on example's tusb_config.h + set(TINYUSB_TARGET_PREFIX ${TARGET}-) + add_library(${TARGET}-tinyusb_config INTERFACE) + + target_include_directories(${TARGET}-tinyusb_config INTERFACE + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) + target_compile_definitions(${TARGET}-tinyusb_config INTERFACE + CFG_TUSB_MCU=${OPT_MCU} + ) + + # tinyusb's CMakeList.txt + add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) +endfunction() + + +# Add freeRTOS support to example +function(family_add_freertos TARGET) + # freeros config + if (NOT TARGET freertos_config) + add_library(freertos_config INTERFACE) + target_include_directories(freertos_config SYSTEM INTERFACE + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig + ) + endif() + + # freertos kernel should be generic as freertos_config however, CMAKE complains with missing variable + # such as CMAKE_C_COMPILE_OBJECT + if (NOT TARGET freertos_kernel) + add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel) + endif () + + # Add FreeRTOS option to tinyusb_config + target_compile_definitions(${TARGET}-tinyusb_config INTERFACE + CFG_TUSB_OS=OPT_OS_FREERTOS + ) + # link tinyusb with freeRTOS kernel + target_link_libraries(${TARGET}-tinyusb PUBLIC + freertos_kernel + ) + target_link_libraries(${TARGET} PUBLIC + freertos_kernel + ) +endfunction() + + # Add bin/hex output function(family_add_bin_hex TARGET) add_custom_command(TARGET ${TARGET} POST_BUILD @@ -167,6 +232,10 @@ function(family_add_bin_hex TARGET) endfunction() +#---------------------------------- +# Flashing target +#---------------------------------- + # Add flash jlink target function(family_flash_jlink TARGET) if (NOT DEFINED JLINKEXE) @@ -233,48 +302,7 @@ function(family_flash_nxplink TARGET) endfunction() -# configure an executable target to link to tinyusb in device mode, and add the board implementation -function(family_configure_device_example TARGET) - # default implementation is empty, the function should be redefined in the FAMILY/family.cmake -endfunction() - - -# configure an executable target to link to tinyusb in host mode, and add the board implementation -function(family_configure_host_example TARGET) - # default implementation is empty, the function should be redefined in the FAMILY/family.cmake -endfunction() - - -# Add freeRTOS support to example, can be overridden by FAMILY/family.cmake -function(family_add_freertos TARGET) - # freeros config - if (NOT TARGET freertos_config) - add_library(freertos_config INTERFACE) - target_include_directories(freertos_config SYSTEM INTERFACE - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig - ) - endif() - - # freertos kernel should be generic as freertos_config however, CMAKE complains with missing variable - # such as CMAKE_C_COMPILE_OBJECT - if (NOT TARGET freertos_kernel) - add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel) - endif () - - # Add FreeRTOS option to tinyusb_config - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE - CFG_TUSB_OS=OPT_OS_FREERTOS - ) - # link tinyusb with freeRTOS kernel - target_link_libraries(${TARGET}-tinyusb PUBLIC - freertos_kernel - ) - target_link_libraries(${TARGET} PUBLIC - freertos_kernel - ) -endfunction() - - +# family specific: can override above functions include(${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake) if (NOT FAMILY_MCUS) diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 49a4a9281..3c156285c 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -36,7 +36,6 @@ if (NOT TARGET ${BOARD_TARGET}) ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c ) target_compile_definitions(${BOARD_TARGET} PUBLIC - CFG_TUSB_MCU=OPT_MCU_MIMXRT __ARMVFP__=0 __ARMFPV5__=0 XIP_EXTERNAL_FLASH=1 @@ -100,33 +99,16 @@ function(family_configure_example TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) - #---------- TinyUSB ---------- - # tinyusb target is built for each example since it depends on example's tusb_config.h - set(TINYUSB_TARGET_PREFIX ${TARGET}-) - add_library(${TARGET}-tinyusb_config INTERFACE) - - target_include_directories(${TARGET}-tinyusb_config INTERFACE - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE - CFG_TUSB_MCU=OPT_MCU_MIMXRT - ) - - # tinyusb's CMakeList.txt - add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) + # Add TinyUSB + family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT) # Link dependencies target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb) - # group target (not yet supported by clion) - set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config - PROPERTIES FOLDER ${TARGET}_sub - ) - - #---------- Flash ---------- + # Flashing family_flash_jlink(${TARGET}) family_flash_nxplink(${TARGET}) - family_flash_pyocd(${TARGET}) + #family_flash_pyocd(${TARGET}) endfunction() diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake index 515348e10..a133e7217 100644 --- a/hw/bsp/lpc18/family.cmake +++ b/hw/bsp/lpc18/family.cmake @@ -83,30 +83,13 @@ function(family_configure_example TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) - #---------- TinyUSB ---------- - # tinyusb target is built for each example since it depends on example's tusb_config.h - set(TINYUSB_TARGET_PREFIX ${TARGET}-) - add_library(${TARGET}-tinyusb_config INTERFACE) - - target_include_directories(${TARGET}-tinyusb_config INTERFACE - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE - CFG_TUSB_MCU=OPT_MCU_LPC18XX - ) - - # tinyusb's CMakeList.txt - add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) + # Add TinyUSB + family_add_tinyusb(${TARGET} OPT_MCU_LPC18XX) # Link dependencies target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb) - # group target (not yet supported by clion) - set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config - PROPERTIES FOLDER ${TARGET}_sub - ) - - #---------- Flash ---------- + # Flashing family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake index eb163bde7..25eed48de 100644 --- a/hw/bsp/lpc55/family.cmake +++ b/hw/bsp/lpc55/family.cmake @@ -109,33 +109,16 @@ function(family_configure_example TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) - #---------- TinyUSB ---------- - # tinyusb target is built for each example since it depends on example's tusb_config.h - set(TINYUSB_TARGET_PREFIX ${TARGET}-) - add_library(${TARGET}-tinyusb_config INTERFACE) - - target_include_directories(${TARGET}-tinyusb_config INTERFACE - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE - CFG_TUSB_MCU=OPT_MCU_LPC55XX - ) - - # tinyusb's CMakeList.txt - add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) + # Add TinyUSB + family_add_tinyusb(${TARGET} OPT_MCU_LPC55XX) # Link dependencies target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb) - # group target (not yet supported by clion) - set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config - PROPERTIES FOLDER ${TARGET}_sub - ) - - #---------- Flash ---------- + # Flashing family_flash_jlink(${TARGET}) family_flash_nxplink(${TARGET}) - family_flash_pyocd(${TARGET}) + #family_flash_pyocd(${TARGET}) endfunction() diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake index d5a17f584..17f54a53b 100644 --- a/hw/bsp/mcx/family.cmake +++ b/hw/bsp/mcx/family.cmake @@ -91,30 +91,13 @@ function(family_configure_example TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) - #---------- TinyUSB ---------- - # tinyusb target is built for each example since it depends on example's tusb_config.h - set(TINYUSB_TARGET_PREFIX ${TARGET}-) - add_library(${TARGET}-tinyusb_config INTERFACE) - - target_include_directories(${TARGET}-tinyusb_config INTERFACE - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE - CFG_TUSB_MCU=OPT_MCU_MCXN9 - ) - - # tinyusb's CMakeList.txt - add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) + # Add TinyUSB + family_add_tinyusb(${TARGET} OPT_MCU_MCXN9) # Link dependencies target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb) - # group target (not yet supported by clion) - set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config - PROPERTIES FOLDER ${TARGET}_sub - ) - - #---------- Flash ---------- + # Flashing family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) #family_flash_pyocd(${TARGET}) diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 71067c8ae..2c5d7a431 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -98,30 +98,13 @@ function(family_configure_example TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) - #---------- TinyUSB ---------- - # tinyusb target is built for each example since it depends on example's tusb_config.h - set(TINYUSB_TARGET_PREFIX ${TARGET}-) - add_library(${TARGET}-tinyusb_config INTERFACE) - - target_include_directories(${TARGET}-tinyusb_config INTERFACE - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE - CFG_TUSB_MCU=OPT_MCU_NRF5X - ) - - # tinyusb's CMakeList.txt - add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) + # Add TinyUSB + family_add_tinyusb(${TARGET} OPT_MCU_NRF5X) # Link dependencies target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb) - # group target (not yet supported by clion) - set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config - PROPERTIES FOLDER ${TARGET}_sub - ) - - #---------- Flash ---------- + # Flashing family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake index 9674bc759..184dc6062 100644 --- a/hw/bsp/stm32g0/family.cmake +++ b/hw/bsp/stm32g0/family.cmake @@ -96,30 +96,13 @@ function(family_configure_example TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) - #---------- TinyUSB ---------- - # tinyusb target is built for each example since it depends on example's tusb_config.h - set(TINYUSB_TARGET_PREFIX ${TARGET}-) - add_library(${TARGET}-tinyusb_config INTERFACE) - - target_include_directories(${TARGET}-tinyusb_config INTERFACE - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE - CFG_TUSB_MCU=OPT_MCU_STM32G0 - ) - - # tinyusb's CMakeList.txt - add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) + # Add TinyUSB + family_add_tinyusb(${TARGET} OPT_MCU_STM32G0) # Link dependencies target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb) - # group target (not yet supported by clion) - set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config - PROPERTIES FOLDER ${TARGET}_sub - ) - - #---------- Flash ---------- + # Flashing family_flash_stlink(${TARGET}) #family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake index 1de6fd674..5578a9b6c 100644 --- a/hw/bsp/stm32g4/family.cmake +++ b/hw/bsp/stm32g4/family.cmake @@ -12,7 +12,7 @@ set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY}) set(CMSIS_5 ${TOP}/lib/CMSIS_5) # enable LTO -#set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE) +set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE) # toolchain set up set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") @@ -96,30 +96,13 @@ function(family_configure_example TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) - #---------- TinyUSB ---------- - # tinyusb target is built for each example since it depends on example's tusb_config.h - set(TINYUSB_TARGET_PREFIX ${TARGET}-) - add_library(${TARGET}-tinyusb_config INTERFACE) - - target_include_directories(${TARGET}-tinyusb_config INTERFACE - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE - CFG_TUSB_MCU=OPT_MCU_STM32G4 - ) - - # tinyusb's CMakeList.txt - add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) + # Add TinyUSB + family_add_tinyusb(${TARGET} OPT_MCU_STM32G4) # Link dependencies target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb) - # group target (not yet supported by clion) - set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config - PROPERTIES FOLDER ${TARGET}_sub - ) - - #---------- Flash ---------- + # Flashing family_flash_stlink(${TARGET}) #family_flash_jlink(${TARGET}) endfunction() diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 396737ed5..ad9fbc7c0 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -96,3 +96,7 @@ endif() target_link_libraries(${TINYUSB_TARGET} PUBLIC ${TINYUSB_CONFIG_TARGET} ) + +# export target name +# set(TINYUSB_TARGET ${TINYUSB_TARGET} PARENT_SCOPE) +# set(TINYUSB_CONFIG_TARGET ${TINYUSB_CONFIG_TARGET} PARENT_SCOPE) diff --git a/tools/build_cmake.py b/tools/build_cmake.py index 88d27dfb8..d85726213 100644 --- a/tools/build_cmake.py +++ b/tools/build_cmake.py @@ -34,13 +34,15 @@ def build_family(family, make_option): for board in all_boards: start_time = time.monotonic() + build_dir = f"cmake-build/cmake-build-{board}" + # Generate build - r = subprocess.run(f"cmake examples -B cmake-build-ci-{board} -G \"Ninja\" -DFAMILY={family} -DBOARD" + r = subprocess.run(f"cmake examples -B {build_dir} -G \"Ninja\" -DFAMILY={family} -DBOARD" f"={board}", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) # Build if r.returncode == 0: - r = subprocess.run(f"cmake --build cmake-build-ci-{board}", shell=True, stdout=subprocess.PIPE, + r = subprocess.run(f"cmake --build {build_dir}", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) duration = time.monotonic() - start_time @@ -71,10 +73,10 @@ if __name__ == '__main__': if make_iar_option not in sys.argv: make_iar_option = '' - # If family are not specified in arguments, build all + # If family are not specified in arguments, build all supported all_families = [] for entry in os.scandir("hw/bsp"): - if entry.is_dir() and os.path.isdir(entry.path + "/boards") and entry.name != 'espressif': + if entry.is_dir() and entry.name != 'espressif' and os.path.isfile(entry.path + "/family.cmake"): all_families.append(entry.name) filter_with_input(all_families) all_families.sort() -- cgit v1.3.1 From fcf77914546496d88d5915223095d93bb63c67fe Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 2 Jun 2023 13:27:18 +0700 Subject: add IAR support for G0 with cmake --- examples/device/net_lwip_webserver/CMakeLists.txt | 16 +-- hw/bsp/family_support.cmake | 108 +++++++++++---------- hw/bsp/imxrt/family.cmake | 4 +- hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake | 2 +- hw/bsp/lpc18/boards/mcb1800/board.cmake | 2 +- hw/bsp/lpc18/family.cmake | 2 +- hw/bsp/lpc55/boards/double_m33_express/board.cmake | 2 +- hw/bsp/lpc55/family.cmake | 4 +- hw/bsp/nrf/boards/pca10056/board.cmake | 2 +- hw/bsp/nrf/boards/pca10095/board.cmake | 2 +- hw/bsp/nrf/family.cmake | 4 +- hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake | 8 +- hw/bsp/stm32g0/family.cmake | 86 ++++++++-------- hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake | 8 +- hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake | 8 +- hw/bsp/stm32g4/family.cmake | 4 +- src/CMakeLists.txt | 2 + tools/cmake/cpu/cortex-m0plus.cmake | 12 ++- tools/cmake/toolchain/arm_gcc.cmake | 14 ++- tools/cmake/toolchain/arm_iar.cmake | 34 +++++++ tools/cmake/toolchain/set_flags.cmake | 17 +--- 21 files changed, 196 insertions(+), 145 deletions(-) create mode 100644 tools/cmake/toolchain/arm_iar.cmake (limited to 'src') diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt index 5225f7c42..2c21aa52b 100644 --- a/examples/device/net_lwip_webserver/CMakeLists.txt +++ b/examples/device/net_lwip_webserver/CMakeLists.txt @@ -77,12 +77,16 @@ target_sources(${PROJECT} PUBLIC ) # due to warnings from other net source, we need to prevent error from some of the warnings options -target_compile_options(${PROJECT} PUBLIC - -Wno-error=null-dereference - -Wno-error=conversion - -Wno-error=sign-conversion - -Wno-error=sign-compare - ) +if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_compile_options(${PROJECT} PUBLIC + -Wno-error=null-dereference + -Wno-error=conversion + -Wno-error=sign-conversion + -Wno-error=sign-compare + ) +elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + +endif () # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index fdc9580ae..e801f0116 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -97,53 +97,6 @@ function(family_initialize_project PROJECT DIR) endfunction() -function(family_add_default_example_warnings TARGET) - target_compile_options(${TARGET} PUBLIC - -Wall - -Wextra - -Werror - -Wfatal-errors - -Wdouble-promotion - -Wfloat-equal - -Wshadow - -Wwrite-strings - -Wsign-compare - -Wmissing-format-attribute - -Wunreachable-code - -Wcast-align - -Wcast-qual - -Wnull-dereference - -Wuninitialized - -Wunused - -Wredundant-decls - #-Wstrict-prototypes - #-Werror-implicit-function-declaration - #-Wundef - ) - - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0) - target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") - endif() - - # GCC 10 - if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 10.0) - target_compile_options(${TARGET} PUBLIC -Wconversion) - endif() - - # GCC 8 - if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 8.0) - target_compile_options(${TARGET} PUBLIC -Wcast-function-type -Wstrict-overflow) - endif() - - # GCC 6 - if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 6.0) - target_compile_options(${TARGET} PUBLIC -Wno-strict-aliasing) - endif() - endif() -endfunction() - - #------------------------------------ # Main target configure #------------------------------------ @@ -155,11 +108,13 @@ function(family_configure_common TARGET) COMMAND ${CMAKE_SIZE} $ ) - # Generate map file - target_link_options(${TARGET} PUBLIC - # link map - "LINKER:-Map=$.map" - ) + if (CMAKE_C_COMPILER_ID STREQUAL "GCC") + # Generate map file + target_link_options(${TARGET} PUBLIC + # link map + "LINKER:-Map=$.map" + ) + endif() endfunction() @@ -198,7 +153,7 @@ function(family_add_freertos TARGET) # freeros config if (NOT TARGET freertos_config) add_library(freertos_config INTERFACE) - target_include_directories(freertos_config SYSTEM INTERFACE + target_include_directories(freertos_config INTERFACE ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig ) endif() @@ -223,6 +178,53 @@ function(family_add_freertos TARGET) endfunction() +function(family_add_default_example_warnings TARGET) + target_compile_options(${TARGET} PUBLIC + -Wall + -Wextra + -Werror + -Wfatal-errors + -Wdouble-promotion + -Wfloat-equal + -Wshadow + -Wwrite-strings + -Wsign-compare + -Wmissing-format-attribute + -Wunreachable-code + -Wcast-align + -Wcast-qual + -Wnull-dereference + -Wuninitialized + -Wunused + -Wredundant-decls + #-Wstrict-prototypes + #-Werror-implicit-function-declaration + #-Wundef + ) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0) + target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") + endif() + + # GCC 10 + if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 10.0) + target_compile_options(${TARGET} PUBLIC -Wconversion) + endif() + + # GCC 8 + if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 8.0) + target_compile_options(${TARGET} PUBLIC -Wcast-function-type -Wstrict-overflow) + endif() + + # GCC 6 + if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 6.0) + target_compile_options(${TARGET} PUBLIC -Wno-strict-aliasing) + endif() + endif() +endfunction() + + # Add bin/hex output function(family_add_bin_hex TARGET) add_custom_command(TARGET ${TARGET} POST_BUILD diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 3c156285c..b5d47614e 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -53,7 +53,7 @@ if (NOT TARGET ${BOARD_TARGET}) update_board(${BOARD_TARGET}) if (NOT DEFINED LD_FILE_${TOOLCHAIN}) - set(LD_FILE_gcc ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld) + set(LD_FILE_GCC ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld) endif () if (TOOLCHAIN STREQUAL "gcc") @@ -61,7 +61,7 @@ if (NOT TARGET ${BOARD_TARGET}) ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S ) target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_gcc}" + "LINKER:--script=${LD_FILE_GCC}" # nanolib --specs=nosys.specs --specs=nano.specs diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake index b540012a4..00686ca01 100644 --- a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake +++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake @@ -4,7 +4,7 @@ set(JLINK_DEVICE LPC18S37) set(PYOCD_TARGET LPC18S37) set(NXPLINK_DEVICE LPC18S37:LPCXPRESSO18S37) -set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/lpc1837.ld) +set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/lpc1837.ld) function(update_board TARGET) # nothing to do diff --git a/hw/bsp/lpc18/boards/mcb1800/board.cmake b/hw/bsp/lpc18/boards/mcb1800/board.cmake index 1efeafd12..cfc2739e3 100644 --- a/hw/bsp/lpc18/boards/mcb1800/board.cmake +++ b/hw/bsp/lpc18/boards/mcb1800/board.cmake @@ -4,7 +4,7 @@ set(JLINK_DEVICE LPC1857) set(PYOCD_TARGET LPC1857) set(NXPLINK_DEVICE LPC1857:MCB1857) -set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/lpc1857.ld) +set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/lpc1857.ld) function(update_board TARGET) # nothing to do diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake index a133e7217..38b0f61fc 100644 --- a/hw/bsp/lpc18/family.cmake +++ b/hw/bsp/lpc18/family.cmake @@ -48,7 +48,7 @@ if (NOT TARGET ${BOARD_TARGET}) if (TOOLCHAIN STREQUAL "gcc") target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_gcc}" + "LINKER:--script=${LD_FILE_GCC}" # nanolib --specs=nosys.specs --specs=nano.specs diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.cmake b/hw/bsp/lpc55/boards/double_m33_express/board.cmake index 7c46c075e..62b0993dc 100644 --- a/hw/bsp/lpc55/boards/double_m33_express/board.cmake +++ b/hw/bsp/lpc55/boards/double_m33_express/board.cmake @@ -5,7 +5,7 @@ set(JLINK_DEVICE LPC55S69) set(PYOCD_TARGET LPC55S69) set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69) -set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/LPC55S69_cm33_core0_uf2.ld) +set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/LPC55S69_cm33_core0_uf2.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake index 25eed48de..967ed3fa6 100644 --- a/hw/bsp/lpc55/family.cmake +++ b/hw/bsp/lpc55/family.cmake @@ -65,7 +65,7 @@ if (NOT TARGET ${BOARD_TARGET}) update_board(${BOARD_TARGET}) if (NOT DEFINED LD_FILE_${TOOLCHAIN}) - set(LD_FILE_gcc ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) + set(LD_FILE_GCC ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) endif () if (TOOLCHAIN STREQUAL "gcc") @@ -74,7 +74,7 @@ if (NOT TARGET ${BOARD_TARGET}) ) target_link_options(${BOARD_TARGET} PUBLIC # linker file - "LINKER:--script=${LD_FILE_gcc}" + "LINKER:--script=${LD_FILE_GCC}" # nanolib --specs=nosys.specs --specs=nano.specs diff --git a/hw/bsp/nrf/boards/pca10056/board.cmake b/hw/bsp/nrf/boards/pca10056/board.cmake index cc8ef2fcb..3137c4fcd 100644 --- a/hw/bsp/nrf/boards/pca10056/board.cmake +++ b/hw/bsp/nrf/boards/pca10056/board.cmake @@ -1,5 +1,5 @@ set(MCU_VARIANT nrf52840) -set(LD_FILE_gcc ${NRFX_DIR}/mdk/nrf52840_xxaa.ld) +set(LD_FILE_GCC ${NRFX_DIR}/mdk/nrf52840_xxaa.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake index e90d76e91..a0562c738 100644 --- a/hw/bsp/nrf/boards/pca10095/board.cmake +++ b/hw/bsp/nrf/boards/pca10095/board.cmake @@ -1,5 +1,5 @@ set(MCU_VARIANT nrf5340_application) -set(LD_FILE_gcc ${NRFX_DIR}/mdk/nrf5340_xxaa_application.ld) +set(LD_FILE_GCC ${NRFX_DIR}/mdk/nrf5340_xxaa_application.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 2c5d7a431..e94aeb9bd 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -55,7 +55,7 @@ if (NOT TARGET ${BOARD_TARGET}) update_board(${BOARD_TARGET}) if (NOT DEFINED LD_FILE_${TOOLCHAIN}) - set(LD_FILE_gcc ${NRFX_DIR}/mdk/${MCU_VARIANT}_xxaa.ld) + set(LD_FILE_GCC ${NRFX_DIR}/mdk/${MCU_VARIANT}_xxaa.ld) endif () if (TOOLCHAIN STREQUAL "gcc") @@ -64,7 +64,7 @@ if (NOT TARGET ${BOARD_TARGET}) ) target_link_options(${BOARD_TARGET} PUBLIC # linker file - "LINKER:--script=${LD_FILE_gcc}" + "LINKER:--script=${LD_FILE_GCC}" -L${NRFX_DIR}/mdk # nanolib --specs=nosys.specs diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake index c9f2a9c8e..145490921 100644 --- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake +++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake @@ -1,11 +1,11 @@ #set(MCU_VARIANT MIMXRT1011) set(JLINK_DEVICE STM32G0B1RE) -set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/STM32G0B1RETx_FLASH.ld) -set(LD_FILE_iar ${ST_CMSIS}/Source/Templates/iar/linker/stm32g0b1xx_flash.icf) +set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/STM32G0B1RETx_FLASH.ld) +set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/stm32g0b1xx_flash.icf) -set(STARTUP_FILE_gcc ${ST_CMSIS}/Source/Templates/gcc/startup_stm32g0b1xx.s) -set(STARTUP_FILE_iar ${ST_CMSIS}/Source/Templates/iar/startup_stm32g0b1xx.s) +set(STARTUP_FILE_GCC ${ST_CMSIS}/Source/Templates/gcc/startup_stm32g0b1xx.s) +set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_stm32g0b1xx.s) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake index 184dc6062..d77b3c102 100644 --- a/hw/bsp/stm32g0/family.cmake +++ b/hw/bsp/stm32g0/family.cmake @@ -28,50 +28,49 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # BOARD_TARGET #------------------------------------ # only need to be built ONCE for all examples -set(BOARD_TARGET board_${BOARD}) -if (NOT TARGET ${BOARD_TARGET}) - add_library(${BOARD_TARGET} STATIC - ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c - ) - target_include_directories(${BOARD_TARGET} PUBLIC - ${CMAKE_CURRENT_LIST_DIR} - ${CMSIS_5}/CMSIS/Core/Include - ${ST_CMSIS}/Include - ${ST_HAL_DRIVER}/Inc - ) - target_compile_options(${BOARD_TARGET} PUBLIC - ) - target_compile_definitions(${BOARD_TARGET} PUBLIC - ) - update_board(${BOARD_TARGET}) - - target_sources(${BOARD_TARGET} PUBLIC - ${STARTUP_FILE_${TOOLCHAIN}} - ) - - if (TOOLCHAIN STREQUAL "gcc") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_gcc}" - -nostartfiles - # nanolib - --specs=nosys.specs - --specs=nano.specs +function(add_board_target TARGET) + if (NOT TARGET ${TARGET}) + add_library(${TARGET} STATIC + ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${ST_CMSIS}/Include + ${ST_HAL_DRIVER}/Inc + ) + target_compile_options(${TARGET} PUBLIC ) - else () - # TODO support IAR - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--config=${LD_FILE_iar}" + target_compile_definitions(${TARGET} PUBLIC ) + + update_board(${TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GCC") + target_link_options(${TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GCC}" + -nostartfiles + # nanolib + --specs=nosys.specs + --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + # TODO support IAR + target_link_options(${TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () endif () -endif () # BOARD_TARGET +endfunction() #------------------------------------ @@ -80,6 +79,9 @@ endif () # BOARD_TARGET function(family_configure_example TARGET) family_configure_common(${TARGET}) + # Board target + add_board_target(board_${BOARD}) + #---------- Port Specific ---------- # These files are built for each example since it depends on example's tusb_config.h target_sources(${TARGET} PUBLIC @@ -100,7 +102,7 @@ function(family_configure_example TARGET) family_add_tinyusb(${TARGET} OPT_MCU_STM32G0) # Link dependencies - target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb) + target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_flash_stlink(${TARGET}) diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake index 4e8f3f059..3a4849ef6 100644 --- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake +++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake @@ -1,11 +1,11 @@ set(MCU_VARIANT stm32g474xx) set(JLINK_DEVICE stm32g474re) -set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld) -set(LD_FILE_iar ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) +set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld) +set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) -set(STARTUP_FILE_gcc ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) -set(STARTUP_FILE_iar ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s) +set(STARTUP_FILE_GCC ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) +set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake index 8cc633449..f13f1fc28 100644 --- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake +++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake @@ -1,11 +1,11 @@ set(MCU_VARIANT stm32g474xx) set(JLINK_DEVICE stm32g474re) -set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld) -set(LD_FILE_iar ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) +set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld) +set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) -set(STARTUP_FILE_gcc ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) -set(STARTUP_FILE_iar ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s) +set(STARTUP_FILE_GCC ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) +set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake index 5578a9b6c..c87486677 100644 --- a/hw/bsp/stm32g4/family.cmake +++ b/hw/bsp/stm32g4/family.cmake @@ -59,7 +59,7 @@ if (NOT TARGET ${BOARD_TARGET}) if (TOOLCHAIN STREQUAL "gcc") target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_gcc}" + "LINKER:--script=${LD_FILE_GCC}" -nostartfiles # nanolib --specs=nosys.specs @@ -68,7 +68,7 @@ if (NOT TARGET ${BOARD_TARGET}) else () # TODO support IAR target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--config=${LD_FILE_iar}" + "LINKER:--config=${LD_FILE_IAR}" ) endif () endif () # BOARD_TARGET diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index ad9fbc7c0..09f41c9ab 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -65,6 +65,8 @@ function(add_tinyusb TARGET) -Wreturn-type -Wredundant-decls ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + endif () endfunction() diff --git a/tools/cmake/cpu/cortex-m0plus.cmake b/tools/cmake/cpu/cortex-m0plus.cmake index 1e316ccfc..bc2257048 100644 --- a/tools/cmake/cpu/cortex-m0plus.cmake +++ b/tools/cmake/cpu/cortex-m0plus.cmake @@ -1,11 +1,17 @@ if (TOOLCHAIN STREQUAL "gcc") - list(APPEND TOOLCHAIN_COMMON_FLAGS + set(TOOLCHAIN_COMMON_FLAGS -mthumb -mcpu=cortex-m0plus -mfloat-abi=soft ) set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "") -else () - # TODO support IAR + +elseif (TOOLCHAIN STREQUAL "iar") + set(TOOLCHAIN_COMMON_FLAGS + --cpu cortex-m0 + ) + + set(FREERTOS_PORT IAR_ARM_CM0 CACHE INTERNAL "") + endif () diff --git a/tools/cmake/toolchain/arm_gcc.cmake b/tools/cmake/toolchain/arm_gcc.cmake index c7f12f43a..6dd1e7002 100644 --- a/tools/cmake/toolchain/arm_gcc.cmake +++ b/tools/cmake/toolchain/arm_gcc.cmake @@ -1,8 +1,8 @@ set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_ASM_COMPILER "arm-none-eabi-gcc") set(CMAKE_C_COMPILER "arm-none-eabi-gcc") set(CMAKE_CXX_COMPILER "arm-none-eabi-g++") +set(CMAKE_ASM_COMPILER "arm-none-eabi-gcc") set(CMAKE_SIZE "arm-none-eabi-size" CACHE FILEPATH "") set(CMAKE_OBJCOPY "arm-none-eabi-objcopy" CACHE FILEPATH "") @@ -29,13 +29,13 @@ list(APPEND TOOLCHAIN_COMMON_FLAGS -fno-strict-aliasing ) -list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS +set(TOOLCHAIN_EXE_LINKER_FLAGS -Wl,--print-memory-usage -Wl,--gc-sections -Wl,--cref ) -list(APPEND TOOLCHAIN_WARNING_FLAGS +set(TOOLCHAIN_WARNING_FLAGS -Wall -Wextra -Werror @@ -62,3 +62,11 @@ list(APPEND TOOLCHAIN_WARNING_FLAGS ) include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake) + +# try_compile is cmake test compiling its own example, +# pass -nostdlib to skip stdlib linking +get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE) +if (IS_IN_TRY_COMPILE) + set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib") + set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib") +endif () diff --git a/tools/cmake/toolchain/arm_iar.cmake b/tools/cmake/toolchain/arm_iar.cmake new file mode 100644 index 000000000..dfbe55e0d --- /dev/null +++ b/tools/cmake/toolchain/arm_iar.cmake @@ -0,0 +1,34 @@ +set(CMAKE_SYSTEM_NAME Generic) + +set(CMAKE_C_COMPILER "iccarm") +set(CMAKE_CXX_COMPILER "iccarm") +set(CMAKE_ASM_COMPILER "iasmarm") + +set(CMAKE_SIZE "size" CACHE FILEPATH "") +set(CMAKE_OBJCOPY "ielftool" CACHE FILEPATH "") +set(CMAKE_OBJDUMP "iefdumparm" CACHE FILEPATH "") + +set_property(GLOBAL PROPERTY TARGET_SUPPORTS_SHARED_LIBS FALSE) + +# Look for includes and libraries only in the target system prefix. +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) + +# pass TOOLCHAIN_CPU to +set(CMAKE_TRY_COMPILE_PLATFORM_VARIABLES CMAKE_SYSTEM_PROCESSOR) + +include(${CMAKE_CURRENT_LIST_DIR}/../cpu/${CMAKE_SYSTEM_PROCESSOR}.cmake) + +# enable all possible warnings for building examples +list(APPEND TOOLCHAIN_COMMON_FLAGS + ) + +list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS + ) + +list(APPEND TOOLCHAIN_WARNING_FLAGS + ) + +include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake) diff --git a/tools/cmake/toolchain/set_flags.cmake b/tools/cmake/toolchain/set_flags.cmake index 6f74fe673..44930ef4d 100644 --- a/tools/cmake/toolchain/set_flags.cmake +++ b/tools/cmake/toolchain/set_flags.cmake @@ -1,9 +1,10 @@ include(CMakePrintHelpers) + +# join the toolchain flags into a single string +list(JOIN TOOLCHAIN_COMMON_FLAGS " " TOOLCHAIN_COMMON_FLAGS) + foreach (LANG IN ITEMS C CXX ASM) - # join the toolchain flags into a single string - list(APPEND TOOLCHAIN_${LANG}_FLAGS ${TOOLCHAIN_COMMON_FLAGS}) - list(JOIN TOOLCHAIN_${LANG}_FLAGS " " TOOLCHAIN_${LANG}_FLAGS) - set(CMAKE_${LANG}_FLAGS_INIT "${TOOLCHAIN_${LANG}_FLAGS}") + set(CMAKE_${LANG}_FLAGS_INIT ${TOOLCHAIN_COMMON_FLAGS}) #cmake_print_variables(CMAKE_${LANG}_FLAGS_INIT) @@ -14,11 +15,3 @@ endforeach () # Linker list(JOIN TOOLCHAIN_EXE_LINKER_FLAGS " " CMAKE_EXE_LINKER_FLAGS_INIT) - -# try_compile is cmake test compiling its own example, -# pass -nostdlib to skip stdlib linking -get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE) -if (IS_IN_TRY_COMPILE) - set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib") - set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib") -endif () -- cgit v1.3.1 From 268ab5863a3437c804d6db0ea5dc9f90560e9ffc Mon Sep 17 00:00:00 2001 From: Aladdin Bakosh Date: Wed, 24 May 2023 14:08:42 +0200 Subject: fix(RA Host Portable): git rid of the IAR warnings for packed --- src/portable/renesas/rusb2/rusb2_type.h | 146 ++++++++++++++++---------------- 1 file changed, 73 insertions(+), 73 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index 7a2898366..d80ecc62e 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -41,11 +41,11 @@ extern "C" { TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN -typedef struct TU_ATTR_PACKED { +typedef struct { union { volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */ - struct { + struct TU_ATTR_PACKED { uint16_t : 8; volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */ volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */ @@ -56,18 +56,18 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t N; /* (@ 0x00000002) Pipe Transaction Counter Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */ } N_b; }; } RUSB2_PIPE_TR_t; /* Size = 4 (0x4) */ /* LINK_REG Structure */ -typedef struct TU_ATTR_PACKED { +typedef struct { union { volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t USBE : 1; /* [0..0] USB Operation Enable */ uint16_t : 2; volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */ @@ -85,7 +85,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */ uint16_t : 12; } BUSWAIT_b; @@ -94,7 +94,7 @@ typedef struct TU_ATTR_PACKED { union { volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */ - struct { + struct TU_ATTR_PACKED { volatile const uint16_t LNST : 2; /* [1..0] USB Data Line Status Monitor */ volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */ uint16_t : 2; @@ -109,7 +109,7 @@ typedef struct TU_ATTR_PACKED { union { volatile const uint16_t PLLSTA; /* (@ 0x00000006) PLL Status Register */ - struct { + struct TU_ATTR_PACKED { volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */ uint16_t : 15; } PLLSTA_b; @@ -118,7 +118,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t DVSTCTR0; /* (@ 0x00000008) Device State Control Register 0 */ - struct { + struct TU_ATTR_PACKED { volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */ uint16_t : 1; volatile uint16_t UACT : 1; /* [4..4] USB Bus Enable */ @@ -137,7 +137,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t TESTMODE; /* (@ 0x0000000C) USB Test Mode Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t UTST : 4; /* [3..0] Test Mode */ uint16_t : 12; } TESTMODE_b; @@ -148,7 +148,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint32_t CFIFO; /* (@ 0x00000014) CFIFO Port Register */ - struct { + struct TU_ATTR_PACKED { union { volatile uint16_t CFIFOL; /* (@ 0x00000014) CFIFO Port Register L */ volatile uint8_t CFIFOLL; /* (@ 0x00000014) CFIFO Port Register LL */ @@ -157,7 +157,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t CFIFOH; /* (@ 0x00000016) CFIFO Port Register H */ - struct { + struct TU_ATTR_PACKED { volatile const uint8_t RESERVED3; volatile uint8_t CFIFOHH; /* (@ 0x00000017) CFIFO Port Register HH */ }; @@ -168,7 +168,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint32_t D0FIFO; /* (@ 0x00000018) D0FIFO Port Register */ - struct { + struct TU_ATTR_PACKED { union { volatile uint16_t D0FIFOL; /* (@ 0x00000018) D0FIFO Port Register L */ volatile uint8_t D0FIFOLL; /* (@ 0x00000018) D0FIFO Port Register LL */ @@ -177,7 +177,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t D0FIFOH; /* (@ 0x0000001A) D0FIFO Port Register H */ - struct { + struct TU_ATTR_PACKED { volatile const uint8_t RESERVED4; volatile uint8_t D0FIFOHH; /* (@ 0x0000001B) D0FIFO Port Register HH */ }; @@ -188,7 +188,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint32_t D1FIFO; /* (@ 0x0000001C) D1FIFO Port Register */ - struct { + struct TU_ATTR_PACKED { union { volatile uint16_t D1FIFOL; /* (@ 0x0000001C) D1FIFO Port Register L */ volatile uint8_t D1FIFOLL; /* (@ 0x0000001C) D1FIFO Port Register LL */ @@ -197,7 +197,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t D1FIFOH; /* (@ 0x0000001E) D1FIFO Port Register H */ - struct { + struct TU_ATTR_PACKED { volatile const uint8_t RESERVED5; volatile uint8_t D1FIFOHH; /* (@ 0x0000001F) D1FIFO Port Register HH */ }; @@ -208,7 +208,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t CFIFOSEL; /* (@ 0x00000020) CFIFO Port Select Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */ uint16_t : 1; volatile uint16_t ISEL : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */ @@ -225,12 +225,12 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */ - struct { + struct TU_ATTR_PACKED { volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ uint16_t : 1; volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ - volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ + volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; volatile const uint32_t RESERVED6; @@ -238,7 +238,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t D0FIFOSEL; /* (@ 0x00000028) D0FIFO Port Select Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */ uint16_t : 4; volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ @@ -254,19 +254,19 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */ - struct { + struct TU_ATTR_PACKED { volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ uint16_t : 1; volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ - volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ + volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + volatile uint16_t BVAL : 1; /* [15..15] Buffer Memory Valid Flag */ } D0FIFOCTR_b; }; union { volatile uint16_t D1FIFOSEL; /* (@ 0x0000002C) D1FIFO Port Select Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */ uint16_t : 4; volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */ @@ -282,7 +282,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */ - struct { + struct TU_ATTR_PACKED { volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */ uint16_t : 1; volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */ @@ -294,7 +294,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */ - struct { + struct TU_ATTR_PACKED { uint16_t : 8; volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */ volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */ @@ -310,7 +310,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t INTENB1; /* (@ 0x00000032) Interrupt Enable Register 1 */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */ uint16_t : 3; volatile uint16_t SACKE : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */ @@ -329,7 +329,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t BRDYENB; /* (@ 0x00000036) BRDY Interrupt Enable Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t PIPE0BRDYE : 1; /* [0..0] BRDY Interrupt Enable for PIPE */ volatile uint16_t PIPE1BRDYE : 1; /* [1..1] BRDY Interrupt Enable for PIPE */ volatile uint16_t PIPE2BRDYE : 1; /* [2..2] BRDY Interrupt Enable for PIPE */ @@ -347,7 +347,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t NRDYENB; /* (@ 0x00000038) NRDY Interrupt Enable Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t PIPE0NRDYE : 1; /* [0..0] NRDY Interrupt Enable for PIPE */ volatile uint16_t PIPE1NRDYE : 1; /* [1..1] NRDY Interrupt Enable for PIPE */ volatile uint16_t PIPE2NRDYE : 1; /* [2..2] NRDY Interrupt Enable for PIPE */ @@ -365,7 +365,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t BEMPENB; /* (@ 0x0000003A) BEMP Interrupt Enable Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t PIPE0BEMPE : 1; /* [0..0] BEMP Interrupt Enable for PIPE */ volatile uint16_t PIPE1BEMPE : 1; /* [1..1] BEMP Interrupt Enable for PIPE */ volatile uint16_t PIPE2BEMPE : 1; /* [2..2] BEMP Interrupt Enable for PIPE */ @@ -383,7 +383,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */ - struct { + struct TU_ATTR_PACKED { uint16_t : 4; volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */ volatile uint16_t INTL : 1; /* [5..5] Interrupt Output Sense Select */ @@ -397,7 +397,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t DIRPD : 1; /* [0..0] Power-Down Control */ volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */ uint16_t : 1; @@ -415,7 +415,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */ - struct { + struct TU_ATTR_PACKED { volatile const uint16_t CTSQ : 3; /* [2..0] Control Transfer Stage */ volatile uint16_t VALID : 1; /* [3..3] USB Request Reception */ volatile const uint16_t DVSQ : 3; /* [6..4] Device State */ @@ -434,7 +434,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t INTSTS1; /* (@ 0x00000042) Interrupt Status Register 1 */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */ uint16_t : 3; volatile uint16_t SACK : 1; /* [4..4] Setup Transaction Normal Response Interrupt Status */ @@ -456,7 +456,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t BRDYSTS; /* (@ 0x00000046) BRDY Interrupt Status Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t PIPE0BRDY : 1; /* [0..0] BRDY Interrupt Status for PIPE */ volatile uint16_t PIPE1BRDY : 1; /* [1..1] BRDY Interrupt Status for PIPE */ volatile uint16_t PIPE2BRDY : 1; /* [2..2] BRDY Interrupt Status for PIPE */ @@ -474,7 +474,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t NRDYSTS; /* (@ 0x00000048) NRDY Interrupt Status Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t PIPE0NRDY : 1; /* [0..0] NRDY Interrupt Status for PIPE */ volatile uint16_t PIPE1NRDY : 1; /* [1..1] NRDY Interrupt Status for PIPE */ volatile uint16_t PIPE2NRDY : 1; /* [2..2] NRDY Interrupt Status for PIPE */ @@ -492,7 +492,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t BEMPSTS; /* (@ 0x0000004A) BEMP Interrupt Status Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t PIPE0BEMP : 1; /* [0..0] BEMP Interrupt Status for PIPE */ volatile uint16_t PIPE1BEMP : 1; /* [1..1] BEMP Interrupt Status for PIPE */ volatile uint16_t PIPE2BEMP : 1; /* [2..2] BEMP Interrupt Status for PIPE */ @@ -510,7 +510,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t FRMNUM; /* (@ 0x0000004C) Frame Number Register */ - struct { + struct TU_ATTR_PACKED { volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */ uint16_t : 3; volatile uint16_t CRCE : 1; /* [14..14] Receive Data Error */ @@ -521,7 +521,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t UFRMNUM; /* (@ 0x0000004E) uFrame Number Register */ - struct { + struct TU_ATTR_PACKED { volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */ uint16_t : 12; volatile uint16_t DVCHG : 1; /* [15..15] Device State Change */ @@ -531,7 +531,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t USBADDR; /* (@ 0x00000050) USB Address Register */ - struct { + struct TU_ATTR_PACKED { volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */ uint16_t : 1; volatile uint16_t STSRECOV0 : 3; /* [10..8] Status Recovery */ @@ -543,7 +543,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */ volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */ } USBREQ_b; @@ -552,7 +552,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t USBVAL; /* (@ 0x00000056) USB Request Value Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t WVALUE : 16; /* [15..0] ValueThese bits store the USB request Value value. */ } USBVAL_b; }; @@ -560,7 +560,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t USBINDX; /* (@ 0x00000058) USB Request Index Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t WINDEX : 16; /* [15..0] IndexThese bits store the USB request wIndex value. */ } USBINDX_b; }; @@ -568,7 +568,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t USBLENG; /* (@ 0x0000005A) USB Request Length Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t WLENGTH : 16; /* [15..0] LengthThese bits store the USB request wLength value. */ } USBLENG_b; }; @@ -576,7 +576,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */ - struct { + struct TU_ATTR_PACKED { uint16_t : 4; volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ uint16_t : 2; @@ -589,7 +589,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t MXPS : 7; /* [6..0] Maximum Packet Size */ uint16_t : 5; volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ @@ -599,7 +599,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t PID : 2; /* [1..0] Response PID */ volatile uint16_t CCPL : 1; /* [2..2] Control Transfer End Enable */ uint16_t : 2; @@ -619,7 +619,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t PIPESEL; /* (@ 0x00000064) Pipe Window Select Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */ uint16_t : 12; } PIPESEL_b; @@ -629,7 +629,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t PIPECFG; /* (@ 0x00000068) Pipe Configuration Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t EPNUM : 4; /* [3..0] Endpoint Number */ volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ uint16_t : 2; @@ -646,7 +646,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */ uint16_t : 3; volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ @@ -656,7 +656,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t PIPEPERI; /* (@ 0x0000006E) Pipe Cycle Control Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */ uint16_t : 9; volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */ @@ -667,7 +667,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t PIPE_CTR[9]; /* (@ 0x00000070) Pipe [0..8] Control Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t PID : 2; /* [1..0] Response PID */ uint16_t : 3; volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */ @@ -691,7 +691,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t USBBCCTRL0; /* (@ 0x000000B0) BC Control Register 0 */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t RPDME0 : 1; /* [0..0] D- Pin Pull-Down Control */ volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */ volatile uint16_t @@ -713,7 +713,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t UCKSEL; /* (@ 0x000000C4) USB Clock Selection Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */ uint16_t : 15; } UCKSEL_b; @@ -724,7 +724,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t USBMC; /* (@ 0x000000CC) USB Module Control Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */ uint16_t : 6; volatile uint16_t VDCEN : 1; /* [7..7] USB Regulator On/Off Control */ @@ -736,7 +736,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */ - struct { + struct TU_ATTR_PACKED { uint16_t : 6; volatile uint16_t USBSPD : 2; /* [7..6] Transfer Speed of Communication Target Device */ volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */ @@ -749,7 +749,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint32_t PHYSLEW; /* (@ 0x000000F0) PHY Cross Point Adjustment Register */ - struct { + struct TU_ATTR_PACKED { volatile uint32_t SLEWR00 : 1; /* [0..0] Receiver Cross Point Adjustment 00 */ volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */ volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */ @@ -762,7 +762,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */ - struct { + struct TU_ATTR_PACKED { uint16_t : 7; volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */ uint16_t : 8; @@ -772,7 +772,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */ - struct { + struct TU_ATTR_PACKED { uint16_t : 14; volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */ uint16_t : 1; @@ -783,7 +783,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t IDPSRCE : 1; /* [0..0] IDPSRC Control */ volatile uint16_t IDMSINKE : 1; /* [1..1] IDMSINK Control */ volatile uint16_t VDPSRCE : 1; /* [2..2] VDPSRC Control */ @@ -801,7 +801,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */ volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */ volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */ @@ -816,7 +816,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */ - struct { + struct TU_ATTR_PACKED { uint16_t : 8; volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */ volatile uint16_t RWEMON : 1; /* [12..12] RWE Value Monitor */ @@ -827,8 +827,8 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */ - struct { - volatile uint16_t L1REQ : 1; /* [0..0] L1 Transition Request */ + struct TU_ATTR_PACKED { + volatile uint16_t L1REQ : 1; /* [0..0] L1 Transition Request */ volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */ uint16_t : 13; } HL1CTRL1_b; @@ -837,7 +837,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t HL1CTRL2; /* (@ 0x0000014A) Host L1 Control Register 2 */ - struct { + struct TU_ATTR_PACKED { volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */ uint16_t : 4; volatile uint16_t HIRD : 4; /* [11..8] LPM Token HIRD */ @@ -851,7 +851,7 @@ typedef struct TU_ATTR_PACKED { union { volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */ - struct { + struct TU_ATTR_PACKED { uint32_t : 20; volatile const uint32_t DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */ volatile const uint32_t DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */ @@ -864,7 +864,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ - struct { + struct TU_ATTR_PACKED { uint32_t : 4; volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */ volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */ @@ -882,7 +882,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t DPUSR2R; /* (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ - struct { + struct TU_ATTR_PACKED { volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */ volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */ uint16_t : 2; @@ -898,8 +898,8 @@ typedef struct TU_ATTR_PACKED { union { volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ - struct { - volatile uint16_t FIXPHY : 1; /* [0..0] USB Transceiver Control Fix */ + struct TU_ATTR_PACKED { + volatile uint16_t FIXPHY : 1; /* [0..0] USB Transceiver Control Fix */ volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */ uint16_t : 14; } DPUSRCR_b; @@ -910,7 +910,7 @@ typedef struct TU_ATTR_PACKED { volatile uint32_t DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */ - struct { + struct TU_ATTR_PACKED { volatile uint32_t SRPC0 : 1; /* [0..0] USB Single End Receiver Control */ volatile uint32_t RPUE0 : 1; /* [1..1] DP Pull-Up Resistor Control */ uint32_t : 1; @@ -931,7 +931,7 @@ typedef struct TU_ATTR_PACKED { union { volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */ - struct { + struct TU_ATTR_PACKED { volatile uint32_t DPINTE0 : 1; /* [0..0] USB DP Interrupt Enable/Clear */ volatile uint32_t DMINTE0 : 1; /* [1..1] USB DM Interrupt Enable/Clear */ uint32_t : 2; -- cgit v1.3.1 From cdae66c8371e1c73d28279462fa8598a9daae5a7 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 5 Jun 2023 09:04:52 +0200 Subject: renesas_rx: fix compilation on latest GCC __CCRX__ only applyes to version 4 of RX family compiler http://tool-support.renesas.com/autoupdate/support/onlinehelp/csp/V4.01.00/CS+.chm/Compiler-CCRX.chm/Output/ccrx04c0201y.html __RX__ is one of the macros exported by latest gcc (gcc_8.3.0.202305_rx_elf) --- src/portable/renesas/rusb2/dcd_rusb2.c | 2 ++ src/portable/renesas/rusb2/hcd_rusb2.c | 2 ++ 2 files changed, 4 insertions(+) (limited to 'src') diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 2653d0da6..e9ac46517 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -67,6 +67,8 @@ /* LINK core registers */ #if defined(__CCRX__) #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE) +#elif defined(__RX__) + #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE) #elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE) #else diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 1e26c931d..b97ffd7e9 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -54,6 +54,8 @@ /* LINK core registers */ #if defined(__CCRX__) #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE) +#elif defined(__RX__) + #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE) #elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) #define RUSB2 ((R_USB_HS0_Type*) R_USB_HS0_BASE) #else -- cgit v1.3.1 From 2b735ee8f5476168d6b5ed1dc32edc52f4d3648a Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 5 Jun 2023 09:31:58 +0200 Subject: renesas_ra: fix wrong ifdef Since CFG_TUSB_RHPORT1_MODE is always defined now for backwards compatibility --- src/portable/renesas/rusb2/rusb2_ra.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c index 2b6ce7b2f..ff2191b1f 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.c +++ b/src/portable/renesas/rusb2/rusb2_ra.c @@ -1,16 +1,16 @@ #include "tusb_option.h" #include "rusb2_ra.h" -#ifdef CFG_TUSB_RHPORT0_MODE +#if (CFG_TUSB_RHPORT0_MODE != 0) IRQn_Type _usb_fs_irqn = USBFS_INT_IRQn; void tud_set_irq_usbfs(IRQn_Type q) { _usb_fs_irqn = q; } #endif -#ifdef CFG_TUSB_RHPORT1_MODE +#if (CFG_TUSB_RHPORT1_MODE != 0) IRQn_Type _usb_hs_irqn = USBHS_USB_INT_RESUME_IRQn; void tud_set_irq_usbhs(IRQn_Type q) { _usb_hs_irqn = q; } -#endif \ No newline at end of file +#endif -- cgit v1.3.1 From f6a45a7aab42264fc9c270150549cd4c4a54292e Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 5 Jun 2023 15:41:35 +0700 Subject: clean up --- .idea/runConfigurations/stm32g474_jlink.xml | 10 ++++++ hw/bsp/board.c | 11 ++++--- hw/bsp/family_support.cmake | 17 ++++++---- hw/bsp/stm32g4/family.c | 50 ++++++++++++++++------------- src/CMakeLists.txt | 4 --- 5 files changed, 55 insertions(+), 37 deletions(-) create mode 100644 .idea/runConfigurations/stm32g474_jlink.xml (limited to 'src') diff --git a/.idea/runConfigurations/stm32g474_jlink.xml b/.idea/runConfigurations/stm32g474_jlink.xml new file mode 100644 index 000000000..45a755da4 --- /dev/null +++ b/.idea/runConfigurations/stm32g474_jlink.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/hw/bsp/board.c b/hw/bsp/board.c index 66ffcb199..3f62547a0 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -39,7 +39,7 @@ #define sys_read _read #endif -#if defined(LOGGER_RTT) +#if defined(LOGGER_RTT) || defined(LOGGER_rtt) // Logging with RTT // If using SES IDE, use the Syscalls/SEGGER_RTT_Syscalls_SES.c instead @@ -62,7 +62,7 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) #endif -#elif defined(LOGGER_SWO) +#elif defined(LOGGER_SWO) || defined(LOGGER_swo) // Logging with SWO for ARM Cortex #include "board_mcu.h" @@ -71,11 +71,12 @@ TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) { (void) fhdl; uint8_t const* buf8 = (uint8_t const*) buf; - for(size_t i=0; i.map" ) endif() + + # LOGGER + if (DEFINED LOGGER) + target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER}) + endif () + endfunction() @@ -136,12 +142,11 @@ function(family_add_tinyusb TARGET OPT_MCU) set(TINYUSB_TARGET_PREFIX ${TARGET}-) add_library(${TARGET}-tinyusb_config INTERFACE) - target_include_directories(${TARGET}-tinyusb_config INTERFACE - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE - CFG_TUSB_MCU=${OPT_MCU} - ) + target_include_directories(${TARGET}-tinyusb_config INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/src) + target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_MCU=${OPT_MCU}) + if (DEFINED LOG) + target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_DEBUG=${LOG}) + endif() # tinyusb's CMakeList.txt add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c index 3b490e9b3..19ba415bc 100644 --- a/hw/bsp/stm32g4/family.c +++ b/hw/bsp/stm32g4/family.c @@ -79,32 +79,35 @@ void board_init(void) NVIC_SetPriority(USBWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); #endif - GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitTypeDef gpio_init; // LED - GPIO_InitStruct.Pin = LED_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct); + memset(&gpio_init, 0, sizeof(gpio_init)); + gpio_init.Pin = LED_PIN; + gpio_init.Mode = GPIO_MODE_OUTPUT_PP; + gpio_init.Pull = GPIO_PULLUP; + gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(LED_PORT, &gpio_init); board_led_write(false); // Button - GPIO_InitStruct.Pin = BUTTON_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); + memset(&gpio_init, 0, sizeof(gpio_init)); + gpio_init.Pin = BUTTON_PIN; + gpio_init.Mode = GPIO_MODE_INPUT; + gpio_init.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP; + gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(BUTTON_PORT, &gpio_init); #ifdef UART_DEV // UART - GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - GPIO_InitStruct.Alternate = UART_GPIO_AF; - HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct); + memset(&gpio_init, 0, sizeof(gpio_init)); + gpio_init.Pin = UART_TX_PIN | UART_RX_PIN; + gpio_init.Mode = GPIO_MODE_AF_PP; + gpio_init.Pull = GPIO_PULLUP; + gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; + gpio_init.Alternate = UART_GPIO_AF; + HAL_GPIO_Init(UART_GPIO_PORT, &gpio_init); UartHandle = (UART_HandleTypeDef){ .Instance = UART_DEV, @@ -121,15 +124,18 @@ void board_init(void) // USB Pins TODO double check USB clock and pin setup // Configure USB DM and DP pins. This is optional, and maintained only for user guidance. - GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12); - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + memset(&gpio_init, 0, sizeof(gpio_init)); + gpio_init.Pin = (GPIO_PIN_11 | GPIO_PIN_12); + gpio_init.Mode = GPIO_MODE_INPUT; + gpio_init.Pull = GPIO_NOPULL; + gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOA, &gpio_init); __HAL_RCC_USB_CLK_ENABLE(); board_vbus_sense_init(); + + // USB PD } //--------------------------------------------------------------------+ diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 09f41c9ab..3dbd72d61 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -98,7 +98,3 @@ endif() target_link_libraries(${TINYUSB_TARGET} PUBLIC ${TINYUSB_CONFIG_TARGET} ) - -# export target name -# set(TINYUSB_TARGET ${TINYUSB_TARGET} PARENT_SCOPE) -# set(TINYUSB_CONFIG_TARGET ${TINYUSB_CONFIG_TARGET} PARENT_SCOPE) -- cgit v1.3.1 From b3fda4a35433a4102743ea9719e2323e4076ff34 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 6 Jun 2023 23:55:33 +0700 Subject: able to get usbpd irq handler - handle cc1, cc2 voltage changes - get order set, rx message end interrupt - add segger rtt support for cmake --- hw/bsp/family_support.cmake | 15 +++ hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h | 22 ++-- hw/bsp/stm32g4/family.c | 183 ++++++++++++++++++++++++---- src/common/tusb_types.h | 13 ++ 4 files changed, 196 insertions(+), 37 deletions(-) (limited to 'src') diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 2c0ee95d6..e9b4f2fdb 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -97,6 +97,18 @@ function(family_initialize_project PROJECT DIR) endfunction() +# Add segger rtt to example +function(family_add_segger_rtt TARGET) + if (NOT TARGET segger_rtt) + add_library(segger_rtt STATIC + ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + ) + target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT) + endif() + + target_link_libraries(${TARGET} PUBLIC segger_rtt) +endfunction() + #------------------------------------ # Main target configure #------------------------------------ @@ -119,6 +131,9 @@ function(family_configure_common TARGET) # LOGGER if (DEFINED LOGGER) target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER}) + if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt") + family_add_segger_rtt(${TARGET}) + endif () endif () endfunction() diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h index 21d4e459b..b1a98ba97 100644 --- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h +++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h @@ -58,7 +58,7 @@ // RCC Clock //--------------------------------------------------------------------+ -// CPU Frequency (Core Clock) is 170MHz +// CPU Frequency (Core Clock) is 150MHz static inline void board_clock_init(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; @@ -68,16 +68,16 @@ static inline void board_clock_init(void) HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); /* Activate PLL with HSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4; - RCC_OscInitStruct.PLL.PLLN = 85; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV10; - RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; - RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4; + RCC_OscInitStruct.PLL.PLLN = 75; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; HAL_RCC_OscConfig(&RCC_OscInitStruct); // Initializes the CPU, AHB and APB buses clocks @@ -87,7 +87,7 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8); + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); //------------- HSI48 and CRS for USB -------------// RCC_OscInitTypeDef osc_hsi48 = {0}; diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c index 030abe0d0..8b17c0643 100644 --- a/hw/bsp/stm32g4/family.c +++ b/hw/bsp/stm32g4/family.c @@ -25,9 +25,127 @@ */ #include "stm32g4xx_hal.h" +#include "stm32g4xx_ll_bus.h" + #include "bsp/board.h" #include "board.h" + +//--------------------------------------------------------------------+ +// USB PD +//--------------------------------------------------------------------+ + +void usbpd_init(uint8_t port_num, tusb_typec_port_type_t port_type) { + (void) port_num; + + // Initialization phase: CFG1 + UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) | + (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) | + ( 0 << UCPD_CFG1_TXDMAEN_Pos) | (0 << UCPD_CFG1_RXDMAEN_Pos); + UCPD1->CFG1 |= UCPD_CFG1_UCPDEN; + + // General programming sequence (with UCPD configured then enabled) + if (port_type == TUSB_TYPEC_PORT_SNK) { + // Enable both CC Phy + UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos); + + // Read Voltage State on CC1 & CC2 fore initial state + uint32_t vstate_cc[2]; + vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; + vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03; + + TU_LOG1_INT(vstate_cc[0]); + TU_LOG1_INT(vstate_cc[1]); + + // Enable CC1 & CC2 Interrupt + UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE; + } + + // Enable interrupt + //NVIC_SetPriority(UCPD1_IRQn, 0); +// NVIC_EnableIRQ(UCPD1_IRQn); +} + +uint8_t pd_rx_buf[262]; +uint32_t pd_rx_count = 0; + +void UCPD1_IRQHandler(void) { + uint32_t sr = UCPD1->SR; + sr &= UCPD1->IMR; + + TU_LOG1("UCPD1_IRQHandler: sr = 0x%08X\n", sr); + + if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) { + uint32_t vstate_cc[2]; + vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; + vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03; + + TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]); + + uint32_t cr = UCPD1->CR; + + if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) { + TU_LOG1("Attach CC1\n"); + cr &= ~UCPD_CR_PHYCCSEL; + cr |= UCPD_CR_PHYRXEN; + } else if ((sr & UCPD_SR_TYPECEVT2) && (vstate_cc[1] == 3)) { + TU_LOG1("Attach CC2\n"); + cr |= UCPD_CR_PHYCCSEL; + cr |= UCPD_CR_PHYRXEN; + } else { + TU_LOG1("Detach\n"); + cr &= ~UCPD_CR_PHYRXEN; + } + + // Enable Interrupt + UCPD1->IMR |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE | + /*UCPD_IMR_RXNEIE |*/ UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE | + UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE; + + // Enable PD RX + UCPD1->CR = cr; + + // ack + UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF; + } + + if (sr & UCPD_SR_RXORDDET) { + // SOP: Start of Packet + // TODO DMA later + uint8_t order_set = UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk; + TU_LOG1_HEX(order_set); + + // ack + UCPD1->ICR = UCPD_ICR_RXORDDETCF; + } + + if ( sr & UCPD_SR_RXMSGEND) { + // End of message +// uint32_t payload_size = UCPD1->RX_PAYSZ; +// TU_LOG1_HEX(payload_size); +// +// for(uint32_t i=0; iRXDR; +// +// TU_LOG1("0x%02X ", pd_rx_buf[i]); +// } +// TU_LOG1("\n"); + + // ack + UCPD1->ICR = UCPD_ICR_RXMSGENDCF; + } + +// if (sr & UCPD_SR_RXNE) { +// uint8_t data = UCPD1->RXDR; +// pd_rx_buf[pd_rx_count++] = data; +// TU_LOG1_HEX(data); +// } + +// else { +// TU_LOG_LOCATION(); +// } +} + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ @@ -79,35 +197,35 @@ void board_init(void) NVIC_SetPriority(USBWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); #endif - GPIO_InitTypeDef gpio_init; + GPIO_InitTypeDef GPIO_InitStruct; // LED - memset(&gpio_init, 0, sizeof(gpio_init)); - gpio_init.Pin = LED_PIN; - gpio_init.Mode = GPIO_MODE_OUTPUT_PP; - gpio_init.Pull = GPIO_PULLUP; - gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(LED_PORT, &gpio_init); + memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct)); + GPIO_InitStruct.Pin = LED_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct); board_led_write(false); // Button - memset(&gpio_init, 0, sizeof(gpio_init)); - gpio_init.Pin = BUTTON_PIN; - gpio_init.Mode = GPIO_MODE_INPUT; - gpio_init.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP; - gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(BUTTON_PORT, &gpio_init); + memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct)); + GPIO_InitStruct.Pin = BUTTON_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); #ifdef UART_DEV // UART - memset(&gpio_init, 0, sizeof(gpio_init)); - gpio_init.Pin = UART_TX_PIN | UART_RX_PIN; - gpio_init.Mode = GPIO_MODE_AF_PP; - gpio_init.Pull = GPIO_PULLUP; - gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; - gpio_init.Alternate = UART_GPIO_AF; - HAL_GPIO_Init(UART_GPIO_PORT, &gpio_init); + memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct)); + GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = UART_GPIO_AF; + HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct); UartHandle = (UART_HandleTypeDef){ .Instance = UART_DEV, @@ -124,18 +242,31 @@ void board_init(void) // USB Pins TODO double check USB clock and pin setup // Configure USB DM and DP pins. This is optional, and maintained only for user guidance. - memset(&gpio_init, 0, sizeof(gpio_init)); - gpio_init.Pin = (GPIO_PIN_11 | GPIO_PIN_12); - gpio_init.Mode = GPIO_MODE_INPUT; - gpio_init.Pull = GPIO_NOPULL; - gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(GPIOA, &gpio_init); + memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct)); + GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12); + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); __HAL_RCC_USB_CLK_ENABLE(); board_vbus_sense_init(); +#if 0 // USB PD + /* PWR register access (for disabling dead battery feature) */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC); + + __HAL_RCC_UCPD1_CLK_ENABLE(); + + // Default CC1/CC2 is PB4/PB6 + // PB4 ------> UCPD1_CC2 + // PB6 ------> UCPD1_CC1 + + usbpd_init(0, TUSB_TYPEC_PORT_SNK); +#endif } diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 39a2d4564..7b82c51d9 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -232,6 +232,19 @@ enum { #define TUSB_DESC_CONFIG_POWER_MA(x) ((x)/2) +//--------------------------------------------------------------------+ +// TYPE-C +//--------------------------------------------------------------------+ + +typedef enum { + TUSB_TYPEC_PORT_SRC, + TUSB_TYPEC_PORT_SNK, + TUSB_TYPEC_PORT_DRP +} tusb_typec_port_type_t; + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ typedef enum { XFER_RESULT_SUCCESS = 0, -- cgit v1.3.1 From b893f1d5417adf8cf874d6b2e7946582ca37982a Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 7 Jun 2023 15:10:40 +0700 Subject: inital support for usb typec and pd example --- examples/typec/power_delivery/CMakeLists.txt | 32 +++++ examples/typec/power_delivery/Makefile | 11 ++ examples/typec/power_delivery/only.txt | 1 + examples/typec/power_delivery/src/main.c | 90 ++++++++++++ examples/typec/power_delivery/src/tusb_config.h | 79 +++++++++++ hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h | 8 +- hw/bsp/stm32g4/family.c | 133 +---------------- hw/bsp/stm32g4/family.cmake | 1 + src/CMakeLists.txt | 2 + src/common/tusb_mcu.h | 2 + src/common/tusb_types.h | 91 ++++++++++-- src/portable/st/typec/typec_stm32.c | 181 ++++++++++++++++++++++++ src/tusb.h | 5 + src/typec/tcd.h | 58 ++++++++ src/typec/utcd.c | 48 +++++++ src/typec/utcd.h | 54 +++++++ 16 files changed, 651 insertions(+), 145 deletions(-) create mode 100644 examples/typec/power_delivery/CMakeLists.txt create mode 100644 examples/typec/power_delivery/Makefile create mode 100644 examples/typec/power_delivery/only.txt create mode 100644 examples/typec/power_delivery/src/main.c create mode 100644 examples/typec/power_delivery/src/tusb_config.h create mode 100644 src/portable/st/typec/typec_stm32.c create mode 100644 src/typec/tcd.h create mode 100644 src/typec/utcd.c create mode 100644 src/typec/utcd.h (limited to 'src') diff --git a/examples/typec/power_delivery/CMakeLists.txt b/examples/typec/power_delivery/CMakeLists.txt new file mode 100644 index 000000000..4ab8d5a65 --- /dev/null +++ b/examples/typec/power_delivery/CMakeLists.txt @@ -0,0 +1,32 @@ +cmake_minimum_required(VERSION 3.17) + +include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) + +# gets PROJECT name for the example (e.g. -) +family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) + +project(${PROJECT} C CXX ASM) + +# Checks this example is valid for the family and initializes the project +family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) + +# Espressif has its own cmake build system +if(FAMILY STREQUAL "espressif") + return() +endif() + +add_executable(${PROJECT}) + +# Example source +target_sources(${PROJECT} PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ) + +# Example include +target_include_directories(${PROJECT} PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) + +# Configure compilation flags and libraries for the example... see the corresponding function +# in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT}) diff --git a/examples/typec/power_delivery/Makefile b/examples/typec/power_delivery/Makefile new file mode 100644 index 000000000..2a3d854fb --- /dev/null +++ b/examples/typec/power_delivery/Makefile @@ -0,0 +1,11 @@ +include ../../make.mk + +INC += \ + src \ + $(TOP)/hw \ + +# Example source +EXAMPLE_SOURCE += $(wildcard src/*.c) +SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) + +include ../../rules.mk diff --git a/examples/typec/power_delivery/only.txt b/examples/typec/power_delivery/only.txt new file mode 100644 index 000000000..657aeaac5 --- /dev/null +++ b/examples/typec/power_delivery/only.txt @@ -0,0 +1 @@ +mcu:STM32G4 diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c new file mode 100644 index 000000000..9d032b6bb --- /dev/null +++ b/examples/typec/power_delivery/src/main.c @@ -0,0 +1,90 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include +#include +#include + +#include "bsp/board.h" +#include "tusb.h" + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF PROTOTYPES +//--------------------------------------------------------------------+ + +/* Blink pattern + * - 250 ms : button is not pressed + * - 1000 ms : button is pressed (and hold) + */ +enum { + BLINK_PRESSED = 250, + BLINK_UNPRESSED = 1000 +}; + +static uint32_t blink_interval_ms = BLINK_UNPRESSED; + +void led_blinking_task(void); + +#define HELLO_STR "Hello from TinyUSB\r\n" + +int main(void) +{ + board_init(); + board_led_write(true); + + tuc_init(0, TYPEC_PORT_SNK); + + uint32_t start_ms = 0; + bool led_state = false; + + while (1) { + led_blinking_task(); + +// tuc_task(); + } +} + +#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +void app_main(void) +{ + main(); +} +#endif + +//--------------------------------------------------------------------+ +// BLINKING TASK +//--------------------------------------------------------------------+ +void led_blinking_task(void) +{ + static uint32_t start_ms = 0; + static bool led_state = false; + + // Blink every interval ms + if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time + start_ms += blink_interval_ms; + + board_led_write(led_state); + led_state = 1 - led_state; // toggle +} diff --git a/examples/typec/power_delivery/src/tusb_config.h b/examples/typec/power_delivery/src/tusb_config.h new file mode 100644 index 000000000..deddcbfa4 --- /dev/null +++ b/examples/typec/power_delivery/src/tusb_config.h @@ -0,0 +1,79 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#ifndef _TUSB_CONFIG_H_ +#define _TUSB_CONFIG_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// special example that doesn't enable device or host stack +// This can cause some TinyUSB API missing, this define hack to allow us to fill those API +// to pass the compilation process +#define tud_int_handler(x) + +//-------------------------------------------------------------------- +// COMMON CONFIGURATION +//-------------------------------------------------------------------- + +// defined by compiler flags for flexibility +#ifndef CFG_TUSB_MCU + #error CFG_TUSB_MCU must be defined +#endif + +#ifndef CFG_TUSB_OS + #define CFG_TUSB_OS OPT_OS_NONE +#endif + +#define CFG_TUD_ENABLED 0 +#define CFG_TUH_ENABLED 0 + +// Enable TYPEC stack +#define CFG_TUC_ENABLED 1 + +// CFG_TUSB_DEBUG is defined by compiler in DEBUG build +// #define CFG_TUSB_DEBUG 0 + +/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. + * Tinyusb use follows macros to declare transferring memory so that they can be put + * into those specific section. + * e.g + * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) + * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) + */ +#ifndef CFG_TUSB_MEM_SECTION +#define CFG_TUSB_MEM_SECTION +#endif + +#ifndef CFG_TUSB_MEM_ALIGN +#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4))) +#endif + +#ifdef __cplusplus + } +#endif + +#endif /* _TUSB_CONFIG_H_ */ diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h index 6b00efc8f..e61b13170 100644 --- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h +++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h @@ -58,7 +58,7 @@ // RCC Clock //--------------------------------------------------------------------+ -// CPU Frequency (Core Clock) is 150MHz +// CPU Frequency (Core Clock) is 170 MHz static inline void board_clock_init(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; @@ -74,9 +74,9 @@ static inline void board_clock_init(void) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4; - RCC_OscInitStruct.PLL.PLLN = 75; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4; + RCC_OscInitStruct.PLL.PLLN = 85; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV10; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; HAL_RCC_OscConfig(&RCC_OscInitStruct); diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c index 6c870ac7a..d0601b385 100644 --- a/hw/bsp/stm32g4/family.c +++ b/hw/bsp/stm32g4/family.c @@ -30,132 +30,6 @@ #include "bsp/board.h" #include "board.h" - -//--------------------------------------------------------------------+ -// USB PD -//--------------------------------------------------------------------+ - -void usbpd_init(uint8_t port_num, tusb_typec_port_type_t port_type) { - (void) port_num; - - // Initialization phase: CFG1 - UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) | - (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) | - ( 0 << UCPD_CFG1_TXDMAEN_Pos) | (0 << UCPD_CFG1_RXDMAEN_Pos); - UCPD1->CFG1 |= UCPD_CFG1_UCPDEN; - - // General programming sequence (with UCPD configured then enabled) - if (port_type == TUSB_TYPEC_PORT_SNK) { - // Enable both CC Phy - UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos); - - // Read Voltage State on CC1 & CC2 fore initial state - uint32_t vstate_cc[2]; - vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; - vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03; - - TU_LOG1_INT(vstate_cc[0]); - TU_LOG1_INT(vstate_cc[1]); - - // Enable CC1 & CC2 Interrupt - UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE; - } - - // Enable interrupt - NVIC_EnableIRQ(UCPD1_IRQn); -} - -uint8_t pd_rx_buf[262]; -uint32_t pd_rx_count = 0; - -void UCPD1_IRQHandler(void) { - uint32_t sr = UCPD1->SR; - sr &= UCPD1->IMR; - -// TU_LOG1("UCPD1_IRQHandler: sr = 0x%08X\n", sr); - - if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) { - uint32_t vstate_cc[2]; - vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; - vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03; - - TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]); - - uint32_t cr = UCPD1->CR; - - // TODO only support SNK for now, required highest voltage for now - if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) { - TU_LOG1("Attach CC1\n"); - cr &= ~UCPD_CR_PHYCCSEL; - cr |= UCPD_CR_PHYRXEN; - } else if ((sr & UCPD_SR_TYPECEVT2) && (vstate_cc[1] == 3)) { - TU_LOG1("Attach CC2\n"); - cr |= UCPD_CR_PHYCCSEL; - cr |= UCPD_CR_PHYRXEN; - } else { - TU_LOG1("Detach\n"); - cr &= ~UCPD_CR_PHYRXEN; - } - - if (cr & UCPD_CR_PHYRXEN) { - // Enable Interrupt - UCPD1->IMR |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE | - UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | - UCPD_IMR_RXMSGENDIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE; - } - - // Enable PD RX - UCPD1->CR = cr; - - // ack - UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF; - } - - //------------- Receive -------------// - if (sr & UCPD_SR_RXORDDET) { - // SOP: Start of Packet. - // uint8_t order_set = UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk; - - // reset count when received SOP - pd_rx_count = 0; - - // ack - UCPD1->ICR = UCPD_ICR_RXORDDETCF; - } - - if (sr & UCPD_SR_RXNE) { - // TODO DMA later - do { - pd_rx_buf[pd_rx_count++] = UCPD1->RXDR; - } while (UCPD1->SR & UCPD_SR_RXNE); - } - - if (sr & UCPD_SR_RXMSGEND) { - // End of message - uint32_t payload_size = UCPD1->RX_PAYSZ; - - // ack - UCPD1->ICR = UCPD_ICR_RXMSGENDCF; - } - - if (sr & UCPD_SR_RXOVR) { - TU_LOG1("RXOVR\n"); - TU_LOG1_HEX(pd_rx_count); - // ack - UCPD1->ICR = UCPD_ICR_RXOVRCF; - } - -// if (sr & UCPD_SR_RXNE) { -// uint8_t data = UCPD1->RXDR; -// pd_rx_buf[pd_rx_count++] = data; -// TU_LOG1_HEX(data); -// } - -// else { -// TU_LOG_LOCATION(); -// } -} - //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ @@ -174,6 +48,11 @@ void USBWakeUp_IRQHandler(void) tud_int_handler(0); } +// USB PD +void UCPD1_IRQHandler(void) { + tuc_int_handler(0); +} + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ @@ -274,8 +153,6 @@ void board_init(void) // Default CC1/CC2 is PB4/PB6 // PB4 ------> UCPD1_CC2 // PB6 ------> UCPD1_CC1 - - usbpd_init(0, TUSB_TYPEC_PORT_SNK); #endif } diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake index 2c10a9769..618563f66 100644 --- a/hw/bsp/stm32g4/family.cmake +++ b/hw/bsp/stm32g4/family.cmake @@ -90,6 +90,7 @@ function(family_configure_example TARGET) target_sources(${TARGET} PUBLIC # TinyUSB Port ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + ${TOP}/src/portable/st/typec/typec_stm32.c # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 3dbd72d61..ce4486ecd 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -32,6 +32,8 @@ function(add_tinyusb TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_host.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_host.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_host.c + # typec + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/typec/utcd.c ) target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 48f765674..bb4483f7d 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -199,6 +199,8 @@ #elif TU_CHECK_MCU(OPT_MCU_STM32G4) #define TUP_USBIP_FSDEV #define TUP_USBIP_FSDEV_STM32 + #define TUP_USBIP_TYPEC_STM32 + #define TUP_DCD_ENDPOINT_MAX 8 #elif TU_CHECK_MCU(OPT_MCU_STM32G0) diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 7b82c51d9..e6b350a40 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -232,16 +232,6 @@ enum { #define TUSB_DESC_CONFIG_POWER_MA(x) ((x)/2) -//--------------------------------------------------------------------+ -// TYPE-C -//--------------------------------------------------------------------+ - -typedef enum { - TUSB_TYPEC_PORT_SRC, - TUSB_TYPEC_PORT_SNK, - TUSB_TYPEC_PORT_DRP -} tusb_typec_port_type_t; - //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ @@ -487,9 +477,9 @@ typedef struct TU_ATTR_PACKED uint16_t bcdDFUVersion; } tusb_desc_dfu_functional_t; -/*------------------------------------------------------------------*/ -/* Types - *------------------------------------------------------------------*/ +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ typedef struct TU_ATTR_PACKED{ union { struct TU_ATTR_PACKED { @@ -509,6 +499,81 @@ typedef struct TU_ATTR_PACKED{ TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct"); +//--------------------------------------------------------------------+ +// TYPE-C +//--------------------------------------------------------------------+ + +typedef enum { + TYPEC_PORT_SRC, + TYPEC_PORT_SNK, + TYPEC_PORT_DRP +} typec_port_type_t; + +typedef enum { + TYPEC_MSG_CTRL_RESERVED = 0, // 0b00000: 0 + TYPEC_MSG_CTRL_GOOD_CRC, // 0b00001: 1 + TYPEC_MSG_CTRL_GO_TO_MIN, // 0b00010: 2 + TYPEC_MSG_CTRL_ACCEPT, // 0b00011: 3 + TYPEC_MSG_CTRL_REJECT, // 0b00100: 4 + TYPEC_MSG_CTRL_PING, // 0b00101: 5 + TYPEC_MSG_CTRL_PS_RDY, // 0b00110: 6 + TYPEC_MSG_CTRL_GET_SOURCE_CAP, // 0b00111: 7 + TYPEC_MSG_CTRL_GET_SINK_CAP, // 0b01000: 8 + TYPEC_MSG_CTRL_DR_SWAP, // 0b01001: 9 + TYPEC_MSG_CTRL_PR_SWAP, // 0b01010: 10 + TYPEC_MSG_CTRL_VCONN_SWAP, // 0b01011: 11 + TYPEC_MSG_CTRL_WAIT, // 0b01100: 12 + TYPEC_MSG_CTRL_SOFT_RESET, // 0b01101: 13 + TYPEC_MSG_CTRL_DATA_RESET, // 0b01110: 14 + TYPEC_MSG_CTRL_DATA_RESET_COMPLETE, // 0b01111: 15 + TYPEC_MSG_CTRL_NOT_SUPPORTED, // 0b10000: 16 + TYPEC_MSG_CTRL_GET_SOURCE_CAP_EXTENDED, // 0b10001: 17 + TYPEC_MSG_CTRL_GET_STATUS, // 0b10010: 18 + TYPEC_MSG_CTRL_FR_SWAP, // 0b10011: 19 + TYPEC_MSG_CTRL_GET_PPS_STATUS, // 0b10100: 20 + TYPEC_MSG_CTRL_GET_COUNTRY_CODES, // 0b10101: 21 + TYPEC_MSG_CTRL_GET_SINK_CAP_EXTENDED, // 0b10110: 22 + TYPEC_MSG_CTRL_GET_SOURCE_INFO, // 0b10111: 23 + TYPEC_MSG_CTRL_REVISION, // 0b11000: 24 +} typec_msg_ctrl_type_t; + +typedef enum { + TYPEC_MSG_DATA_RESERVED = 0, // 0b00000: 0 + TYPEC_MSG_DATA_SOURCE_CAP, // 0b00001: 1 + TYPEC_MSG_DATA_REQUEST, // 0b00010: 2 + TYPEC_MSG_DATA_BIST, // 0b00011: 3 + TYPEC_MSG_DATA_SINK_CAP, // 0b00100: 4 + TYPEC_MSG_DATA_BATTERY_STATUS, // 0b00101: 5 + TYPEC_MSG_DATA_ALERT, // 0b00110: 6 + TYPEC_MSG_DATA_GET_COUNTRY_INFO, // 0b00111: 7 + TYPEC_MSG_DATA_ENTER_USB, // 0b01000: 8 + TYPEC_MSG_DATA_EPR_REQUEST, // 0b01001: 9 + TYPEC_MSG_DATA_EPR_MODE, // 0b01010: 10 + TYPEC_MSG_DATA_SRC_INFO, // 0b01011: 11 + TYPEC_MSG_DATA_REVISION, // 0b01100: 12 + TYPEC_MSG_DATA_RESERVED_13, // 0b01101: 13 + TYPEC_MSG_DATA_RESERVED_14, // 0b01110: 14 + TYPEC_MSG_DATA_VENDOR_DEFINED, // 0b01111: 15 +} typec_msg_data_type_t; + +typedef struct TU_ATTR_PACKED { + uint16_t msg_type : 5; // [0:4] + uint16_t data_role : 1; // [5] SOP only + uint16_t specs_rev : 2; // [6:7] + uint16_t power_role : 1; // [8] SOP only + uint16_t msg_id : 3; // [9:11] + uint16_t n_data_obj : 3; // [12:14] + uint16_t extended : 1; // [15] +} tusb_typec_message_header_t; + +typedef struct TU_ATTR_PACKED { + uint16_t data_size : 9; // [0:8] + uint16_t reserved : 1; // [9] + uint16_t request_chunk : 1; // [10] + uint16_t chunk_number : 4; // [11:14] + uint16_t chunked : 1; // [15] +} tusb_typec_message_header_extended_t; + TU_ATTR_PACKED_END // End of all packed definitions TU_ATTR_BIT_FIELD_ORDER_END diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c new file mode 100644 index 000000000..fd029473d --- /dev/null +++ b/src/portable/st/typec/typec_stm32.c @@ -0,0 +1,181 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "tusb_option.h" +#include "typec/tcd.h" + +#if CFG_TUC_ENABLED && defined(TUP_USBIP_TYPEC_STM32) + +#include "common/tusb_common.h" + +#include "stm32g4xx.h" + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ +uint8_t pd_rx_buf[262]; +uint32_t pd_rx_count = 0; +uint8_t pd_rx_order_set; + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +bool tcd_init(uint8_t rhport, typec_port_type_t port_type) { + (void) rhport; + + // Initialization phase: CFG1 + UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) | + (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) | + (0 << UCPD_CFG1_TXDMAEN_Pos) | (0 << UCPD_CFG1_RXDMAEN_Pos); + UCPD1->CFG1 |= UCPD_CFG1_UCPDEN; + + // General programming sequence (with UCPD configured then enabled) + if (port_type == TYPEC_PORT_SNK) { + // Enable both CC Phy + UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos); + + // Read Voltage State on CC1 & CC2 fore initial state + uint32_t vstate_cc[2]; + vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; + vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03; + + TU_LOG1_INT(vstate_cc[0]); + TU_LOG1_INT(vstate_cc[1]); + + // Enable CC1 & CC2 Interrupt + UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE; + } + + return true; +} + +// Enable interrupt +void tcd_int_enable (uint8_t rhport) { + (void) rhport; + NVIC_EnableIRQ(UCPD1_IRQn); +} + +// Disable interrupt +void tcd_int_disable(uint8_t rhport) { + (void) rhport; + NVIC_DisableIRQ(UCPD1_IRQn); +} + +void tcd_int_handler(uint8_t rhport) { + (void) rhport; + + uint32_t sr = UCPD1->SR; + sr &= UCPD1->IMR; + +// TU_LOG1("UCPD1_IRQHandler: sr = 0x%08X\n", sr); + + if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) { + uint32_t vstate_cc[2]; + vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; + vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03; + + TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]); + + uint32_t cr = UCPD1->CR; + + // TODO only support SNK for now, required highest voltage for now + if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) { + TU_LOG1("Attach CC1\n"); + cr &= ~UCPD_CR_PHYCCSEL; + cr |= UCPD_CR_PHYRXEN; + } else if ((sr & UCPD_SR_TYPECEVT2) && (vstate_cc[1] == 3)) { + TU_LOG1("Attach CC2\n"); + cr |= UCPD_CR_PHYCCSEL; + cr |= UCPD_CR_PHYRXEN; + } else { + TU_LOG1("Detach\n"); + cr &= ~UCPD_CR_PHYRXEN; + } + + if (cr & UCPD_CR_PHYRXEN) { + // Enable Interrupt + UCPD1->IMR |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE | + UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | + UCPD_IMR_RXMSGENDIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE; + } + + // Enable PD RX + UCPD1->CR = cr; + + // ack + UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF; + } + + //------------- Receive -------------// + if (sr & UCPD_SR_RXORDDET) { + // SOP: Start of Packet. + pd_rx_order_set = UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk; + + // reset count when received SOP + pd_rx_count = 0; + + // ack + UCPD1->ICR = UCPD_ICR_RXORDDETCF; + } + + if (sr & UCPD_SR_RXNE) { + // TODO DMA later + do { + pd_rx_buf[pd_rx_count++] = UCPD1->RXDR; + } while (UCPD1->SR & UCPD_SR_RXNE); + } + + if (sr & UCPD_SR_RXMSGEND) { + // End of message + + // Skip if CRC failed + if (!(sr & UCPD_SR_RXERR)) { + uint32_t payload_size = UCPD1->RX_PAYSZ; + TU_LOG1("RXMSGEND: payload_size = %u, rx count = %u\n", payload_size, pd_rx_count); + } + + // ack + UCPD1->ICR = UCPD_ICR_RXMSGENDCF; + } + + if (sr & UCPD_SR_RXOVR) { + TU_LOG1("RXOVR\n"); + TU_LOG1_HEX(pd_rx_count); + // ack + UCPD1->ICR = UCPD_ICR_RXOVRCF; + } + +// if (sr & UCPD_SR_RXNE) { +// uint8_t data = UCPD1->RXDR; +// pd_rx_buf[pd_rx_count++] = data; +// TU_LOG1_HEX(data); +// } + +// else { +// TU_LOG_LOCATION(); +// } +} + +#endif diff --git a/src/tusb.h b/src/tusb.h index b776d7d01..0b87b1969 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -40,6 +40,11 @@ #include "class/hid/hid.h" +//------------- TypeC -------------// +#if CFG_TUC_ENABLED + #include "typec/utcd.h" +#endif + //------------- HOST -------------// #if CFG_TUH_ENABLED #include "host/usbh.h" diff --git a/src/typec/tcd.h b/src/typec/tcd.h new file mode 100644 index 000000000..397c0ac83 --- /dev/null +++ b/src/typec/tcd.h @@ -0,0 +1,58 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (thach@tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_TCD_H_ +#define _TUSB_TCD_H_ + +#include "common/tusb_common.h" +#include "osal/osal.h" +#include "common/tusb_fifo.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +// Initialize controller +bool tcd_init(uint8_t rhport, typec_port_type_t port_type); + +// Enable interrupt +void tcd_int_enable (uint8_t rhport); + +// Disable interrupt +void tcd_int_disable(uint8_t rhport); + +// Interrupt Handler +void tcd_int_handler(uint8_t rhport); + +#endif diff --git a/src/typec/utcd.c b/src/typec/utcd.c new file mode 100644 index 000000000..baa95fbe5 --- /dev/null +++ b/src/typec/utcd.c @@ -0,0 +1,48 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (thach@tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUC_ENABLED + +#include "tcd.h" + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +bool tuc_init(uint8_t rhport, typec_port_type_t port_type) { + TU_ASSERT(tcd_init(rhport, port_type)); + tcd_int_enable(rhport); + return true; +} + +#endif diff --git a/src/typec/utcd.h b/src/typec/utcd.h new file mode 100644 index 000000000..2f9b84fb7 --- /dev/null +++ b/src/typec/utcd.h @@ -0,0 +1,54 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_UTCD_H_ +#define _TUSB_UTCD_H_ + +#include "common/tusb_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------+ +// Application API +//--------------------------------------------------------------------+ + +// init typec stack +bool tuc_init(uint8_t rhport, typec_port_type_t port_type); + +#ifndef _TUSB_TCD_H_ +extern void tcd_int_handler(uint8_t rhport); +#endif + +// Interrupt handler, name alias to TCD +#define tuc_int_handler tcd_int_handler + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +#endif -- cgit v1.3.1 From 8bb012e50b39d9ed05c80509e69f9e26d463367c Mon Sep 17 00:00:00 2001 From: Aladdin Bakosh Date: Wed, 7 Jun 2023 12:01:59 +0200 Subject: fix(RA): static assert RUSB2 register --- src/portable/renesas/rusb2/rusb2_type.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index d80ecc62e..90ba4f012 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -1599,6 +1599,7 @@ TU_ATTR_BIT_FIELD_ORDER_END //--------------------------------------------------------------------+ TU_VERIFY_STATIC(sizeof(RUSB2_PIPE_TR_t) == 4, "incorrect size"); +TU_VERIFY_STATIC(sizeof(RUSB2_REG_t) == 1032, "incorrect size"); TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSCFG ) == 0x00000000, "incorrect offset"); TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BUSWAIT ) == 0x00000002, "incorrect offset"); -- cgit v1.3.1 From 9b7dee563e83a548f0d0fb68dd991a868a6427c9 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 7 Jun 2023 18:57:48 +0700 Subject: able to response with good crc --- examples/typec/power_delivery/src/main.c | 2 +- src/common/tusb_mcu.h | 5 ++ src/common/tusb_types.h | 112 +++++++++++++++++-------------- src/device/usbd.c | 10 +++ src/host/usbh.c | 2 +- src/portable/st/typec/typec_stm32.c | 105 +++++++++++++++++++++++++---- src/typec/tcd.h | 15 ++++- src/typec/utcd.c | 57 +++++++++++++++- src/typec/utcd.h | 16 ++++- 9 files changed, 253 insertions(+), 71 deletions(-) (limited to 'src') diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c index 9d032b6bb..648345a55 100644 --- a/examples/typec/power_delivery/src/main.c +++ b/examples/typec/power_delivery/src/main.c @@ -54,7 +54,7 @@ int main(void) board_init(); board_led_write(true); - tuc_init(0, TYPEC_PORT_SNK); + tuc_init(0, TUSB_TYPEC_PORT_SNK); uint32_t start_ms = 0; bool led_state = false; diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index bb4483f7d..f89467e75 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -197,12 +197,17 @@ #define TUP_DCD_ENDPOINT_MAX 9 #elif TU_CHECK_MCU(OPT_MCU_STM32G4) + // Device controller #define TUP_USBIP_FSDEV #define TUP_USBIP_FSDEV_STM32 + + // TypeC controller #define TUP_USBIP_TYPEC_STM32 #define TUP_DCD_ENDPOINT_MAX 8 + #define TUP_TYPEC_RHPORTS_NUM 1 + #elif TU_CHECK_MCU(OPT_MCU_STM32G0) #define TUP_USBIP_FSDEV #define TUP_USBIP_FSDEV_STM32 diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index e6b350a40..c92320e5c 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -504,67 +504,75 @@ TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct"); //--------------------------------------------------------------------+ typedef enum { - TYPEC_PORT_SRC, - TYPEC_PORT_SNK, - TYPEC_PORT_DRP -} typec_port_type_t; + TUSB_TYPEC_PORT_SRC, + TUSB_TYPEC_PORT_SNK, + TUSB_TYPEC_PORT_DRP +} tusb_typec_port_type_t; typedef enum { - TYPEC_MSG_CTRL_RESERVED = 0, // 0b00000: 0 - TYPEC_MSG_CTRL_GOOD_CRC, // 0b00001: 1 - TYPEC_MSG_CTRL_GO_TO_MIN, // 0b00010: 2 - TYPEC_MSG_CTRL_ACCEPT, // 0b00011: 3 - TYPEC_MSG_CTRL_REJECT, // 0b00100: 4 - TYPEC_MSG_CTRL_PING, // 0b00101: 5 - TYPEC_MSG_CTRL_PS_RDY, // 0b00110: 6 - TYPEC_MSG_CTRL_GET_SOURCE_CAP, // 0b00111: 7 - TYPEC_MSG_CTRL_GET_SINK_CAP, // 0b01000: 8 - TYPEC_MSG_CTRL_DR_SWAP, // 0b01001: 9 - TYPEC_MSG_CTRL_PR_SWAP, // 0b01010: 10 - TYPEC_MSG_CTRL_VCONN_SWAP, // 0b01011: 11 - TYPEC_MSG_CTRL_WAIT, // 0b01100: 12 - TYPEC_MSG_CTRL_SOFT_RESET, // 0b01101: 13 - TYPEC_MSG_CTRL_DATA_RESET, // 0b01110: 14 - TYPEC_MSG_CTRL_DATA_RESET_COMPLETE, // 0b01111: 15 - TYPEC_MSG_CTRL_NOT_SUPPORTED, // 0b10000: 16 - TYPEC_MSG_CTRL_GET_SOURCE_CAP_EXTENDED, // 0b10001: 17 - TYPEC_MSG_CTRL_GET_STATUS, // 0b10010: 18 - TYPEC_MSG_CTRL_FR_SWAP, // 0b10011: 19 - TYPEC_MSG_CTRL_GET_PPS_STATUS, // 0b10100: 20 - TYPEC_MSG_CTRL_GET_COUNTRY_CODES, // 0b10101: 21 - TYPEC_MSG_CTRL_GET_SINK_CAP_EXTENDED, // 0b10110: 22 - TYPEC_MSG_CTRL_GET_SOURCE_INFO, // 0b10111: 23 - TYPEC_MSG_CTRL_REVISION, // 0b11000: 24 -} typec_msg_ctrl_type_t; + TUSB_PD_CTRL_RESERVED = 0, // 0b00000: 0 + TUSB_PD_CTRL_GOOD_CRC, // 0b00001: 1 + TUSB_PD_CTRL_GO_TO_MIN, // 0b00010: 2 + TUSB_PD_CTRL_ACCEPT, // 0b00011: 3 + TUSB_PD_CTRL_REJECT, // 0b00100: 4 + TUSB_PD_CTRL_PING, // 0b00101: 5 + TUSB_PD_CTRL_PS_RDY, // 0b00110: 6 + TUSB_PD_CTRL_GET_SOURCE_CAP, // 0b00111: 7 + TUSB_PD_CTRL_GET_SINK_CAP, // 0b01000: 8 + TUSB_PD_CTRL_DR_SWAP, // 0b01001: 9 + TUSB_PD_CTRL_PR_SWAP, // 0b01010: 10 + TUSB_PD_CTRL_VCONN_SWAP, // 0b01011: 11 + TUSB_PD_CTRL_WAIT, // 0b01100: 12 + TUSB_PD_CTRL_SOFT_RESET, // 0b01101: 13 + TUSB_PD_CTRL_DATA_RESET, // 0b01110: 14 + TUSB_PD_CTRL_DATA_RESET_COMPLETE, // 0b01111: 15 + TUSB_PD_CTRL_NOT_SUPPORTED, // 0b10000: 16 + TUSB_PD_CTRL_GET_SOURCE_CAP_EXTENDED, // 0b10001: 17 + TUSB_PD_CTRL_GET_STATUS, // 0b10010: 18 + TUSB_PD_CTRL_FR_SWAP, // 0b10011: 19 + TUSB_PD_CTRL_GET_PPS_STATUS, // 0b10100: 20 + TUSB_PD_CTRL_GET_COUNTRY_CODES, // 0b10101: 21 + TUSB_PD_CTRL_GET_SINK_CAP_EXTENDED, // 0b10110: 22 + TUSB_PD_CTRL_GET_SOURCE_INFO, // 0b10111: 23 + TUSB_PD_CTRL_REVISION, // 0b11000: 24 +} tusb_pd_ctrl_type_t; typedef enum { - TYPEC_MSG_DATA_RESERVED = 0, // 0b00000: 0 - TYPEC_MSG_DATA_SOURCE_CAP, // 0b00001: 1 - TYPEC_MSG_DATA_REQUEST, // 0b00010: 2 - TYPEC_MSG_DATA_BIST, // 0b00011: 3 - TYPEC_MSG_DATA_SINK_CAP, // 0b00100: 4 - TYPEC_MSG_DATA_BATTERY_STATUS, // 0b00101: 5 - TYPEC_MSG_DATA_ALERT, // 0b00110: 6 - TYPEC_MSG_DATA_GET_COUNTRY_INFO, // 0b00111: 7 - TYPEC_MSG_DATA_ENTER_USB, // 0b01000: 8 - TYPEC_MSG_DATA_EPR_REQUEST, // 0b01001: 9 - TYPEC_MSG_DATA_EPR_MODE, // 0b01010: 10 - TYPEC_MSG_DATA_SRC_INFO, // 0b01011: 11 - TYPEC_MSG_DATA_REVISION, // 0b01100: 12 - TYPEC_MSG_DATA_RESERVED_13, // 0b01101: 13 - TYPEC_MSG_DATA_RESERVED_14, // 0b01110: 14 - TYPEC_MSG_DATA_VENDOR_DEFINED, // 0b01111: 15 -} typec_msg_data_type_t; + TUSB_PD_DATA_RESERVED = 0, // 0b00000: 0 + TUSB_PD_DATA_SOURCE_CAP, // 0b00001: 1 + TUSB_PD_DATA_REQUEST, // 0b00010: 2 + TUSB_PD_DATA_BIST, // 0b00011: 3 + TUSB_PD_DATA_SINK_CAP, // 0b00100: 4 + TUSB_PD_DATA_BATTERY_STATUS, // 0b00101: 5 + TUSB_PD_DATA_ALERT, // 0b00110: 6 + TUSB_PD_DATA_GET_COUNTRY_INFO, // 0b00111: 7 + TUSB_PD_DATA_ENTER_USB, // 0b01000: 8 + TUSB_PD_DATA_EPR_REQUEST, // 0b01001: 9 + TUSB_PD_DATA_EPR_MODE, // 0b01010: 10 + TUSB_PD_DATA_SRC_INFO, // 0b01011: 11 + TUSB_PD_DATA_REVISION, // 0b01100: 12 + TUSB_PD_DATA_RESERVED_13, // 0b01101: 13 + TUSB_PD_DATA_RESERVED_14, // 0b01110: 14 + TUSB_PD_DATA_VENDOR_DEFINED, // 0b01111: 15 +} tusb_pd_data_type_t; + +enum { + TUSB_PD_REV10 = 0x0, + TUSB_PD_REV20 = 0x1, + TUSB_PD_REV30 = 0x2, +}; typedef struct TU_ATTR_PACKED { uint16_t msg_type : 5; // [0:4] - uint16_t data_role : 1; // [5] SOP only + uint16_t data_role : 1; // [5] SOP only: 0 UFP, 1 DFP uint16_t specs_rev : 2; // [6:7] - uint16_t power_role : 1; // [8] SOP only + uint16_t power_role : 1; // [8] SOP only: 0 Sink, 1 Source uint16_t msg_id : 3; // [9:11] uint16_t n_data_obj : 3; // [12:14] uint16_t extended : 1; // [15] -} tusb_typec_message_header_t; +} tusb_pd_header_t; + +TU_VERIFY_STATIC( sizeof(tusb_pd_header_t) == 2, "size is not correct"); typedef struct TU_ATTR_PACKED { uint16_t data_size : 9; // [0:8] @@ -572,7 +580,9 @@ typedef struct TU_ATTR_PACKED { uint16_t request_chunk : 1; // [10] uint16_t chunk_number : 4; // [11:14] uint16_t chunked : 1; // [15] -} tusb_typec_message_header_extended_t; +} tusb_pd_header_extended_t; + +TU_VERIFY_STATIC( sizeof(tusb_pd_header_extended_t) == 2, "size is not correct"); TU_ATTR_PACKED_END // End of all packed definitions diff --git a/src/device/usbd.c b/src/device/usbd.c index 409a5ec10..44c2530ce 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -252,9 +252,19 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid) drvid -= _app_driver_count; } + // when there is no built-in drivers BUILTIN_DRIVER_COUNT = 0 will cause -Wtype-limits warning +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wtype-limits" +#endif + // Built-in drivers if (drvid < BUILTIN_DRIVER_COUNT) return &_usbd_driver[drvid]; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + return NULL; } diff --git a/src/host/usbh.c b/src/host/usbh.c index 6159044ab..98e959a12 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -724,7 +724,7 @@ uint8_t* usbh_get_enum_buf(void) void usbh_int_set(bool enabled) { - // TODO all host controller if multiple is used + // TODO all host controller if multiple are used since they shared the same event queue if (enabled) { hcd_int_enable(_usbh_controller); diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c index fd029473d..79f37b729 100644 --- a/src/portable/st/typec/typec_stm32.c +++ b/src/portable/st/typec/typec_stm32.c @@ -29,20 +29,43 @@ #include "common/tusb_common.h" -#include "stm32g4xx.h" +#if CFG_TUSB_MCU == OPT_MCU_STM32G4 + #include "stm32g4xx.h" +#else + #error "Unsupported STM32 family" +#endif //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ -uint8_t pd_rx_buf[262]; -uint32_t pd_rx_count = 0; -uint8_t pd_rx_order_set; + +#define PHY_SYNC1 0x18u +#define PHY_SYNC2 0x11u +#define PHY_SYNC3 0x06u +#define PHY_RST1 0x07u +#define PHY_RST2 0x19u +#define PHY_EOP 0x0Du + +#define PHY_ORDERED_SET_SOP (PHY_SYNC1 | (PHY_SYNC1<<5u) | (PHY_SYNC1<<10u) | (PHY_SYNC2<<15u)) // SOP Ordered set coding +#define PHY_ORDERED_SET_SOP_P (PHY_SYNC1 | (PHY_SYNC1<<5u) | (PHY_SYNC3<<10u) | (PHY_SYNC3<<15u)) // SOP' Ordered set coding +#define PHY_ORDERED_SET_SOP_PP (PHY_SYNC1 | (PHY_SYNC3<<5u) | (PHY_SYNC1<<10u) | (PHY_SYNC3<<15u)) // SOP'' Ordered set coding +#define PHY_ORDERED_SET_HARD_RESET (PHY_RST1 | (PHY_RST1<<5u) | (PHY_RST1<<10u) | (PHY_RST2<<15u )) // Hard Reset Ordered set coding +#define PHY_ORDERED_SET_CABLE_RESET (PHY_RST1 | (PHY_SYNC1<<5u) | (PHY_RST1<<10u) | (PHY_SYNC3<<15u)) // Cable Reset Ordered set coding +#define PHY_ORDERED_SET_SOP_P_DEBUG (PHY_SYNC1 | (PHY_RST2<<5u) | (PHY_RST2<<10u) | (PHY_SYNC3<<15u)) // SOP' Debug Ordered set coding +#define PHY_ORDERED_SET_SOP_PP_DEBUG (PHY_SYNC1 | (PHY_RST2<<5u) | (PHY_SYNC3<<10u) | (PHY_SYNC2<<15u)) // SOP'' Debug Ordered set coding + + +static uint8_t rx_buf[262] TU_ATTR_ALIGNED(4); +static uint32_t rx_count = 0; + +static uint8_t tx_buf[262] TU_ATTR_ALIGNED(4); +static uint32_t tx_count; //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ -bool tcd_init(uint8_t rhport, typec_port_type_t port_type) { +bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) { (void) rhport; // Initialization phase: CFG1 @@ -52,7 +75,7 @@ bool tcd_init(uint8_t rhport, typec_port_type_t port_type) { UCPD1->CFG1 |= UCPD_CFG1_UCPDEN; // General programming sequence (with UCPD configured then enabled) - if (port_type == TYPEC_PORT_SNK) { + if (port_type == TUSB_TYPEC_PORT_SNK) { // Enable both CC Phy UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos); @@ -83,6 +106,19 @@ void tcd_int_disable(uint8_t rhport) { NVIC_DisableIRQ(UCPD1_IRQn); } +bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) { + (void) rhport; + + return true; +} + +bool tcd_tx_start(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes) { + (void) rhport; + (void) buffer; + (void) total_bytes; + return false; +} + void tcd_int_handler(uint8_t rhport) { (void) rhport; @@ -116,7 +152,7 @@ void tcd_int_handler(uint8_t rhport) { if (cr & UCPD_CR_PHYRXEN) { // Enable Interrupt - UCPD1->IMR |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE | + UCPD1->IMR |= UCPD_IMR_TXISIE | UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE | UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE; } @@ -128,13 +164,13 @@ void tcd_int_handler(uint8_t rhport) { UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF; } - //------------- Receive -------------// + //------------- RX -------------// if (sr & UCPD_SR_RXORDDET) { // SOP: Start of Packet. - pd_rx_order_set = UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk; + // UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk; // reset count when received SOP - pd_rx_count = 0; + rx_count = 0; // ack UCPD1->ICR = UCPD_ICR_RXORDDETCF; @@ -143,17 +179,38 @@ void tcd_int_handler(uint8_t rhport) { if (sr & UCPD_SR_RXNE) { // TODO DMA later do { - pd_rx_buf[pd_rx_count++] = UCPD1->RXDR; + rx_buf[rx_count++] = UCPD1->RXDR; } while (UCPD1->SR & UCPD_SR_RXNE); + + // no ack needed } + // End of message if (sr & UCPD_SR_RXMSGEND) { - // End of message // Skip if CRC failed if (!(sr & UCPD_SR_RXERR)) { uint32_t payload_size = UCPD1->RX_PAYSZ; - TU_LOG1("RXMSGEND: payload_size = %u, rx count = %u\n", payload_size, pd_rx_count); + // TU_LOG1("RXMSGEND: payload_size = %u, rx count = %u\n", payload_size, pd_rx_count); + + tusb_pd_header_t const* rx_header = (tusb_pd_header_t const*) rx_buf; + (*(tusb_pd_header_t*) tx_buf) = (tusb_pd_header_t) { + .msg_type = TUSB_PD_CTRL_GOOD_CRC, + .data_role = 0, // UFP + .specs_rev = TUSB_PD_REV30, + .power_role = 0, // Sink + .msg_id = rx_header->msg_id, + .n_data_obj = 0, + .extended = 0 + }; + tx_count = 0; + + // response with good crc + UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP; + UCPD1->TX_PAYSZ = 2; + UCPD1->CR |= UCPD_CR_TXSEND; // will trigger TXIS interrupt + + // notify stack after good crc ? } // ack @@ -162,11 +219,31 @@ void tcd_int_handler(uint8_t rhport) { if (sr & UCPD_SR_RXOVR) { TU_LOG1("RXOVR\n"); - TU_LOG1_HEX(pd_rx_count); + TU_LOG1_HEX(rx_count); // ack UCPD1->ICR = UCPD_ICR_RXOVRCF; } + //------------- TX -------------// + if (sr & UCPD_SR_TXIS) { + // TU_LOG1("TXIS\n"); + + // TODO DMA later + do { + UCPD1->TXDR = tx_buf[tx_count++]; + } while (UCPD1->SR & UCPD_SR_TXIS); + + // no ack needed + } + + if (sr & UCPD_SR_TXMSGSENT) { + // all byte sent + TU_LOG1("TXMSGSENT\n"); + + // ack + UCPD1->ICR = UCPD_ICR_TXMSGSENTCF; + } + // if (sr & UCPD_SR_RXNE) { // uint8_t data = UCPD1->RXDR; // pd_rx_buf[pd_rx_count++] = data; diff --git a/src/typec/tcd.h b/src/typec/tcd.h index 397c0ac83..e823bf8d7 100644 --- a/src/typec/tcd.h +++ b/src/typec/tcd.h @@ -38,13 +38,19 @@ extern "C" { //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ +typedef struct { + uint8_t rhport; + uint8_t event_id; + + +} tcd_event_t;; //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ // Initialize controller -bool tcd_init(uint8_t rhport, typec_port_type_t port_type); +bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type); // Enable interrupt void tcd_int_enable (uint8_t rhport); @@ -55,4 +61,11 @@ void tcd_int_disable(uint8_t rhport); // Interrupt Handler void tcd_int_handler(uint8_t rhport); +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes); +bool tcd_tx_start(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes); + #endif diff --git a/src/typec/utcd.c b/src/typec/utcd.c index baa95fbe5..b5f9965fe 100644 --- a/src/typec/utcd.c +++ b/src/typec/utcd.c @@ -29,20 +29,75 @@ #if CFG_TUC_ENABLED #include "tcd.h" +#include "utcd.h" //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ +// Debug level of USBD +#define UTCD_DEBUG 2 +#define TU_LOG_UTCD(...) TU_LOG(UTCD_DEBUG, __VA_ARGS__) + +// Event queue +// utcd_int_set() is used as mutex in OS NONE config +void utcd_int_set(bool enabled); +OSAL_QUEUE_DEF(utcd_int_set, utcd_qdef, CFG_TUC_TASK_QUEUE_SZ, tcd_event_t); +tu_static osal_queue_t utcd_q; + +// if stack is initialized +static bool utcd_inited = false; + +// if port is initialized +static bool port_inited[TUP_TYPEC_RHPORTS_NUM]; //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ +bool tuc_inited(uint8_t rhport) { + return utcd_inited && port_inited[rhport]; +} + +bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) { + // Initialize stack + if (!utcd_inited) { + tu_memclr(port_inited, sizeof(port_inited)); + + utcd_q = osal_queue_create(&utcd_qdef); + TU_ASSERT(utcd_q != NULL); + + utcd_inited = true; + } + + // skip if port already initialized + if ( port_inited[rhport] ) { + return true; + } + + TU_LOG_UTCD("UTCD init on port %u\r\n", rhport); -bool tuc_init(uint8_t rhport, typec_port_type_t port_type) { TU_ASSERT(tcd_init(rhport, port_type)); tcd_int_enable(rhport); + + port_inited[rhport] = true; return true; } + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ +void utcd_int_set(bool enabled) { + // Disable all controllers since they shared the same event queue + for (uint8_t p = 0; p < TUP_TYPEC_RHPORTS_NUM; p++) { + if ( port_inited[p] ) { + if (enabled) { + tcd_int_enable(p); + }else { + tcd_int_disable(p); + } + } + } +} + #endif diff --git a/src/typec/utcd.h b/src/typec/utcd.h index 2f9b84fb7..06a62ef23 100644 --- a/src/typec/utcd.h +++ b/src/typec/utcd.h @@ -33,12 +33,24 @@ extern "C" { #endif +//--------------------------------------------------------------------+ +// TypeC Configuration +//--------------------------------------------------------------------+ + +#ifndef CFG_TUC_TASK_QUEUE_SZ +#define CFG_TUC_TASK_QUEUE_SZ 16 +#endif + + //--------------------------------------------------------------------+ // Application API //--------------------------------------------------------------------+ -// init typec stack -bool tuc_init(uint8_t rhport, typec_port_type_t port_type); +// Init typec stack on a port +bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type); + +// Check if typec port is initialized +bool tuc_inited(uint8_t rhport); #ifndef _TUSB_TCD_H_ extern void tcd_int_handler(uint8_t rhport); -- cgit v1.3.1 From 7fd0a17bc3eb1e992865c851c3d24484131fa284 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 8 Jun 2023 09:11:29 +0700 Subject: default CFG_TUC_ENABLED to 0 --- src/tusb_option.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src') diff --git a/src/tusb_option.h b/src/tusb_option.h index 948c9edf3..427d19719 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -483,6 +483,14 @@ #endif +//--------------------------------------------------------------------+ +// TypeC Options (Default) +//--------------------------------------------------------------------+ + +#ifndef CFG_TUC_ENABLED +#define CFG_TUC_ENABLED 0 +#endif + //------------------------------------------------------------------ // Configuration Validation //------------------------------------------------------------------ -- cgit v1.3.1 From fc761953b323b7565c42254fcfbb248520d83e0e Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 8 Jun 2023 09:34:15 +0700 Subject: define tuc_int_handler() to empty if TUC not enabled --- src/tusb_option.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/tusb_option.h b/src/tusb_option.h index 427d19719..bb669e693 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -489,6 +489,8 @@ #ifndef CFG_TUC_ENABLED #define CFG_TUC_ENABLED 0 + +#define tuc_int_handler(_p) #endif //------------------------------------------------------------------ -- cgit v1.3.1 From 9c2a8490afadd47d5847793a806e2dce51565868 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 8 Jun 2023 13:37:37 +0700 Subject: dma rx works well --- .../stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc | 194 +++++++++++++++++++++ hw/bsp/stm32g4/family.c | 7 +- src/portable/st/typec/typec_stm32.c | 80 +++++++-- 3 files changed, 267 insertions(+), 14 deletions(-) create mode 100644 hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc (limited to 'src') diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc b/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc new file mode 100644 index 000000000..6ce126f84 --- /dev/null +++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc @@ -0,0 +1,194 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +Dma.Request0=UCPD1_RX +Dma.Request1=UCPD1_TX +Dma.RequestsNb=2 +Dma.UCPD1_RX.0.Direction=DMA_PERIPH_TO_MEMORY +Dma.UCPD1_RX.0.EventEnable=DISABLE +Dma.UCPD1_RX.0.Instance=DMA1_Channel1 +Dma.UCPD1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.UCPD1_RX.0.MemInc=DMA_MINC_ENABLE +Dma.UCPD1_RX.0.Mode=DMA_NORMAL +Dma.UCPD1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.UCPD1_RX.0.PeriphInc=DMA_PINC_DISABLE +Dma.UCPD1_RX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.UCPD1_RX.0.Priority=DMA_PRIORITY_HIGH +Dma.UCPD1_RX.0.RequestNumber=1 +Dma.UCPD1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.UCPD1_RX.0.SignalID=NONE +Dma.UCPD1_RX.0.SyncEnable=DISABLE +Dma.UCPD1_RX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.UCPD1_RX.0.SyncRequestNumber=1 +Dma.UCPD1_RX.0.SyncSignalID=NONE +Dma.UCPD1_TX.1.Direction=DMA_MEMORY_TO_PERIPH +Dma.UCPD1_TX.1.EventEnable=DISABLE +Dma.UCPD1_TX.1.Instance=DMA1_Channel2 +Dma.UCPD1_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.UCPD1_TX.1.MemInc=DMA_MINC_ENABLE +Dma.UCPD1_TX.1.Mode=DMA_NORMAL +Dma.UCPD1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.UCPD1_TX.1.PeriphInc=DMA_PINC_DISABLE +Dma.UCPD1_TX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.UCPD1_TX.1.Priority=DMA_PRIORITY_HIGH +Dma.UCPD1_TX.1.RequestNumber=1 +Dma.UCPD1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.UCPD1_TX.1.SignalID=NONE +Dma.UCPD1_TX.1.SyncEnable=DISABLE +Dma.UCPD1_TX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.UCPD1_TX.1.SyncRequestNumber=1 +Dma.UCPD1_TX.1.SyncSignalID=NONE +File.Version=6 +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=true +Mcu.CPN=STM32G474RET3 +Mcu.Family=STM32G4 +Mcu.IP0=DMA +Mcu.IP1=NVIC +Mcu.IP2=RCC +Mcu.IP3=SYS +Mcu.IP4=UCPD1 +Mcu.IP5=USART3 +Mcu.IPNb=6 +Mcu.Name=STM32G474R(B-C-E)Tx +Mcu.Package=LQFP64 +Mcu.Pin0=PC10 +Mcu.Pin1=PC11 +Mcu.Pin2=PB4 +Mcu.Pin3=PB6 +Mcu.Pin4=VP_SYS_VS_Systick +Mcu.Pin5=VP_SYS_VS_DBSignals +Mcu.PinsNb=6 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32G474RETx +MxCube.Version=6.8.1 +MxDb.Version=DB.6.0.81 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false +NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:false +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false +PB4.Mode=Sink_AllSignals +PB4.Signal=UCPD1_CC2 +PB6.Mode=Sink_AllSignals +PB6.Signal=UCPD1_CC1 +PC10.GPIOParameters=GPIO_PuPd +PC10.GPIO_PuPd=GPIO_PULLUP +PC10.Mode=Asynchronous +PC10.Signal=USART3_TX +PC11.GPIOParameters=GPIO_PuPd +PC11.GPIO_PuPd=GPIO_PULLUP +PC11.Mode=Asynchronous +PC11.Signal=USART3_RX +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32G474RETx +ProjectManager.FirmwarePackage=STM32Cube FW_G4 V1.5.1 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=2 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=board.ioc +ProjectManager.ProjectName=board +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=Makefile +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_UCPD1_Init-UCPD1-false-LL-true +RCC.ADC12Freq_Value=150000000 +RCC.ADC345Freq_Value=150000000 +RCC.AHBFreq_Value=150000000 +RCC.APB1Freq_Value=150000000 +RCC.APB1TimFreq_Value=150000000 +RCC.APB2Freq_Value=150000000 +RCC.APB2TimFreq_Value=150000000 +RCC.CRSFreq_Value=48000000 +RCC.CortexFreq_Value=150000000 +RCC.EXTERNAL_CLOCK_VALUE=12288000 +RCC.FCLKCortexFreq_Value=150000000 +RCC.FDCANFreq_Value=150000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=150000000 +RCC.HRTIM1Freq_Value=150000000 +RCC.HSE_VALUE=24000000 +RCC.HSI48_VALUE=48000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=150000000 +RCC.I2C2Freq_Value=150000000 +RCC.I2C3Freq_Value=150000000 +RCC.I2C4Freq_Value=150000000 +RCC.I2SFreq_Value=150000000 +RCC.IPParameters=ADC12Freq_Value,ADC345Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HRTIM1Freq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQ,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,QSPIFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value +RCC.LPTIM1Freq_Value=150000000 +RCC.LPUART1Freq_Value=150000000 +RCC.LSCOPinFreq_Value=32000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO1PinFreq_Value=16000000 +RCC.PLLM=RCC_PLLM_DIV4 +RCC.PLLN=75 +RCC.PLLPoutputFreq_Value=150000000 +RCC.PLLQ=RCC_PLLQ_DIV4 +RCC.PLLQoutputFreq_Value=75000000 +RCC.PLLRCLKFreq_Value=150000000 +RCC.PWRFreq_Value=150000000 +RCC.QSPIFreq_Value=150000000 +RCC.RNGFreq_Value=75000000 +RCC.SAI1Freq_Value=150000000 +RCC.SYSCLKFreq_VALUE=150000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.UART4Freq_Value=150000000 +RCC.UART5Freq_Value=150000000 +RCC.USART1Freq_Value=150000000 +RCC.USART2Freq_Value=150000000 +RCC.USART3Freq_Value=150000000 +RCC.USBFreq_Value=75000000 +RCC.VCOInputFreq_Value=4000000 +RCC.VCOOutputFreq_Value=300000000 +USART3.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE +USART3.BaudRate=115200 +USART3.DMADisableonRxErrorParam=ADVFEATURE_DMA_ENABLEONRXERROR +USART3.DataInvertParam=ADVFEATURE_DATAINV_DISABLE +USART3.IPParameters=BaudRate,WordLength,Parity,StopBits,Mode,OverSampling,OneBitSampling,AutoBaudRateEnableParam,TxPinLevelInvertParam,RxPinLevelInvertParam,DataInvertParam,SwapParam,OverrunDisableParam,DMADisableonRxErrorParam,MSBFirstParam,VirtualMode-Asynchronous +USART3.MSBFirstParam=ADVFEATURE_MSBFIRST_DISABLE +USART3.Mode=MODE_TX_RX +USART3.OneBitSampling=UART_ONE_BIT_SAMPLE_DISABLE +USART3.OverSampling=UART_OVERSAMPLING_16 +USART3.OverrunDisableParam=ADVFEATURE_OVERRUN_ENABLE +USART3.Parity=PARITY_ODD +USART3.RxPinLevelInvertParam=ADVFEATURE_RXINV_DISABLE +USART3.StopBits=STOPBITS_1 +USART3.SwapParam=ADVFEATURE_SWAP_DISABLE +USART3.TxPinLevelInvertParam=ADVFEATURE_TXINV_DISABLE +USART3.VirtualMode-Asynchronous=VM_ASYNC +USART3.WordLength=WORDLENGTH_8B +VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals +VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c index d0601b385..5fa6e3dbb 100644 --- a/hw/bsp/stm32g4/family.c +++ b/hw/bsp/stm32g4/family.c @@ -144,15 +144,16 @@ void board_init(void) #if 1 // USB PD + // Default CC1/CC2 is PB4/PB6 /* PWR register access (for disabling dead battery feature) */ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC); __HAL_RCC_UCPD1_CLK_ENABLE(); - // Default CC1/CC2 is PB4/PB6 - // PB4 ------> UCPD1_CC2 - // PB6 ------> UCPD1_CC1 + // Enable DMA clock + __HAL_RCC_DMAMUX1_CLK_ENABLE(); + __HAL_RCC_DMA1_CLK_ENABLE(); #endif } diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c index 79f37b729..c96dd0902 100644 --- a/src/portable/st/typec/typec_stm32.c +++ b/src/portable/st/typec/typec_stm32.c @@ -31,6 +31,7 @@ #if CFG_TUSB_MCU == OPT_MCU_STM32G4 #include "stm32g4xx.h" + #include "stm32g4xx_hal_dma.h" #else #error "Unsupported STM32 family" #endif @@ -61,13 +62,46 @@ static uint32_t rx_count = 0; static uint8_t tx_buf[262] TU_ATTR_ALIGNED(4); static uint32_t tx_count; +#define CFG_TUC_STM32_DMA_RX { DMA1_Channel1 } +//#define CFG_TUC_STM32_DMA_TX { DMA1_Channel2 } + +#ifdef CFG_TUC_STM32_DMA_RX +static DMA_Channel_TypeDef* dma_rx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_RX; + +TU_ATTR_ALWAYS_INLINE static inline +void dma_rx_start(uint8_t rhport) +{ + DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport]; + + dma_rx_ch->CMAR = (uint32_t) rx_buf; + dma_rx_ch->CNDTR = sizeof(rx_buf); + dma_rx_ch->CCR |= DMA_CCR_EN; +} +#endif + +#ifdef CFG_TUC_STM32_DMA_TX +static DMA_Channel_TypeDef* dma_tx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_TX; +#endif + //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ +#include "stm32g4xx_ll_dma.h" bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) { (void) rhport; +#ifdef CFG_TUC_STM32_DMA_RX + // Init DMA + DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport]; + + // Peripheral -> Memory, Memory inc, 8-bit, High priority + dma_rx_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1; + dma_rx_ch->CPAR = (uint32_t) &UCPD1->RXDR; + + LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_UCPD1_RX); +#endif + // Initialization phase: CFG1 UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) | (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) | @@ -77,7 +111,7 @@ bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) { // General programming sequence (with UCPD configured then enabled) if (port_type == TUSB_TYPEC_PORT_SNK) { // Enable both CC Phy - UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos); + UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1; // Read Voltage State on CC1 & CC2 fore initial state uint32_t vstate_cc[2]; @@ -135,30 +169,48 @@ void tcd_int_handler(uint8_t rhport) { TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]); uint32_t cr = UCPD1->CR; + uint32_t cfg1 = UCPD1->CFG1; // TODO only support SNK for now, required highest voltage for now + // Enable PHY on correct CC and disable Rd on other CC if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) { TU_LOG1("Attach CC1\n"); - cr &= ~UCPD_CR_PHYCCSEL; - cr |= UCPD_CR_PHYRXEN; + + cr &= ~(UCPD_CR_PHYCCSEL | UCPD_CR_CCENABLE); + cr |= UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_0; } else if ((sr & UCPD_SR_TYPECEVT2) && (vstate_cc[1] == 3)) { TU_LOG1("Attach CC2\n"); - cr |= UCPD_CR_PHYCCSEL; - cr |= UCPD_CR_PHYRXEN; + cr &= ~UCPD_CR_CCENABLE; + cr |= (UCPD_CR_PHYCCSEL | UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_1); } else { TU_LOG1("Detach\n"); cr &= ~UCPD_CR_PHYRXEN; + cr |= UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1; } if (cr & UCPD_CR_PHYRXEN) { // Enable Interrupt - UCPD1->IMR |= UCPD_IMR_TXISIE | UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE | - UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | - UCPD_IMR_RXMSGENDIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE; + uint32_t imr = UCPD1->IMR; + imr |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE | + UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE | UCPD_IMR_RXORDDETIE | + UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE | UCPD_IMR_FRSEVTIE; + + #ifdef CFG_TUC_STM32_DMA_RX + cfg1 |= UCPD_CFG1_RXDMAEN; + dma_rx_start(rhport); + #else + imr |= UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE; + #endif + + #ifndef CFG_TUC_STM32_DMA_TX + imr |= UCPD_IMR_TXISIE; + #endif + + UCPD1->IMR = imr; } - // Enable PD RX UCPD1->CR = cr; + UCPD1->CFG1 = cfg1; // ack UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF; @@ -176,6 +228,7 @@ void tcd_int_handler(uint8_t rhport) { UCPD1->ICR = UCPD_ICR_RXORDDETCF; } +#ifndef CFG_TUC_STM32_DMA_RX if (sr & UCPD_SR_RXNE) { // TODO DMA later do { @@ -184,8 +237,9 @@ void tcd_int_handler(uint8_t rhport) { // no ack needed } +#endif - // End of message + // Received full message if (sr & UCPD_SR_RXMSGEND) { // Skip if CRC failed @@ -213,13 +267,17 @@ void tcd_int_handler(uint8_t rhport) { // notify stack after good crc ? } + #ifdef CFG_TUC_STM32_DMA_RX + // prepare next receive + dma_rx_start(rhport); + #endif + // ack UCPD1->ICR = UCPD_ICR_RXMSGENDCF; } if (sr & UCPD_SR_RXOVR) { TU_LOG1("RXOVR\n"); - TU_LOG1_HEX(rx_count); // ack UCPD1->ICR = UCPD_ICR_RXOVRCF; } -- cgit v1.3.1 From 8181d470e5bbb01f873d8fa11e8e1293cb76703f Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 8 Jun 2023 18:55:54 +0700 Subject: enable DMA for both pd rx, tx --- src/portable/st/typec/typec_stm32.c | 207 +++++++++++++++++++----------------- 1 file changed, 108 insertions(+), 99 deletions(-) (limited to 'src') diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c index c96dd0902..a898cda47 100644 --- a/src/portable/st/typec/typec_stm32.c +++ b/src/portable/st/typec/typec_stm32.c @@ -31,7 +31,7 @@ #if CFG_TUSB_MCU == OPT_MCU_STM32G4 #include "stm32g4xx.h" - #include "stm32g4xx_hal_dma.h" + #include "stm32g4xx_ll_dma.h" // for UCLP REQID #else #error "Unsupported STM32 family" #endif @@ -40,6 +40,12 @@ // //--------------------------------------------------------------------+ +enum { + IMR_ATTACHED = UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE | + UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE | UCPD_IMR_RXORDDETIE | + UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE | UCPD_IMR_FRSEVTIE +}; + #define PHY_SYNC1 0x18u #define PHY_SYNC2 0x11u #define PHY_SYNC3 0x06u @@ -57,55 +63,101 @@ static uint8_t rx_buf[262] TU_ATTR_ALIGNED(4); -static uint32_t rx_count = 0; - static uint8_t tx_buf[262] TU_ATTR_ALIGNED(4); -static uint32_t tx_count; +static uint32_t tx_index; -#define CFG_TUC_STM32_DMA_RX { DMA1_Channel1 } -//#define CFG_TUC_STM32_DMA_TX { DMA1_Channel2 } +// address of DMA channel rx, tx for each port +#define CFG_TUC_STM32_DMA { { DMA1_Channel1_BASE, DMA1_Channel2_BASE } } -#ifdef CFG_TUC_STM32_DMA_RX -static DMA_Channel_TypeDef* dma_rx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_RX; +//--------------------------------------------------------------------+ +// DMA +//--------------------------------------------------------------------+ -TU_ATTR_ALWAYS_INLINE static inline -void dma_rx_start(uint8_t rhport) -{ - DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport]; +static const uint32_t dma_addr_arr[TUP_TYPEC_RHPORTS_NUM][2] = CFG_TUC_STM32_DMA; - dma_rx_ch->CMAR = (uint32_t) rx_buf; - dma_rx_ch->CNDTR = sizeof(rx_buf); - dma_rx_ch->CCR |= DMA_CCR_EN; +TU_ATTR_ALWAYS_INLINE static inline uint32_t dma_get_addr(uint8_t rhport, bool is_rx) { + return dma_addr_arr[rhport][is_rx ? 0 : 1]; } -#endif -#ifdef CFG_TUC_STM32_DMA_TX -static DMA_Channel_TypeDef* dma_tx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_TX; -#endif +static void dma_init(uint8_t rhport, bool is_rx) { + uint32_t dma_addr = dma_get_addr(rhport, is_rx); + DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_addr; + uint32_t req_id; + + if (is_rx) { + // Peripheral -> Memory, Memory inc, 8-bit, High priority + dma_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1; + dma_ch->CPAR = (uint32_t) &UCPD1->RXDR; + + req_id = LL_DMAMUX_REQ_UCPD1_RX; + } else { + // Memory -> Peripheral, Memory inc, 8-bit, High priority + dma_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1 | DMA_CCR_DIR; + dma_ch->CPAR = (uint32_t) &UCPD1->TXDR; + + req_id = LL_DMAMUX_REQ_UCPD1_TX; + } + + // find and set up mux channel TODO support mcu with multiple DMAMUXs + enum { + CH_DIFF = DMA1_Channel2_BASE - DMA1_Channel1_BASE + }; + uint32_t mux_ch_num; + + #ifdef DMA2_BASE + if (dma_addr > DMA2_BASE) { + mux_ch_num = 8 * ((dma_addr - DMA2_Channel1_BASE) / CH_DIFF); + } else + #endif + { + mux_ch_num = (dma_addr - DMA1_Channel1_BASE) / CH_DIFF; + } + + DMAMUX_Channel_TypeDef* mux_ch = DMAMUX1_Channel0 + mux_ch_num; + + uint32_t mux_ccr = mux_ch->CCR & ~(DMAMUX_CxCR_DMAREQ_ID); + mux_ccr |= req_id; + mux_ch->CCR = mux_ccr; +} + +TU_ATTR_ALWAYS_INLINE static inline void dma_start(uint8_t rhport, bool is_rx, void const* buf, uint16_t len) { + DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_get_addr(rhport, is_rx); + + dma_ch->CMAR = (uint32_t) buf; + dma_ch->CNDTR = len; + dma_ch->CCR |= DMA_CCR_EN; +} + +TU_ATTR_ALWAYS_INLINE static inline void dma_stop(uint8_t rhport, bool is_rx) { + DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_get_addr(rhport, is_rx); + dma_ch->CCR &= ~DMA_CCR_EN; +} + +TU_ATTR_ALWAYS_INLINE static inline void dma_rx_start(uint8_t rhport) { + dma_start(rhport, true, rx_buf, sizeof(rx_buf)); +} + +TU_ATTR_ALWAYS_INLINE static inline void dma_tx_start(uint8_t rhport, void const* buf, uint16_t len) { + UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP; + UCPD1->TX_PAYSZ = len; + dma_start(rhport, false, buf, len); +} //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ -#include "stm32g4xx_ll_dma.h" + bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) { (void) rhport; -#ifdef CFG_TUC_STM32_DMA_RX - // Init DMA - DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport]; - - // Peripheral -> Memory, Memory inc, 8-bit, High priority - dma_rx_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1; - dma_rx_ch->CPAR = (uint32_t) &UCPD1->RXDR; - - LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_UCPD1_RX); -#endif + // Init DMA for RX, TX + dma_init(rhport, true); + dma_init(rhport, false); // Initialization phase: CFG1 UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) | - (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) | - (0 << UCPD_CFG1_TXDMAEN_Pos) | (0 << UCPD_CFG1_RXDMAEN_Pos); + (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos); UCPD1->CFG1 |= UCPD_CFG1_UCPDEN; // General programming sequence (with UCPD configured then enabled) @@ -118,8 +170,7 @@ bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) { vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03; - TU_LOG1_INT(vstate_cc[0]); - TU_LOG1_INT(vstate_cc[1]); + TU_LOG1("Initial VState CC1 = %u, CC2 = %u\r\n", vstate_cc[0], vstate_cc[1]); // Enable CC1 & CC2 Interrupt UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE; @@ -142,7 +193,8 @@ void tcd_int_disable(uint8_t rhport) { bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) { (void) rhport; - + (void) buffer; + (void) total_bytes; return true; } @@ -159,8 +211,6 @@ void tcd_int_handler(uint8_t rhport) { uint32_t sr = UCPD1->SR; sr &= UCPD1->IMR; -// TU_LOG1("UCPD1_IRQHandler: sr = 0x%08X\n", sr); - if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) { uint32_t vstate_cc[2]; vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; @@ -169,7 +219,6 @@ void tcd_int_handler(uint8_t rhport) { TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]); uint32_t cr = UCPD1->CR; - uint32_t cfg1 = UCPD1->CFG1; // TODO only support SNK for now, required highest voltage for now // Enable PHY on correct CC and disable Rd on other CC @@ -189,28 +238,18 @@ void tcd_int_handler(uint8_t rhport) { } if (cr & UCPD_CR_PHYRXEN) { - // Enable Interrupt - uint32_t imr = UCPD1->IMR; - imr |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE | - UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE | UCPD_IMR_RXORDDETIE | - UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE | UCPD_IMR_FRSEVTIE; - - #ifdef CFG_TUC_STM32_DMA_RX - cfg1 |= UCPD_CFG1_RXDMAEN; - dma_rx_start(rhport); - #else - imr |= UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE; - #endif + // Attached + UCPD1->IMR |= IMR_ATTACHED; + UCPD1->CFG1 |= UCPD_CFG1_RXDMAEN | UCPD_CFG1_TXDMAEN; - #ifndef CFG_TUC_STM32_DMA_TX - imr |= UCPD_IMR_TXISIE; - #endif - - UCPD1->IMR = imr; + dma_rx_start(rhport); + }else { + // Detached + UCPD1->CFG1 &= ~(UCPD_CFG1_RXDMAEN | UCPD_CFG1_TXDMAEN); + UCPD1->IMR &= ~IMR_ATTACHED; } UCPD1->CR = cr; - UCPD1->CFG1 = cfg1; // ack UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF; @@ -221,27 +260,15 @@ void tcd_int_handler(uint8_t rhport) { // SOP: Start of Packet. // UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk; - // reset count when received SOP - rx_count = 0; - // ack UCPD1->ICR = UCPD_ICR_RXORDDETCF; } -#ifndef CFG_TUC_STM32_DMA_RX - if (sr & UCPD_SR_RXNE) { - // TODO DMA later - do { - rx_buf[rx_count++] = UCPD1->RXDR; - } while (UCPD1->SR & UCPD_SR_RXNE); - - // no ack needed - } -#endif - // Received full message if (sr & UCPD_SR_RXMSGEND) { + dma_stop(rhport, true); + // Skip if CRC failed if (!(sr & UCPD_SR_RXERR)) { uint32_t payload_size = UCPD1->RX_PAYSZ; @@ -251,26 +278,23 @@ void tcd_int_handler(uint8_t rhport) { (*(tusb_pd_header_t*) tx_buf) = (tusb_pd_header_t) { .msg_type = TUSB_PD_CTRL_GOOD_CRC, .data_role = 0, // UFP - .specs_rev = TUSB_PD_REV30, + .specs_rev = TUSB_PD_REV20, .power_role = 0, // Sink .msg_id = rx_header->msg_id, .n_data_obj = 0, .extended = 0 }; - tx_count = 0; // response with good crc - UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP; - UCPD1->TX_PAYSZ = 2; - UCPD1->CR |= UCPD_CR_TXSEND; // will trigger TXIS interrupt + dma_tx_start(rhport, tx_buf, 2); + + UCPD1->CR |= UCPD_CR_TXSEND; - // notify stack after good crc ? + // notify stack } - #ifdef CFG_TUC_STM32_DMA_RX // prepare next receive dma_rx_start(rhport); - #endif // ack UCPD1->ICR = UCPD_ICR_RXMSGENDCF; @@ -283,34 +307,19 @@ void tcd_int_handler(uint8_t rhport) { } //------------- TX -------------// - if (sr & UCPD_SR_TXIS) { - // TU_LOG1("TXIS\n"); - - // TODO DMA later - do { - UCPD1->TXDR = tx_buf[tx_count++]; - } while (UCPD1->SR & UCPD_SR_TXIS); - - // no ack needed - } - if (sr & UCPD_SR_TXMSGSENT) { // all byte sent - TU_LOG1("TXMSGSENT\n"); + dma_stop(rhport, false); // ack UCPD1->ICR = UCPD_ICR_TXMSGSENTCF; } -// if (sr & UCPD_SR_RXNE) { -// uint8_t data = UCPD1->RXDR; -// pd_rx_buf[pd_rx_count++] = data; -// TU_LOG1_HEX(data); -// } - -// else { -// TU_LOG_LOCATION(); -// } + if (sr & (UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND)) { + TU_LOG1("TX Error\n"); + dma_stop(rhport, false); + UCPD1->ICR = UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND; + } } #endif -- cgit v1.3.1 From 08338069805a4e1b5bdf6d3bac0b694d6b10f20e Mon Sep 17 00:00:00 2001 From: Eugene Kliuchnikov Date: Thu, 8 Jun 2023 15:38:30 +0200 Subject: Fix typos --- examples/device/audio_test_multi_rate/src/usb_descriptors.h | 2 +- examples/device/uac2_headset/src/usb_descriptors.h | 4 ++-- src/class/video/video.h | 4 ++-- src/device/usbd.h | 10 +++++----- 4 files changed, 10 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/examples/device/audio_test_multi_rate/src/usb_descriptors.h b/examples/device/audio_test_multi_rate/src/usb_descriptors.h index 8d8a03e49..8381e31f5 100644 --- a/examples/device/audio_test_multi_rate/src/usb_descriptors.h +++ b/examples/device/audio_test_multi_rate/src/usb_descriptors.h @@ -60,7 +60,7 @@ #define TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESCRIPTOR(_itfnum, _stridx, _epin) \ /* Standard Interface Association Descriptor (IAD) */\ - TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\ + TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\ /* Standard AC Interface Descriptor(4.7.1) */\ TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\ /* Class-Specific AC Interface Header Descriptor(4.7.2) */\ diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h index 457e69882..d7e170162 100644 --- a/examples/device/uac2_headset/src/usb_descriptors.h +++ b/examples/device/uac2_headset/src/usb_descriptors.h @@ -57,7 +57,7 @@ enum + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\ /* Interface 1, Alternate 0 */\ + TUD_AUDIO_DESC_STD_AS_INT_LEN\ - /* Interface 1, Alternate 0 */\ + /* Interface 1, Alternate 1 */\ + TUD_AUDIO_DESC_STD_AS_INT_LEN\ + TUD_AUDIO_DESC_CS_AS_INT_LEN\ + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\ @@ -86,7 +86,7 @@ enum #define TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(_stridx, _epout, _epin) \ /* Standard Interface Association Descriptor (IAD) */\ - TUD_AUDIO_DESC_IAD(/*_firstitfs*/ ITF_NUM_AUDIO_CONTROL, /*_nitfs*/ 3, /*_stridx*/ 0x00),\ + TUD_AUDIO_DESC_IAD(/*_firstitf*/ ITF_NUM_AUDIO_CONTROL, /*_nitfs*/ ITF_NUM_TOTAL, /*_stridx*/ 0x00),\ /* Standard AC Interface Descriptor(4.7.1) */\ TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\ /* Class-Specific AC Interface Header Descriptor(4.7.2) */\ diff --git a/src/class/video/video.h b/src/class/video/video.h index c0088c4f6..d9880c291 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -448,9 +448,9 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c #define TUD_VIDEO_GUID_M420 0x4D,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71 #define TUD_VIDEO_GUID_I420 0x49,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71 -#define TUD_VIDEO_DESC_IAD(_firstitfs, _nitfs, _stridx) \ +#define TUD_VIDEO_DESC_IAD(_firstitf, _nitfs, _stridx) \ TUD_VIDEO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, \ - _firstitfs, _nitfs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_INTERFACE_COLLECTION, \ + _firstitf, _nitfs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_INTERFACE_COLLECTION, \ VIDEO_ITF_PROTOCOL_UNDEFINED, _stridx #define TUD_VIDEO_DESC_STD_VC(_itfnum, _nEPs, _stridx) \ diff --git a/src/device/usbd.h b/src/device/usbd.h index 255e5a844..b11c1a09d 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -347,8 +347,8 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Standard Interface Association Descriptor (IAD) */ #define TUD_AUDIO_DESC_IAD_LEN 8 -#define TUD_AUDIO_DESC_IAD(_firstitfs, _nitfs, _stridx) \ - TUD_AUDIO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, _firstitfs, _nitfs, TUSB_CLASS_AUDIO, AUDIO_FUNCTION_SUBCLASS_UNDEFINED, AUDIO_FUNC_PROTOCOL_CODE_V2, _stridx +#define TUD_AUDIO_DESC_IAD(_firstitf, _nitfs, _stridx) \ + TUD_AUDIO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, _firstitf, _nitfs, TUSB_CLASS_AUDIO, AUDIO_FUNCTION_SUBCLASS_UNDEFINED, AUDIO_FUNC_PROTOCOL_CODE_V2, _stridx /* Standard AC Interface Descriptor(4.7.1) */ #define TUD_AUDIO_DESC_STD_AC_LEN 9 @@ -443,7 +443,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb #define TUD_AUDIO_MIC_ONE_CH_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epin, _epsize) \ /* Standard Interface Association Descriptor (IAD) */\ - TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\ + TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\ /* Standard AC Interface Descriptor(4.7.1) */\ TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\ /* Class-Specific AC Interface Header Descriptor(4.7.2) */\ @@ -492,7 +492,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb #define TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epin, _epsize) \ /* Standard Interface Association Descriptor (IAD) */\ - TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\ + TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\ /* Standard AC Interface Descriptor(4.7.1) */\ TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\ /* Class-Specific AC Interface Header Descriptor(4.7.2) */\ @@ -540,7 +540,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb #define TUD_AUDIO_SPEAKER_MONO_FB_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epout, _epsize, _epfb) \ /* Standard Interface Association Descriptor (IAD) */\ - TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\ + TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\ /* Standard AC Interface Descriptor(4.7.1) */\ TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\ /* Class-Specific AC Interface Header Descriptor(4.7.2) */\ -- cgit v1.3.1 From 912802456b568e4b666a9205c3799da79f87ef69 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 9 Jun 2023 18:15:28 +0700 Subject: move protocol message to stack, disable battery in PWR's CR3 there is still issue with CC1/CC2 pull down resistor and vstate is not correct. --- hw/bsp/stm32g4/family.c | 8 +-- src/device/dcd.h | 1 + src/portable/st/typec/typec_stm32.c | 113 ++++++++++++++++++------------------ src/typec/tcd.h | 52 +++++++++++++++++ src/typec/utcd.c | 61 ++++++++++++++----- src/typec/utcd.h | 2 +- 6 files changed, 162 insertions(+), 75 deletions(-) (limited to 'src') diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c index 5fa6e3dbb..d77183357 100644 --- a/hw/bsp/stm32g4/family.c +++ b/hw/bsp/stm32g4/family.c @@ -145,13 +145,13 @@ void board_init(void) #if 1 // USB PD // Default CC1/CC2 is PB4/PB6 - /* PWR register access (for disabling dead battery feature) */ - LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); - LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC); + // Enable pwr for disabling dead battery feature in Power's CR3 + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_CRC_CLK_ENABLE(); __HAL_RCC_UCPD1_CLK_ENABLE(); - // Enable DMA clock + // Enable DMA for USB PD __HAL_RCC_DMAMUX1_CLK_ENABLE(); __HAL_RCC_DMA1_CLK_ENABLE(); #endif diff --git a/src/device/dcd.h b/src/device/dcd.h index f82b8633d..4e9cfd5d5 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -189,6 +189,7 @@ TU_ATTR_WEAK bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t l // Configure and enable an ISO endpoint according to descriptor TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc); + //--------------------------------------------------------------------+ // Event API (implemented by stack) //--------------------------------------------------------------------+ diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c index a898cda47..1dba54492 100644 --- a/src/portable/st/typec/typec_stm32.c +++ b/src/portable/st/typec/typec_stm32.c @@ -31,7 +31,7 @@ #if CFG_TUSB_MCU == OPT_MCU_STM32G4 #include "stm32g4xx.h" - #include "stm32g4xx_ll_dma.h" // for UCLP REQID + #include "stm32g4xx_ll_dma.h" // for UCPD REQID #else #error "Unsupported STM32 family" #endif @@ -62,9 +62,17 @@ enum { #define PHY_ORDERED_SET_SOP_PP_DEBUG (PHY_SYNC1 | (PHY_RST2<<5u) | (PHY_SYNC3<<10u) | (PHY_SYNC2<<15u)) // SOP'' Debug Ordered set coding -static uint8_t rx_buf[262] TU_ATTR_ALIGNED(4); -static uint8_t tx_buf[262] TU_ATTR_ALIGNED(4); -static uint32_t tx_index; +static uint8_t const* _rx_buf; + +static tusb_pd_header_t _good_crc = { + .msg_type = TUSB_PD_CTRL_GOOD_CRC, + .data_role = 0, // UFP + .specs_rev = TUSB_PD_REV20, + .power_role = 0, // Sink + .msg_id = 0, + .n_data_obj = 0, + .extended = 0 +}; // address of DMA channel rx, tx for each port #define CFG_TUC_STM32_DMA { { DMA1_Channel1_BASE, DMA1_Channel2_BASE } } @@ -73,10 +81,10 @@ static uint32_t tx_index; // DMA //--------------------------------------------------------------------+ -static const uint32_t dma_addr_arr[TUP_TYPEC_RHPORTS_NUM][2] = CFG_TUC_STM32_DMA; +static const uint32_t _dma_addr_arr[TUP_TYPEC_RHPORTS_NUM][2] = CFG_TUC_STM32_DMA; TU_ATTR_ALWAYS_INLINE static inline uint32_t dma_get_addr(uint8_t rhport, bool is_rx) { - return dma_addr_arr[rhport][is_rx ? 0 : 1]; + return _dma_addr_arr[rhport][is_rx ? 0 : 1]; } static void dma_init(uint8_t rhport, bool is_rx) { @@ -133,10 +141,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dma_stop(uint8_t rhport, bool is_rx) { dma_ch->CCR &= ~DMA_CCR_EN; } -TU_ATTR_ALWAYS_INLINE static inline void dma_rx_start(uint8_t rhport) { - dma_start(rhport, true, rx_buf, sizeof(rx_buf)); -} - TU_ATTR_ALWAYS_INLINE static inline void dma_tx_start(uint8_t rhport, void const* buf, uint16_t len) { UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP; UCPD1->TX_PAYSZ = len; @@ -147,7 +151,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dma_tx_start(uint8_t rhport, void const // //--------------------------------------------------------------------+ - bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) { (void) rhport; @@ -155,27 +158,30 @@ bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) { dma_init(rhport, true); dma_init(rhport, false); - // Initialization phase: CFG1 + // Initialization phase: CFG1, detect all SOPs UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) | (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos); UCPD1->CFG1 |= UCPD_CFG1_UCPDEN; // General programming sequence (with UCPD configured then enabled) if (port_type == TUSB_TYPEC_PORT_SNK) { - // Enable both CC Phy - UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1; + // Set analog mode enable both CC Phy + UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1); // Read Voltage State on CC1 & CC2 fore initial state - uint32_t vstate_cc[2]; - vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; - vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03; + uint32_t v_cc[2]; + v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; + v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03; - TU_LOG1("Initial VState CC1 = %u, CC2 = %u\r\n", vstate_cc[0], vstate_cc[1]); + TU_LOG1("Initial VState CC1 = %u, CC2 = %u\r\n", v_cc[0], v_cc[1]); // Enable CC1 & CC2 Interrupt UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE; } + // Disable dead battery in PWR's CR3 + PWR->CR3 |= PWR_CR3_UCPD_DBDIS; + return true; } @@ -192,9 +198,8 @@ void tcd_int_disable(uint8_t rhport) { } bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) { - (void) rhport; - (void) buffer; - (void) total_bytes; + _rx_buf = buffer; + dma_start(rhport, true, buffer, total_bytes); return true; } @@ -212,27 +217,28 @@ void tcd_int_handler(uint8_t rhport) { sr &= UCPD1->IMR; if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) { - uint32_t vstate_cc[2]; - vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; - vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03; + uint32_t v_cc[2]; + v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; + v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03; - TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]); + TU_LOG3("VState CC1 = %u, CC2 = %u\n", v_cc[0], v_cc[1]); uint32_t cr = UCPD1->CR; // TODO only support SNK for now, required highest voltage for now - // Enable PHY on correct CC and disable Rd on other CC - if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) { - TU_LOG1("Attach CC1\n"); - + // Enable PHY on active CC and disable Rd on other CC + // FIXME somehow CC2 is vstate is not correct, always 1 even not attached. + // on DPOW1 board, it is connected to PA10 (USBPD_DBCC2), we probably miss something. + if ((sr & UCPD_SR_TYPECEVT1) && (v_cc[0] == 3)) { + TU_LOG3("Attach CC1\n"); cr &= ~(UCPD_CR_PHYCCSEL | UCPD_CR_CCENABLE); cr |= UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_0; - } else if ((sr & UCPD_SR_TYPECEVT2) && (vstate_cc[1] == 3)) { - TU_LOG1("Attach CC2\n"); + } else if ((sr & UCPD_SR_TYPECEVT2) && (v_cc[1] == 3)) { + TU_LOG3("Attach CC2\n"); cr &= ~UCPD_CR_CCENABLE; cr |= (UCPD_CR_PHYCCSEL | UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_1); } else { - TU_LOG1("Detach\n"); + TU_LOG3("Detach\n"); cr &= ~UCPD_CR_PHYRXEN; cr |= UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1; } @@ -241,14 +247,15 @@ void tcd_int_handler(uint8_t rhport) { // Attached UCPD1->IMR |= IMR_ATTACHED; UCPD1->CFG1 |= UCPD_CFG1_RXDMAEN | UCPD_CFG1_TXDMAEN; - - dma_rx_start(rhport); }else { // Detached UCPD1->CFG1 &= ~(UCPD_CFG1_RXDMAEN | UCPD_CFG1_TXDMAEN); UCPD1->IMR &= ~IMR_ATTACHED; } + // notify stack + tcd_event_cc_changed(rhport, v_cc[0], v_cc[1], true); + UCPD1->CR = cr; // ack @@ -258,6 +265,7 @@ void tcd_int_handler(uint8_t rhport) { //------------- RX -------------// if (sr & UCPD_SR_RXORDDET) { // SOP: Start of Packet. + TU_LOG3("SOP\n"); // UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk; // ack @@ -266,48 +274,39 @@ void tcd_int_handler(uint8_t rhport) { // Received full message if (sr & UCPD_SR_RXMSGEND) { - + TU_LOG3("RX MSG END\n"); dma_stop(rhport, true); - // Skip if CRC failed - if (!(sr & UCPD_SR_RXERR)) { - uint32_t payload_size = UCPD1->RX_PAYSZ; - // TU_LOG1("RXMSGEND: payload_size = %u, rx count = %u\n", payload_size, pd_rx_count); - - tusb_pd_header_t const* rx_header = (tusb_pd_header_t const*) rx_buf; - (*(tusb_pd_header_t*) tx_buf) = (tusb_pd_header_t) { - .msg_type = TUSB_PD_CTRL_GOOD_CRC, - .data_role = 0, // UFP - .specs_rev = TUSB_PD_REV20, - .power_role = 0, // Sink - .msg_id = rx_header->msg_id, - .n_data_obj = 0, - .extended = 0 - }; + uint8_t result; + if (!(sr & UCPD_SR_RXERR)) { // response with good crc - dma_tx_start(rhport, tx_buf, 2); - + _good_crc.msg_id = ((tusb_pd_header_t const*) _rx_buf)->msg_id; + dma_tx_start(rhport, &_good_crc, 2); UCPD1->CR |= UCPD_CR_TXSEND; - // notify stack + result = XFER_RESULT_SUCCESS; + }else { + // CRC failed + result = XFER_RESULT_FAILED; } - // prepare next receive - dma_rx_start(rhport); + // notify stack + tcd_event_rx_complete(rhport, UCPD1->RX_PAYSZ, result, true); // ack UCPD1->ICR = UCPD_ICR_RXMSGENDCF; } if (sr & UCPD_SR_RXOVR) { - TU_LOG1("RXOVR\n"); + TU_LOG3("RXOVR\n"); // ack UCPD1->ICR = UCPD_ICR_RXOVRCF; } //------------- TX -------------// if (sr & UCPD_SR_TXMSGSENT) { + TU_LOG3("TX MSG SENT\n"); // all byte sent dma_stop(rhport, false); @@ -316,7 +315,7 @@ void tcd_int_handler(uint8_t rhport) { } if (sr & (UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND)) { - TU_LOG1("TX Error\n"); + TU_LOG3("TX Error\n"); dma_stop(rhport, false); UCPD1->ICR = UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND; } diff --git a/src/typec/tcd.h b/src/typec/tcd.h index e823bf8d7..41dceaa74 100644 --- a/src/typec/tcd.h +++ b/src/typec/tcd.h @@ -38,10 +38,28 @@ extern "C" { //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ + +enum { + TCD_EVENT_INVALID = 0, + TCD_EVENT_CC_CHANGED, + TCD_EVENT_RX_COMPLETE, +}; + + typedef struct { uint8_t rhport; uint8_t event_id; + union { + struct { + uint8_t cc_state[2]; + } cc_changed; + + struct { + uint16_t xferred_bytes; + uint8_t result; + } rx_complete; + }; } tcd_event_t;; @@ -68,4 +86,38 @@ void tcd_int_handler(uint8_t rhport); bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes); bool tcd_tx_start(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes); +//--------------------------------------------------------------------+ +// Event API (implemented by stack) +// Called by TCD to notify stack +//--------------------------------------------------------------------+ + +extern void tcd_event_handler(tcd_event_t const * event, bool in_isr); + +TU_ATTR_ALWAYS_INLINE static inline +void tcd_event_cc_changed(uint8_t rhport, uint8_t cc1, uint8_t cc2, bool in_isr) { + tcd_event_t event = { + .rhport = rhport, + .event_id = TCD_EVENT_CC_CHANGED, + .cc_changed = { + .cc_state = {cc1, cc2 } + } + }; + + tcd_event_handler(&event, in_isr); +} + +TU_ATTR_ALWAYS_INLINE static inline +void tcd_event_rx_complete(uint8_t rhport, uint16_t xferred_bytes, uint8_t result, bool in_isr) { + tcd_event_t event = { + .rhport = rhport, + .event_id = TCD_EVENT_RX_COMPLETE, + .rx_complete = { + .xferred_bytes = xferred_bytes, + .result = result + } + }; + + tcd_event_handler(&event, in_isr); +} + #endif diff --git a/src/typec/utcd.c b/src/typec/utcd.c index b5f9965fe..fb69b01e8 100644 --- a/src/typec/utcd.c +++ b/src/typec/utcd.c @@ -42,35 +42,38 @@ // Event queue // utcd_int_set() is used as mutex in OS NONE config void utcd_int_set(bool enabled); -OSAL_QUEUE_DEF(utcd_int_set, utcd_qdef, CFG_TUC_TASK_QUEUE_SZ, tcd_event_t); -tu_static osal_queue_t utcd_q; +OSAL_QUEUE_DEF(utcd_int_set, _utcd_qdef, CFG_TUC_TASK_QUEUE_SZ, tcd_event_t); +tu_static osal_queue_t _utcd_q; // if stack is initialized -static bool utcd_inited = false; +static bool _utcd_inited = false; // if port is initialized -static bool port_inited[TUP_TYPEC_RHPORTS_NUM]; +static bool _port_inited[TUP_TYPEC_RHPORTS_NUM]; + +// Max possible PD size is 262 bytes +static uint8_t _rx_buf[262] TU_ATTR_ALIGNED(4); //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ bool tuc_inited(uint8_t rhport) { - return utcd_inited && port_inited[rhport]; + return _utcd_inited && _port_inited[rhport]; } bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) { // Initialize stack - if (!utcd_inited) { - tu_memclr(port_inited, sizeof(port_inited)); + if (!_utcd_inited) { + tu_memclr(_port_inited, sizeof(_port_inited)); - utcd_q = osal_queue_create(&utcd_qdef); - TU_ASSERT(utcd_q != NULL); + _utcd_q = osal_queue_create(&_utcd_qdef); + TU_ASSERT(_utcd_q != NULL); - utcd_inited = true; + _utcd_inited = true; } // skip if port already initialized - if ( port_inited[rhport] ) { + if ( _port_inited[rhport] ) { return true; } @@ -79,10 +82,42 @@ bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) { TU_ASSERT(tcd_init(rhport, port_type)); tcd_int_enable(rhport); - port_inited[rhport] = true; + _port_inited[rhport] = true; return true; } +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +//bool parse_message(uint8_t const * data, uint16_t len, pd_msg_t * msg) { +// // TODO +// (void) data; +// (void) len; +// (void) msg; +// return false; +//} + +void tcd_event_handler(tcd_event_t const * event, bool in_isr) { + (void) in_isr; + switch(event->event_id) { + case TCD_EVENT_CC_CHANGED: + if (event->cc_changed.cc_state[0] || event->cc_changed.cc_state[1]) { + // Attach + tcd_rx_start(event->rhport, _rx_buf, sizeof(_rx_buf)); + }else { + // Detach + } + break; + + case TCD_EVENT_RX_COMPLETE: + // TODO process message here in ISR, move to thread later + + // start new rx + tcd_rx_start(event->rhport, _rx_buf, sizeof(_rx_buf)); + break; + } +} //--------------------------------------------------------------------+ // @@ -90,7 +125,7 @@ bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) { void utcd_int_set(bool enabled) { // Disable all controllers since they shared the same event queue for (uint8_t p = 0; p < TUP_TYPEC_RHPORTS_NUM; p++) { - if ( port_inited[p] ) { + if ( _port_inited[p] ) { if (enabled) { tcd_int_enable(p); }else { diff --git a/src/typec/utcd.h b/src/typec/utcd.h index 06a62ef23..75ff6f1db 100644 --- a/src/typec/utcd.h +++ b/src/typec/utcd.h @@ -38,7 +38,7 @@ extern "C" { //--------------------------------------------------------------------+ #ifndef CFG_TUC_TASK_QUEUE_SZ -#define CFG_TUC_TASK_QUEUE_SZ 16 +#define CFG_TUC_TASK_QUEUE_SZ 8 #endif -- cgit v1.3.1 From bb4fb0543bab21e68748b359ec7d59e74cac1445 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 9 Jun 2023 19:38:50 +0700 Subject: able to parse SOURCE_CAP message from dfp --- src/typec/utcd.c | 56 +++++++++++++++++++++++++++++++++++++++++++++------- src/typec/utcd.h | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 109 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/typec/utcd.c b/src/typec/utcd.c index fb69b01e8..abbe8b43e 100644 --- a/src/typec/utcd.c +++ b/src/typec/utcd.c @@ -90,13 +90,50 @@ bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) { // //--------------------------------------------------------------------+ -//bool parse_message(uint8_t const * data, uint16_t len, pd_msg_t * msg) { -// // TODO -// (void) data; -// (void) len; -// (void) msg; -// return false; -//} +bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) { + (void) rhport; + uint8_t const* p_end = buf + len; + tusb_pd_header_t const* header = (tusb_pd_header_t const*) buf; + uint8_t const * ptr = buf + sizeof(tusb_pd_header_t); + + if (header->n_data_obj == 0) { + // control message + } else { + // data message + switch (header->msg_type) { + case TUSB_PD_DATA_SOURCE_CAP: { + for(size_t i=0; in_data_obj; i++) { + TU_VERIFY(ptr < p_end); + uint32_t const pdo = tu_le32toh(tu_unaligned_read32(ptr)); + + switch ((pdo >> 30) & 0x03ul) { + case PD_PDO_TYPE_FIXED: { + pd_pdo_fixed_t const* fixed = (pd_pdo_fixed_t const*) &pdo; + TU_LOG3("[Fixed] %u mV %u mA\r\n", fixed->voltage_50mv*50, fixed->current_max_10ma*10); + break; + } + + case PD_PDO_TYPE_BATTERY: + break; + + case PD_PDO_TYPE_VARIABLE: + break; + + case PD_PDO_TYPE_APDO: + break; + } + + ptr += 4; + } + break; + } + + default: break; + } + } + + return true; +} void tcd_event_handler(tcd_event_t const * event, bool in_isr) { (void) in_isr; @@ -112,10 +149,15 @@ void tcd_event_handler(tcd_event_t const * event, bool in_isr) { case TCD_EVENT_RX_COMPLETE: // TODO process message here in ISR, move to thread later + if (event->rx_complete.result == XFER_RESULT_SUCCESS) { + parse_message(event->rhport, _rx_buf, event->rx_complete.xferred_bytes); + } // start new rx tcd_rx_start(event->rhport, _rx_buf, sizeof(_rx_buf)); break; + + default: break; } } diff --git a/src/typec/utcd.h b/src/typec/utcd.h index 75ff6f1db..dbc909592 100644 --- a/src/typec/utcd.h +++ b/src/typec/utcd.h @@ -41,6 +41,66 @@ extern "C" { #define CFG_TUC_TASK_QUEUE_SZ 8 #endif +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +// All table references are from USBPD Specification rev3.1 version 1.8 +enum { + PD_PDO_TYPE_FIXED = 0, // Vmin = Vmax + PD_PDO_TYPE_BATTERY, + PD_PDO_TYPE_VARIABLE, // non-battery + PD_PDO_TYPE_APDO, // Augmented Power Data Object +}; + +// Fixed Power Data Object (PDO) table 6-9 +typedef struct TU_ATTR_PACKED { + uint32_t current_max_10ma : 10; // [9..0] Max current in 10mA unit + uint32_t voltage_50mv : 10; // [19..10] Voltage in 50mV unit + uint32_t current_peak : 2; // [21..20] Peak current + uint32_t reserved : 1; // [22] Reserved + uint32_t epr_mode_capable : 1; // [23] epr_mode_capable + uint32_t unchunked_ext_msg_support : 1; // [24] UnChunked Extended Message Supported + uint32_t dual_role_data : 1; // [25] Dual Role Data + uint32_t usb_comm_capable : 1; // [26] USB Communications Capable + uint32_t unconstrained_power : 1; // [27] Unconstrained Power + uint32_t usb_suspend_supported : 1; // [28] USB Suspend Supported + uint32_t dual_role_power : 1; // [29] Dual Role Power + uint32_t type : 2; // [30] Fixed Supply type = PD_PDO_TYPE_FIXED +} pd_pdo_fixed_t; +TU_VERIFY_STATIC(sizeof(pd_pdo_fixed_t) == 4, "Invalid size"); + +// Battery Power Data Object (PDO) table 6-12 +typedef struct TU_ATTR_PACKED { + uint32_t power_max_250mw : 10; // [9..0] Max allowable power in 250mW unit + uint32_t voltage_min_50mv : 10; // [19..10] Minimum voltage in 50mV unit + uint32_t voltage_max_50mv : 10; // [29..20] Maximum voltage in 50mV unit + uint32_t type : 2; // [31..30] Battery type = PD_PDO_TYPE_BATTERY +} pd_pdo_battery_t; +TU_VERIFY_STATIC(sizeof(pd_pdo_battery_t) == 4, "Invalid size"); + +// Variable Power Data Object (PDO) table 6-11 +typedef struct TU_ATTR_PACKED { + uint32_t current_max_10ma : 10; // [9..0] Max current in 10mA unit + uint32_t voltage_min_50mv : 10; // [19..10] Minimum voltage in 50mV unit + uint32_t voltage_max_50mv : 10; // [29..20] Maximum voltage in 50mV unit + uint32_t type : 2; // [31..30] Variable Supply type = PD_PDO_TYPE_VARIABLE +} pd_pdo_variable_t; +TU_VERIFY_STATIC(sizeof(pd_pdo_variable_t) == 4, "Invalid size"); + +// Augmented Power Data Object (PDO) table 6-13 +typedef struct TU_ATTR_PACKED { + uint32_t current_max_50ma : 7; // [6..0] Max current in 50mA unit + uint32_t reserved1 : 1; // [7] Reserved + uint32_t voltage_min_100mv : 8; // [15..8] Minimum Voltage in 100mV unit + uint32_t reserved2 : 1; // [16] Reserved + uint32_t voltage_max_100mv : 8; // [24..17] Maximum Voltage in 100mV unit + uint32_t reserved3 : 2; // [26..25] Reserved + uint32_t pps_power_limited : 1; // [27] PPS Power Limited + uint32_t spr_programmable : 2; // [29..28] SPR Programmable Power Supply + uint32_t type : 2; // [31..30] Augmented Power Data Object = PD_PDO_TYPE_APDO +} pd_pdo_apdo_t; +TU_VERIFY_STATIC(sizeof(pd_pdo_apdo_t) == 4, "Invalid size"); //--------------------------------------------------------------------+ // Application API -- cgit v1.3.1 From debde4cc97cb7c6c13d62d0e3bbe195c80bfec9f Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 12 Jun 2023 12:14:55 +0700 Subject: response with request safe5v, get passed PS_READY --- src/common/tusb_types.h | 10 +++++ src/portable/st/typec/typec_stm32.c | 78 +++++++++++++++++++++++++++++-------- src/typec/tcd.h | 17 +++++++- src/typec/utcd.c | 59 ++++++++++++++++++++++++++++ src/typec/utcd.h | 34 +++++++++++++++- 5 files changed, 180 insertions(+), 18 deletions(-) (limited to 'src') diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index c92320e5c..cad633ee4 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -562,6 +562,16 @@ enum { TUSB_PD_REV30 = 0x2, }; +enum { + TUSB_PD_DATA_ROLE_UFP = 0x0, + TUSB_PD_DATA_ROLE_DFP = 0x1, +}; + +enum { + TUSB_PD_POWER_ROLE_SINK = 0x0, + TUSB_PD_POWER_ROLE_SOURCE = 0x1, +}; + typedef struct TU_ATTR_PACKED { uint16_t msg_type : 5; // [0:4] uint16_t data_role : 1; // [5] SOP only: 0 UFP, 1 DFP diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c index 1dba54492..9b3b21707 100644 --- a/src/portable/st/typec/typec_stm32.c +++ b/src/portable/st/typec/typec_stm32.c @@ -63,6 +63,9 @@ enum { static uint8_t const* _rx_buf; +static uint8_t const* _tx_pending_buf; +static uint16_t _tx_pending_bytes; +static uint16_t _tx_xferring_bytes; static tusb_pd_header_t _good_crc = { .msg_type = TUSB_PD_CTRL_GOOD_CRC, @@ -141,10 +144,21 @@ TU_ATTR_ALWAYS_INLINE static inline void dma_stop(uint8_t rhport, bool is_rx) { dma_ch->CCR &= ~DMA_CCR_EN; } +TU_ATTR_ALWAYS_INLINE static inline bool dma_enabled(uint8_t rhport, bool is_rx) { + DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_get_addr(rhport, is_rx); + return dma_ch->CCR & DMA_CCR_EN; +} + + TU_ATTR_ALWAYS_INLINE static inline void dma_tx_start(uint8_t rhport, void const* buf, uint16_t len) { UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP; UCPD1->TX_PAYSZ = len; dma_start(rhport, false, buf, len); + UCPD1->CR |= UCPD_CR_TXSEND; +} + +TU_ATTR_ALWAYS_INLINE static inline void dma_tx_stop(uint8_t rhport) { + dma_stop(rhport, false); } //--------------------------------------------------------------------+ @@ -203,11 +217,23 @@ bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) { return true; } -bool tcd_tx_start(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes) { +bool tcd_msg_send(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes) { (void) rhport; - (void) buffer; - (void) total_bytes; - return false; + + if (dma_enabled(rhport, false)) { + // DMA is busy, probably sending GoodCRC, save as pending TX + _tx_pending_buf = buffer; + _tx_pending_bytes = total_bytes; + }else { + // DMA is free, start sending + _tx_pending_buf = NULL; + _tx_pending_bytes = 0; + + _tx_xferring_bytes = total_bytes; + dma_tx_start(rhport, buffer, total_bytes); + } + + return true; } void tcd_int_handler(uint8_t rhport) { @@ -275,6 +301,8 @@ void tcd_int_handler(uint8_t rhport) { // Received full message if (sr & UCPD_SR_RXMSGEND) { TU_LOG3("RX MSG END\n"); + + // stop TX dma_stop(rhport, true); uint8_t result; @@ -283,7 +311,6 @@ void tcd_int_handler(uint8_t rhport) { // response with good crc _good_crc.msg_id = ((tusb_pd_header_t const*) _rx_buf)->msg_id; dma_tx_start(rhport, &_good_crc, 2); - UCPD1->CR |= UCPD_CR_TXSEND; result = XFER_RESULT_SUCCESS; }else { @@ -305,19 +332,38 @@ void tcd_int_handler(uint8_t rhport) { } //------------- TX -------------// - if (sr & UCPD_SR_TXMSGSENT) { - TU_LOG3("TX MSG SENT\n"); - // all byte sent - dma_stop(rhport, false); + // All tx events: complete and error + if (sr & (UCPD_SR_TXMSGSENT | (UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND))) { + // force TX stop + dma_tx_stop(rhport); - // ack - UCPD1->ICR = UCPD_ICR_TXMSGSENTCF; - } + uint16_t const xferred_bytes = _tx_xferring_bytes - UCPD1->TX_PAYSZ; + uint8_t result; - if (sr & (UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND)) { - TU_LOG3("TX Error\n"); - dma_stop(rhport, false); - UCPD1->ICR = UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND; + if ( sr & UCPD_SR_TXMSGSENT ) { + TU_LOG3("TX MSG SENT\n"); + result = XFER_RESULT_SUCCESS; + // ack + UCPD1->ICR = UCPD_ICR_TXMSGSENTCF; + }else { + TU_LOG3("TX Error\n"); + result = XFER_RESULT_FAILED; + // ack + UCPD1->ICR = UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND; + } + + // start pending TX if any + if (_tx_pending_buf && _tx_pending_bytes ) { + // Start the pending TX + dma_tx_start(rhport, _tx_pending_buf, _tx_pending_bytes); + + // clear pending + _tx_pending_buf = NULL; + _tx_pending_bytes = 0; + } + + // notify stack + tcd_event_tx_complete(rhport, xferred_bytes, result, true); } } diff --git a/src/typec/tcd.h b/src/typec/tcd.h index 41dceaa74..b131d6ba9 100644 --- a/src/typec/tcd.h +++ b/src/typec/tcd.h @@ -43,6 +43,7 @@ enum { TCD_EVENT_INVALID = 0, TCD_EVENT_CC_CHANGED, TCD_EVENT_RX_COMPLETE, + TCD_EVENT_TX_COMPLETE, }; @@ -84,7 +85,7 @@ void tcd_int_handler(uint8_t rhport); //--------------------------------------------------------------------+ bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes); -bool tcd_tx_start(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes); +bool tcd_msg_send(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes); //--------------------------------------------------------------------+ // Event API (implemented by stack) @@ -120,4 +121,18 @@ void tcd_event_rx_complete(uint8_t rhport, uint16_t xferred_bytes, uint8_t resul tcd_event_handler(&event, in_isr); } +TU_ATTR_ALWAYS_INLINE static inline +void tcd_event_tx_complete(uint8_t rhport, uint16_t xferred_bytes, uint8_t result, bool in_isr) { + tcd_event_t event = { + .rhport = rhport, + .event_id = TCD_EVENT_TX_COMPLETE, + .rx_complete = { + .xferred_bytes = xferred_bytes, + .result = result + } + }; + + tcd_event_handler(&event, in_isr); +} + #endif diff --git a/src/typec/utcd.c b/src/typec/utcd.c index abbe8b43e..09031e5c9 100644 --- a/src/typec/utcd.c +++ b/src/typec/utcd.c @@ -53,6 +53,7 @@ static bool _port_inited[TUP_TYPEC_RHPORTS_NUM]; // Max possible PD size is 262 bytes static uint8_t _rx_buf[262] TU_ATTR_ALIGNED(4); +static uint8_t _tx_buf[100] TU_ATTR_ALIGNED(4); //--------------------------------------------------------------------+ // @@ -90,6 +91,19 @@ bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) { // //--------------------------------------------------------------------+ +bool utcd_msg_send(uint8_t rhport, tusb_pd_header_t const* header, void const* data) { + // copy header + memcpy(_tx_buf, header, sizeof(tusb_pd_header_t)); + + // copy data objcet if available + uint16_t const n_data_obj = header->n_data_obj; + if (n_data_obj > 0) { + memcpy(_tx_buf + sizeof(tusb_pd_header_t), data, n_data_obj * 4); + } + + return tcd_msg_send(rhport, _tx_buf, sizeof(tusb_pd_header_t) + n_data_obj * 4); +} + bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) { (void) rhport; uint8_t const* p_end = buf + len; @@ -98,10 +112,28 @@ bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) { if (header->n_data_obj == 0) { // control message + switch (header->msg_type) { + case TUSB_PD_CTRL_GOOD_CRC: + break; + + case TUSB_PD_CTRL_ACCEPT: + break; + + case TUSB_PD_CTRL_REJECT: + break; + + case TUSB_PD_CTRL_PS_RDY: + break; + + default: break; + } } else { // data message switch (header->msg_type) { case TUSB_PD_DATA_SOURCE_CAP: { + // Examine source capability and select a suitable PDO (starting from 1 with safe5v) + uint8_t obj_pos = 1; + for(size_t i=0; in_data_obj; i++) { TU_VERIFY(ptr < p_end); uint32_t const pdo = tu_le32toh(tu_unaligned_read32(ptr)); @@ -125,6 +157,33 @@ bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) { ptr += 4; } + + // Send request with selected PDO position as response to Source Cap + pd_rdo_fixed_variable_t rdo = { + .current_extremum_10ma = 50, // max 500mA + .current_operate_10ma = 30, // 300mA + .reserved = 0, + .epr_mode_capable = 0, + .unchunked_ext_msg_support = 0, + .no_usb_suspend = 0, + .usb_comm_capable = 1, + .capability_mismatch = 0, + .give_back_flag = 0, // exteremum is max + .object_position = obj_pos, + }; + + tusb_pd_header_t const req_header = { + .msg_type = TUSB_PD_DATA_REQUEST, + .data_role = TUSB_PD_DATA_ROLE_UFP, + .specs_rev = TUSB_PD_REV20, + .power_role = TUSB_PD_POWER_ROLE_SINK, + .msg_id = 0, + .n_data_obj = 1, + .extended = 0, + }; + + utcd_msg_send(rhport, &req_header, &rdo); + break; } diff --git a/src/typec/utcd.h b/src/typec/utcd.h index dbc909592..bb1523253 100644 --- a/src/typec/utcd.h +++ b/src/typec/utcd.h @@ -42,7 +42,7 @@ extern "C" { #endif //--------------------------------------------------------------------+ -// +// Source Capability //--------------------------------------------------------------------+ // All table references are from USBPD Specification rev3.1 version 1.8 @@ -102,6 +102,38 @@ typedef struct TU_ATTR_PACKED { } pd_pdo_apdo_t; TU_VERIFY_STATIC(sizeof(pd_pdo_apdo_t) == 4, "Invalid size"); +//--------------------------------------------------------------------+ +// Request +//--------------------------------------------------------------------+ + +typedef struct TU_ATTR_PACKED { + uint32_t current_extremum_10ma : 10; // [9..0] Max (give back = 0) or Min (give back = 1) current in 10mA unit + uint32_t current_operate_10ma : 10; // [19..10] Operating current in 10mA unit + uint32_t reserved : 2; // [21..20] Reserved + uint32_t epr_mode_capable : 1; // [22] EPR mode capable + uint32_t unchunked_ext_msg_support : 1; // [23] UnChunked Extended Message Supported + uint32_t no_usb_suspend : 1; // [24] No USB Suspend + uint32_t usb_comm_capable : 1; // [25] USB Communications Capable + uint32_t capability_mismatch : 1; // [26] Capability Mismatch + uint32_t give_back_flag : 1; // [27] GiveBack Flag: 0 = Max, 1 = Min + uint32_t object_position : 4; // [31..28] Object Position +} pd_rdo_fixed_variable_t; +TU_VERIFY_STATIC(sizeof(pd_rdo_fixed_variable_t) == 4, "Invalid size"); + +typedef struct TU_ATTR_PACKED { + uint32_t power_extremum_250mw : 10; // [9..0] Max (give back = 0) or Min (give back = 1) operating power in 250mW unit + uint32_t power_operate_250mw : 10; // [19..10] Operating power in 250mW unit + uint32_t reserved : 2; // [21..20] Reserved + uint32_t epr_mode_capable : 1; // [22] EPR mode capable + uint32_t unchunked_ext_msg_support : 1; // [23] UnChunked Extended Message Supported + uint32_t no_usb_suspend : 1; // [24] No USB Suspend + uint32_t usb_comm_capable : 1; // [25] USB Communications Capable + uint32_t capability_mismatch : 1; // [26] Capability Mismatch + uint32_t give_back_flag : 1; // [27] GiveBack Flag: 0 = Max, 1 = Min + uint32_t object_position : 4; // [31..28] Object Position +} pd_rdo_battery_t; +TU_VERIFY_STATIC(sizeof(pd_rdo_battery_t) == 4, "Invalid size"); + //--------------------------------------------------------------------+ // Application API //--------------------------------------------------------------------+ -- cgit v1.3.1 From c28503060c0c3cb09d8e2ce63d1b0009affbdf72 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 12 Jun 2023 14:57:50 +0700 Subject: ad pd_types.h --- src/common/tusb_types.h | 96 +-------------- src/portable/st/typec/typec_stm32.c | 13 +- src/typec/pd_types.h | 237 ++++++++++++++++++++++++++++++++++++ src/typec/tcd.h | 10 +- src/typec/utcd.c | 38 +++--- src/typec/utcd.h | 101 ++------------- 6 files changed, 278 insertions(+), 217 deletions(-) create mode 100644 src/typec/pd_types.h (limited to 'src') diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index cad633ee4..fab680989 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -480,6 +480,7 @@ typedef struct TU_ATTR_PACKED //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ + typedef struct TU_ATTR_PACKED{ union { struct TU_ATTR_PACKED { @@ -499,101 +500,6 @@ typedef struct TU_ATTR_PACKED{ TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct"); -//--------------------------------------------------------------------+ -// TYPE-C -//--------------------------------------------------------------------+ - -typedef enum { - TUSB_TYPEC_PORT_SRC, - TUSB_TYPEC_PORT_SNK, - TUSB_TYPEC_PORT_DRP -} tusb_typec_port_type_t; - -typedef enum { - TUSB_PD_CTRL_RESERVED = 0, // 0b00000: 0 - TUSB_PD_CTRL_GOOD_CRC, // 0b00001: 1 - TUSB_PD_CTRL_GO_TO_MIN, // 0b00010: 2 - TUSB_PD_CTRL_ACCEPT, // 0b00011: 3 - TUSB_PD_CTRL_REJECT, // 0b00100: 4 - TUSB_PD_CTRL_PING, // 0b00101: 5 - TUSB_PD_CTRL_PS_RDY, // 0b00110: 6 - TUSB_PD_CTRL_GET_SOURCE_CAP, // 0b00111: 7 - TUSB_PD_CTRL_GET_SINK_CAP, // 0b01000: 8 - TUSB_PD_CTRL_DR_SWAP, // 0b01001: 9 - TUSB_PD_CTRL_PR_SWAP, // 0b01010: 10 - TUSB_PD_CTRL_VCONN_SWAP, // 0b01011: 11 - TUSB_PD_CTRL_WAIT, // 0b01100: 12 - TUSB_PD_CTRL_SOFT_RESET, // 0b01101: 13 - TUSB_PD_CTRL_DATA_RESET, // 0b01110: 14 - TUSB_PD_CTRL_DATA_RESET_COMPLETE, // 0b01111: 15 - TUSB_PD_CTRL_NOT_SUPPORTED, // 0b10000: 16 - TUSB_PD_CTRL_GET_SOURCE_CAP_EXTENDED, // 0b10001: 17 - TUSB_PD_CTRL_GET_STATUS, // 0b10010: 18 - TUSB_PD_CTRL_FR_SWAP, // 0b10011: 19 - TUSB_PD_CTRL_GET_PPS_STATUS, // 0b10100: 20 - TUSB_PD_CTRL_GET_COUNTRY_CODES, // 0b10101: 21 - TUSB_PD_CTRL_GET_SINK_CAP_EXTENDED, // 0b10110: 22 - TUSB_PD_CTRL_GET_SOURCE_INFO, // 0b10111: 23 - TUSB_PD_CTRL_REVISION, // 0b11000: 24 -} tusb_pd_ctrl_type_t; - -typedef enum { - TUSB_PD_DATA_RESERVED = 0, // 0b00000: 0 - TUSB_PD_DATA_SOURCE_CAP, // 0b00001: 1 - TUSB_PD_DATA_REQUEST, // 0b00010: 2 - TUSB_PD_DATA_BIST, // 0b00011: 3 - TUSB_PD_DATA_SINK_CAP, // 0b00100: 4 - TUSB_PD_DATA_BATTERY_STATUS, // 0b00101: 5 - TUSB_PD_DATA_ALERT, // 0b00110: 6 - TUSB_PD_DATA_GET_COUNTRY_INFO, // 0b00111: 7 - TUSB_PD_DATA_ENTER_USB, // 0b01000: 8 - TUSB_PD_DATA_EPR_REQUEST, // 0b01001: 9 - TUSB_PD_DATA_EPR_MODE, // 0b01010: 10 - TUSB_PD_DATA_SRC_INFO, // 0b01011: 11 - TUSB_PD_DATA_REVISION, // 0b01100: 12 - TUSB_PD_DATA_RESERVED_13, // 0b01101: 13 - TUSB_PD_DATA_RESERVED_14, // 0b01110: 14 - TUSB_PD_DATA_VENDOR_DEFINED, // 0b01111: 15 -} tusb_pd_data_type_t; - -enum { - TUSB_PD_REV10 = 0x0, - TUSB_PD_REV20 = 0x1, - TUSB_PD_REV30 = 0x2, -}; - -enum { - TUSB_PD_DATA_ROLE_UFP = 0x0, - TUSB_PD_DATA_ROLE_DFP = 0x1, -}; - -enum { - TUSB_PD_POWER_ROLE_SINK = 0x0, - TUSB_PD_POWER_ROLE_SOURCE = 0x1, -}; - -typedef struct TU_ATTR_PACKED { - uint16_t msg_type : 5; // [0:4] - uint16_t data_role : 1; // [5] SOP only: 0 UFP, 1 DFP - uint16_t specs_rev : 2; // [6:7] - uint16_t power_role : 1; // [8] SOP only: 0 Sink, 1 Source - uint16_t msg_id : 3; // [9:11] - uint16_t n_data_obj : 3; // [12:14] - uint16_t extended : 1; // [15] -} tusb_pd_header_t; - -TU_VERIFY_STATIC( sizeof(tusb_pd_header_t) == 2, "size is not correct"); - -typedef struct TU_ATTR_PACKED { - uint16_t data_size : 9; // [0:8] - uint16_t reserved : 1; // [9] - uint16_t request_chunk : 1; // [10] - uint16_t chunk_number : 4; // [11:14] - uint16_t chunked : 1; // [15] -} tusb_pd_header_extended_t; - -TU_VERIFY_STATIC( sizeof(tusb_pd_header_extended_t) == 2, "size is not correct"); - TU_ATTR_PACKED_END // End of all packed definitions TU_ATTR_BIT_FIELD_ORDER_END diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c index 9b3b21707..b09dc5bae 100644 --- a/src/portable/st/typec/typec_stm32.c +++ b/src/portable/st/typec/typec_stm32.c @@ -67,10 +67,10 @@ static uint8_t const* _tx_pending_buf; static uint16_t _tx_pending_bytes; static uint16_t _tx_xferring_bytes; -static tusb_pd_header_t _good_crc = { - .msg_type = TUSB_PD_CTRL_GOOD_CRC, +static pd_header_t _good_crc = { + .msg_type = PD_CTRL_GOOD_CRC, .data_role = 0, // UFP - .specs_rev = TUSB_PD_REV20, + .specs_rev = PD_REV_20, .power_role = 0, // Sink .msg_id = 0, .n_data_obj = 0, @@ -149,7 +149,6 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_enabled(uint8_t rhport, bool is_rx) return dma_ch->CCR & DMA_CCR_EN; } - TU_ATTR_ALWAYS_INLINE static inline void dma_tx_start(uint8_t rhport, void const* buf, uint16_t len) { UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP; UCPD1->TX_PAYSZ = len; @@ -165,7 +164,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dma_tx_stop(uint8_t rhport) { // //--------------------------------------------------------------------+ -bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) { +bool tcd_init(uint8_t rhport, uint32_t port_type) { (void) rhport; // Init DMA for RX, TX @@ -211,7 +210,7 @@ void tcd_int_disable(uint8_t rhport) { NVIC_DisableIRQ(UCPD1_IRQn); } -bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) { +bool tcd_msg_receive(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) { _rx_buf = buffer; dma_start(rhport, true, buffer, total_bytes); return true; @@ -309,7 +308,7 @@ void tcd_int_handler(uint8_t rhport) { if (!(sr & UCPD_SR_RXERR)) { // response with good crc - _good_crc.msg_id = ((tusb_pd_header_t const*) _rx_buf)->msg_id; + _good_crc.msg_id = ((pd_header_t const*) _rx_buf)->msg_id; dma_tx_start(rhport, &_good_crc, 2); result = XFER_RESULT_SUCCESS; diff --git a/src/typec/pd_types.h b/src/typec/pd_types.h new file mode 100644 index 000000000..1b2968f65 --- /dev/null +++ b/src/typec/pd_types.h @@ -0,0 +1,237 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_PD_TYPES_H_ +#define _TUSB_PD_TYPES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "common/tusb_compiler.h" + +// Start of all packed definitions for compiler without per-type packed +TU_ATTR_PACKED_BEGIN +TU_ATTR_BIT_FIELD_ORDER_BEGIN + +//--------------------------------------------------------------------+ +// TYPE-C +//--------------------------------------------------------------------+ + +typedef enum { + TUSB_TYPEC_PORT_SRC, + TUSB_TYPEC_PORT_SNK, + TUSB_TYPEC_PORT_DRP +} tusb_typec_port_type_t; + +enum { + PD_CTRL_RESERVED = 0, // 0b00000: 0 + PD_CTRL_GOOD_CRC, // 0b00001: 1 + PD_CTRL_GO_TO_MIN, // 0b00010: 2 + PD_CTRL_ACCEPT, // 0b00011: 3 + PD_CTRL_REJECT, // 0b00100: 4 + PD_CTRL_PING, // 0b00101: 5 + PD_CTRL_PS_READY, // 0b00110: 6 + PD_CTRL_GET_SOURCE_CAP, // 0b00111: 7 + PD_CTRL_GET_SINK_CAP, // 0b01000: 8 + PD_CTRL_DR_SWAP, // 0b01001: 9 + PD_CTRL_PR_SWAP, // 0b01010: 10 + PD_CTRL_VCONN_SWAP, // 0b01011: 11 + PD_CTRL_WAIT, // 0b01100: 12 + PD_CTRL_SOFT_RESET, // 0b01101: 13 + PD_CTRL_DATA_RESET, // 0b01110: 14 + PD_CTRL_DATA_RESET_COMPLETE, // 0b01111: 15 + PD_CTRL_NOT_SUPPORTED, // 0b10000: 16 + PD_CTRL_GET_SOURCE_CAP_EXTENDED, // 0b10001: 17 + PD_CTRL_GET_STATUS, // 0b10010: 18 + PD_CTRL_FR_SWAP, // 0b10011: 19 + PD_CTRL_GET_PPS_STATUS, // 0b10100: 20 + PD_CTRL_GET_COUNTRY_CODES, // 0b10101: 21 + PD_CTRL_GET_SINK_CAP_EXTENDED, // 0b10110: 22 + PD_CTRL_GET_SOURCE_INFO, // 0b10111: 23 + PD_CTRL_REVISION, // 0b11000: 24 +}; + +enum { + PD_DATA_RESERVED = 0, // 0b00000: 0 + PD_DATA_SOURCE_CAP, // 0b00001: 1 + PD_DATA_REQUEST, // 0b00010: 2 + PD_DATA_BIST, // 0b00011: 3 + PD_DATA_SINK_CAP, // 0b00100: 4 + PD_DATA_BATTERY_STATUS, // 0b00101: 5 + PD_DATA_ALERT, // 0b00110: 6 + PD_DATA_GET_COUNTRY_INFO, // 0b00111: 7 + PD_DATA_ENTER_USB, // 0b01000: 8 + PD_DATA_EPR_REQUEST, // 0b01001: 9 + PD_DATA_EPR_MODE, // 0b01010: 10 + PD_DATA_SRC_INFO, // 0b01011: 11 + PD_DATA_REVISION, // 0b01100: 12 + PD_DATA_RESERVED_13, // 0b01101: 13 + PD_DATA_RESERVED_14, // 0b01110: 14 + PD_DATA_VENDOR_DEFINED, // 0b01111: 15 +}; + +enum { + PD_REV_10 = 0x0, + PD_REV_20 = 0x1, + PD_REV_30 = 0x2, +}; + +enum { + PD_DATA_ROLE_UFP = 0x0, + PD_DATA_ROLE_DFP = 0x1, +}; + +enum { + PD_POWER_ROLE_SINK = 0x0, + PD_POWER_ROLE_SOURCE = 0x1, +}; + +typedef struct TU_ATTR_PACKED { + uint16_t msg_type : 5; // [0:4] + uint16_t data_role : 1; // [5] SOP only: 0 UFP, 1 DFP + uint16_t specs_rev : 2; // [6:7] + uint16_t power_role : 1; // [8] SOP only: 0 Sink, 1 Source + uint16_t msg_id : 3; // [9:11] + uint16_t n_data_obj : 3; // [12:14] + uint16_t extended : 1; // [15] +} pd_header_t; +TU_VERIFY_STATIC(sizeof(pd_header_t) == 2, "size is not correct"); + +typedef struct TU_ATTR_PACKED { + uint16_t data_size : 9; // [0:8] + uint16_t reserved : 1; // [9] + uint16_t request_chunk : 1; // [10] + uint16_t chunk_number : 4; // [11:14] + uint16_t chunked : 1; // [15] +} pd_header_extended_t; +TU_VERIFY_STATIC(sizeof(pd_header_extended_t) == 2, "size is not correct"); + +//--------------------------------------------------------------------+ +// Source Capability +//--------------------------------------------------------------------+ + +// All table references are from USBPD Specification rev3.1 version 1.8 +enum { + PD_PDO_TYPE_FIXED = 0, // Vmin = Vmax + PD_PDO_TYPE_BATTERY, + PD_PDO_TYPE_VARIABLE, // non-battery + PD_PDO_TYPE_APDO, // Augmented Power Data Object +}; + +// Fixed Power Data Object (PDO) table 6-9 +typedef struct TU_ATTR_PACKED { + uint32_t current_max_10ma : 10; // [9..0] Max current in 10mA unit + uint32_t voltage_50mv : 10; // [19..10] Voltage in 50mV unit + uint32_t current_peak : 2; // [21..20] Peak current + uint32_t reserved : 1; // [22] Reserved + uint32_t epr_mode_capable : 1; // [23] epr_mode_capable + uint32_t unchunked_ext_msg_support : 1; // [24] UnChunked Extended Message Supported + uint32_t dual_role_data : 1; // [25] Dual Role Data + uint32_t usb_comm_capable : 1; // [26] USB Communications Capable + uint32_t unconstrained_power : 1; // [27] Unconstrained Power + uint32_t usb_suspend_supported : 1; // [28] USB Suspend Supported + uint32_t dual_role_power : 1; // [29] Dual Role Power + uint32_t type : 2; // [30] Fixed Supply type = PD_PDO_TYPE_FIXED +} pd_pdo_fixed_t; +TU_VERIFY_STATIC(sizeof(pd_pdo_fixed_t) == 4, "Invalid size"); + +// Battery Power Data Object (PDO) table 6-12 +typedef struct TU_ATTR_PACKED { + uint32_t power_max_250mw : 10; // [9..0] Max allowable power in 250mW unit + uint32_t voltage_min_50mv : 10; // [19..10] Minimum voltage in 50mV unit + uint32_t voltage_max_50mv : 10; // [29..20] Maximum voltage in 50mV unit + uint32_t type : 2; // [31..30] Battery type = PD_PDO_TYPE_BATTERY +} pd_pdo_battery_t; +TU_VERIFY_STATIC(sizeof(pd_pdo_battery_t) == 4, "Invalid size"); + +// Variable Power Data Object (PDO) table 6-11 +typedef struct TU_ATTR_PACKED { + uint32_t current_max_10ma : 10; // [9..0] Max current in 10mA unit + uint32_t voltage_min_50mv : 10; // [19..10] Minimum voltage in 50mV unit + uint32_t voltage_max_50mv : 10; // [29..20] Maximum voltage in 50mV unit + uint32_t type : 2; // [31..30] Variable Supply type = PD_PDO_TYPE_VARIABLE +} pd_pdo_variable_t; +TU_VERIFY_STATIC(sizeof(pd_pdo_variable_t) == 4, "Invalid size"); + +// Augmented Power Data Object (PDO) table 6-13 +typedef struct TU_ATTR_PACKED { + uint32_t current_max_50ma : 7; // [6..0] Max current in 50mA unit + uint32_t reserved1 : 1; // [7] Reserved + uint32_t voltage_min_100mv : 8; // [15..8] Minimum Voltage in 100mV unit + uint32_t reserved2 : 1; // [16] Reserved + uint32_t voltage_max_100mv : 8; // [24..17] Maximum Voltage in 100mV unit + uint32_t reserved3 : 2; // [26..25] Reserved + uint32_t pps_power_limited : 1; // [27] PPS Power Limited + uint32_t spr_programmable : 2; // [29..28] SPR Programmable Power Supply + uint32_t type : 2; // [31..30] Augmented Power Data Object = PD_PDO_TYPE_APDO +} pd_pdo_apdo_t; +TU_VERIFY_STATIC(sizeof(pd_pdo_apdo_t) == 4, "Invalid size"); + +//--------------------------------------------------------------------+ +// Request +//--------------------------------------------------------------------+ + +typedef struct TU_ATTR_PACKED { + uint32_t current_extremum_10ma : 10; // [9..0] Max (give back = 0) or Min (give back = 1) current in 10mA unit + uint32_t current_operate_10ma : 10; // [19..10] Operating current in 10mA unit + uint32_t reserved : 2; // [21..20] Reserved + uint32_t epr_mode_capable : 1; // [22] EPR mode capable + uint32_t unchunked_ext_msg_support : 1; // [23] UnChunked Extended Message Supported + uint32_t no_usb_suspend : 1; // [24] No USB Suspend + uint32_t usb_comm_capable : 1; // [25] USB Communications Capable + uint32_t capability_mismatch : 1; // [26] Capability Mismatch + uint32_t give_back_flag : 1; // [27] GiveBack Flag: 0 = Max, 1 = Min + uint32_t object_position : 4; // [31..28] Object Position +} pd_rdo_fixed_variable_t; +TU_VERIFY_STATIC(sizeof(pd_rdo_fixed_variable_t) == 4, "Invalid size"); + +typedef struct TU_ATTR_PACKED { + uint32_t power_extremum_250mw : 10; // [9..0] Max (give back = 0) or Min (give back = 1) operating power in 250mW unit + uint32_t power_operate_250mw : 10; // [19..10] Operating power in 250mW unit + uint32_t reserved : 2; // [21..20] Reserved + uint32_t epr_mode_capable : 1; // [22] EPR mode capable + uint32_t unchunked_ext_msg_support : 1; // [23] UnChunked Extended Message Supported + uint32_t no_usb_suspend : 1; // [24] No USB Suspend + uint32_t usb_comm_capable : 1; // [25] USB Communications Capable + uint32_t capability_mismatch : 1; // [26] Capability Mismatch + uint32_t give_back_flag : 1; // [27] GiveBack Flag: 0 = Max, 1 = Min + uint32_t object_position : 4; // [31..28] Object Position +} pd_rdo_battery_t; +TU_VERIFY_STATIC(sizeof(pd_rdo_battery_t) == 4, "Invalid size"); + + +TU_ATTR_PACKED_END // End of all packed definitions +TU_ATTR_BIT_FIELD_ORDER_END + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/typec/tcd.h b/src/typec/tcd.h index b131d6ba9..ee73943bd 100644 --- a/src/typec/tcd.h +++ b/src/typec/tcd.h @@ -28,6 +28,8 @@ #define _TUSB_TCD_H_ #include "common/tusb_common.h" +#include "pd_types.h" + #include "osal/osal.h" #include "common/tusb_fifo.h" @@ -69,7 +71,7 @@ typedef struct { //--------------------------------------------------------------------+ // Initialize controller -bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type); +bool tcd_init(uint8_t rhport, uint32_t port_type); // Enable interrupt void tcd_int_enable (uint8_t rhport); @@ -84,7 +86,7 @@ void tcd_int_handler(uint8_t rhport); // //--------------------------------------------------------------------+ -bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes); +bool tcd_msg_receive(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes); bool tcd_msg_send(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes); //--------------------------------------------------------------------+ @@ -135,4 +137,8 @@ void tcd_event_tx_complete(uint8_t rhport, uint16_t xferred_bytes, uint8_t resul tcd_event_handler(&event, in_isr); } +#ifdef __cplusplus +} +#endif + #endif diff --git a/src/typec/utcd.c b/src/typec/utcd.c index 09031e5c9..439fe89b9 100644 --- a/src/typec/utcd.c +++ b/src/typec/utcd.c @@ -62,7 +62,7 @@ bool tuc_inited(uint8_t rhport) { return _utcd_inited && _port_inited[rhport]; } -bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) { +bool tuc_init(uint8_t rhport, uint32_t port_type) { // Initialize stack if (!_utcd_inited) { tu_memclr(_port_inited, sizeof(_port_inited)); @@ -91,38 +91,38 @@ bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) { // //--------------------------------------------------------------------+ -bool utcd_msg_send(uint8_t rhport, tusb_pd_header_t const* header, void const* data) { +bool utcd_msg_send(uint8_t rhport, pd_header_t const* header, void const* data) { // copy header - memcpy(_tx_buf, header, sizeof(tusb_pd_header_t)); + memcpy(_tx_buf, header, sizeof(pd_header_t)); // copy data objcet if available uint16_t const n_data_obj = header->n_data_obj; if (n_data_obj > 0) { - memcpy(_tx_buf + sizeof(tusb_pd_header_t), data, n_data_obj * 4); + memcpy(_tx_buf + sizeof(pd_header_t), data, n_data_obj * 4); } - return tcd_msg_send(rhport, _tx_buf, sizeof(tusb_pd_header_t) + n_data_obj * 4); + return tcd_msg_send(rhport, _tx_buf, sizeof(pd_header_t) + n_data_obj * 4); } bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) { (void) rhport; uint8_t const* p_end = buf + len; - tusb_pd_header_t const* header = (tusb_pd_header_t const*) buf; - uint8_t const * ptr = buf + sizeof(tusb_pd_header_t); + pd_header_t const* header = (pd_header_t const*) buf; + uint8_t const * ptr = buf + sizeof(pd_header_t); if (header->n_data_obj == 0) { // control message switch (header->msg_type) { - case TUSB_PD_CTRL_GOOD_CRC: + case PD_CTRL_GOOD_CRC: break; - case TUSB_PD_CTRL_ACCEPT: + case PD_CTRL_ACCEPT: break; - case TUSB_PD_CTRL_REJECT: + case PD_CTRL_REJECT: break; - case TUSB_PD_CTRL_PS_RDY: + case PD_CTRL_PS_READY: break; default: break; @@ -130,7 +130,7 @@ bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) { } else { // data message switch (header->msg_type) { - case TUSB_PD_DATA_SOURCE_CAP: { + case PD_DATA_SOURCE_CAP: { // Examine source capability and select a suitable PDO (starting from 1 with safe5v) uint8_t obj_pos = 1; @@ -172,11 +172,11 @@ bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) { .object_position = obj_pos, }; - tusb_pd_header_t const req_header = { - .msg_type = TUSB_PD_DATA_REQUEST, - .data_role = TUSB_PD_DATA_ROLE_UFP, - .specs_rev = TUSB_PD_REV20, - .power_role = TUSB_PD_POWER_ROLE_SINK, + pd_header_t const req_header = { + .msg_type = PD_DATA_REQUEST, + .data_role = PD_DATA_ROLE_UFP, + .specs_rev = PD_REV_20, + .power_role = PD_POWER_ROLE_SINK, .msg_id = 0, .n_data_obj = 1, .extended = 0, @@ -200,7 +200,7 @@ void tcd_event_handler(tcd_event_t const * event, bool in_isr) { case TCD_EVENT_CC_CHANGED: if (event->cc_changed.cc_state[0] || event->cc_changed.cc_state[1]) { // Attach - tcd_rx_start(event->rhport, _rx_buf, sizeof(_rx_buf)); + tcd_msg_receive(event->rhport, _rx_buf, sizeof(_rx_buf)); }else { // Detach } @@ -213,7 +213,7 @@ void tcd_event_handler(tcd_event_t const * event, bool in_isr) { } // start new rx - tcd_rx_start(event->rhport, _rx_buf, sizeof(_rx_buf)); + tcd_msg_receive(event->rhport, _rx_buf, sizeof(_rx_buf)); break; default: break; diff --git a/src/typec/utcd.h b/src/typec/utcd.h index bb1523253..740e477ac 100644 --- a/src/typec/utcd.h +++ b/src/typec/utcd.h @@ -28,6 +28,7 @@ #define _TUSB_UTCD_H_ #include "common/tusb_common.h" +#include "pd_types.h" #ifdef __cplusplus extern "C" { @@ -41,105 +42,12 @@ extern "C" { #define CFG_TUC_TASK_QUEUE_SZ 8 #endif -//--------------------------------------------------------------------+ -// Source Capability -//--------------------------------------------------------------------+ - -// All table references are from USBPD Specification rev3.1 version 1.8 -enum { - PD_PDO_TYPE_FIXED = 0, // Vmin = Vmax - PD_PDO_TYPE_BATTERY, - PD_PDO_TYPE_VARIABLE, // non-battery - PD_PDO_TYPE_APDO, // Augmented Power Data Object -}; - -// Fixed Power Data Object (PDO) table 6-9 -typedef struct TU_ATTR_PACKED { - uint32_t current_max_10ma : 10; // [9..0] Max current in 10mA unit - uint32_t voltage_50mv : 10; // [19..10] Voltage in 50mV unit - uint32_t current_peak : 2; // [21..20] Peak current - uint32_t reserved : 1; // [22] Reserved - uint32_t epr_mode_capable : 1; // [23] epr_mode_capable - uint32_t unchunked_ext_msg_support : 1; // [24] UnChunked Extended Message Supported - uint32_t dual_role_data : 1; // [25] Dual Role Data - uint32_t usb_comm_capable : 1; // [26] USB Communications Capable - uint32_t unconstrained_power : 1; // [27] Unconstrained Power - uint32_t usb_suspend_supported : 1; // [28] USB Suspend Supported - uint32_t dual_role_power : 1; // [29] Dual Role Power - uint32_t type : 2; // [30] Fixed Supply type = PD_PDO_TYPE_FIXED -} pd_pdo_fixed_t; -TU_VERIFY_STATIC(sizeof(pd_pdo_fixed_t) == 4, "Invalid size"); - -// Battery Power Data Object (PDO) table 6-12 -typedef struct TU_ATTR_PACKED { - uint32_t power_max_250mw : 10; // [9..0] Max allowable power in 250mW unit - uint32_t voltage_min_50mv : 10; // [19..10] Minimum voltage in 50mV unit - uint32_t voltage_max_50mv : 10; // [29..20] Maximum voltage in 50mV unit - uint32_t type : 2; // [31..30] Battery type = PD_PDO_TYPE_BATTERY -} pd_pdo_battery_t; -TU_VERIFY_STATIC(sizeof(pd_pdo_battery_t) == 4, "Invalid size"); - -// Variable Power Data Object (PDO) table 6-11 -typedef struct TU_ATTR_PACKED { - uint32_t current_max_10ma : 10; // [9..0] Max current in 10mA unit - uint32_t voltage_min_50mv : 10; // [19..10] Minimum voltage in 50mV unit - uint32_t voltage_max_50mv : 10; // [29..20] Maximum voltage in 50mV unit - uint32_t type : 2; // [31..30] Variable Supply type = PD_PDO_TYPE_VARIABLE -} pd_pdo_variable_t; -TU_VERIFY_STATIC(sizeof(pd_pdo_variable_t) == 4, "Invalid size"); - -// Augmented Power Data Object (PDO) table 6-13 -typedef struct TU_ATTR_PACKED { - uint32_t current_max_50ma : 7; // [6..0] Max current in 50mA unit - uint32_t reserved1 : 1; // [7] Reserved - uint32_t voltage_min_100mv : 8; // [15..8] Minimum Voltage in 100mV unit - uint32_t reserved2 : 1; // [16] Reserved - uint32_t voltage_max_100mv : 8; // [24..17] Maximum Voltage in 100mV unit - uint32_t reserved3 : 2; // [26..25] Reserved - uint32_t pps_power_limited : 1; // [27] PPS Power Limited - uint32_t spr_programmable : 2; // [29..28] SPR Programmable Power Supply - uint32_t type : 2; // [31..30] Augmented Power Data Object = PD_PDO_TYPE_APDO -} pd_pdo_apdo_t; -TU_VERIFY_STATIC(sizeof(pd_pdo_apdo_t) == 4, "Invalid size"); - -//--------------------------------------------------------------------+ -// Request -//--------------------------------------------------------------------+ - -typedef struct TU_ATTR_PACKED { - uint32_t current_extremum_10ma : 10; // [9..0] Max (give back = 0) or Min (give back = 1) current in 10mA unit - uint32_t current_operate_10ma : 10; // [19..10] Operating current in 10mA unit - uint32_t reserved : 2; // [21..20] Reserved - uint32_t epr_mode_capable : 1; // [22] EPR mode capable - uint32_t unchunked_ext_msg_support : 1; // [23] UnChunked Extended Message Supported - uint32_t no_usb_suspend : 1; // [24] No USB Suspend - uint32_t usb_comm_capable : 1; // [25] USB Communications Capable - uint32_t capability_mismatch : 1; // [26] Capability Mismatch - uint32_t give_back_flag : 1; // [27] GiveBack Flag: 0 = Max, 1 = Min - uint32_t object_position : 4; // [31..28] Object Position -} pd_rdo_fixed_variable_t; -TU_VERIFY_STATIC(sizeof(pd_rdo_fixed_variable_t) == 4, "Invalid size"); - -typedef struct TU_ATTR_PACKED { - uint32_t power_extremum_250mw : 10; // [9..0] Max (give back = 0) or Min (give back = 1) operating power in 250mW unit - uint32_t power_operate_250mw : 10; // [19..10] Operating power in 250mW unit - uint32_t reserved : 2; // [21..20] Reserved - uint32_t epr_mode_capable : 1; // [22] EPR mode capable - uint32_t unchunked_ext_msg_support : 1; // [23] UnChunked Extended Message Supported - uint32_t no_usb_suspend : 1; // [24] No USB Suspend - uint32_t usb_comm_capable : 1; // [25] USB Communications Capable - uint32_t capability_mismatch : 1; // [26] Capability Mismatch - uint32_t give_back_flag : 1; // [27] GiveBack Flag: 0 = Max, 1 = Min - uint32_t object_position : 4; // [31..28] Object Position -} pd_rdo_battery_t; -TU_VERIFY_STATIC(sizeof(pd_rdo_battery_t) == 4, "Invalid size"); - //--------------------------------------------------------------------+ // Application API //--------------------------------------------------------------------+ // Init typec stack on a port -bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type); +bool tuc_init(uint8_t rhport, uint32_t port_type); // Check if typec port is initialized bool tuc_inited(uint8_t rhport); @@ -155,4 +63,9 @@ extern void tcd_int_handler(uint8_t rhport); // //--------------------------------------------------------------------+ + +#ifdef __cplusplus +} +#endif + #endif -- cgit v1.3.1 From 6941a5af81b53cd0df52632d403cccdb7d22cf30 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 12 Jun 2023 16:42:27 +0700 Subject: wrap up initial PD support for G4 --- examples/typec/power_delivery/src/main.c | 90 +++++++++++++++- src/typec/tcd.h | 15 ++- src/typec/utcd.c | 178 ++++++++++++++----------------- src/typec/utcd.h | 20 ++++ 4 files changed, 195 insertions(+), 108 deletions(-) (limited to 'src') diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c index 648345a55..42665ed1b 100644 --- a/examples/typec/power_delivery/src/main.c +++ b/examples/typec/power_delivery/src/main.c @@ -62,7 +62,8 @@ int main(void) while (1) { led_blinking_task(); -// tuc_task(); + // tinyusb typec task + tuc_task(); } } @@ -73,6 +74,93 @@ void app_main(void) } #endif +//--------------------------------------------------------------------+ +// TypeC PD callbacks +//--------------------------------------------------------------------+ + +bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end) { + switch (header->msg_type) { + case PD_DATA_SOURCE_CAP: { + printf("PD Source Capabilities\r\n"); + // Examine source capability and select a suitable PDO (starting from 1 with safe5v) + uint8_t obj_pos = 1; + + for(size_t i=0; in_data_obj; i++) { + TU_VERIFY(dobj < p_end); + uint32_t const pdo = tu_le32toh(tu_unaligned_read32(dobj)); + + switch ((pdo >> 30) & 0x03ul) { + case PD_PDO_TYPE_FIXED: { + pd_pdo_fixed_t const* fixed = (pd_pdo_fixed_t const*) &pdo; + printf("[Fixed] %u mV %u mA\r\n", fixed->voltage_50mv*50, fixed->current_max_10ma*10); + break; + } + + case PD_PDO_TYPE_BATTERY: + break; + + case PD_PDO_TYPE_VARIABLE: + break; + + case PD_PDO_TYPE_APDO: + break; + } + + dobj += 4; + } + + //------------- Response with selected PDO -------------// + // Be careful and make sure your board can withstand the selected PDO voltage other than safe5v e.g 12v or 20v + + // Send request with selected PDO position as response to Source Cap + pd_rdo_fixed_variable_t rdo = { + .current_extremum_10ma = 50, // max 500mA + .current_operate_10ma = 30, // 300mA + .reserved = 0, + .epr_mode_capable = 0, + .unchunked_ext_msg_support = 0, + .no_usb_suspend = 0, + .usb_comm_capable = 1, + .capability_mismatch = 0, + .give_back_flag = 0, // exteremum is max + .object_position = obj_pos, + }; + + tuc_msg_request(rhport, &rdo); + + break; + } + + default: break; + } + + return true; +} + +bool tuc_pd_control_received_cb(uint8_t rhport, pd_header_t const* header) { + switch (header->msg_type) { + case PD_CTRL_ACCEPT: + printf("PD Request Accepted\r\n"); + // preparing for power transition + break; + + case PD_CTRL_REJECT: + printf("PD Request Rejected\r\n"); + // try to negotiate further power + break; + + case PD_CTRL_PS_READY: + printf("PD Power Ready\r\n"); + // Source is ready to supply power + break; + + default: + break; + } + + return true; +} + //--------------------------------------------------------------------+ // BLINKING TASK //--------------------------------------------------------------------+ diff --git a/src/typec/tcd.h b/src/typec/tcd.h index ee73943bd..86499c951 100644 --- a/src/typec/tcd.h +++ b/src/typec/tcd.h @@ -48,8 +48,7 @@ enum { TCD_EVENT_TX_COMPLETE, }; - -typedef struct { +typedef struct TU_ATTR_PACKED { uint8_t rhport; uint8_t event_id; @@ -58,10 +57,10 @@ typedef struct { uint8_t cc_state[2]; } cc_changed; - struct { - uint16_t xferred_bytes; - uint8_t result; - } rx_complete; + struct TU_ATTR_PACKED { + uint16_t result : 2; + uint16_t xferred_bytes : 14; + } xfer_complete; }; } tcd_event_t;; @@ -114,7 +113,7 @@ void tcd_event_rx_complete(uint8_t rhport, uint16_t xferred_bytes, uint8_t resul tcd_event_t event = { .rhport = rhport, .event_id = TCD_EVENT_RX_COMPLETE, - .rx_complete = { + .xfer_complete = { .xferred_bytes = xferred_bytes, .result = result } @@ -128,7 +127,7 @@ void tcd_event_tx_complete(uint8_t rhport, uint16_t xferred_bytes, uint8_t resul tcd_event_t event = { .rhport = rhport, .event_id = TCD_EVENT_TX_COMPLETE, - .rx_complete = { + .xfer_complete = { .xferred_bytes = xferred_bytes, .result = result } diff --git a/src/typec/utcd.c b/src/typec/utcd.c index 439fe89b9..831df1fe8 100644 --- a/src/typec/utcd.c +++ b/src/typec/utcd.c @@ -52,8 +52,12 @@ static bool _utcd_inited = false; static bool _port_inited[TUP_TYPEC_RHPORTS_NUM]; // Max possible PD size is 262 bytes -static uint8_t _rx_buf[262] TU_ATTR_ALIGNED(4); -static uint8_t _tx_buf[100] TU_ATTR_ALIGNED(4); +static uint8_t _rx_buf[64] TU_ATTR_ALIGNED(4); +static uint8_t _tx_buf[64] TU_ATTR_ALIGNED(4); + +bool utcd_msg_send(uint8_t rhport, pd_header_t const* header, void const* data); +bool parse_msg_data(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end); +bool parse_msg_control(uint8_t rhport, pd_header_t const* header); //--------------------------------------------------------------------+ // @@ -79,6 +83,7 @@ bool tuc_init(uint8_t rhport, uint32_t port_type) { } TU_LOG_UTCD("UTCD init on port %u\r\n", rhport); + TU_LOG_INT(UTCD_DEBUG, sizeof(tcd_event_t)); TU_ASSERT(tcd_init(rhport, port_type)); tcd_int_enable(rhport); @@ -87,137 +92,112 @@ bool tuc_init(uint8_t rhport, uint32_t port_type) { return true; } -//--------------------------------------------------------------------+ -// -//--------------------------------------------------------------------+ - -bool utcd_msg_send(uint8_t rhport, pd_header_t const* header, void const* data) { - // copy header - memcpy(_tx_buf, header, sizeof(pd_header_t)); - - // copy data objcet if available - uint16_t const n_data_obj = header->n_data_obj; - if (n_data_obj > 0) { - memcpy(_tx_buf + sizeof(pd_header_t), data, n_data_obj * 4); - } +void tuc_task_ext(uint32_t timeout_ms, bool in_isr) { + (void) in_isr; // not implemented yet - return tcd_msg_send(rhport, _tx_buf, sizeof(pd_header_t) + n_data_obj * 4); -} + // Skip if stack is not initialized + if (!_utcd_inited) return; -bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) { - (void) rhport; - uint8_t const* p_end = buf + len; - pd_header_t const* header = (pd_header_t const*) buf; - uint8_t const * ptr = buf + sizeof(pd_header_t); + // Loop until there is no more events in the queue + while (1) { + tcd_event_t event; + if (!osal_queue_receive(_utcd_q, &event, timeout_ms)) return; - if (header->n_data_obj == 0) { - // control message - switch (header->msg_type) { - case PD_CTRL_GOOD_CRC: + switch (event.event_id) { + case TCD_EVENT_CC_CHANGED: break; - case PD_CTRL_ACCEPT: - break; + case TCD_EVENT_RX_COMPLETE: + // TODO process message here in ISR, move to thread later + if (event.xfer_complete.result == XFER_RESULT_SUCCESS) { + pd_header_t const* header = (pd_header_t const*) _rx_buf; - case PD_CTRL_REJECT: - break; + if (header->n_data_obj == 0) { + parse_msg_control(event.rhport, header); - case PD_CTRL_PS_READY: - break; + }else { + uint8_t const* p_end = _rx_buf + event.xfer_complete.xferred_bytes; + uint8_t const * dobj = _rx_buf + sizeof(pd_header_t); - default: break; - } - } else { - // data message - switch (header->msg_type) { - case PD_DATA_SOURCE_CAP: { - // Examine source capability and select a suitable PDO (starting from 1 with safe5v) - uint8_t obj_pos = 1; - - for(size_t i=0; in_data_obj; i++) { - TU_VERIFY(ptr < p_end); - uint32_t const pdo = tu_le32toh(tu_unaligned_read32(ptr)); - - switch ((pdo >> 30) & 0x03ul) { - case PD_PDO_TYPE_FIXED: { - pd_pdo_fixed_t const* fixed = (pd_pdo_fixed_t const*) &pdo; - TU_LOG3("[Fixed] %u mV %u mA\r\n", fixed->voltage_50mv*50, fixed->current_max_10ma*10); - break; - } - - case PD_PDO_TYPE_BATTERY: - break; - - case PD_PDO_TYPE_VARIABLE: - break; - - case PD_PDO_TYPE_APDO: - break; + parse_msg_data(event.rhport, header, dobj, p_end); } - - ptr += 4; } - // Send request with selected PDO position as response to Source Cap - pd_rdo_fixed_variable_t rdo = { - .current_extremum_10ma = 50, // max 500mA - .current_operate_10ma = 30, // 300mA - .reserved = 0, - .epr_mode_capable = 0, - .unchunked_ext_msg_support = 0, - .no_usb_suspend = 0, - .usb_comm_capable = 1, - .capability_mismatch = 0, - .give_back_flag = 0, // exteremum is max - .object_position = obj_pos, - }; - - pd_header_t const req_header = { - .msg_type = PD_DATA_REQUEST, - .data_role = PD_DATA_ROLE_UFP, - .specs_rev = PD_REV_20, - .power_role = PD_POWER_ROLE_SINK, - .msg_id = 0, - .n_data_obj = 1, - .extended = 0, - }; - - utcd_msg_send(rhport, &req_header, &rdo); + // prepare for next message + tcd_msg_receive(event.rhport, _rx_buf, sizeof(_rx_buf)); + break; + case TCD_EVENT_TX_COMPLETE: break; - } default: break; } } +} + +bool parse_msg_data(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end) { + if (tuc_pd_data_received_cb) { + tuc_pd_data_received_cb(rhport, header, dobj, p_end); + } + + return true; +} + +bool parse_msg_control(uint8_t rhport, pd_header_t const* header) { + if (tuc_pd_control_received_cb) { + tuc_pd_control_received_cb(rhport, header); + } return true; } +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +bool utcd_msg_send(uint8_t rhport, pd_header_t const* header, void const* data) { + // copy header + memcpy(_tx_buf, header, sizeof(pd_header_t)); + + // copy data objcet if available + uint16_t const n_data_obj = header->n_data_obj; + if (n_data_obj > 0) { + memcpy(_tx_buf + sizeof(pd_header_t), data, n_data_obj * 4); + } + + return tcd_msg_send(rhport, _tx_buf, sizeof(pd_header_t) + n_data_obj * 4); +} + +bool tuc_msg_request(uint8_t rhport, void const* rdo) { + pd_header_t const header = { + .msg_type = PD_DATA_REQUEST, + .data_role = PD_DATA_ROLE_UFP, + .specs_rev = PD_REV_30, + .power_role = PD_POWER_ROLE_SINK, + .msg_id = 0, + .n_data_obj = 1, + .extended = 0, + }; + + return utcd_msg_send(rhport, &header, rdo); +} + void tcd_event_handler(tcd_event_t const * event, bool in_isr) { (void) in_isr; switch(event->event_id) { case TCD_EVENT_CC_CHANGED: if (event->cc_changed.cc_state[0] || event->cc_changed.cc_state[1]) { - // Attach + // Attach, start receiving tcd_msg_receive(event->rhport, _rx_buf, sizeof(_rx_buf)); }else { // Detach } break; - case TCD_EVENT_RX_COMPLETE: - // TODO process message here in ISR, move to thread later - if (event->rx_complete.result == XFER_RESULT_SUCCESS) { - parse_message(event->rhport, _rx_buf, event->rx_complete.xferred_bytes); - } - - // start new rx - tcd_msg_receive(event->rhport, _rx_buf, sizeof(_rx_buf)); - break; - default: break; } + + osal_queue_send(_utcd_q, event, in_isr); } //--------------------------------------------------------------------+ diff --git a/src/typec/utcd.h b/src/typec/utcd.h index 740e477ac..9fbff9bc6 100644 --- a/src/typec/utcd.h +++ b/src/typec/utcd.h @@ -52,6 +52,17 @@ bool tuc_init(uint8_t rhport, uint32_t port_type); // Check if typec port is initialized bool tuc_inited(uint8_t rhport); +// Task function should be called in main/rtos loop, extended version of tud_task() +// - timeout_ms: millisecond to wait, zero = no wait, 0xFFFFFFFF = wait forever +// - in_isr: if function is called in ISR +void tuc_task_ext(uint32_t timeout_ms, bool in_isr); + +// Task function should be called in main/rtos loop +TU_ATTR_ALWAYS_INLINE static inline +void tuc_task (void) { + tuc_task_ext(UINT32_MAX, false); +} + #ifndef _TUSB_TCD_H_ extern void tcd_int_handler(uint8_t rhport); #endif @@ -59,10 +70,19 @@ extern void tcd_int_handler(uint8_t rhport); // Interrupt handler, name alias to TCD #define tuc_int_handler tcd_int_handler +//--------------------------------------------------------------------+ +// Callbacks +//--------------------------------------------------------------------+ + +TU_ATTR_WEAK bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end); +TU_ATTR_WEAK bool tuc_pd_control_received_cb(uint8_t rhport, pd_header_t const* header); + //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ +bool tuc_msg_request(uint8_t rhport, void const* rdo); + #ifdef __cplusplus } -- cgit v1.3.1 From 9593ab7acc528814faf86c652b2a22209938128d Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 13 Jun 2023 16:40:29 +0700 Subject: fix usbh issue when device genreate multiple attach/detach/attach when plugging in --- src/host/usbh.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 98e959a12..f3e9d3858 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -411,7 +411,14 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) if ( _dev0.enumerating ) { TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport); + + bool is_empty = osal_queue_empty(_usbh_q); osal_queue_send(_usbh_q, &event, in_isr); + + if (is_empty) { + // Exit if this is the only event in the queue, otherwise we may loop forever + return; + } }else { TU_LOG_USBH("[%u:] USBH DEVICE ATTACH\r\n", event.rhport); @@ -1461,7 +1468,10 @@ static bool enum_new_device(hcd_event_t* event) hcd_port_reset_end( _dev0.rhport); // device unplugged while delaying - if ( !hcd_port_connect_status(_dev0.rhport) ) return true; + if ( !hcd_port_connect_status(_dev0.rhport) ) { + enum_full_complete(); + return true; + } _dev0.speed = hcd_port_speed_get(_dev0.rhport ); TU_LOG_USBH("%s Speed\r\n", tu_str_speed[_dev0.speed]); -- cgit v1.3.1 From 05969d2a58d426e5948df5dc0479e2ad8dfd02a9 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 14 Jun 2023 11:07:58 +0700 Subject: rename typec driver --- src/CMakeLists.txt | 2 +- src/tusb.h | 2 +- src/typec/usbc.c | 219 +++++++++++++++++++++++++++++++++++++++++++++++++++++ src/typec/usbc.h | 91 ++++++++++++++++++++++ src/typec/utcd.c | 219 ----------------------------------------------------- src/typec/utcd.h | 91 ---------------------- 6 files changed, 312 insertions(+), 312 deletions(-) create mode 100644 src/typec/usbc.c create mode 100644 src/typec/usbc.h delete mode 100644 src/typec/utcd.c delete mode 100644 src/typec/utcd.h (limited to 'src') diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index ce4486ecd..b99c7be6e 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -33,7 +33,7 @@ function(add_tinyusb TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_host.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_host.c # typec - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/typec/utcd.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/typec/usbc.c ) target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} diff --git a/src/tusb.h b/src/tusb.h index 0b87b1969..37a521fa8 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -42,7 +42,7 @@ //------------- TypeC -------------// #if CFG_TUC_ENABLED - #include "typec/utcd.h" + #include "typec/usbc.h" #endif //------------- HOST -------------// diff --git a/src/typec/usbc.c b/src/typec/usbc.c new file mode 100644 index 000000000..fdf2a0cd6 --- /dev/null +++ b/src/typec/usbc.c @@ -0,0 +1,219 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (thach@tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUC_ENABLED + +#include "tcd.h" +#include "usbc.h" + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +// Debug level of USBD +#define USBC_DEBUG 2 +#define TU_LOG_USBC(...) TU_LOG(USBC_DEBUG, __VA_ARGS__) + +// Event queue +// usbc_int_set() is used as mutex in OS NONE config +void usbc_int_set(bool enabled); +OSAL_QUEUE_DEF(usbc_int_set, _usbc_qdef, CFG_TUC_TASK_QUEUE_SZ, tcd_event_t); +tu_static osal_queue_t _usbc_q; + +// if stack is initialized +static bool _usbc_inited = false; + +// if port is initialized +static bool _port_inited[TUP_TYPEC_RHPORTS_NUM]; + +// Max possible PD size is 262 bytes +static uint8_t _rx_buf[64] TU_ATTR_ALIGNED(4); +static uint8_t _tx_buf[64] TU_ATTR_ALIGNED(4); + +bool usbc_msg_send(uint8_t rhport, pd_header_t const* header, void const* data); +bool parse_msg_data(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end); +bool parse_msg_control(uint8_t rhport, pd_header_t const* header); + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ +bool tuc_inited(uint8_t rhport) { + return _usbc_inited && _port_inited[rhport]; +} + +bool tuc_init(uint8_t rhport, uint32_t port_type) { + // Initialize stack + if (!_usbc_inited) { + tu_memclr(_port_inited, sizeof(_port_inited)); + + _usbc_q = osal_queue_create(&_usbc_qdef); + TU_ASSERT(_usbc_q != NULL); + + _usbc_inited = true; + } + + // skip if port already initialized + if ( _port_inited[rhport] ) { + return true; + } + + TU_LOG_USBC("USBC init on port %u\r\n", rhport); + TU_LOG_INT(USBC_DEBUG, sizeof(tcd_event_t)); + + TU_ASSERT(tcd_init(rhport, port_type)); + tcd_int_enable(rhport); + + _port_inited[rhport] = true; + return true; +} + +void tuc_task_ext(uint32_t timeout_ms, bool in_isr) { + (void) in_isr; // not implemented yet + + // Skip if stack is not initialized + if (!_usbc_inited) return; + + // Loop until there is no more events in the queue + while (1) { + tcd_event_t event; + if (!osal_queue_receive(_usbc_q, &event, timeout_ms)) return; + + switch (event.event_id) { + case TCD_EVENT_CC_CHANGED: + break; + + case TCD_EVENT_RX_COMPLETE: + // TODO process message here in ISR, move to thread later + if (event.xfer_complete.result == XFER_RESULT_SUCCESS) { + pd_header_t const* header = (pd_header_t const*) _rx_buf; + + if (header->n_data_obj == 0) { + parse_msg_control(event.rhport, header); + + }else { + uint8_t const* p_end = _rx_buf + event.xfer_complete.xferred_bytes; + uint8_t const * dobj = _rx_buf + sizeof(pd_header_t); + + parse_msg_data(event.rhport, header, dobj, p_end); + } + } + + // prepare for next message + tcd_msg_receive(event.rhport, _rx_buf, sizeof(_rx_buf)); + break; + + case TCD_EVENT_TX_COMPLETE: + break; + + default: break; + } + } +} + +bool parse_msg_data(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end) { + if (tuc_pd_data_received_cb) { + tuc_pd_data_received_cb(rhport, header, dobj, p_end); + } + + return true; +} + +bool parse_msg_control(uint8_t rhport, pd_header_t const* header) { + if (tuc_pd_control_received_cb) { + tuc_pd_control_received_cb(rhport, header); + } + + return true; +} + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +bool usbc_msg_send(uint8_t rhport, pd_header_t const* header, void const* data) { + // copy header + memcpy(_tx_buf, header, sizeof(pd_header_t)); + + // copy data objcet if available + uint16_t const n_data_obj = header->n_data_obj; + if (n_data_obj > 0) { + memcpy(_tx_buf + sizeof(pd_header_t), data, n_data_obj * 4); + } + + return tcd_msg_send(rhport, _tx_buf, sizeof(pd_header_t) + n_data_obj * 4); +} + +bool tuc_msg_request(uint8_t rhport, void const* rdo) { + pd_header_t const header = { + .msg_type = PD_DATA_REQUEST, + .data_role = PD_DATA_ROLE_UFP, + .specs_rev = PD_REV_30, + .power_role = PD_POWER_ROLE_SINK, + .msg_id = 0, + .n_data_obj = 1, + .extended = 0, + }; + + return usbc_msg_send(rhport, &header, rdo); +} + +void tcd_event_handler(tcd_event_t const * event, bool in_isr) { + (void) in_isr; + switch(event->event_id) { + case TCD_EVENT_CC_CHANGED: + if (event->cc_changed.cc_state[0] || event->cc_changed.cc_state[1]) { + // Attach, start receiving + tcd_msg_receive(event->rhport, _rx_buf, sizeof(_rx_buf)); + }else { + // Detach + } + break; + + default: break; + } + + osal_queue_send(_usbc_q, event, in_isr); +} + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ +void usbc_int_set(bool enabled) { + // Disable all controllers since they shared the same event queue + for (uint8_t p = 0; p < TUP_TYPEC_RHPORTS_NUM; p++) { + if ( _port_inited[p] ) { + if (enabled) { + tcd_int_enable(p); + }else { + tcd_int_disable(p); + } + } + } +} + +#endif diff --git a/src/typec/usbc.h b/src/typec/usbc.h new file mode 100644 index 000000000..9fbff9bc6 --- /dev/null +++ b/src/typec/usbc.h @@ -0,0 +1,91 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_UTCD_H_ +#define _TUSB_UTCD_H_ + +#include "common/tusb_common.h" +#include "pd_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------+ +// TypeC Configuration +//--------------------------------------------------------------------+ + +#ifndef CFG_TUC_TASK_QUEUE_SZ +#define CFG_TUC_TASK_QUEUE_SZ 8 +#endif + +//--------------------------------------------------------------------+ +// Application API +//--------------------------------------------------------------------+ + +// Init typec stack on a port +bool tuc_init(uint8_t rhport, uint32_t port_type); + +// Check if typec port is initialized +bool tuc_inited(uint8_t rhport); + +// Task function should be called in main/rtos loop, extended version of tud_task() +// - timeout_ms: millisecond to wait, zero = no wait, 0xFFFFFFFF = wait forever +// - in_isr: if function is called in ISR +void tuc_task_ext(uint32_t timeout_ms, bool in_isr); + +// Task function should be called in main/rtos loop +TU_ATTR_ALWAYS_INLINE static inline +void tuc_task (void) { + tuc_task_ext(UINT32_MAX, false); +} + +#ifndef _TUSB_TCD_H_ +extern void tcd_int_handler(uint8_t rhport); +#endif + +// Interrupt handler, name alias to TCD +#define tuc_int_handler tcd_int_handler + +//--------------------------------------------------------------------+ +// Callbacks +//--------------------------------------------------------------------+ + +TU_ATTR_WEAK bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end); +TU_ATTR_WEAK bool tuc_pd_control_received_cb(uint8_t rhport, pd_header_t const* header); + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +bool tuc_msg_request(uint8_t rhport, void const* rdo); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/typec/utcd.c b/src/typec/utcd.c deleted file mode 100644 index 831df1fe8..000000000 --- a/src/typec/utcd.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2023 Ha Thach (thach@tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -#if CFG_TUC_ENABLED - -#include "tcd.h" -#include "utcd.h" - -//--------------------------------------------------------------------+ -// -//--------------------------------------------------------------------+ - -// Debug level of USBD -#define UTCD_DEBUG 2 -#define TU_LOG_UTCD(...) TU_LOG(UTCD_DEBUG, __VA_ARGS__) - -// Event queue -// utcd_int_set() is used as mutex in OS NONE config -void utcd_int_set(bool enabled); -OSAL_QUEUE_DEF(utcd_int_set, _utcd_qdef, CFG_TUC_TASK_QUEUE_SZ, tcd_event_t); -tu_static osal_queue_t _utcd_q; - -// if stack is initialized -static bool _utcd_inited = false; - -// if port is initialized -static bool _port_inited[TUP_TYPEC_RHPORTS_NUM]; - -// Max possible PD size is 262 bytes -static uint8_t _rx_buf[64] TU_ATTR_ALIGNED(4); -static uint8_t _tx_buf[64] TU_ATTR_ALIGNED(4); - -bool utcd_msg_send(uint8_t rhport, pd_header_t const* header, void const* data); -bool parse_msg_data(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end); -bool parse_msg_control(uint8_t rhport, pd_header_t const* header); - -//--------------------------------------------------------------------+ -// -//--------------------------------------------------------------------+ -bool tuc_inited(uint8_t rhport) { - return _utcd_inited && _port_inited[rhport]; -} - -bool tuc_init(uint8_t rhport, uint32_t port_type) { - // Initialize stack - if (!_utcd_inited) { - tu_memclr(_port_inited, sizeof(_port_inited)); - - _utcd_q = osal_queue_create(&_utcd_qdef); - TU_ASSERT(_utcd_q != NULL); - - _utcd_inited = true; - } - - // skip if port already initialized - if ( _port_inited[rhport] ) { - return true; - } - - TU_LOG_UTCD("UTCD init on port %u\r\n", rhport); - TU_LOG_INT(UTCD_DEBUG, sizeof(tcd_event_t)); - - TU_ASSERT(tcd_init(rhport, port_type)); - tcd_int_enable(rhport); - - _port_inited[rhport] = true; - return true; -} - -void tuc_task_ext(uint32_t timeout_ms, bool in_isr) { - (void) in_isr; // not implemented yet - - // Skip if stack is not initialized - if (!_utcd_inited) return; - - // Loop until there is no more events in the queue - while (1) { - tcd_event_t event; - if (!osal_queue_receive(_utcd_q, &event, timeout_ms)) return; - - switch (event.event_id) { - case TCD_EVENT_CC_CHANGED: - break; - - case TCD_EVENT_RX_COMPLETE: - // TODO process message here in ISR, move to thread later - if (event.xfer_complete.result == XFER_RESULT_SUCCESS) { - pd_header_t const* header = (pd_header_t const*) _rx_buf; - - if (header->n_data_obj == 0) { - parse_msg_control(event.rhport, header); - - }else { - uint8_t const* p_end = _rx_buf + event.xfer_complete.xferred_bytes; - uint8_t const * dobj = _rx_buf + sizeof(pd_header_t); - - parse_msg_data(event.rhport, header, dobj, p_end); - } - } - - // prepare for next message - tcd_msg_receive(event.rhport, _rx_buf, sizeof(_rx_buf)); - break; - - case TCD_EVENT_TX_COMPLETE: - break; - - default: break; - } - } -} - -bool parse_msg_data(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end) { - if (tuc_pd_data_received_cb) { - tuc_pd_data_received_cb(rhport, header, dobj, p_end); - } - - return true; -} - -bool parse_msg_control(uint8_t rhport, pd_header_t const* header) { - if (tuc_pd_control_received_cb) { - tuc_pd_control_received_cb(rhport, header); - } - - return true; -} - -//--------------------------------------------------------------------+ -// -//--------------------------------------------------------------------+ - -bool utcd_msg_send(uint8_t rhport, pd_header_t const* header, void const* data) { - // copy header - memcpy(_tx_buf, header, sizeof(pd_header_t)); - - // copy data objcet if available - uint16_t const n_data_obj = header->n_data_obj; - if (n_data_obj > 0) { - memcpy(_tx_buf + sizeof(pd_header_t), data, n_data_obj * 4); - } - - return tcd_msg_send(rhport, _tx_buf, sizeof(pd_header_t) + n_data_obj * 4); -} - -bool tuc_msg_request(uint8_t rhport, void const* rdo) { - pd_header_t const header = { - .msg_type = PD_DATA_REQUEST, - .data_role = PD_DATA_ROLE_UFP, - .specs_rev = PD_REV_30, - .power_role = PD_POWER_ROLE_SINK, - .msg_id = 0, - .n_data_obj = 1, - .extended = 0, - }; - - return utcd_msg_send(rhport, &header, rdo); -} - -void tcd_event_handler(tcd_event_t const * event, bool in_isr) { - (void) in_isr; - switch(event->event_id) { - case TCD_EVENT_CC_CHANGED: - if (event->cc_changed.cc_state[0] || event->cc_changed.cc_state[1]) { - // Attach, start receiving - tcd_msg_receive(event->rhport, _rx_buf, sizeof(_rx_buf)); - }else { - // Detach - } - break; - - default: break; - } - - osal_queue_send(_utcd_q, event, in_isr); -} - -//--------------------------------------------------------------------+ -// -//--------------------------------------------------------------------+ -void utcd_int_set(bool enabled) { - // Disable all controllers since they shared the same event queue - for (uint8_t p = 0; p < TUP_TYPEC_RHPORTS_NUM; p++) { - if ( _port_inited[p] ) { - if (enabled) { - tcd_int_enable(p); - }else { - tcd_int_disable(p); - } - } - } -} - -#endif diff --git a/src/typec/utcd.h b/src/typec/utcd.h deleted file mode 100644 index 9fbff9bc6..000000000 --- a/src/typec/utcd.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2023 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef _TUSB_UTCD_H_ -#define _TUSB_UTCD_H_ - -#include "common/tusb_common.h" -#include "pd_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -//--------------------------------------------------------------------+ -// TypeC Configuration -//--------------------------------------------------------------------+ - -#ifndef CFG_TUC_TASK_QUEUE_SZ -#define CFG_TUC_TASK_QUEUE_SZ 8 -#endif - -//--------------------------------------------------------------------+ -// Application API -//--------------------------------------------------------------------+ - -// Init typec stack on a port -bool tuc_init(uint8_t rhport, uint32_t port_type); - -// Check if typec port is initialized -bool tuc_inited(uint8_t rhport); - -// Task function should be called in main/rtos loop, extended version of tud_task() -// - timeout_ms: millisecond to wait, zero = no wait, 0xFFFFFFFF = wait forever -// - in_isr: if function is called in ISR -void tuc_task_ext(uint32_t timeout_ms, bool in_isr); - -// Task function should be called in main/rtos loop -TU_ATTR_ALWAYS_INLINE static inline -void tuc_task (void) { - tuc_task_ext(UINT32_MAX, false); -} - -#ifndef _TUSB_TCD_H_ -extern void tcd_int_handler(uint8_t rhport); -#endif - -// Interrupt handler, name alias to TCD -#define tuc_int_handler tcd_int_handler - -//--------------------------------------------------------------------+ -// Callbacks -//--------------------------------------------------------------------+ - -TU_ATTR_WEAK bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end); -TU_ATTR_WEAK bool tuc_pd_control_received_cb(uint8_t rhport, pd_header_t const* header); - -//--------------------------------------------------------------------+ -// -//--------------------------------------------------------------------+ - -bool tuc_msg_request(uint8_t rhport, void const* rdo); - - -#ifdef __cplusplus -} -#endif - -#endif -- cgit v1.3.1 From d70403f1f496f5853251f83392ffe80130255489 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 15 Jun 2023 13:06:27 +0700 Subject: refactor khci to chipidea fs driver for device (host is not yet) --- .idea/cmake.xml | 3 +- .idea/runConfigurations/mcx947_jlink.xml | 2 +- .idea/runConfigurations/rt1010_jlink.xml | 2 +- .idea/runConfigurations/rt1060_jlink.xml | 2 +- hw/bsp/kinetis_kl/family.cmake | 2 +- hw/bsp/mcx/boards/mcxn947brk/board.cmake | 8 +- hw/bsp/mcx/family.c | 27 +- hw/bsp/mcx/family.cmake | 4 +- hw/bsp/mcx/family.mk | 17 +- src/common/tusb_mcu.h | 6 +- src/portable/chipidea/ci_fs/ci_fs_kinetis.h | 51 +++ src/portable/chipidea/ci_fs/ci_fs_mcx.h | 47 +++ src/portable/chipidea/ci_fs/ci_fs_type.h | 118 ++++++ src/portable/chipidea/ci_fs/dcd_ci_fs.c | 555 ++++++++++++++++++++++++++++ 14 files changed, 804 insertions(+), 40 deletions(-) create mode 100644 src/portable/chipidea/ci_fs/ci_fs_kinetis.h create mode 100644 src/portable/chipidea/ci_fs/ci_fs_mcx.h create mode 100644 src/portable/chipidea/ci_fs/ci_fs_type.h create mode 100644 src/portable/chipidea/ci_fs/dcd_ci_fs.c (limited to 'src') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 3c016ccff..c9024715c 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -2,7 +2,7 @@ - + @@ -37,6 +37,7 @@ + \ No newline at end of file diff --git a/.idea/runConfigurations/mcx947_jlink.xml b/.idea/runConfigurations/mcx947_jlink.xml index 71616ab70..27661bec5 100644 --- a/.idea/runConfigurations/mcx947_jlink.xml +++ b/.idea/runConfigurations/mcx947_jlink.xml @@ -1,5 +1,5 @@ - + diff --git a/.idea/runConfigurations/rt1010_jlink.xml b/.idea/runConfigurations/rt1010_jlink.xml index e660a46ae..68ebb8885 100644 --- a/.idea/runConfigurations/rt1010_jlink.xml +++ b/.idea/runConfigurations/rt1010_jlink.xml @@ -1,5 +1,5 @@ - + diff --git a/.idea/runConfigurations/rt1060_jlink.xml b/.idea/runConfigurations/rt1060_jlink.xml index b9a47a2ce..014a4d1b1 100644 --- a/.idea/runConfigurations/rt1060_jlink.xml +++ b/.idea/runConfigurations/rt1060_jlink.xml @@ -1,5 +1,5 @@ - + diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake index 77b932b8e..f491b3dee 100644 --- a/hw/bsp/kinetis_kl/family.cmake +++ b/hw/bsp/kinetis_kl/family.cmake @@ -88,7 +88,7 @@ function(family_configure_example TARGET) # These files are built for each example since it depends on example's tusb_config.h target_sources(${TARGET} PUBLIC # TinyUSB Port - ${TOP}/src/portable/nxp/khci/dcd_khci.c + ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c ${TOP}/src/portable/nxp/khci/hcd_khci.c # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.cmake b/hw/bsp/mcx/boards/mcxn947brk/board.cmake index 650f10967..8c3280743 100644 --- a/hw/bsp/mcx/boards/mcxn947brk/board.cmake +++ b/hw/bsp/mcx/boards/mcxn947brk/board.cmake @@ -5,12 +5,14 @@ set(JLINK_DEVICE MCXN947_M33_0) set(PYOCD_TARGET MCXN947) set(NXPLINK_DEVICE MCXN947:MCXN947) +set(PORT 1) + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC CPU_MCXN947VDF_cm33_core0 - # port 1 is highspeed - BOARD_TUD_RHPORT=1 - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + BOARD_TUD_RHPORT=${PORT} + # port 0 is fullspeed, port 1 is highspeed + BOARD_TUD_MAX_SPEED=$ ) target_sources(${TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c index 36d2f2d0a..4344ffc4e 100644 --- a/hw/bsp/mcx/family.c +++ b/hw/bsp/mcx/family.c @@ -66,6 +66,7 @@ void board_init(void) { BOARD_InitPins(); BOARD_InitBootClocks(); + CLOCK_SetupExtClocking(XTAL0_CLK_HZ); // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); @@ -122,31 +123,13 @@ void board_init(void) // USB VBUS /* PORT0 PIN22 configured as USB0_VBUS */ - CLOCK_SetupExtClocking(XTAL0_CLK_HZ); - #if PORT_SUPPORT_DEVICE(0) // Port0 is Full Speed - /* Turn on USB0 Phy */ - POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); - - /* reset the IP to make sure it's in reset state. */ - RESET_PeripheralReset(kUSB0D_RST_SHIFT_RSTn); - RESET_PeripheralReset(kUSB0HSL_RST_SHIFT_RSTn); - RESET_PeripheralReset(kUSB0HMR_RST_SHIFT_RSTn); - - // Enable USB Clock Adjustments to trim the FRO for the full speed controller - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK; - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); - CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); - - /*According to reference manual, device mode setting has to be set by access usb host register */ - CLOCK_EnableClock(kCLOCK_Usbhsl0); // enable usb0 host clock - USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK; - CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock - - /* enable USB Device clock */ - CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); + CLOCK_AttachClk(kCLK_48M_to_USB0); + CLOCK_EnableClock(kCLOCK_Usb0Ram); + CLOCK_EnableClock(kCLOCK_Usb0Fs); + CLOCK_EnableUsbfsClock(); #endif #if PORT_SUPPORT_DEVICE(1) diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake index 1c85b51f8..7c5feaecf 100644 --- a/hw/bsp/mcx/family.cmake +++ b/hw/bsp/mcx/family.cmake @@ -88,8 +88,8 @@ function(family_configure_example TARGET) #---------- Port Specific ---------- # These files are built for each example since it depends on example's tusb_config.h target_sources(${TARGET} PUBLIC - # TinyUSB Port - ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c + # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS + ${TOP}/src/portable/chipidea/$ # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk index 2cd4c2448..2722c2038 100644 --- a/hw/bsp/mcx/family.mk +++ b/hw/bsp/mcx/family.mk @@ -16,21 +16,24 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_MCXN9 \ -DBOARD_TUD_RHPORT=$(PORT) \ +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration + +# All source paths should be relative to the top level. +LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld + +# TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS ifeq ($(PORT), 1) $(info "PORT1 High Speed") CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + SRC_C += src/portable/chipidea/ci_hs/dcd_ci_hs.c else $(info "PORT0 Full Speed") + CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED + SRC_C += src/portable/chipidea/ci_fs/dcd_ci_fs.c endif -# mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration - -# All source paths should be relative to the top level. -LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld - SRC_C += \ - src/portable/chipidea/ci_hs/dcd_ci_hs.c \ $(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \ diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index f89467e75..485d6168d 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -79,7 +79,11 @@ #define TUP_RHPORT_HIGHSPEED 1 #elif TU_CHECK_MCU(OPT_MCU_MCXN9) - // NOTE: MCXN943 port 1 use chipidea HS, port 0 use chipidea FS + // USB0 is chipidea FS + #define TUP_USBIP_CHIPIDEA_FS + #define TUP_USBIP_CHIPIDEA_FS_MCX + + // USB1 is chipidea HS #define TUP_USBIP_CHIPIDEA_HS #define TUP_USBIP_EHCI diff --git a/src/portable/chipidea/ci_fs/ci_fs_kinetis.h b/src/portable/chipidea/ci_fs/ci_fs_kinetis.h new file mode 100644 index 000000000..cd21af1c7 --- /dev/null +++ b/src/portable/chipidea/ci_fs/ci_fs_kinetis.h @@ -0,0 +1,51 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _CI_FS_KINETIS_H +#define _CI_FS_KINETIS_H + +#include "fsl_device_registers.h" + +//static const ci_fs_controller_t _ci_controller[] = { +// {.reg_base = USB0_BASE, .irqnum = USB0_IRQn} +//}; + +#define CI_FS_REG(_port) ((ci_fs_regs_t*) USB0_BASE) +#define CI_REG CI_FS_REG(0) + +void dcd_int_enable(uint8_t rhport) +{ + (void) rhport; + NVIC_EnableIRQ(USB0_IRQn); +} + +void dcd_int_disable(uint8_t rhport) +{ + (void) rhport; + NVIC_DisableIRQ(USB0_IRQn); +} + +#endif diff --git a/src/portable/chipidea/ci_fs/ci_fs_mcx.h b/src/portable/chipidea/ci_fs/ci_fs_mcx.h new file mode 100644 index 000000000..3bfcd398e --- /dev/null +++ b/src/portable/chipidea/ci_fs/ci_fs_mcx.h @@ -0,0 +1,47 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _CI_FS_MCX_H +#define _CI_FS_MCX_H + +#include "fsl_device_registers.h" + +#define CI_FS_REG(_port) ((ci_fs_regs_t*) USBFS0_BASE) +#define CI_REG CI_FS_REG(0) + +void dcd_int_enable(uint8_t rhport) +{ + (void) rhport; + NVIC_EnableIRQ(USB0_FS_IRQn); +} + +void dcd_int_disable(uint8_t rhport) +{ + (void) rhport; + NVIC_DisableIRQ(USB0_FS_IRQn); +} + +#endif diff --git a/src/portable/chipidea/ci_fs/ci_fs_type.h b/src/portable/chipidea/ci_fs/ci_fs_type.h new file mode 100644 index 000000000..5a5e53fb0 --- /dev/null +++ b/src/portable/chipidea/ci_fs/ci_fs_type.h @@ -0,0 +1,118 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _CI_FS_TYPE_H +#define _CI_FS_TYPE_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +// Note: some MCUs can only access these registers in 8-bit mode +// align 4 is used to get rid of reserved fields +#define _va32 volatile TU_ATTR_ALIGNED(4) + +typedef struct { + _va32 uint8_t PER_ID; // [00] Peripheral ID register + _va32 uint8_t ID_COMP; // [04] Peripheral ID complement register + _va32 uint8_t REV; // [08] Peripheral revision register + _va32 uint8_t ADD_INFO; // [0C] Peripheral additional info register + _va32 uint8_t OTG_ISTAT; // [10] OTG Interrupt Status Register + _va32 uint8_t OTG_ICTRL; // [14] OTG Interrupt Control Register + _va32 uint8_t OTG_STAT; // [18] OTG Status Register + _va32 uint8_t OTG_CTRL; // [1C] OTG Control register + uint32_t reserved_20[24]; // [20] + _va32 uint8_t INT_STAT; // [80] Interrupt status register + _va32 uint8_t INT_EN; // [84] Interrupt enable register + _va32 uint8_t ERR_STAT; // [88] Error interrupt status register + _va32 uint8_t ERR_ENB; // [8C] Error interrupt enable register + _va32 uint8_t STAT; // [90] Status register + _va32 uint8_t CTL; // [94] Control register + _va32 uint8_t ADDR; // [98] Address register + _va32 uint8_t BDT_PAGE1; // [9C] BDT page register 1 + _va32 uint8_t FRM_NUML; // [A0] Frame number register + _va32 uint8_t FRM_NUMH; // [A4] Frame number register + _va32 uint8_t TOKEN; // [A8] Token register + _va32 uint8_t SOF_THLD; // [AC] SOF threshold register + _va32 uint8_t BDT_PAGE2; // [B0] BDT page register 2 + _va32 uint8_t BDT_PAGE3; // [B4] BDT page register 3 + + uint32_t reserved_b8; // [B8] + uint32_t reserved_bc; // [BC] + + struct { + _va32 uint8_t CTL; + }EP[16]; // [C0] Endpoint control register + + //----- Following is only found available in NXP Kinetis + _va32 uint8_t USBCTRL; // [100] USB Control register, + _va32 uint8_t OBSERVE; // [104] USB OTG Observe register, + _va32 uint8_t CONTROL; // [108] USB OTG Control register, + _va32 uint8_t USBTRC0; // [10C] USB Transceiver Control Register 0, + uint32_t reserved_110; // [110] + _va32 uint8_t USBFRMADJUST; // [114] Frame Adjust Register, + + //----- Following is only found available in NXP MCX + uint32_t reserved_118[3]; // [118] + _va32 uint8_t KEEP_ALIVE_CTRL; // [124] Keep Alive Mode Control, + _va32 uint8_t KEEP_ALIVE_WKCTRL; // [128] Keep Alive Mode Wakeup Control, + _va32 uint8_t MISCCTRL; // [12C] Miscellaneous Control, + _va32 uint8_t STALL_IL_DIS; // [130] Peripheral Mode Stall Disable for Endpoints[ 7..0] IN + _va32 uint8_t STALL_IH_DIS; // [134] Peripheral Mode Stall Disable for Endpoints[15..8] IN + _va32 uint8_t STALL_OL_DIS; // [138] Peripheral Mode Stall Disable for Endpoints[ 7..0] OUT + _va32 uint8_t STALL_OH_DIS; // [13C] Peripheral Mode Stall Disable for Endpoints[15..8] OUT + _va32 uint8_t CLK_RECOVER_CTRL; // [140] USB Clock Recovery Control, + _va32 uint8_t CLK_RECOVER_IRC_EN; // [144] FIRC Oscillator Enable, + uint32_t reserved_148[3]; // [148] + _va32 uint8_t CLK_RECOVER_INT_EN; // [154] Clock Recovery Combined Interrupt Enable, + uint32_t reserved_158; // [158] + _va32 uint8_t CLK_RECOVER_INT_STATUS; // [15C] Clock Recovery Separated Interrupt Status, +} ci_fs_regs_t; + +TU_VERIFY_STATIC(sizeof(ci_fs_regs_t) == 0x160, "Size is not correct"); + +typedef struct +{ + uint32_t reg_base; + uint32_t irqnum; +} ci_fs_controller_t; + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c new file mode 100644 index 000000000..37265df8b --- /dev/null +++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c @@ -0,0 +1,555 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Koji Kitayama + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUD_ENABLED && defined(TUP_USBIP_CHIPIDEA_FS) + +#include "device/dcd.h" +#include "ci_fs_type.h" + +#if defined(TUP_USBIP_CHIPIDEA_FS_KINETIS) + #include "ci_fs_kinetis.h" +#elif defined(TUP_USBIP_CHIPIDEA_FS_MCX) + #include "ci_fs_mcx.h" +#else + #error "MCU is not supported" +#endif + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ + +enum { + TOK_PID_OUT = 0x1u, + TOK_PID_IN = 0x9u, + TOK_PID_SETUP = 0xDu, +}; + +typedef struct TU_ATTR_PACKED +{ + union { + uint32_t head; + struct { + union { + struct { + uint16_t : 2; + __IO uint16_t tok_pid : 4; + uint16_t data : 1; + __IO uint16_t own : 1; + uint16_t : 8; + }; + struct { + uint16_t : 2; + uint16_t bdt_stall : 1; + uint16_t dts : 1; + uint16_t ninc : 1; + uint16_t keep : 1; + uint16_t : 10; + }; + }; + __IO uint16_t bc : 10; + uint16_t : 6; + }; + }; + uint8_t *addr; +}buffer_descriptor_t; + +TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 8, "size is not correct" ); + +typedef struct TU_ATTR_PACKED +{ + union { + uint32_t state; + struct { + uint32_t max_packet_size :11; + uint32_t : 5; + uint32_t odd : 1; + uint32_t :15; + }; + }; + uint16_t length; + uint16_t remaining; +}endpoint_state_t; + +TU_VERIFY_STATIC( sizeof(endpoint_state_t) == 8, "size is not correct" ); + +typedef struct +{ + union { + /* [#EP][OUT,IN][EVEN,ODD] */ + buffer_descriptor_t bdt[16][2][2]; + uint16_t bda[512]; + }; + TU_ATTR_ALIGNED(4) union { + endpoint_state_t endpoint[16][2]; + endpoint_state_t endpoint_unified[16 * 2]; + }; + uint8_t setup_packet[8]; + uint8_t addr; +}dcd_data_t; + +//--------------------------------------------------------------------+ +// INTERNAL OBJECT & FUNCTION DECLARATION +//--------------------------------------------------------------------+ +// BDT(Buffer Descriptor Table) must be 256-byte aligned +CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd; + +TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" ); + +static void prepare_next_setup_packet(uint8_t rhport) +{ + const unsigned out_odd = _dcd.endpoint[0][0].odd; + const unsigned in_odd = _dcd.endpoint[0][1].odd; + TU_ASSERT(0 == _dcd.bdt[0][0][out_odd].own, ); + + _dcd.bdt[0][0][out_odd].data = 0; + _dcd.bdt[0][0][out_odd ^ 1].data = 1; + _dcd.bdt[0][1][in_odd].data = 1; + _dcd.bdt[0][1][in_odd ^ 1].data = 0; + dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT), + _dcd.setup_packet, sizeof(_dcd.setup_packet)); +} + +static void process_stall(uint8_t rhport) +{ + for (int i = 0; i < 16; ++i) { + uint32_t const ep_ctl = CI_REG->EP[i].CTL; + + if (ep_ctl & USB_ENDPT_EPSTALL_MASK) { + // prepare next setup if endpoint0 + if ( i == 0 ) prepare_next_setup_packet(rhport); + + // clear stall bit + CI_REG->EP[i].CTL = ep_ctl & ~USB_ENDPT_EPSTALL_MASK; + } + } +} + +static void process_tokdne(uint8_t rhport) +{ + const unsigned s = CI_REG->STAT; + CI_REG->INT_STAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */ + + uint8_t const epnum = (s >> USB_STAT_ENDP_SHIFT); + uint8_t const dir = (s & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT; + unsigned const odd = (s & USB_STAT_ODD_MASK) ? 1 : 0; + + buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s]; + endpoint_state_t *ep = &_dcd.endpoint_unified[s >> 3]; + + /* fetch pid before discarded by the next steps */ + const unsigned pid = bd->tok_pid; + + /* reset values for a next transfer */ + bd->bdt_stall = 0; + bd->dts = 1; + bd->ninc = 0; + bd->keep = 0; + /* update the odd variable to prepare for the next transfer */ + ep->odd = odd ^ 1; + if (pid == TOK_PID_SETUP) { + dcd_event_setup_received(rhport, bd->addr, true); + CI_REG->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; + return; + } + + const unsigned bc = bd->bc; + const unsigned remaining = ep->remaining - bc; + if (remaining && bc == ep->max_packet_size) { + /* continue the transferring consecutive data */ + ep->remaining = remaining; + const int next_remaining = remaining - ep->max_packet_size; + if (next_remaining > 0) { + /* prepare to the after next transfer */ + bd->addr += ep->max_packet_size * 2; + bd->bc = next_remaining > ep->max_packet_size ? ep->max_packet_size: next_remaining; + __DSB(); + bd->own = 1; /* the own bit must set after addr */ + } + return; + } + const unsigned length = ep->length; + dcd_event_xfer_complete(rhport, + tu_edpt_addr(epnum, dir), + length - remaining, XFER_RESULT_SUCCESS, true); + if (0 == epnum && 0 == length) { + /* After completion a ZLP of control transfer, + * it prepares for the next steup transfer. */ + if (_dcd.addr) { + /* When the transfer was the SetAddress, + * the device address should be updated here. */ + CI_REG->ADDR = _dcd.addr; + _dcd.addr = 0; + } + prepare_next_setup_packet(rhport); + } +} + +static void process_bus_reset(uint8_t rhport) +{ + CI_REG->USBCTRL &= ~USB_USBCTRL_SUSP_MASK; + CI_REG->CTL |= USB_CTL_ODDRST_MASK; + CI_REG->ADDR = 0; + CI_REG->INT_EN = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK | USB_INTEN_SLEEPEN_MASK | + USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK; + + CI_REG->EP[0].CTL = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK; + for (unsigned i = 1; i < 16; ++i) { + CI_REG->EP[i].CTL = 0; + } + buffer_descriptor_t *bd = _dcd.bdt[0][0]; + for (unsigned i = 0; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) { + bd->head = 0; + } + const endpoint_state_t ep0 = { + .max_packet_size = CFG_TUD_ENDPOINT0_SIZE, + .odd = 0, + .length = 0, + .remaining = 0, + }; + _dcd.endpoint[0][0] = ep0; + _dcd.endpoint[0][1] = ep0; + tu_memclr(_dcd.endpoint[1], sizeof(_dcd.endpoint) - sizeof(_dcd.endpoint[0])); + _dcd.addr = 0; + prepare_next_setup_packet(rhport); + CI_REG->CTL &= ~USB_CTL_ODDRST_MASK; + dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); +} + +static void process_bus_sleep(uint8_t rhport) +{ + // Enable resume & disable suspend interrupt + const unsigned inten = CI_REG->INT_EN; + + CI_REG->INT_EN = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK; + CI_REG->USBTRC0 |= USB_USBTRC0_USBRESMEN_MASK; + CI_REG->USBCTRL |= USB_USBCTRL_SUSP_MASK; + + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); +} + +static void process_bus_resume(uint8_t rhport) +{ + // Enable suspend & disable resume interrupt + const unsigned inten = CI_REG->INT_EN; + + CI_REG->USBCTRL &= ~USB_USBCTRL_SUSP_MASK; // will also clear USB_USBTRC0_USB_RESUME_INT_MASK + CI_REG->USBTRC0 &= ~USB_USBTRC0_USBRESMEN_MASK; + CI_REG->INT_EN = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK; + + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); +} + +/*------------------------------------------------------------------*/ +/* Device API + *------------------------------------------------------------------*/ +void dcd_init(uint8_t rhport) +{ + (void) rhport; + + CI_REG->USBTRC0 |= USB_USBTRC0_USBRESET_MASK; + while (CI_REG->USBTRC0 & USB_USBTRC0_USBRESET_MASK); + + tu_memclr(&_dcd, sizeof(_dcd)); + CI_REG->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */ + CI_REG->BDT_PAGE1 = (uint8_t)((uintptr_t)_dcd.bdt >> 8); + CI_REG->BDT_PAGE2 = (uint8_t)((uintptr_t)_dcd.bdt >> 16); + CI_REG->BDT_PAGE3 = (uint8_t)((uintptr_t)_dcd.bdt >> 24); + + CI_REG->INT_EN = USB_INTEN_USBRSTEN_MASK; + + dcd_connect(rhport); + // NVIC_ClearPendingIRQ(USB0_IRQn); +} + +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) +{ + _dcd.addr = dev_addr & 0x7F; + /* Response with status first before changing device address */ + dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); +} + +void dcd_remote_wakeup(uint8_t rhport) +{ + (void) rhport; + + CI_REG->CTL |= USB_CTL_RESUME_MASK; + + unsigned cnt = SystemCoreClock / 1000; + while (cnt--) __NOP(); + + CI_REG->CTL &= ~USB_CTL_RESUME_MASK; +} + +void dcd_connect(uint8_t rhport) +{ + (void) rhport; + CI_REG->USBCTRL = 0; + CI_REG->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK; + CI_REG->CTL |= USB_CTL_USBENSOFEN_MASK; +} + +void dcd_disconnect(uint8_t rhport) +{ + (void) rhport; + CI_REG->CTL = 0; + CI_REG->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK; +} + +void dcd_sof_enable(uint8_t rhport, bool en) +{ + (void) rhport; + (void) en; + + // TODO implement later +} + +//--------------------------------------------------------------------+ +// Endpoint API +//--------------------------------------------------------------------+ +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) +{ + (void) rhport; + + const unsigned ep_addr = ep_desc->bEndpointAddress; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir = tu_edpt_dir(ep_addr); + const unsigned xfer = ep_desc->bmAttributes.xfer; + endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; + const unsigned odd = ep->odd; + buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; + + /* No support for control transfer */ + TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL)); + + ep->max_packet_size = tu_edpt_packet_size(ep_desc); + unsigned val = USB_ENDPT_EPCTLDIS_MASK; + val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0; + val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; + CI_REG->EP[epn].CTL |= val; + + if (xfer != TUSB_XFER_ISOCHRONOUS) { + bd[odd].dts = 1; + bd[odd].data = 0; + bd[odd ^ 1].dts = 1; + bd[odd ^ 1].data = 1; + } + + return true; +} + +void dcd_edpt_close_all(uint8_t rhport) +{ + dcd_int_disable(rhport); + + for (unsigned i = 1; i < 16; ++i) { + CI_REG->EP[i].CTL = 0; + } + + dcd_int_enable(rhport); + + buffer_descriptor_t *bd = _dcd.bdt[1][0]; + for (unsigned i = 2; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) { + bd->head = 0; + } + + endpoint_state_t *ep = &_dcd.endpoint[1][0]; + for (unsigned i = 2; i < sizeof(_dcd.endpoint)/sizeof(*ep); ++i, ++ep) { + /* Clear except the odd */ + ep->max_packet_size = 0; + ep->length = 0; + ep->remaining = 0; + } +} + +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) +{ + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir = tu_edpt_dir(ep_addr); + endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; + buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; + const unsigned msk = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; + + dcd_int_disable(rhport); + + CI_REG->EP[epn].CTL &= ~msk; + ep->max_packet_size = 0; + ep->length = 0; + ep->remaining = 0; + bd[0].head = 0; + bd[1].head = 0; + + dcd_int_enable(rhport); +} + +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) +{ + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir = tu_edpt_dir(ep_addr); + endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; + buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd]; + TU_ASSERT(0 == bd->own); + + dcd_int_disable(rhport); + + ep->length = total_bytes; + ep->remaining = total_bytes; + + const unsigned mps = ep->max_packet_size; + if (total_bytes > mps) { + buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1; + /* When total_bytes is greater than the max packet size, + * it prepares to the next transfer to avoid NAK in advance. */ + next->bc = total_bytes >= 2 * mps ? mps: total_bytes - mps; + next->addr = buffer + mps; + next->own = 1; + } + bd->bc = total_bytes >= mps ? mps: total_bytes; + bd->addr = buffer; + __DSB(); + bd->own = 1; /* This bit must be set last */ + + dcd_int_enable(rhport); + + return true; +} + +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) +{ + (void) rhport; + const unsigned epn = tu_edpt_number(ep_addr); + + if (0 == epn) { + CI_REG->EP[epn].CTL |= USB_ENDPT_EPSTALL_MASK; + } else { + const unsigned dir = tu_edpt_dir(ep_addr); + const unsigned odd = _dcd.endpoint[epn][dir].odd; + buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][odd]; + TU_ASSERT(0 == bd->own,); + + dcd_int_disable(rhport); + + bd->bdt_stall = 1; + __DSB(); + bd->own = 1; /* This bit must be set last */ + + dcd_int_enable(rhport); + } +} + +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) +{ + const unsigned epn = tu_edpt_number(ep_addr); + TU_VERIFY(epn,); + const unsigned dir = tu_edpt_dir(ep_addr); + const unsigned odd = _dcd.endpoint[epn][dir].odd; + buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; + TU_VERIFY(bd[odd].own,); + + dcd_int_disable(rhport); + + bd[odd].own = 0; + __DSB(); + + // clear stall + bd[odd].bdt_stall = 0; + + // Reset data toggle + bd[odd ].data = 0; + bd[odd ^ 1].data = 1; + + // We already cleared this in ISR, but just clear it here to be safe + const uint32_t ep_ctl = CI_REG->EP[epn].CTL; + if (ep_ctl & USB_ENDPT_EPSTALL_MASK) { + CI_REG->EP[epn].CTL = ep_ctl & ~USB_ENDPT_EPSTALL_MASK; + } + + dcd_int_enable(rhport); +} + +//--------------------------------------------------------------------+ +// ISR +//--------------------------------------------------------------------+ +void dcd_int_handler(uint8_t rhport) +{ + uint32_t is = CI_REG->INT_STAT; + uint32_t msk = CI_REG->INT_EN; + + // clear non-enabled interrupts + CI_REG->INT_STAT = is & ~msk; + is &= msk; + + if (is & USB_ISTAT_ERROR_MASK) { + /* TODO: */ + uint32_t es = CI_REG->ERR_STAT; + CI_REG->ERR_STAT = es; + CI_REG->INT_STAT = is; /* discard any pending events */ + } + + if (is & USB_ISTAT_USBRST_MASK) { + CI_REG->INT_STAT = is; /* discard any pending events */ + process_bus_reset(rhport); + } + + if (is & USB_ISTAT_SLEEP_MASK) { + // TU_LOG2("Suspend: "); TU_LOG2_HEX(is); + + // Note Host usually has extra delay after bus reset (without SOF), which could falsely + // detected as Sleep event. Though usbd has debouncing logic so we are good + CI_REG->INT_STAT = USB_ISTAT_SLEEP_MASK; + process_bus_sleep(rhport); + } + +#if 0 // ISTAT_RESUME never trigger, probably for host mode ? + if (is & USB_ISTAT_RESUME_MASK) { + // TU_LOG2("ISTAT Resume: "); TU_LOG2_HEX(is); + KHCI->ISTAT = USB_ISTAT_RESUME_MASK; + process_bus_resume(rhport); + } +#endif + + if (CI_REG->USBTRC0 & USB_USBTRC0_USB_RESUME_INT_MASK) { + // TU_LOG2("USBTRC0 Resume: "); TU_LOG2_HEX(is); TU_LOG2_HEX(KHCI->USBTRC0); + process_bus_resume(rhport); + } + + if (is & USB_ISTAT_SOFTOK_MASK) { + CI_REG->INT_STAT = USB_ISTAT_SOFTOK_MASK; + dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); + } + + if (is & USB_ISTAT_STALL_MASK) { + CI_REG->INT_STAT = USB_ISTAT_STALL_MASK; + process_stall(rhport); + } + + if (is & USB_ISTAT_TOKDNE_MASK) { + process_tokdne(rhport); + } +} + +#endif -- cgit v1.3.1 From 96f7cd09dc2c8cd62afc5bb4b325ade45332e0ba Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 16 Jun 2023 10:45:59 +0700 Subject: remove legacy transdimension driver --- .../nxp/transdimension/common_transdimension.h | 136 ----- .../nxp/transdimension/dcd_transdimension.c | 672 --------------------- .../nxp/transdimension/hcd_transdimension.c | 119 ---- 3 files changed, 927 deletions(-) delete mode 100644 src/portable/nxp/transdimension/common_transdimension.h delete mode 100644 src/portable/nxp/transdimension/dcd_transdimension.c delete mode 100644 src/portable/nxp/transdimension/hcd_transdimension.c (limited to 'src') diff --git a/src/portable/nxp/transdimension/common_transdimension.h b/src/portable/nxp/transdimension/common_transdimension.h deleted file mode 100644 index 95ae1903e..000000000 --- a/src/portable/nxp/transdimension/common_transdimension.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2021, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef COMMON_TRANSDIMENSION_H_ -#define COMMON_TRANSDIMENSION_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -// USBCMD -enum { - USBCMD_RUN_STOP = TU_BIT(0), - USBCMD_RESET = TU_BIT(1), - USBCMD_SETUP_TRIPWIRE = TU_BIT(13), - USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14) ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD -// Interrupt Threshold bit 23:16 -}; - -// PORTSC1 -#define PORTSC1_PORT_SPEED_POS 26 - -enum { - PORTSC1_CURRENT_CONNECT_STATUS = TU_BIT(0), - PORTSC1_FORCE_PORT_RESUME = TU_BIT(6), - PORTSC1_SUSPEND = TU_BIT(7), - PORTSC1_FORCE_FULL_SPEED = TU_BIT(24), - PORTSC1_PORT_SPEED = TU_BIT(26) | TU_BIT(27) -}; - -// OTGSC -enum { - OTGSC_VBUS_DISCHARGE = TU_BIT(0), - OTGSC_VBUS_CHARGE = TU_BIT(1), -// OTGSC_HWASSIST_AUTORESET = TU_BIT(2), - OTGSC_OTG_TERMINATION = TU_BIT(3), ///< Must set to 1 when OTG go to device mode - OTGSC_DATA_PULSING = TU_BIT(4), - OTGSC_ID_PULLUP = TU_BIT(5), -// OTGSC_HWASSIT_DATA_PULSE = TU_BIT(6), -// OTGSC_HWASSIT_BDIS_ACONN = TU_BIT(7), - OTGSC_ID = TU_BIT(8), ///< 0 = A device, 1 = B Device - OTGSC_A_VBUS_VALID = TU_BIT(9), - OTGSC_A_SESSION_VALID = TU_BIT(10), - OTGSC_B_SESSION_VALID = TU_BIT(11), - OTGSC_B_SESSION_END = TU_BIT(12), - OTGSC_1MS_TOGGLE = TU_BIT(13), - OTGSC_DATA_BUS_PULSING_STATUS = TU_BIT(14), -}; - -// USBMode -enum { - USBMODE_CM_DEVICE = 2, - USBMODE_CM_HOST = 3, - - USBMODE_SLOM = TU_BIT(3), - USBMODE_SDIS = TU_BIT(4), - - USBMODE_VBUS_POWER_SELECT = TU_BIT(5), // Need to be enabled for LPC18XX/43XX in host mode -}; - -// Device Registers -typedef struct -{ - //------------- ID + HW Parameter Registers-------------// - __I uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX - - //------------- Capability Registers-------------// - __I uint8_t CAPLENGTH; ///< Capability Registers Length - __I uint8_t TU_RESERVED[1]; - __I uint16_t HCIVERSION; ///< Host Controller Interface Version - - __I uint32_t HCSPARAMS; ///< Host Controller Structural Parameters - __I uint32_t HCCPARAMS; ///< Host Controller Capability Parameters - __I uint32_t TU_RESERVED[5]; - - __I uint16_t DCIVERSION; ///< Device Controller Interface Version - __I uint8_t TU_RESERVED[2]; - - __I uint32_t DCCPARAMS; ///< Device Controller Capability Parameters - __I uint32_t TU_RESERVED[6]; - - //------------- Operational Registers -------------// - __IO uint32_t USBCMD; ///< USB Command Register - __IO uint32_t USBSTS; ///< USB Status Register - __IO uint32_t USBINTR; ///< Interrupt Enable Register - __IO uint32_t FRINDEX; ///< USB Frame Index - __I uint32_t TU_RESERVED; - __IO uint32_t DEVICEADDR; ///< Device Address - __IO uint32_t ENDPTLISTADDR; ///< Endpoint List Address - __I uint32_t TU_RESERVED; - __IO uint32_t BURSTSIZE; ///< Programmable Burst Size - __IO uint32_t TXFILLTUNING; ///< TX FIFO Fill Tuning - uint32_t TU_RESERVED[4]; - __IO uint32_t ENDPTNAK; ///< Endpoint NAK - __IO uint32_t ENDPTNAKEN; ///< Endpoint NAK Enable - __I uint32_t TU_RESERVED; - __IO uint32_t PORTSC1; ///< Port Status & Control - __I uint32_t TU_RESERVED[7]; - __IO uint32_t OTGSC; ///< On-The-Go Status & control - __IO uint32_t USBMODE; ///< USB Device Mode - __IO uint32_t ENDPTSETUPSTAT; ///< Endpoint Setup Status - __IO uint32_t ENDPTPRIME; ///< Endpoint Prime - __IO uint32_t ENDPTFLUSH; ///< Endpoint Flush - __I uint32_t ENDPTSTAT; ///< Endpoint Status - __IO uint32_t ENDPTCOMPLETE; ///< Endpoint Complete - __IO uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7 -} dcd_registers_t, hcd_registers_t; - -#ifdef __cplusplus - } -#endif - -#endif /* COMMON_TRANSDIMENSION_H_ */ diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c deleted file mode 100644 index 983d7cfcf..000000000 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ /dev/null @@ -1,672 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -#if CFG_TUD_ENABLED && \ - (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT) - -#warning "transdimenion is renamed to chipidea (portable/chipidea/ci_hs) to match other opensource naming convention such as linux. This file will be removed in the future, please update your makefile accordingly" - -//--------------------------------------------------------------------+ -// INCLUDE -//--------------------------------------------------------------------+ -#if CFG_TUSB_MCU == OPT_MCU_MIMXRT - #include "fsl_device_registers.h" - #define INCLUDE_FSL_DEVICE_REGISTERS -#else - // LPCOpen for 18xx & 43xx - #include "chip.h" -#endif - -#include "common/tusb_common.h" -#include "device/dcd.h" -#include "common_transdimension.h" - -#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1 - #define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr -#else - #define CleanInvalidateDCache_by_Addr(_addr, _dsize) -#endif - -//--------------------------------------------------------------------+ -// MACRO CONSTANT TYPEDEF -//--------------------------------------------------------------------+ - -// ENDPTCTRL -enum { - ENDPTCTRL_STALL = TU_BIT(0), - ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT(5), // used for test only - ENDPTCTRL_TOGGLE_RESET = TU_BIT(6), - ENDPTCTRL_ENABLE = TU_BIT(7) -}; - -enum { - ENDPTCTRL_TYPE_POS = 2, // Endpoint type is 2-bit field -}; - -// USBSTS, USBINTR -enum { - INTR_USB = TU_BIT(0), - INTR_ERROR = TU_BIT(1), - INTR_PORT_CHANGE = TU_BIT(2), - INTR_RESET = TU_BIT(6), - INTR_SOF = TU_BIT(7), - INTR_SUSPEND = TU_BIT(8), - INTR_NAK = TU_BIT(16) -}; - -// Queue Transfer Descriptor -typedef struct -{ - // Word 0: Next QTD Pointer - uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed - - // Word 1: qTQ Token - uint32_t : 3 ; - volatile uint32_t xact_err : 1 ; - uint32_t : 1 ; - volatile uint32_t buffer_err : 1 ; - volatile uint32_t halted : 1 ; - volatile uint32_t active : 1 ; - uint32_t : 2 ; - uint32_t iso_mult_override : 2 ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO. - uint32_t : 3 ; - uint32_t int_on_complete : 1 ; - volatile uint32_t total_bytes : 15 ; - uint32_t : 1 ; - - // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page - uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous - - //--------------------------------------------------------------------+ - // TD is 32 bytes aligned but occupies only 28 bytes - // Therefore there are 4 bytes padding that we can use. - //--------------------------------------------------------------------+ - uint16_t expected_bytes; - uint8_t reserved[2]; -} dcd_qtd_t; - -TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct"); - -// Queue Head -typedef struct -{ - // Word 0: Capabilities and Characteristics - uint32_t : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed. - uint32_t int_on_setup : 1 ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received. - uint32_t max_packet_size : 11 ; ///< Endpoint's wMaxPacketSize - uint32_t : 2 ; - uint32_t zero_length_termination : 1 ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length. - uint32_t iso_mult : 2 ; ///< - - // Word 1: Current qTD Pointer - volatile uint32_t qtd_addr; - - // Word 2-9: Transfer Overlay - volatile dcd_qtd_t qtd_overlay; - - // Word 10-11: Setup request (control OUT only) - volatile tusb_control_request_t setup_request; - - //--------------------------------------------------------------------+ - // QHD is 64 bytes aligned but occupies only 48 bytes - // Therefore there are 16 bytes padding that we can use. - //--------------------------------------------------------------------+ - tu_fifo_t * ff; - uint8_t reserved[12]; -} dcd_qhd_t; - -TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct"); - -//--------------------------------------------------------------------+ -// Variables -//--------------------------------------------------------------------+ - -typedef struct -{ - dcd_registers_t* regs; // registers - const IRQn_Type irqnum; // IRQ number - const uint8_t ep_count; // Max bi-directional Endpoints -}dcd_controller_t; - -#if CFG_TUSB_MCU == OPT_MCU_MIMXRT - static const dcd_controller_t _dcd_controller[] = - { - // RT1010 and RT1020 only has 1 USB controller - #if FSL_FEATURE_SOC_USBHS_COUNT == 1 - { .regs = (dcd_registers_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 } - #else - { .regs = (dcd_registers_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 }, - { .regs = (dcd_registers_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 } - #endif - }; - -#else - static const dcd_controller_t _dcd_controller[] = - { - { .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 }, - { .regs = (dcd_registers_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 } - }; -#endif - -#define QTD_NEXT_INVALID 0x01 - -typedef struct { - // Must be at 2K alignment - // Each endpoint with direction (IN/OUT) occupies a queue head - // for portability, TinyUSB only queue 1 TD for each Qhd - dcd_qhd_t qhd[TUP_DCD_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(64); - dcd_qtd_t qtd[TUP_DCD_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(32); -}dcd_data_t; - -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048) -static dcd_data_t _dcd_data; - -//--------------------------------------------------------------------+ -// Controller API -//--------------------------------------------------------------------+ - -/// follows LPC43xx User Manual 23.10.3 -static void bus_reset(uint8_t rhport) -{ - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - - // The reset value for all endpoint types is the control endpoint. If one endpoint - // direction is enabled and the paired endpoint of opposite direction is disabled, then the - // endpoint type of the unused direction must be changed from the control type to any other - // type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior - // for the data PID tracking on the active endpoint. - for( uint8_t i=1; i < _dcd_controller[rhport].ep_count; i++) - { - dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS)); - } - - //------------- Clear All Registers -------------// - dcd_reg->ENDPTNAK = dcd_reg->ENDPTNAK; - dcd_reg->ENDPTNAKEN = 0; - dcd_reg->USBSTS = dcd_reg->USBSTS; - dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT; - dcd_reg->ENDPTCOMPLETE = dcd_reg->ENDPTCOMPLETE; - - while (dcd_reg->ENDPTPRIME) {} - dcd_reg->ENDPTFLUSH = 0xFFFFFFFF; - while (dcd_reg->ENDPTFLUSH) {} - - // read reset bit in portsc - - //------------- Queue Head & Queue TD -------------// - tu_memclr(&_dcd_data, sizeof(dcd_data_t)); - - //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------// - _dcd_data.qhd[0][0].zero_length_termination = _dcd_data.qhd[0][1].zero_length_termination = 1; - _dcd_data.qhd[0][0].max_packet_size = _dcd_data.qhd[0][1].max_packet_size = CFG_TUD_ENDPOINT0_SIZE; - _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID; - - _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only -} - -void dcd_init(uint8_t rhport) -{ - tu_memclr(&_dcd_data, sizeof(dcd_data_t)); - - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - - // Reset controller - dcd_reg->USBCMD |= USBCMD_RESET; - while( dcd_reg->USBCMD & USBCMD_RESET ) {} - - // Set mode to device, must be set immediately after reset - dcd_reg->USBMODE = USBMODE_CM_DEVICE; - dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION; - -#if !TUD_OPT_HIGH_SPEED - dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED; -#endif - - CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); - - dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment - dcd_reg->USBSTS = dcd_reg->USBSTS; - dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND; - - dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0 - dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect -} - -void dcd_int_enable(uint8_t rhport) -{ - NVIC_EnableIRQ(_dcd_controller[rhport].irqnum); -} - -void dcd_int_disable(uint8_t rhport) -{ - NVIC_DisableIRQ(_dcd_controller[rhport].irqnum); -} - -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) -{ - // Response with status first before changing device address - dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); - - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - dcd_reg->DEVICEADDR = (dev_addr << 25) | TU_BIT(24); -} - -void dcd_remote_wakeup(uint8_t rhport) -{ - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - dcd_reg->PORTSC1 |= PORTSC1_FORCE_PORT_RESUME; -} - -void dcd_connect(uint8_t rhport) -{ - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - dcd_reg->USBCMD |= USBCMD_RUN_STOP; -} - -void dcd_disconnect(uint8_t rhport) -{ - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - dcd_reg->USBCMD &= ~USBCMD_RUN_STOP; -} - -void dcd_sof_enable(uint8_t rhport, bool en) -{ - (void) rhport; - (void) en; - - // TODO implement later -} - -//--------------------------------------------------------------------+ -// HELPER -//--------------------------------------------------------------------+ - -static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes) -{ - // Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the - // address to 32-byte boundaries. Buffer must be word aligned - CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31); - - tu_memclr(p_qtd, sizeof(dcd_qtd_t)); - - p_qtd->next = QTD_NEXT_INVALID; - p_qtd->active = 1; - p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes; - p_qtd->int_on_complete = true; - - if (data_ptr != NULL) - { - p_qtd->buffer[0] = (uint32_t) data_ptr; - - uint32_t const bufend = p_qtd->buffer[0] + total_bytes; - for(uint8_t i=1; i<5; i++) - { - uint32_t const next_page = tu_align4k( p_qtd->buffer[i-1] ) + 4096; - if ( bufend <= next_page ) break; - - p_qtd->buffer[i] = next_page; - - // TODO page[1] FRAME_N for ISO transfer - } - } -} - -//--------------------------------------------------------------------+ -// DCD Endpoint Port -//--------------------------------------------------------------------+ -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) -{ - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0); - - // flush to abort any primed buffer - dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0)); -} - -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) -{ - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - // data toggle also need to be reset - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 ); - dcd_reg->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir ? 16 : 0)); -} - -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) -{ - uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); - - // Must not exceed max endpoint number - TU_ASSERT( epnum < _dcd_controller[rhport].ep_count ); - - //------------- Prepare Queue Head -------------// - dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir]; - tu_memclr(p_qhd, sizeof(dcd_qhd_t)); - - p_qhd->zero_length_termination = 1; - p_qhd->max_packet_size = tu_edpt_packet_size(p_endpoint_desc); - if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) - { - p_qhd->iso_mult = 1; - } - - p_qhd->qtd_overlay.next = QTD_NEXT_INVALID; - - CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); - - // Enable EP Control - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - - uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET; - - if ( dir == TUSB_DIR_OUT ) - { - dcd_reg->ENDPTCTRL[epnum] = (dcd_reg->ENDPTCTRL[epnum] & 0xFFFF0000u) | epctrl; - }else - { - dcd_reg->ENDPTCTRL[epnum] = (dcd_reg->ENDPTCTRL[epnum] & 0x0000FFFFu) | (epctrl << 16); - } - - return true; -} - -void dcd_edpt_close_all (uint8_t rhport) -{ - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - - // Disable all non-control endpoints - for( uint8_t epnum=1; epnum < _dcd_controller[rhport].ep_count; epnum++) - { - _dcd_data.qhd[epnum][TUSB_DIR_OUT].qtd_overlay.halted = 1; - _dcd_data.qhd[epnum][TUSB_DIR_IN ].qtd_overlay.halted = 1; - - dcd_reg->ENDPTFLUSH = TU_BIT(epnum) | TU_BIT(epnum+16); - dcd_reg->ENDPTCTRL[epnum] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS)); - } -} - -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) -{ - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - - _dcd_data.qhd[epnum][dir].qtd_overlay.halted = 1; - - // Flush EP - uint32_t const flush_mask = TU_BIT(epnum + (dir ? 16 : 0)); - dcd_reg->ENDPTFLUSH = flush_mask; - while(dcd_reg->ENDPTFLUSH & flush_mask); - - // Clear EP enable - dcd_reg->ENDPTCTRL[epnum] &=~(ENDPTCTRL_ENABLE << (dir ? 16 : 0)); -} - -static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir) -{ - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir]; - dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir]; - - p_qhd->qtd_overlay.halted = false; // clear any previous error - p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd - - // flush cache - CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); - - if ( epnum == 0 ) - { - // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism - // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out - while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {} - } - - // start transfer - dcd_reg->ENDPTPRIME = TU_BIT(epnum + (dir ? 16 : 0)); -} - -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) -{ - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir]; - dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir]; - - // Prepare qtd - qtd_init(p_qtd, buffer, total_bytes); - - // Start qhd transfer - p_qhd->ff = NULL; - qhd_start_xfer(rhport, epnum, dir); - - return true; -} - -// fifo has to be aligned to 4k boundary -bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) -{ - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir]; - dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir]; - - tu_fifo_buffer_info_t fifo_info; - - if (dir) - { - tu_fifo_get_read_info(ff, &fifo_info); - } else - { - tu_fifo_get_write_info(ff, &fifo_info); - } - - if ( fifo_info.len_lin >= total_bytes ) - { - // Linear length is enough for this transfer - qtd_init(p_qtd, fifo_info.ptr_lin, total_bytes); - } - else - { - // linear part is not enough - - // prepare TD up to linear length - qtd_init(p_qtd, fifo_info.ptr_lin, fifo_info.len_lin); - - if ( !tu_offset4k((uint32_t) fifo_info.ptr_wrap) && !tu_offset4k(tu_fifo_depth(ff)) ) - { - // If buffer is aligned to 4K & buffer size is multiple of 4K - // We can make use of buffer page array to also combine the linear + wrapped length - p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes; - - for(uint8_t i = 1, page = 0; i < 5; i++) - { - // pick up buffer array where linear ends - if (p_qtd->buffer[i] == 0) - { - p_qtd->buffer[i] = (uint32_t) fifo_info.ptr_wrap + 4096 * page; - page++; - } - } - - CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31); - } - else - { - // TODO we may need to carry the wrapped length after the linear part complete - // for now only transfer up to linear part - } - } - - // Start qhd transfer - p_qhd->ff = ff; - qhd_start_xfer(rhport, epnum, dir); - - return true; -} - -//--------------------------------------------------------------------+ -// ISR -//--------------------------------------------------------------------+ - -static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir) -{ - dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir]; - dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir]; - - uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED : - ( p_qtd->xact_err || p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS; - - if ( result != XFER_RESULT_SUCCESS ) - { - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - // flush to abort error buffer - dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0)); - } - - uint16_t const xferred_bytes = p_qtd->expected_bytes - p_qtd->total_bytes; - - if (p_qhd->ff) - { - if (dir == TUSB_DIR_IN) - { - tu_fifo_advance_read_pointer(p_qhd->ff, xferred_bytes); - } else - { - tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes); - } - } - - // only number of bytes in the IOC qtd - dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true); -} - -void dcd_int_handler(uint8_t rhport) -{ - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - - uint32_t const int_enable = dcd_reg->USBINTR; - uint32_t const int_status = dcd_reg->USBSTS & int_enable; - dcd_reg->USBSTS = int_status; // Acknowledge handled interrupt - - // disabled interrupt sources - if (int_status == 0) return; - - // Set if the port controller enters the full or high-speed operational state. - // either from Bus Reset or Suspended state - if (int_status & INTR_PORT_CHANGE) - { - // TU_LOG2("PortChange %08lx\r\n", dcd_reg->PORTSC1); - - // Reset interrupt is not enabled, we manually check if Port Change is due - // to connection / disconnection - if ( dcd_reg->USBSTS & INTR_RESET ) - { - dcd_reg->USBSTS = INTR_RESET; - - if (dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS) - { - uint32_t const speed = (dcd_reg->PORTSC1 & PORTSC1_PORT_SPEED) >> PORTSC1_PORT_SPEED_POS; - bus_reset(rhport); - dcd_event_bus_reset(rhport, (tusb_speed_t) speed, true); - }else - { - dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); - } - } - else - { - // Triggered by resuming from suspended state - if ( !(dcd_reg->PORTSC1 & PORTSC1_SUSPEND) ) - { - dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); - } - } - } - - if (int_status & INTR_SUSPEND) - { - // TU_LOG2("Suspend %08lx\r\n", dcd_reg->PORTSC1); - - if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND) - { - // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration. - // Skip suspend event if we are not addressed - if ((dcd_reg->DEVICEADDR >> 25) & 0x0f) - { - dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); - } - } - } - - if (int_status & INTR_USB) - { - // Make sure we read the latest version of _dcd_data. - CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); - - uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE; - dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge - - if (dcd_reg->ENDPTSETUPSTAT) - { - //------------- Set up Received -------------// - // 23.10.10.2 Operational model for setup transfers - dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT; - - dcd_event_setup_received(rhport, (uint8_t*)(uintptr_t) &_dcd_data.qhd[0][0].setup_request, true); - } - - // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set - // nothing to do, we will submit xfer as error to usbd - // if (int_status & INTR_ERROR) { } - - if ( edpt_complete ) - { - for(uint8_t epnum = 0; epnum < TUP_DCD_ENDPOINT_MAX; epnum++) - { - if ( tu_bit_test(edpt_complete, epnum) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_OUT); - if ( tu_bit_test(edpt_complete, epnum+16) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_IN); - } - } - } - - if (int_status & INTR_SOF) - { - dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); - } -} - -#endif diff --git a/src/portable/nxp/transdimension/hcd_transdimension.c b/src/portable/nxp/transdimension/hcd_transdimension.c deleted file mode 100644 index 0b3e9e4ef..000000000 --- a/src/portable/nxp/transdimension/hcd_transdimension.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -// NXP Trans-Dimension USB IP implement EHCI for host functionality - -#if CFG_TUH_ENABLED && \ - (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT) - -#warning "transdimenion is renamed to chipidea (portable/chipidea/ci_hs) to match other opensource naming convention such as linux. This file will be removed in the future, please update your makefile accordingly" - -//--------------------------------------------------------------------+ -// INCLUDE -//--------------------------------------------------------------------+ -#if CFG_TUSB_MCU == OPT_MCU_MIMXRT - #include "fsl_device_registers.h" -#else - // LPCOpen for 18xx & 43xx - #include "chip.h" -#endif - -#include "common/tusb_common.h" -#include "common_transdimension.h" -#include "portable/ehci/ehci_api.h" - -//--------------------------------------------------------------------+ -// MACRO CONSTANT TYPEDEF -//--------------------------------------------------------------------+ - -// TODO can be merged with dcd_controller_t -typedef struct -{ - uint32_t regs_base; // registers base - const IRQn_Type irqnum; // IRQ number -}hcd_controller_t; - -#if CFG_TUSB_MCU == OPT_MCU_MIMXRT - static const hcd_controller_t _hcd_controller[] = - { - // RT1010 and RT1020 only has 1 USB controller - #if FSL_FEATURE_SOC_USBHS_COUNT == 1 - { .regs_base = USB_BASE , .irqnum = USB_OTG1_IRQn } - #else - { .regs_base = USB1_BASE, .irqnum = USB_OTG1_IRQn }, - { .regs_base = USB2_BASE, .irqnum = USB_OTG2_IRQn } - #endif - }; - -#else - static const hcd_controller_t _hcd_controller[] = - { - { .regs_base = LPC_USB0_BASE, .irqnum = USB0_IRQn }, - { .regs_base = LPC_USB1_BASE, .irqnum = USB1_IRQn } - }; -#endif - -//--------------------------------------------------------------------+ -// Controller API -//--------------------------------------------------------------------+ - -bool hcd_init(uint8_t rhport) -{ - hcd_registers_t* hcd_reg = (hcd_registers_t*) _hcd_controller[rhport].regs_base; - - // Reset controller - hcd_reg->USBCMD |= USBCMD_RESET; - while( hcd_reg->USBCMD & USBCMD_RESET ) {} - - // Set mode to device, must be set immediately after reset -#if CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX - // LPC18XX/43XX need to set VBUS Power Select to HIGH - // RHPORT1 is fullspeed only (need external PHY for Highspeed) - hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT; - if (rhport == 1) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED; -#else - hcd_reg->USBMODE = USBMODE_CM_HOST; -#endif - - // FIXME force full speed, still have issue with Highspeed enumeration - hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED; - - return ehci_init(rhport, (uint32_t) &hcd_reg->CAPLENGTH, (uint32_t) &hcd_reg->USBCMD); -} - -void hcd_int_enable(uint8_t rhport) -{ - NVIC_EnableIRQ(_hcd_controller[rhport].irqnum); -} - -void hcd_int_disable(uint8_t rhport) -{ - NVIC_DisableIRQ(_hcd_controller[rhport].irqnum); -} - -#endif -- cgit v1.3.1 From 8af8869d3bcb1504835ead4ba472cd922d997e8d Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 16 Jun 2023 11:26:38 +0700 Subject: renam OPT_MCU_MIMXRT to OPT_MCU_MIMXRT1XXX fix build util with makefile --- examples/host/bare_api/only.txt | 2 +- examples/host/cdc_msc_hid/only.txt | 2 +- examples/host/hid_controller/only.txt | 2 +- examples/host/msc_file_explorer/only.txt | 2 +- hw/bsp/board_mcu.h | 2 +- hw/bsp/f1c100s/README.md | 2 +- hw/bsp/imxrt/family.cmake | 4 ++-- hw/bsp/imxrt/family.mk | 2 +- src/class/audio/audio_device.c | 4 ++-- src/common/tusb_mcu.h | 2 +- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 2 +- src/portable/chipidea/ci_hs/hcd_ci_hs.c | 5 ++--- src/tusb_option.h | 6 +++--- tools/build_utils.py | 7 +------ 14 files changed, 19 insertions(+), 25 deletions(-) (limited to 'src') diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt index fa9c14857..45da6c3f2 100644 --- a/examples/host/bare_api/only.txt +++ b/examples/host/bare_api/only.txt @@ -3,7 +3,7 @@ mcu:LPC177X_8X mcu:LPC18XX mcu:LPC40XX mcu:LPC43XX -mcu:MIMXRT +mcu:MIMXRT1XXX mcu:MIMXRT10XX mcu:MIMXRT11XX mcu:RP2040 diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt index fa9c14857..45da6c3f2 100644 --- a/examples/host/cdc_msc_hid/only.txt +++ b/examples/host/cdc_msc_hid/only.txt @@ -3,7 +3,7 @@ mcu:LPC177X_8X mcu:LPC18XX mcu:LPC40XX mcu:LPC43XX -mcu:MIMXRT +mcu:MIMXRT1XXX mcu:MIMXRT10XX mcu:MIMXRT11XX mcu:RP2040 diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt index fa9c14857..45da6c3f2 100644 --- a/examples/host/hid_controller/only.txt +++ b/examples/host/hid_controller/only.txt @@ -3,7 +3,7 @@ mcu:LPC177X_8X mcu:LPC18XX mcu:LPC40XX mcu:LPC43XX -mcu:MIMXRT +mcu:MIMXRT1XXX mcu:MIMXRT10XX mcu:MIMXRT11XX mcu:RP2040 diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt index fa9c14857..45da6c3f2 100644 --- a/examples/host/msc_file_explorer/only.txt +++ b/examples/host/msc_file_explorer/only.txt @@ -3,7 +3,7 @@ mcu:LPC177X_8X mcu:LPC18XX mcu:LPC40XX mcu:LPC43XX -mcu:MIMXRT +mcu:MIMXRT1XXX mcu:MIMXRT10XX mcu:MIMXRT11XX mcu:RP2040 diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index edae4c645..ce2f919bf 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -116,7 +116,7 @@ #elif CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI // no header needed -#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT +#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX #include "fsl_device_registers.h" #elif CFG_TUSB_MCU == OPT_MCU_NUC120 diff --git a/hw/bsp/f1c100s/README.md b/hw/bsp/f1c100s/README.md index f7a863c34..86d454f8e 100644 --- a/hw/bsp/f1c100s/README.md +++ b/hw/bsp/f1c100s/README.md @@ -17,4 +17,4 @@ Flash: `make BOARD=f1c100s flash` will write the image to SPI flash, and then re ## TODO -* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT` high speed MCU check in examples (maybe we should extract the logic?) +* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX` high speed MCU check in examples (maybe we should extract the logic?) diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index f687fe833..c2c067141 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -14,7 +14,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(FAMILY_MCUS MIMXRT CACHE INTERNAL "") +set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "") # enable LTO if supported include(CheckIPOSupported) @@ -119,7 +119,7 @@ function(family_configure_example TARGET) ) # Add TinyUSB - family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT) + family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX) # Link dependencies target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk index 0c297f060..c3a69e7c5 100644 --- a/hw/bsp/imxrt/family.mk +++ b/hw/bsp/imxrt/family.mk @@ -13,7 +13,7 @@ CFLAGS += \ -D__ARMVFP__=0 -D__ARMFPV5__=0\ -DXIP_EXTERNAL_FLASH=1 \ -DXIP_BOOT_HEADER_ENABLE=1 \ - -DCFG_TUSB_MCU=OPT_MCU_MIMXRT + -DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX ifdef BOARD_TUD_RHPORT CFLAGS += -DBOARD_TUD_RHPORT=$(BOARD_TUD_RHPORT) diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index f487fe60e..e5dbe988a 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -66,7 +66,7 @@ // Use ring buffer if it's available, some MCUs need extra RAM requirements #ifndef TUD_AUDIO_PREFER_RING_BUFFER - #if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT + #if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX #define TUD_AUDIO_PREFER_RING_BUFFER 0 #else #define TUD_AUDIO_PREFER_RING_BUFFER 1 @@ -85,7 +85,7 @@ CFG_TUSB_MCU == OPT_MCU_RX72N || \ CFG_TUSB_MCU == OPT_MCU_LPC18XX || \ CFG_TUSB_MCU == OPT_MCU_LPC43XX || \ - CFG_TUSB_MCU == OPT_MCU_MIMXRT || \ + CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX || \ CFG_TUSB_MCU == OPT_MCU_MSP432E4 #if TUD_AUDIO_PREFER_RING_BUFFER #define USE_LINEAR_BUFFER 0 diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 485d6168d..56525725e 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -90,7 +90,7 @@ #define TUP_DCD_ENDPOINT_MAX 8 #define TUP_RHPORT_HIGHSPEED 1 -#elif TU_CHECK_MCU(OPT_MCU_MIMXRT) +#elif TU_CHECK_MCU(OPT_MCU_MIMXRT1XXX) #define TUP_USBIP_CHIPIDEA_HS #define TUP_USBIP_EHCI diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 850c82e43..588e761a9 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -31,7 +31,7 @@ #include "device/dcd.h" #include "ci_hs_type.h" -#if CFG_TUSB_MCU == OPT_MCU_MIMXRT +#if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX #include "ci_hs_imxrt.h" void dcd_dcache_clean(void* addr, uint32_t data_size) { diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index 8c27abbf6..0f095147d 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -28,8 +28,7 @@ // Chipidea Highspeed USB IP implement EHCI for host functionality -#if CFG_TUH_ENABLED && \ - (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT) +#if CFG_TUH_ENABLED && defined(TUP_USBIP_EHCI) //--------------------------------------------------------------------+ // INCLUDE @@ -39,7 +38,7 @@ #include "portable/ehci/ehci_api.h" #include "ci_hs_type.h" -#if CFG_TUSB_MCU == OPT_MCU_MIMXRT +#if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX #include "ci_hs_imxrt.h" void hcd_dcache_clean(void* addr, uint32_t data_size) { diff --git a/src/tusb_option.h b/src/tusb_option.h index bb669e693..43e67cf64 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -97,9 +97,9 @@ #define OPT_MCU_VALENTYUSB_EPTRI 600 ///< Fomu eptri config // NXP iMX RT -#define OPT_MCU_MIMXRT 700 ///< NXP iMX RT Series -#define OPT_MCU_MIMXRT10XX OPT_MCU_MIMXRT ///< RT10xx -#define OPT_MCU_MIMXRT11XX OPT_MCU_MIMXRT ///< RT11xx +#define OPT_MCU_MIMXRT1XXX 700 ///< NXP iMX RT1xxx Series +#define OPT_MCU_MIMXRT10XX OPT_MCU_MIMXRT1XXX ///< RT10xx +#define OPT_MCU_MIMXRT11XX OPT_MCU_MIMXRT1XXX ///< RT11xx // Nuvoton #define OPT_MCU_NUC121 800 diff --git a/tools/build_utils.py b/tools/build_utils.py index 6f907729b..5d735bc17 100644 --- a/tools/build_utils.py +++ b/tools/build_utils.py @@ -30,13 +30,8 @@ def skip_example(example, board): family_dir = board_dir.parent.parent family = family_dir.name - # family CMake - family_mk = family_dir / "family.cmake" - # family.mk - if not family_mk.exists(): - family_mk = family_dir / "family.mk" - + family_mk = family_dir / "family.mk" mk_contents = family_mk.read_text() # Find the mcu, first in family mk then board mk -- cgit v1.3.1 From 65d6acdbfaea84c3274e359acd5e5474f04e8851 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 16 Jun 2023 12:02:42 +0700 Subject: fix build warnings --- hw/bsp/family_support.cmake | 2 ++ hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h | 11 +++++------ hw/bsp/imxrt/family.cmake | 12 ++++++++---- src/device/dcd.h | 6 +++--- src/host/hcd.h | 6 +++--- src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 23 +++++++++++++---------- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 12 ++++++------ src/portable/chipidea/ci_hs/hcd_ci_hs.c | 6 +++--- src/portable/ehci/ehci.c | 8 ++++---- 9 files changed, 47 insertions(+), 39 deletions(-) (limited to 'src') diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index dfc2095e5..02040c4ed 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -177,6 +177,8 @@ function(family_add_freertos TARGET) target_include_directories(freertos_config INTERFACE ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig ) + # add board definition to freertos_config mostly for SystemCoreClock + target_link_libraries(freertos_config INTERFACE board_${BOARD}) endif() # freertos kernel should be generic as freertos_config however, CMAKE complains with missing variable diff --git a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h index c1928fbcd..f95927069 100644 --- a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h @@ -44,15 +44,14 @@ // skip if included from IAR assembler #ifndef __IASMARM__ -// FIXME cause redundant-decls warnings -extern uint32_t SystemCoreClock; + #include "fsl_device_registers.h" #endif /* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 1 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE (1024) +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) #define configUSE_PREEMPTION 1 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index c2c067141..fc90b7e80 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -103,10 +103,6 @@ function(family_configure_example TARGET) #---------- Port Specific ---------- # These files are built for each example since it depends on example's tusb_config.h target_sources(${TARGET} PUBLIC - # TinyUSB Port - ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c - ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c - ${TOP}/src/portable/ehci/ehci.c # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c @@ -121,6 +117,14 @@ function(family_configure_example TARGET) # Add TinyUSB family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX) + # Add TinyUSB Port source + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c + ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c + ${TOP}/src/portable/ehci/ehci.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + # Link dependencies target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) diff --git a/src/device/dcd.h b/src/device/dcd.h index 4e9cfd5d5..18a708347 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -108,15 +108,15 @@ typedef struct TU_ATTR_ALIGNED(4) // clean/flush data cache: write cache -> memory. // Required before an DMA TX transfer to make sure data is in memory -void dcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK; +void dcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; // invalidate data cache: mark cache as invalid, next read will read from memory // Required BOTH before and after an DMA RX transfer -void dcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; +void dcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; // clean and invalidate data cache // Required before an DMA transfer where memory is both read/write by DMA -void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; +void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; //--------------------------------------------------------------------+ // Controller API diff --git a/src/host/hcd.h b/src/host/hcd.h index 5a3b0a087..3355c18b2 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -110,15 +110,15 @@ typedef struct // clean/flush data cache: write cache -> memory. // Required before an DMA TX transfer to make sure data is in memory -void hcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK; +void hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; // invalidate data cache: mark cache as invalid, next read will read from memory // Required BOTH before and after an DMA RX transfer -void hcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; +void hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; // clean and invalidate data cache // Required before an DMA transfer where memory is both read/write by DMA -void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; +void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; //--------------------------------------------------------------------+ // Controller API diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h index ceff893bd..c14f00431 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h +++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h @@ -64,25 +64,28 @@ static const ci_hs_controller_t _ci_controller[] = #define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) //------------- DCache -------------// -TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uint32_t addr) { +TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uintptr_t addr) { return !(0x20000000 <= addr && addr < 0x20100000); } -TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean(void* addr, uint32_t data_size) { - if (imxrt_is_cache_mem((uint32_t) addr)) { - SCB_CleanDCache_by_Addr((uint32_t *) addr, (int32_t) data_size); +TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean(void const* addr, uint32_t data_size) { + const uintptr_t addr32 = (uintptr_t) addr; + if (imxrt_is_cache_mem(addr32)) { + SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size); } } -TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_invalidate(void* addr, uint32_t data_size) { - if (imxrt_is_cache_mem((uint32_t) addr)) { - SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size); +TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_invalidate(void const* addr, uint32_t data_size) { + const uintptr_t addr32 = (uintptr_t) addr; + if (imxrt_is_cache_mem(addr32)) { + SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size); } } -TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean_invalidate(void* addr, uint32_t data_size) { - if (imxrt_is_cache_mem((uint32_t) addr)) { - SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size); +TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean_invalidate(void const* addr, uint32_t data_size) { + const uintptr_t addr32 = (uintptr_t) addr; + if (imxrt_is_cache_mem(addr32)) { + SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size); } } diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 588e761a9..f50550d33 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -34,15 +34,15 @@ #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX #include "ci_hs_imxrt.h" - void dcd_dcache_clean(void* addr, uint32_t data_size) { + void dcd_dcache_clean(void const* addr, uint32_t data_size) { imxrt_dcache_clean(addr, data_size); } - void dcd_dcache_invalidate(void* addr, uint32_t data_size) { + void dcd_dcache_invalidate(void const* addr, uint32_t data_size) { imxrt_dcache_invalidate(addr, data_size); } - void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { + void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { imxrt_dcache_clean_invalidate(addr, data_size); } @@ -58,15 +58,15 @@ #error "Unsupported MCUs" #endif - TU_ATTR_WEAK void dcd_dcache_clean(void* addr, uint32_t data_size) { + TU_ATTR_WEAK void dcd_dcache_clean(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; } - TU_ATTR_WEAK void dcd_dcache_invalidate(void* addr, uint32_t data_size) { + TU_ATTR_WEAK void dcd_dcache_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; } - TU_ATTR_WEAK void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { + TU_ATTR_WEAK void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; } #endif diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index 0f095147d..56167b8f6 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -41,15 +41,15 @@ #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX #include "ci_hs_imxrt.h" - void hcd_dcache_clean(void* addr, uint32_t data_size) { + void hcd_dcache_clean(void const* addr, uint32_t data_size) { imxrt_dcache_clean(addr, data_size); } - void hcd_dcache_invalidate(void* addr, uint32_t data_size) { + void hcd_dcache_invalidate(void const* addr, uint32_t data_size) { imxrt_dcache_invalidate(addr, data_size); } - void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { + void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { imxrt_dcache_clean_invalidate(addr, data_size); } diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 2b25eee9d..38711e382 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -162,15 +162,15 @@ static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes) static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type); static inline ehci_link_t* list_next (ehci_link_t const *p_link); -TU_ATTR_WEAK void hcd_dcache_clean(void* addr, uint32_t data_size) { +TU_ATTR_WEAK void hcd_dcache_clean(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; } -TU_ATTR_WEAK void hcd_dcache_invalidate(void* addr, uint32_t data_size) { +TU_ATTR_WEAK void hcd_dcache_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; } -TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { +TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; } @@ -461,7 +461,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet qtd_init(td, setup_packet, 8); td->pid = EHCI_PID_SETUP; - hcd_dcache_clean((void *) setup_packet, 8); + hcd_dcache_clean(setup_packet, 8); // attach TD to QHD -> start transferring qhd_attach_qtd(qhd, td); -- cgit v1.3.1 From a7f330fa94b7a39858f6d770737451b51f061c25 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 16 Jun 2023 14:17:25 +0700 Subject: fix build, update freertos config for cmake --- examples/device/net_lwip_webserver/skip.txt | 2 +- hw/bsp/family_support.cmake | 8 ++------ hw/bsp/imxrt/family.cmake | 4 +--- hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h | 11 +++++------ hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c | 2 +- hw/bsp/kinetis_kl/family.cmake | 10 ++++++---- hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h | 13 ++++++------- hw/bsp/lpc18/family.cmake | 12 +++++++----- hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h | 13 ++++++------- hw/bsp/lpc55/family.cmake | 20 ++++++-------------- hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h | 13 ++++++------- hw/bsp/mcx/family.cmake | 9 ++++++--- hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h | 13 ++++++------- hw/bsp/nrf/boards/pca10095/board.cmake | 2 +- hw/bsp/nrf/family.cmake | 10 +++++++--- hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h | 13 ++++++------- hw/bsp/stm32g0/family.cmake | 11 ++++++----- hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h | 13 ++++++------- hw/bsp/stm32g4/family.cmake | 10 ++++++---- src/portable/nordic/nrf5x/dcd_nrf5x.c | 14 ++++++++++++++ src/portable/st/typec/typec_stm32.c | 4 ++-- 21 files changed, 107 insertions(+), 100 deletions(-) (limited to 'src') diff --git a/examples/device/net_lwip_webserver/skip.txt b/examples/device/net_lwip_webserver/skip.txt index 77c7ec63a..e3a726a2b 100644 --- a/examples/device/net_lwip_webserver/skip.txt +++ b/examples/device/net_lwip_webserver/skip.txt @@ -4,7 +4,7 @@ mcu:MSP430x5xx mcu:NUC121 mcu:SAMD11 mcu:STM32L0 -mcu:MKL25ZXX +mcu:KINETIS_KL family:broadcom_64bit family:broadcom_32bit board:curiosity_nano diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 02040c4ed..0132ef629 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -192,12 +192,8 @@ function(family_add_freertos TARGET) CFG_TUSB_OS=OPT_OS_FREERTOS ) # link tinyusb with freeRTOS kernel - target_link_libraries(${TARGET}-tinyusb PUBLIC - freertos_kernel - ) - target_link_libraries(${TARGET} PUBLIC - freertos_kernel - ) + target_link_libraries(${TARGET}-tinyusb PUBLIC freertos_kernel) + target_link_libraries(${TARGET} PUBLIC freertos_kernel) endfunction() diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index fc90b7e80..4a9842cf9 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -114,10 +114,8 @@ function(family_configure_example TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) - # Add TinyUSB + # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX) - - # Add TinyUSB Port source target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c diff --git a/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h index 960bb23e1..a46af1759 100644 --- a/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h @@ -44,15 +44,14 @@ // skip if included from IAR assembler #ifndef __IASMARM__ -// FIXME cause redundant-decls warnings -extern uint32_t SystemCoreClock; + #include "fsl_device_registers.h" #endif /* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 1 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE (1024) +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) #define configUSE_PREEMPTION 1 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c b/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c index 1ba35e0dc..deabe25aa 100644 --- a/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c +++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c @@ -83,7 +83,7 @@ board: FRDM-KL25Z * Variables ******************************************************************************/ /* System clock frequency. */ -extern uint32_t SystemCoreClock; +//extern uint32_t SystemCoreClock; /******************************************************************************* * Code diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake index f491b3dee..5d4165185 100644 --- a/hw/bsp/kinetis_kl/family.cmake +++ b/hw/bsp/kinetis_kl/family.cmake @@ -87,9 +87,6 @@ function(family_configure_example TARGET) #---------- Port Specific ---------- # These files are built for each example since it depends on example's tusb_config.h target_sources(${TARGET} PUBLIC - # TinyUSB Port - ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c - ${TOP}/src/portable/nxp/khci/hcd_khci.c # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c @@ -101,8 +98,13 @@ function(family_configure_example TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) - # Add TinyUSB + # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_KL) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c + ${TOP}/src/portable/nxp/khci/hcd_khci.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) # Link dependencies target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) diff --git a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h index 323c1a0a4..1b3c64e0b 100644 --- a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h @@ -42,17 +42,16 @@ * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ -// IAR assembler have limited preprocessor support and it only need following macros: +// skip if included from IAR assembler #ifndef __IASMARM__ -// FIXME cause redundant-decls warnings -extern uint32_t SystemCoreClock; + #include "chip.h" #endif /* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 0 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE (1024) +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) #define configUSE_PREEMPTION 1 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake index bcdec9c01..4e6e2b56d 100644 --- a/hw/bsp/lpc18/family.cmake +++ b/hw/bsp/lpc18/family.cmake @@ -79,10 +79,6 @@ function(family_configure_example TARGET) #---------- Port Specific ---------- # These files are built for each example since it depends on example's tusb_config.h target_sources(${TARGET} PUBLIC - # TinyUSB Port - ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c - ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c - ${TOP}/src/portable/ehci/ehci.c # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c @@ -94,8 +90,14 @@ function(family_configure_example TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) - # Add TinyUSB + # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_LPC18XX) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c + ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c + ${TOP}/src/portable/ehci/ehci.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) # Link dependencies target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) diff --git a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h index 421106f08..b1cef793e 100644 --- a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h @@ -42,17 +42,16 @@ * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ -// IAR assembler have limited preprocessor support and it only need following macros: +// skip if included from IAR assembler #ifndef __IASMARM__ -// FIXME cause redundant-decls warnings -extern uint32_t SystemCoreClock; + #include "fsl_device_registers.h" #endif /* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 1 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE (1024) +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) #define configUSE_PREEMPTION 1 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake index 22a09ce10..43fbe8638 100644 --- a/hw/bsp/lpc55/family.cmake +++ b/hw/bsp/lpc55/family.cmake @@ -16,16 +16,6 @@ set(FAMILY_MCUS LPC55XX CACHE INTERNAL "") # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) -#------------------------------------ -# freertos -#------------------------------------ -if (NOT TARGET freertos_config) - add_library(freertos_config INTERFACE) - target_include_directories(freertos_config SYSTEM INTERFACE - ${CMAKE_CURRENT_LIST_DIR}/FreeRTOSConfig - ) -endif() - #------------------------------------ # BOARD_TARGET @@ -106,8 +96,6 @@ function(family_configure_example TARGET) #---------- Port Specific ---------- # These files are built for each example since it depends on example's tusb_config.h target_sources(${TARGET} PUBLIC - # TinyUSB Port - ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c @@ -121,15 +109,19 @@ function(family_configure_example TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) - # Add TinyUSB + # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_LPC55XX) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) # Link dependencies target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_flash_jlink(${TARGET}) - family_flash_nxplink(${TARGET}) + #family_flash_nxplink(${TARGET}) #family_flash_pyocd(${TARGET}) endfunction() diff --git a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h index 421106f08..b1cef793e 100644 --- a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h @@ -42,17 +42,16 @@ * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ -// IAR assembler have limited preprocessor support and it only need following macros: +// skip if included from IAR assembler #ifndef __IASMARM__ -// FIXME cause redundant-decls warnings -extern uint32_t SystemCoreClock; + #include "fsl_device_registers.h" #endif /* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 1 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE (1024) +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) #define configUSE_PREEMPTION 1 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake index 7c5feaecf..83f44222b 100644 --- a/hw/bsp/mcx/family.cmake +++ b/hw/bsp/mcx/family.cmake @@ -88,8 +88,6 @@ function(family_configure_example TARGET) #---------- Port Specific ---------- # These files are built for each example since it depends on example's tusb_config.h target_sources(${TARGET} PUBLIC - # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS - ${TOP}/src/portable/chipidea/$ # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c @@ -101,8 +99,13 @@ function(family_configure_example TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) - # Add TinyUSB + # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MCXN9) + target_sources(${TARGET}-tinyusb PUBLIC + # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS + ${TOP}/src/portable/chipidea/$ + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) # Link dependencies target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) diff --git a/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h index 421106f08..a56f243ea 100644 --- a/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h @@ -42,17 +42,16 @@ * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ -// IAR assembler have limited preprocessor support and it only need following macros: +// skip if included from IAR assembler #ifndef __IASMARM__ -// FIXME cause redundant-decls warnings -extern uint32_t SystemCoreClock; + #include "nrf.h" #endif /* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 1 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE (1024) +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) #define configUSE_PREEMPTION 1 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake index 1eb8ad4f1..1e72243c9 100644 --- a/hw/bsp/nrf/boards/pca10095/board.cmake +++ b/hw/bsp/nrf/boards/pca10095/board.cmake @@ -6,7 +6,7 @@ function(update_board TARGET) NRF5340_XXAA NRF5340_XXAA_APPLICATION ) - target_sources(${TARGET} PUBLIC + target_sources(${TARGET} PRIVATE ${NRFX_DIR}/drivers/src/nrfx_usbreg.c ) endfunction() diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 7faeaf6cb..88670b50b 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -100,8 +100,6 @@ function(family_configure_example TARGET) #---------- Port Specific ---------- # These files are built for each example since it depends on example's tusb_config.h target_sources(${TARGET} PUBLIC - # TinyUSB Port - ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c @@ -113,8 +111,14 @@ function(family_configure_example TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) - # Add TinyUSB + # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_NRF5X) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + + # Link dependencies target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) diff --git a/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h index 1758efcf2..c8736f6d1 100644 --- a/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h @@ -42,17 +42,16 @@ * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ -// IAR assembler have limited preprocessor support and it only need following macros: +// skip if included from IAR assembler #ifndef __IASMARM__ -// FIXME cause redundant-decls warnings -extern uint32_t SystemCoreClock; + #include "stm32g0xx.h" #endif /* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 0 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE (1024) +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) #define configUSE_PREEMPTION 1 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake index 988033070..1381eaa5f 100644 --- a/hw/bsp/stm32g0/family.cmake +++ b/hw/bsp/stm32g0/family.cmake @@ -59,8 +59,6 @@ function(add_board_target BOARD_TARGET) update_board(${BOARD_TARGET}) - cmake_print_variables(CMAKE_C_COMPILER_ID) - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" @@ -90,8 +88,6 @@ function(family_configure_example TARGET) #---------- Port Specific ---------- # These files are built for each example since it depends on example's tusb_config.h target_sources(${TARGET} PUBLIC - # TinyUSB Port - ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c @@ -103,8 +99,13 @@ function(family_configure_example TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) - # Add TinyUSB + # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32G0) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + ${TOP}/src/portable/st/typec/typec_stm32.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) # Link dependencies target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) diff --git a/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h index 7974434d3..95fcbb08a 100644 --- a/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h @@ -42,17 +42,16 @@ * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ -// IAR assembler have limited preprocessor support and it only need following macros: +// skip if included from IAR assembler #ifndef __IASMARM__ -// FIXME cause redundant-decls warnings -extern uint32_t SystemCoreClock; + #include "stm32g4xx.h" #endif /* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 0 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE (1024) +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) #define configUSE_PREEMPTION 1 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake index 618563f66..45525c744 100644 --- a/hw/bsp/stm32g4/family.cmake +++ b/hw/bsp/stm32g4/family.cmake @@ -88,9 +88,6 @@ function(family_configure_example TARGET) #---------- Port Specific ---------- # These files are built for each example since it depends on example's tusb_config.h target_sources(${TARGET} PUBLIC - # TinyUSB Port - ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - ${TOP}/src/portable/st/typec/typec_stm32.c # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c @@ -102,8 +99,13 @@ function(family_configure_example TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) - # Add TinyUSB + # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32G4) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + ${TOP}/src/portable/st/typec/typec_stm32.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) # Link dependencies target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index eee5686f4..acc967bb3 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -29,10 +29,24 @@ #if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_NRF5X #include + +// Suppress warning caused by nrfx driver +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wcast-qual" +#pragma GCC diagnostic ignored "-Wcast-align" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + #include "nrf.h" #include "nrf_clock.h" #include "nrf_power.h" #include "nrfx_usbd_errata.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + #include "device/dcd.h" // TODO remove later diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c index b09dc5bae..231da5450 100644 --- a/src/portable/st/typec/typec_stm32.c +++ b/src/portable/st/typec/typec_stm32.c @@ -186,7 +186,7 @@ bool tcd_init(uint8_t rhport, uint32_t port_type) { v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03; - TU_LOG1("Initial VState CC1 = %u, CC2 = %u\r\n", v_cc[0], v_cc[1]); + TU_LOG1("Initial VState CC1 = %lu, CC2 = %lu\r\n", v_cc[0], v_cc[1]); // Enable CC1 & CC2 Interrupt UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE; @@ -246,7 +246,7 @@ void tcd_int_handler(uint8_t rhport) { v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03; - TU_LOG3("VState CC1 = %u, CC2 = %u\n", v_cc[0], v_cc[1]); + TU_LOG3("VState CC1 = %lu, CC2 = %lu\n", v_cc[0], v_cc[1]); uint32_t cr = UCPD1->CR; -- cgit v1.3.1 From e754795d3adec4bc3a66a4131d0662d87acb4893 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 16 Jun 2023 15:29:34 +0700 Subject: fix build warnings --- .github/workflows/build_iar.yml | 2 +- examples/device/audio_test_multi_rate/src/main.c | 2 +- examples/host/msc_file_explorer/CMakeLists.txt | 7 ++++++ examples/rules.mk | 1 + examples/typec/power_delivery/src/main.c | 4 +--- hw/bsp/family_support.cmake | 29 ++++++++++++++++++++++++ hw/bsp/imxrt/family.c | 11 +++++++++ hw/bsp/lpc55/family.cmake | 1 + hw/bsp/nrf/family.c | 14 ++++++++++++ hw/bsp/stm32g4/family.mk | 1 + src/portable/st/typec/typec_stm32.c | 9 +++++--- tools/cmake/toolchain/arm_gcc.cmake | 26 --------------------- tools/cmake/toolchain/arm_iar.cmake | 3 --- 13 files changed, 73 insertions(+), 37 deletions(-) (limited to 'src') diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml index 83e81164a..7e42a66f8 100644 --- a/.github/workflows/build_iar.yml +++ b/.github/workflows/build_iar.yml @@ -32,7 +32,7 @@ jobs: # Alphabetical order # Note: bundle multiple families into a matrix since there is only one self-hosted instance can # run IAR build. Too many matrix can hurt due to setup/teardown overhead. - - 'stm32f0 stm32f1 stm32f4 stm32f7 stm32g4 stm32h7 stm32l4' + - 'stm32f0 stm32f1 stm32f7 stm32h7 stm32l4' steps: - name: Clean workspace run: | diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c index 4dd53dd34..078e783eb 100644 --- a/examples/device/audio_test_multi_rate/src/main.c +++ b/examples/device/audio_test_multi_rate/src/main.c @@ -268,7 +268,7 @@ bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * sampFreq = (uint32_t)((audio_control_cur_4_t *)pBuff)->bCur; - TU_LOG2("Clock set current freq: %d\r\n", sampFreq); + TU_LOG2("Clock set current freq: %lu\r\n", sampFreq); return true; break; diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt index 2d5600059..327d1218a 100644 --- a/examples/host/msc_file_explorer/CMakeLists.txt +++ b/examples/host/msc_file_explorer/CMakeLists.txt @@ -21,6 +21,13 @@ target_sources(${PROJECT} PUBLIC ${TOP}/lib/fatfs/source/ffunicode.c ) +# Suppress warnings on fatfs +set_source_files_properties( + ${TOP}/lib/fatfs/source/ff.c + PROPERTIES + COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual" +) + # Example include target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src diff --git a/examples/rules.mk b/examples/rules.mk index f6422092a..5727ab7e3 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -28,6 +28,7 @@ SRC_C += \ src/common/tusb_fifo.c \ src/device/usbd.c \ src/device/usbd_control.c \ + src/typec/usbc.c \ src/class/audio/audio_device.c \ src/class/cdc/cdc_device.c \ src/class/dfu/dfu_device.c \ diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c index 342a2235f..08590aa74 100644 --- a/examples/typec/power_delivery/src/main.c +++ b/examples/typec/power_delivery/src/main.c @@ -63,9 +63,6 @@ int main(void) tuc_init(0, TUSB_TYPEC_PORT_SNK); - uint32_t start_ms = 0; - bool led_state = false; - while (1) { led_blinking_task(); @@ -155,6 +152,7 @@ bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t } bool tuc_pd_control_received_cb(uint8_t rhport, pd_header_t const* header) { + (void) rhport; switch (header->msg_type) { case PD_CTRL_ACCEPT: printf("PD Request Accepted\r\n"); diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 0132ef629..ec36df5c8 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -19,6 +19,33 @@ if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake) message(FATAL_ERROR "Family '${FAMILY}' is not known/supported") endif() +set(WARNING_FLAGS_GNU + -Wall + -Wextra + -Werror + -Wfatal-errors + -Wdouble-promotion + -Wstrict-prototypes + -Wstrict-overflow + -Werror-implicit-function-declaration + -Wfloat-equal + -Wundef + -Wshadow + -Wwrite-strings + -Wsign-compare + -Wmissing-format-attribute + -Wunreachable-code + -Wcast-align + -Wcast-function-type + -Wcast-qual + -Wnull-dereference + -Wuninitialized + -Wunused + -Wreturn-type + -Wredundant-decls + ) + +set(WARNINGS_FLAGS_IAR "") function(family_filter RESULT DIR) get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR}) @@ -121,6 +148,8 @@ function(family_configure_common TARGET) COMMAND ${CMAKE_SIZE} $ ) + target_compile_options(${TARGET} PUBLIC ${WARNING_FLAGS_${CMAKE_C_COMPILER_ID}}) + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") # Generate map file target_link_options(${TARGET} PUBLIC diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index 46adabf0a..735fbdb9b 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -26,12 +26,23 @@ #include "bsp/board.h" #include "board.h" + +// Suppress warning caused by mcu driver +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + #include "fsl_device_registers.h" #include "fsl_gpio.h" #include "fsl_iomuxc.h" #include "fsl_clock.h" #include "fsl_lpuart.h" +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + #include "clock_config.h" #if defined(BOARD_TUD_RHPORT) && CFG_TUD_ENABLED diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake index 43fbe8638..9f6b1f63d 100644 --- a/hw/bsp/lpc55/family.cmake +++ b/hw/bsp/lpc55/family.cmake @@ -102,6 +102,7 @@ function(family_configure_example TARGET) # external driver ${TOP}/lib/sct_neopixel/sct_neopixel.c ) + target_include_directories(${TARGET} PUBLIC # family, hw, board ${CMAKE_CURRENT_FUNCTION_LIST_DIR} diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index 157b2bf21..6a559ada6 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -27,6 +27,15 @@ #include "bsp/board.h" #include "board.h" +// Suppress warning caused by mcu driver +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wcast-qual" +#pragma GCC diagnostic ignored "-Wcast-align" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wundef" +#endif + #include "nrfx.h" #include "hal/nrf_gpio.h" #include "drivers/include/nrfx_power.h" @@ -37,6 +46,11 @@ #include "nrf_soc.h" #endif +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ diff --git a/hw/bsp/stm32g4/family.mk b/hw/bsp/stm32g4/family.mk index 5ed84422d..a4b644245 100644 --- a/hw/bsp/stm32g4/family.mk +++ b/hw/bsp/stm32g4/family.mk @@ -36,6 +36,7 @@ IAR_ASFLAGS += --cpu cortex-m4 --fpu VFPv4 SRC_C += \ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ + src/portable/st/typec/typec_stm32.c \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c index 231da5450..bf8b660f0 100644 --- a/src/portable/st/typec/typec_stm32.c +++ b/src/portable/st/typec/typec_stm32.c @@ -183,9 +183,9 @@ bool tcd_init(uint8_t rhport, uint32_t port_type) { // Read Voltage State on CC1 & CC2 fore initial state uint32_t v_cc[2]; + (void) v_cc; v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03; - TU_LOG1("Initial VState CC1 = %lu, CC2 = %lu\r\n", v_cc[0], v_cc[1]); // Enable CC1 & CC2 Interrupt @@ -308,8 +308,11 @@ void tcd_int_handler(uint8_t rhport) { if (!(sr & UCPD_SR_RXERR)) { // response with good crc - _good_crc.msg_id = ((pd_header_t const*) _rx_buf)->msg_id; - dma_tx_start(rhport, &_good_crc, 2); + // TODO move this to usbc stack + if (_rx_buf) { + _good_crc.msg_id = ((pd_header_t const *) _rx_buf)->msg_id; + dma_tx_start(rhport, &_good_crc, 2); + } result = XFER_RESULT_SUCCESS; }else { diff --git a/tools/cmake/toolchain/arm_gcc.cmake b/tools/cmake/toolchain/arm_gcc.cmake index 6dd1e7002..cefa9d2ce 100644 --- a/tools/cmake/toolchain/arm_gcc.cmake +++ b/tools/cmake/toolchain/arm_gcc.cmake @@ -35,32 +35,6 @@ set(TOOLCHAIN_EXE_LINKER_FLAGS -Wl,--cref ) -set(TOOLCHAIN_WARNING_FLAGS - -Wall - -Wextra - -Werror - -Wfatal-errors - -Wdouble-promotion - -Wstrict-prototypes - -Wstrict-overflow - -Werror-implicit-function-declaration - -Wfloat-equal - -Wundef - -Wshadow - -Wwrite-strings - -Wsign-compare - -Wmissing-format-attribute - -Wunreachable-code - -Wcast-align - -Wcast-function-type - -Wcast-qual - -Wnull-dereference - -Wuninitialized - -Wunused - -Wreturn-type - -Wredundant-decls - ) - include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake) # try_compile is cmake test compiling its own example, diff --git a/tools/cmake/toolchain/arm_iar.cmake b/tools/cmake/toolchain/arm_iar.cmake index dfbe55e0d..a487e5b9f 100644 --- a/tools/cmake/toolchain/arm_iar.cmake +++ b/tools/cmake/toolchain/arm_iar.cmake @@ -28,7 +28,4 @@ list(APPEND TOOLCHAIN_COMMON_FLAGS list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS ) -list(APPEND TOOLCHAIN_WARNING_FLAGS - ) - include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake) -- cgit v1.3.1 From edbf06aaab9ac7cf098f1170a7a9861f5cf3572e Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 24 Jun 2023 17:35:37 +0700 Subject: separate iar and gcc build for clean make, also add cpu specific make --- examples/device/cdc_msc/Makefile | 6 +- examples/make.mk | 93 ++++++---------------- examples/rules.mk | 144 ++-------------------------------- hw/bsp/stm32h7/family.mk | 13 +-- src/tinyusb.mk | 19 +++++ tools/make/cpu/cortex-m7.mk | 13 ++- tools/make/toolchain/arm_gcc.mk | 77 ++++++++++++++++++ tools/make/toolchain/arm_gcc_rules.mk | 78 ++++++++++++++++++ tools/make/toolchain/arm_iar.mk | 13 +++ tools/make/toolchain/arm_iar_rules.mk | 44 +++++++++++ 10 files changed, 277 insertions(+), 223 deletions(-) create mode 100644 src/tinyusb.mk create mode 100644 tools/make/toolchain/arm_gcc.mk create mode 100644 tools/make/toolchain/arm_gcc_rules.mk create mode 100644 tools/make/toolchain/arm_iar.mk create mode 100644 tools/make/toolchain/arm_iar_rules.mk (limited to 'src') diff --git a/examples/device/cdc_msc/Makefile b/examples/device/cdc_msc/Makefile index da088ea6b..429959e70 100644 --- a/examples/device/cdc_msc/Makefile +++ b/examples/device/cdc_msc/Makefile @@ -5,7 +5,11 @@ INC += \ $(TOP)/hw \ # Example source -EXAMPLE_SOURCE += $(wildcard src/*.c) +EXAMPLE_SOURCE += \ + src/main.c \ + src/msc_disk.c \ + src/usb_descriptors.c \ + SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) include ../../rules.mk diff --git a/examples/make.mk b/examples/make.mk index 28ebc62da..4fcde83c8 100644 --- a/examples/make.mk +++ b/examples/make.mk @@ -2,6 +2,7 @@ # Common make definition for all examples # --------------------------------------- +# Supported toolchain: gcc, iar TOOLCHAIN ?= gcc #-------------- TOP and CURRENT_PATH ------------ @@ -32,13 +33,6 @@ CMDEXE := 1 SHELL := cmd.exe endif - -# Build directory -BUILD := _build/$(BOARD) - -PROJECT := $(notdir $(CURDIR)) -BIN := $(TOP)/_bin/$(BOARD)/$(notdir $(CURDIR)) - # Handy check parameter function check_defined = \ $(strip $(foreach 1,$1, \ @@ -47,6 +41,13 @@ __check_defined = \ $(if $(value $1),, \ $(error Undefined make flag: $1$(if $2, ($2)))) + +# Build directory +BUILD := _build/$(BOARD) + +PROJECT := $(notdir $(CURDIR)) +BIN := $(TOP)/_bin/$(BOARD)/$(notdir $(CURDIR)) + #-------------- Select the board to build for. ------------ # Board without family @@ -81,25 +82,12 @@ endif # Can be set by board, default to ARM GCC CROSS_COMPILE ?= arm-none-eabi- -ifeq ($(CC),iccarm) -USE_IAR = 1 +ifeq ($(TOOLCHAIN),iar) +CC := iccarm endif -ifdef USE_IAR - AS = iasmarm - LD = ilinkarm - OBJCOPY = ielftool - SIZE = size - -else - CC = $(CROSS_COMPILE)gcc - CXX = $(CROSS_COMPILE)g++ - AS = $(CC) -x assembler-with-cpp - LD = $(CC) - - GDB = $(CROSS_COMPILE)gdb - OBJCOPY = $(CROSS_COMPILE)objcopy - SIZE = $(CROSS_COMPILE)size +ifeq ($(CC),iccarm) +USE_IAR = 1 endif ifeq ($(CMDEXE),1) @@ -115,57 +103,19 @@ else endif #-------------- Source files and compiler flags -------------- +# tinyusb makefile +include $(TOP)/src/tinyusb.mk # Include all source C in family & board folder SRC_C += hw/bsp/board.c SRC_C += $(subst $(TOP)/,,$(wildcard $(TOP)/$(BOARD_PATH)/*.c)) -INC += $(TOP)/$(FAMILY_PATH) - -# Allow for -Os to be changed by board makefiles in case -Os is not allowed -CFLAGS_OPTIMIZED ?= -Os - -# GCC Compiler Flags -GCC_CFLAGS += \ - -ggdb \ - -fdata-sections \ - -ffunction-sections \ - -fsingle-precision-constant \ - -fno-strict-aliasing \ - -Wall \ - -Wextra \ - -Werror \ - -Wfatal-errors \ - -Wdouble-promotion \ - -Wstrict-prototypes \ - -Wstrict-overflow \ - -Werror-implicit-function-declaration \ - -Wfloat-equal \ - -Wundef \ - -Wshadow \ - -Wwrite-strings \ - -Wsign-compare \ - -Wmissing-format-attribute \ - -Wunreachable-code \ - -Wcast-align \ - -Wcast-function-type \ - -Wcast-qual \ - -Wnull-dereference \ - -Wuninitialized \ - -Wunused \ - -Wreturn-type \ - -Wredundant-decls - -# conversion is too strict for most mcu driver, may be disable sign/int/arith-conversion -# -Wconversion - -# Debugging/Optimization -ifeq ($(DEBUG), 1) - GCC_CFLAGS += -O0 - NO_LTO = 1 -else - GCC_CFLAGS += $(CFLAGS_OPTIMIZED) -endif +SRC_C += $(TINYUSB_SRC_C) + +INC += \ + $(TOP)/$(FAMILY_PATH) \ + $(TOP)/src \ + # Log level is mapped to TUSB DEBUG option ifneq ($(LOG),) @@ -186,3 +136,6 @@ ifeq ($(LOGGER),rtt) else ifeq ($(LOGGER),swo) CFLAGS += -DLOGGER_SWO endif + +# toolchain specific +include $(TOP)/tools/make/toolchain/arm_$(TOOLCHAIN).mk diff --git a/examples/rules.mk b/examples/rules.mk index 5727ab7e3..e50c0ec7d 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -13,87 +13,8 @@ ifeq (,$(findstring $(FAMILY),espressif rp2040)) # Compiler Flags # --------------------------------------- -LIBS_GCC ?= -lgcc -lm -lnosys - -# libc -LIBS += $(LIBS_GCC) - -ifneq ($(BOARD), spresense) -LIBS += -lc -endif - -# TinyUSB Stack source -SRC_C += \ - src/tusb.c \ - src/common/tusb_fifo.c \ - src/device/usbd.c \ - src/device/usbd_control.c \ - src/typec/usbc.c \ - src/class/audio/audio_device.c \ - src/class/cdc/cdc_device.c \ - src/class/dfu/dfu_device.c \ - src/class/dfu/dfu_rt_device.c \ - src/class/hid/hid_device.c \ - src/class/midi/midi_device.c \ - src/class/msc/msc_device.c \ - src/class/net/ecm_rndis_device.c \ - src/class/net/ncm_device.c \ - src/class/usbtmc/usbtmc_device.c \ - src/class/video/video_device.c \ - src/class/vendor/vendor_device.c - -# TinyUSB stack include -INC += $(TOP)/src - CFLAGS += $(addprefix -I,$(INC)) -ifdef USE_IAR - -SRC_S += $(IAR_SRC_S) - -ASFLAGS := $(CFLAGS) $(IAR_ASFLAGS) $(ASFLAGS) -S -IAR_LDFLAGS += --config $(TOP)/$(IAR_LD_FILE) -CFLAGS += $(IAR_CFLAGS) -e --debug --silent - -else - -SRC_S += $(GCC_SRC_S) - -CFLAGS += $(GCC_CFLAGS) -MD - -# LTO makes it difficult to analyze map file for optimizing size purpose -# We will run this option in ci -ifeq ($(NO_LTO),1) -CFLAGS := $(filter-out -flto,$(CFLAGS)) -endif - -ifneq ($(CFLAGS_SKIP),) -CFLAGS := $(filter-out $(CFLAGS_SKIP),$(CFLAGS)) -endif - -LDFLAGS += $(CFLAGS) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections - -# Some toolchain such as renesas rx does not support --print-memory-usage flags -ifneq ($(FAMILY),rx) -LDFLAGS += -Wl,--print-memory-usage -endif - -ifdef LD_FILE -LDFLAGS += -Wl,-T,$(TOP)/$(LD_FILE) -endif - -ifdef GCC_LD_FILE -LDFLAGS += -Wl,-T,$(TOP)/$(GCC_LD_FILE) -endif - -ifneq ($(SKIP_NANOLIB), 1) -LDFLAGS += --specs=nosys.specs --specs=nano.specs -endif - -ASFLAGS += $(CFLAGS) - -endif # USE_IAR - # Verbose mode ifeq ("$(V)","1") $(info CFLAGS $(CFLAGS) ) $(info ) @@ -101,15 +22,6 @@ $(info LDFLAGS $(LDFLAGS)) $(info ) $(info ASFLAGS $(ASFLAGS)) $(info ) endif -# Assembly files can be name with upper case .S, convert it to .s -SRC_S := $(SRC_S:.S=.s) - -# Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966 -# assembly file should be placed first in linking order -# '_asm' suffix is added to object of assembly file -OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o)) -OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o)) - # --------------------------------------- # Rules # --------------------------------------- @@ -118,15 +30,6 @@ all: $(BUILD)/$(PROJECT).bin $(BUILD)/$(PROJECT).hex size uf2: $(BUILD)/$(PROJECT).uf2 -OBJ_DIRS = $(sort $(dir $(OBJ))) -$(OBJ): | $(OBJ_DIRS) -$(OBJ_DIRS): -ifeq ($(CMDEXE),1) - -@$(MKDIR) $(subst /,\,$@) -else - @$(MKDIR) -p $@ -endif - # We set vpath to point to the top of the tree so that the source files # can be located. By following this scheme, it allows a single build rule # to be used to compile all .c files. @@ -134,49 +37,16 @@ vpath %.c . $(TOP) vpath %.s . $(TOP) vpath %.S . $(TOP) -# Compile .c file -$(BUILD)/obj/%.o: %.c - @echo CC $(notdir $@) - @$(CC) $(CFLAGS) -c -o $@ $< - -# ASM sources lower case .s -$(BUILD)/obj/%_asm.o: %.s - @echo AS $(notdir $@) - @$(AS) $(ASFLAGS) -c -o $@ $< +include $(TOP)/tools/make/toolchain/arm_$(TOOLCHAIN)_rules.mk -# ASM sources upper case .S -$(BUILD)/obj/%_asm.o: %.S - @echo AS $(notdir $@) - @$(AS) $(ASFLAGS) -c -o $@ $< - -ifdef USE_IAR -# IAR Compiler -$(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf - @echo CREATE $@ - @$(OBJCOPY) --silent --bin $^ $@ - -$(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf - @echo CREATE $@ - @$(OBJCOPY) --silent --ihex $^ $@ - -$(BUILD)/$(PROJECT).elf: $(OBJ) - @echo LINK $@ - @$(LD) -o $@ $(IAR_LDFLAGS) $^ +OBJ_DIRS = $(sort $(dir $(OBJ))) +$(OBJ): | $(OBJ_DIRS) +$(OBJ_DIRS): +ifeq ($(CMDEXE),1) + -@$(MKDIR) $(subst /,\,$@) else -# GCC based compiler -$(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf - @echo CREATE $@ - @$(OBJCOPY) -O binary $^ $@ - -$(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf - @echo CREATE $@ - @$(OBJCOPY) -O ihex $^ $@ - -$(BUILD)/$(PROJECT).elf: $(OBJ) - @echo LINK $@ - @$(LD) -o $@ $(LDFLAGS) $^ -Wl,--start-group $(LIBS) -Wl,--end-group - + @$(MKDIR) -p $@ endif # UF2 generation, iMXRT need to strip to text only before conversion diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk index c11240207..48730bbb4 100644 --- a/hw/bsp/stm32h7/family.mk +++ b/hw/bsp/stm32h7/family.mk @@ -6,6 +6,7 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= cortex-m7 # -------------- # Compiler Flags @@ -29,20 +30,11 @@ endif # GCC Flags GCC_CFLAGS += \ -flto \ - -mthumb \ - -mabi=aapcs \ - -mcpu=cortex-m7 \ - -mfloat-abi=hard \ - -mfpu=fpv5-d16 \ -nostdlib -nostartfiles # suppress warning caused by vendor mcu driver GCC_CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align -Wno-error=unused-parameter -# IAR Flags -IAR_CFLAGS += --cpu cortex-m7 --fpu VFPv5_D16 -IAR_ASFLAGS += --cpu cortex-m7 --fpu VFPv5_D16 - # ----------------- # Sources & Include # ----------------- @@ -66,6 +58,3 @@ INC += \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(ST_CMSIS)/Include \ $(TOP)/$(ST_HAL_DRIVER)/Inc - -# For freeRTOS port source -FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1 diff --git a/src/tinyusb.mk b/src/tinyusb.mk new file mode 100644 index 000000000..85052f90f --- /dev/null +++ b/src/tinyusb.mk @@ -0,0 +1,19 @@ +# C source files +TINYUSB_SRC_C += \ + src/tusb.c \ + src/common/tusb_fifo.c \ + src/device/usbd.c \ + src/device/usbd_control.c \ + src/typec/usbc.c \ + src/class/audio/audio_device.c \ + src/class/cdc/cdc_device.c \ + src/class/dfu/dfu_device.c \ + src/class/dfu/dfu_rt_device.c \ + src/class/hid/hid_device.c \ + src/class/midi/midi_device.c \ + src/class/msc/msc_device.c \ + src/class/net/ecm_rndis_device.c \ + src/class/net/ncm_device.c \ + src/class/usbtmc/usbtmc_device.c \ + src/class/video/video_device.c \ + src/class/vendor/vendor_device.c \ diff --git a/tools/make/cpu/cortex-m7.mk b/tools/make/cpu/cortex-m7.mk index 504ffd486..0e53cbe9c 100644 --- a/tools/make/cpu/cortex-m7.mk +++ b/tools/make/cpu/cortex-m7.mk @@ -5,8 +5,15 @@ ifeq ($(TOOLCHAIN),gcc) -mfloat-abi=hard \ -mfpu=fpv5-d16 \ - #set(FREERTOS_PORT GCC_ARM_CM7 CACHE INTERNAL "") - FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1 else ifeq ($(TOOLCHAIN),iar) - # TODO support IAR + CFLAGS += \ + --cpu cortex-m7 \ + --fpu VFPv5_D16 \ + + ASFLAGS += \ + --cpu cortex-m7 \ + --fpu VFPv5_D16 \ + endif + +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1 diff --git a/tools/make/toolchain/arm_gcc.mk b/tools/make/toolchain/arm_gcc.mk new file mode 100644 index 000000000..d5ee98def --- /dev/null +++ b/tools/make/toolchain/arm_gcc.mk @@ -0,0 +1,77 @@ +# makefile for arm gcc toolchain + +CC = $(CROSS_COMPILE)gcc +CXX = $(CROSS_COMPILE)g++ +AS = $(CC) -x assembler-with-cpp +LD = $(CC) + +GDB = $(CROSS_COMPILE)gdb +OBJCOPY = $(CROSS_COMPILE)objcopy +SIZE = $(CROSS_COMPILE)size + +# CPU specific flags +include $(TOP)/tools/make/cpu/$(CPU_CORE).mk + +# --------------------------------------- +# Compiler Flags +# --------------------------------------- +CFLAGS += \ + -MD \ + -ggdb \ + -fdata-sections \ + -ffunction-sections \ + -fsingle-precision-constant \ + -fno-strict-aliasing \ + -Wall \ + -Wextra \ + -Werror \ + -Wfatal-errors \ + -Wdouble-promotion \ + -Wstrict-prototypes \ + -Wstrict-overflow \ + -Werror-implicit-function-declaration \ + -Wfloat-equal \ + -Wundef \ + -Wshadow \ + -Wwrite-strings \ + -Wsign-compare \ + -Wmissing-format-attribute \ + -Wunreachable-code \ + -Wcast-align \ + -Wcast-function-type \ + -Wcast-qual \ + -Wnull-dereference \ + -Wuninitialized \ + -Wunused \ + -Wreturn-type \ + -Wredundant-decls \ + +# conversion is too strict for most mcu driver, may be disable sign/int/arith-conversion +# -Wconversion + +# Size Optimization as default +CFLAGS_OPTIMIZED ?= -Os + +# Debugging/Optimization +ifeq ($(DEBUG), 1) + CFLAGS += -O0 + NO_LTO = 1 +else + CFLAGS += $(CFLAGS_OPTIMIZED) +endif + +# --------------------------------------- +# Linker Flags +# --------------------------------------- +LDFLAGS += \ + -Wl,-Map=$@.map \ + -Wl,-cref \ + -Wl,-gc-sections \ + +# Some toolchain such as renesas rx does not support --print-memory-usage flags +ifneq ($(FAMILY),rx) +LDFLAGS += -Wl,--print-memory-usage +endif + +LDFLAGS += \ + -Wl,--print-memory-usage \ diff --git a/tools/make/toolchain/arm_gcc_rules.mk b/tools/make/toolchain/arm_gcc_rules.mk new file mode 100644 index 000000000..a39caf351 --- /dev/null +++ b/tools/make/toolchain/arm_gcc_rules.mk @@ -0,0 +1,78 @@ +SRC_S += $(GCC_SRC_S) + +# Assembly files can be name with upper case .S, convert it to .s +SRC_S := $(SRC_S:.S=.s) + +# Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966 +# assembly file should be placed first in linking order +# '_asm' suffix is added to object of assembly file +OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o)) +OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o)) + +CFLAGS += $(GCC_CFLAGS) -MD + +# LTO makes it difficult to analyze map file for optimizing size purpose +# We will run this option in ci +ifeq ($(NO_LTO),1) +CFLAGS := $(filter-out -flto,$(CFLAGS)) +endif + +ifneq ($(CFLAGS_SKIP),) +CFLAGS := $(filter-out $(CFLAGS_SKIP),$(CFLAGS)) +endif + +LDFLAGS += $(CFLAGS) + +ifdef LD_FILE +LDFLAGS += -Wl,-T,$(TOP)/$(LD_FILE) +endif + +ifdef GCC_LD_FILE +LDFLAGS += -Wl,-T,$(TOP)/$(GCC_LD_FILE) +endif + +ifneq ($(SKIP_NANOLIB), 1) +LDFLAGS += --specs=nosys.specs --specs=nano.specs +endif + +ASFLAGS += $(CFLAGS) + +LIBS_GCC ?= -lgcc -lm -lnosys + +# libc +LIBS += $(LIBS_GCC) + +ifneq ($(BOARD), spresense) +LIBS += -lc +endif + +# --------------------------------------- +# Rules +# --------------------------------------- + +# Compile .c file +$(BUILD)/obj/%.o: %.c + @echo CC $(notdir $@) + @$(CC) $(CFLAGS) -c -o $@ $< + +# ASM sources lower case .s +$(BUILD)/obj/%_asm.o: %.s + @echo AS $(notdir $@) + @$(AS) $(ASFLAGS) -c -o $@ $< + +# ASM sources upper case .S +$(BUILD)/obj/%_asm.o: %.S + @echo AS $(notdir $@) + @$(AS) $(ASFLAGS) -c -o $@ $< + +$(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf + @echo CREATE $@ + @$(OBJCOPY) -O binary $^ $@ + +$(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf + @echo CREATE $@ + @$(OBJCOPY) -O ihex $^ $@ + +$(BUILD)/$(PROJECT).elf: $(OBJ) + @echo LINK $@ + @$(LD) -o $@ $(LDFLAGS) $^ -Wl,--start-group $(LIBS) -Wl,--end-group diff --git a/tools/make/toolchain/arm_iar.mk b/tools/make/toolchain/arm_iar.mk new file mode 100644 index 000000000..42b31cfd3 --- /dev/null +++ b/tools/make/toolchain/arm_iar.mk @@ -0,0 +1,13 @@ +# makefile for arm iar toolchain +AS = iasmarm +LD = ilinkarm +OBJCOPY = ielftool --silent +SIZE = size + +include $(TOP)/tools/make/cpu/$(CPU_CORE).mk + +# Enable extension mode (gcc compatible) +CFLAGS += -e --debug --silent + +# silent mode +ASFLAGS += -S diff --git a/tools/make/toolchain/arm_iar_rules.mk b/tools/make/toolchain/arm_iar_rules.mk new file mode 100644 index 000000000..4b5cc90e3 --- /dev/null +++ b/tools/make/toolchain/arm_iar_rules.mk @@ -0,0 +1,44 @@ +SRC_S += $(IAR_SRC_S) + +# Assembly files can be name with upper case .S, convert it to .s +SRC_S := $(SRC_S:.S=.s) + +# Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966 +# assembly file should be placed first in linking order +# '_asm' suffix is added to object of assembly file +OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o)) +OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o)) + +# Linker script +LDFLAGS += --config $(TOP)/$(IAR_LD_FILE) + +# --------------------------------------- +# Rules +# --------------------------------------- + +# Compile .c file +$(BUILD)/obj/%.o: %.c + @echo CC $(notdir $@) + @$(CC) $(CFLAGS) -c -o $@ $< + +# ASM sources lower case .s +$(BUILD)/obj/%_asm.o: %.s + @echo AS $(notdir $@) + @$(AS) $(ASFLAGS) -c -o $@ $< + +# ASM sources upper case .S +$(BUILD)/obj/%_asm.o: %.S + @echo AS $(notdir $@) + @$(AS) $(ASFLAGS) -c -o $@ $< + +$(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf + @echo CREATE $@ + @$(OBJCOPY) --bin $^ $@ + +$(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf + @echo CREATE $@ + @$(OBJCOPY) --ihex $^ $@ + +$(BUILD)/$(PROJECT).elf: $(OBJ) + @echo LINK $@ + @$(LD) -o $@ $(LDFLAGS) $^ -- cgit v1.3.1 From b59b65d2ed0f6fa14b18b7bc233309d9b9710898 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 24 Jun 2023 18:26:51 +0700 Subject: rename to kinetis_k32l2, rename OPT_MCU_KINETIS_K32 to OPT_MCU_KINETIS_K32L --- .github/workflows/build_arm.yml | 2 +- hw/bsp/board_mcu.h | 2 +- hw/bsp/imxrt/family.mk | 2 +- hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.h | 58 ------ hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.mk | 26 --- .../boards/frdm_k32l2a4s/frdm_k32l2a4s.c | 171 ---------------- hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.h | 56 ------ hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.mk | 26 --- .../kinetis_k32l/boards/frdm_k32l2b/frdm_k32l2b.c | 140 ------------- .../boards/kuiic/K32L2B31xxxxA_flash.ld | 216 --------------------- hw/bsp/kinetis_k32l/boards/kuiic/board.h | 45 ----- hw/bsp/kinetis_k32l/boards/kuiic/board.mk | 26 --- hw/bsp/kinetis_k32l/boards/kuiic/kuiic.c | 203 ------------------- hw/bsp/kinetis_k32l/family.mk | 32 --- hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h | 58 ++++++ hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk | 21 ++ .../boards/frdm_k32l2a4s/frdm_k32l2a4s.c | 171 ++++++++++++++++ hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h | 56 ++++++ hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk | 21 ++ .../kinetis_k32l2/boards/frdm_k32l2b/frdm_k32l2b.c | 140 +++++++++++++ .../boards/kuiic/K32L2B31xxxxA_flash.ld | 216 +++++++++++++++++++++ hw/bsp/kinetis_k32l2/boards/kuiic/board.h | 45 +++++ hw/bsp/kinetis_k32l2/boards/kuiic/board.mk | 18 ++ hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c | 203 +++++++++++++++++++ hw/bsp/kinetis_k32l2/family.mk | 32 +++ src/common/tusb_mcu.h | 2 +- src/tusb_option.h | 3 +- tools/get_deps.py | 4 +- 28 files changed, 989 insertions(+), 1006 deletions(-) delete mode 100644 hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.h delete mode 100644 hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.mk delete mode 100644 hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/frdm_k32l2a4s.c delete mode 100644 hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.h delete mode 100644 hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.mk delete mode 100644 hw/bsp/kinetis_k32l/boards/frdm_k32l2b/frdm_k32l2b.c delete mode 100644 hw/bsp/kinetis_k32l/boards/kuiic/K32L2B31xxxxA_flash.ld delete mode 100644 hw/bsp/kinetis_k32l/boards/kuiic/board.h delete mode 100644 hw/bsp/kinetis_k32l/boards/kuiic/board.mk delete mode 100644 hw/bsp/kinetis_k32l/boards/kuiic/kuiic.c delete mode 100644 hw/bsp/kinetis_k32l/family.mk create mode 100644 hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h create mode 100644 hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk create mode 100644 hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/frdm_k32l2a4s.c create mode 100644 hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h create mode 100644 hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk create mode 100644 hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/frdm_k32l2b.c create mode 100644 hw/bsp/kinetis_k32l2/boards/kuiic/K32L2B31xxxxA_flash.ld create mode 100644 hw/bsp/kinetis_k32l2/boards/kuiic/board.h create mode 100644 hw/bsp/kinetis_k32l2/boards/kuiic/board.mk create mode 100644 hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c create mode 100644 hw/bsp/kinetis_k32l2/family.mk (limited to 'src') diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml index a7c7fd1e1..620aec193 100644 --- a/.github/workflows/build_arm.yml +++ b/.github/workflows/build_arm.yml @@ -34,7 +34,7 @@ jobs: family: # Alphabetical order - 'broadcom_32bit' - - 'kinetis_k32l kinetis_kl' + - 'kinetis_k32l2 kinetis_kl' - 'lpc11 lpc13 lpc15 lpc17' - 'lpc51 lpc54 lpc55' - 'mm32 msp432e4' diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index ce2f919bf..e5d2bb608 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -47,7 +47,7 @@ #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX, OPT_MCU_MCXN9) #include "fsl_device_registers.h" -#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32) +#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L) #include "fsl_device_registers.h" #elif CFG_TUSB_MCU == OPT_MCU_NRF5X diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk index d0bb5be17..9eb541473 100644 --- a/hw/bsp/imxrt/family.mk +++ b/hw/bsp/imxrt/family.mk @@ -5,7 +5,6 @@ DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5 include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m7 -include $(TOP)/tools/make/cpu/$(CPU_CORE).mk CFLAGS += \ -D__ARMVFP__=0 \ @@ -17,6 +16,7 @@ CFLAGS += \ ifdef BOARD_TUD_RHPORT CFLAGS += -DBOARD_TUD_RHPORT=$(BOARD_TUD_RHPORT) endif + ifdef BOARD_TUH_RHPORT CFLAGS += -DBOARD_TUH_RHPORT=$(BOARD_TUH_RHPORT) endif diff --git a/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.h b/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.h deleted file mode 100644 index b1f38c997..000000000 --- a/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "fsl_device_registers.h" - -// LED -// The Red LED is on PTE29. -// The Green LED is on PTC4. -// The Blue LED is on PTE31. -#define LED_PIN_CLOCK kCLOCK_PortC -#define LED_GPIO GPIOC -#define LED_PORT PORTC -#define LED_PIN 4 -#define LED_STATE_ON 0 - -// SW3 button1 -#define BUTTON_PIN_CLOCK kCLOCK_PortE -#define BUTTON_GPIO GPIOE -#define BUTTON_PORT PORTE -#define BUTTON_PIN 4 -#define BUTTON_STATE_ACTIVE 0 - -// UART -#define UART_PORT LPUART0 -#define UART_PIN_CLOCK kCLOCK_PortB -#define UART_PIN_GPIO GPIOB -#define UART_PIN_PORT PORTB -#define UART_PIN_RX 16u -#define UART_PIN_TX 17u - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.mk deleted file mode 100644 index d96ab58b8..000000000 --- a/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.mk +++ /dev/null @@ -1,26 +0,0 @@ -MCU = K32L2A41A - -CFLAGS += \ - -mcpu=cortex-m0plus \ - -DCPU_K32L2A41VLH1A \ - -# mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual - -# All source paths should be relative to the top level. -LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld - -SRC_C += \ - $(MCU_DIR)/project_template/clock_config.c \ - -# For freeRTOS port source -FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 - -# For flash-jlink target -JLINK_DEVICE = K32L2A41xxxxA - -# For flash-pyocd target -PYOCD_TARGET = K32L2A - -# flash using pyocd -flash: flash-pyocd diff --git a/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/frdm_k32l2a4s.c b/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/frdm_k32l2a4s.c deleted file mode 100644 index 80830163b..000000000 --- a/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/frdm_k32l2a4s.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2018, hathach (tinyusb.org) - * Copyright (c) 2020, Koji Kitayama - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "bsp/board.h" -#include "board.h" -#include "fsl_gpio.h" -#include "fsl_port.h" -#include "fsl_clock.h" -#include "fsl_lpuart.h" - -#include "clock_config.h" - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB0_IRQHandler(void) -{ - tud_int_handler(0); -} - -void board_init(void) -{ - /* Enable port clocks for UART/LED/Button pins */ - CLOCK_EnableClock(UART_PIN_CLOCK); - CLOCK_EnableClock(LED_PIN_CLOCK); - CLOCK_EnableClock(BUTTON_PIN_CLOCK); - - gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; - GPIO_PinInit(LED_GPIO, LED_PIN, &led_config); - PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio); - - gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; - GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); - const port_pin_config_t BUTTON_CFG = { - kPORT_PullUp, - kPORT_FastSlewRate, - kPORT_PassiveFilterDisable, - kPORT_OpenDrainDisable, - kPORT_LowDriveStrength, - kPORT_MuxAsGpio, - kPORT_UnlockRegister - }; - PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); - - /* - Enable LPUART0 clock and configure port pins. - FIR clock is being used so the USB examples work. - */ - PCC_LPUART0 = 0U; /* Clock must be off to set PCS */ - PCC_LPUART0 = PCC_CLKCFG_PCS( 3U ); /* Select the clock. 1:OSCCLK/Bus Clock, 2:Slow IRC, 3: Fast IRC, 6: System PLL */ - PCC_LPUART0 |= PCC_CLKCFG_CGC( 1U ); /* Enable LPUART */ - - /* PORTB16 (pin 62) is configured as LPUART0_RX */ - gpio_pin_config_t const lpuart_config_rx = { kGPIO_DigitalInput, 0 }; - GPIO_PinInit(UART_PIN_GPIO, UART_PIN_RX, &lpuart_config_rx); - const port_pin_config_t UART_CFG = { - kPORT_PullUp, - kPORT_FastSlewRate, - kPORT_PassiveFilterDisable, - kPORT_OpenDrainDisable, - kPORT_LowDriveStrength, - kPORT_MuxAsGpio, - kPORT_UnlockRegister - }; - PORT_SetPinConfig(UART_PIN_PORT, UART_PIN_RX, &UART_CFG); - PORT_SetPinMux( UART_PIN_PORT, UART_PIN_RX, kPORT_MuxAlt3); - - /* PORTB17 (pin 63) is configured as LPUART0_TX */ - gpio_pin_config_t const lpuart_config_tx = { kGPIO_DigitalOutput, 0 }; - GPIO_PinInit( UART_PIN_GPIO, UART_PIN_TX, &lpuart_config_tx); - PORT_SetPinMux( UART_PIN_PORT, UART_PIN_TX, kPORT_MuxAlt3); - - BOARD_BootClockRUN(); - SystemCoreClockUpdate(); - -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); -#endif - - lpuart_config_t uart_config; - LPUART_GetDefaultConfig(&uart_config); - uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; - uart_config.enableTx = true; - uart_config.enableRx = true; - LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_ScgFircClk)); - - // USB - CLOCK_EnableUsbfs0Clock(kCLOCK_IpSrcFircAsync, 48000000U); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); -} - -uint32_t board_button_read(void) -{ - return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); -} - -int board_uart_read(uint8_t* buf, int len) -{ -#if 0 /* - Use this version if want the LED to blink during BOARD=board_test, - without having to hit a key. - */ - if( 0U != (kLPUART_RxDataRegFullFlag & LPUART_GetStatusFlags( UART_PORT )) ) - { - LPUART_ReadBlocking(UART_PORT, buf, len); - return len; - } - - return( 0 ); -#else /* Wait for 'len' characters to come in */ - - LPUART_ReadBlocking(UART_PORT, buf, len); - return len; - -#endif -} - -int board_uart_write(void const * buf, int len) -{ - LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler(void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#endif diff --git a/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.h b/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.h deleted file mode 100644 index 8d21fdcd4..000000000 --- a/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "fsl_device_registers.h" - -// LED -#define LED_PIN_CLOCK kCLOCK_PortD -#define LED_GPIO GPIOD -#define LED_PORT PORTD -#define LED_PIN 5 -#define LED_STATE_ON 0 - -// SW3 button1 -#define BUTTON_PIN_CLOCK kCLOCK_PortC -#define BUTTON_GPIO GPIOC -#define BUTTON_PORT PORTC -#define BUTTON_PIN 3 -#define BUTTON_STATE_ACTIVE 0 - -// UART -#define UART_PORT LPUART0 -#define UART_PIN_CLOCK kCLOCK_PortA -#define UART_PIN_PORT PORTA -#define UART_PIN_RX 1u -#define UART_PIN_TX 2u -#define SOPT5_LPUART0RXSRC_LPUART_RX 0x00u /*!<@brief LPUART0 Receive Data Source Select: LPUART_RX pin */ -#define SOPT5_LPUART0TXSRC_LPUART_TX 0x00u /*!<@brief LPUART0 Transmit Data Source Select: LPUART0_TX pin */ - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.mk b/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.mk deleted file mode 100644 index 5f8ecbfe4..000000000 --- a/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.mk +++ /dev/null @@ -1,26 +0,0 @@ -MCU = K32L2B31A - -CFLAGS += \ - -mcpu=cortex-m0plus \ - -DCPU_K32L2B31VLH0A \ - -# mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls - -# All source paths should be relative to the top level. -LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld - -SRC_C += \ - $(MCU_DIR)/project_template/clock_config.c \ - -# For freeRTOS port source -FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 - -# For flash-jlink target -JLINK_DEVICE = K32L2B31xxxxA - -# For flash-pyocd target -PYOCD_TARGET = K32L2B - -# flash using pyocd -flash: flash-pyocd diff --git a/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/frdm_k32l2b.c deleted file mode 100644 index 1566b4e2e..000000000 --- a/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/frdm_k32l2b.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2018, hathach (tinyusb.org) - * Copyright (c) 2020, Koji Kitayama - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "bsp/board.h" -#include "board.h" -#include "fsl_gpio.h" -#include "fsl_port.h" -#include "fsl_clock.h" -#include "fsl_lpuart.h" - -#include "clock_config.h" - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB0_IRQHandler(void) -{ - tud_int_handler(0); -} - -void board_init(void) -{ - /* Enable port clocks for UART/LED/Button pins */ - CLOCK_EnableClock(UART_PIN_CLOCK); - CLOCK_EnableClock(LED_PIN_CLOCK); - CLOCK_EnableClock(BUTTON_PIN_CLOCK); - - gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; - GPIO_PinInit(LED_GPIO, LED_PIN, &led_config); - PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio); - - gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; - GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); - const port_pin_config_t BUTTON_CFG = { - kPORT_PullUp, - kPORT_FastSlewRate, - kPORT_PassiveFilterDisable, - kPORT_LowDriveStrength, - kPORT_MuxAsGpio - }; - PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); - - /* PORTA1 (pin 23) is configured as LPUART0_RX */ - PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2); - /* PORTA2 (pin 24) is configured as LPUART0_TX */ - PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2); - - SIM->SOPT5 = ((SIM->SOPT5 & - /* Mask bits to zero which are setting */ - (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK))) - /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */ - | SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX) - /* LPUART0 Receive Data Source Select: LPUART_RX pin. */ - | SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX)); - - BOARD_BootClockRUN(); - SystemCoreClockUpdate(); - CLOCK_SetLpuart0Clock(1); - -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); -#endif - - lpuart_config_t uart_config; - LPUART_GetDefaultConfig(&uart_config); - uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; - uart_config.enableTx = true; - uart_config.enableRx = true; - LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk)); - - // USB - CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); -} - -uint32_t board_button_read(void) -{ - return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); -} - -int board_uart_read(uint8_t* buf, int len) -{ - LPUART_ReadBlocking(UART_PORT, buf, len); - return len; -} - -int board_uart_write(void const * buf, int len) -{ - LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler(void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#endif diff --git a/hw/bsp/kinetis_k32l/boards/kuiic/K32L2B31xxxxA_flash.ld b/hw/bsp/kinetis_k32l/boards/kuiic/K32L2B31xxxxA_flash.ld deleted file mode 100644 index f478a99c7..000000000 --- a/hw/bsp/kinetis_k32l/boards/kuiic/K32L2B31xxxxA_flash.ld +++ /dev/null @@ -1,216 +0,0 @@ -/* -** ################################################################### -** Processors: K32L2B31VFM0A -** K32L2B31VFT0A -** K32L2B31VLH0A -** K32L2B31VMP0A -** -** Compiler: GNU C Compiler -** Reference manual: K32L2B3xRM, Rev.0, July 2019 -** Version: rev. 1.0, 2019-07-30 -** Build: b190930 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x00008000, LENGTH = 0x00000200 - m_flash_config (RX) : ORIGIN = 0x00008400, LENGTH = 0x00000010 - m_text (RX) : ORIGIN = 0x00008410, LENGTH = 0x00037BF0 - m_data (RW) : ORIGIN = 0x1FFFE000, LENGTH = 0x00008000 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - .flash_config : - { - . = ALIGN(4); - KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ - . = ALIGN(4); - } > m_flash_config - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - /* reserve MTB memory at the beginning of m_data */ - .mtb : /* MTB buffer address as defined by the hardware */ - { - . = ALIGN(8); - _mtb_start = .; - KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */ - . = ALIGN(8); - _mtb_end = .; - } > m_data - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} diff --git a/hw/bsp/kinetis_k32l/boards/kuiic/board.h b/hw/bsp/kinetis_k32l/boards/kuiic/board.h deleted file mode 100644 index 1e2d4f18b..000000000 --- a/hw/bsp/kinetis_k32l/boards/kuiic/board.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "fsl_device_registers.h" - -// LED -#define LED_PIN_CLOCK kCLOCK_PortA -#define LED_GPIO GPIOA -#define LED_PORT PORTA -#define LED_PIN 2 -#define LED_STATE_ON 1 - -// UART -#define UART_PORT LPUART1 -#define UART_PIN_RX 3u -#define UART_PIN_TX 0u - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/kinetis_k32l/boards/kuiic/board.mk b/hw/bsp/kinetis_k32l/boards/kuiic/board.mk deleted file mode 100644 index 29a12e982..000000000 --- a/hw/bsp/kinetis_k32l/boards/kuiic/board.mk +++ /dev/null @@ -1,26 +0,0 @@ -MCU = K32L2B31A - -# This board uses TinyUF2 for updates -UF2_FAMILY_ID = 0x7f83e793 - -CFLAGS += \ - -mcpu=cortex-m0plus \ - -DCPU_K32L2B31VLH0A \ - -# mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls - -# All source paths should be relative to the top level. -LD_FILE = $(BOARD_PATH)/K32L2B31xxxxA_flash.ld - -# For freeRTOS port source -FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0 - -# For flash-jlink target -JLINK_DEVICE = K32L2B31xxxxA - -# For flash-pyocd target -PYOCD_TARGET = K32L2B - -# flash using pyocd -flash: flash-pyocd diff --git a/hw/bsp/kinetis_k32l/boards/kuiic/kuiic.c b/hw/bsp/kinetis_k32l/boards/kuiic/kuiic.c deleted file mode 100644 index f9002a6d3..000000000 --- a/hw/bsp/kinetis_k32l/boards/kuiic/kuiic.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2018, hathach (tinyusb.org) - * Copyright (c) 2020, Koji Kitayama - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "bsp/board.h" -#include "board.h" -#include "fsl_smc.h" -#include "fsl_gpio.h" -#include "fsl_port.h" -#include "fsl_clock.h" -#include "fsl_lpuart.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */ -#define SOPT5_LPUART1RXSRC_LPUART_RX 0x00u /*!<@brief LPUART1 Receive Data Source Select: LPUART_RX pin */ -#define SOPT5_LPUART1TXSRC_LPUART_TX 0x00u /*!<@brief LPUART1 Transmit Data Source Select: LPUART_TX pin */ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -// extern uint32_t SystemCoreClock; - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = { - .outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */ - .irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ - .ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock selected */ - .fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */ - .lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */ - .hircEnableInNotHircMode = true, /* HIRC source is enabled */ -}; -const sim_clock_config_t simConfig_BOARD_BootClockRUN = { - .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */ - .clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */ -}; - -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Set the system clock dividers in SIM to safe value. */ - CLOCK_SetSimSafeDivs(); - /* Set MCG to HIRC mode. */ - CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN); - /* Set the clock configuration in SIM module. */ - CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; -} - - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB0_IRQHandler(void) -{ - tud_int_handler(0); -} - -void board_init(void) -{ - /* Enable port clocks for GPIO pins */ - CLOCK_EnableClock(kCLOCK_PortA); - CLOCK_EnableClock(kCLOCK_PortB); - CLOCK_EnableClock(kCLOCK_PortC); - CLOCK_EnableClock(kCLOCK_PortD); - CLOCK_EnableClock(kCLOCK_PortE); - - - gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 1 }; - GPIO_PinInit(GPIOA, 1U, &led_config); - PORT_SetPinMux(PORTA, 1U, kPORT_MuxAsGpio); - led_config.outputLogic = 0; - GPIO_PinInit(GPIOA, 2U, &led_config); - PORT_SetPinMux(PORTA, 2U, kPORT_MuxAsGpio); - -#ifdef BUTTON_PIN - gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; - GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); - const port_pin_config_t BUTTON_CFG = { - kPORT_PullUp, - kPORT_FastSlewRate, - kPORT_PassiveFilterDisable, - kPORT_LowDriveStrength, - kPORT_MuxAsGpio - }; - PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); -#endif - - /* PORTC3 is configured as LPUART0_RX */ - PORT_SetPinMux(PORTC, 3U, kPORT_MuxAlt3); - /* PORTA2 (pin 24) is configured as LPUART0_TX */ - PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3); - - SIM->SOPT5 = ((SIM->SOPT5 & - /* Mask bits to zero which are setting */ - (~(SIM_SOPT5_LPUART1TXSRC_MASK | SIM_SOPT5_LPUART1RXSRC_MASK))) - /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */ - | SIM_SOPT5_LPUART1TXSRC(SOPT5_LPUART1TXSRC_LPUART_TX) - /* LPUART0 Receive Data Source Select: LPUART_RX pin. */ - | SIM_SOPT5_LPUART1RXSRC(SOPT5_LPUART1RXSRC_LPUART_RX)); - - BOARD_BootClockRUN(); - SystemCoreClockUpdate(); - CLOCK_SetLpuart1Clock(1); - -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); -#endif - - lpuart_config_t uart_config; - LPUART_GetDefaultConfig(&uart_config); - uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; - uart_config.enableTx = true; - uart_config.enableRx = true; - LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk)); - - // USB - CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - if (state) { - LED_GPIO->PDDR |= GPIO_FIT_REG((1UL << LED_PIN)); - } else { - LED_GPIO->PDDR &= GPIO_FIT_REG(~(1UL << LED_PIN)); - } -// GPIO_PinWrite(GPIOA, 1, state ? LED_STATE_ON : (1-LED_STATE_ON) ); -// GPIO_PinWrite(GPIOA, 2, state ? (1-LED_STATE_ON) : LED_STATE_ON ); -} - -uint32_t board_button_read(void) -{ -#ifdef BUTTON_PIN - return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); -#else - return 0; -#endif -} - -int board_uart_read(uint8_t* buf, int len) -{ - LPUART_ReadBlocking(UART_PORT, buf, len); - return len; -} - -int board_uart_write(void const * buf, int len) -{ - LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler(void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#endif diff --git a/hw/bsp/kinetis_k32l/family.mk b/hw/bsp/kinetis_k32l/family.mk deleted file mode 100644 index 41f22e250..000000000 --- a/hw/bsp/kinetis_k32l/family.mk +++ /dev/null @@ -1,32 +0,0 @@ -SDK_DIR = hw/mcu/nxp/mcux-sdk -DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5 - -MCU_DIR = $(SDK_DIR)/devices/$(MCU) -include $(TOP)/$(BOARD_PATH)/board.mk - -CFLAGS += \ - -mthumb \ - -mabi=aapcs \ - -DCFG_TUSB_MCU=OPT_MCU_KINETIS_K32 - -SRC_C += \ - src/portable/nxp/khci/dcd_khci.c \ - src/portable/nxp/khci/hcd_khci.c \ - $(MCU_DIR)/system_$(MCU).c \ - $(MCU_DIR)/drivers/fsl_clock.c \ - $(SDK_DIR)/drivers/gpio/fsl_gpio.c \ - $(SDK_DIR)/drivers/lpuart/fsl_lpuart.c - -INC += \ - $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ - $(TOP)/$(MCU_DIR) \ - $(TOP)/$(MCU_DIR)/project_template \ - $(TOP)/$(MCU_DIR)/drivers \ - $(TOP)/$(SDK_DIR)/drivers/smc \ - $(TOP)/$(SDK_DIR)/drivers/common \ - $(TOP)/$(SDK_DIR)/drivers/gpio \ - $(TOP)/$(SDK_DIR)/drivers/port \ - $(TOP)/$(SDK_DIR)/drivers/lpuart \ - -SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h new file mode 100644 index 000000000..b1f38c997 --- /dev/null +++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h @@ -0,0 +1,58 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "fsl_device_registers.h" + +// LED +// The Red LED is on PTE29. +// The Green LED is on PTC4. +// The Blue LED is on PTE31. +#define LED_PIN_CLOCK kCLOCK_PortC +#define LED_GPIO GPIOC +#define LED_PORT PORTC +#define LED_PIN 4 +#define LED_STATE_ON 0 + +// SW3 button1 +#define BUTTON_PIN_CLOCK kCLOCK_PortE +#define BUTTON_GPIO GPIOE +#define BUTTON_PORT PORTE +#define BUTTON_PIN 4 +#define BUTTON_STATE_ACTIVE 0 + +// UART +#define UART_PORT LPUART0 +#define UART_PIN_CLOCK kCLOCK_PortB +#define UART_PIN_GPIO GPIOB +#define UART_PIN_PORT PORTB +#define UART_PIN_RX 16u +#define UART_PIN_TX 17u + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk new file mode 100644 index 000000000..f69700139 --- /dev/null +++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk @@ -0,0 +1,21 @@ +MCU = K32L2A41A + +CFLAGS += -DCPU_K32L2A41VLH1A + +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual + +# All source paths should be relative to the top level. +LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld + +SRC_C += \ + $(MCU_DIR)/project_template/clock_config.c \ + +# For flash-jlink target +JLINK_DEVICE = K32L2A41xxxxA + +# For flash-pyocd target +PYOCD_TARGET = K32L2A + +# flash using pyocd +flash: flash-pyocd diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/frdm_k32l2a4s.c b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/frdm_k32l2a4s.c new file mode 100644 index 000000000..80830163b --- /dev/null +++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/frdm_k32l2a4s.c @@ -0,0 +1,171 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2018, hathach (tinyusb.org) + * Copyright (c) 2020, Koji Kitayama + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "bsp/board.h" +#include "board.h" +#include "fsl_gpio.h" +#include "fsl_port.h" +#include "fsl_clock.h" +#include "fsl_lpuart.h" + +#include "clock_config.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB0_IRQHandler(void) +{ + tud_int_handler(0); +} + +void board_init(void) +{ + /* Enable port clocks for UART/LED/Button pins */ + CLOCK_EnableClock(UART_PIN_CLOCK); + CLOCK_EnableClock(LED_PIN_CLOCK); + CLOCK_EnableClock(BUTTON_PIN_CLOCK); + + gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; + GPIO_PinInit(LED_GPIO, LED_PIN, &led_config); + PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio); + + gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); + const port_pin_config_t BUTTON_CFG = { + kPORT_PullUp, + kPORT_FastSlewRate, + kPORT_PassiveFilterDisable, + kPORT_OpenDrainDisable, + kPORT_LowDriveStrength, + kPORT_MuxAsGpio, + kPORT_UnlockRegister + }; + PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); + + /* + Enable LPUART0 clock and configure port pins. + FIR clock is being used so the USB examples work. + */ + PCC_LPUART0 = 0U; /* Clock must be off to set PCS */ + PCC_LPUART0 = PCC_CLKCFG_PCS( 3U ); /* Select the clock. 1:OSCCLK/Bus Clock, 2:Slow IRC, 3: Fast IRC, 6: System PLL */ + PCC_LPUART0 |= PCC_CLKCFG_CGC( 1U ); /* Enable LPUART */ + + /* PORTB16 (pin 62) is configured as LPUART0_RX */ + gpio_pin_config_t const lpuart_config_rx = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(UART_PIN_GPIO, UART_PIN_RX, &lpuart_config_rx); + const port_pin_config_t UART_CFG = { + kPORT_PullUp, + kPORT_FastSlewRate, + kPORT_PassiveFilterDisable, + kPORT_OpenDrainDisable, + kPORT_LowDriveStrength, + kPORT_MuxAsGpio, + kPORT_UnlockRegister + }; + PORT_SetPinConfig(UART_PIN_PORT, UART_PIN_RX, &UART_CFG); + PORT_SetPinMux( UART_PIN_PORT, UART_PIN_RX, kPORT_MuxAlt3); + + /* PORTB17 (pin 63) is configured as LPUART0_TX */ + gpio_pin_config_t const lpuart_config_tx = { kGPIO_DigitalOutput, 0 }; + GPIO_PinInit( UART_PIN_GPIO, UART_PIN_TX, &lpuart_config_tx); + PORT_SetPinMux( UART_PIN_PORT, UART_PIN_TX, kPORT_MuxAlt3); + + BOARD_BootClockRUN(); + SystemCoreClockUpdate(); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + lpuart_config_t uart_config; + LPUART_GetDefaultConfig(&uart_config); + uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; + uart_config.enableTx = true; + uart_config.enableRx = true; + LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_ScgFircClk)); + + // USB + CLOCK_EnableUsbfs0Clock(kCLOCK_IpSrcFircAsync, 48000000U); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); +} + +int board_uart_read(uint8_t* buf, int len) +{ +#if 0 /* + Use this version if want the LED to blink during BOARD=board_test, + without having to hit a key. + */ + if( 0U != (kLPUART_RxDataRegFullFlag & LPUART_GetStatusFlags( UART_PORT )) ) + { + LPUART_ReadBlocking(UART_PORT, buf, len); + return len; + } + + return( 0 ); +#else /* Wait for 'len' characters to come in */ + + LPUART_ReadBlocking(UART_PORT, buf, len); + return len; + +#endif +} + +int board_uart_write(void const * buf, int len) +{ + LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h new file mode 100644 index 000000000..8d21fdcd4 --- /dev/null +++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h @@ -0,0 +1,56 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "fsl_device_registers.h" + +// LED +#define LED_PIN_CLOCK kCLOCK_PortD +#define LED_GPIO GPIOD +#define LED_PORT PORTD +#define LED_PIN 5 +#define LED_STATE_ON 0 + +// SW3 button1 +#define BUTTON_PIN_CLOCK kCLOCK_PortC +#define BUTTON_GPIO GPIOC +#define BUTTON_PORT PORTC +#define BUTTON_PIN 3 +#define BUTTON_STATE_ACTIVE 0 + +// UART +#define UART_PORT LPUART0 +#define UART_PIN_CLOCK kCLOCK_PortA +#define UART_PIN_PORT PORTA +#define UART_PIN_RX 1u +#define UART_PIN_TX 2u +#define SOPT5_LPUART0RXSRC_LPUART_RX 0x00u /*!<@brief LPUART0 Receive Data Source Select: LPUART_RX pin */ +#define SOPT5_LPUART0TXSRC_LPUART_TX 0x00u /*!<@brief LPUART0 Transmit Data Source Select: LPUART0_TX pin */ + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk new file mode 100644 index 000000000..82456b721 --- /dev/null +++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk @@ -0,0 +1,21 @@ +MCU = K32L2B31A + +CFLAGS += -DCPU_K32L2B31VLH0A + +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls + +# All source paths should be relative to the top level. +LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld + +SRC_C += \ + $(MCU_DIR)/project_template/clock_config.c \ + +# For flash-jlink target +JLINK_DEVICE = K32L2B31xxxxA + +# For flash-pyocd target +PYOCD_TARGET = K32L2B + +# flash using pyocd +flash: flash-pyocd diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/frdm_k32l2b.c new file mode 100644 index 000000000..1566b4e2e --- /dev/null +++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/frdm_k32l2b.c @@ -0,0 +1,140 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2018, hathach (tinyusb.org) + * Copyright (c) 2020, Koji Kitayama + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "bsp/board.h" +#include "board.h" +#include "fsl_gpio.h" +#include "fsl_port.h" +#include "fsl_clock.h" +#include "fsl_lpuart.h" + +#include "clock_config.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB0_IRQHandler(void) +{ + tud_int_handler(0); +} + +void board_init(void) +{ + /* Enable port clocks for UART/LED/Button pins */ + CLOCK_EnableClock(UART_PIN_CLOCK); + CLOCK_EnableClock(LED_PIN_CLOCK); + CLOCK_EnableClock(BUTTON_PIN_CLOCK); + + gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; + GPIO_PinInit(LED_GPIO, LED_PIN, &led_config); + PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio); + + gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); + const port_pin_config_t BUTTON_CFG = { + kPORT_PullUp, + kPORT_FastSlewRate, + kPORT_PassiveFilterDisable, + kPORT_LowDriveStrength, + kPORT_MuxAsGpio + }; + PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); + + /* PORTA1 (pin 23) is configured as LPUART0_RX */ + PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2); + /* PORTA2 (pin 24) is configured as LPUART0_TX */ + PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2); + + SIM->SOPT5 = ((SIM->SOPT5 & + /* Mask bits to zero which are setting */ + (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK))) + /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */ + | SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX) + /* LPUART0 Receive Data Source Select: LPUART_RX pin. */ + | SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX)); + + BOARD_BootClockRUN(); + SystemCoreClockUpdate(); + CLOCK_SetLpuart0Clock(1); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + lpuart_config_t uart_config; + LPUART_GetDefaultConfig(&uart_config); + uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; + uart_config.enableTx = true; + uart_config.enableRx = true; + LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk)); + + // USB + CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); +} + +int board_uart_read(uint8_t* buf, int len) +{ + LPUART_ReadBlocking(UART_PORT, buf, len); + return len; +} + +int board_uart_write(void const * buf, int len) +{ + LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/K32L2B31xxxxA_flash.ld b/hw/bsp/kinetis_k32l2/boards/kuiic/K32L2B31xxxxA_flash.ld new file mode 100644 index 000000000..f478a99c7 --- /dev/null +++ b/hw/bsp/kinetis_k32l2/boards/kuiic/K32L2B31xxxxA_flash.ld @@ -0,0 +1,216 @@ +/* +** ################################################################### +** Processors: K32L2B31VFM0A +** K32L2B31VFT0A +** K32L2B31VLH0A +** K32L2B31VMP0A +** +** Compiler: GNU C Compiler +** Reference manual: K32L2B3xRM, Rev.0, July 2019 +** Version: rev. 1.0, 2019-07-30 +** Build: b190930 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00008000, LENGTH = 0x00000200 + m_flash_config (RX) : ORIGIN = 0x00008400, LENGTH = 0x00000010 + m_text (RX) : ORIGIN = 0x00008410, LENGTH = 0x00037BF0 + m_data (RW) : ORIGIN = 0x1FFFE000, LENGTH = 0x00008000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .flash_config : + { + . = ALIGN(4); + KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_flash_config + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + /* reserve MTB memory at the beginning of m_data */ + .mtb : /* MTB buffer address as defined by the hardware */ + { + . = ALIGN(8); + _mtb_start = .; + KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */ + . = ALIGN(8); + _mtb_end = .; + } > m_data + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/board.h b/hw/bsp/kinetis_k32l2/boards/kuiic/board.h new file mode 100644 index 000000000..1e2d4f18b --- /dev/null +++ b/hw/bsp/kinetis_k32l2/boards/kuiic/board.h @@ -0,0 +1,45 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "fsl_device_registers.h" + +// LED +#define LED_PIN_CLOCK kCLOCK_PortA +#define LED_GPIO GPIOA +#define LED_PORT PORTA +#define LED_PIN 2 +#define LED_STATE_ON 1 + +// UART +#define UART_PORT LPUART1 +#define UART_PIN_RX 3u +#define UART_PIN_TX 0u + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/board.mk b/hw/bsp/kinetis_k32l2/boards/kuiic/board.mk new file mode 100644 index 000000000..fc5bdeec8 --- /dev/null +++ b/hw/bsp/kinetis_k32l2/boards/kuiic/board.mk @@ -0,0 +1,18 @@ +MCU = K32L2B31A + +CFLAGS += -DCPU_K32L2B31VLH0A + +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls + +# All source paths should be relative to the top level. +LD_FILE = $(BOARD_PATH)/K32L2B31xxxxA_flash.ld + +# For flash-jlink target +JLINK_DEVICE = K32L2B31xxxxA + +# For flash-pyocd target +PYOCD_TARGET = K32L2B + +# flash using pyocd +flash: flash-pyocd diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c b/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c new file mode 100644 index 000000000..f9002a6d3 --- /dev/null +++ b/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c @@ -0,0 +1,203 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2018, hathach (tinyusb.org) + * Copyright (c) 2020, Koji Kitayama + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "bsp/board.h" +#include "board.h" +#include "fsl_smc.h" +#include "fsl_gpio.h" +#include "fsl_port.h" +#include "fsl_clock.h" +#include "fsl_lpuart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */ +#define SOPT5_LPUART1RXSRC_LPUART_RX 0x00u /*!<@brief LPUART1 Receive Data Source Select: LPUART_RX pin */ +#define SOPT5_LPUART1TXSRC_LPUART_TX 0x00u /*!<@brief LPUART1 Transmit Data Source Select: LPUART_TX pin */ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +// extern uint32_t SystemCoreClock; + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = { + .outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */ + .irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ + .ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock selected */ + .fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */ + .lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */ + .hircEnableInNotHircMode = true, /* HIRC source is enabled */ +}; +const sim_clock_config_t simConfig_BOARD_BootClockRUN = { + .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */ + .clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */ +}; + +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Set the system clock dividers in SIM to safe value. */ + CLOCK_SetSimSafeDivs(); + /* Set MCG to HIRC mode. */ + CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN); + /* Set the clock configuration in SIM module. */ + CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} + + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB0_IRQHandler(void) +{ + tud_int_handler(0); +} + +void board_init(void) +{ + /* Enable port clocks for GPIO pins */ + CLOCK_EnableClock(kCLOCK_PortA); + CLOCK_EnableClock(kCLOCK_PortB); + CLOCK_EnableClock(kCLOCK_PortC); + CLOCK_EnableClock(kCLOCK_PortD); + CLOCK_EnableClock(kCLOCK_PortE); + + + gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 1 }; + GPIO_PinInit(GPIOA, 1U, &led_config); + PORT_SetPinMux(PORTA, 1U, kPORT_MuxAsGpio); + led_config.outputLogic = 0; + GPIO_PinInit(GPIOA, 2U, &led_config); + PORT_SetPinMux(PORTA, 2U, kPORT_MuxAsGpio); + +#ifdef BUTTON_PIN + gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config); + const port_pin_config_t BUTTON_CFG = { + kPORT_PullUp, + kPORT_FastSlewRate, + kPORT_PassiveFilterDisable, + kPORT_LowDriveStrength, + kPORT_MuxAsGpio + }; + PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG); +#endif + + /* PORTC3 is configured as LPUART0_RX */ + PORT_SetPinMux(PORTC, 3U, kPORT_MuxAlt3); + /* PORTA2 (pin 24) is configured as LPUART0_TX */ + PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3); + + SIM->SOPT5 = ((SIM->SOPT5 & + /* Mask bits to zero which are setting */ + (~(SIM_SOPT5_LPUART1TXSRC_MASK | SIM_SOPT5_LPUART1RXSRC_MASK))) + /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */ + | SIM_SOPT5_LPUART1TXSRC(SOPT5_LPUART1TXSRC_LPUART_TX) + /* LPUART0 Receive Data Source Select: LPUART_RX pin. */ + | SIM_SOPT5_LPUART1RXSRC(SOPT5_LPUART1RXSRC_LPUART_RX)); + + BOARD_BootClockRUN(); + SystemCoreClockUpdate(); + CLOCK_SetLpuart1Clock(1); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + lpuart_config_t uart_config; + LPUART_GetDefaultConfig(&uart_config); + uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; + uart_config.enableTx = true; + uart_config.enableRx = true; + LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk)); + + // USB + CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + if (state) { + LED_GPIO->PDDR |= GPIO_FIT_REG((1UL << LED_PIN)); + } else { + LED_GPIO->PDDR &= GPIO_FIT_REG(~(1UL << LED_PIN)); + } +// GPIO_PinWrite(GPIOA, 1, state ? LED_STATE_ON : (1-LED_STATE_ON) ); +// GPIO_PinWrite(GPIOA, 2, state ? (1-LED_STATE_ON) : LED_STATE_ON ); +} + +uint32_t board_button_read(void) +{ +#ifdef BUTTON_PIN + return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN); +#else + return 0; +#endif +} + +int board_uart_read(uint8_t* buf, int len) +{ + LPUART_ReadBlocking(UART_PORT, buf, len); + return len; +} + +int board_uart_write(void const * buf, int len) +{ + LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif diff --git a/hw/bsp/kinetis_k32l2/family.mk b/hw/bsp/kinetis_k32l2/family.mk new file mode 100644 index 000000000..357485762 --- /dev/null +++ b/hw/bsp/kinetis_k32l2/family.mk @@ -0,0 +1,32 @@ +UF2_FAMILY_ID = 0x7f83e793 +SDK_DIR = hw/mcu/nxp/mcux-sdk +DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5 +MCU_DIR = $(SDK_DIR)/devices/$(MCU) + +include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= cortex-m0plus + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_KINETIS_K32L + +SRC_C += \ + src/portable/nxp/khci/dcd_khci.c \ + src/portable/nxp/khci/hcd_khci.c \ + $(MCU_DIR)/system_$(MCU).c \ + $(MCU_DIR)/drivers/fsl_clock.c \ + $(SDK_DIR)/drivers/gpio/fsl_gpio.c \ + $(SDK_DIR)/drivers/lpuart/fsl_lpuart.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(MCU_DIR) \ + $(TOP)/$(MCU_DIR)/project_template \ + $(TOP)/$(MCU_DIR)/drivers \ + $(TOP)/$(SDK_DIR)/drivers/smc \ + $(TOP)/$(SDK_DIR)/drivers/common \ + $(TOP)/$(SDK_DIR)/drivers/gpio \ + $(TOP)/$(SDK_DIR)/drivers/port \ + $(TOP)/$(SDK_DIR)/drivers/lpuart \ + +SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 56525725e..9f3be78fd 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -97,7 +97,7 @@ #define TUP_DCD_ENDPOINT_MAX 8 #define TUP_RHPORT_HIGHSPEED 1 -#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32) +#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L) #define TUP_USBIP_CHIPIDEA_FS #define TUP_USBIP_CHIPIDEA_FS_KINETIS #define TUP_DCD_ENDPOINT_MAX 16 diff --git a/src/tusb_option.h b/src/tusb_option.h index 43e67cf64..f16d8a5d0 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -119,7 +119,8 @@ // NXP Kinetis #define OPT_MCU_KINETIS_KL 1200 ///< NXP KL series -#define OPT_MCU_KINETIS_K32 1201 ///< NXP K32 series +#define OPT_MCU_KINETIS_K32L 1201 ///< NXP K32L series +#define OPT_MCU_KINETIS_K32 1201 ///< Alias to K32L #define OPT_MCU_MKL25ZXX 1200 ///< Alias to KL (obsolete) #define OPT_MCU_K32L2BXX 1201 ///< Alias to K32 (obsolete) diff --git a/tools/get_deps.py b/tools/get_deps.py index 7e798cf9e..b81dabae0 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -52,7 +52,7 @@ deps_optional = { 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'], 'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git', '950819b7de9b32f92c3edf396bc5ffb8d66e7009', - 'kinetis_k32l lpc51 lpc54 lpc55 mcx imxrt'], + 'kinetis_k32l2 lpc51 lpc54 lpc55 mcx imxrt'], 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git', 'c3715ce94b6f6391856de56081d4d9b3e98fa93d', 'rp2040'], @@ -166,7 +166,7 @@ deps_optional = { 'ch32v307'], 'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git', '20285262657d1b482d132d20d755c8c330d55c1f', - 'imxrt kinetis_k32l lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x' + 'imxrt kinetis_k32l2 lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x' 'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 ' 'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb'], 'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git', -- cgit v1.3.1 From 3cfb838ba7f1f1a12203d36c9cbb615178af2cf7 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 26 Jun 2023 17:03:45 +0700 Subject: fix warnings when enable rtt with rp2040 --- hw/bsp/rp2040/family.c | 4 ++-- hw/bsp/rp2040/family.cmake | 6 +++++- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 2 +- src/portable/raspberrypi/rp2040/rp2040_usb.c | 2 +- 4 files changed, 9 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index 3aa989c0e..097e6fbd6 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -93,12 +93,12 @@ bool __no_inline_not_in_flash_func(get_bootsel_button)(void) { static void stdio_rtt_write (const char *buf, int length) { - SEGGER_RTT_Write(0, buf, length); + SEGGER_RTT_Write(0, buf, (unsigned) length); } static int stdio_rtt_read (char *buf, int len) { - return SEGGER_RTT_Read(0, buf, len); + return (int) SEGGER_RTT_Read(0, buf, (unsigned) len); } static stdio_driver_t stdio_rtt = diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index 28637e3ee..5cf6b1219 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -127,7 +127,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker) target_compile_definitions(tinyusb_additions INTERFACE CFG_TUSB_DEBUG=${LOG}) endif() - if(LOGGER STREQUAL "rtt") + if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt") target_compile_definitions(tinyusb_additions INTERFACE LOGGER_RTT SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL @@ -137,6 +137,10 @@ if (NOT TARGET _rp2040_family_inclusion_marker) ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c ) + set_source_files_properties(${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + PROPERTIES + COMPILE_FLAGS "-Wno-cast-qual -Wno-cast-align -Wno-sign-conversion") + target_include_directories(tinyusb_additions INTERFACE ${TOP}/lib/SEGGER_RTT/RTT ) diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 500a5373f..479b17b67 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -189,7 +189,7 @@ static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_by static void __tusb_irq_path_func(hw_handle_buff_status)(void) { uint32_t remaining_buffers = usb_hw->buf_status; - pico_trace("buf_status = 0x%08x\n", remaining_buffers); + pico_trace("buf_status = 0x%08lx\n", remaining_buffers); uint bit = 1u; for (uint8_t i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++) { diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index cf37cba07..1f49665ff 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -419,7 +419,7 @@ static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoi if (delta < 800 || delta > 998) { return false; } - TU_LOG(3, "Avoiding sof %u now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof); + TU_LOG(3, "Avoiding sof %lu now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof); return true; } -- cgit v1.3.1 From 8aa28e63fbcb4f38b62a8e111e29ee48b710db6b Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 26 Jun 2023 17:54:31 +0700 Subject: minor clean up with include_guard() --- .idea/cmake.xml | 2 +- hw/bsp/rp2040/family.cmake | 596 ++++++++++++++++++++++----------------------- src/CMakeLists.txt | 7 +- 3 files changed, 303 insertions(+), 302 deletions(-) (limited to 'src') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 012dc63ef..2ac7993c1 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -25,7 +25,7 @@ - + diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index 5cf6b1219..fee376538 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -1,341 +1,339 @@ cmake_minimum_required(VERSION 3.13) -if (NOT TARGET _rp2040_family_inclusion_marker) - add_library(_rp2040_family_inclusion_marker INTERFACE) +include_guard() - if (NOT BOARD) - message("BOARD not specified, defaulting to pico_sdk") - set(BOARD pico_sdk) - endif() - - # add the SDK in case we are standalone tinyusb example (noop if already present) - include(${CMAKE_CURRENT_LIST_DIR}/pico_sdk_import.cmake) +if (NOT BOARD) + message("BOARD not specified, defaulting to pico_sdk") + set(BOARD pico_sdk) +endif() - # include basic family CMake functionality - set(FAMILY_MCUS RP2040) +# add the SDK in case we are standalone tinyusb example (noop if already present) +include(${CMAKE_CURRENT_LIST_DIR}/pico_sdk_import.cmake) - include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) +# include basic family CMake functionality +set(FAMILY_MCUS RP2040) - # TOP is absolute path to root directory of TinyUSB git repo - #set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..") - #get_filename_component(TOP "${TOP}" REALPATH) +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) - if (NOT PICO_TINYUSB_PATH) - set(PICO_TINYUSB_PATH ${TOP}) - endif() +# TOP is absolute path to root directory of TinyUSB git repo +#set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..") +#get_filename_component(TOP "${TOP}" REALPATH) - if (NOT TINYUSB_OPT_OS) - set(TINYUSB_OPT_OS OPT_OS_PICO) - endif() +if (NOT PICO_TINYUSB_PATH) + set(PICO_TINYUSB_PATH ${TOP}) +endif() - #------------------------------------ - # Base config for both device and host; wrapped by SDK's tinyusb_common - #------------------------------------ - add_library(tinyusb_common_base INTERFACE) - - target_sources(tinyusb_common_base INTERFACE - ${TOP}/src/tusb.c - ${TOP}/src/common/tusb_fifo.c - ) - - target_include_directories(tinyusb_common_base INTERFACE - ${TOP}/src - ${TOP}/src/common - ${TOP}/hw - ) - - target_link_libraries(tinyusb_common_base INTERFACE - hardware_structs - hardware_irq - hardware_resets - pico_sync - ) - - set(TINYUSB_DEBUG_LEVEL 0) - if (CMAKE_BUILD_TYPE STREQUAL "Debug") - message("Compiling TinyUSB with CFG_TUSB_DEBUG=1") - set(TINYUSB_DEBUG_LEVEL 1) - endif() +if (NOT TINYUSB_OPT_OS) + set(TINYUSB_OPT_OS OPT_OS_PICO) +endif() - target_compile_definitions(tinyusb_common_base INTERFACE - CFG_TUSB_MCU=OPT_MCU_RP2040 - CFG_TUSB_OS=${TINYUSB_OPT_OS} - #CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL} - ) +#------------------------------------ +# Base config for both device and host; wrapped by SDK's tinyusb_common +#------------------------------------ +add_library(tinyusb_common_base INTERFACE) - #------------------------------------ - # Base config for device mode; wrapped by SDK's tinyusb_device - #------------------------------------ - add_library(tinyusb_device_base INTERFACE) - target_sources(tinyusb_device_base INTERFACE - ${TOP}/src/portable/raspberrypi/rp2040/dcd_rp2040.c - ${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c - ${TOP}/src/device/usbd.c - ${TOP}/src/device/usbd_control.c - ${TOP}/src/class/audio/audio_device.c - ${TOP}/src/class/cdc/cdc_device.c - ${TOP}/src/class/dfu/dfu_device.c - ${TOP}/src/class/dfu/dfu_rt_device.c - ${TOP}/src/class/hid/hid_device.c - ${TOP}/src/class/midi/midi_device.c - ${TOP}/src/class/msc/msc_device.c - ${TOP}/src/class/net/ecm_rndis_device.c - ${TOP}/src/class/net/ncm_device.c - ${TOP}/src/class/usbtmc/usbtmc_device.c - ${TOP}/src/class/vendor/vendor_device.c - ${TOP}/src/class/video/video_device.c - ) - - #------------------------------------ - # Base config for host mode; wrapped by SDK's tinyusb_host - #------------------------------------ - add_library(tinyusb_host_base INTERFACE) - target_sources(tinyusb_host_base INTERFACE - ${TOP}/src/portable/raspberrypi/rp2040/hcd_rp2040.c - ${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c - ${TOP}/src/host/usbh.c - ${TOP}/src/host/hub.c - ${TOP}/src/class/cdc/cdc_host.c - ${TOP}/src/class/hid/hid_host.c - ${TOP}/src/class/msc/msc_host.c - ${TOP}/src/class/vendor/vendor_host.c - ) - - # Sometimes have to do host specific actions in mostly common functions - target_compile_definitions(tinyusb_host_base INTERFACE - RP2040_USB_HOST_MODE=1 - ) +target_sources(tinyusb_common_base INTERFACE + ${TOP}/src/tusb.c + ${TOP}/src/common/tusb_fifo.c + ) - #------------------------------------ - # BSP & Additions - #------------------------------------ - add_library(tinyusb_bsp INTERFACE) - target_sources(tinyusb_bsp INTERFACE - ${TOP}/hw/bsp/rp2040/family.c - ) - # target_include_directories(tinyusb_bsp INTERFACE - # ${TOP}/hw/bsp/rp2040) +target_include_directories(tinyusb_common_base INTERFACE + ${TOP}/src + ${TOP}/src/common + ${TOP}/hw + ) - # tinyusb_additions will hold our extra settings for examples - add_library(tinyusb_additions INTERFACE) +target_link_libraries(tinyusb_common_base INTERFACE + hardware_structs + hardware_irq + hardware_resets + pico_sync + ) - target_compile_definitions(tinyusb_additions INTERFACE - PICO_RP2040_USB_DEVICE_ENUMERATION_FIX=1 - PICO_RP2040_USB_DEVICE_UFRAME_FIX=1 - ) +set(TINYUSB_DEBUG_LEVEL 0) +if (CMAKE_BUILD_TYPE STREQUAL "Debug") + message("Compiling TinyUSB with CFG_TUSB_DEBUG=1") + set(TINYUSB_DEBUG_LEVEL 1) +endif() - if(DEFINED LOG) - target_compile_definitions(tinyusb_additions INTERFACE CFG_TUSB_DEBUG=${LOG}) - endif() +target_compile_definitions(tinyusb_common_base INTERFACE + CFG_TUSB_MCU=OPT_MCU_RP2040 + CFG_TUSB_OS=${TINYUSB_OPT_OS} + #CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL} +) + +#------------------------------------ +# Base config for device mode; wrapped by SDK's tinyusb_device +#------------------------------------ +add_library(tinyusb_device_base INTERFACE) +target_sources(tinyusb_device_base INTERFACE + ${TOP}/src/portable/raspberrypi/rp2040/dcd_rp2040.c + ${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c + ${TOP}/src/device/usbd.c + ${TOP}/src/device/usbd_control.c + ${TOP}/src/class/audio/audio_device.c + ${TOP}/src/class/cdc/cdc_device.c + ${TOP}/src/class/dfu/dfu_device.c + ${TOP}/src/class/dfu/dfu_rt_device.c + ${TOP}/src/class/hid/hid_device.c + ${TOP}/src/class/midi/midi_device.c + ${TOP}/src/class/msc/msc_device.c + ${TOP}/src/class/net/ecm_rndis_device.c + ${TOP}/src/class/net/ncm_device.c + ${TOP}/src/class/usbtmc/usbtmc_device.c + ${TOP}/src/class/vendor/vendor_device.c + ${TOP}/src/class/video/video_device.c + ) - if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt") - target_compile_definitions(tinyusb_additions INTERFACE - LOGGER_RTT - SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL +#------------------------------------ +# Base config for host mode; wrapped by SDK's tinyusb_host +#------------------------------------ +add_library(tinyusb_host_base INTERFACE) +target_sources(tinyusb_host_base INTERFACE + ${TOP}/src/portable/raspberrypi/rp2040/hcd_rp2040.c + ${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c + ${TOP}/src/host/usbh.c + ${TOP}/src/host/hub.c + ${TOP}/src/class/cdc/cdc_host.c + ${TOP}/src/class/hid/hid_host.c + ${TOP}/src/class/msc/msc_host.c + ${TOP}/src/class/vendor/vendor_host.c ) - target_sources(tinyusb_additions INTERFACE - ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c +# Sometimes have to do host specific actions in mostly common functions +target_compile_definitions(tinyusb_host_base INTERFACE + RP2040_USB_HOST_MODE=1 +) + +#------------------------------------ +# BSP & Additions +#------------------------------------ +add_library(tinyusb_bsp INTERFACE) +target_sources(tinyusb_bsp INTERFACE + ${TOP}/hw/bsp/rp2040/family.c ) +# target_include_directories(tinyusb_bsp INTERFACE +# ${TOP}/hw/bsp/rp2040) - set_source_files_properties(${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - PROPERTIES - COMPILE_FLAGS "-Wno-cast-qual -Wno-cast-align -Wno-sign-conversion") +# tinyusb_additions will hold our extra settings for examples +add_library(tinyusb_additions INTERFACE) - target_include_directories(tinyusb_additions INTERFACE - ${TOP}/lib/SEGGER_RTT/RTT - ) - endif() +target_compile_definitions(tinyusb_additions INTERFACE + PICO_RP2040_USB_DEVICE_ENUMERATION_FIX=1 + PICO_RP2040_USB_DEVICE_UFRAME_FIX=1 +) - #------------------------------------ - # Functions - #------------------------------------ +if(DEFINED LOG) + target_compile_definitions(tinyusb_additions INTERFACE CFG_TUSB_DEBUG=${LOG}) +endif() - function(family_configure_target TARGET) - pico_add_extra_outputs(${TARGET}) - pico_enable_stdio_uart(${TARGET} 1) - target_link_libraries(${TARGET} PUBLIC pico_stdlib pico_bootsel_via_double_reset tinyusb_board tinyusb_additions) - endfunction() +if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt") + target_compile_definitions(tinyusb_additions INTERFACE + LOGGER_RTT + SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL + ) - function(rp2040_family_configure_example_warnings TARGET) - if (NOT PICO_TINYUSB_NO_EXAMPLE_WARNINGS) - family_add_default_example_warnings(${TARGET}) - endif() - if(CMAKE_C_COMPILER_ID STREQUAL "Clang") - target_compile_options(${TARGET} PRIVATE -Wno-unreachable-code) - endif() - suppress_tinyusb_warnings() - endfunction() + target_sources(tinyusb_additions INTERFACE + ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + ) - function(family_configure_device_example TARGET) - family_configure_target(${TARGET}) - target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device) - rp2040_family_configure_example_warnings(${TARGET}) - endfunction() + set_source_files_properties(${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + PROPERTIES + COMPILE_FLAGS "-Wno-cast-qual -Wno-cast-align -Wno-sign-conversion") + + target_include_directories(tinyusb_additions INTERFACE + ${TOP}/lib/SEGGER_RTT/RTT + ) +endif() - function(family_add_pico_pio_usb TARGET) - target_link_libraries(${TARGET} PUBLIC tinyusb_pico_pio_usb) - endfunction() +#------------------------------------ +# Functions +#------------------------------------ - function(family_configure_host_example TARGET) - family_configure_target(${TARGET}) - target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host) - rp2040_family_configure_example_warnings(${TARGET}) +function(family_configure_target TARGET) + pico_add_extra_outputs(${TARGET}) + pico_enable_stdio_uart(${TARGET} 1) + target_link_libraries(${TARGET} PUBLIC pico_stdlib pico_bootsel_via_double_reset tinyusb_board tinyusb_additions) +endfunction() - # For rp2040 enable pico-pio-usb - if (TARGET tinyusb_pico_pio_usb) - # code does not compile with non GCC, or GCC 11.3+ - if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND NOT CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.3) - family_add_pico_pio_usb(${PROJECT}) - endif() +function(rp2040_family_configure_example_warnings TARGET) + if (NOT PICO_TINYUSB_NO_EXAMPLE_WARNINGS) + family_add_default_example_warnings(${TARGET}) + endif() + if(CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_compile_options(${TARGET} PRIVATE -Wno-unreachable-code) + endif() + suppress_tinyusb_warnings() +endfunction() + +function(family_configure_device_example TARGET) + family_configure_target(${TARGET}) + target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device) + rp2040_family_configure_example_warnings(${TARGET}) +endfunction() + +function(family_add_pico_pio_usb TARGET) + target_link_libraries(${TARGET} PUBLIC tinyusb_pico_pio_usb) +endfunction() + +function(family_configure_host_example TARGET) + family_configure_target(${TARGET}) + target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host) + rp2040_family_configure_example_warnings(${TARGET}) + + # For rp2040 enable pico-pio-usb + if (TARGET tinyusb_pico_pio_usb) + # code does not compile with non GCC, or GCC 11.3+ + if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND NOT CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.3) + family_add_pico_pio_usb(${PROJECT}) endif() - endfunction() - - function(family_configure_dual_usb_example TARGET) - family_configure_target(${TARGET}) - # require tinyusb_pico_pio_usb - target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device tinyusb_host tinyusb_pico_pio_usb ) - rp2040_family_configure_example_warnings(${TARGET}) - endfunction() - - function(check_and_add_pico_pio_usb_support) - # check for pico_generate_pio_header (as depending on environment we may be called before SDK is - # initialized in which case it isn't available yet), and only do the initialization once - if (COMMAND pico_generate_pio_header AND NOT TARGET tinyusb_pico_pio_usb) - #------------------------------------ - # PIO USB for both host and device - #------------------------------------ - - if (NOT DEFINED PICO_PIO_USB_PATH) - set(PICO_PIO_USB_PATH "${TOP}/hw/mcu/raspberry_pi/Pico-PIO-USB") - endif() - - if (EXISTS ${PICO_PIO_USB_PATH}/src/pio_usb.c) - add_library(tinyusb_pico_pio_usb INTERFACE) - target_sources(tinyusb_device_base INTERFACE - ${TOP}/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c - ) - target_sources(tinyusb_host_base INTERFACE - ${TOP}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c - ) - - target_sources(tinyusb_pico_pio_usb INTERFACE - ${PICO_PIO_USB_PATH}/src/pio_usb.c - ${PICO_PIO_USB_PATH}/src/pio_usb_host.c - ${PICO_PIO_USB_PATH}/src/pio_usb_device.c - ${PICO_PIO_USB_PATH}/src/usb_crc.c - ) - - target_include_directories(tinyusb_pico_pio_usb INTERFACE - ${PICO_PIO_USB_PATH}/src - ) - - target_link_libraries(tinyusb_pico_pio_usb INTERFACE - hardware_dma - hardware_pio - pico_multicore - ) - - target_compile_definitions(tinyusb_pico_pio_usb INTERFACE - PIO_USB_USE_TINYUSB - ) - - pico_generate_pio_header(tinyusb_pico_pio_usb ${PICO_PIO_USB_PATH}/src/usb_tx.pio) - pico_generate_pio_header(tinyusb_pico_pio_usb ${PICO_PIO_USB_PATH}/src/usb_rx.pio) - endif() + endif() +endfunction() + +function(family_configure_dual_usb_example TARGET) + family_configure_target(${TARGET}) + # require tinyusb_pico_pio_usb + target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device tinyusb_host tinyusb_pico_pio_usb ) + rp2040_family_configure_example_warnings(${TARGET}) +endfunction() + +function(check_and_add_pico_pio_usb_support) + # check for pico_generate_pio_header (as depending on environment we may be called before SDK is + # initialized in which case it isn't available yet), and only do the initialization once + if (COMMAND pico_generate_pio_header AND NOT TARGET tinyusb_pico_pio_usb) + #------------------------------------ + # PIO USB for both host and device + #------------------------------------ + + if (NOT DEFINED PICO_PIO_USB_PATH) + set(PICO_PIO_USB_PATH "${TOP}/hw/mcu/raspberry_pi/Pico-PIO-USB") endif() - endfunction() - # Try to add Pico-PIO_USB support now for the case where this file is included directly - # after Pico SDK initialization, but without using the family_ functions (as is the case - # when included by the SDK itself) - check_and_add_pico_pio_usb_support() + if (EXISTS ${PICO_PIO_USB_PATH}/src/pio_usb.c) + add_library(tinyusb_pico_pio_usb INTERFACE) + target_sources(tinyusb_device_base INTERFACE + ${TOP}/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c + ) + target_sources(tinyusb_host_base INTERFACE + ${TOP}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c + ) - function(family_initialize_project PROJECT DIR) - # call the original version of this function from family_common.cmake - _family_initialize_project(${PROJECT} ${DIR}) - enable_language(C CXX ASM) - pico_sdk_init() - - # now re-check for adding Pico-PIO_USB support now SDK is definitely available - check_and_add_pico_pio_usb_support() - endfunction() - - # This method must be called from the project scope to suppress known warnings in TinyUSB source files - function(suppress_tinyusb_warnings) - # some of these are pretty silly warnings only occurring in some older GCC versions 9 or prior - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - if (CMAKE_C_COMPILER_VERSION VERSION_LESS 10.0) - set(CONVERSION_WARNING_FILES - ${PICO_TINYUSB_PATH}/src/tusb.c - ${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c - ${PICO_TINYUSB_PATH}/src/device/usbd.c - ${PICO_TINYUSB_PATH}/src/device/usbd_control.c - ${PICO_TINYUSB_PATH}/src/host/usbh.c - ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c - ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c - ${PICO_TINYUSB_PATH}/src/class/hid/hid_device.c - ${PICO_TINYUSB_PATH}/src/class/hid/hid_host.c - ${PICO_TINYUSB_PATH}/src/class/audio/audio_device.c - ${PICO_TINYUSB_PATH}/src/class/dfu/dfu_device.c - ${PICO_TINYUSB_PATH}/src/class/dfu/dfu_rt_device.c - ${PICO_TINYUSB_PATH}/src/class/midi/midi_device.c - ${PICO_TINYUSB_PATH}/src/class/usbtmc/usbtmc_device.c - ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/hcd_rp2040.c + target_sources(tinyusb_pico_pio_usb INTERFACE + ${PICO_PIO_USB_PATH}/src/pio_usb.c + ${PICO_PIO_USB_PATH}/src/pio_usb_host.c + ${PICO_PIO_USB_PATH}/src/pio_usb_device.c + ${PICO_PIO_USB_PATH}/src/usb_crc.c ) - foreach(SOURCE_FILE IN LISTS CONVERSION_WARNING_FILES) - set_source_files_properties( - ${SOURCE_FILE} - PROPERTIES - COMPILE_FLAGS "-Wno-conversion") - endforeach() - endif() - if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.0) - set_source_files_properties( - ${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c - COMPILE_FLAGS "-Wno-stringop-overflow -Wno-array-bounds") - endif() - set_source_files_properties( - ${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c - PROPERTIES - COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual") - set_source_files_properties( - ${PICO_TINYUSB_PATH}/lib/lwip/src/core/tcp_in.c - ${PICO_TINYUSB_PATH}/lib/lwip/src/core/tcp_out.c - PROPERTIES - COMPILE_FLAGS "-Wno-conversion") + target_include_directories(tinyusb_pico_pio_usb INTERFACE + ${PICO_PIO_USB_PATH}/src + ) - set_source_files_properties( - ${PICO_TINYUSB_PATH}/lib/networking/dnserver.c - ${PICO_TINYUSB_PATH}/lib/networking/dhserver.c - ${PICO_TINYUSB_PATH}/lib/networking/rndis_reports.c - PROPERTIES - COMPILE_FLAGS "-Wno-conversion -Wno-sign-conversion") + target_link_libraries(tinyusb_pico_pio_usb INTERFACE + hardware_dma + hardware_pio + pico_multicore + ) + + target_compile_definitions(tinyusb_pico_pio_usb INTERFACE + PIO_USB_USE_TINYUSB + ) - if (TARGET tinyusb_pico_pio_usb) + pico_generate_pio_header(tinyusb_pico_pio_usb ${PICO_PIO_USB_PATH}/src/usb_tx.pio) + pico_generate_pio_header(tinyusb_pico_pio_usb ${PICO_PIO_USB_PATH}/src/usb_rx.pio) + endif() + endif() +endfunction() + +# Try to add Pico-PIO_USB support now for the case where this file is included directly +# after Pico SDK initialization, but without using the family_ functions (as is the case +# when included by the SDK itself) +check_and_add_pico_pio_usb_support() + +function(family_initialize_project PROJECT DIR) + # call the original version of this function from family_common.cmake + _family_initialize_project(${PROJECT} ${DIR}) + enable_language(C CXX ASM) + pico_sdk_init() + + # now re-check for adding Pico-PIO_USB support now SDK is definitely available + check_and_add_pico_pio_usb_support() +endfunction() + +# This method must be called from the project scope to suppress known warnings in TinyUSB source files +function(suppress_tinyusb_warnings) + # some of these are pretty silly warnings only occurring in some older GCC versions 9 or prior + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + if (CMAKE_C_COMPILER_VERSION VERSION_LESS 10.0) + set(CONVERSION_WARNING_FILES + ${PICO_TINYUSB_PATH}/src/tusb.c + ${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c + ${PICO_TINYUSB_PATH}/src/device/usbd.c + ${PICO_TINYUSB_PATH}/src/device/usbd_control.c + ${PICO_TINYUSB_PATH}/src/host/usbh.c + ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c + ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c + ${PICO_TINYUSB_PATH}/src/class/hid/hid_device.c + ${PICO_TINYUSB_PATH}/src/class/hid/hid_host.c + ${PICO_TINYUSB_PATH}/src/class/audio/audio_device.c + ${PICO_TINYUSB_PATH}/src/class/dfu/dfu_device.c + ${PICO_TINYUSB_PATH}/src/class/dfu/dfu_rt_device.c + ${PICO_TINYUSB_PATH}/src/class/midi/midi_device.c + ${PICO_TINYUSB_PATH}/src/class/usbtmc/usbtmc_device.c + ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/hcd_rp2040.c + ) + foreach(SOURCE_FILE IN LISTS CONVERSION_WARNING_FILES) set_source_files_properties( - ${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb_device.c - ${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb.c - ${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb_host.c - ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c + ${SOURCE_FILE} PROPERTIES - COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual -Wno-attributes") - endif() - elseif(CMAKE_C_COMPILER_ID STREQUAL "Clang") - set_source_files_properties( - ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c - COMPILE_FLAGS "-Wno-unreachable-code") - set_source_files_properties( - ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c - COMPILE_FLAGS "-Wno-unreachable-code-fallthrough") + COMPILE_FLAGS "-Wno-conversion") + endforeach() + endif() + if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.0) set_source_files_properties( ${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c + COMPILE_FLAGS "-Wno-stringop-overflow -Wno-array-bounds") + endif() + set_source_files_properties( + ${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c + PROPERTIES + COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual") + + set_source_files_properties( + ${PICO_TINYUSB_PATH}/lib/lwip/src/core/tcp_in.c + ${PICO_TINYUSB_PATH}/lib/lwip/src/core/tcp_out.c + PROPERTIES + COMPILE_FLAGS "-Wno-conversion") + + set_source_files_properties( + ${PICO_TINYUSB_PATH}/lib/networking/dnserver.c + ${PICO_TINYUSB_PATH}/lib/networking/dhserver.c + ${PICO_TINYUSB_PATH}/lib/networking/rndis_reports.c + PROPERTIES + COMPILE_FLAGS "-Wno-conversion -Wno-sign-conversion") + + if (TARGET tinyusb_pico_pio_usb) + set_source_files_properties( + ${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb_device.c + ${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb.c + ${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb_host.c + ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c PROPERTIES - COMPILE_FLAGS "-Wno-cast-qual") + COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual -Wno-attributes") endif() - endfunction() + elseif(CMAKE_C_COMPILER_ID STREQUAL "Clang") + set_source_files_properties( + ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c + COMPILE_FLAGS "-Wno-unreachable-code") + set_source_files_properties( + ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c + COMPILE_FLAGS "-Wno-unreachable-code-fallthrough") + set_source_files_properties( + ${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c + PROPERTIES + COMPILE_FLAGS "-Wno-cast-qual") + endif() +endfunction() - # rp2040 does not support freeRTOS example yet - function(family_add_freertos TARGET) - endfunction() -endif() +# rp2040 does not support freeRTOS example yet +function(family_add_freertos TARGET) +endfunction() diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index b99c7be6e..8f7f38589 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -75,8 +75,11 @@ endfunction() #------------------------------------ # TinyUSB as library target #------------------------------------ -set(TINYUSB_TARGET "tinyusb") -set(TINYUSB_CONFIG_TARGET "tinyusb_config") +if (NOT DEFINED TINYUSB_TARGET) + set(TINYUSB_TARGET "tinyusb") +endif () + +set(TINYUSB_CONFIG_TARGET "${TINYUSB_TARGET}_config") if (DEFINED TINYUSB_TARGET_PREFIX) set(TINYUSB_TARGET "${TINYUSB_TARGET_PREFIX}${TINYUSB_TARGET}") -- cgit v1.3.1 From e43387abaca2044f96017481ccb00b3b68dbdc2a Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 27 Jun 2023 15:45:38 +0700 Subject: rework cmake with rtos support add RTOS to family_configure_device/host/dual_example() --- examples/device/audio_4_channel_mic/CMakeLists.txt | 6 +- examples/device/audio_test/CMakeLists.txt | 6 +- .../device/audio_test_multi_rate/CMakeLists.txt | 6 +- examples/device/board_test/CMakeLists.txt | 6 +- examples/device/cdc_dual_ports/CMakeLists.txt | 6 +- examples/device/cdc_msc/CMakeLists.txt | 2 +- examples/device/cdc_msc_freertos/CMakeLists.txt | 9 +- examples/device/dfu/CMakeLists.txt | 6 +- examples/device/dfu_runtime/CMakeLists.txt | 6 +- .../device/dynamic_configuration/CMakeLists.txt | 6 +- examples/device/hid_boot_interface/CMakeLists.txt | 6 +- examples/device/hid_composite/CMakeLists.txt | 6 +- .../device/hid_composite_freertos/CMakeLists.txt | 9 +- examples/device/hid_generic_inout/CMakeLists.txt | 6 +- .../device/hid_multiple_interface/CMakeLists.txt | 6 +- examples/device/midi_test/CMakeLists.txt | 6 +- examples/device/msc_dual_lun/CMakeLists.txt | 6 +- examples/device/net_lwip_webserver/CMakeLists.txt | 6 +- examples/device/uac2_headset/CMakeLists.txt | 6 +- examples/device/usbtmc/CMakeLists.txt | 6 +- examples/device/video_capture/CMakeLists.txt | 6 +- examples/device/webusb_serial/CMakeLists.txt | 6 +- .../dual/host_hid_to_device_cdc/CMakeLists.txt | 6 +- examples/host/bare_api/CMakeLists.txt | 6 +- examples/host/cdc_msc_hid/CMakeLists.txt | 6 +- examples/host/hid_controller/CMakeLists.txt | 6 +- examples/host/msc_file_explorer/CMakeLists.txt | 6 +- examples/typec/power_delivery/CMakeLists.txt | 6 +- examples/typec/power_delivery/src/tusb_config.h | 14 +- hw/bsp/family_support.cmake | 164 ++++++++++++--------- hw/bsp/imxrt/family.cmake | 19 +-- hw/bsp/kinetis_kl/family.cmake | 19 +-- hw/bsp/lpc18/family.cmake | 19 +-- hw/bsp/lpc55/family.cmake | 19 +-- hw/bsp/mcx/family.cmake | 19 +-- hw/bsp/nrf/family.cmake | 19 +-- hw/bsp/rp2040/family.cmake | 43 ++++-- hw/bsp/stm32f0/family.cmake | 19 +-- hw/bsp/stm32f1/family.cmake | 19 +-- hw/bsp/stm32f7/family.cmake | 19 +-- hw/bsp/stm32g0/family.cmake | 19 +-- hw/bsp/stm32g4/family.cmake | 19 +-- hw/bsp/stm32h7/family.cmake | 19 +-- hw/bsp/stm32l4/family.cmake | 19 +-- src/common/tusb_compiler.h | 8 +- test/fuzz/device/cdc/CMakeLists.txt | 18 +-- test/fuzz/device/msc/CMakeLists.txt | 6 +- test/fuzz/device/net/CMakeLists.txt | 6 +- 48 files changed, 272 insertions(+), 404 deletions(-) (limited to 'src') diff --git a/examples/device/audio_4_channel_mic/CMakeLists.txt b/examples/device/audio_4_channel_mic/CMakeLists.txt index 87b7d07d4..f61e1b640 100644 --- a/examples/device/audio_4_channel_mic/CMakeLists.txt +++ b/examples/device/audio_4_channel_mic/CMakeLists.txt @@ -28,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/audio_test/CMakeLists.txt b/examples/device/audio_test/CMakeLists.txt index 87b7d07d4..f61e1b640 100644 --- a/examples/device/audio_test/CMakeLists.txt +++ b/examples/device/audio_test/CMakeLists.txt @@ -28,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/audio_test_multi_rate/CMakeLists.txt b/examples/device/audio_test_multi_rate/CMakeLists.txt index 87b7d07d4..f61e1b640 100644 --- a/examples/device/audio_test_multi_rate/CMakeLists.txt +++ b/examples/device/audio_test_multi_rate/CMakeLists.txt @@ -28,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt index 4ab8d5a65..012eff095 100644 --- a/examples/device/board_test/CMakeLists.txt +++ b/examples/device/board_test/CMakeLists.txt @@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/cdc_dual_ports/CMakeLists.txt b/examples/device/cdc_dual_ports/CMakeLists.txt index 87b7d07d4..f61e1b640 100644 --- a/examples/device/cdc_dual_ports/CMakeLists.txt +++ b/examples/device/cdc_dual_ports/CMakeLists.txt @@ -28,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt index 4ec172f17..9415f8c68 100644 --- a/examples/device/cdc_msc/CMakeLists.txt +++ b/examples/device/cdc_msc/CMakeLists.txt @@ -32,4 +32,4 @@ target_include_directories(${PROJECT} PUBLIC # Configure compilation flags and libraries for the example... see the corresponding function # in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt index 319ad0356..33c7a1ec0 100644 --- a/examples/device/cdc_msc_freertos/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/CMakeLists.txt @@ -30,9 +30,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) - -# Add FreeRTOS for this example -family_add_freertos(${PROJECT}) +# Configure compilation flags and libraries for the example with FreeRTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} freertos) diff --git a/examples/device/dfu/CMakeLists.txt b/examples/device/dfu/CMakeLists.txt index eb4c198d6..a01eb3456 100644 --- a/examples/device/dfu/CMakeLists.txt +++ b/examples/device/dfu/CMakeLists.txt @@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/dfu_runtime/CMakeLists.txt b/examples/device/dfu_runtime/CMakeLists.txt index eb4c198d6..a01eb3456 100644 --- a/examples/device/dfu_runtime/CMakeLists.txt +++ b/examples/device/dfu_runtime/CMakeLists.txt @@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/dynamic_configuration/CMakeLists.txt b/examples/device/dynamic_configuration/CMakeLists.txt index 046a32257..2b20d2234 100644 --- a/examples/device/dynamic_configuration/CMakeLists.txt +++ b/examples/device/dynamic_configuration/CMakeLists.txt @@ -28,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/hid_boot_interface/CMakeLists.txt b/examples/device/hid_boot_interface/CMakeLists.txt index eb4c198d6..a01eb3456 100644 --- a/examples/device/hid_boot_interface/CMakeLists.txt +++ b/examples/device/hid_boot_interface/CMakeLists.txt @@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/hid_composite/CMakeLists.txt b/examples/device/hid_composite/CMakeLists.txt index eb4c198d6..a01eb3456 100644 --- a/examples/device/hid_composite/CMakeLists.txt +++ b/examples/device/hid_composite/CMakeLists.txt @@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/hid_composite_freertos/CMakeLists.txt b/examples/device/hid_composite_freertos/CMakeLists.txt index 211904cf9..eb22014fb 100644 --- a/examples/device/hid_composite_freertos/CMakeLists.txt +++ b/examples/device/hid_composite_freertos/CMakeLists.txt @@ -29,9 +29,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) - -# Add FreeRTOS for this example -family_add_freertos(${PROJECT}) +# Configure compilation flags and libraries for the example with FreeRTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} freertos) diff --git a/examples/device/hid_generic_inout/CMakeLists.txt b/examples/device/hid_generic_inout/CMakeLists.txt index eb4c198d6..a01eb3456 100644 --- a/examples/device/hid_generic_inout/CMakeLists.txt +++ b/examples/device/hid_generic_inout/CMakeLists.txt @@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/hid_multiple_interface/CMakeLists.txt b/examples/device/hid_multiple_interface/CMakeLists.txt index eb4c198d6..a01eb3456 100644 --- a/examples/device/hid_multiple_interface/CMakeLists.txt +++ b/examples/device/hid_multiple_interface/CMakeLists.txt @@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/midi_test/CMakeLists.txt b/examples/device/midi_test/CMakeLists.txt index 5b1a5547d..e51f14c02 100644 --- a/examples/device/midi_test/CMakeLists.txt +++ b/examples/device/midi_test/CMakeLists.txt @@ -26,6 +26,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/msc_dual_lun/CMakeLists.txt b/examples/device/msc_dual_lun/CMakeLists.txt index dc8d5512c..e69fead35 100644 --- a/examples/device/msc_dual_lun/CMakeLists.txt +++ b/examples/device/msc_dual_lun/CMakeLists.txt @@ -29,6 +29,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt index 2c21aa52b..1e34428fe 100644 --- a/examples/device/net_lwip_webserver/CMakeLists.txt +++ b/examples/device/net_lwip_webserver/CMakeLists.txt @@ -88,6 +88,6 @@ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") endif () -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/uac2_headset/CMakeLists.txt b/examples/device/uac2_headset/CMakeLists.txt index d142e9c04..e92a57148 100644 --- a/examples/device/uac2_headset/CMakeLists.txt +++ b/examples/device/uac2_headset/CMakeLists.txt @@ -28,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/usbtmc/CMakeLists.txt b/examples/device/usbtmc/CMakeLists.txt index a6b22ab36..a63ca2d81 100644 --- a/examples/device/usbtmc/CMakeLists.txt +++ b/examples/device/usbtmc/CMakeLists.txt @@ -29,6 +29,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/video_capture/CMakeLists.txt b/examples/device/video_capture/CMakeLists.txt index e0bd975c4..80dc39ca5 100644 --- a/examples/device/video_capture/CMakeLists.txt +++ b/examples/device/video_capture/CMakeLists.txt @@ -34,6 +34,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/device/webusb_serial/CMakeLists.txt b/examples/device/webusb_serial/CMakeLists.txt index d142e9c04..e92a57148 100644 --- a/examples/device/webusb_serial/CMakeLists.txt +++ b/examples/device/webusb_serial/CMakeLists.txt @@ -28,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt index c6d19a720..a6557c2d0 100644 --- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt +++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt @@ -23,9 +23,9 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_dual_usb_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_dual_usb_example(${PROJECT} noos) # due to warnings from Pico-PIO-USB target_compile_options(${PROJECT} PUBLIC diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt index b6d8c9c89..95af48718 100644 --- a/examples/host/bare_api/CMakeLists.txt +++ b/examples/host/bare_api/CMakeLists.txt @@ -22,9 +22,9 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_host_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_host_example(${PROJECT} noos) # Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host if(FAMILY STREQUAL "rp2040") diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt index 68b52e274..3fdc832ab 100644 --- a/examples/host/cdc_msc_hid/CMakeLists.txt +++ b/examples/host/cdc_msc_hid/CMakeLists.txt @@ -25,9 +25,9 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_host_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_host_example(${PROJECT} noos) # Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host if(FAMILY STREQUAL "rp2040") diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt index e27f83c53..d1d901b53 100644 --- a/examples/host/hid_controller/CMakeLists.txt +++ b/examples/host/hid_controller/CMakeLists.txt @@ -23,9 +23,9 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_host_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_host_example(${PROJECT} noos) # Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host if(FAMILY STREQUAL "rp2040") diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt index 327d1218a..99c797275 100644 --- a/examples/host/msc_file_explorer/CMakeLists.txt +++ b/examples/host/msc_file_explorer/CMakeLists.txt @@ -35,9 +35,9 @@ target_include_directories(${PROJECT} PUBLIC ${TOP}/lib/embedded-cli ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_host_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_host_example(${PROJECT} noos) # Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host if(FAMILY STREQUAL "rp2040") diff --git a/examples/typec/power_delivery/CMakeLists.txt b/examples/typec/power_delivery/CMakeLists.txt index 4ab8d5a65..012eff095 100644 --- a/examples/typec/power_delivery/CMakeLists.txt +++ b/examples/typec/power_delivery/CMakeLists.txt @@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/examples/typec/power_delivery/src/tusb_config.h b/examples/typec/power_delivery/src/tusb_config.h index deddcbfa4..f7cb3cc04 100644 --- a/examples/typec/power_delivery/src/tusb_config.h +++ b/examples/typec/power_delivery/src/tusb_config.h @@ -30,11 +30,6 @@ extern "C" { #endif -// special example that doesn't enable device or host stack -// This can cause some TinyUSB API missing, this define hack to allow us to fill those API -// to pass the compilation process -#define tud_int_handler(x) - //-------------------------------------------------------------------- // COMMON CONFIGURATION //-------------------------------------------------------------------- @@ -54,6 +49,15 @@ // Enable TYPEC stack #define CFG_TUC_ENABLED 1 + +// special example that doesn't enable device or host stack +// This can cause some TinyUSB API missing, this define hack to allow us to fill those API +// to pass the compilation process +#if CFG_TUD_ENABLED == 0 +#define tud_int_handler(x) +#endif + + // CFG_TUSB_DEBUG is defined by compiler in DEBUG build // #define CFG_TUSB_DEBUG 0 diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 93cab8723..781c67bf7 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -64,6 +64,8 @@ set(WARNING_FLAGS_GNU set(WARNINGS_FLAGS_IAR "") + +# Filter example based on only.txt and skip.txt function(family_filter RESULT DIR) get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR}) @@ -142,112 +144,136 @@ function(family_initialize_project PROJECT DIR) endfunction() -# Add segger rtt to example -function(family_add_segger_rtt TARGET) - if (NOT TARGET segger_rtt) - add_library(segger_rtt STATIC - ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - ) - target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT) - endif() +#------------------------------------------------------------- +# Common Target Configure +# Most families use these settings except rp2040 and espressif +#------------------------------------------------------------- + +# Add RTOS to example +function(family_add_rtos TARGET RTOS) + if (RTOS STREQUAL "freertos") + # freertos config + if (NOT TARGET freertos_config) + add_library(freertos_config INTERFACE) + target_include_directories(freertos_config INTERFACE ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig) + # add board definition to freertos_config mostly for SystemCoreClock + target_link_libraries(freertos_config INTERFACE board_${BOARD}) + endif() + + # freertos kernel + if (NOT TARGET freertos_kernel) + add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel) + endif () - target_link_libraries(${TARGET} PUBLIC segger_rtt) + target_link_libraries(${TARGET} PUBLIC freertos_kernel) + endif () endfunction() -#------------------------------------ -# Main target configure -#------------------------------------ # Add common configuration to example -function(family_configure_common TARGET) +function(family_configure_common TARGET RTOS) + family_add_rtos(${TARGET} ${RTOS}) + # run size after build add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_SIZE} $ ) + # Add warnings flags target_compile_options(${TARGET} PUBLIC ${WARNING_FLAGS_${CMAKE_C_COMPILER_ID}}) + # Generate linker map file if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - # Generate map file - target_link_options(${TARGET} PUBLIC - # link map - "LINKER:-Map=$.map" - ) + target_link_options(${TARGET} PUBLIC "LINKER:-Map=$.map") endif() - # LOGGER - if (DEFINED LOGGER) - target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER}) - if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt") - family_add_segger_rtt(${TARGET}) - endif () - endif () - - # ETM Trace + # ETM Trace option if (TRACE_ETM STREQUAL "1") target_compile_definitions(${TARGET} PUBLIC TRACE_ETM) endif () -endfunction() - - -# configure an executable target to link to tinyusb in device mode, and add the board implementation -function(family_configure_device_example TARGET) - # default implementation is empty, the function should be redefined in the FAMILY/family.cmake -endfunction() - + # LOGGER option + if (DEFINED LOGGER) + target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER}) -# configure an executable target to link to tinyusb in host mode, and add the board implementation -function(family_configure_host_example TARGET) - # default implementation is empty, the function should be redefined in the FAMILY/family.cmake + # Add segger rtt to example + if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt") + if (NOT TARGET segger_rtt) + add_library(segger_rtt STATIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c) + target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT) + endif() + target_link_libraries(${TARGET} PUBLIC segger_rtt) + endif () + endif () endfunction() # Add tinyusb to example -function(family_add_tinyusb TARGET OPT_MCU) +function(family_add_tinyusb TARGET OPT_MCU RTOS) # tinyusb target is built for each example since it depends on example's tusb_config.h set(TINYUSB_TARGET_PREFIX ${TARGET}-) add_library(${TARGET}-tinyusb_config INTERFACE) + # path to tusb_config.h target_include_directories(${TARGET}-tinyusb_config INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/src) target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_MCU=${OPT_MCU}) + if (DEFINED LOG) target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_DEBUG=${LOG}) endif() + if (RTOS STREQUAL "freertos") + target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_OS=OPT_OS_FREERTOS) + endif () + # tinyusb's CMakeList.txt add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) + + if (RTOS STREQUAL "freertos") + # link tinyusb with freeRTOS kernel + target_link_libraries(${TARGET}-tinyusb PUBLIC freertos_kernel) + endif () endfunction() -# Add freeRTOS support to example -function(family_add_freertos TARGET) - # freeros config - if (NOT TARGET freertos_config) - add_library(freertos_config INTERFACE) - target_include_directories(freertos_config INTERFACE - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig - ) - # add board definition to freertos_config mostly for SystemCoreClock - target_link_libraries(freertos_config INTERFACE board_${BOARD}) - endif() +# Add bin/hex output +function(family_add_bin_hex TARGET) + add_custom_command(TARGET ${TARGET} POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -Obinary $ $/${TARGET}.bin + COMMAND ${CMAKE_OBJCOPY} -Oihex $ $/${TARGET}.hex + VERBATIM) +endfunction() - # freertos kernel should be generic as freertos_config however, CMAKE complains with missing variable - # such as CMAKE_C_COMPILE_OBJECT - if (NOT TARGET freertos_kernel) - add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel) - endif () - # Add FreeRTOS option to tinyusb_config - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE - CFG_TUSB_OS=OPT_OS_FREERTOS - ) - # link tinyusb with freeRTOS kernel - target_link_libraries(${TARGET}-tinyusb PUBLIC freertos_kernel) - target_link_libraries(${TARGET} PUBLIC freertos_kernel) +#---------------------------------- +# Example Target Configure (Default rule) +# These function can be redefined in FAMILY/family.cmake +#---------------------------------- + +function(family_configure_example TARGET RTOS) + # empty function, should be redefined in FAMILY/family.cmake +endfunction() + +# Configure device example with RTOS +function(family_configure_device_example TARGET RTOS) + family_configure_example(${TARGET} ${RTOS}) +endfunction() + + +# Configure host example with RTOS +function(family_configure_host_example TARGET RTOS) + family_configure_example(${TARGET} ${RTOS}) endfunction() +# Configure host + device example with RTOS +function(family_configure_dual_usb_example TARGET RTOS) + family_configure_example(${TARGET} ${RTOS}) +endfunction() + +#---------------------------------- +# RPI specific: refactor later +#---------------------------------- function(family_add_default_example_warnings TARGET) target_compile_options(${TARGET} PUBLIC -Wall @@ -294,16 +320,6 @@ function(family_add_default_example_warnings TARGET) endif() endfunction() - -# Add bin/hex output -function(family_add_bin_hex TARGET) - add_custom_command(TARGET ${TARGET} POST_BUILD - COMMAND ${CMAKE_OBJCOPY} -Obinary $ $/${TARGET}.bin - COMMAND ${CMAKE_OBJCOPY} -Oihex $ $/${TARGET}.hex - VERBATIM) -endfunction() - - #---------------------------------- # Flashing target #---------------------------------- @@ -374,6 +390,10 @@ function(family_flash_nxplink TARGET) endfunction() +#---------------------------------- +# Family specific +#---------------------------------- + # family specific: can override above functions include(${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake) diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 4a9842cf9..aaedfc9d6 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -94,8 +94,8 @@ endfunction() #------------------------------------ # Functions #------------------------------------ -function(family_configure_example TARGET) - family_configure_common(${TARGET}) +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) # Board target add_board_target(board_${BOARD}) @@ -115,7 +115,7 @@ function(family_configure_example TARGET) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX) + family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -130,16 +130,3 @@ function(family_configure_example TARGET) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) endfunction() - - -function(family_configure_device_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_host_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_dual_usb_example TARGET) - family_configure_example(${TARGET}) -endfunction() diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake index 5d4165185..4df3d1ed1 100644 --- a/hw/bsp/kinetis_kl/family.cmake +++ b/hw/bsp/kinetis_kl/family.cmake @@ -78,8 +78,8 @@ endfunction() #------------------------------------ # Functions #------------------------------------ -function(family_configure_example TARGET) - family_configure_common(${TARGET}) +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) # Board target add_board_target(board_${BOARD}) @@ -99,7 +99,7 @@ function(family_configure_example TARGET) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_KL) + family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_KL ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c ${TOP}/src/portable/nxp/khci/hcd_khci.c @@ -113,16 +113,3 @@ function(family_configure_example TARGET) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) endfunction() - - -function(family_configure_device_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_host_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_dual_usb_example TARGET) - family_configure_example(${TARGET}) -endfunction() diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake index 4e6e2b56d..da71a0e5d 100644 --- a/hw/bsp/lpc18/family.cmake +++ b/hw/bsp/lpc18/family.cmake @@ -70,8 +70,8 @@ endfunction() #------------------------------------ # Functions #------------------------------------ -function(family_configure_example TARGET) - family_configure_common(${TARGET}) +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) # Board target add_board_target(board_${BOARD}) @@ -91,7 +91,7 @@ function(family_configure_example TARGET) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC18XX) + family_add_tinyusb(${TARGET} OPT_MCU_LPC18XX ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -106,16 +106,3 @@ function(family_configure_example TARGET) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) endfunction() - - -function(family_configure_device_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_host_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_dual_usb_example TARGET) - family_configure_example(${TARGET}) -endfunction() diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake index e443f47d3..dfd08a732 100644 --- a/hw/bsp/lpc55/family.cmake +++ b/hw/bsp/lpc55/family.cmake @@ -87,8 +87,8 @@ endfunction() #------------------------------------ # Functions #------------------------------------ -function(family_configure_example TARGET) - family_configure_common(${TARGET}) +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) # Board target add_board_target(board_${BOARD}) @@ -117,7 +117,7 @@ function(family_configure_example TARGET) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC55XX) + family_add_tinyusb(${TARGET} OPT_MCU_LPC55XX ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) @@ -131,16 +131,3 @@ function(family_configure_example TARGET) #family_flash_nxplink(${TARGET}) #family_flash_pyocd(${TARGET}) endfunction() - - -function(family_configure_device_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_host_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_dual_usb_example TARGET) - family_configure_example(${TARGET}) -endfunction() diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake index 83f44222b..f548ac4f3 100644 --- a/hw/bsp/mcx/family.cmake +++ b/hw/bsp/mcx/family.cmake @@ -79,8 +79,8 @@ endfunction() #------------------------------------ # Functions #------------------------------------ -function(family_configure_example TARGET) - family_configure_common(${TARGET}) +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) # Board target add_board_target(board_${BOARD}) @@ -100,7 +100,7 @@ function(family_configure_example TARGET) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MCXN9) + family_add_tinyusb(${TARGET} OPT_MCU_MCXN9 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS ${TOP}/src/portable/chipidea/$ @@ -115,16 +115,3 @@ function(family_configure_example TARGET) #family_flash_nxplink(${TARGET}) #family_flash_pyocd(${TARGET}) endfunction() - - -function(family_configure_device_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_host_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_dual_usb_example TARGET) - family_configure_example(${TARGET}) -endfunction() diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 825380d0b..30fd41d7b 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -97,8 +97,8 @@ endfunction() #------------------------------------ # Functions #------------------------------------ -function(family_configure_example TARGET) - family_configure_common(${TARGET}) +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) # Board target add_board_target(board_${BOARD}) @@ -118,7 +118,7 @@ function(family_configure_example TARGET) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_NRF5X) + family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c ) @@ -132,16 +132,3 @@ function(family_configure_example TARGET) # Flashing family_flash_jlink(${TARGET}) endfunction() - - -function(family_configure_device_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_host_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_dual_usb_example TARGET) - family_configure_example(${TARGET}) -endfunction() diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index 2d37f8be9..b986b3ebb 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -11,6 +11,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/pico_sdk_import.cmake) # include basic family CMake functionality set(FAMILY_MCUS RP2040) +set(JLINK_DEVICE rp2040_m0_0) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) @@ -143,12 +144,23 @@ endif() # Functions #------------------------------------ -function(family_configure_target TARGET) +function(family_configure_target TARGET RTOS) + if (RTOS STREQUAL noos OR RTOS STREQUAL "") + set(RTOS_SUFFIX "") + else() + set(RTOS_SUFFIX _${RTOS}) + endif() + # export RTOS_SUFFIX to parent scope + set(RTOS_SUFFIX ${RTOS_SUFFIX} PARENT_SCOPE) + pico_add_extra_outputs(${TARGET}) pico_enable_stdio_uart(${TARGET} 1) - target_link_libraries(${TARGET} PUBLIC pico_stdlib pico_bootsel_via_double_reset tinyusb_board tinyusb_additions) + target_link_libraries(${TARGET} PUBLIC pico_stdlib pico_bootsel_via_double_reset tinyusb_board${RTOS_SUFFIX} tinyusb_additions) + + family_flash_jlink(${TARGET}) endfunction() + function(rp2040_family_configure_example_warnings TARGET) if (NOT PICO_TINYUSB_NO_EXAMPLE_WARNINGS) family_add_default_example_warnings(${TARGET}) @@ -159,19 +171,22 @@ function(rp2040_family_configure_example_warnings TARGET) suppress_tinyusb_warnings() endfunction() -function(family_configure_device_example TARGET) - family_configure_target(${TARGET}) - target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device) + +function(family_configure_device_example TARGET RTOS) + family_configure_target(${TARGET} ${RTOS}) + target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device${RTOS_SUFFIX}) rp2040_family_configure_example_warnings(${TARGET}) endfunction() + function(family_add_pico_pio_usb TARGET) target_link_libraries(${TARGET} PUBLIC tinyusb_pico_pio_usb) endfunction() -function(family_configure_host_example TARGET) - family_configure_target(${TARGET}) - target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host) + +function(family_configure_host_example TARGET RTOS) + family_configure_target(${TARGET} ${RTOS}) + target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host${RTOS_SUFFIX}) rp2040_family_configure_example_warnings(${TARGET}) # For rp2040 enable pico-pio-usb @@ -183,13 +198,15 @@ function(family_configure_host_example TARGET) endif() endfunction() -function(family_configure_dual_usb_example TARGET) - family_configure_target(${TARGET}) + +function(family_configure_dual_usb_example TARGET RTOS) + family_configure_target(${TARGET} ${RTOS}) # require tinyusb_pico_pio_usb target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device tinyusb_host tinyusb_pico_pio_usb ) rp2040_family_configure_example_warnings(${TARGET}) endfunction() + function(check_and_add_pico_pio_usb_support) # check for pico_generate_pio_header (as depending on environment we may be called before SDK is # initialized in which case it isn't available yet), and only do the initialization once @@ -243,6 +260,7 @@ endfunction() # when included by the SDK itself) check_and_add_pico_pio_usb_support() + function(family_initialize_project PROJECT DIR) # call the original version of this function from family_common.cmake _family_initialize_project(${PROJECT} ${DIR}) @@ -253,6 +271,7 @@ function(family_initialize_project PROJECT DIR) check_and_add_pico_pio_usb_support() endfunction() + # This method must be called from the project scope to suppress known warnings in TinyUSB source files function(suppress_tinyusb_warnings) # some of these are pretty silly warnings only occurring in some older GCC versions 9 or prior @@ -327,7 +346,3 @@ function(suppress_tinyusb_warnings) COMPILE_FLAGS "-Wno-cast-qual") endif() endfunction() - -# rp2040 does not support freeRTOS example yet -function(family_add_freertos TARGET) -endfunction() diff --git a/hw/bsp/stm32f0/family.cmake b/hw/bsp/stm32f0/family.cmake index ecf6a8424..73f43de82 100644 --- a/hw/bsp/stm32f0/family.cmake +++ b/hw/bsp/stm32f0/family.cmake @@ -84,8 +84,8 @@ endfunction() #------------------------------------ # Functions #------------------------------------ -function(family_configure_example TARGET) - family_configure_common(${TARGET}) +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) # Board target add_board_target(board_${BOARD}) @@ -105,7 +105,7 @@ function(family_configure_example TARGET) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32F0) + family_add_tinyusb(${TARGET} OPT_MCU_STM32F0 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) @@ -118,16 +118,3 @@ function(family_configure_example TARGET) family_flash_stlink(${TARGET}) #family_flash_jlink(${TARGET}) endfunction() - - -function(family_configure_device_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_host_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_dual_usb_example TARGET) - family_configure_example(${TARGET}) -endfunction() diff --git a/hw/bsp/stm32f1/family.cmake b/hw/bsp/stm32f1/family.cmake index ab46c9872..efe41bc1b 100644 --- a/hw/bsp/stm32f1/family.cmake +++ b/hw/bsp/stm32f1/family.cmake @@ -81,8 +81,8 @@ endfunction() #------------------------------------ # Functions #------------------------------------ -function(family_configure_example TARGET) - family_configure_common(${TARGET}) +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) # Board target add_board_target(board_${BOARD}) @@ -102,7 +102,7 @@ function(family_configure_example TARGET) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32F1) + family_add_tinyusb(${TARGET} OPT_MCU_STM32F1 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) @@ -115,16 +115,3 @@ function(family_configure_example TARGET) family_flash_stlink(${TARGET}) #family_flash_jlink(${TARGET}) endfunction() - - -function(family_configure_device_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_host_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_dual_usb_example TARGET) - family_configure_example(${TARGET}) -endfunction() diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake index 3b6ba1a15..30bde9b0d 100644 --- a/hw/bsp/stm32f7/family.cmake +++ b/hw/bsp/stm32f7/family.cmake @@ -86,8 +86,8 @@ endfunction() #------------------------------------ # Functions #------------------------------------ -function(family_configure_example TARGET) - family_configure_common(${TARGET}) +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) # Board target add_board_target(board_${BOARD}) @@ -107,7 +107,7 @@ function(family_configure_example TARGET) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32F7) + family_add_tinyusb(${TARGET} OPT_MCU_STM32F7 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ) @@ -120,16 +120,3 @@ function(family_configure_example TARGET) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() - - -function(family_configure_device_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_host_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_dual_usb_example TARGET) - family_configure_example(${TARGET}) -endfunction() diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake index fa93566bf..f7b665090 100644 --- a/hw/bsp/stm32g0/family.cmake +++ b/hw/bsp/stm32g0/family.cmake @@ -84,8 +84,8 @@ endfunction() #------------------------------------ # Functions #------------------------------------ -function(family_configure_example TARGET) - family_configure_common(${TARGET}) +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) # Board target add_board_target(board_${BOARD}) @@ -105,7 +105,7 @@ function(family_configure_example TARGET) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32G0) + family_add_tinyusb(${TARGET} OPT_MCU_STM32G0 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/st/typec/typec_stm32.c @@ -119,16 +119,3 @@ function(family_configure_example TARGET) family_flash_stlink(${TARGET}) #family_flash_jlink(${TARGET}) endfunction() - - -function(family_configure_device_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_host_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_dual_usb_example TARGET) - family_configure_example(${TARGET}) -endfunction() diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake index c89993f6d..3c7633d64 100644 --- a/hw/bsp/stm32g4/family.cmake +++ b/hw/bsp/stm32g4/family.cmake @@ -84,8 +84,8 @@ endfunction() #------------------------------------ # Functions #------------------------------------ -function(family_configure_example TARGET) - family_configure_common(${TARGET}) +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) # Board target add_board_target(board_${BOARD}) @@ -105,7 +105,7 @@ function(family_configure_example TARGET) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32G4) + family_add_tinyusb(${TARGET} OPT_MCU_STM32G4 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/st/typec/typec_stm32.c @@ -119,16 +119,3 @@ function(family_configure_example TARGET) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() - - -function(family_configure_device_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_host_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_dual_usb_example TARGET) - family_configure_example(${TARGET}) -endfunction() diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake index f3705edb4..1a8c4354c 100644 --- a/hw/bsp/stm32h7/family.cmake +++ b/hw/bsp/stm32h7/family.cmake @@ -89,8 +89,8 @@ endfunction() #------------------------------------ # Functions #------------------------------------ -function(family_configure_example TARGET) - family_configure_common(${TARGET}) +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) # Board target add_board_target(board_${BOARD}) @@ -110,7 +110,7 @@ function(family_configure_example TARGET) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32H7) + family_add_tinyusb(${TARGET} OPT_MCU_STM32H7 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ) @@ -123,16 +123,3 @@ function(family_configure_example TARGET) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() - - -function(family_configure_device_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_host_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_dual_usb_example TARGET) - family_configure_example(${TARGET}) -endfunction() diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake index 83c51c9bf..da017cdde 100644 --- a/hw/bsp/stm32l4/family.cmake +++ b/hw/bsp/stm32l4/family.cmake @@ -86,8 +86,8 @@ endfunction() #------------------------------------ # Functions #------------------------------------ -function(family_configure_example TARGET) - family_configure_common(${TARGET}) +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) # Board target add_board_target(board_${BOARD}) @@ -107,7 +107,7 @@ function(family_configure_example TARGET) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS}) + family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS} ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -121,16 +121,3 @@ function(family_configure_example TARGET) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() - - -function(family_configure_device_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_host_example TARGET) - family_configure_example(${TARGET}) -endfunction() - -function(family_configure_dual_usb_example TARGET) - family_configure_example(${TARGET}) -endfunction() diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index 5ab56e145..6f07bdd53 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -128,7 +128,9 @@ #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name))) #define TU_ATTR_PACKED __attribute__ ((packed)) #define TU_ATTR_WEAK __attribute__ ((weak)) - #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) + #ifndef TU_ATTR_ALWAYS_INLINE // allow to override for debug + #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) + #endif #define TU_ATTR_DEPRECATED(mess) __attribute__ ((deprecated(mess))) // warn if function with this attribute is used #define TU_ATTR_UNUSED __attribute__ ((unused)) // Function/Variable is meant to be possibly unused #define TU_ATTR_USED __attribute__ ((used)) // Function/Variable is meant to be used @@ -205,7 +207,9 @@ #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name))) #define TU_ATTR_PACKED __attribute__ ((packed)) #define TU_ATTR_WEAK __attribute__ ((weak)) - #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) + #ifndef TU_ATTR_ALWAYS_INLINE // allow to override for debug + #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) + #endif #define TU_ATTR_DEPRECATED(mess) __attribute__ ((deprecated(mess))) // warn if function with this attribute is used #define TU_ATTR_UNUSED __attribute__ ((unused)) // Function/Variable is meant to be possibly unused #define TU_ATTR_USED __attribute__ ((used)) // Function/Variable is meant to be used diff --git a/test/fuzz/device/cdc/CMakeLists.txt b/test/fuzz/device/cdc/CMakeLists.txt index 8e4db9d29..c60f292b9 100644 --- a/test/fuzz/device/cdc/CMakeLists.txt +++ b/test/fuzz/device/cdc/CMakeLists.txt @@ -14,16 +14,16 @@ add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c + ) # Example include target_include_directories(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/test/fuzz/device/msc/CMakeLists.txt b/test/fuzz/device/msc/CMakeLists.txt index 8e4db9d29..8bff217cb 100644 --- a/test/fuzz/device/msc/CMakeLists.txt +++ b/test/fuzz/device/msc/CMakeLists.txt @@ -24,6 +24,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) diff --git a/test/fuzz/device/net/CMakeLists.txt b/test/fuzz/device/net/CMakeLists.txt index 8e4db9d29..8bff217cb 100644 --- a/test/fuzz/device/net/CMakeLists.txt +++ b/test/fuzz/device/net/CMakeLists.txt @@ -24,6 +24,6 @@ target_include_directories(${PROJECT} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT}) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} noos) -- cgit v1.3.1 From 98fb10a724a33b545990a8593f60b5f10f030f5d Mon Sep 17 00:00:00 2001 From: Devin Auclair Date: Wed, 28 Jun 2023 14:03:18 -0400 Subject: Fix minor spelling --- src/class/msc/msc.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/class/msc/msc.h b/src/class/msc/msc.h index 7f25a29ba..bbfd35a43 100644 --- a/src/class/msc/msc.h +++ b/src/class/msc/msc.h @@ -53,7 +53,7 @@ enum { }; /// \brief MassStorage Protocol. -/// \details CBI only approved to use with full-speed floopy disk & should not used with highspeed or device other than floopy +/// \details CBI only approved to use with full-speed floppy disk & should not used with highspeed or device other than floppy typedef enum { MSC_PROTOCOL_CBI = 0 , ///< Control/Bulk/Interrupt protocol (with command completion interrupt) @@ -97,7 +97,7 @@ typedef struct TU_ATTR_PACKED { uint32_t signature ; ///< Signature that helps identify this data packet as a CSW. The signature field shall contain the value 53425355h (little endian), indicating CSW. uint32_t tag ; ///< The device shall set this field to the value received in the dCBWTag of the associated CBW. - uint32_t data_residue ; ///< For Data-Out the device shall report in the dCSWDataResiduethe difference between the amount of data expected as stated in the dCBWDataTransferLength, and the actual amount of data processed by the device. For Data-In the device shall report in the dCSWDataResiduethe difference between the amount of data expected as stated in the dCBWDataTransferLengthand the actual amount of relevant data sent by the device + uint32_t data_residue ; ///< For Data-Out the device shall report in the dCSWDataResidue the difference between the amount of data expected as stated in the dCBWDataTransferLength, and the actual amount of data processed by the device. For Data-In the device shall report in the dCSWDataResiduethe difference between the amount of data expected as stated in the dCBWDataTransferLengthand the actual amount of relevant data sent by the device uint8_t status ; ///< indicates the success or failure of the command. Values from \ref msc_csw_status_t }msc_csw_t; @@ -120,14 +120,14 @@ typedef enum SCSI_CMD_REQUEST_SENSE = 0x03, ///< The SCSI Request Sense command is part of the SCSI computer protocol standard. This command is used to obtain sense data -- status/error information -- from a target device. SCSI_CMD_READ_FORMAT_CAPACITY = 0x23, ///< The command allows the Host to request a list of the possible format capacities for an installed writable media. This command also has the capability to report the writable capacity for a media when it is installed SCSI_CMD_READ_10 = 0x28, ///< The READ (10) command requests that the device server read the specified logical block(s) and transfer them to the data-in buffer. - SCSI_CMD_WRITE_10 = 0x2A, ///< The WRITE (10) command requests thatthe device server transfer the specified logical block(s) from the data-out buffer and write them. + SCSI_CMD_WRITE_10 = 0x2A, ///< The WRITE (10) command requests that the device server transfer the specified logical block(s) from the data-out buffer and write them. }scsi_cmd_type_t; /// SCSI Sense Key typedef enum { SCSI_SENSE_NONE = 0x00, ///< no specific Sense Key. This would be the case for a successful command - SCSI_SENSE_RECOVERED_ERROR = 0x01, ///< ndicates the last command completed successfully with some recovery action performed by the disc drive. + SCSI_SENSE_RECOVERED_ERROR = 0x01, ///< Indicates the last command completed successfully with some recovery action performed by the disc drive. SCSI_SENSE_NOT_READY = 0x02, ///< Indicates the logical unit addressed cannot be accessed. SCSI_SENSE_MEDIUM_ERROR = 0x03, ///< Indicates the command terminated with a non-recovered error condition. SCSI_SENSE_HARDWARE_ERROR = 0x04, ///< Indicates the disc drive detected a nonrecoverable hardware failure while performing the command or during a self test. @@ -138,7 +138,7 @@ typedef enum SCSI_SENSE_ABORTED_COMMAND = 0x0b, ///< Indicates the disc drive aborted the command. SCSI_SENSE_EQUAL = 0x0c, ///< Indicates a SEARCH DATA command has satisfied an equal comparison. SCSI_SENSE_VOLUME_OVERFLOW = 0x0d, ///< Indicates a buffered peripheral device has reached the end of medium partition and data remains in the buffer that has not been written to the medium. - SCSI_SENSE_MISCOMPARE = 0x0e ///< ndicates that the source data did not match the data read from the medium. + SCSI_SENSE_MISCOMPARE = 0x0e ///< Indicates that the source data did not match the data read from the medium. }scsi_sense_key_type_t; //--------------------------------------------------------------------+ -- cgit v1.3.1 From 11fba59319d81fb9502fbf399abb4fe27cf3fa29 Mon Sep 17 00:00:00 2001 From: Dave Nadler Date: Wed, 28 Jun 2023 17:25:22 -0400 Subject: Name queues for easier FreeRTOS debugging with task- and queue-aware debuggers --- src/device/usbd.c | 4 ++-- src/host/usbh.c | 4 ++-- src/osal/osal_freertos.h | 5 +++-- 3 files changed, 7 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index 44c2530ce..b6c679b22 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -279,7 +279,7 @@ tu_static uint8_t _usbd_rhport = RHPORT_INVALID; // Event queue // usbd_int_set() is used as mutex in OS NONE config -OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t); +OSAL_QUEUE_DEF(usbd_int_set, usbd_events, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t); tu_static osal_queue_t _usbd_q; // Mutex for claiming endpoint @@ -410,7 +410,7 @@ bool tud_init (uint8_t rhport) #endif // Init device queue & task - _usbd_q = osal_queue_create(&_usbd_qdef); + _usbd_q = osal_queue_create(&usbd_events); TU_ASSERT(_usbd_q); // Get application driver if available diff --git a/src/host/usbh.c b/src/host/usbh.c index f3e9d3858..987ff7a6e 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -219,7 +219,7 @@ static usbh_device_t _usbh_devices[TOTAL_DEVICES]; // Event queue // usbh_int_set is used as mutex in OS NONE config -OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t); +OSAL_QUEUE_DEF(usbh_int_set, usbh_events, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t); static osal_queue_t _usbh_q; CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN @@ -330,7 +330,7 @@ bool tuh_init(uint8_t controller_id) TU_LOG_INT(USBH_DEBUG, sizeof(tu_edpt_stream_t)); // Event queue - _usbh_q = osal_queue_create( &_usbh_qdef ); + _usbh_q = osal_queue_create( &usbh_events ); TU_ASSERT(_usbh_q != NULL); #if OSAL_MUTEX_REQUIRED diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index 0b1b11589..e83277eb3 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -56,7 +56,7 @@ typedef SemaphoreHandle_t osal_mutex_t; // _int_set is not used with an RTOS #define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \ static _type _name##_##buf[_depth];\ - osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf }; + osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, .pQueueName = #_name }; typedef struct { @@ -66,6 +66,7 @@ typedef struct #if configSUPPORT_STATIC_ALLOCATION StaticQueue_t sq; #endif + const char* pQueueName; }osal_queue_def_t; typedef QueueHandle_t osal_queue_t; @@ -176,7 +177,7 @@ TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_de q = xQueueCreate(qdef->depth, qdef->item_sz); #endif #if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0) - vQueueAddToRegistry(q, "tinyUSB"); + vQueueAddToRegistry(q, qdef->pQueueName); #endif return q; } -- cgit v1.3.1 From 6284f2d72287396a0df153a0a7bd192c4e3847a7 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 29 Jun 2023 18:58:33 +0700 Subject: add hcd_frame_number() for pio-usb host --- .gitmodules | 0 hw/bsp/rp2040/board.h | 4 +++- src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 2 +- tools/get_deps.py | 2 +- 4 files changed, 5 insertions(+), 3 deletions(-) delete mode 100644 .gitmodules (limited to 'src') diff --git a/.gitmodules b/.gitmodules deleted file mode 100644 index e69de29bb..000000000 diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h index ccad00c4a..934e1c7ae 100644 --- a/hw/bsp/rp2040/board.h +++ b/hw/bsp/rp2040/board.h @@ -49,7 +49,10 @@ #define UART_RX_PIN PICO_DEFAULT_UART_RX_PIN #endif +//--------------------------------------------------------------------+ // PIO_USB +// default to pin on Adafruit Feather rp2040 USB Host or Tester if defined +//--------------------------------------------------------------------+ // #define USE_ADAFRUIT_RP2040_TESTER #ifdef USE_ADAFRUIT_RP2040_TESTER @@ -57,7 +60,6 @@ #define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 22 #endif -// following default to pin on Adafruit Feather rp2040 USB Host #ifndef PICO_DEFAULT_PIO_USB_DP_PIN #define PICO_DEFAULT_PIO_USB_DP_PIN 16 #endif diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c index 58b153ac3..264af2e7a 100644 --- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c @@ -105,7 +105,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) uint32_t hcd_frame_number(uint8_t rhport) { (void) rhport; - return 0; + return pio_usb_host_get_frame_number(); } void hcd_int_enable(uint8_t rhport) diff --git a/tools/get_deps.py b/tools/get_deps.py index 34e2f30a3..9b89c5e4c 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -54,7 +54,7 @@ deps_optional = { '950819b7de9b32f92c3edf396bc5ffb8d66e7009', 'kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'], 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git', - 'c3715ce94b6f6391856de56081d4d9b3e98fa93d', + '58879cfa0eca5725d8db6443ec17f8896a321042', 'rp2040'], 'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git', '8dc14709f2a6518b43f71efad70d900b7718d9f1', -- cgit v1.3.1 From 99e75e6a8a0de9903e574a51d6ce8057a1e3e73f Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 1 Jul 2023 12:40:56 +0700 Subject: rework ra build --- .github/workflows/cmake_arm.yml | 1 + hw/bsp/ra/boards/ra4m1_ek/board.cmake | 15 ++ hw/bsp/ra/boards/ra4m1_ek/board.h | 53 +++++ hw/bsp/ra/boards/ra4m1_ek/board.mk | 7 - hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h | 6 +- .../boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h | 5 + hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c | 232 -------------------- hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld | 1 + hw/bsp/ra/boards/ra4m3_ek/board.cmake | 15 ++ hw/bsp/ra/boards/ra4m3_ek/board.h | 52 +++++ hw/bsp/ra/boards/ra4m3_ek/board.mk | 7 - hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h | 4 +- hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c | 236 --------------------- hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld | 1 + hw/bsp/ra/family.c | 231 ++++++++++++++++++++ hw/bsp/ra/family.cmake | 114 ++++++++++ hw/bsp/ra/family.mk | 2 +- src/portable/renesas/rusb2/rusb2_ra.h | 12 ++ 18 files changed, 509 insertions(+), 485 deletions(-) create mode 100644 hw/bsp/ra/boards/ra4m1_ek/board.cmake create mode 100644 hw/bsp/ra/boards/ra4m1_ek/board.h delete mode 100644 hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c create mode 100644 hw/bsp/ra/boards/ra4m3_ek/board.cmake create mode 100644 hw/bsp/ra/boards/ra4m3_ek/board.h delete mode 100644 hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c create mode 100644 hw/bsp/ra/family.c create mode 100644 hw/bsp/ra/family.cmake (limited to 'src') diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml index 0ce63281e..4d8cd5591 100644 --- a/.github/workflows/cmake_arm.yml +++ b/.github/workflows/cmake_arm.yml @@ -38,6 +38,7 @@ jobs: - 'lpc18' - 'lpc55' - 'mcx' + - 'ra' - 'rp2040' - 'stm32f0' - 'stm32f1' diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.cmake b/hw/bsp/ra/boards/ra4m1_ek/board.cmake new file mode 100644 index 000000000..37c39061d --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/board.cmake @@ -0,0 +1,15 @@ +set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(MCU_VARIANT ra4m1) + +set(JLINK_DEVICE R7FA4M1AB) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/ra4m1_ek.ld) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + ) + target_sources(${TARGET} PRIVATE + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ) +endfunction() diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.h b/hw/bsp/ra/boards/ra4m1_ek/board.h new file mode 100644 index 000000000..383ab7399 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/board.h @@ -0,0 +1,53 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define LED1 (BSP_IO_PORT_01_PIN_06) +#define LED_STATE_ON 1 + +#define SW1 (BSP_IO_PORT_01_PIN_05) +#define BUTTON_STATE_ACTIVE 0 + +const ioport_pin_cfg_t board_pin_cfg[] = { + { .pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) }, + { .pin = SW1 , .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) }, + + { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) }, + { .pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) }, + { .pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) }, +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.mk b/hw/bsp/ra/boards/ra4m1_ek/board.mk index eae68f87d..9b0fafb28 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/board.mk +++ b/hw/bsp/ra/boards/ra4m1_ek/board.mk @@ -3,13 +3,6 @@ MCU_VARIANT = ra4m1 FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m1_ek -SRC_C += \ - $(FSP_BOARD_DIR)/board_init.c \ - $(FSP_BOARD_DIR)/board_leds.c \ - -INC += \ - $(TOP)/$(FSP_BOARD_DIR) - # All source paths should be relative to the top level. LD_FILE = $(BOARD_PATH)/ra4m1_ek.ld diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h index b38a79b40..b337e49f2 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h @@ -2,7 +2,6 @@ #ifndef BSP_CFG_H_ #define BSP_CFG_H_ -#include "board.h" #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" @@ -32,4 +31,9 @@ #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#define BSP_FEATURE_TFU_SUPPORTED 0 + +// for SystemInit() +void bsp_init(void * p_args); + #endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h index 3bde2db0d..4e080023e 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h @@ -25,6 +25,11 @@ #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) +#define BSP_TZ_SECURE_BUILD (0) +#define BSP_TZ_NONSECURE_BUILD (0) + +#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0 + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c b/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c deleted file mode 100644 index ea2204837..000000000 --- a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2022, Rafael Silva - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include - -#include "bsp/board.h" -#include "bsp_api.h" -#include "r_ioport.h" -#include "r_ioport_api.h" -#include "renesas.h" - -/* Key code for writing PRCR register. */ -#define BSP_PRV_PRCR_KEY (0xA500U) -#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U) -#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) - -#define SW1 (BSP_IO_PORT_01_PIN_05) -#define LED1 (BSP_IO_PORT_01_PIN_06) - -#define LED_STATE_ON 1 -#define BUTTON_STATE_ACTIVE 0 - -/* ISR prototypes */ -void usbfs_interrupt_handler(void); -void usbfs_resume_handler(void); -void usbfs_d0fifo_handler(void); -void usbfs_d1fifo_handler(void); - -BSP_DONT_REMOVE const - fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = { - [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */ - [1] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */ - [2] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */ - [3] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */ -}; -const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = { - [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */ - [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */ - [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */ - [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1) /* USBFS FIFO 1 (DMA transfer request 1) */ -}; - -const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { - { .pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) }, - { .pin = SW1 , .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) }, - - { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) }, - { .pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) }, - { .pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) }, - -}; - -const ioport_cfg_t g_bsp_pin_cfg = { - .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), - .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], -}; -ioport_instance_ctrl_t g_ioport_ctrl; -const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg}; - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void usbfs_interrupt_handler(void) -{ - IRQn_Type irq = R_FSP_CurrentIrqGet(); - R_BSP_IrqStatusClear(irq); - -#if CFG_TUH_ENABLED - tuh_int_handler(0); -#endif - -#if CFG_TUD_ENABLED - tud_int_handler(0); -#endif -} - -void usbfs_resume_handler(void) -{ - IRQn_Type irq = R_FSP_CurrentIrqGet(); - R_BSP_IrqStatusClear(irq); - -#if CFG_TUH_ENABLED - tuh_int_handler(0); -#endif - -#if CFG_TUD_ENABLED - tud_int_handler(0); -#endif -} - -void usbfs_d0fifo_handler(void) -{ - IRQn_Type irq = R_FSP_CurrentIrqGet(); - R_BSP_IrqStatusClear(irq); - -#if CFG_TUH_ENABLED - tuh_int_handler(0); -#endif - -#if CFG_TUD_ENABLED - tud_int_handler(0); -#endif -} - -void usbfs_d1fifo_handler(void) -{ - IRQn_Type irq = R_FSP_CurrentIrqGet(); - R_BSP_IrqStatusClear(irq); - -#if CFG_TUH_ENABLED - tuh_int_handler(0); -#endif - -#if CFG_TUD_ENABLED - tud_int_handler(0); -#endif -} - -void board_init(void) -{ - /* Configure pins. */ - R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg); - - /* Enable USB_BASE */ - R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK; - R_MSTP->MSTPCRB &= ~(1U << 11U); - R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; - -#if CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); - NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); - NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); - NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#endif - -#if CFG_TUSB_OS == OPT_OS_NONE - /* Init systick */ - SysTick_Config(SystemCoreClock / 1000); -#endif -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON); -} - -uint32_t board_button_read(void) -{ - bsp_io_level_t lvl; - R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl); - return lvl == BUTTON_STATE_ACTIVE; -} - -int board_uart_read(uint8_t *buf, int len) -{ - (void) buf; - (void) len; - return 0; -} - -int board_uart_write(void const *buf, int len) -{ - (void) buf; - (void) len; - return 0; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler(void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#else -#endif - -int close(int fd) -{ - (void) fd; - return -1; -} -int fstat(int fd, void *pstat) -{ - (void) fd; - (void) pstat; - return 0; -} -off_t lseek(int fd, off_t pos, int whence) -{ - (void) fd; - (void) pos; - (void) whence; - return 0; -} -int isatty(int fd) -{ - (void) fd; - return 1; -} diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld b/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld index 8ddaa0a97..63c1d33aa 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld +++ b/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld @@ -553,6 +553,7 @@ SECTIONS { . = ALIGN(8); __HeapBase = .; + PROVIDE(end = .); /* Place the STD heap here. */ KEEP(*(.heap)) __HeapLimit = .; diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.cmake b/hw/bsp/ra/boards/ra4m3_ek/board.cmake new file mode 100644 index 000000000..241b659a0 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/board.cmake @@ -0,0 +1,15 @@ +set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(MCU_VARIANT ra4m3) + +set(JLINK_DEVICE R7FA4M3AF) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/ra4m3_ek.ld) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + ) + target_sources(${TARGET} PRIVATE + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ) +endfunction() diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.h b/hw/bsp/ra/boards/ra4m3_ek/board.h new file mode 100644 index 000000000..e41302f90 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/board.h @@ -0,0 +1,52 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define LED1 (BSP_IO_PORT_04_PIN_15) +#define LED_STATE_ON 1 + +#define SW1 (BSP_IO_PORT_00_PIN_05) +#define BUTTON_STATE_ACTIVE 0 + +const ioport_pin_cfg_t board_pin_cfg[] = { + {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)}, + {.pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)}, + {.pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)}, + {.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)}, + {.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}, +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.mk b/hw/bsp/ra/boards/ra4m3_ek/board.mk index 4ca1d365e..266de7c0d 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/board.mk +++ b/hw/bsp/ra/boards/ra4m3_ek/board.mk @@ -3,13 +3,6 @@ MCU_VARIANT = ra4m3 FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m3_ek -SRC_C += \ - $(FSP_BOARD_DIR)/board_init.c \ - $(FSP_BOARD_DIR)/board_leds.c \ - -INC += \ - $(TOP)/$(FSP_BOARD_DIR) - # All source paths should be relative to the top level. LD_FILE = $(BOARD_PATH)/ra4m3_ek.ld diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h index a84d81e8d..a9cb8210b 100755 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h @@ -2,7 +2,6 @@ #ifndef BSP_CFG_H_ #define BSP_CFG_H_ -#include "board.h" #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" @@ -32,4 +31,7 @@ #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +// for SystemInit() +void bsp_init(void * p_args); + #endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c b/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c deleted file mode 100644 index 327ef71d5..000000000 --- a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2022, Rafael Silva - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include - -#include "bsp/board.h" -#include "bsp_api.h" -#include "r_ioport.h" -#include "r_ioport_api.h" -#include "renesas.h" - -/* Key code for writing PRCR register. */ -#define BSP_PRV_PRCR_KEY (0xA500U) -#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U) -#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) - -#define SW1 (BSP_IO_PORT_00_PIN_05) -#define SW2 (BSP_IO_PORT_00_PIN_06) -#define LED1 (BSP_IO_PORT_04_PIN_15) -#define LED3 (BSP_IO_PORT_04_PIN_00) -#define LED2 (BSP_IO_PORT_04_PIN_04) - -/* ISR prototypes */ -void usbfs_interrupt_handler(void); -void usbfs_resume_handler(void); -void usbfs_d0fifo_handler(void); -void usbfs_d1fifo_handler(void); - -BSP_DONT_REMOVE const - fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = { - [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */ - [1] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */ - [2] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */ - [3] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */ -}; -const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = { - [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */ - [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */ - [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */ - [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1) /* USBFS FIFO 1 (DMA transfer request 1) */ -}; - -const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { - {.pin = BSP_IO_PORT_04_PIN_07, - .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)}, - {.pin = BSP_IO_PORT_05_PIN_00, - .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)}, - {.pin = BSP_IO_PORT_05_PIN_01, - .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)}, - {.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)}, - {.pin = LED2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)}, - {.pin = LED3, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)}, - {.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}, - {.pin = SW2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}}; - -const ioport_cfg_t g_bsp_pin_cfg = { - .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), - .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], -}; -ioport_instance_ctrl_t g_ioport_ctrl; -const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg}; - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void usbfs_interrupt_handler(void) -{ - IRQn_Type irq = R_FSP_CurrentIrqGet(); - R_BSP_IrqStatusClear(irq); - -#if CFG_TUH_ENABLED - tuh_int_handler(0); -#endif - -#if CFG_TUD_ENABLED - tud_int_handler(0); -#endif -} -void usbfs_resume_handler(void) -{ - IRQn_Type irq = R_FSP_CurrentIrqGet(); - R_BSP_IrqStatusClear(irq); - -#if CFG_TUH_ENABLED - tuh_int_handler(0); -#endif - -#if CFG_TUD_ENABLED - tud_int_handler(0); -#endif -} - -void usbfs_d0fifo_handler(void) -{ - IRQn_Type irq = R_FSP_CurrentIrqGet(); - R_BSP_IrqStatusClear(irq); - -#if CFG_TUH_ENABLED - tuh_int_handler(0); -#endif - -#if CFG_TUD_ENABLED - tud_int_handler(0); -#endif -} - -void usbfs_d1fifo_handler(void) -{ - IRQn_Type irq = R_FSP_CurrentIrqGet(); - R_BSP_IrqStatusClear(irq); - -#if CFG_TUH_ENABLED - tuh_int_handler(0); -#endif - -#if CFG_TUD_ENABLED - tud_int_handler(0); -#endif -} - -void board_init(void) -{ - /* Configure pins. */ - R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg); - - /* Enable USB_BASE */ - R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK; - R_MSTP->MSTPCRB &= ~(1U << 11U); - R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; - -#if CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); - NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); - NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); - NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#endif - -#if CFG_TUSB_OS == OPT_OS_NONE - /* Init systick */ - SysTick_Config(SystemCoreClock / 1000); -#endif -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state); - R_IOPORT_PinWrite(&g_ioport_ctrl, LED2, state); - R_IOPORT_PinWrite(&g_ioport_ctrl, LED3, state); -} - -uint32_t board_button_read(void) -{ - bsp_io_level_t lvl; - R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl); - return lvl; -} - -int board_uart_read(uint8_t *buf, int len) -{ - (void) buf; - (void) len; - return 0; -} - -int board_uart_write(void const *buf, int len) -{ - (void) buf; - (void) len; - return 0; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler(void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#else -#endif - -int close(int fd) -{ - (void) fd; - return -1; -} -int fstat(int fd, void *pstat) -{ - (void) fd; - (void) pstat; - return 0; -} -off_t lseek(int fd, off_t pos, int whence) -{ - (void) fd; - (void) pos; - (void) whence; - return 0; -} -int isatty(int fd) -{ - (void) fd; - return 1; -} diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld b/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld index 5bc335cb4..520b44cc6 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld +++ b/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld @@ -413,6 +413,7 @@ SECTIONS { . = ALIGN(8); __HeapBase = .; + PROVIDE(end = .); /* Place the STD heap here. */ KEEP(*(.heap)) __HeapLimit = .; diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c new file mode 100644 index 000000000..42cb2d4a4 --- /dev/null +++ b/hw/bsp/ra/family.c @@ -0,0 +1,231 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2022, Rafael Silva + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-prototypes" +#pragma GCC diagnostic ignored "-Wundef" + +// extra push due to https://github.com/renesas/fsp/pull/278 +#pragma GCC diagnostic push +#endif + +#include "bsp_api.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "r_ioport.h" +#include "r_ioport_api.h" +#include "renesas.h" + +#include "bsp/board.h" +#include "board.h" + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) + +/* ISR prototypes */ +void usbfs_interrupt_handler(void); +void usbfs_resume_handler(void); +void usbfs_d0fifo_handler(void); +void usbfs_d1fifo_handler(void); + +BSP_DONT_REMOVE const +fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = { + [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */ + [1] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */ + [2] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */ + [3] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */ +}; +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = { + [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */ + [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */ + [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */ + [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1) /* USBFS FIFO 1 (DMA transfer request 1) */ +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = board_pin_cfg, +}; +ioport_instance_ctrl_t g_ioport_ctrl; +//const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg}; + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void usbfs_interrupt_handler(void) +{ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + +#if CFG_TUH_ENABLED + tuh_int_handler(0); +#endif + +#if CFG_TUD_ENABLED + tud_int_handler(0); +#endif +} + +void usbfs_resume_handler(void) +{ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + +#if CFG_TUH_ENABLED + tuh_int_handler(0); +#endif + +#if CFG_TUD_ENABLED + tud_int_handler(0); +#endif +} + +void usbfs_d0fifo_handler(void) +{ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + +#if CFG_TUH_ENABLED + tuh_int_handler(0); +#endif + +#if CFG_TUD_ENABLED + tud_int_handler(0); +#endif +} + +void usbfs_d1fifo_handler(void) +{ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + +#if CFG_TUH_ENABLED + tuh_int_handler(0); +#endif + +#if CFG_TUD_ENABLED + tud_int_handler(0); +#endif +} + +void board_init(void) +{ + /* Configure pins. */ + R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg); + + /* Enable USB_BASE */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK; + R_MSTP->MSTPCRB &= ~(1U << 11U); + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; + +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + +#if CFG_TUSB_OS == OPT_OS_NONE + /* Init systick */ + SysTick_Config(SystemCoreClock / 1000); +#endif +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON); +} + +uint32_t board_button_read(void) +{ + bsp_io_level_t lvl; + R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl); + return lvl == BUTTON_STATE_ACTIVE; +} + +int board_uart_read(uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif + +int close(int fd) +{ + (void) fd; + return -1; +} +int fstat(int fd, void *pstat) +{ + (void) fd; + (void) pstat; + return 0; +} +off_t lseek(int fd, off_t pos, int whence) +{ + (void) fd; + (void) pos; + (void) whence; + return 0; +} +int isatty(int fd) +{ + (void) fd; + return 1; +} diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake new file mode 100644 index 000000000..c4c25bf4f --- /dev/null +++ b/hw/bsp/ra/family.cmake @@ -0,0 +1,114 @@ +include_guard() + +if (NOT BOARD) + message(FATAL_ERROR "BOARD not specified") +endif () + +set(CMSIS_DIR ${TOP}/lib/CMSIS_5) +set(FSP_RA ${TOP}/hw/mcu/renesas/fsp/ra/fsp) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS RA CACHE INTERNAL "") + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (NOT TARGET ${BOARD_TARGET}) + add_library(${BOARD_TARGET} STATIC + ${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Source/startup.c + ${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Source/system.c + ${FSP_RA}/src/bsp/mcu/all/bsp_clocks.c + ${FSP_RA}/src/bsp/mcu/all/bsp_common.c + ${FSP_RA}/src/bsp/mcu/all/bsp_delay.c + ${FSP_RA}/src/bsp/mcu/all/bsp_group_irq.c + ${FSP_RA}/src/bsp/mcu/all/bsp_guard.c + ${FSP_RA}/src/bsp/mcu/all/bsp_io.c + ${FSP_RA}/src/bsp/mcu/all/bsp_irq.c + ${FSP_RA}/src/bsp/mcu/all/bsp_register_protection.c + ${FSP_RA}/src/bsp/mcu/all/bsp_rom_registers.c + ${FSP_RA}/src/bsp/mcu/all/bsp_sbrk.c + ${FSP_RA}/src/bsp/mcu/all/bsp_security.c + ${FSP_RA}/src/r_ioport/r_ioport.c + ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + _RA_TZ_NONSECURE + ) + + target_compile_options(${BOARD_TARGET} PUBLIC + -ffreestanding + ) + + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg + ${CMSIS_DIR}/CMSIS/Core/Include + ${FSP_RA}/inc + ${FSP_RA}/inc/api + ${FSP_RA}/inc/instances + ${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Include + ${FSP_RA}/src/bsp/mcu/${MCU_VARIANT} + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + # linker file + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + # nanolib + --specs=nano.specs + --specs=nosys.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_RAXXX ${RTOS}) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c + ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + + # Link dependencies + target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + + # Flashing + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index 103d3cfa6..8e4f80eaf 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -35,9 +35,9 @@ SRC_C += \ INC += \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ - $(TOP)/$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Include \ $(TOP)/$(BOARD_PATH) \ $(TOP)/$(BOARD_PATH)/fsp_cfg \ + $(TOP)/$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Include \ $(TOP)/$(FSP_RA)/inc \ $(TOP)/$(FSP_RA)/inc/api \ $(TOP)/$(FSP_RA)/inc/instances \ diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 5be9f11ce..be0a9fa66 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -31,9 +31,21 @@ extern "C" { #endif +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-prototypes" + +// extra push due to https://github.com/renesas/fsp/pull/278 +#pragma GCC diagnostic push +#endif + /* renesas fsp api */ #include "bsp_api.h" +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + #define RUSB2_REG_BASE (0x40090000) #if defined(__ICCARM__) -- cgit v1.3.1 From e7431f54f207b8563f2d8dba3384dba243d55bf4 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 1 Jul 2023 17:46:21 +0700 Subject: fix undef with fsp --- src/portable/renesas/rusb2/rusb2_ra.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index be0a9fa66..df4afdfa0 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -34,6 +34,7 @@ extern "C" { #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstrict-prototypes" +#pragma GCC diagnostic ignored "-Wundef" // extra push due to https://github.com/renesas/fsp/pull/278 #pragma GCC diagnostic push -- cgit v1.3.1 From 0693462ebad20338de78aeb93d60d6c3c73a6ca7 Mon Sep 17 00:00:00 2001 From: Lars Pötter Date: Sun, 2 Jul 2023 09:02:24 +0200 Subject: made line ends consistent. --- src/class/cdc/cdc_host.c | 4 ++-- src/class/video/video_device.c | 16 +++++++------- src/common/tusb_fifo.c | 2 +- src/portable/dialog/da146xx/dcd_da146xx.c | 2 +- src/portable/mentor/musb/dcd_musb.c | 30 +++++++++++++------------- src/portable/mentor/musb/hcd_musb.c | 8 +++---- src/portable/nxp/khci/hcd_khci.c | 16 +++++++------- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 4 ++-- src/portable/raspberrypi/rp2040/rp2040_usb.c | 4 ++-- src/portable/renesas/rusb2/hcd_rusb2.c | 8 +++---- src/portable/st/typec/typec_stm32.c | 18 ++++++++-------- src/portable/sunxi/dcd_sunxi_musb.c | 32 ++++++++++++++-------------- 12 files changed, 72 insertions(+), 72 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index ce9f27c33..e1af8d801 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -973,7 +973,7 @@ static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate); - TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\n", baudrate, divisor); + TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor); p_cdc->user_control_cb = complete_cb; _ftdi_requested_baud = baudrate; @@ -1108,7 +1108,7 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe } static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG_DRV("CDC CP210x Set BaudRate = %lu\n", baudrate); + TU_LOG_DRV("CDC CP210x Set BaudRate = %lu\r\n", baudrate); uint32_t baud_le = tu_htole32(baudrate); p_cdc->user_control_cb = complete_cb; return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 91f452afc..16eae0ced 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -609,17 +609,17 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) * @param[in] altnum The target alternate setting number. */ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum) { - TU_LOG2(" open VC %d\n", altnum); + TU_LOG2(" open VC %d\r\n", altnum); uint8_t const *beg = self->beg; uint8_t const *end = beg + self->len; /* The first descriptor is a video control interface descriptor. */ uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); - TU_LOG2(" cur %d\n", cur - beg); + TU_LOG2(" cur %d\r\n", cur - beg); TU_VERIFY(cur < end); tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur; - TU_LOG2(" bInCollection %d\n", vc->ctl.bInCollection); + TU_LOG2(" bInCollection %d\r\n", vc->ctl.bInCollection); /* Support for up to 2 streaming interfaces only. */ TU_ASSERT(vc->ctl.bInCollection <= CFG_TUD_VIDEO_STREAMING); @@ -628,7 +628,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t /* Advance to the next descriptor after the class-specific VC interface header descriptor. */ cur += vc->std.bLength + vc->ctl.bLength; - TU_LOG2(" bNumEndpoints %d\n", vc->std.bNumEndpoints); + TU_LOG2(" bNumEndpoints %d\r\n", vc->std.bNumEndpoints); /* Open the notification endpoint if it exist. */ if (vc->std.bNumEndpoints) { /* Support for 1 endpoint only. */ @@ -662,7 +662,7 @@ static bool _init_vs_configuration(videod_streaming_interface_t *stm) static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint_fast8_t altnum) { uint_fast8_t i; - TU_LOG2(" reopen VS %d\n", altnum); + TU_LOG2(" reopen VS %d\r\n", altnum); uint8_t const *desc = _videod_itf[stm->index_vc].beg; /* Close endpoints of previous settings. */ @@ -672,7 +672,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint uint8_t ep_adr = _desc_ep_addr(desc + ofs_ep); usbd_edpt_close(rhport, ep_adr); stm->desc.ep[i] = 0; - TU_LOG2(" close EP%02x\n", ep_adr); + TU_LOG2(" close EP%02x\r\n", ep_adr); } /* clear transfer management information */ @@ -709,12 +709,12 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint } TU_ASSERT(usbd_edpt_open(rhport, ep)); stm->desc.ep[i] = (uint16_t) (cur - desc); - TU_LOG2(" open EP%02x\n", _desc_ep_addr(cur)); + TU_LOG2(" open EP%02x\r\n", _desc_ep_addr(cur)); } if (altnum) { stm->state = VS_STATE_STREAMING; } - TU_LOG2(" done\n"); + TU_LOG2(" done\r\n"); return true; } diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index a52c92267..d6c3db4ce 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -539,7 +539,7 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu // Advance index f->wr_idx = advance_index(f->depth, wr_idx, n); - TU_LOG(TU_FIFO_DBG, "\tnew_wr = %u\n", f->wr_idx); + TU_LOG(TU_FIFO_DBG, "\tnew_wr = %u\r\n", f->wr_idx); } _ff_unlock(f->mutex_wr); diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index 961da81d6..d1e85c2df 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -651,7 +651,7 @@ static void handle_epx_tx_ev(xfer_ctl_t *xfer) } if (txs & USB_USB_TXS1_REG_USB_TX_URUN_Msk) { - TU_LOG1("EP %d FIFO underrun\n", epnum); + TU_LOG1("EP %d FIFO underrun\r\n", epnum); } // Start next or repeated packet. start_tx_packet(xfer); diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 487761847..3c0114e41 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -317,7 +317,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr) const unsigned mps = regs->TXMAXP; const unsigned len = TU_MIN(mps, rem); void *buf = pipe->buf; - // TU_LOG1(" %p mps %d len %d rem %d\n", buf, mps, len, rem); + // TU_LOG1(" %p mps %d len %d rem %d\r\n", buf, mps, len, rem); if (len) { if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) { pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_IN); @@ -328,7 +328,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr) pipe->remaining = rem - len; } regs->TXCSRL = USB_TXCSRL1_TXRDY; - // TU_LOG1(" TXCSRL%d = %x %d\n", epnum_minus1 + 1, regs->TXCSRL, rem - len); + // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum_minus1 + 1, regs->TXCSRL, rem - len); return false; } @@ -337,7 +337,7 @@ static bool handle_xfer_out(uint_fast8_t ep_addr) unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1; pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1); - // TU_LOG1(" RXCSRL%d = %x\n", epnum_minus1 + 1, regs->RXCSRL); + // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, regs->RXCSRL); TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY); @@ -399,14 +399,14 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ * may have already finished and received the next setup packet * without calling this function, so we have no choice but to * invoke the callback function of status packet here. */ - // TU_LOG1(" STATUS OUT USB0->CSRL0 = %x\n", USB0->CSRL0); + // TU_LOG1(" STATUS OUT USB0->CSRL0 = %x\r\n", USB0->CSRL0); _dcd.status_out = 0; if (req == REQUEST_TYPE_INVALID) { dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false); } else { /* The next setup packet has already been received, it aborts * invoking callback function to avoid confusing TUSB stack. */ - TU_LOG1("Drop CONTROL_STAGE_ACK\n"); + TU_LOG1("Drop CONTROL_STAGE_ACK\r\n"); } return true; } @@ -431,16 +431,16 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ } else { USB0->CSRL0 = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */ } - // TU_LOG1(" IN USB0->CSRL0 = %x\n", USB0->CSRL0); + // TU_LOG1(" IN USB0->CSRL0 = %x\r\n", USB0->CSRL0); } else { - // TU_LOG1(" OUT USB0->CSRL0 = %x\n", USB0->CSRL0); + // TU_LOG1(" OUT USB0->CSRL0 = %x\r\n", USB0->CSRL0); _dcd.pipe0.buf = buffer; _dcd.pipe0.length = len; _dcd.pipe0.remaining = len; USB0->CSRL0 = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */ } } else if (dir_in) { - // TU_LOG1(" STATUS IN USB0->CSRL0 = %x\n", USB0->CSRL0); + // TU_LOG1(" STATUS IN USB0->CSRL0 = %x\r\n", USB0->CSRL0); _dcd.pipe0.buf = NULL; _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; @@ -454,7 +454,7 @@ static void process_ep0(uint8_t rhport) { uint_fast8_t csrl = USB0->CSRL0; - // TU_LOG1(" EP0 USB0->CSRL0 = %x\n", csrl); + // TU_LOG1(" EP0 USB0->CSRL0 = %x\r\n", csrl); if (csrl & USB_CSRL0_STALLED) { /* Returned STALL packet to HOST. */ @@ -464,7 +464,7 @@ static void process_ep0(uint8_t rhport) unsigned req = _dcd.setup_packet.bmRequestType; if (csrl & USB_CSRL0_SETEND) { - TU_LOG1(" ABORT by the next packets\n"); + TU_LOG1(" ABORT by the next packets\r\n"); USB0->CSRL0 = USB_CSRL0_SETENDC; if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) { /* DATA stage was aborted by receiving STATUS or SETUP packet. */ @@ -539,14 +539,14 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) volatile hw_endpoint_t *regs = edpt_regs(epn_minus1); if (dir_in) { - // TU_LOG1(" TXCSRL%d = %x\n", epn_minus1 + 1, regs->TXCSRL); + // TU_LOG1(" TXCSRL%d = %x\r\n", epn_minus1 + 1, regs->TXCSRL); if (regs->TXCSRL & USB_TXCSRL1_STALLED) { regs->TXCSRL &= ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_UNDRN); return; } completed = handle_xfer_in(ep_addr); } else { - // TU_LOG1(" RXCSRL%d = %x\n", epn_minus1 + 1, regs->RXCSRL); + // TU_LOG1(" RXCSRL%d = %x\r\n", epn_minus1 + 1, regs->RXCSRL); if (regs->RXCSRL & USB_RXCSRL1_STALLED) { regs->RXCSRL &= ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_OVER); return; @@ -789,7 +789,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t { (void)rhport; bool ret; - // TU_LOG1("X %x %d\n", ep_addr, total_bytes); + // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes); unsigned const epnum = tu_edpt_number(ep_addr); unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); NVIC_DisableIRQ(USB0_IRQn); @@ -807,7 +807,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_ { (void)rhport; bool ret; - // TU_LOG1("X %x %d\n", ep_addr, total_bytes); + // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes); unsigned const epnum = tu_edpt_number(ep_addr); TU_ASSERT(epnum); unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); @@ -869,7 +869,7 @@ void dcd_int_handler(uint8_t rhport) is = USB0->IS; /* read and clear interrupt status */ txis = USB0->TXIS; /* read and clear interrupt status */ rxis = USB0->RXIS; /* read and clear interrupt status */ - // TU_LOG1("D%2x T%2x R%2x\n", is, txis, rxis); + // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis); is &= USB0->IE; /* Clear disabled interrupts */ if (is & USB_IS_DISCON) { diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c index 9eb2e005e..7e67b8291 100644 --- a/src/portable/mentor/musb/hcd_musb.c +++ b/src/portable/mentor/musb/hcd_musb.c @@ -418,7 +418,7 @@ static void process_ep0(uint8_t rhport) (void)rhport; uint_fast8_t csrl = USB0->CSRL0; - // TU_LOG1(" EP0 CSRL = %x\n", csrl); + // TU_LOG1(" EP0 CSRL = %x\r\n", csrl); unsigned const dev_addr = USB0->TXFUNCADDR0; unsigned const req = _hcd.bmRequestType; @@ -508,7 +508,7 @@ static void process_pipe_tx(uint8_t rhport, uint_fast8_t pipenum) volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1); unsigned const csrl = regs->TXCSRL; - // TU_LOG1(" TXCSRL%d = %x\n", pipenum, csrl); + // TU_LOG1(" TXCSRL%d = %x\r\n", pipenum, csrl); if (csrl & (USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR)) { if (csrl & USB_TXCSRL1_TXRDY) regs->TXCSRL = (csrl & ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR)) | USB_TXCSRL1_FLUSH; @@ -537,7 +537,7 @@ static void process_pipe_rx(uint8_t rhport, uint_fast8_t pipenum) volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1); unsigned const csrl = regs->RXCSRL; - // TU_LOG1(" RXCSRL%d = %x\n", pipenum, csrl); + // TU_LOG1(" RXCSRL%d = %x\r\n", pipenum, csrl); if (csrl & (USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR)) { if (csrl & USB_RXCSRL1_RXRDY) regs->RXCSRL = (csrl & ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR)) | USB_RXCSRL1_FLUSH; @@ -846,7 +846,7 @@ void hcd_int_handler(uint8_t rhport) is = USB0->IS; /* read and clear interrupt status */ txis = USB0->TXIS; /* read and clear interrupt status */ rxis = USB0->RXIS; /* read and clear interrupt status */ - // TU_LOG1("D%2x T%2x R%2x\n", is, txis, rxis); + // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis); is &= USB0->IE; /* Clear disabled interrupts */ if (is & USB_IS_RESUME) { diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index f6029ee0d..fb978cac8 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -161,7 +161,7 @@ static int prepare_packets(int pipenum) buffer_descriptor_t *bd = _hcd.bdt[dir_tx]; TU_ASSERT(0 == bd[odd].own, -1); - // TU_LOG1(" %p dir %d odd %d data %d\n", &bd[odd], dir_tx, odd, pipe->data); + // TU_LOG1(" %p dir %d odd %d data %d\r\n", &bd[odd], dir_tx, odd, pipe->data); ep->pipenum = pipenum; @@ -251,7 +251,7 @@ static bool resume_transfer(int pipenum) flags |= USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPCTLDIS_MASK | USB_ENDPT_RETRYDIS_MASK; break; } - // TU_LOG1(" resume pipenum %d flags %x\n", pipenum, flags); + // TU_LOG1(" resume pipenum %d flags %x\r\n", pipenum, flags); KHCI->ENDPOINT[0].ENDPT = flags; KHCI->ADDR = (KHCI->ADDR & USB_ADDR_LSEN_MASK) | pipe->dev_addr; @@ -302,7 +302,7 @@ static void process_tokdne(uint8_t rhport) int pipenum = ep->pipenum; int next_pipenum; - // TU_LOG1("TOKDNE %x PID %x pipe %d\n", s, pid, pipenum); + // TU_LOG1("TOKDNE %x PID %x pipe %d\r\n", s, pid, pipenum); xfer_result_t result; switch (pid) { @@ -479,7 +479,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { (void)rhport; - // TU_LOG1("SETUP %u\n", dev_addr); + // TU_LOG1("SETUP %u\r\n", dev_addr); TU_ASSERT(0 == (_hcd.in_progress & TU_BIT(0))); int pipenum = find_pipe(dev_addr, 0); @@ -510,7 +510,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const { (void)rhport; uint8_t const ep_addr = ep_desc->bEndpointAddress; - // TU_LOG1("O %u %x\n", dev_addr, ep_addr); + // TU_LOG1("O %u %x\r\n", dev_addr, ep_addr); /* Find a free pipe */ pipe_state_t *p = &_hcd.pipe[0]; pipe_state_t *end = &_hcd.pipe[CFG_TUH_ENDPOINT_MAX * 2]; @@ -543,7 +543,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { (void)rhport; - // TU_LOG1("X %u %x %x %d\n", dev_addr, ep_addr, (uintptr_t)buffer, buflen); + // TU_LOG1("X %u %x %x %d\r\n", dev_addr, ep_addr, (uintptr_t)buffer, buflen); int pipenum = find_pipe(dev_addr, ep_addr); TU_ASSERT(0 <= pipenum); @@ -580,7 +580,7 @@ void hcd_int_handler(uint8_t rhport) uint32_t is = KHCI->ISTAT; uint32_t msk = KHCI->INTEN; - // TU_LOG1("S %lx\n", is); + // TU_LOG1("S %lx\r\n", is); /* clear disabled interrupts */ KHCI->ISTAT = (is & ~msk & ~USB_ISTAT_TOKDNE_MASK) | USB_ISTAT_SOFTOK_MASK; @@ -589,7 +589,7 @@ void hcd_int_handler(uint8_t rhport) if (is & USB_ISTAT_ERROR_MASK) { unsigned err = KHCI->ERRSTAT; if (err) { - TU_LOG1(" ERR %x\n", err); + TU_LOG1(" ERR %x\r\n", err); KHCI->ERRSTAT = err; } else { KHCI->INTEN &= ~USB_ISTAT_ERROR_MASK; diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 02f9968a7..51b8bf72d 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -219,7 +219,7 @@ static void __tusb_irq_path_func(hcd_rp2040_irq)(void) if ( status & USB_INTS_BUFF_STATUS_BITS ) { handled |= USB_INTS_BUFF_STATUS_BITS; - TU_LOG(2, "Buffer complete\n"); + TU_LOG(2, "Buffer complete\r\n"); hw_handle_buff_status(); } @@ -227,7 +227,7 @@ static void __tusb_irq_path_func(hcd_rp2040_irq)(void) { handled |= USB_INTS_TRANS_COMPLETE_BITS; usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS; - TU_LOG(2, "Transfer complete\n"); + TU_LOG(2, "Transfer complete\r\n"); hw_trans_complete(); } diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index 1f49665ff..53486a586 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -219,7 +219,7 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to if ( ep->active ) { // TODO: Is this acceptable for interrupt packets? - TU_LOG(1, "WARN: starting new transfer on already active ep %d %s\n", tu_edpt_number(ep->ep_addr), + TU_LOG(1, "WARN: starting new transfer on already active ep %d %s\r\n", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]); hw_endpoint_reset_transfer(ep); @@ -419,7 +419,7 @@ static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoi if (delta < 800 || delta > 998) { return false; } - TU_LOG(3, "Avoiding sof %lu now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof); + TU_LOG(3, "Avoiding sof %lu now %lu last %lu\r\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof); return true; } diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 0e6fa1618..886a6f6b8 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -409,7 +409,7 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num) (void)rhport; xfer_result_t result; uint16_t volatile *ctr = get_pipectr(num); - // TU_LOG1("NRDY %d %x\n", num, *ctr); + // TU_LOG1("NRDY %d %x\r\n", num, *ctr); switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) { default: return; case RUSB2_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break; @@ -608,7 +608,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { (void)rhport; - // TU_LOG1("S %d %x\n", dev_addr, RUSB2->DCPCTR); + // TU_LOG1("S %d %x\r\n", dev_addr, RUSB2->DCPCTR); TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ TU_ASSERT(0 == RUSB2->DCPCTR_b.SUREQ); @@ -701,7 +701,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b { bool r; hcd_int_disable(rhport); - // TU_LOG1("X %d %x %u\n", dev_addr, ep_addr, buflen); + // TU_LOG1("X %d %x %u\r\n", dev_addr, ep_addr, buflen); r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen); hcd_int_enable(rhport); return r; @@ -745,7 +745,7 @@ void hcd_int_handler(uint8_t rhport) /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1); RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0); - // TU_LOG1("IS %04x %04x\n", is0, is1); + // TU_LOG1("IS %04x %04x\r\n", is0, is1); is1 &= RUSB2->INTENB1; is0 &= RUSB2->INTENB0; diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c index bf8b660f0..8da2e39ba 100644 --- a/src/portable/st/typec/typec_stm32.c +++ b/src/portable/st/typec/typec_stm32.c @@ -246,7 +246,7 @@ void tcd_int_handler(uint8_t rhport) { v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03; v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03; - TU_LOG3("VState CC1 = %lu, CC2 = %lu\n", v_cc[0], v_cc[1]); + TU_LOG3("VState CC1 = %lu, CC2 = %lu\r\n", v_cc[0], v_cc[1]); uint32_t cr = UCPD1->CR; @@ -255,15 +255,15 @@ void tcd_int_handler(uint8_t rhport) { // FIXME somehow CC2 is vstate is not correct, always 1 even not attached. // on DPOW1 board, it is connected to PA10 (USBPD_DBCC2), we probably miss something. if ((sr & UCPD_SR_TYPECEVT1) && (v_cc[0] == 3)) { - TU_LOG3("Attach CC1\n"); + TU_LOG3("Attach CC1\r\n"); cr &= ~(UCPD_CR_PHYCCSEL | UCPD_CR_CCENABLE); cr |= UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_0; } else if ((sr & UCPD_SR_TYPECEVT2) && (v_cc[1] == 3)) { - TU_LOG3("Attach CC2\n"); + TU_LOG3("Attach CC2\r\n"); cr &= ~UCPD_CR_CCENABLE; cr |= (UCPD_CR_PHYCCSEL | UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_1); } else { - TU_LOG3("Detach\n"); + TU_LOG3("Detach\r\n"); cr &= ~UCPD_CR_PHYRXEN; cr |= UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1; } @@ -290,7 +290,7 @@ void tcd_int_handler(uint8_t rhport) { //------------- RX -------------// if (sr & UCPD_SR_RXORDDET) { // SOP: Start of Packet. - TU_LOG3("SOP\n"); + TU_LOG3("SOP\r\n"); // UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk; // ack @@ -299,7 +299,7 @@ void tcd_int_handler(uint8_t rhport) { // Received full message if (sr & UCPD_SR_RXMSGEND) { - TU_LOG3("RX MSG END\n"); + TU_LOG3("RX MSG END\r\n"); // stop TX dma_stop(rhport, true); @@ -328,7 +328,7 @@ void tcd_int_handler(uint8_t rhport) { } if (sr & UCPD_SR_RXOVR) { - TU_LOG3("RXOVR\n"); + TU_LOG3("RXOVR\r\n"); // ack UCPD1->ICR = UCPD_ICR_RXOVRCF; } @@ -343,12 +343,12 @@ void tcd_int_handler(uint8_t rhport) { uint8_t result; if ( sr & UCPD_SR_TXMSGSENT ) { - TU_LOG3("TX MSG SENT\n"); + TU_LOG3("TX MSG SENT\r\n"); result = XFER_RESULT_SUCCESS; // ack UCPD1->ICR = UCPD_ICR_TXMSGSENTCF; }else { - TU_LOG3("TX Error\n"); + TU_LOG3("TX Error\r\n"); result = XFER_RESULT_FAILED; // ack UCPD1->ICR = UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND; diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c index e26be775d..6cc1975a8 100644 --- a/src/portable/sunxi/dcd_sunxi_musb.c +++ b/src/portable/sunxi/dcd_sunxi_musb.c @@ -408,9 +408,9 @@ static inline unsigned free_block_size(free_block_t const *blk) #if 0 static inline void print_block_list(free_block_t const *blk, unsigned num) { - TU_LOG1("*************\n"); + TU_LOG1("*************\r\n"); for (unsigned i = 0; i < num; ++i) { - TU_LOG1(" Blk%u %u %u\n", i, blk->beg, blk->end); + TU_LOG1(" Blk%u %u %u\r\n", i, blk->beg, blk->end); ++blk; } } @@ -590,7 +590,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr) const unsigned mps = USBC_Readw(USBC_REG_TXMAXP(USBC0_BASE)); const unsigned len = TU_MIN(mps, rem); uint8_t *buf = pipe->buf; - // TU_LOG1(" %p mps %d len %d rem %d\n", buf, mps, len, rem); + // TU_LOG1(" %p mps %d len %d rem %d\r\n", buf, mps, len, rem); if (len) { volatile void* addr = (volatile void*)(USBC_REG_EPFIFO1(USBC0_BASE) + (epnum_minus1 << 2)); if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) { @@ -602,7 +602,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr) pipe->remaining = rem - len; } __USBC_Dev_Tx_WriteDataComplete(); - // TU_LOG1(" TXCSRL%d = %x %d\n", epnum_minus1 + 1, regs->TXCSRL, rem - len); + // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum_minus1 + 1, regs->TXCSRL, rem - len); return false; } @@ -610,7 +610,7 @@ static bool handle_xfer_out(uint_fast8_t ep_addr) { unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1; pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; - // TU_LOG1(" RXCSRL%d = %x\n", epnum_minus1 + 1, regs->RXCSRL); + // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, regs->RXCSRL); TU_ASSERT(__USBC_Dev_Rx_IsReadDataReady()); @@ -677,14 +677,14 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ * may have already finished and received the next setup packet * without calling this function, so we have no choice but to * invoke the callback function of status packet here. */ - // TU_LOG1(" STATUS OUT CSRL0 = %x\n", CSRL0); + // TU_LOG1(" STATUS OUT CSRL0 = %x\r\n", CSRL0); _dcd.status_out = 0; if (req == REQUEST_TYPE_INVALID) { dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false); } else { /* The next setup packet has already been received, it aborts * invoking callback function to avoid confusing TUSB stack. */ - TU_LOG1("Drop CONTROL_STAGE_ACK\n"); + TU_LOG1("Drop CONTROL_STAGE_ACK\r\n"); } return true; } @@ -709,16 +709,16 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ } else { __USBC_Dev_ep0_WriteDataHalf(); } - // TU_LOG1(" IN CSRL0 = %x\n", CSRL0); + // TU_LOG1(" IN CSRL0 = %x\r\n", CSRL0); } else { - // TU_LOG1(" OUT CSRL0 = %x\n", CSRL0); + // TU_LOG1(" OUT CSRL0 = %x\r\n", CSRL0); _dcd.pipe0.buf = buffer; _dcd.pipe0.length = len; _dcd.pipe0.remaining = len; __USBC_Dev_ep0_ReadDataHalf(); } } else if (dir_in) { - // TU_LOG1(" STATUS IN CSRL0 = %x\n", CSRL0); + // TU_LOG1(" STATUS IN CSRL0 = %x\r\n", CSRL0); _dcd.pipe0.buf = NULL; _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; @@ -733,7 +733,7 @@ static void process_ep0(uint8_t rhport) USBC_SelectActiveEp(0); uint_fast8_t csrl = USBC_Readw(USBC_REG_CSR0(USBC0_BASE)); - // TU_LOG1(" EP0 CSRL0 = %x\n", csrl); + // TU_LOG1(" EP0 CSRL0 = %x\r\n", csrl); if (csrl & USB_CSRL0_STALLED) { /* Returned STALL packet to HOST. */ @@ -743,7 +743,7 @@ static void process_ep0(uint8_t rhport) unsigned req = _dcd.setup_packet.bmRequestType; if (csrl & USB_CSRL0_SETEND) { - // TU_LOG1(" ABORT by the next packets\n"); + // TU_LOG1(" ABORT by the next packets\r\n"); USBC_Dev_Ctrl_ClearSetupEnd(); if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) { /* DATA stage was aborted by receiving STATUS or SETUP packet. */ @@ -819,14 +819,14 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) USBC_SelectActiveEp(epn); if (dir_in) { - // TU_LOG1(" TXCSRL%d = %x\n", epn_minus1 + 1, regs->TXCSRL); + // TU_LOG1(" TXCSRL%d = %x\r\n", epn_minus1 + 1, regs->TXCSRL); if (__USBC_Dev_Tx_IsEpStall()) { __USBC_Dev_Tx_ClearStall(); return; } completed = handle_xfer_in(ep_addr); } else { - // TU_LOG1(" RXCSRL%d = %x\n", epn_minus1 + 1, regs->RXCSRL); + // TU_LOG1(" RXCSRL%d = %x\r\n", epn_minus1 + 1, regs->RXCSRL); if (__USBC_Dev_Rx_IsEpStall()) { __USBC_Dev_Rx_ClearStall(); return; @@ -1092,7 +1092,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t { (void)rhport; bool ret; - // TU_LOG1("X %x %d\n", ep_addr, total_bytes); + // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes); unsigned const epnum = tu_edpt_number(ep_addr); musb_int_mask(); @@ -1111,7 +1111,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_ { (void)rhport; bool ret; - // TU_LOG1("X %x %d\n", ep_addr, total_bytes); + // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes); unsigned const epnum = tu_edpt_number(ep_addr); TU_ASSERT(epnum); -- cgit v1.3.1 From 2029ca9536e7e889f0f420218136e7bd1ac091fc Mon Sep 17 00:00:00 2001 From: Lars Pötter Date: Sun, 2 Jul 2023 10:53:08 +0200 Subject: also fixed pico_trac() log messages. --- src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 4 ++-- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 6 +++--- src/portable/raspberrypi/rp2040/rp2040_usb.c | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c index 264af2e7a..130716da4 100644 --- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c @@ -150,11 +150,11 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet // // so if any transfer is active on epx, we are busy. Interrupt endpoints have their own // // EPX so ep->active will only be busy if there is a pending transfer on that interrupt endpoint // // on that device -// pico_trace("hcd_edpt_busy dev addr %d ep_addr 0x%x\n", dev_addr, ep_addr); +// pico_trace("hcd_edpt_busy dev addr %d ep_addr 0x%x\r\n", dev_addr, ep_addr); // struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr); // assert(ep); // bool busy = ep->active; -// pico_trace("busy == %d\n", busy); +// pico_trace("busy == %d\r\n", busy); // return busy; //} diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 479b17b67..e8cee73fd 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -189,7 +189,7 @@ static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_by static void __tusb_irq_path_func(hw_handle_buff_status)(void) { uint32_t remaining_buffers = usb_hw->buf_status; - pico_trace("buf_status = 0x%08lx\n", remaining_buffers); + pico_trace("buf_status = 0x%08lx\r\n", remaining_buffers); uint bit = 1u; for (uint8_t i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++) { @@ -331,7 +331,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) // SE0 for 2.5 us or more (will last at least 10ms) if ( status & USB_INTS_BUS_RESET_BITS ) { - pico_trace("BUS RESET\n"); + pico_trace("BUS RESET\r\n"); handled |= USB_INTS_BUS_RESET_BITS; @@ -565,7 +565,7 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) { (void) rhport; - pico_trace("dcd_edpt_close %02x\n", ep_addr); + pico_trace("dcd_edpt_close %02x\r\n", ep_addr); hw_endpoint_close(ep_addr); } diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index 53486a586..a512dc34f 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -276,7 +276,7 @@ static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint *ep, uin // Short packet if (xferred_bytes < ep->wMaxPacketSize) { - pico_trace(" Short packet on buffer %d with %u bytes\n", buf_id, xferred_bytes); + pico_trace(" Short packet on buffer %d with %u bytes\r\n", buf_id, xferred_bytes); // Reduce total length as this is last packet ep->remaining_len = 0; } @@ -352,7 +352,7 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep) // If we are done then notify tinyusb if (ep->remaining_len == 0) { - pico_trace("Completed transfer of %d bytes on ep %d %s\n", + pico_trace("Completed transfer of %d bytes on ep %d %s\r\n", ep->xferred_len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]); // Notify caller we are done so it can notify the tinyusb stack hw_endpoint_lock_update(ep, -1); -- cgit v1.3.1 From f79529c09c6e7c0d6ee5586633ceb8c83e345406 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 5 Jul 2023 17:13:01 +0700 Subject: usb hs work with ra 6m5 ek --- .idea/runConfigurations/ra4m1.xml | 10 ++ .idea/runConfigurations/ra6m1.xml | 10 ++ .idea/runConfigurations/ra6m5.xml | 10 ++ hw/bsp/ra/board_cfg.h | 45 +++++++++ hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h | 4 +- hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h | 4 +- hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h | 4 +- hw/bsp/ra/boards/ra6m5_ek/board.cmake | 20 +++- hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h | 4 +- hw/bsp/ra/family.c | 118 ++++++++++++++++-------- hw/bsp/ra/vector_data.h | 15 ++- src/common/tusb_mcu.h | 1 + src/portable/renesas/rusb2/dcd_rusb2.c | 3 +- 13 files changed, 188 insertions(+), 60 deletions(-) create mode 100644 .idea/runConfigurations/ra4m1.xml create mode 100644 .idea/runConfigurations/ra6m1.xml create mode 100644 .idea/runConfigurations/ra6m5.xml create mode 100644 hw/bsp/ra/board_cfg.h (limited to 'src') diff --git a/.idea/runConfigurations/ra4m1.xml b/.idea/runConfigurations/ra4m1.xml new file mode 100644 index 000000000..22bb61949 --- /dev/null +++ b/.idea/runConfigurations/ra4m1.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/ra6m1.xml b/.idea/runConfigurations/ra6m1.xml new file mode 100644 index 000000000..438ac4063 --- /dev/null +++ b/.idea/runConfigurations/ra6m1.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml new file mode 100644 index 000000000..02df11610 --- /dev/null +++ b/.idea/runConfigurations/ra6m5.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/hw/bsp/ra/board_cfg.h b/hw/bsp/ra/board_cfg.h new file mode 100644 index 000000000..baed46b5f --- /dev/null +++ b/hw/bsp/ra/board_cfg.h @@ -0,0 +1,45 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#ifndef _BOARD_CFG_H +#define _BOARD_CFG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8) + #define BOARD_HAS_USB_HIGHSPEED +#endif + +// for SystemInit() +void bsp_init(void * p_args); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h index 19bb473eb..f0577b702 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h @@ -4,6 +4,7 @@ #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" #undef RA_NOT_DEFINED #define BSP_CFG_RTOS (0) @@ -31,7 +32,4 @@ #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -// for SystemInit() -void bsp_init(void * p_args); - #endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h index 6a47bccc6..47de7747d 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h @@ -7,6 +7,7 @@ extern "C" { #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" #define RA_NOT_DEFINED 0 #ifndef BSP_CFG_RTOS @@ -56,9 +57,6 @@ extern "C" { #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 #endif -// for SystemInit() -void bsp_init(void * p_args); - #ifdef __cplusplus } #endif diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h index 75a331fc2..b5ed53a3b 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h @@ -8,6 +8,7 @@ extern "C" { #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" #define RA_NOT_DEFINED 0 #ifndef BSP_CFG_RTOS @@ -60,9 +61,6 @@ extern "C" { #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 #endif -// for SystemInit() -void bsp_init(void * p_args); - #ifdef __cplusplus } #endif diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake index 42a4c7417..d934a0c0d 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake +++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake @@ -3,8 +3,22 @@ set(MCU_VARIANT ra6m5) set(JLINK_DEVICE R7FA6M5BH) +# default to PORT1 Highspeed +if (NOT DEFINED PORT) +set(PORT 1) +endif() + function(update_board TARGET) -# target_compile_definitions(${TARGET} PUBLIC) -# target_sources(${TARGET} PRIVATE) -# target_include_directories(${BOARD_TARGET} PUBLIC) + target_compile_definitions(${TARGET} PUBLIC + BOARD_TUD_RHPORT=${PORT} + # port 0 is fullspeed, port 1 is highspeed + BOARD_TUD_MAX_SPEED=$ + ) + + if (PORT STREQUAL 1) + target_compile_definitions(${TARGET} PUBLIC + CFG_TUSB_RHPORT1_MODE=OPT_MODE_DEVICE|OPT_MODE_HIGH_SPEED + CFG_TUSB_RHPORT0_MODE=0 + ) + endif () endfunction() diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h index e41f603ad..a41536eda 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h @@ -7,6 +7,7 @@ extern "C" { #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" #define RA_NOT_DEFINED 0 #ifndef BSP_CFG_RTOS @@ -56,9 +57,6 @@ extern "C" { #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 #endif -// for SystemInit() -void bsp_init(void * p_args); - #ifdef __cplusplus } #endif diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 769678954..36b46beab 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -48,9 +48,9 @@ #include "board.h" /* Key code for writing PRCR register. */ -#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_KEY (0xA500U) #define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U) -#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) static const ioport_cfg_t family_pin_cfg = { .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t), @@ -62,25 +62,38 @@ static ioport_instance_ctrl_t port_ctrl; // Vector Data //--------------------------------------------------------------------+ -BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = { +BSP_DONT_REMOVE BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) +const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] = { [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */ [1] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */ [2] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */ [3] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */ + +#ifdef BOARD_HAS_USB_HIGHSPEED + [4] = usbhs_interrupt_handler, /* USBHS INT (USBHS interrupt) */ + [5] = usbhs_d0fifo_handler, /* USBHS FIFO 0 (DMA transfer request 0) */ + [6] = usbhs_d1fifo_handler, /* USBHS FIFO 1 (DMA transfer request 1) */ +#endif }; + const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = { - [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */ - [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */ - [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */ - [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1) /* USBFS FIFO 1 (DMA transfer request 1) */ + [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */ + [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */ + [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */ + [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1), /* USBFS FIFO 1 (DMA transfer request 1) */ + +#ifdef BOARD_HAS_USB_HIGHSPEED + [4] = BSP_PRV_IELS_ENUM(EVENT_USBHS_USB_INT_RESUME), /* USBHS USB INT RESUME (USBHS interrupt) */ + [5] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_0), /* USBHS FIFO 0 (DMA transfer request 0) */ + [6] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_1), /* USBHS FIFO 1 (DMA transfer request 1) */ +#endif }; //--------------------------------------------------------------------+ // Board porting API //--------------------------------------------------------------------+ -void board_init(void) -{ +void board_init(void) { /* Configure pins. */ R_IOPORT_Open(&port_ctrl, &family_pin_cfg); @@ -94,8 +107,8 @@ void board_init(void) // Enable USB module R_MSTP->MSTPCRB &= ~(1U << 11U); // FS -#ifdef R_USB_HS0_BASE -// R_MSTP->MSTPCRB &= ~(1U << 12U); // HS +#ifdef BOARD_HAS_USB_HIGHSPEED + R_MSTP->MSTPCRB &= ~(1U << 12U); #endif #if CFG_TUSB_OS == OPT_OS_FREERTOS @@ -145,66 +158,93 @@ void SysTick_Handler(void) { uint32_t board_millis(void) { return system_ticks; } + #endif //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void usbfs_interrupt_handler(void) -{ + +#if CFG_TUD_ENABLED && defined(BOARD_TUD_RHPORT) + #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n) +#else + #define PORT_SUPPORT_DEVICE(_n) 0 +#endif + +#if CFG_TUH_ENABLED && defined(BOARD_TUH_RHPORT) + #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n) +#else + #define PORT_SUPPORT_HOST(_n) 0 +#endif + +//------------- USB0 FullSpeed -------------// +void usbfs_interrupt_handler(void) { IRQn_Type irq = R_FSP_CurrentIrqGet(); R_BSP_IrqStatusClear(irq); -#if CFG_TUH_ENABLED + #if PORT_SUPPORT_HOST(0) tuh_int_handler(0); -#endif + #endif -#if CFG_TUD_ENABLED + #if PORT_SUPPORT_DEVICE(0) tud_int_handler(0); -#endif + #endif } -void usbfs_resume_handler(void) -{ +void usbfs_resume_handler(void) { IRQn_Type irq = R_FSP_CurrentIrqGet(); R_BSP_IrqStatusClear(irq); -#if CFG_TUH_ENABLED + #if PORT_SUPPORT_HOST(0) tuh_int_handler(0); -#endif + #endif -#if CFG_TUD_ENABLED + #if PORT_SUPPORT_DEVICE(0) tud_int_handler(0); -#endif + #endif } -void usbfs_d0fifo_handler(void) -{ +void usbfs_d0fifo_handler(void) { IRQn_Type irq = R_FSP_CurrentIrqGet(); R_BSP_IrqStatusClear(irq); + // TODO not used yet +} -#if CFG_TUH_ENABLED - tuh_int_handler(0); -#endif +void usbfs_d1fifo_handler(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + // TODO not used yet +} -#if CFG_TUD_ENABLED - tud_int_handler(0); -#endif +//------------- USB1 HighSpeed -------------// +#ifdef BOARD_HAS_USB_HIGHSPEED + +void usbhs_interrupt_handler(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + #if PORT_SUPPORT_HOST(1) + tuh_int_handler(1); + #endif + + #if PORT_SUPPORT_DEVICE(1) + tud_int_handler(1); + #endif } -void usbfs_d1fifo_handler(void) -{ +void usbhs_d0fifo_handler(void) { IRQn_Type irq = R_FSP_CurrentIrqGet(); R_BSP_IrqStatusClear(irq); + // TODO not used yet +} -#if CFG_TUH_ENABLED - tuh_int_handler(0); -#endif +void usbhs_d1fifo_handler(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + // TODO not used yet +} -#if CFG_TUD_ENABLED - tud_int_handler(0); #endif -} //--------------------------------------------------------------------+ // stdlib diff --git a/hw/bsp/ra/vector_data.h b/hw/bsp/ra/vector_data.h index 3d8a24634..ca667faa3 100644 --- a/hw/bsp/ra/vector_data.h +++ b/hw/bsp/ra/vector_data.h @@ -6,22 +6,29 @@ extern "C" { #endif -#ifndef VECTOR_DATA_IRQ_COUNT - #define VECTOR_DATA_IRQ_COUNT 4 -#endif - /* ISR prototypes */ void usbfs_interrupt_handler(void); void usbfs_resume_handler(void); void usbfs_d0fifo_handler(void); void usbfs_d1fifo_handler(void); +#ifdef BOARD_HAS_USB_HIGHSPEED +void usbhs_interrupt_handler(void); +void usbhs_d0fifo_handler(void); +void usbhs_d1fifo_handler(void); +#endif + /* Vector table allocations */ #define USBFS_INT_IRQn 0 #define USBFS_RESUME_IRQn 1 #define USBFS_FIFO_0_IRQn 2 #define USBFS_FIFO_1_IRQn 3 +#define USBHS_USB_INT_RESUME_IRQn 4 /* USBHS USB INT RESUME (USBHS interrupt) */ +#define USBHS_FIFO_0_IRQn 5 /* USBHS FIFO 0 (DMA transfer request 0) */ +#define USBHS_FIFO_1_IRQn 6 /* USBHS FIFO 1 (DMA transfer request 1) */ + + #ifdef __cplusplus } #endif diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 9f3be78fd..496ebfc85 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -327,6 +327,7 @@ // Renesas //--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N, OPT_MCU_RAXXX) + #define TUP_USBIP_RUSB2 #define TUP_DCD_ENDPOINT_MAX 10 //--------------------------------------------------------------------+ diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index e9ac46517..83d2a34c6 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -31,8 +31,7 @@ // We disable SOF for now until needed later on #define USE_SOF 0 -#if CFG_TUD_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \ - TU_CHECK_MCU(OPT_MCU_RAXXX)) +#if CFG_TUD_ENABLED && defined(TUP_USBIP_RUSB2) #include "device/dcd.h" #include "rusb2_type.h" -- cgit v1.3.1 From 4f4c93594d8f82c18f9a1052c4da2e7c31fc1b8c Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 5 Jul 2023 17:51:36 +0700 Subject: minor pipe clean up --- src/portable/renesas/rusb2/dcd_rusb2.c | 74 ++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 31 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 83d2a34c6..b58e0be01 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -93,20 +93,20 @@ typedef struct TU_ATTR_PACKED { typedef union TU_ATTR_PACKED { struct { - volatile uint16_t u8: 8; - volatile uint16_t : 0; + volatile uint8_t u8; + volatile uint8_t reserved8; }; volatile uint16_t u16; } hw_fifo_t; typedef union TU_ATTR_PACKED { struct { - volatile uint32_t : 24; - volatile uint32_t u8: 8; + volatile uint8_t reserved8[3]; + volatile uint8_t u8; }; struct { - volatile uint32_t : 16; - volatile uint32_t u16: 16; + volatile uint16_t reserved16; + volatile uint16_t u16; }; volatile uint32_t u32; } hw_fifo32_t; @@ -126,6 +126,19 @@ typedef struct TU_ATTR_PACKED TU_ATTR_PACKED_END // End of definition of packed structs (used by the CCRX toolchain) TU_ATTR_BIT_FIELD_ORDER_END +// Transfer conditions specifiable for each pipe: +// - Pipe 0: Control transfer with 64-byte single buffer +// - Pipes 1 and 2: Bulk isochronous transfer continuous transfer mode with programmable buffer size up +// to 2 KB and optional double buffer +// - Pipes 3 to 5: Bulk transfer continuous transfer mode with programmable buffer size up to 2 KB and +// optional double buffer +// - Pipes 6 to 9: Interrupt transfer with 64-byte single buffer +enum { + PIPE_1ST_BULK = 3, + PIPE_1ST_INTERRUPT = 6, + PIPE_COUNT = 10, +}; + typedef struct { pipe_state_t pipe[10]; @@ -137,34 +150,33 @@ typedef struct //--------------------------------------------------------------------+ static dcd_data_t _dcd; -#ifndef FIRST_BULK_PIPE -#define FIRST_BULK_PIPE 3 -#endif - static unsigned find_pipe(unsigned xfer) { switch (xfer) { - case TUSB_XFER_ISOCHRONOUS: - for (int i = 1; i <= 2; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_BULK: - for (int i = FIRST_BULK_PIPE; i <= 5; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - for (int i = 1; i <= 1; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_INTERRUPT: - for (int i = 6; i <= 9; ++i) { - if (0 == _dcd.pipe[i].ep) return i; - } - break; - default: - /* No support for control transfer */ - break; + case TUSB_XFER_ISOCHRONOUS: + for (int i = 1; i < PIPE_1ST_BULK; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + break; + + case TUSB_XFER_BULK: + for (int i = PIPE_1ST_BULK; i < PIPE_1ST_INTERRUPT; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + for (int i = 1; i < PIPE_1ST_BULK; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + break; + + case TUSB_XFER_INTERRUPT: + for (int i = PIPE_1ST_INTERRUPT; i < PIPE_COUNT; ++i) { + if (0 == _dcd.pipe[i].ep) return i; + } + break; + + default: + /* No support for control transfer */ + break; } return 0; } -- cgit v1.3.1 From f308435b649c37f0cffc1d5a566fb71c22b57aa1 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 5 Jul 2023 22:09:35 +0700 Subject: update ra type to include usbhs registers --- hw/bsp/ra/family.cmake | 1 - hw/bsp/ra/family.mk | 1 - src/portable/renesas/rusb2/rusb2_ra.c | 16 -- src/portable/renesas/rusb2/rusb2_ra.h | 83 +++++---- src/portable/renesas/rusb2/rusb2_type.h | 315 ++++++++++++++++++++------------ 5 files changed, 245 insertions(+), 171 deletions(-) delete mode 100644 src/portable/renesas/rusb2/rusb2_ra.c (limited to 'src') diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index f4e978230..74329165f 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -120,7 +120,6 @@ function(family_configure_example TARGET RTOS) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c - ${TOP}/src/portable/renesas/rusb2/rusb2_ra.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index 9b6b02c02..b6e1bb0ae 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -18,7 +18,6 @@ CFLAGS += \ SRC_C += \ src/portable/renesas/rusb2/dcd_rusb2.c \ src/portable/renesas/rusb2/hcd_rusb2.c \ - src/portable/renesas/rusb2/rusb2_ra.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \ $(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \ diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c deleted file mode 100644 index ff2191b1f..000000000 --- a/src/portable/renesas/rusb2/rusb2_ra.c +++ /dev/null @@ -1,16 +0,0 @@ -#include "tusb_option.h" -#include "rusb2_ra.h" - -#if (CFG_TUSB_RHPORT0_MODE != 0) -IRQn_Type _usb_fs_irqn = USBFS_INT_IRQn; -void tud_set_irq_usbfs(IRQn_Type q) { - _usb_fs_irqn = q; -} -#endif - -#if (CFG_TUSB_RHPORT1_MODE != 0) -IRQn_Type _usb_hs_irqn = USBHS_USB_INT_RESUME_IRQn; -void tud_set_irq_usbhs(IRQn_Type q) { - _usb_hs_irqn = q; -} -#endif diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 07fcafe6f..ca7c38907 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -47,55 +47,53 @@ extern "C" { #pragma GCC diagnostic pop #endif -extern IRQn_Type _usb_fs_irqn; -extern IRQn_Type _usb_hs_irqn; +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ -#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) -// fallback -#define CFG_TUSB_RHPORT0_MODE ( CFG_TUD_ENABLED ? OPT_MODE_DEVICE : OPT_MODE_HOST ) -#define CFG_TUSB_RHPORT1_MODE 0 +// IAR does not have __builtin_ctz +#if defined(__ICCARM__) + #define __builtin_ctz(x) __iar_builtin_CLZ(__iar_builtin_RBIT(x)) #endif -#if defined(__ICCARM__) - #define __builtin_ctz(x) __iar_builtin_CLZ(__iar_builtin_RBIT(x)) +typedef struct { + uint32_t reg_base; + int32_t irqnum; +}rusb2_controller_t; + +#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8) + #define RUSB2_HAS_HIGHSPEED + #define RUSB2_CONTROLLER_COUNT 2 +#else + #define RUSB2_CONTROLLER_COUNT 1 #endif +// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP +static rusb2_controller_t rusb2_controller[] = { + { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn }, + #ifdef RUSB2_HAS_HIGHSPEED + { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn }, + #endif +}; + TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) { -#ifdef CFG_TUSB_RHPORT1_MODE -#if (CFG_TUSB_RHPORT1_MODE != 0) - if (rhport == 1) { - NVIC_EnableIRQ(_usb_hs_irqn); - } -#endif -#endif - -#ifdef CFG_TUSB_RHPORT0_MODE -#if (CFG_TUSB_RHPORT0_MODE != 0) - if (rhport == 0) { - NVIC_EnableIRQ(_usb_fs_irqn); - } -#endif -#endif + #if RUSB2_CONTROLLER_COUNT > 1 + NVIC_EnableIRQ(rusb2_controller[rhport].irqnum); + #else + (void) rhport; + NVIC_EnableIRQ(rusb2_controller[0].irqnum); + #endif } TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) { -#ifdef CFG_TUSB_RHPORT1_MODE -#if (CFG_TUSB_RHPORT1_MODE != 0) - if (rhport == 1) { - NVIC_DisableIRQ(_usb_hs_irqn); - } -#endif -#endif - -#ifdef CFG_TUSB_RHPORT0_MODE -#if (CFG_TUSB_RHPORT0_MODE != 0) - if (rhport == 0) { - NVIC_DisableIRQ(_usb_fs_irqn); - } -#endif -#endif + #if RUSB2_CONTROLLER_COUNT > 1 + NVIC_DisableIRQ(rusb2_controller[rhport].irqnum); + #else + (void) rhport; + NVIC_DisableIRQ(rusb2_controller[0].irqnum); + #endif } // MCU specific PHY init @@ -103,6 +101,15 @@ TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) { } +void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) { + #if RUSB2_CONTROLLER_COUNT > 1 + rusb2_controller[rhport].irqnum = irqnum; + #else + (void) rhport; + rusb2_controller[0].irqnum = irqnum; + #endif +} + #ifdef __cplusplus } #endif diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index 90ba4f012..0928f5aeb 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -46,10 +46,10 @@ typedef struct { volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */ struct TU_ATTR_PACKED { - uint16_t : 8; + uint16_t : 8; volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */ volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */ - uint16_t : 6; + uint16_t : 6; } E_b; }; @@ -62,7 +62,8 @@ typedef struct { }; } RUSB2_PIPE_TR_t; /* Size = 4 (0x4) */ -/* LINK_REG Structure */ + +/* RUSB2 Registers Structure */ typedef struct { union { volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */ @@ -74,7 +75,7 @@ typedef struct { volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */ volatile uint16_t DRPD : 1; /* [5..5] D+/D- Line Resistor Control */ volatile uint16_t DCFM : 1; /* [6..6] Controller Function Select */ - uint16_t : 1; + volatile uint16_t HSE : 1; // [7..7] High-Speed Operation Enable volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */ uint16_t : 1; volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */ @@ -87,7 +88,7 @@ typedef struct { struct TU_ATTR_PACKED { volatile uint16_t BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */ - uint16_t : 12; + uint16_t : 12; } BUSWAIT_b; }; @@ -98,8 +99,7 @@ typedef struct { volatile const uint16_t LNST : 2; /* [1..0] USB Data Line Status Monitor */ volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */ uint16_t : 2; - volatile const uint16_t - SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */ + volatile const uint16_t SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */ volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */ uint16_t : 7; volatile const uint16_t OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */ @@ -111,7 +111,7 @@ typedef struct { struct TU_ATTR_PACKED { volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */ - uint16_t : 15; + uint16_t : 15; } PLLSTA_b; }; @@ -139,7 +139,7 @@ typedef struct { struct TU_ATTR_PACKED { volatile uint16_t UTST : 4; /* [3..0] Test Mode */ - uint16_t : 12; + uint16_t : 12; } TESTMODE_b; }; volatile const uint16_t RESERVED1; @@ -295,7 +295,7 @@ typedef struct { volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */ struct TU_ATTR_PACKED { - uint16_t : 8; + uint16_t : 8; volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */ volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */ volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */ @@ -316,7 +316,10 @@ typedef struct { volatile uint16_t SACKE : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */ volatile uint16_t SIGNE : 1; /* [5..5] Setup Transaction Error Interrupt Enable */ volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 4; + uint16_t : 1; + volatile uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + volatile uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */ volatile uint16_t DTCHE : 1; /* [12..12] Disconnection Detection Interrupt Enable */ uint16_t : 1; @@ -340,7 +343,7 @@ typedef struct { volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */ volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */ volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */ - uint16_t : 6; + uint16_t : 6; } BRDYENB_b; }; @@ -358,7 +361,7 @@ typedef struct { volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */ volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */ volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */ - uint16_t : 6; + uint16_t : 6; } NRDYENB_b; }; @@ -376,7 +379,7 @@ typedef struct { volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */ volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */ volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */ - uint16_t : 6; + uint16_t : 6; } BEMPENB_b; }; @@ -390,7 +393,7 @@ typedef struct { volatile uint16_t BRDYM : 1; /* [6..6] BRDY Interrupt Status Clear Timing */ uint16_t : 1; volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */ - uint16_t : 7; + uint16_t : 7; } SOFCFG_b; }; @@ -467,7 +470,7 @@ typedef struct { volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */ volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */ volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */ - uint16_t : 6; + uint16_t : 6; } BRDYSTS_b; }; @@ -485,7 +488,7 @@ typedef struct { volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */ volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */ volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */ - uint16_t : 6; + uint16_t : 6; } NRDYSTS_b; }; @@ -503,7 +506,7 @@ typedef struct { volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */ volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */ volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */ - uint16_t : 6; + uint16_t : 6; } BEMPSTS_b; }; @@ -609,7 +612,8 @@ typedef struct { volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */ uint16_t : 2; volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */ - uint16_t : 2; + volatile uint16_t CSSTS : 1; /* [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + volatile uint16_t CSCLR : 1; /* [13..13] Split Transaction CSPLIT Status Clear */ volatile uint16_t SUREQ : 1; /* [14..14] Setup Token Transmission */ volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */ } DCPCTR_b; @@ -621,7 +625,7 @@ typedef struct { struct TU_ATTR_PACKED { volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */ - uint16_t : 12; + uint16_t : 12; } PIPESEL_b; }; volatile const uint16_t RESERVED11; @@ -634,21 +638,31 @@ typedef struct { volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */ uint16_t : 2; volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */ - uint16_t : 1; + volatile uint16_t CNTMD : 1; /* [8..8] Continuous Transfer Mode */ volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */ volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */ uint16_t : 3; volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */ } PIPECFG_b; }; - volatile const uint16_t RESERVED12; + + union { + volatile uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ + + struct { + volatile uint16_t BUFNMB : 8; // [7..0] Buffer NumberThese bits specify the FIFO buffer number of the selected pipe (04h to 87h) + uint16_t : 2; + volatile uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + uint16_t : 1; + } PIPEBUF_b; + }; union { volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */ struct TU_ATTR_PACKED { - volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */ - uint16_t : 3; + volatile uint16_t MXPS : 11; /* [10..0] Maximum Packet Size */ + uint16_t : 1; volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */ } PIPEMAXP_b; }; @@ -694,11 +708,9 @@ typedef struct { struct TU_ATTR_PACKED { volatile uint16_t RPDME0 : 1; /* [0..0] D- Pin Pull-Down Control */ volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */ - volatile uint16_t - IDMSINKE0 : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + volatile uint16_t IDMSINKE0 : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ - volatile uint16_t - IDPSINKE0 : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + volatile uint16_t IDPSINKE0 : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */ uint16_t : 1; volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ @@ -715,7 +727,7 @@ typedef struct { struct TU_ATTR_PACKED { volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */ - uint16_t : 15; + uint16_t : 15; } UCKSEL_b; }; volatile const uint16_t RESERVED18; @@ -737,11 +749,11 @@ typedef struct { volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */ struct TU_ATTR_PACKED { - uint16_t : 6; + uint16_t : 6; volatile uint16_t USBSPD : 2; /* [7..6] Transfer Speed of Communication Target Device */ volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */ volatile uint16_t UPPHUB : 4; /* [14..11] Communication Target Connecting Hub Register */ - uint16_t : 1; + uint16_t : 1; } DEVADD_b[10]; }; volatile const uint32_t RESERVED21[3]; @@ -754,7 +766,7 @@ typedef struct { volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */ volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */ volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */ - uint32_t : 28; + uint32_t : 28; } PHYSLEW_b; }; volatile const uint32_t RESERVED22[3]; @@ -763,9 +775,9 @@ typedef struct { volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */ struct TU_ATTR_PACKED { - uint16_t : 7; + uint16_t : 7; volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */ - uint16_t : 8; + uint16_t : 8; } LPCTRL_b; }; @@ -773,9 +785,9 @@ typedef struct { volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */ struct TU_ATTR_PACKED { - uint16_t : 14; + uint16_t : 14; volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */ - uint16_t : 1; + uint16_t : 1; } LPSTS_b; }; volatile const uint32_t RESERVED23[15]; @@ -793,7 +805,7 @@ typedef struct { uint16_t : 2; volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */ volatile const uint16_t PDDETSTS : 1; /* [9..9] PDDET Status */ - uint16_t : 6; + uint16_t : 6; } BCCTRL_b; }; volatile const uint16_t RESERVED24; @@ -809,7 +821,7 @@ typedef struct { volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */ uint16_t : 2; volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */ - uint16_t : 1; + uint16_t : 1; } PL1CTRL1_b; }; @@ -817,10 +829,10 @@ typedef struct { volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */ struct TU_ATTR_PACKED { - uint16_t : 8; + uint16_t : 8; volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */ volatile uint16_t RWEMON : 1; /* [12..12] RWE Value Monitor */ - uint16_t : 3; + uint16_t : 3; } PL1CTRL2_b; }; @@ -830,7 +842,7 @@ typedef struct { struct TU_ATTR_PACKED { volatile uint16_t L1REQ : 1; /* [0..0] L1 Transition Request */ volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */ - uint16_t : 13; + uint16_t : 13; } HL1CTRL1_b; }; @@ -846,18 +858,48 @@ typedef struct { volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */ } HL1CTRL2_b; }; - volatile const uint32_t RESERVED25[5]; + + volatile uint32_t RESERVED25_1; + + union { + volatile uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ + + struct { + volatile uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ + volatile uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + volatile uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ + volatile uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ + volatile uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset value for adjusting the terminating resistance. */ + uint16_t : 1; + } PHYTRIM1_b; + }; + + union { + volatile uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ + + struct { + volatile uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ + uint16_t : 3; + volatile uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ + volatile uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ + uint16_t : 2; + volatile uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ + uint16_t : 1; + } PHYTRIM2_b; + }; + volatile uint32_t RESERVED25_2[3]; union { volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */ struct TU_ATTR_PACKED { - uint32_t : 20; + uint32_t : 20; volatile const uint32_t DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */ volatile const uint32_t DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */ uint32_t : 1; volatile const uint32_t DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */ - uint32_t : 8; + uint32_t : 8; } DPUSR0R_b; }; @@ -865,7 +907,7 @@ typedef struct { volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ struct TU_ATTR_PACKED { - uint32_t : 4; + uint32_t : 4; volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */ volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */ uint32_t : 1; @@ -875,7 +917,7 @@ typedef struct { volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */ uint32_t : 1; volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */ - uint32_t : 8; + uint32_t : 8; } DPUSR1R_b; }; @@ -891,7 +933,7 @@ typedef struct { uint16_t : 2; volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */ volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */ - uint16_t : 6; + uint16_t : 6; } DPUSR2R_b; }; @@ -901,7 +943,7 @@ typedef struct { struct TU_ATTR_PACKED { volatile uint16_t FIXPHY : 1; /* [0..0] USB Transceiver Control Fix */ volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */ - uint16_t : 14; + uint16_t : 14; } DPUSRCR_b; }; volatile const uint32_t RESERVED26[165]; @@ -924,7 +966,7 @@ typedef struct { volatile const uint32_t DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */ uint32_t : 1; volatile const uint32_t DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */ - uint32_t : 8; + uint32_t : 8; } DPUSR0R_FS_b; }; @@ -947,10 +989,10 @@ typedef struct { volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */ uint32_t : 1; volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */ - uint32_t : 8; + uint32_t : 8; } DPUSR1R_FS_b; }; -} RUSB2_REG_t; /* Size = 1032 (0x408) */ +} rusb2_reg_t; /* Size = 1032 (0x408) */ TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */ TU_ATTR_BIT_FIELD_ORDER_END @@ -970,13 +1012,15 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_PIPE_TR_N_TRNCNT_Pos (0UL) /* TRNCNT (Bit 0) */ #define RUSB2_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /* TRNCNT (Bitfield-Mask: 0xffff) */ -// LINK_REG +// Core Registers // SYSCFG #define RUSB2_SYSCFG_SCKE_Pos (10UL) /* SCKE (Bit 10) */ #define RUSB2_SYSCFG_SCKE_Msk (0x400UL) /* SCKE (Bitfield-Mask: 0x01) */ #define RUSB2_SYSCFG_CNEN_Pos (8UL) /* CNEN (Bit 8) */ #define RUSB2_SYSCFG_CNEN_Msk (0x100UL) /* CNEN (Bitfield-Mask: 0x01) */ +#define RUSB2_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ +#define RUSB2_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ #define RUSB2_SYSCFG_DCFM_Pos (6UL) /* DCFM (Bit 6) */ #define RUSB2_SYSCFG_DCFM_Msk (0x40UL) /* DCFM (Bitfield-Mask: 0x01) */ #define RUSB2_SYSCFG_DRPD_Pos (5UL) /* DRPD (Bit 5) */ @@ -1135,6 +1179,10 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_INTENB1_DTCHE_Msk (0x1000UL) /* DTCHE (Bitfield-Mask: 0x01) */ #define RUSB2_INTENB1_ATTCHE_Pos (11UL) /* ATTCHE (Bit 11) */ #define RUSB2_INTENB1_ATTCHE_Msk (0x800UL) /* ATTCHE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ +#define RUSB2_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ +#define RUSB2_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ +#define RUSB2_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ #define RUSB2_INTENB1_EOFERRE_Pos (6UL) /* EOFERRE (Bit 6) */ #define RUSB2_INTENB1_EOFERRE_Msk (0x40UL) /* EOFERRE (Bitfield-Mask: 0x01) */ #define RUSB2_INTENB1_SIGNE_Pos (5UL) /* SIGNE (Bit 5) */ @@ -1299,6 +1347,10 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_DCPCTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ #define RUSB2_DCPCTR_SUREQ_Pos (14UL) /* SUREQ (Bit 14) */ #define RUSB2_DCPCTR_SUREQ_Msk (0x4000UL) /* SUREQ (Bitfield-Mask: 0x01) */ +#define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ +#define RUSB2_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ +#define RUSB2_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ +#define RUSB2_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ #define RUSB2_DCPCTR_SUREQCLR_Pos (11UL) /* SUREQCLR (Bit 11) */ #define RUSB2_DCPCTR_SUREQCLR_Msk (0x800UL) /* SUREQCLR (Bitfield-Mask: 0x01) */ #define RUSB2_DCPCTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ @@ -1325,6 +1377,8 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_PIPECFG_BFRE_Msk (0x400UL) /* BFRE (Bitfield-Mask: 0x01) */ #define RUSB2_PIPECFG_DBLB_Pos (9UL) /* DBLB (Bit 9) */ #define RUSB2_PIPECFG_DBLB_Msk (0x200UL) /* DBLB (Bitfield-Mask: 0x01) */ +#define RUSB2_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ +#define RUSB2_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ #define RUSB2_PIPECFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ #define RUSB2_PIPECFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ #define RUSB2_PIPECFG_DIR_Pos (4UL) /* DIR (Bit 4) */ @@ -1332,6 +1386,12 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_PIPECFG_EPNUM_Pos (0UL) /* EPNUM (Bit 0) */ #define RUSB2_PIPECFG_EPNUM_Msk (0xfUL) /* EPNUM (Bitfield-Mask: 0x0f) */ +// PIPEBUF +#define RUSB2_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ +#define RUSB2_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ +#define RUSB2_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ +#define RUSB2_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ + // PIPEMAXP #define RUSB2_PIPEMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ #define RUSB2_PIPEMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ @@ -1478,6 +1538,28 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_HL1CTRL2_L1ADDR_Pos (0UL) /* L1ADDR (Bit 0) */ #define RUSB2_HL1CTRL2_L1ADDR_Msk (0xfUL) /* L1ADDR (Bitfield-Mask: 0x0f) */ +// PHYTRIM1 +#define RUSB2_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ +#define RUSB2_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ +#define RUSB2_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ +#define RUSB2_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ +#define RUSB2_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ +#define RUSB2_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ +#define RUSB2_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ +#define RUSB2_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ +#define RUSB2_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ +#define RUSB2_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ + +// PHYTRIM2 +#define RUSB2_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ +#define RUSB2_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ +#define RUSB2_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ +#define RUSB2_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ +#define RUSB2_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ +#define RUSB2_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ +#define RUSB2_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ +#define RUSB2_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ + // DPUSR0R #define RUSB2_DPUSR0R_DVBSTSHM_Pos (23UL) /* DVBSTSHM (Bit 23) */ #define RUSB2_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */ @@ -1599,69 +1681,72 @@ TU_ATTR_BIT_FIELD_ORDER_END //--------------------------------------------------------------------+ TU_VERIFY_STATIC(sizeof(RUSB2_PIPE_TR_t) == 4, "incorrect size"); -TU_VERIFY_STATIC(sizeof(RUSB2_REG_t) == 1032, "incorrect size"); - -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSCFG ) == 0x00000000, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BUSWAIT ) == 0x00000002, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSSTS0 ) == 0x00000004, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PLLSTA ) == 0x00000006, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DVSTCTR0 ) == 0x00000008, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, TESTMODE ) == 0x0000000C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFO ) == 0x00000014, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFO ) == 0x00000018, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFO ) == 0x0000001C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFOSEL ) == 0x00000020, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFOCTR ) == 0x00000022, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFOSEL ) == 0x00000028, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFOCTR ) == 0x0000002A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFOSEL ) == 0x0000002C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFOCTR ) == 0x0000002E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTENB0 ) == 0x00000030, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTENB1 ) == 0x00000032, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BRDYENB ) == 0x00000036, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, NRDYENB ) == 0x00000038, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BEMPENB ) == 0x0000003A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SOFCFG ) == 0x0000003C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PHYSET ) == 0x0000003E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTSTS0 ) == 0x00000040, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTSTS1 ) == 0x00000042, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BRDYSTS ) == 0x00000046, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, NRDYSTS ) == 0x00000048, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BEMPSTS ) == 0x0000004A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, FRMNUM ) == 0x0000004C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, UFRMNUM ) == 0x0000004E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBADDR ) == 0x00000050, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBREQ ) == 0x00000054, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBVAL ) == 0x00000056, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBINDX ) == 0x00000058, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBLENG ) == 0x0000005A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPCFG ) == 0x0000005C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPMAXP ) == 0x0000005E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPCTR ) == 0x00000060, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPESEL ) == 0x00000064, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPECFG ) == 0x00000068, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPEMAXP ) == 0x0000006C, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPEPERI ) == 0x0000006E, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPE_CTR ) == 0x00000070, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPE_TR ) == 0x00000090, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBBCCTRL0 ) == 0x000000B0, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, UCKSEL ) == 0x000000C4, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBMC ) == 0x000000CC, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DEVADD ) == 0x000000D0, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PHYSLEW ) == 0x000000F0, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, LPCTRL ) == 0x00000100, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, LPSTS ) == 0x00000102, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BCCTRL ) == 0x00000140, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PL1CTRL1 ) == 0x00000144, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PL1CTRL2 ) == 0x00000146, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, HL1CTRL1 ) == 0x00000148, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, HL1CTRL2 ) == 0x0000014A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR0R ) == 0x00000160, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R ) == 0x00000164, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR2R ) == 0x00000168, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSRCR ) == 0x0000016A, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR0R_FS ) == 0x00000400, "incorrect offset"); -TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect offset"); +TU_VERIFY_STATIC(sizeof(rusb2_reg_t) == 1032, "incorrect size"); + +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SYSCFG ) == 0x0000, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BUSWAIT ) == 0x0002, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SYSSTS0 ) == 0x0004, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PLLSTA ) == 0x0006, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DVSTCTR0 ) == 0x0008, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, TESTMODE ) == 0x000C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFO ) == 0x0014, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFO ) == 0x0018, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFO ) == 0x001C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFOSEL ) == 0x0020, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFOCTR ) == 0x0022, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFOSEL ) == 0x0028, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFOCTR ) == 0x002A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFOSEL ) == 0x002C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFOCTR ) == 0x002E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTENB0 ) == 0x0030, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTENB1 ) == 0x0032, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BRDYENB ) == 0x0036, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, NRDYENB ) == 0x0038, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BEMPENB ) == 0x003A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SOFCFG ) == 0x003C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYSET ) == 0x003E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTSTS0 ) == 0x0040, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTSTS1 ) == 0x0042, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BRDYSTS ) == 0x0046, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, NRDYSTS ) == 0x0048, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BEMPSTS ) == 0x004A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, FRMNUM ) == 0x004C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, UFRMNUM ) == 0x004E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBADDR ) == 0x0050, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBREQ ) == 0x0054, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBVAL ) == 0x0056, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBINDX ) == 0x0058, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBLENG ) == 0x005A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPCFG ) == 0x005C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPMAXP ) == 0x005E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPCTR ) == 0x0060, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPESEL ) == 0x0064, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPECFG ) == 0x0068, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEBUF ) == 0x006A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEMAXP ) == 0x006C, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEPERI ) == 0x006E, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPE_CTR ) == 0x0070, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPE_TR ) == 0x0090, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBBCCTRL0 ) == 0x00B0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, UCKSEL ) == 0x00C4, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBMC ) == 0x00CC, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DEVADD ) == 0x00D0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYSLEW ) == 0x00F0, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, LPCTRL ) == 0x0100, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, LPSTS ) == 0x0102, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BCCTRL ) == 0x0140, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PL1CTRL1 ) == 0x0144, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PL1CTRL2 ) == 0x0146, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, HL1CTRL1 ) == 0x0148, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, HL1CTRL2 ) == 0x014A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYTRIM1 ) == 0x0150, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYTRIM2 ) == 0x0152, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR0R ) == 0x0160, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR1R ) == 0x0164, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR2R ) == 0x0168, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSRCR ) == 0x016A, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR0R_FS ) == 0x0400, "incorrect offset"); +TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR1R_FS ) == 0x0404, "incorrect offset"); #ifdef __cplusplus } -- cgit v1.3.1 From 95b77a0e7356b5f6625fbdb66f35415db3aac7a9 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 6 Jul 2023 15:54:07 +0700 Subject: add rusb2_module_start(), more update for multiple ports for dcd rusb2 --- hw/bsp/ra/family.c | 7 - src/portable/renesas/rusb2/dcd_rusb2.c | 280 +++++++++++++++++++------------- src/portable/renesas/rusb2/rusb2_ra.h | 38 ++--- src/portable/renesas/rusb2/rusb2_rx.h | 6 + src/portable/renesas/rusb2/rusb2_type.h | 1 + 5 files changed, 190 insertions(+), 142 deletions(-) (limited to 'src') diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 36b46beab..2c21a9967 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -104,13 +104,6 @@ void board_init(void) { R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x01; #endif - // Enable USB module - R_MSTP->MSTPCRB &= ~(1U << 11U); // FS - -#ifdef BOARD_HAS_USB_HIGHSPEED - R_MSTP->MSTPCRB &= ~(1U << 12U); -#endif - #if CFG_TUSB_OS == OPT_OS_FREERTOS // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) NVIC_SetPriority(USBFS_INT_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index b58e0be01..27d525b68 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -65,9 +65,9 @@ /* LINK core registers */ #if defined(__CCRX__) - #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE) + #define RUSB2 ((rusb2_reg_t __evenaccess*) RUSB2_REG_BASE) #elif defined(__RX__) - #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE) + #define RUSB2 ((rusb2_reg_t*) RUSB2_REG_BASE) #elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE) #else @@ -145,10 +145,15 @@ typedef struct uint8_t ep[2][16]; /* a lookup table for a pipe index from an endpoint address */ } dcd_data_t; +static dcd_data_t _dcd; + //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -static dcd_data_t _dcd; + +TU_ATTR_ALWAYS_INLINE static inline bool is_highspeed(uint8_t rhport) { + return rhport == 1; +} static unsigned find_pipe(unsigned xfer) { @@ -543,38 +548,60 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num) static void process_bus_reset(uint8_t rhport) { - RUSB2->BEMPENB = 1; - RUSB2->BRDYENB = 1; - RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; - RUSB2->D0FIFOSEL = 0; - while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - RUSB2->D1FIFOSEL = 0; - while (RUSB2->D1FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ - volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&RUSB2->PIPE_CTR[0])); - volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&RUSB2->PIPE_TR[0].E)); + rusb2_reg_t* rusb = RUSB2_REG(rhport); + + rusb->BEMPENB = 1; + rusb->BRDYENB = 1; + rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; + + rusb->D0FIFOSEL = 0; + while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + + rusb->D1FIFOSEL = 0; + while (rusb->D1FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + + volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&rusb->PIPE_CTR[0])); + volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&rusb->PIPE_TR[0].E)); + for (int i = 1; i <= 5; ++i) { - RUSB2->PIPESEL = i; - RUSB2->PIPECFG = 0; + rusb->PIPESEL = i; + rusb->PIPECFG = 0; *ctr = RUSB2_PIPE_CTR_ACLRM_Msk; *ctr = 0; ++ctr; *tre = TU_BIT(8); tre += 2; } + for (int i = 6; i <= 9; ++i) { - RUSB2->PIPESEL = i; - RUSB2->PIPECFG = 0; + rusb->PIPESEL = i; + rusb->PIPECFG = 0; *ctr = RUSB2_PIPE_CTR_ACLRM_Msk; *ctr = 0; ++ctr; } tu_varclr(&_dcd); -#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) - dcd_event_bus_reset(rhport, TUSB_SPEED_HIGH, true); -#else - dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); -#endif + TU_LOG3("Bus reset, RHST = %u\r\n", rusb->DVSTCTR0_b.RHST); + tusb_speed_t speed; + switch(rusb->DVSTCTR0 & RUSB2_DVSTCTR0_RHST_Msk) { + case RUSB2_DVSTCTR0_RHST_LS: + speed = TUSB_SPEED_LOW; + break; + + case RUSB2_DVSTCTR0_RHST_FS: + speed = TUSB_SPEED_FULL; + break; + + case RUSB2_DVSTCTR0_RHST_HS: + speed = TUSB_SPEED_HIGH; + break; + + default: + TU_ASSERT(false, ); + } + + dcd_event_bus_reset(rhport, speed, true); } static void process_set_address(uint8_t rhport) @@ -625,56 +652,63 @@ static void enable_interrupt(uint32_t pswi) void dcd_init(uint8_t rhport) { - (void)rhport; + rusb2_reg_t* rusb = RUSB2_REG(rhport); -#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) - RUSB2->SYSCFG_b.HSE = 1; - RUSB2->PHYSET_b.DIRPD = 0; - R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS); - RUSB2->PHYSET_b.PLLRESET = 0; - //RUSB2->PHYSET_b.REPSTART = 1; - RUSB2->SYSCFG_b.DRPD = 0; - RUSB2->SYSCFG_b.USBE = 1; - RUSB2->LPSTS_b.SUSPENDM = 1; - while (!RUSB2->PLLSTA_b.PLLLOCK); - //RUSB2->BUSWAIT |= 0x0F00U; - //RUSB2->PHYSET_b.REPSEL = 1; - RUSB2->CFIFOSEL_b.MBW = 1; - RUSB2->D0FIFOSEL_b.MBW = 1; - RUSB2->D1FIFOSEL_b.MBW = 1; - RUSB2->INTSTS0 = 0; -#else - RUSB2->SYSCFG_b.SCKE = 1; - while (!RUSB2->SYSCFG_b.SCKE) ; - RUSB2->SYSCFG_b.DRPD = 0; - RUSB2->SYSCFG_b.DCFM = 0; - RUSB2->SYSCFG_b.USBE = 1; -#endif + rusb2_module_start(rhport, true); - // MCU specific PHY init - rusb2_phy_init(); + if ( is_highspeed(rhport) ) { + rusb->SYSCFG_b.HSE = 1; -#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE) - RUSB2->PHYSLEW = 0x5; - RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */ + // leave CLKSEL as default (0x11) 24Mhz - #define USB_VDCEN (0x0080U) /* b7: Regulator ON/OFF control */ - RUSB2->USBMC = (uint16_t) (RUSB2->USBMC | (USB_VDCEN)); -#endif + // Power and reset UTMI Phy + uint16_t physet = (rusb->PHYSET | RUSB2_PHYSET_PLLRESET_Msk) & ~RUSB2_PHYSET_DIRPD_Msk; + rusb->PHYSET = physet; + R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS); + rusb->PHYSET_b.PLLRESET = 0; + + // set UTMI to operating mode and wait for PLL lock confirmation + rusb->LPSTS_b.SUSPENDM = 1; + while (!rusb->PLLSTA_b.PLLLOCK) {} + + rusb->SYSCFG_b.DRPD = 0; + rusb->SYSCFG_b.USBE = 1; + + // Set CPU bus wait time (fine tunne later) + // rusb2->BUSWAIT |= 0x0F00U; + + rusb->PHYSET_b.REPSEL = 1; + + rusb->CFIFOSEL_b.MBW = 1; + rusb->D0FIFOSEL_b.MBW = 1; + rusb->D1FIFOSEL_b.MBW = 1; + } else { + rusb->SYSCFG_b.SCKE = 1; + while (!rusb->SYSCFG_b.SCKE) {} + rusb->SYSCFG_b.DRPD = 0; + rusb->SYSCFG_b.DCFM = 0; + rusb->SYSCFG_b.USBE = 1; + + // MCU specific PHY init + rusb2_phy_init(); + + rusb->PHYSLEW = 0x5; + rusb->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */ + + // rusb2->USBMC = (uint16_t) (rusb2->USBMC | RUSB2_USBMC_VDCEN_Msk); + } /* Setup default control pipe */ - RUSB2->DCPMAXP_b.MXPS = 64; - RUSB2->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk | - RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) | - RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk; - RUSB2->BEMPENB = 1; - RUSB2->BRDYENB = 1; - -#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE) - RUSB2->SYSCFG_b.DPRPU = 1; /* necessary in this position */ -#endif + rusb->DCPMAXP_b.MXPS = 64; + + rusb->INTSTS0 = 0; + rusb->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk | + RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) | + RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk; + rusb->BEMPENB = 1; + rusb->BRDYENB = 1; - if (RUSB2->INTSTS0_b.VBSTS) { + if (rusb->INTSTS0_b.VBSTS) { dcd_connect(rhport); } } @@ -697,24 +731,24 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) void dcd_remote_wakeup(uint8_t rhport) { - (void)rhport; - RUSB2->DVSTCTR0_b.WKUP = 1; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + rusb->DVSTCTR0_b.WKUP = 1; } void dcd_connect(uint8_t rhport) { - (void)rhport; - #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) - RUSB2->SYSCFG_b.CNEN = 1; - R_BSP_SoftwareDelay((uint32_t) 10, BSP_DELAY_UNITS_MILLISECONDS); - #endif - RUSB2->SYSCFG_b.DPRPU = 1; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + + if ( is_highspeed(rhport)) { + rusb->SYSCFG_b.CNEN = 1; + } + rusb->SYSCFG_b.DPRPU = 1; } void dcd_disconnect(uint8_t rhport) { - (void)rhport; - RUSB2->SYSCFG_b.DPRPU = 0; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + rusb->SYSCFG_b.DPRPU = 0; } void dcd_sof_enable(uint8_t rhport, bool en) @@ -861,76 +895,94 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) //--------------------------------------------------------------------+ void dcd_int_handler(uint8_t rhport) { - (void)rhport; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + + uint16_t is0 = rusb->INTSTS0; - unsigned is0 = RUSB2->INTSTS0; /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ - RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_CTRT_Msk | RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_SOFR_Msk | - RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_VBINT_Msk) & is0) | RUSB2_INTSTS0_VALID_Msk; - if (is0 & RUSB2_INTSTS0_VBINT_Msk) { - if (RUSB2->INTSTS0_b.VBSTS) { + rusb->INTSTS0 = ~((RUSB2_INTSTS0_CTRT_Msk | RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_SOFR_Msk | + RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_VBINT_Msk) & is0) | RUSB2_INTSTS0_VALID_Msk; + + // VBUS changes + if ( is0 & RUSB2_INTSTS0_VBINT_Msk ) { + if ( rusb->INTSTS0_b.VBSTS ) { dcd_connect(rhport); } else { dcd_disconnect(rhport); } } - if (is0 & RUSB2_INTSTS0_RESM_Msk) { + + // Resumed + if ( is0 & RUSB2_INTSTS0_RESM_Msk ) { dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); -#if (0==USE_SOF) - RUSB2->INTENB0_b.SOFE = 0; +#if (0 == USE_SOF) + rusb->INTENB0_b.SOFE = 0; #endif } - if ((is0 & RUSB2_INTSTS0_SOFR_Msk) && RUSB2->INTENB0_b.SOFE) { + + // SOF received + if ( (is0 & RUSB2_INTSTS0_SOFR_Msk) && rusb->INTENB0_b.SOFE ) { // USBD will exit suspended mode when SOF event is received dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); #if (0 == USE_SOF) - RUSB2->INTENB0_b.SOFE = 0; + rusb->INTENB0_b.SOFE = 0; #endif } - if (is0 & RUSB2_INTSTS0_DVST_Msk) { + + // Device state changes + if ( is0 & RUSB2_INTSTS0_DVST_Msk ) { switch (is0 & RUSB2_INTSTS0_DVSQ_Msk) { - case RUSB2_INTSTS0_DVSQ_STATE_DEF: - process_bus_reset(rhport); - break; - case RUSB2_INTSTS0_DVSQ_STATE_ADDR: - process_set_address(rhport); - break; - case RUSB2_INTSTS0_DVSQ_STATE_SUSP0: - case RUSB2_INTSTS0_DVSQ_STATE_SUSP1: - case RUSB2_INTSTS0_DVSQ_STATE_SUSP2: - case RUSB2_INTSTS0_DVSQ_STATE_SUSP3: - dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); -#if (0==USE_SOF) - RUSB2->INTENB0_b.SOFE = 1; + case RUSB2_INTSTS0_DVSQ_STATE_DEF: + process_bus_reset(rhport); + break; + + case RUSB2_INTSTS0_DVSQ_STATE_ADDR: + process_set_address(rhport); + break; + + case RUSB2_INTSTS0_DVSQ_STATE_SUSP0: + case RUSB2_INTSTS0_DVSQ_STATE_SUSP1: + case RUSB2_INTSTS0_DVSQ_STATE_SUSP2: + case RUSB2_INTSTS0_DVSQ_STATE_SUSP3: + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); +#if (0 == USE_SOF) + rusb->INTENB0_b.SOFE = 1; #endif - default: - break; + + default: break; } } - if (is0 & RUSB2_INTSTS0_NRDY_Msk) { - RUSB2->NRDYSTS = 0; + + if ( is0 & RUSB2_INTSTS0_NRDY_Msk ) { + rusb->NRDYSTS = 0; } - if (is0 & RUSB2_INTSTS0_CTRT_Msk) { - if (is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA) { + + // Control transfer stage changes + if ( is0 & RUSB2_INTSTS0_CTRT_Msk ) { + if ( is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA ) { /* A setup packet has been received. */ process_setup_packet(rhport); - } else if (0 == (is0 & RUSB2_INTSTS0_CTSQ_Msk)) { + } else if ( 0 == (is0 & RUSB2_INTSTS0_CTSQ_Msk) ) { /* A ZLP has been sent/received. */ process_status_completion(rhport); } } - if (is0 & RUSB2_INTSTS0_BEMP_Msk) { - const unsigned s = RUSB2->BEMPSTS; - RUSB2->BEMPSTS = 0; - if (s & 1) { + + // Buffer empty + if ( is0 & RUSB2_INTSTS0_BEMP_Msk ) { + const unsigned s = rusb->BEMPSTS; + rusb->BEMPSTS = 0; + if ( s & 1 ) { process_pipe0_bemp(rhport); } } - if (is0 & RUSB2_INTSTS0_BRDY_Msk) { - const unsigned m = RUSB2->BRDYENB; - unsigned s = RUSB2->BRDYSTS & m; + + // Buffer ready + if ( is0 & RUSB2_INTSTS0_BRDY_Msk ) { + const unsigned m = rusb->BRDYENB; + unsigned s = rusb->BRDYSTS & m; /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ - RUSB2->BRDYSTS = ~s; + rusb->BRDYSTS = ~s; while (s) { #if defined(__CCRX__) static const int Mod37BitPosition[] = { diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index ca7c38907..0dc59331a 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -76,38 +76,34 @@ static rusb2_controller_t rusb2_controller[] = { #endif }; -TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) -{ - #if RUSB2_CONTROLLER_COUNT > 1 +#define RUSB2_REG(_p) ((rusb2_reg_t*) rusb2_controller[_p].reg_base) + +TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) { + uint32_t const mask = 1U << (11+rhport); + if (start) { + R_MSTP->MSTPCRB &= ~mask; + }else { + R_MSTP->MSTPCRB |= mask; + } +} + +TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) { NVIC_EnableIRQ(rusb2_controller[rhport].irqnum); - #else - (void) rhport; - NVIC_EnableIRQ(rusb2_controller[0].irqnum); - #endif } -TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) -{ - #if RUSB2_CONTROLLER_COUNT > 1 +TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) { NVIC_DisableIRQ(rusb2_controller[rhport].irqnum); - #else - (void) rhport; - NVIC_DisableIRQ(rusb2_controller[0].irqnum); - #endif } // MCU specific PHY init -TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) -{ +TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) { } +//--------------------------------------------------------------------+ +// Application API for setting IRQ number +//--------------------------------------------------------------------+ void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) { - #if RUSB2_CONTROLLER_COUNT > 1 rusb2_controller[rhport].irqnum = irqnum; - #else - (void) rhport; - rusb2_controller[0].irqnum = irqnum; - #endif } #ifdef __cplusplus diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h index 397c0d56c..d7f4e0b42 100644 --- a/src/portable/renesas/rusb2/rusb2_rx.h +++ b/src/portable/renesas/rusb2/rusb2_rx.h @@ -37,6 +37,12 @@ extern "C" { #define RUSB2_REG_BASE (0x000A0000) +// Start/Stop MSTP TODO implement later +TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) { + (void) rhport; + (void) start; +} + TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) { (void) rhport; diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index 0928f5aeb..b704626f6 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -1653,6 +1653,7 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_DVSTCTR0_RHST_LS (1U << RUSB2_DVSTCTR0_RHST_Pos) /* Low-speed connection */ #define RUSB2_DVSTCTR0_RHST_FS (2U << RUSB2_DVSTCTR0_RHST_Pos) /* Full-speed connection */ +#define RUSB2_DVSTCTR0_RHST_HS (3U << RUSB2_DVSTCTR0_RHST_Pos) /* Full-speed connection */ #define RUSB2_DEVADD_USBSPD_LS (1U << RUSB2_DEVADD_USBSPD_Pos) /* Target Device Low-speed */ #define RUSB2_DEVADD_USBSPD_FS (2U << RUSB2_DEVADD_USBSPD_Pos) /* Target Device Full-speed */ -- cgit v1.3.1 From 1eefc2b3ef2e268e839002a8b5221eebe26f6cd3 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 6 Jul 2023 19:35:42 +0700 Subject: more multiple ports update --- src/portable/renesas/rusb2/dcd_rusb2.c | 344 ++++++++++++++++++-------------- src/portable/renesas/rusb2/rusb2_rx.h | 2 + src/portable/renesas/rusb2/rusb2_type.h | 9 +- 3 files changed, 208 insertions(+), 147 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 27d525b68..833737181 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -63,22 +63,11 @@ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -/* LINK core registers */ -#if defined(__CCRX__) - #define RUSB2 ((rusb2_reg_t __evenaccess*) RUSB2_REG_BASE) -#elif defined(__RX__) - #define RUSB2 ((rusb2_reg_t*) RUSB2_REG_BASE) -#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) - #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE) -#else - #define RUSB2 ((R_USB_FS0_Type*)R_USB_FS0_BASE) -#endif - /* Start of definition of packed structs (used by the CCRX toolchain) */ TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN -typedef struct TU_ATTR_PACKED { +typedef struct TU_ATTR_PACKED _ccrx_evenaccess { union { struct { uint16_t : 8; @@ -186,52 +175,53 @@ static unsigned find_pipe(unsigned xfer) return 0; } -static volatile uint16_t* get_pipectr(unsigned num) +static volatile uint16_t* get_pipectr(rusb2_reg_t *rusb, unsigned num) { if (num) { - return (volatile uint16_t*)&(RUSB2->PIPE_CTR[num - 1]); + return (volatile uint16_t*)&(rusb->PIPE_CTR[num - 1]); } else { - return (volatile uint16_t*)&(RUSB2->DCPCTR); + return (volatile uint16_t*)&(rusb->DCPCTR); } } -static volatile reg_pipetre_t* get_pipetre(unsigned num) +static volatile reg_pipetre_t* get_pipetre(rusb2_reg_t *rusb, unsigned num) { volatile reg_pipetre_t* tre = NULL; if ((1 <= num) && (num <= 5)) { - tre = (volatile reg_pipetre_t*)&(RUSB2->PIPE_TR[num - 1].E); + tre = (volatile reg_pipetre_t*)&(rusb->PIPE_TR[num - 1].E); } return tre; } static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr) { - (void)rhport; + rusb2_reg_t *rusb = RUSB2_REG(rhport); const unsigned epn = tu_edpt_number(ep_addr); + if (epn) { const unsigned dir = tu_edpt_dir(ep_addr); const unsigned num = _dcd.ep[dir][epn]; - return get_pipectr(num); + return get_pipectr(rusb, num); } else { - return get_pipectr(0); + return get_pipectr(rusb, 0); } } -static unsigned edpt0_max_packet_size(void) +static uint16_t edpt0_max_packet_size(rusb2_reg_t* rusb) { - return RUSB2->DCPMAXP_b.MXPS; + return rusb->DCPMAXP_b.MXPS; } -static unsigned edpt_max_packet_size(unsigned num) +static uint16_t edpt_max_packet_size(rusb2_reg_t *rusb, unsigned num) { - RUSB2->PIPESEL = num; - return RUSB2->PIPEMAXP; + rusb->PIPESEL = num; + return rusb->PIPEMAXP; } -static inline void pipe_wait_for_ready(unsigned num) +static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num) { - while (RUSB2->D0FIFOSEL_b.CURPIPE != num) ; - while (!RUSB2->D0FIFOCTR_b.FRDY) ; + while ( rusb->D0FIFOSEL_b.CURPIPE != num ) {} + while ( !rusb->D0FIFOCTR_b.FRDY ) {} } static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) @@ -284,61 +274,70 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne ops[dir].tu_fifo_advance(f, total_len - rem); } -static bool pipe0_xfer_in(void) +static bool pipe0_xfer_in(rusb2_reg_t* rusb) { pipe_state_t *pipe = &_dcd.pipe[0]; const unsigned rem = pipe->remaining; + if (!rem) { pipe->buf = NULL; return true; } - const unsigned mps = edpt0_max_packet_size(); - const unsigned len = TU_MIN(mps, rem); + + const uint16_t mps = edpt0_max_packet_size(rusb); + const uint16_t len = tu_min16(mps, rem); void *buf = pipe->buf; + if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->CFIFO, len, TUSB_DIR_IN); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_IN); } else { - pipe_write_packet(buf, (volatile void*)&RUSB2->CFIFO, len); + pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } } + if (len < mps) { - RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; } + pipe->remaining = rem - len; return false; } -static bool pipe0_xfer_out(void) +static bool pipe0_xfer_out(rusb2_reg_t* rusb) { pipe_state_t *pipe = &_dcd.pipe[0]; const unsigned rem = pipe->remaining; - const unsigned mps = edpt0_max_packet_size(); - const unsigned vld = RUSB2->CFIFOCTR_b.DTLN; - const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + const uint16_t mps = edpt0_max_packet_size(rusb); + const uint16_t vld = rusb->CFIFOCTR_b.DTLN; + const uint16_t len = tu_min16(tu_min16(rem, mps), vld); void *buf = pipe->buf; + if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->CFIFO, len, TUSB_DIR_OUT); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_OUT); } else { - pipe_read_packet(buf, (volatile void*)&RUSB2->CFIFO, len); + pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } } + if (len < mps) { - RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; + rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; } + pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; return true; } + return false; } -static bool pipe_xfer_in(unsigned num) +static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num) { pipe_state_t *pipe = &_dcd.pipe[num]; const unsigned rem = pipe->remaining; @@ -348,119 +347,141 @@ static bool pipe_xfer_in(unsigned num) return true; } - RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); - const unsigned len = TU_MIN(rem, mps); + rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); + const uint16_t mps = edpt_max_packet_size(rusb, num); + pipe_wait_for_ready(rusb, num); + const uint16_t len = tu_min16(rem, mps); void *buf = pipe->buf; + if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->D0FIFO, len, TUSB_DIR_IN); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_IN); } else { - pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len); + pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } } + if (len < mps) { - RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; } - RUSB2->D0FIFOSEL = 0; - while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + + rusb->D0FIFOSEL = 0; + while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + pipe->remaining = rem - len; + return false; } -static bool pipe_xfer_out(unsigned num) +static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num) { pipe_state_t *pipe = &_dcd.pipe[num]; - const unsigned rem = pipe->remaining; + const uint16_t rem = pipe->remaining; - RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT; - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); - const unsigned vld = RUSB2->D0FIFOCTR_b.DTLN; - const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT; + const uint16_t mps = edpt_max_packet_size(rusb, num); + pipe_wait_for_ready(rusb, num); + + const uint16_t vld = rusb->D0FIFOCTR_b.DTLN; + const uint16_t len = tu_min16(tu_min16(rem, mps), vld); void *buf = pipe->buf; + if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->D0FIFO, len, TUSB_DIR_OUT); + pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_OUT); } else { - pipe_read_packet(buf, (volatile void*)&RUSB2->D0FIFO, len); + pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } } + if (len < mps) { - RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; + rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; } - RUSB2->D0FIFOSEL = 0; - while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + + rusb->D0FIFOSEL = 0; + while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; return NULL != buf; } + return false; } static void process_setup_packet(uint8_t rhport) { - uint16_t setup_packet[4]; - if (0 == (RUSB2->INTSTS0 & RUSB2_INTSTS0_VALID_Msk)) return; - RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; - setup_packet[0] = tu_le16toh(RUSB2->USBREQ); - setup_packet[1] = RUSB2->USBVAL; - setup_packet[2] = RUSB2->USBINDX; - setup_packet[3] = RUSB2->USBLENG; - RUSB2->INTSTS0 = ~((uint16_t)RUSB2_INTSTS0_VALID_Msk); + rusb2_reg_t* rusb = RUSB2_REG(rhport); + if (0 == (rusb->INTSTS0 & RUSB2_INTSTS0_VALID_Msk)) return; + + rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; + uint16_t setup_packet[4] = { + tu_htole16(rusb->USBREQ), + tu_htole16(rusb->USBVAL), + tu_htole16(rusb->USBINDX), + tu_htole16(rusb->USBLENG) + }; + + rusb->INTSTS0 = ~((uint16_t) RUSB2_INTSTS0_VALID_Msk); dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true); } static void process_status_completion(uint8_t rhport) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); uint8_t ep_addr; /* Check the data stage direction */ - if (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) { + if (rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) { /* IN transfer. */ ep_addr = tu_edpt_addr(0, TUSB_DIR_IN); } else { /* OUT transfer. */ ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT); } + dcd_event_xfer_complete(rhport, ep_addr, 0, XFER_RESULT_SUCCESS, true); } -static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) +static bool process_pipe0_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) { /* configure fifo direction and access unit settings */ - if (ep_addr) { /* IN, 2 bytes */ - RUSB2->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT | - (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); - while (!(RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ; - } else { /* OUT, a byte */ - RUSB2->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT; - while (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ; + if ( ep_addr ) { + /* IN, 2 bytes */ + rusb->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT | + (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); + while ( !(rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ) {} + } else { + /* OUT, a byte */ + rusb->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT; + while ( rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE ) {} } pipe_state_t *pipe = &_dcd.pipe[0]; pipe->ff = buffer_type; pipe->length = total_bytes; pipe->remaining = total_bytes; - if (total_bytes) { - pipe->buf = buffer; - if (ep_addr) { /* IN */ - TU_ASSERT(RUSB2->DCPCTR_b.BSTS && (RUSB2->USBREQ & 0x80)); - pipe0_xfer_in(); + + if ( total_bytes ) { + pipe->buf = buffer; + if ( ep_addr ) { + /* IN */ + TU_ASSERT(rusb->DCPCTR_b.BSTS && (rusb->USBREQ & 0x80)); + pipe0_xfer_in(rusb); } - RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF; + rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF; } else { /* ZLP */ - pipe->buf = NULL; - RUSB2->DCPCTR = RUSB2_DCPCTR_CCPL_Msk | RUSB2_PIPE_CTR_PID_BUF; + pipe->buf = NULL; + rusb->DCPCTR = RUSB2_DCPCTR_CCPL_Msk | RUSB2_PIPE_CTR_PID_BUF; } + return true; } -static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) +static bool process_pipe_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) { const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir = tu_edpt_dir(ep_addr); @@ -473,49 +494,55 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui pipe->buf = buffer; pipe->length = total_bytes; pipe->remaining = total_bytes; - if (dir) { /* IN */ + + if (dir) { + /* IN */ if (total_bytes) { - pipe_xfer_in(num); - } else { /* ZLP */ - RUSB2->D0FIFOSEL = num; - pipe_wait_for_ready(num); - RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; - RUSB2->D0FIFOSEL = 0; - while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + pipe_xfer_in(rusb, num); + } else { + /* ZLP */ + rusb->D0FIFOSEL = num; + pipe_wait_for_ready(rusb, num); + rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->D0FIFOSEL = 0; + /* if CURPIPE bits changes, check written value */ + while (rusb->D0FIFOSEL_b.CURPIPE) {} } } else { -#if defined(__CCRX__) - __evenaccess volatile reg_pipetre_t *pt = get_pipetre(num); -#else - volatile reg_pipetre_t *pt = get_pipetre(num); -#endif + // OUT + volatile reg_pipetre_t *pt = get_pipetre(rusb, num); + if (pt) { - const unsigned mps = edpt_max_packet_size(num); - volatile uint16_t *ctr = get_pipectr(num); + const uint16_t mps = edpt_max_packet_size(rusb, num); + volatile uint16_t *ctr = get_pipectr(rusb, num); + if (*ctr & 0x3) *ctr = RUSB2_PIPE_CTR_PID_NAK; + pt->TRE = TU_BIT(8); pt->TRN = (total_bytes + mps - 1) / mps; pt->TRENB = 1; *ctr = RUSB2_PIPE_CTR_PID_BUF; } } - // TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type); + + // TU_LOG2("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type); return true; } -static bool process_edpt_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) +static bool process_edpt_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes) { const unsigned epn = tu_edpt_number(ep_addr); if (0 == epn) { - return process_pipe0_xfer(buffer_type, ep_addr, buffer, total_bytes); + return process_pipe0_xfer(rusb, buffer_type, ep_addr, buffer, total_bytes); } else { - return process_pipe_xfer(buffer_type, ep_addr, buffer, total_bytes); + return process_pipe_xfer(rusb, buffer_type, ep_addr, buffer, total_bytes); } } static void process_pipe0_bemp(uint8_t rhport) { - bool completed = pipe0_xfer_in(); + rusb2_reg_t* rusb = RUSB2_REG(rhport); + bool completed = pipe0_xfer_in(rusb); if (completed) { pipe_state_t *pipe = &_dcd.pipe[0]; dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN), @@ -525,17 +552,20 @@ static void process_pipe0_bemp(uint8_t rhport) static void process_pipe_brdy(uint8_t rhport, unsigned num) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); pipe_state_t *pipe = &_dcd.pipe[num]; const unsigned dir = tu_edpt_dir(pipe->ep); bool completed; - if (dir) { /* IN */ - completed = pipe_xfer_in(num); + if (dir) { + /* IN */ + completed = pipe_xfer_in(rusb, num); } else { + // OUT if (num) { - completed = pipe_xfer_out(num); + completed = pipe_xfer_out(rusb, num); } else { - completed = pipe0_xfer_out(); + completed = pipe0_xfer_out(rusb); } } if (completed) { @@ -606,8 +636,10 @@ static void process_bus_reset(uint8_t rhport) static void process_set_address(uint8_t rhport) { - const uint32_t addr = RUSB2->USBADDR & 0xFF; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + const uint32_t addr = rusb->USBADDR & 0xFF; if (!addr) return; + const tusb_control_request_t setup_packet = { #if defined(__CCRX__) .bmRequestType = { 0 }, /* Note: CCRX needs the braces over this struct member */ @@ -618,8 +650,9 @@ static void process_set_address(uint8_t rhport) .wValue = addr, .wIndex = 0, .wLength = 0, - }; - dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet, true); + }; + + dcd_event_setup_received(rhport, (const uint8_t *) &setup_packet, true); } /*------------------------------------------------------------------*/ @@ -704,7 +737,7 @@ void dcd_init(uint8_t rhport) rusb->INTSTS0 = 0; rusb->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk | RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) | - RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk; + RUSB2_INTSTS0_RESM_Msk; rusb->BEMPENB = 1; rusb->BRDYENB = 1; @@ -766,33 +799,43 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { (void)rhport; + rusb2_reg_t * rusb = RUSB2_REG(rhport); const unsigned ep_addr = ep_desc->bEndpointAddress; const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir = tu_edpt_dir(ep_addr); const unsigned xfer = ep_desc->bmAttributes.xfer; const unsigned mps = tu_edpt_packet_size(ep_desc); - if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) { - /* USBa supports up to 256 bytes */ - return false; + + if (xfer == TUSB_XFER_ISOCHRONOUS) { + // Fullspeed ISO is limit to 256 bytes + if ( !is_highspeed(rhport) && mps > 256) { + return false; + } } const unsigned num = find_pipe(xfer); - if (!num) return false; + TU_ASSERT(num); + _dcd.pipe[num].ep = ep_addr; _dcd.ep[dir][epn] = num; /* setup pipe */ dcd_int_disable(rhport); - #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) - RUSB2->PIPEBUF = 0x7C08; - #endif - RUSB2->PIPESEL = num; - RUSB2->PIPEMAXP = mps; - volatile uint16_t *ctr = get_pipectr(num); + + if ( is_highspeed(rhport) ) { + // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed + // depending on the allocation scheme + rusb->PIPEBUF = 0x7C08; + } + + rusb->PIPESEL = num; + rusb->PIPEMAXP = mps; + volatile uint16_t *ctr = get_pipectr(rusb, num); *ctr = RUSB2_PIPE_CTR_ACLRM_Msk | RUSB2_PIPE_CTR_SQCLR_Msk; *ctr = 0; unsigned cfg = (dir << 4) | epn; + if (xfer == TUSB_XFER_BULK) { cfg |= (RUSB2_PIPECFG_TYPE_BULK | RUSB2_PIPECFG_SHTNAK_Msk | RUSB2_PIPECFG_DBLB_Msk); } else if (xfer == TUSB_XFER_INTERRUPT) { @@ -800,13 +843,16 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) } else { cfg |= (RUSB2_PIPECFG_TYPE_ISO | RUSB2_PIPECFG_DBLB_Msk); } - RUSB2->PIPECFG = cfg; - RUSB2->BRDYSTS = 0x1FFu ^ TU_BIT(num); - RUSB2->BRDYENB |= TU_BIT(num); + + rusb->PIPECFG = cfg; + rusb->BRDYSTS = 0x1FFu ^ TU_BIT(num); + rusb->BRDYENB |= TU_BIT(num); + if (dir || (xfer != TUSB_XFER_BULK)) { *ctr = RUSB2_PIPE_CTR_PID_BUF; } - // TU_LOG1("O %d %x %x\r\n", RUSB2->PIPESEL, RUSB2->PIPECFG, RUSB2->PIPEMAXP); + + // TU_LOG1("O %d %x %x\r\n", rusb->PIPESEL, rusb->PIPECFG, rusb->PIPEMAXP); dcd_int_enable(rhport); return true; @@ -826,26 +872,28 @@ void dcd_edpt_close_all(uint8_t rhport) void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; + rusb2_reg_t * rusb = RUSB2_REG(rhport); const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir = tu_edpt_dir(ep_addr); const unsigned num = _dcd.ep[dir][epn]; - RUSB2->BRDYENB &= ~TU_BIT(num); - volatile uint16_t *ctr = get_pipectr(num); + rusb->BRDYENB &= ~TU_BIT(num); + volatile uint16_t *ctr = get_pipectr(rusb, num); *ctr = 0; - RUSB2->PIPESEL = num; - RUSB2->PIPECFG = 0; + rusb->PIPESEL = num; + rusb->PIPECFG = 0; _dcd.pipe[num].ep = 0; _dcd.ep[dir][epn] = 0; } bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { - bool r; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + dcd_int_disable(rhport); - r = process_edpt_xfer(0, ep_addr, buffer, total_bytes); + bool r = process_edpt_xfer(rusb, 0, ep_addr, buffer, total_bytes); dcd_int_enable(rhport); + return r; } @@ -853,10 +901,12 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_ { // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1 TU_ASSERT(ff->item_size == 1); - bool r; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + dcd_int_disable(rhport); - r = process_edpt_xfer(1, ep_addr, ff, total_bytes); + bool r = process_edpt_xfer(rusb, 1, ep_addr, ff, total_bytes); dcd_int_enable(rhport); + return r; } @@ -873,8 +923,10 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { + rusb2_reg_t * rusb = RUSB2_REG(rhport); volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr); if (!ctr) return; + dcd_int_disable(rhport); *ctr = RUSB2_PIPE_CTR_SQCLR_Msk; @@ -882,8 +934,8 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) *ctr = RUSB2_PIPE_CTR_PID_BUF; } else { const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)]; - RUSB2->PIPESEL = num; - if (RUSB2->PIPECFG_b.TYPE != 1) { + rusb->PIPESEL = num; + if (rusb->PIPECFG_b.TYPE != 1) { *ctr = RUSB2_PIPE_CTR_PID_BUF; } } @@ -953,9 +1005,9 @@ void dcd_int_handler(uint8_t rhport) } } - if ( is0 & RUSB2_INTSTS0_NRDY_Msk ) { - rusb->NRDYSTS = 0; - } +// if ( is0 & RUSB2_INTSTS0_NRDY_Msk ) { +// rusb->NRDYSTS = 0; +// } // Control transfer stage changes if ( is0 & RUSB2_INTSTS0_CTRT_Msk ) { @@ -970,7 +1022,7 @@ void dcd_int_handler(uint8_t rhport) // Buffer empty if ( is0 & RUSB2_INTSTS0_BEMP_Msk ) { - const unsigned s = rusb->BEMPSTS; + const uint16_t s = rusb->BEMPSTS; rusb->BEMPSTS = 0; if ( s & 1 ) { process_pipe0_bemp(rhport); diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h index d7f4e0b42..21b2527c3 100644 --- a/src/portable/renesas/rusb2/rusb2_rx.h +++ b/src/portable/renesas/rusb2/rusb2_rx.h @@ -37,6 +37,8 @@ extern "C" { #define RUSB2_REG_BASE (0x000A0000) +#define RUSB2_REG(_p) ((rusb2_reg_t *) RUSB2_REG_BASE) + // Start/Stop MSTP TODO implement later TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) { (void) rhport; diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index b704626f6..7a5e37089 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -33,6 +33,13 @@ extern "C" { #endif +// CCRX specific attribute to generate a Code that Accesses Variables in the Declared Size +#ifdef __CCRX__ + #define _ccrx_evenaccess __evenaccess +#else + #define _ccrx_evenaccess +#endif + /*--------------------------------------------------------------------*/ /* Register Definitions */ /*--------------------------------------------------------------------*/ @@ -64,7 +71,7 @@ typedef struct { /* RUSB2 Registers Structure */ -typedef struct { +typedef struct _ccrx_evenaccess { union { volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */ -- cgit v1.3.1 From c53acb145589e2733b7d1abe012e85ae590bffb7 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 6 Jul 2023 20:10:58 +0700 Subject: fix build with rx --- src/portable/renesas/rusb2/dcd_rusb2.c | 37 +++++++++++++++++++--------------- src/portable/renesas/rusb2/rusb2_ra.h | 4 ++-- src/portable/renesas/rusb2/rusb2_rx.h | 5 ++++- 3 files changed, 27 insertions(+), 19 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 833737181..81b60b3bc 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -36,12 +36,6 @@ #include "device/dcd.h" #include "rusb2_type.h" -#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) -// fallback -#define CFG_TUSB_RHPORT0_MODE OPT_MODE_DEVICE -#define CFG_TUSB_RHPORT1_MODE 0 -#endif - #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #include "rusb2_rx.h" #elif TU_CHECK_MCU(OPT_MCU_RAXXX) @@ -86,7 +80,7 @@ typedef union TU_ATTR_PACKED { volatile uint8_t reserved8; }; volatile uint16_t u16; -} hw_fifo_t; +} hw_fifo16_t; typedef union TU_ATTR_PACKED { struct { @@ -140,9 +134,11 @@ static dcd_data_t _dcd; // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -TU_ATTR_ALWAYS_INLINE static inline bool is_highspeed(uint8_t rhport) { - return rhport == 1; -} +#ifdef RUSB2_SUPPORT_HIGHSPEED + #define is_highspeed_usbip(_p) (_p == 1) +#else + #define is_highspeed_usbip(_p) (false) +#endif static unsigned find_pipe(unsigned xfer) { @@ -229,14 +225,17 @@ static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) volatile hw_fifo32_t *reg = (volatile hw_fifo32_t*) fifo; #else - volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo; + volatile hw_fifo16_t *reg = (volatile hw_fifo16_t*) fifo; #endif + uintptr_t addr = (uintptr_t)buf; + while (len >= 2) { reg->u16 = *(const uint16_t *)addr; addr += 2; len -= 2; } + if (len > 0) { reg->u8 = *(const uint8_t *)addr; ++addr; @@ -260,11 +259,14 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet}, /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, }; + tu_fifo_buffer_info_t info; ops[dir].tu_fifo_get_info(f, &info); + unsigned total_len = len; len = TU_MIN(total_len, info.len_lin); ops[dir].pipe_read_write(info.ptr_lin, fifo, len); + unsigned rem = total_len - len; if (rem) { len = TU_MIN(rem, info.len_wrap); @@ -689,7 +691,8 @@ void dcd_init(uint8_t rhport) rusb2_module_start(rhport, true); - if ( is_highspeed(rhport) ) { +#ifdef RUSB2_SUPPORT_HIGHSPEED + if ( is_highspeed_usbip(rhport) ) { rusb->SYSCFG_b.HSE = 1; // leave CLKSEL as default (0x11) 24Mhz @@ -715,7 +718,9 @@ void dcd_init(uint8_t rhport) rusb->CFIFOSEL_b.MBW = 1; rusb->D0FIFOSEL_b.MBW = 1; rusb->D1FIFOSEL_b.MBW = 1; - } else { + } else +#endif + { rusb->SYSCFG_b.SCKE = 1; while (!rusb->SYSCFG_b.SCKE) {} rusb->SYSCFG_b.DRPD = 0; @@ -772,7 +777,7 @@ void dcd_connect(uint8_t rhport) { rusb2_reg_t* rusb = RUSB2_REG(rhport); - if ( is_highspeed(rhport)) { + if ( is_highspeed_usbip(rhport)) { rusb->SYSCFG_b.CNEN = 1; } rusb->SYSCFG_b.DPRPU = 1; @@ -809,7 +814,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) if (xfer == TUSB_XFER_ISOCHRONOUS) { // Fullspeed ISO is limit to 256 bytes - if ( !is_highspeed(rhport) && mps > 256) { + if ( !is_highspeed_usbip(rhport) && mps > 256) { return false; } } @@ -823,7 +828,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) /* setup pipe */ dcd_int_disable(rhport); - if ( is_highspeed(rhport) ) { + if ( is_highspeed_usbip(rhport) ) { // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed // depending on the allocation scheme rusb->PIPEBUF = 0x7C08; diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 0dc59331a..e04a99685 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -62,7 +62,7 @@ typedef struct { }rusb2_controller_t; #if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8) - #define RUSB2_HAS_HIGHSPEED + #define RUSB2_SUPPORT_HIGHSPEED #define RUSB2_CONTROLLER_COUNT 2 #else #define RUSB2_CONTROLLER_COUNT 1 @@ -71,7 +71,7 @@ typedef struct { // USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP static rusb2_controller_t rusb2_controller[] = { { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn }, - #ifdef RUSB2_HAS_HIGHSPEED + #ifdef RUSB2_SUPPORT_HIGHSPEED { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn }, #endif }; diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h index 21b2527c3..17b9a918c 100644 --- a/src/portable/renesas/rusb2/rusb2_rx.h +++ b/src/portable/renesas/rusb2/rusb2_rx.h @@ -37,7 +37,10 @@ extern "C" { #define RUSB2_REG_BASE (0x000A0000) -#define RUSB2_REG(_p) ((rusb2_reg_t *) RUSB2_REG_BASE) +TU_ATTR_ALWAYS_INLINE static inline rusb2_reg_t* RUSB2_REG(uint8_t rhport) { + (void) rhport; + return (rusb2_reg_t *) RUSB2_REG_BASE; +} // Start/Stop MSTP TODO implement later TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) { -- cgit v1.3.1 From 4c156100fafa682407f1a9a459d8b8800a029446 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 7 Jul 2023 12:27:18 +0700 Subject: use unaligned access read for hw fifo --- src/common/tusb_common.h | 18 ++++++-- src/common/tusb_mcu.h | 12 ++++-- src/portable/renesas/rusb2/dcd_rusb2.c | 77 +++++++++++++++++++++------------- 3 files changed, 71 insertions(+), 36 deletions(-) (limited to 'src') diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 957491aa9..576cb123f 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -260,11 +260,21 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void* mem, uint16_ #else // MCU that could access unaligned memory natively -TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32 (const void* mem) { return *((uint32_t const *) mem); } -TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16 (const void* mem) { return *((uint16_t const *) mem); } +TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32(const void *mem) { + return *((uint32_t const *) mem); +} + +TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16(const void *mem) { + return *((uint16_t const *) mem); +} -TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32 (void* mem, uint32_t value ) { *((uint32_t*) mem) = value; } -TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16 (void* mem, uint16_t value ) { *((uint16_t*) mem) = value; } +TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32(void *mem, uint32_t value) { + *((uint32_t *) mem) = value; +} + +TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void *mem, uint16_t value) { + *((uint16_t *) mem) = value; +} #endif diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 496ebfc85..89f89182e 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -34,10 +34,16 @@ //------------- Unaligned Memory Access -------------// -// ARMv7+ (M3-M7, M23-M33) can access unaligned memory -#if (defined(__ARM_ARCH) && (__ARM_ARCH >= 7)) - #define TUP_ARCH_STRICT_ALIGN 0 +#ifdef __ARM_ARCH + // ARM Architecture set __ARM_FEATURE_UNALIGNED to 1 for mcu supports unaligned access + #if defined(__ARM_FEATURE_UNALIGNED) && __ARM_FEATURE_UNALIGNED == 1 + #define TUP_ARCH_STRICT_ALIGN 0 + #else + #define TUP_ARCH_STRICT_ALIGN 1 + #endif #else + // TODO default to strict align for others + // Should investigate other architecture such as risv, xtensa, mips for optimal setting #define TUP_ARCH_STRICT_ALIGN 1 #endif diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 81b60b3bc..464929224 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -220,6 +220,11 @@ static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num) while ( !rusb->D0FIFOCTR_b.FRDY ) {} } +//--------------------------------------------------------------------+ +// Pipe FIFO +//--------------------------------------------------------------------+ + +// Write data buffer --> hw fifo static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) @@ -228,54 +233,68 @@ static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) volatile hw_fifo16_t *reg = (volatile hw_fifo16_t*) fifo; #endif - uintptr_t addr = (uintptr_t)buf; + uint8_t const* buf8 = (uint8_t const*) buf; while (len >= 2) { - reg->u16 = *(const uint16_t *)addr; - addr += 2; + reg->u16 = tu_unaligned_read16(buf8); + buf8 += 2; len -= 2; } if (len > 0) { - reg->u8 = *(const uint8_t *)addr; - ++addr; + reg->u8 = *buf8; + ++buf8; } } +// Read data buffer <-- hw fifo static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) { - uint8_t *p = (uint8_t*)buf; + uint8_t *p = (uint8_t*)buf; volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ while (len--) *p++ = *reg; } -static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) -{ - static const struct { - void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info); - void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n); - void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len); - } ops[] = { - /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet}, - /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, - }; +// Write data sw fifo --> hw fifo +static void pipe_write_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) { + tu_fifo_buffer_info_t info; + tu_fifo_get_read_info(f, &info); + + uint16_t count = tu_min16(total_len, info.len_lin); + pipe_write_packet(info.ptr_lin, fifo, count); + + uint16_t rem = total_len - count; + if (rem) { + rem = tu_min16(rem, info.len_wrap); + pipe_write_packet(info.ptr_wrap, fifo, rem); + count += rem; + } + + tu_fifo_advance_read_pointer(f, count); +} +// Read data sw fifo <-- hw fifo +static void pipe_read_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) { tu_fifo_buffer_info_t info; - ops[dir].tu_fifo_get_info(f, &info); + tu_fifo_get_write_info(f, &info); - unsigned total_len = len; - len = TU_MIN(total_len, info.len_lin); - ops[dir].pipe_read_write(info.ptr_lin, fifo, len); + uint16_t count = tu_min16(total_len, info.len_lin); + pipe_read_packet(info.ptr_lin, fifo, count); - unsigned rem = total_len - len; + uint16_t rem = total_len - count; if (rem) { - len = TU_MIN(rem, info.len_wrap); - ops[dir].pipe_read_write(info.ptr_wrap, fifo, len); - rem -= len; + rem = tu_min16(rem, info.len_wrap); + pipe_read_packet(info.ptr_wrap, fifo, rem); + count += rem; } - ops[dir].tu_fifo_advance(f, total_len - rem); + + tu_fifo_advance_write_pointer(f, count); } +//--------------------------------------------------------------------+ +// Pipe Transfer +//--------------------------------------------------------------------+ + static bool pipe0_xfer_in(rusb2_reg_t* rusb) { pipe_state_t *pipe = &_dcd.pipe[0]; @@ -292,7 +311,7 @@ static bool pipe0_xfer_in(rusb2_reg_t* rusb) if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_IN); + pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len); } else { pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; @@ -319,7 +338,7 @@ static bool pipe0_xfer_out(rusb2_reg_t* rusb) if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_OUT); + pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len); } else { pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; @@ -357,7 +376,7 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num) if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_IN); + pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len); } else { pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; @@ -391,7 +410,7 @@ static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num) if (len) { if (pipe->ff) { - pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_OUT); + pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len); } else { pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; -- cgit v1.3.1 From e0f1ba8b0e9cf46fabcddc72a61d5515df424edf Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 7 Jul 2023 16:07:11 +0700 Subject: fully work with multiple ports without CFG_TUSB_RHPORT0/1 --- hw/bsp/family_support.cmake | 4 +- hw/bsp/ra/boards/ra6m5_ek/board.cmake | 7 --- src/portable/renesas/rusb2/dcd_rusb2.c | 85 ++++++++++++++------------------- src/portable/renesas/rusb2/rusb2_type.h | 1 + 4 files changed, 39 insertions(+), 58 deletions(-) (limited to 'src') diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 5b97eb5e4..d8298c8ad 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -227,8 +227,8 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS) if (DEFINED LOG) target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_DEBUG=${LOG}) - if (LOG STREQUAL "3") - # no inline for debug level 3 + if (LOG STREQUAL "4") + # no inline for debug level 4 target_compile_definitions(${TARGET}-tinyusb_config INTERFACE TU_ATTR_ALWAYS_INLINE=) endif () endif() diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake index d934a0c0d..5a615f9b0 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake +++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake @@ -14,11 +14,4 @@ function(update_board TARGET) # port 0 is fullspeed, port 1 is highspeed BOARD_TUD_MAX_SPEED=$ ) - - if (PORT STREQUAL 1) - target_compile_definitions(${TARGET} PUBLIC - CFG_TUSB_RHPORT1_MODE=OPT_MODE_DEVICE|OPT_MODE_HIGH_SPEED - CFG_TUSB_RHPORT0_MODE=0 - ) - endif () endfunction() diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 464929224..3d3e52bfa 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -74,26 +74,6 @@ typedef struct TU_ATTR_PACKED _ccrx_evenaccess { uint16_t TRN; } reg_pipetre_t; -typedef union TU_ATTR_PACKED { - struct { - volatile uint8_t u8; - volatile uint8_t reserved8; - }; - volatile uint16_t u16; -} hw_fifo16_t; - -typedef union TU_ATTR_PACKED { - struct { - volatile uint8_t reserved8[3]; - volatile uint8_t u8; - }; - struct { - volatile uint16_t reserved16; - volatile uint16_t u16; - }; - volatile uint32_t u32; -} hw_fifo32_t; - typedef struct TU_ATTR_PACKED { void *buf; /* the start address of a transfer data buffer */ @@ -135,9 +115,11 @@ static dcd_data_t _dcd; //--------------------------------------------------------------------+ #ifdef RUSB2_SUPPORT_HIGHSPEED - #define is_highspeed_usbip(_p) (_p == 1) + #define is_highspeed_usbip(_p) (_p == 1) + #define is_highspeed_regbase(_reg) (_reg == RUSB2_REG(1)) #else - #define is_highspeed_usbip(_p) (false) + #define is_highspeed_usbip(_p) (false) + #define is_highspeed_regbase(_reg) (false) #endif static unsigned find_pipe(unsigned xfer) @@ -225,48 +207,57 @@ static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num) //--------------------------------------------------------------------+ // Write data buffer --> hw fifo -static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) +static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len) { -#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) - volatile hw_fifo32_t *reg = (volatile hw_fifo32_t*) fifo; -#else - volatile hw_fifo16_t *reg = (volatile hw_fifo16_t*) fifo; -#endif + (void) rusb; + + volatile uint16_t *ff16; + volatile uint8_t *ff8; + + // Highspeed FIFO is 32-bit + if ( is_highspeed_regbase(rusb) ) { + ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2); + ff8 = (volatile uint8_t *) ((uintptr_t) fifo+3); + }else { + ff16 = (volatile uint16_t*) fifo; + ff8 = ((volatile uint8_t*) fifo); + } uint8_t const* buf8 = (uint8_t const*) buf; while (len >= 2) { - reg->u16 = tu_unaligned_read16(buf8); + *ff16 = tu_unaligned_read16(buf8); buf8 += 2; len -= 2; } if (len > 0) { - reg->u8 = *buf8; + *ff8 = *buf8; ++buf8; } } // Read data buffer <-- hw fifo -static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) +static void pipe_read_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len) { + (void) rusb; uint8_t *p = (uint8_t*)buf; volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ while (len--) *p++ = *reg; } // Write data sw fifo --> hw fifo -static void pipe_write_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) { +static void pipe_write_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void *fifo, uint16_t total_len) { tu_fifo_buffer_info_t info; tu_fifo_get_read_info(f, &info); uint16_t count = tu_min16(total_len, info.len_lin); - pipe_write_packet(info.ptr_lin, fifo, count); + pipe_write_packet(rusb, info.ptr_lin, fifo, count); uint16_t rem = total_len - count; if (rem) { rem = tu_min16(rem, info.len_wrap); - pipe_write_packet(info.ptr_wrap, fifo, rem); + pipe_write_packet(rusb, info.ptr_wrap, fifo, rem); count += rem; } @@ -274,17 +265,17 @@ static void pipe_write_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t tot } // Read data sw fifo <-- hw fifo -static void pipe_read_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) { +static void pipe_read_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void *fifo, uint16_t total_len) { tu_fifo_buffer_info_t info; tu_fifo_get_write_info(f, &info); uint16_t count = tu_min16(total_len, info.len_lin); - pipe_read_packet(info.ptr_lin, fifo, count); + pipe_read_packet(rusb, info.ptr_lin, fifo, count); uint16_t rem = total_len - count; if (rem) { rem = tu_min16(rem, info.len_wrap); - pipe_read_packet(info.ptr_wrap, fifo, rem); + pipe_read_packet(rusb, info.ptr_wrap, fifo, rem); count += rem; } @@ -311,9 +302,9 @@ static bool pipe0_xfer_in(rusb2_reg_t* rusb) if (len) { if (pipe->ff) { - pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len); + pipe_write_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len); } else { - pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len); + pipe_write_packet(rusb, buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } } @@ -338,9 +329,9 @@ static bool pipe0_xfer_out(rusb2_reg_t* rusb) if (len) { if (pipe->ff) { - pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len); + pipe_read_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len); } else { - pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len); + pipe_read_packet(rusb, buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } } @@ -376,9 +367,9 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num) if (len) { if (pipe->ff) { - pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len); + pipe_write_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len); } else { - pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len); + pipe_write_packet(rusb, buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } } @@ -410,9 +401,9 @@ static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num) if (len) { if (pipe->ff) { - pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len); + pipe_read_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len); } else { - pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len); + pipe_read_packet(rusb, buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } } @@ -733,10 +724,6 @@ void dcd_init(uint8_t rhport) // rusb2->BUSWAIT |= 0x0F00U; rusb->PHYSET_b.REPSEL = 1; - - rusb->CFIFOSEL_b.MBW = 1; - rusb->D0FIFOSEL_b.MBW = 1; - rusb->D1FIFOSEL_b.MBW = 1; } else #endif { diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index 7a5e37089..28cec9999 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -1670,6 +1670,7 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_FIFOSEL_BIGEND (1U << RUSB2_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */ #define RUSB2_FIFOSEL_MBW_8BIT (0U << RUSB2_CFIFOSEL_MBW_Pos) /* 8-bit width */ #define RUSB2_FIFOSEL_MBW_16BIT (1U << RUSB2_CFIFOSEL_MBW_Pos) /* 16-bit width */ +#define RUSB2_FIFOSEL_MBW_32BIT (2U << RUSB2_CFIFOSEL_MBW_Pos) /* 32-bit width */ #define RUSB2_INTSTS0_CTSQ_CTRL_RDATA (1U << RUSB2_INTSTS0_CTSQ_Pos) -- cgit v1.3.1 From 88478a9d052edc364561da39382faef72f937ecb Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 7 Jul 2023 16:24:22 +0700 Subject: add PORT selection for makefile --- hw/bsp/ra/boards/ra6m5_ek/board.mk | 3 +++ hw/bsp/ra/family.cmake | 2 +- hw/bsp/ra/family.mk | 12 ++++++++++++ src/portable/renesas/rusb2/dcd_rusb2.c | 4 ++++ 4 files changed, 20 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.mk b/hw/bsp/ra/boards/ra6m5_ek/board.mk index 567908b63..a5c933764 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.mk +++ b/hw/bsp/ra/boards/ra6m5_ek/board.mk @@ -4,4 +4,7 @@ MCU_VARIANT = ra6m5 # For flash-jlink target JLINK_DEVICE = R7FA6M5BH +# Port 1 is highspeed +PORT ?= 1 + flash: flash-jlink diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index eb2d4958f..f09e86a72 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -13,7 +13,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(FAMILY_MCUS RA CACHE INTERNAL "") +set(FAMILY_MCUS RAXXX CACHE INTERNAL "") #------------------------------------ # BOARD_TARGET diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index b6e1bb0ae..f5097460a 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -3,8 +3,12 @@ DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5 FSP_RA = hw/mcu/renesas/fsp/ra/fsp include $(TOP)/$(BOARD_PATH)/board.mk +# Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk +PORT ?= 0 + CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_RAXXX \ + -DBOARD_TUD_RHPORT=$(PORT) \ -Wno-error=undef \ -Wno-error=strict-prototypes \ -Wno-error=cast-align \ @@ -15,6 +19,14 @@ CFLAGS += \ -nostartfiles \ -ffreestanding +ifeq ($(PORT), 1) + CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + $(info "Using PORT 1 HighSpeed") +else + CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED + $(info "Using PORT 0 FullSpeed") +endif + SRC_C += \ src/portable/renesas/rusb2/dcd_rusb2.c \ src/portable/renesas/rusb2/hcd_rusb2.c \ diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 3d3e52bfa..17d22f696 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -216,6 +216,7 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo // Highspeed FIFO is 32-bit if ( is_highspeed_regbase(rusb) ) { + // TODO 32-bit access for better performance ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2); ff8 = (volatile uint8_t *) ((uintptr_t) fifo+3); }else { @@ -241,6 +242,9 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo static void pipe_read_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len) { (void) rusb; + + // TODO 16/32-bit access for better performance + uint8_t *p = (uint8_t*)buf; volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ while (len--) *p++ = *reg; -- cgit v1.3.1 From 0f53e746ffa21b6186809b2b896ddc74d38e9058 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 7 Jul 2023 18:41:16 +0700 Subject: move check highspeed to rusb_ra --- src/portable/renesas/rusb2/dcd_rusb2.c | 31 +++++-------------------------- src/portable/renesas/rusb2/rusb2_ra.h | 15 +++++++++++---- src/portable/renesas/rusb2/rusb2_rx.h | 9 +++++++++ src/portable/renesas/rusb2/rusb2_type.h | 14 ++++++++++++++ 4 files changed, 39 insertions(+), 30 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 17d22f696..358e5644b 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -61,19 +61,6 @@ TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN -typedef struct TU_ATTR_PACKED _ccrx_evenaccess { - union { - struct { - uint16_t : 8; - uint16_t TRCLR: 1; - uint16_t TRENB: 1; - uint16_t : 0; - }; - uint16_t TRE; - }; - uint16_t TRN; -} reg_pipetre_t; - typedef struct TU_ATTR_PACKED { void *buf; /* the start address of a transfer data buffer */ @@ -114,14 +101,6 @@ static dcd_data_t _dcd; // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -#ifdef RUSB2_SUPPORT_HIGHSPEED - #define is_highspeed_usbip(_p) (_p == 1) - #define is_highspeed_regbase(_reg) (_reg == RUSB2_REG(1)) -#else - #define is_highspeed_usbip(_p) (false) - #define is_highspeed_regbase(_reg) (false) -#endif - static unsigned find_pipe(unsigned xfer) { switch (xfer) { @@ -215,7 +194,7 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo volatile uint8_t *ff8; // Highspeed FIFO is 32-bit - if ( is_highspeed_regbase(rusb) ) { + if ( rusb2_is_highspeed_reg(rusb) ) { // TODO 32-bit access for better performance ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2); ff8 = (volatile uint8_t *) ((uintptr_t) fifo+3); @@ -706,7 +685,7 @@ void dcd_init(uint8_t rhport) rusb2_module_start(rhport, true); #ifdef RUSB2_SUPPORT_HIGHSPEED - if ( is_highspeed_usbip(rhport) ) { + if ( rusb2_is_highspeed_rhport(rhport) ) { rusb->SYSCFG_b.HSE = 1; // leave CLKSEL as default (0x11) 24Mhz @@ -787,7 +766,7 @@ void dcd_connect(uint8_t rhport) { rusb2_reg_t* rusb = RUSB2_REG(rhport); - if ( is_highspeed_usbip(rhport)) { + if ( rusb2_is_highspeed_rhport(rhport)) { rusb->SYSCFG_b.CNEN = 1; } rusb->SYSCFG_b.DPRPU = 1; @@ -824,7 +803,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) if (xfer == TUSB_XFER_ISOCHRONOUS) { // Fullspeed ISO is limit to 256 bytes - if ( !is_highspeed_usbip(rhport) && mps > 256) { + if ( !rusb2_is_highspeed_rhport(rhport) && mps > 256) { return false; } } @@ -838,7 +817,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) /* setup pipe */ dcd_int_disable(rhport); - if ( is_highspeed_usbip(rhport) ) { + if ( rusb2_is_highspeed_rhport(rhport) ) { // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed // depending on the allocation scheme rusb->PIPEBUF = 0x7C08; diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index e04a99685..28b690512 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -47,15 +47,15 @@ extern "C" { #pragma GCC diagnostic pop #endif -//--------------------------------------------------------------------+ -// -//--------------------------------------------------------------------+ - // IAR does not have __builtin_ctz #if defined(__ICCARM__) #define __builtin_ctz(x) __iar_builtin_CLZ(__iar_builtin_RBIT(x)) #endif +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + typedef struct { uint32_t reg_base; int32_t irqnum; @@ -78,6 +78,13 @@ static rusb2_controller_t rusb2_controller[] = { #define RUSB2_REG(_p) ((rusb2_reg_t*) rusb2_controller[_p].reg_base) +#define rusb2_is_highspeed_rhport(_p) (_p == 1) +#define rusb2_is_highspeed_reg(_reg) (_reg == RUSB2_REG(1)) + +//--------------------------------------------------------------------+ +// RUSB2 API +//--------------------------------------------------------------------+ + TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) { uint32_t const mask = 1U << (11+rhport); if (start) { diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h index 17b9a918c..7bf4be47e 100644 --- a/src/portable/renesas/rusb2/rusb2_rx.h +++ b/src/portable/renesas/rusb2/rusb2_rx.h @@ -42,6 +42,15 @@ TU_ATTR_ALWAYS_INLINE static inline rusb2_reg_t* RUSB2_REG(uint8_t rhport) { return (rusb2_reg_t *) RUSB2_REG_BASE; } + +#define rusb2_is_highspeed_rhport(_p) (false) +#define rusb2_is_highspeed_reg(_reg) (false) + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + + // Start/Stop MSTP TODO implement later TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) { (void) rhport; diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index 28cec9999..aceeb3c3e 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -48,6 +48,20 @@ extern "C" { TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN +// TODO same as RUSB2_PIPE_TR_t +typedef struct TU_ATTR_PACKED _ccrx_evenaccess { + union { + struct { + uint16_t : 8; + uint16_t TRCLR: 1; + uint16_t TRENB: 1; + uint16_t : 0; + }; + uint16_t TRE; + }; + uint16_t TRN; +} reg_pipetre_t; + typedef struct { union { volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */ -- cgit v1.3.1 From 8b6d0a166b3837e664eeabbada724b678b7fd62d Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Fri, 14 Jul 2023 15:30:22 -0700 Subject: Fix host buffer alignment setting --- src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 6 ++++++ src/tusb_option.h | 6 +++++- 2 files changed, 11 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h index c14f00431..96f0ba766 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h +++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h @@ -78,6 +78,12 @@ TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean(void const* addr, ui TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_invalidate(void const* addr, uint32_t data_size) { const uintptr_t addr32 = (uintptr_t) addr; if (imxrt_is_cache_mem(addr32)) { + // Invalidating does not push cached changes back to RAM so we need to be + // *very* careful when we do it. If we're not aligned, then we risk resetting + // values back to their RAM state. + // if (addr32 % 32 != 0) { + // TU_BREAKPOINT(); + // } SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size); } } diff --git a/src/tusb_option.h b/src/tusb_option.h index f16d8a5d0..c792efe6a 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -431,7 +431,11 @@ // Attribute to align memory for host controller #ifndef CFG_TUH_MEM_ALIGN - #define CFG_TUH_MEM_ALIGN TU_ATTR_ALIGNED(4) + #ifdef CFG_TUSB_MEM_ALIGN + #define CFG_TUH_MEM_ALIGN CFG_TUSB_MEM_ALIGN + #else + #define CFG_TUH_MEM_ALIGN TU_ATTR_ALIGNED(4) + #endif #endif //------------- CLASS -------------// -- cgit v1.3.1 From 1923b1845d033a3d42db9b739029b2cc39248150 Mon Sep 17 00:00:00 2001 From: Aladdin Bakosh Date: Fri, 23 Jun 2023 10:26:45 +0200 Subject: fix(RA_hcd): STALL status can be also 3 not only 2 --- src/host/usbh.c | 2 +- src/portable/renesas/rusb2/hcd_rusb2.c | 5 +++-- src/portable/renesas/rusb2/rusb2_type.h | 1 + 3 files changed, 5 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index f3e9d3858..184bda23b 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -791,7 +791,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b uint8_t const dir = tu_edpt_dir(ep_addr); tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir]; - TU_LOG_USBH(" Queue EP %02X with %u bytes ... ", ep_addr, total_bytes); + TU_LOG_USBH(" Queue EP %02X with %u bytes ... \r\n", ep_addr, total_bytes); // Attempt to transfer on a busy endpoint, sound like an race condition ! TU_ASSERT(ep_state->busy == 0); diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 0e6fa1618..193e07d8c 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -116,7 +116,7 @@ static unsigned find_pipe(unsigned xfer) for (int i = 3; i <= 5; ++i) { if (0 == _hcd.pipe[i].ep) return i; } - for (int i = 1; i <= 1; ++i) { + for (int i = 1; i <= 2; ++i) { if (0 == _hcd.pipe[i].ep) return i; } break; @@ -413,6 +413,7 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num) switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) { default: return; case RUSB2_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break; + case RUSB2_PIPE_CTR_PID_STALL2: result = XFER_RESULT_STALLED; break; case RUSB2_PIPE_CTR_PID_NAK: result = XFER_RESULT_FAILED; break; } pipe_state_t *pipe = &_hcd.pipe[num]; @@ -586,7 +587,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) uint8_t *ep = &_hcd.ep[dev_addr - 1][0][0]; for (int i = 0; i < 2 * 15; ++i, ++ep) { unsigned num = *ep; - if (!num || dev_addr != _hcd.pipe[num].dev) continue; + if (!num || (dev_addr != _hcd.pipe[num].dev)) continue; ctr = (uint16_t volatile*)&RUSB2->PIPE_CTR[num - 1]; *ctr = 0; diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index 90ba4f012..83119507a 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -1568,6 +1568,7 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_PIPE_CTR_PID_NAK (0U << RUSB2_PIPE_CTR_PID_Pos) /* NAK response */ #define RUSB2_PIPE_CTR_PID_BUF (1U << RUSB2_PIPE_CTR_PID_Pos) /* BUF response (depends buffer state) */ #define RUSB2_PIPE_CTR_PID_STALL (2U << RUSB2_PIPE_CTR_PID_Pos) /* STALL response */ +#define RUSB2_PIPE_CTR_PID_STALL2 (3U << RUSB2_PIPE_CTR_PID_Pos) /* Also STALL response */ #define RUSB2_DVSTCTR0_RHST_LS (1U << RUSB2_DVSTCTR0_RHST_Pos) /* Low-speed connection */ #define RUSB2_DVSTCTR0_RHST_FS (2U << RUSB2_DVSTCTR0_RHST_Pos) /* Full-speed connection */ -- cgit v1.3.1 From 41b608562a40b68d6b58d01a3239c466533b4b6b Mon Sep 17 00:00:00 2001 From: Aladdin Bakosh Date: Fri, 23 Jun 2023 14:21:58 +0200 Subject: debugging can be configured on renesas hcd --- src/portable/renesas/rusb2/hcd_rusb2.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 193e07d8c..65bbc656b 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -41,6 +41,8 @@ #error "Unsupported MCU" #endif +#define TU_RUSB2_HCD_DBG 0 + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ @@ -409,7 +411,7 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num) (void)rhport; xfer_result_t result; uint16_t volatile *ctr = get_pipectr(num); - // TU_LOG1("NRDY %d %x\n", num, *ctr); + TU_LOG(TU_RUSB2_HCD_DBG, "NRDY %d %x\n", num, *ctr); switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) { default: return; case RUSB2_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break; @@ -442,7 +444,7 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num) hcd_event_xfer_complete(pipe->dev, pipe->ep, pipe->length - pipe->remaining, XFER_RESULT_SUCCESS, true); - // TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining); + TU_LOG(TU_RUSB2_HCD_DBG, "C %d %d\r\n", num, pipe->length - pipe->remaining); } } @@ -609,7 +611,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { (void)rhport; - // TU_LOG1("S %d %x\n", dev_addr, RUSB2->DCPCTR); + TU_LOG(TU_RUSB2_HCD_DBG, "S %d %x\n", dev_addr, RUSB2->DCPCTR); TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ TU_ASSERT(0 == RUSB2->DCPCTR_b.SUREQ); @@ -702,7 +704,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b { bool r; hcd_int_disable(rhport); - // TU_LOG1("X %d %x %u\n", dev_addr, ep_addr, buflen); + TU_LOG(TU_RUSB2_HCD_DBG, "X %d %x %u\n", dev_addr, ep_addr, buflen); r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen); hcd_int_enable(rhport); return r; @@ -746,7 +748,7 @@ void hcd_int_handler(uint8_t rhport) /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1); RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0); - // TU_LOG1("IS %04x %04x\n", is0, is1); + TU_LOG(TU_RUSB2_HCD_DBG, "IS %04x %04x\n", is0, is1); is1 &= RUSB2->INTENB1; is0 &= RUSB2->INTENB0; -- cgit v1.3.1 From 3230d5b1ea45ac2b17e4abaac2bfbe190360fff8 Mon Sep 17 00:00:00 2001 From: Aladdin Bakosh Date: Fri, 23 Jun 2023 14:22:13 +0200 Subject: debugging can be configured on renesas dcd --- src/portable/renesas/rusb2/dcd_rusb2.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 78584125f..022c1b5b6 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -45,6 +45,8 @@ #error "Unsupported MCU" #endif +#define TU_RUSB2_DCD_DBG 0 + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ @@ -444,7 +446,7 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui *ctr = RUSB2_PIPE_CTR_PID_BUF; } } - // TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type); + TU_LOG(TU_RUSB2_DCD_DBG ,"X %x %d %d\r\n", ep_addr, total_bytes, buffer_type); return true; } @@ -487,7 +489,7 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num) dcd_event_xfer_complete(rhport, pipe->ep, pipe->length - pipe->remaining, XFER_RESULT_SUCCESS, true); - // TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining); + TU_LOG(TU_RUSB2_DCD_DBG, "C %d %d\r\n", num, pipe->length - pipe->remaining); } } @@ -691,7 +693,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) if (dir || (xfer != TUSB_XFER_BULK)) { *ctr = RUSB2_PIPE_CTR_PID_BUF; } - // TU_LOG1("O %d %x %x\r\n", RUSB2->PIPESEL, RUSB2->PIPECFG, RUSB2->PIPEMAXP); + TU_LOG(TU_RUSB2_DCD_DBG, "O %d %x %x\r\n", RUSB2->PIPESEL, RUSB2->PIPECFG, RUSB2->PIPEMAXP); dcd_int_enable(rhport); return true; -- cgit v1.3.1 From 3fdd2a40b2103089e47609a05577fc84b786ec4f Mon Sep 17 00:00:00 2001 From: Aladdin Bakosh Date: Fri, 2 Jun 2023 15:04:53 +0200 Subject: osal_none: make it possible to override the task delay function --- src/host/usbh.c | 2 +- src/osal/osal_none.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 184bda23b..1418cfb79 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -256,7 +256,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t #if CFG_TUSB_OS == OPT_OS_NONE // TODO rework time-related function later -void osal_task_delay(uint32_t msec) +TU_ATTR_WEAK void osal_task_delay(uint32_t msec) { const uint32_t start = hcd_frame_number(_usbh_controller); while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {} diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h index 5f407378e..76e77c25d 100644 --- a/src/osal/osal_none.h +++ b/src/osal/osal_none.h @@ -37,7 +37,7 @@ #if CFG_TUH_ENABLED // currently only needed/available in host mode -void osal_task_delay(uint32_t msec); +TU_ATTR_WEAK void osal_task_delay(uint32_t msec); #endif //--------------------------------------------------------------------+ -- cgit v1.3.1 From 77495cf119c89c3091e7ab05773ebce19988da86 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 20 Jul 2023 17:06:57 +0700 Subject: improve logging, allow easier to turn off usbd, driver logging can be useful when focusing on let's say usbh --- src/class/msc/msc_device.c | 43 +++++++++++---------- src/device/usbd.c | 93 ++++++++++++++++++++++------------------------ src/device/usbd_control.c | 9 ++--- src/device/usbd_pvt.h | 9 ++++- src/host/usbh.c | 34 +++++++++-------- 5 files changed, 97 insertions(+), 91 deletions(-) (limited to 'src') diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 159a11259..a409c4e27 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -34,13 +34,16 @@ #include "msc_device.h" +// Level where CFG_TUSB_DEBUG must be at least for this driver is logged +#ifndef CFG_TUD_MSC_LOG_LEVEL + #define CFG_TUD_MSC_LOG_LEVEL 2 +#endif + +#define TU_LOG_DRV(...) TU_LOG(CFG_TUD_MSC_LOG_LEVEL, __VA_ARGS__) + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ - -// Can be selectively disabled to reduce logging when troubleshooting other driver -#define MSC_DEBUG 2 - enum { MSC_STAGE_CMD = 0, @@ -164,7 +167,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) { if ( block_count ) { - TU_LOG(MSC_DEBUG, " SCSI case 2 (Hn < Di) or case 3 (Hn < Do) \r\n"); + TU_LOG_DRV(" SCSI case 2 (Hn < Di) or case 3 (Hn < Do) \r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; }else { @@ -174,22 +177,22 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) { if ( SCSI_CMD_READ_10 == cbw->command[0] && !is_data_in(cbw->dir) ) { - TU_LOG(MSC_DEBUG, " SCSI case 10 (Ho <> Di)\r\n"); + TU_LOG_DRV(" SCSI case 10 (Ho <> Di)\r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; } else if ( SCSI_CMD_WRITE_10 == cbw->command[0] && is_data_in(cbw->dir) ) { - TU_LOG(MSC_DEBUG, " SCSI case 8 (Hi <> Do)\r\n"); + TU_LOG_DRV(" SCSI case 8 (Hi <> Do)\r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; } else if ( 0 == block_count ) { - TU_LOG(MSC_DEBUG, " SCSI case 4 Hi > Dn (READ10) or case 9 Ho > Dn (WRITE10) \r\n"); + TU_LOG_DRV(" SCSI case 4 Hi > Dn (READ10) or case 9 Ho > Dn (WRITE10) \r\n"); status = MSC_CSW_STATUS_FAILED; } else if ( cbw->total_bytes / block_count == 0 ) { - TU_LOG(MSC_DEBUG, " Computed block size = 0. SCSI case 7 Hi < Di (READ10) or case 13 Ho < Do (WRIT10)\r\n"); + TU_LOG_DRV(" Computed block size = 0. SCSI case 7 Hi < Di (READ10) or case 13 Ho < Do (WRIT10)\r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; } } @@ -352,7 +355,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t switch ( request->bRequest ) { case MSC_REQ_RESET: - TU_LOG(MSC_DEBUG, " MSC BOT Reset\r\n"); + TU_LOG_DRV(" MSC BOT Reset\r\n"); TU_VERIFY(request->wValue == 0 && request->wLength == 0); // driver state reset @@ -363,7 +366,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t case MSC_REQ_GET_MAX_LUN: { - TU_LOG(MSC_DEBUG, " MSC Get Max Lun\r\n"); + TU_LOG_DRV(" MSC Get Max Lun\r\n"); TU_VERIFY(request->wValue == 0 && request->wLength == 1); uint8_t maxlun = 1; @@ -400,7 +403,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if ( !(xferred_bytes == sizeof(msc_cbw_t) && p_cbw->signature == MSC_CBW_SIGNATURE) ) { - TU_LOG(MSC_DEBUG, " SCSI CBW is not valid\r\n"); + TU_LOG_DRV(" SCSI CBW is not valid\r\n"); // BOT 6.6.1 If CBW is not valid stall both endpoints until reset recovery p_msc->stage = MSC_STAGE_NEED_RESET; @@ -412,7 +415,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t return false; } - TU_LOG(MSC_DEBUG, " SCSI Command [Lun%u]: %s\r\n", p_cbw->lun, tu_lookup_find(&_msc_scsi_cmd_table, p_cbw->command[0])); + TU_LOG_DRV(" SCSI Command [Lun%u]: %s\r\n", p_cbw->lun, tu_lookup_find(&_msc_scsi_cmd_table, p_cbw->command[0])); //TU_LOG_MEM(MSC_DEBUG, p_cbw, xferred_bytes, 2); p_csw->signature = MSC_CSW_SIGNATURE; @@ -457,7 +460,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t { if (p_cbw->total_bytes > sizeof(_mscd_buf)) { - TU_LOG(MSC_DEBUG, " SCSI reject non READ10/WRITE10 with large data\r\n"); + TU_LOG_DRV(" SCSI reject non READ10/WRITE10 with large data\r\n"); fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); }else { @@ -479,7 +482,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if ( resplen < 0 ) { // unsupported command - TU_LOG(MSC_DEBUG, " SCSI unsupported or failed command\r\n"); + TU_LOG_DRV(" SCSI unsupported or failed command\r\n"); fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); } else if (resplen == 0) @@ -514,7 +517,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t break; case MSC_STAGE_DATA: - TU_LOG(MSC_DEBUG, " SCSI Data [Lun%u]\r\n", p_cbw->lun); + TU_LOG_DRV(" SCSI Data [Lun%u]\r\n", p_cbw->lun); //TU_LOG_MEM(MSC_DEBUG, _mscd_buf, xferred_bytes, 2); if (SCSI_CMD_READ_10 == p_cbw->command[0]) @@ -546,7 +549,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if ( cb_result < 0 ) { // unsupported command - TU_LOG(MSC_DEBUG, " SCSI unsupported command\r\n"); + TU_LOG_DRV(" SCSI unsupported command\r\n"); fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); }else { @@ -575,7 +578,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // Wait for the Status phase to complete if( (ep_addr == p_msc->ep_in) && (xferred_bytes == sizeof(msc_csw_t)) ) { - TU_LOG(MSC_DEBUG, " SCSI Status [Lun%u] = %u\r\n", p_cbw->lun, p_csw->status); + TU_LOG_DRV(" SCSI Status [Lun%u] = %u\r\n", p_cbw->lun, p_csw->status); // TU_LOG_MEM(MSC_DEBUG, p_csw, xferred_bytes, 2); // Invoke complete callback if defined @@ -845,7 +848,7 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) if ( nbytes < 0 ) { // negative means error -> endpoint is stalled & status in CSW set to failed - TU_LOG(MSC_DEBUG, " tud_msc_read10_cb() return -1\r\n"); + TU_LOG_DRV(" tud_msc_read10_cb() return -1\r\n"); // set sense set_sense_medium_not_present(p_cbw->lun); @@ -907,7 +910,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 if ( nbytes < 0 ) { // negative means error -> failed this scsi op - TU_LOG(MSC_DEBUG, " tud_msc_write10_cb() return -1\r\n"); + TU_LOG_DRV(" tud_msc_write10_cb() return -1\r\n"); // update actual byte before failed p_msc->xferred_len += xferred_bytes; diff --git a/src/device/usbd.c b/src/device/usbd.c index 44c2530ce..9429cf664 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -43,9 +43,6 @@ #define CFG_TUD_TASK_QUEUE_SZ 16 #endif -// Debug level of USBD -#define USBD_DBG 2 - //--------------------------------------------------------------------+ // Device Data //--------------------------------------------------------------------+ @@ -81,7 +78,7 @@ tu_static usbd_device_t _usbd_dev; //--------------------------------------------------------------------+ // Class Driver //--------------------------------------------------------------------+ -#if CFG_TUSB_DEBUG >= 2 +#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL #define DRIVER_NAME(_name) .name = _name, #else #define DRIVER_NAME(_name) @@ -308,7 +305,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, //--------------------------------------------------------------------+ // Debug //--------------------------------------------------------------------+ -#if CFG_TUSB_DEBUG >= 2 +#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL tu_static char const* const _usbd_event_str[DCD_EVENT_COUNT] = { "Invalid" , @@ -330,7 +327,7 @@ void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback) usbd_class_driver_t const * driver = get_driver(i); if ( driver && driver->control_xfer_cb == callback ) { - TU_LOG(USBD_DBG, " %s control complete\r\n", driver->name); + TU_LOG_USBD(" %s control complete\r\n", driver->name); return; } } @@ -396,10 +393,10 @@ bool tud_init (uint8_t rhport) // skip if already initialized if ( tud_inited() ) return true; - TU_LOG(USBD_DBG, "USBD init on controller %u\r\n", rhport); - TU_LOG_INT(USBD_DBG, sizeof(usbd_device_t)); - TU_LOG_INT(USBD_DBG, sizeof(tu_fifo_t)); - TU_LOG_INT(USBD_DBG, sizeof(tu_edpt_stream_t)); + TU_LOG_USBD("USBD init on controller %u\r\n", rhport); + TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(usbd_device_t)); + TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_fifo_t)); + TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_edpt_stream_t)); tu_varclr(&_usbd_dev); @@ -424,7 +421,7 @@ bool tud_init (uint8_t rhport) { usbd_class_driver_t const * driver = get_driver(i); TU_ASSERT(driver); - TU_LOG(USBD_DBG, "%s init\r\n", driver->name); + TU_LOG_USBD("%s init\r\n", driver->name); driver->init(); } @@ -496,21 +493,21 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) dcd_event_t event; if ( !osal_queue_receive(_usbd_q, &event, timeout_ms) ) return; -#if CFG_TUSB_DEBUG >= 2 - if (event.event_id == DCD_EVENT_SETUP_RECEIVED) TU_LOG(USBD_DBG, "\r\n"); // extra line for setup - TU_LOG(USBD_DBG, "USBD %s ", event.event_id < DCD_EVENT_COUNT ? _usbd_event_str[event.event_id] : "CORRUPTED"); +#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL + if (event.event_id == DCD_EVENT_SETUP_RECEIVED) TU_LOG_USBD("\r\n"); // extra line for setup + TU_LOG_USBD("USBD %s ", event.event_id < DCD_EVENT_COUNT ? _usbd_event_str[event.event_id] : "CORRUPTED"); #endif switch ( event.event_id ) { case DCD_EVENT_BUS_RESET: - TU_LOG(USBD_DBG, ": %s Speed\r\n", tu_str_speed[event.bus_reset.speed]); + TU_LOG_USBD(": %s Speed\r\n", tu_str_speed[event.bus_reset.speed]); usbd_reset(event.rhport); _usbd_dev.speed = event.bus_reset.speed; break; case DCD_EVENT_UNPLUGGED: - TU_LOG(USBD_DBG, "\r\n"); + TU_LOG_USBD("\r\n"); usbd_reset(event.rhport); // invoke callback @@ -518,8 +515,8 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) break; case DCD_EVENT_SETUP_RECEIVED: - TU_LOG_PTR(USBD_DBG, &event.setup_received); - TU_LOG(USBD_DBG, "\r\n"); + TU_LOG_PTR(CFG_TUD_LOG_LEVEL, &event.setup_received); + TU_LOG_USBD("\r\n"); // Mark as connected after receiving 1st setup packet. // But it is easier to set it every time instead of wasting time to check then set @@ -534,7 +531,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) // Process control request if ( !process_control_request(event.rhport, &event.setup_received) ) { - TU_LOG(USBD_DBG, " Stall EP0\r\n"); + TU_LOG_USBD(" Stall EP0\r\n"); // Failed -> stall both control endpoint IN and OUT dcd_edpt_stall(event.rhport, 0); dcd_edpt_stall(event.rhport, 0 | TUSB_DIR_IN_MASK); @@ -548,7 +545,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const ep_dir = tu_edpt_dir(ep_addr); - TU_LOG(USBD_DBG, "on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len); + TU_LOG_USBD("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len); _usbd_dev.ep_status[epnum][ep_dir].busy = 0; _usbd_dev.ep_status[epnum][ep_dir].claimed = 0; @@ -563,7 +560,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) usbd_class_driver_t const * driver = get_driver( _usbd_dev.ep2drv[epnum][ep_dir] ); TU_ASSERT(driver, ); - TU_LOG(USBD_DBG, " %s xfer callback\r\n", driver->name); + TU_LOG_USBD(" %s xfer callback\r\n", driver->name); driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len); } } @@ -575,27 +572,27 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) // e.g suspend -> resume -> unplug/plug. Skip suspend/resume if not connected if ( _usbd_dev.connected ) { - TU_LOG(USBD_DBG, ": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en); + TU_LOG_USBD(": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en); if (tud_suspend_cb) tud_suspend_cb(_usbd_dev.remote_wakeup_en); }else { - TU_LOG(USBD_DBG, " Skipped\r\n"); + TU_LOG_USBD(" Skipped\r\n"); } break; case DCD_EVENT_RESUME: if ( _usbd_dev.connected ) { - TU_LOG(USBD_DBG, "\r\n"); + TU_LOG_USBD("\r\n"); if (tud_resume_cb) tud_resume_cb(); }else { - TU_LOG(USBD_DBG, " Skipped\r\n"); + TU_LOG_USBD(" Skipped\r\n"); } break; case USBD_EVENT_FUNC_CALL: - TU_LOG(USBD_DBG, "\r\n"); + TU_LOG_USBD("\r\n"); if ( event.func_call.func ) event.func_call.func(event.func_call.param); break; @@ -620,7 +617,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * driver, tusb_control_request_t const * request) { usbd_control_set_complete_callback(driver->control_xfer_cb); - TU_LOG(USBD_DBG, " %s control request\r\n", driver->name); + TU_LOG_USBD(" %s control request\r\n", driver->name); return driver->control_xfer_cb(rhport, CONTROL_STAGE_SETUP, request); } @@ -641,11 +638,11 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const return tud_vendor_control_xfer_cb(rhport, CONTROL_STAGE_SETUP, p_request); } -#if CFG_TUSB_DEBUG >= 2 +#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME) { - TU_LOG(USBD_DBG, " %s", tu_str_std_request[p_request->bRequest]); - if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG(USBD_DBG, "\r\n"); + TU_LOG_USBD(" %s", tu_str_std_request[p_request->bRequest]); + if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG_USBD("\r\n"); } #endif @@ -701,7 +698,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const if ( _usbd_dev.cfg_num ) { // already configured: need to clear all endpoints and driver first - TU_LOG(USBD_DBG, " Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num); + TU_LOG_USBD(" Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num); // close all non-control endpoints, cancel all pending transfers if any dcd_edpt_close_all(rhport); @@ -730,7 +727,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const // Only support remote wakeup for device feature TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue); - TU_LOG(USBD_DBG, " Enable Remote Wakeup\r\n"); + TU_LOG_USBD(" Enable Remote Wakeup\r\n"); // Host may enable remote wake up before suspending especially HID device _usbd_dev.remote_wakeup_en = true; @@ -741,7 +738,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const // Only support remote wakeup for device feature TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue); - TU_LOG(USBD_DBG, " Disable Remote Wakeup\r\n"); + TU_LOG_USBD(" Disable Remote Wakeup\r\n"); // Host may disable remote wake up after resuming _usbd_dev.remote_wakeup_en = false; @@ -924,7 +921,7 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num) if ( (sizeof(tusb_desc_interface_t) <= drv_len) && (drv_len <= remaining_len) ) { // Open successfully - TU_LOG(USBD_DBG, " %s opened\r\n", driver->name); + TU_LOG_USBD(" %s opened\r\n", driver->name); // Some drivers use 2 or more interfaces but may not have IAD e.g MIDI (always) or // BTH (even CDC) with class in device descriptor (single interface) @@ -983,7 +980,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const { case TUSB_DESC_DEVICE: { - TU_LOG(USBD_DBG, " Device\r\n"); + TU_LOG_USBD(" Device\r\n"); void* desc_device = (void*) (uintptr_t) tud_descriptor_device_cb(); @@ -1007,7 +1004,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const case TUSB_DESC_BOS: { - TU_LOG(USBD_DBG, " BOS\r\n"); + TU_LOG_USBD(" BOS\r\n"); // requested by host if USB > 2.0 ( i.e 2.1 or 3.x ) if (!tud_descriptor_bos_cb) return false; @@ -1029,12 +1026,12 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const if ( desc_type == TUSB_DESC_CONFIGURATION ) { - TU_LOG(USBD_DBG, " Configuration[%u]\r\n", desc_index); + TU_LOG_USBD(" Configuration[%u]\r\n", desc_index); desc_config = (uintptr_t) tud_descriptor_configuration_cb(desc_index); }else { // Host only request this after getting Device Qualifier descriptor - TU_LOG(USBD_DBG, " Other Speed Configuration\r\n"); + TU_LOG_USBD(" Other Speed Configuration\r\n"); TU_VERIFY( tud_descriptor_other_speed_configuration_cb ); desc_config = (uintptr_t) tud_descriptor_other_speed_configuration_cb(desc_index); } @@ -1050,7 +1047,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const case TUSB_DESC_STRING: { - TU_LOG(USBD_DBG, " String[%u]\r\n", desc_index); + TU_LOG_USBD(" String[%u]\r\n", desc_index); // String Descriptor always uses the desc set from user uint8_t const* desc_str = (uint8_t const*) tud_descriptor_string_cb(desc_index, tu_le16toh(p_request->wIndex)); @@ -1063,7 +1060,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const case TUSB_DESC_DEVICE_QUALIFIER: { - TU_LOG(USBD_DBG, " Device Qualifier\r\n"); + TU_LOG_USBD(" Device Qualifier\r\n"); TU_VERIFY( tud_descriptor_device_qualifier_cb ); @@ -1248,7 +1245,7 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t // TODO skip ready() check for now since enumeration also use this API // TU_VERIFY(tud_ready()); - TU_LOG(USBD_DBG, " Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes); + TU_LOG_USBD(" Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes); // Attempt to transfer on a busy endpoint, sound like an race condition ! TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0); @@ -1265,7 +1262,7 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t // DCD error, mark endpoint as ready to allow next transfer _usbd_dev.ep_status[epnum][dir].busy = 0; _usbd_dev.ep_status[epnum][dir].claimed = 0; - TU_LOG(USBD_DBG, "FAILED\r\n"); + TU_LOG_USBD("FAILED\r\n"); TU_BREAKPOINT(); return false; } @@ -1282,7 +1279,7 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - TU_LOG(USBD_DBG, " Queue ISO EP %02X with %u bytes ... ", ep_addr, total_bytes); + TU_LOG_USBD(" Queue ISO EP %02X with %u bytes ... ", ep_addr, total_bytes); // Attempt to transfer on a busy endpoint, sound like an race condition ! TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0); @@ -1293,14 +1290,14 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes)) { - TU_LOG(USBD_DBG, "OK\r\n"); + TU_LOG_USBD("OK\r\n"); return true; }else { // DCD error, mark endpoint as ready to allow next transfer _usbd_dev.ep_status[epnum][dir].busy = 0; _usbd_dev.ep_status[epnum][dir].claimed = 0; - TU_LOG(USBD_DBG, "failed\r\n"); + TU_LOG_USBD("failed\r\n"); TU_BREAKPOINT(); return false; } @@ -1326,7 +1323,7 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) // only stalled if currently cleared if ( !_usbd_dev.ep_status[epnum][dir].stalled ) { - TU_LOG(USBD_DBG, " Stall EP %02X\r\n", ep_addr); + TU_LOG_USBD(" Stall EP %02X\r\n", ep_addr); dcd_edpt_stall(rhport, ep_addr); _usbd_dev.ep_status[epnum][dir].stalled = 1; _usbd_dev.ep_status[epnum][dir].busy = 1; @@ -1343,7 +1340,7 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) // only clear if currently stalled if ( _usbd_dev.ep_status[epnum][dir].stalled ) { - TU_LOG(USBD_DBG, " Clear Stall EP %02X\r\n", ep_addr); + TU_LOG_USBD(" Clear Stall EP %02X\r\n", ep_addr); dcd_edpt_clear_stall(rhport, ep_addr); _usbd_dev.ep_status[epnum][dir].stalled = 0; _usbd_dev.ep_status[epnum][dir].busy = 0; @@ -1371,7 +1368,7 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr) rhport = _usbd_rhport; TU_ASSERT(dcd_edpt_close, /**/); - TU_LOG(USBD_DBG, " CLOSING Endpoint: 0x%02X\r\n", ep_addr); + TU_LOG_USBD(" CLOSING Endpoint: 0x%02X\r\n", ep_addr); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index 2afe967b5..c580e6ecf 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -32,10 +32,7 @@ #include "tusb.h" #include "device/usbd_pvt.h" -// Debug level of USBD Control -#define USBD_CONTROL_DEBUG 2 - -#if CFG_TUSB_DEBUG >= USBD_CONTROL_DEBUG +#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback); #endif @@ -191,7 +188,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result { TU_VERIFY(_ctrl_xfer.buffer); memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes); - TU_LOG_MEM(USBD_CONTROL_DEBUG, _usbd_ctrl_buf, xferred_bytes, 2); + TU_LOG_MEM(CFG_TUD_LOG_LEVEL, _usbd_ctrl_buf, xferred_bytes, 2); } _ctrl_xfer.total_xferred += (uint16_t) xferred_bytes; @@ -208,7 +205,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result // callback can still stall control in status phase e.g out data does not make sense if ( _ctrl_xfer.complete_cb ) { - #if CFG_TUSB_DEBUG >= USBD_CONTROL_DEBUG + #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL usbd_driver_print_control_complete_name(_ctrl_xfer.complete_cb); #endif diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h index 8393d3469..940b2858b 100644 --- a/src/device/usbd_pvt.h +++ b/src/device/usbd_pvt.h @@ -33,13 +33,20 @@ extern "C" { #endif +// Level where CFG_TUSB_DEBUG must be at least for USBD is logged +#ifndef CFG_TUD_LOG_LEVEL +#define CFG_TUD_LOG_LEVEL 2 +#endif + +#define TU_LOG_USBD(...) TU_LOG(CFG_TUD_LOG_LEVEL, __VA_ARGS__) + //--------------------------------------------------------------------+ // Class Driver API //--------------------------------------------------------------------+ typedef struct { - #if CFG_TUSB_DEBUG >= 2 + #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL char const* name; #endif diff --git a/src/host/usbh.c b/src/host/usbh.c index 184bda23b..58129c16e 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -38,17 +38,19 @@ //--------------------------------------------------------------------+ #ifndef CFG_TUH_TASK_QUEUE_SZ -#define CFG_TUH_TASK_QUEUE_SZ 16 + #define CFG_TUH_TASK_QUEUE_SZ 16 #endif #ifndef CFG_TUH_INTERFACE_MAX -#define CFG_TUH_INTERFACE_MAX 8 + #define CFG_TUH_INTERFACE_MAX 8 #endif -// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message -#define USBH_DEBUG 2 +// Level where CFG_TUSB_DEBUG must be at least for USBH is logged +#ifndef CFG_TUH_LOG_LEVEL + #define CFG_TUH_LOG_LEVEL 2 +#endif -#define TU_LOG_USBH(...) TU_LOG(USBH_DEBUG, __VA_ARGS__) +#define TU_LOG_USBH(...) TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__) //--------------------------------------------------------------------+ // USBH-HCD common data structure @@ -322,12 +324,12 @@ bool tuh_init(uint8_t controller_id) if ( tuh_inited() ) return true; TU_LOG_USBH("USBH init on controller %u\r\n", controller_id); - TU_LOG_INT(USBH_DEBUG, sizeof(usbh_device_t)); - TU_LOG_INT(USBH_DEBUG, sizeof(hcd_event_t)); - TU_LOG_INT(USBH_DEBUG, sizeof(_ctrl_xfer)); - TU_LOG_INT(USBH_DEBUG, sizeof(tuh_xfer_t)); - TU_LOG_INT(USBH_DEBUG, sizeof(tu_fifo_t)); - TU_LOG_INT(USBH_DEBUG, sizeof(tu_edpt_stream_t)); + TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(usbh_device_t)); + TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(hcd_event_t)); + TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(_ctrl_xfer)); + TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tuh_xfer_t)); + TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tu_fifo_t)); + TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tu_edpt_stream_t)); // Event queue _usbh_q = osal_queue_create( &_usbh_qdef ); @@ -565,7 +567,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr, (xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ? tu_str_std_request[xfer->setup->bRequest] : "Class Request"); - TU_LOG_PTR(USBH_DEBUG, xfer->setup); + TU_LOG_PTR(CFG_TUH_LOG_LEVEL, xfer->setup); TU_LOG_USBH("\r\n"); if (xfer->complete_cb) @@ -671,7 +673,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result if (request->wLength) { TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, dev_addr); - TU_LOG_MEM(USBH_DEBUG, _ctrl_xfer.buffer, xferred_bytes, 2); + TU_LOG_MEM(CFG_TUH_LOG_LEVEL, _ctrl_xfer.buffer, xferred_bytes, 2); } _ctrl_xfer.actual_len = (uint16_t) xferred_bytes; @@ -1186,7 +1188,7 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu TU_LOG_USBH("Device unplugged address = %u\r\n", daddr); if (is_hub_addr(daddr)) { - TU_LOG(USBH_DEBUG, " is a HUB device %u\r\n", daddr); + TU_LOG(CFG_TUH_LOG_LEVEL, " is a HUB device %u\r\n", daddr); // Submit removed event If the device itself is a hub (un-rolled recursive) // TODO a better to unroll recursrive is using array of removing_hubs and mark it here @@ -1657,7 +1659,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur if( drv_id >= USBH_CLASS_DRIVER_COUNT ) { - TU_LOG(USBH_DEBUG, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n", + TU_LOG(CFG_TUH_LOG_LEVEL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n", desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol); } } @@ -1695,7 +1697,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) if (is_hub_addr(dev_addr)) { - TU_LOG(USBH_DEBUG, "HUB address = %u is mounted\r\n", dev_addr); + TU_LOG(CFG_TUH_LOG_LEVEL, "HUB address = %u is mounted\r\n", dev_addr); }else { // Invoke callback if available -- cgit v1.3.1 From 16ad918d96b2bd01189906d64d0871f0ea952833 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 20 Jul 2023 17:37:06 +0700 Subject: prefer application callback over built-in driver --- src/host/usbh.c | 56 +++++++++++++++++++++++++------------------------------- 1 file changed, 25 insertions(+), 31 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 58129c16e..ecc672198 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -452,39 +452,28 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) TU_LOG_USBH("on EP %02X with %u bytes: %s\r\n", ep_addr, (unsigned int) event.xfer_complete.len, tu_str_xfer_result[event.xfer_complete.result]); - if (event.dev_addr == 0) - { + if (event.dev_addr == 0) { // device 0 only has control endpoint TU_ASSERT(epnum == 0, ); usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len); - } - else - { + } else { usbh_device_t* dev = get_device(event.dev_addr); TU_VERIFY(dev && dev->connected, ); dev->ep_status[epnum][ep_dir].busy = 0; dev->ep_status[epnum][ep_dir].claimed = 0; - if ( 0 == epnum ) - { - usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len); - }else - { - uint8_t drv_id = dev->ep2drv[epnum][ep_dir]; - if(drv_id < USBH_CLASS_DRIVER_COUNT) - { - TU_LOG_USBH("%s xfer callback\r\n", usbh_class_drivers[drv_id].name); - usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len); - } - else - { -#if CFG_TUH_API_EDPT_XFER - tuh_xfer_cb_t complete_cb = dev->ep_callback[epnum][ep_dir].complete_cb; - if ( complete_cb ) - { - tuh_xfer_t xfer = - { + if ( 0 == epnum ) { + usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, + event.xfer_complete.len); + }else { + // Prefer application callback over built-in one if available. This occurs when tuh_edpt_xfer() is used + // with enabled driver e.g HID endpoint + #if CFG_TUH_API_EDPT_XFER + tuh_xfer_cb_t const complete_cb = dev->ep_callback[epnum][ep_dir].complete_cb; + if ( complete_cb ) { + // re-construct xfer info + tuh_xfer_t xfer = { .daddr = event.dev_addr, .ep_addr = ep_addr, .result = event.xfer_complete.result, @@ -493,16 +482,21 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) .buffer = NULL, // not available .complete_cb = complete_cb, .user_data = dev->ep_callback[epnum][ep_dir].user_data - }; + }; - complete_cb(&xfer); - }else -#endif - { + complete_cb(&xfer); + }else + #endif + { + uint8_t const drv_id = dev->ep2drv[epnum][ep_dir]; + if ( drv_id < USBH_CLASS_DRIVER_COUNT ) { + TU_LOG_USBH("%s xfer callback\r\n", usbh_class_drivers[drv_id].name); + usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, + event.xfer_complete.len); + } else { // no driver/callback responsible for this transfer - TU_ASSERT(false, ); + TU_ASSERT(false,); } - } } } -- cgit v1.3.1 From 1cc7c5d0309bcc7c6930fba78bc461e5822e8024 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 20 Jul 2023 11:20:12 +0700 Subject: add hcd_edpt_abort_xfer() API --- examples/dual/host_hid_to_device_cdc/only.txt | 1 + src/host/hcd.h | 3 +++ src/host/usbh.c | 28 +++++++++++++++++++-------- src/host/usbh.h | 7 +++++-- src/portable/ehci/ehci.c | 18 +++++++++++++++++ 5 files changed, 47 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/examples/dual/host_hid_to_device_cdc/only.txt b/examples/dual/host_hid_to_device_cdc/only.txt index 6ee8e3fde..de5d8bed9 100644 --- a/examples/dual/host_hid_to_device_cdc/only.txt +++ b/examples/dual/host_hid_to_device_cdc/only.txt @@ -1,3 +1,4 @@ board:mimxrt1060_evk board:mimxrt1064_evk +board:mcb1800 mcu:RP2040 diff --git a/src/host/hcd.h b/src/host/hcd.h index 3355c18b2..cbfffb349 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -171,6 +171,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen); +// Abort a queued transfer. Note: it can only abort transfer that has not been started +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr); + // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]); diff --git a/src/host/usbh.c b/src/host/usbh.c index ecc672198..bbf333d5f 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -710,6 +710,19 @@ bool tuh_edpt_xfer(tuh_xfer_t* xfer) return true; } +bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) { + usbh_device_t* dev = get_device(daddr); + TU_VERIFY(dev); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + // skip if not busy + if (!dev->ep_status[epnum][dir].busy) return true; + + return hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr); +} + //--------------------------------------------------------------------+ // USBH API For Class Driver //--------------------------------------------------------------------+ @@ -741,7 +754,7 @@ void usbh_int_set(bool enabled) // Endpoint API //--------------------------------------------------------------------+ -// TODO has some duplication code with device, refactor later +// Claim an endpoint for transfer bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr) { // Note: addr0 only use tuh_control_xfer @@ -757,7 +770,7 @@ bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr) return true; } -// TODO has some duplication code with device, refactor later +// Release an claimed endpoint due to failed transfer attempt bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr) { // Note: addr0 only use tuh_control_xfer @@ -773,7 +786,7 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr) return true; } -// TODO has some duplication code with device, refactor later +// Submit an transfer bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { @@ -840,14 +853,13 @@ bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep) return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, desc_ep); } -bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr) -{ - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - +bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr) { usbh_device_t* dev = get_device(dev_addr); TU_VERIFY(dev); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + return dev->ep_status[epnum][dir].busy; } diff --git a/src/host/usbh.h b/src/host/usbh.h index 0f969a46a..d765f6744 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -172,8 +172,11 @@ bool tuh_control_xfer(tuh_xfer_t* xfer); // - sync : blocking if complete callback is NULL. bool tuh_edpt_xfer(tuh_xfer_t* xfer); -// Open an non-control endpoint -bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep); +// Open a non-control endpoint +bool tuh_edpt_open(uint8_t daddr, tusb_desc_endpoint_t const * desc_ep); + +// Abort a queued transfer. Note: it can only abort transfer that has not been started +bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr); // Set Configuration (control transfer) // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1 diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 38711e382..fd33d6cfc 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -510,6 +510,24 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * return true; } +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + + return false; + +// uint8_t const epnum = tu_edpt_number(ep_addr); +// ehci_qhd_t* qhd; +// +// // TODO ISO not supported +// if (epnum == 0) { +// qhd = qhd_control(dev_addr); +// }else { +// qhd = qhd_get_from_addr(dev_addr, ep_addr); +// } +} + bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr) { ehci_qhd_t *qhd = qhd_get_from_addr(daddr, ep_addr); -- cgit v1.3.1 From 0da273ea79d7a1c08e3b58301a0b7d3a49c60d13 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 21 Jul 2023 12:52:26 +0700 Subject: add stub hcd_edpt_abort_xfer() for all ports --- src/portable/mentor/musb/hcd_musb.c | 8 ++++++++ src/portable/nxp/khci/hcd_khci.c | 8 ++++++++ src/portable/ohci/ohci.c | 8 ++++++++ src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 8 ++++++++ src/portable/raspberrypi/rp2040/hcd_rp2040.c | 8 ++++++++ src/portable/renesas/rusb2/hcd_rusb2.c | 8 ++++++++ 6 files changed, 48 insertions(+) (limited to 'src') diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c index 9eb2e005e..5be67a186 100644 --- a/src/portable/mentor/musb/hcd_musb.c +++ b/src/portable/mentor/musb/hcd_musb.c @@ -822,6 +822,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b return ret; } +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + // TODO not implemented yet + return false; +} + // clear stall, data toggle is also reset to DATA0 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) { diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index f6029ee0d..6784049c5 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -562,6 +562,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * return true; } +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + // TODO not implemented yet + return false; +} + bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) { if (!tu_edpt_number(ep_addr)) return true; diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 3f702d22c..228c43df6 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -543,6 +543,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * return true; } +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + // TODO not implemented yet + return false; +} + bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) { ohci_ed_t * const p_ed = ed_from_addr(dev_addr, ep_addr); diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c index 264af2e7a..fa285327c 100644 --- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c @@ -138,6 +138,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * return pio_usb_host_endpoint_transfer(pio_rhport, dev_addr, ep_addr, buffer, buflen); } +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + // TODO not implemented yet + return false; +} + bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { uint8_t const pio_rhport = RHPORT_PIO(rhport); diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 02f9968a7..5091fa907 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -576,6 +576,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * return true; } +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + // TODO not implemented yet + return false; +} + bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { (void) rhport; diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 65bbc656b..0a75d0b47 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -710,6 +710,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b return r; } +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + // TODO not implemented yet + return false; +} + bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) { uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr); -- cgit v1.3.1 From 14c98dd863a9cab55fc2981fb826f63eceed4b2d Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 21 Jul 2023 16:39:30 +0700 Subject: minor ehci rename, move code around --- src/portable/ehci/ehci.c | 181 ++++++++++++++++++++++++----------------------- 1 file changed, 91 insertions(+), 90 deletions(-) (limited to 'src') diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index fd33d6cfc..0a26986d5 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -126,53 +126,29 @@ static inline void print_intr(uint32_t intr) { //--------------------------------------------------------------------+ // PROTOTYPE //--------------------------------------------------------------------+ -static inline ehci_link_t* get_period_head(uint8_t rhport, uint32_t interval_ms) -{ - (void) rhport; - return (ehci_link_t*) &ehci_data.period_head_arr[ tu_log2( tu_min32(FRAMELIST_SIZE, interval_ms) ) ]; -} - -static inline ehci_qhd_t* qhd_control(uint8_t dev_addr) -{ - return &ehci_data.control[dev_addr].qhd; -} - -static inline ehci_qhd_t* qhd_async_head(uint8_t rhport) -{ - (void) rhport; - // control qhd of dev0 is used as async head - return qhd_control(0); -} -static inline ehci_qtd_t* qtd_control(uint8_t dev_addr) -{ - return &ehci_data.control[dev_addr].qtd; -} +// weak dcache for non-cacheable MCU +TU_ATTR_WEAK void hcd_dcache_clean(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; } +TU_ATTR_WEAK void hcd_dcache_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; } +TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; } +TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_get_period_head(uint8_t rhport, uint32_t interval_ms); +TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhport); -static inline ehci_qhd_t* qhd_next (ehci_qhd_t const * p_qhd); -static inline ehci_qhd_t* qhd_find_free (void); -static inline ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr); +TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_control(uint8_t dev_addr); +TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_next (ehci_qhd_t const * p_qhd); +TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_find_free (void); +static ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr); static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc); static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd); -static inline ehci_qtd_t* qtd_find_free (void); +TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_control(uint8_t dev_addr); +TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_find_free (void); static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes); static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type); static inline ehci_link_t* list_next (ehci_link_t const *p_link); - -TU_ATTR_WEAK void hcd_dcache_clean(void const* addr, uint32_t data_size) { - (void) addr; (void) data_size; -} - -TU_ATTR_WEAK void hcd_dcache_invalidate(void const* addr, uint32_t data_size) { - (void) addr; (void) data_size; -} - -TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { - (void) addr; (void) data_size; -} +static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr); //--------------------------------------------------------------------+ // HCD API @@ -274,7 +250,7 @@ void hcd_device_close(uint8_t rhport, uint8_t daddr) } // Remove from async list - list_remove_qhd_by_daddr((ehci_link_t *) qhd_async_head(rhport), daddr); + list_remove_qhd_by_daddr((ehci_link_t *) list_get_async_head(rhport), daddr); // Remove from all interval period list for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) { @@ -286,37 +262,42 @@ void hcd_device_close(uint8_t rhport, uint8_t daddr) } static void init_periodic_list(uint8_t rhport) { + (void) rhport; + // Build the polling interval tree with 1 ms, 2 ms, 4 ms and 8 ms (framesize) only for ( uint32_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++ ) { ehci_data.period_head_arr[i].int_smask = 1; // queue head in period list must have smask non-zero ehci_data.period_head_arr[i].qtd_overlay.halted = 1; // dummy node, always inactive } - ehci_link_t * const framelist = ehci_data.period_framelist; - ehci_link_t * const period_1ms = get_period_head(rhport, 1u); - + // TODO EHCI_FRAMELIST_SIZE with other size than 8 // all links --> period_head_arr[0] (1ms) // 0, 2, 4, 6 etc --> period_head_arr[1] (2ms) // 1, 5 --> period_head_arr[2] (4ms) // 3 --> period_head_arr[3] (8ms) - // TODO EHCI_FRAMELIST_SIZE with other size than 8 + ehci_link_t * const framelist = ehci_data.period_framelist; + ehci_link_t * const head_1ms = (ehci_link_t *) &ehci_data.period_head_arr[0]; + ehci_link_t * const head_2ms = (ehci_link_t *) &ehci_data.period_head_arr[1]; + ehci_link_t * const head_4ms = (ehci_link_t *) &ehci_data.period_head_arr[2]; + ehci_link_t * const head_8ms = (ehci_link_t *) &ehci_data.period_head_arr[3]; + for (uint32_t i = 0; i < FRAMELIST_SIZE; i++) { - framelist[i].address = (uint32_t) period_1ms; + framelist[i].address = (uint32_t) head_1ms; framelist[i].type = EHCI_QTYPE_QHD; } for (uint32_t i = 0; i < FRAMELIST_SIZE; i += 2) { - list_insert(framelist + i, get_period_head(rhport, 2u), EHCI_QTYPE_QHD); + list_insert(framelist + i, head_2ms, EHCI_QTYPE_QHD); } for (uint32_t i = 1; i < FRAMELIST_SIZE; i += 4) { - list_insert(framelist + i, get_period_head(rhport, 4u), EHCI_QTYPE_QHD); + list_insert(framelist + i, head_4ms, EHCI_QTYPE_QHD); } - list_insert(framelist + 3, get_period_head(rhport, 8u), EHCI_QTYPE_QHD); + list_insert(framelist + 3, head_8ms, EHCI_QTYPE_QHD); - period_1ms->terminate = 1; + head_1ms->terminate = 1; } bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) @@ -345,7 +326,7 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) EHCI_INT_MASK_NXP_PERIODIC | EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_FRAMELIST_ROLLOVER; //------------- Asynchronous List -------------// - ehci_qhd_t * const async_head = qhd_async_head(rhport); + ehci_qhd_t * const async_head = list_get_async_head(rhport); tu_memclr(async_head, sizeof(ehci_qhd_t)); async_head->next.address = (uint32_t) async_head; // circular list, next is itself @@ -426,11 +407,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const { case TUSB_XFER_CONTROL: case TUSB_XFER_BULK: - list_head = (ehci_link_t*) qhd_async_head(rhport); + list_head = (ehci_link_t*) list_get_async_head(rhport); break; case TUSB_XFER_INTERRUPT: - list_head = get_period_head(rhport, p_qhd->interval_ms); + list_head = list_get_period_head(rhport, p_qhd->interval_ms); break; case TUSB_XFER_ISOCHRONOUS: @@ -439,10 +420,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const default: break; } - TU_ASSERT(list_head); - // TODO might need to disable async/period list list_insert(list_head, (ehci_link_t*) p_qhd, EHCI_QTYPE_QHD); hcd_dcache_clean(p_qhd, sizeof(ehci_qhd_t)); @@ -622,8 +601,8 @@ void async_list_xfer_complete_isr(ehci_qhd_t * const async_head) TU_ATTR_ALWAYS_INLINE static inline void period_list_xfer_complete_isr(uint8_t rhport, uint32_t interval_ms) { - uint32_t const period_1ms_addr = (uint32_t) get_period_head(rhport, 1u); - ehci_link_t next_link = * get_period_head(rhport, interval_ms); + uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u); + ehci_link_t next_link = *list_get_period_head(rhport, interval_ms); while (!next_link.terminate) { if (interval_ms > 1 && period_1ms_addr == tu_align32(next_link.address)) { @@ -721,7 +700,7 @@ TU_ATTR_ALWAYS_INLINE static inline void xfer_error_isr(uint8_t rhport) { //------------- async list -------------// - ehci_qhd_t * const async_head = qhd_async_head(rhport); + ehci_qhd_t * const async_head = list_get_async_head(rhport); ehci_qhd_t *p_qhd = async_head; do { @@ -731,10 +710,10 @@ void xfer_error_isr(uint8_t rhport) }while(p_qhd != async_head); // async list traversal, stop if loop around //------------- TODO refractor period list -------------// - uint32_t const period_1ms_addr = (uint32_t) get_period_head(rhport, 1u); + uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u); for (uint32_t interval_ms=1; interval_ms <= FRAMELIST_SIZE; interval_ms *= 2) { - ehci_link_t next_item = * get_period_head(rhport, interval_ms); + ehci_link_t next_item = *list_get_period_head(rhport, interval_ms); // TODO abstract max loop guard for period while( !next_item.terminate && @@ -801,7 +780,7 @@ void hcd_int_handler(uint8_t rhport) //------------- some QTD/SITD/ITD with IOC set is completed -------------// if (int_status & EHCI_INT_MASK_NXP_ASYNC) { - async_list_xfer_complete_isr(qhd_async_head(rhport)); + async_list_xfer_complete_isr(list_get_async_head(rhport)); regs->status = EHCI_INT_MASK_NXP_ASYNC; // Acknowledge } @@ -828,35 +807,62 @@ void hcd_int_handler(uint8_t rhport) } //--------------------------------------------------------------------+ -// HELPER +// List Managing Helper //--------------------------------------------------------------------+ +// Get head of periodic list +TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_get_period_head(uint8_t rhport, uint32_t interval_ms) { + (void) rhport; + return (ehci_link_t*) &ehci_data.period_head_arr[ tu_log2( tu_min32(FRAMELIST_SIZE, interval_ms) ) ]; +} -//------------- queue head helper -------------// -static inline ehci_qhd_t* qhd_find_free (void) +// Get head of async list +TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhport) { + (void) rhport; + return qhd_control(0); // control qhd of dev0 is used as async head +} + +// insert at head +static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type) { - for (uint32_t i=0; iaddress = current->address; + current->address = ((uint32_t) new) | (new_type << 1); +} + +static inline ehci_link_t* list_next(ehci_link_t const *p_link) +{ + return (ehci_link_t*) tu_align32(p_link->address); +} + +//--------------------------------------------------------------------+ +// Queue Header helper +//--------------------------------------------------------------------+ + +// Get queue head for control transfer (always available) +TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_control(uint8_t dev_addr) { + return &ehci_data.control[dev_addr].qhd; +} + +// Find a free queue head +TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t *qhd_find_free(void) { + for ( uint32_t i = 0; i < QHD_MAX; i++ ) { if ( !ehci_data.qhd_pool[i].used ) return &ehci_data.qhd_pool[i]; } - return NULL; } -static inline ehci_qhd_t* qhd_next(ehci_qhd_t const * p_qhd) -{ - return (ehci_qhd_t*) tu_align32(p_qhd->next.address); +// Next queue head link +TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t *qhd_next(ehci_qhd_t const *p_qhd) { + return (ehci_qhd_t *) tu_align32(p_qhd->next.address); } -static inline ehci_qhd_t* qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) -{ - ehci_qhd_t* qhd_pool = ehci_data.qhd_pool; +// Get queue head from address +static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) { + ehci_qhd_t *qhd_pool = ehci_data.qhd_pool; - for(uint32_t i=0; i cannot be cleared (ehci halted otherwise) @@ -938,6 +945,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c } } +// Attach a TD to queue head static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd) { qhd->attached_qtd = qtd; qhd->attached_buffer = qtd->buffer[0]; @@ -949,9 +957,16 @@ static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd) { hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); } +//--------------------------------------------------------------------+ +// Queue TD helper +//--------------------------------------------------------------------+ + +// Get TD for control transfer (always available) +TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_control(uint8_t dev_addr) { + return &ehci_data.control[dev_addr].qtd; +} -//------------- TD helper -------------// -static inline ehci_qtd_t *qtd_find_free(void) { +TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t *qtd_find_free(void) { for (uint32_t i = 0; i < QTD_MAX; i++) { if (!ehci_data.qtd_pool[i].used) return &ehci_data.qtd_pool[i]; } @@ -979,18 +994,4 @@ static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes) } } -//------------- List Managing Helper -------------// - -// insert at head -static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type) -{ - new->address = current->address; - current->address = ((uint32_t) new) | (new_type << 1); -} - -static inline ehci_link_t* list_next(ehci_link_t const *p_link) -{ - return (ehci_link_t*) tu_align32(p_link->address); -} - #endif -- cgit v1.3.1 From c122e9df73331fa60d1713c7cc4cf46251b0cd76 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 21 Jul 2023 19:06:36 +0700 Subject: implement hcd_edpt_abort_xfer() for EHCI, also move thing around a bit --- src/common/tusb_common.h | 2 + src/host/hcd.h | 1 + src/host/usbh.c | 10 ++- src/host/usbh.h | 1 + src/portable/ehci/ehci.c | 200 +++++++++++++++++++++++++++++------------------ src/portable/ehci/ehci.h | 19 +++-- 6 files changed, 147 insertions(+), 86 deletions(-) (limited to 'src') diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 957491aa9..b3d9fc7cd 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -53,6 +53,8 @@ #define U32_TO_U8S_LE(_u32) TU_U32_BYTE0(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE3(_u32) #define TU_BIT(n) (1UL << (n)) + +// Generate a mask with bit from high (31) to low (0) set, e.g TU_GENMASK(3, 0) = 0b1111 #define TU_GENMASK(h, l) ( (UINT32_MAX << (l)) & (UINT32_MAX >> (31 - (h))) ) //--------------------------------------------------------------------+ diff --git a/src/host/hcd.h b/src/host/hcd.h index cbfffb349..90bfd79db 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -172,6 +172,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen); // Abort a queued transfer. Note: it can only abort transfer that has not been started +// Return true if a queued transfer is aborted, false if there is no transfer to abort bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr); // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked diff --git a/src/host/usbh.c b/src/host/usbh.c index bbf333d5f..15c48be47 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -718,9 +718,15 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) { uint8_t const dir = tu_edpt_dir(ep_addr); // skip if not busy - if (!dev->ep_status[epnum][dir].busy) return true; + TU_VERIFY(dev->ep_status[epnum][dir].busy); - return hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr); + bool const ret = hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr); + if (ret) { + // mark as ready if transfer is aborted + dev->ep_status[epnum][dir].busy = false; + } + + return ret; } //--------------------------------------------------------------------+ diff --git a/src/host/usbh.h b/src/host/usbh.h index d765f6744..0d56f40c9 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -176,6 +176,7 @@ bool tuh_edpt_xfer(tuh_xfer_t* xfer); bool tuh_edpt_open(uint8_t daddr, tusb_desc_endpoint_t const * desc_ep); // Abort a queued transfer. Note: it can only abort transfer that has not been started +// Return true if a queued transfer is aborted, false if there is no transfer to abort bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr); // Set Configuration (control transfer) diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 0a26986d5..6388add08 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -48,8 +48,8 @@ #ifdef TUP_USBIP_CHIPIDEA_HS // NXP Transdimension: 8 elements #define FRAMELIST_SIZE_BIT_VALUE 7u - #define FRAMELIST_SIZE_USBCMD_VALUE (((FRAMELIST_SIZE_BIT_VALUE & 3) << EHCI_USBCMD_POS_FRAMELIST_SIZE) | \ - ((FRAMELIST_SIZE_BIT_VALUE >> 2) << EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB)) + #define FRAMELIST_SIZE_USBCMD_VALUE (((FRAMELIST_SIZE_BIT_VALUE & 3) << EHCI_USBCMD_FRAMELIST_SIZE_SHIFT) | \ + ((FRAMELIST_SIZE_BIT_VALUE >> 2) << EHCI_USBCMD_CHIPIDEA_FRAMELIST_SIZE_MSB_SHIFT)) #else // STD EHCI: 256 elements #define FRAMELIST_SIZE_BIT_VALUE 2u @@ -132,24 +132,46 @@ TU_ATTR_WEAK void hcd_dcache_clean(void const* addr, uint32_t data_size) { (void TU_ATTR_WEAK void hcd_dcache_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; } TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; } -TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_get_period_head(uint8_t rhport, uint32_t interval_ms); -TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhport); - TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_control(uint8_t dev_addr); TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_next (ehci_qhd_t const * p_qhd); TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_find_free (void); static ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr); static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc); static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd); +static void qhd_remove_qtd(ehci_qhd_t *qhd); TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_control(uint8_t dev_addr); TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_find_free (void); static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes); -static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type); -static inline ehci_link_t* list_next (ehci_link_t const *p_link); +TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_get_period_head(uint8_t rhport, uint32_t interval_ms); +TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhport); +TU_ATTR_ALWAYS_INLINE static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type); +TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next (ehci_link_t const *p_link); static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr); +static void ehci_disable_schedule(ehci_registers_t* regs, bool is_period) { + // maybe have a timeout for status + if (is_period) { + regs->command_bm.periodic_enable = 0; + while(regs->status_bm.periodic_status) {} + } else { + regs->command_bm.async_enable = 0; + while(regs->status_bm.async_status) {} // should have a timeout + } +} + +static void ehci_enable_schedule(ehci_registers_t* regs, bool is_period) { + // maybe have a timeout for status + if (is_period) { + regs->command_bm.periodic_enable = 1; + while ( 0 == regs->status_bm.periodic_status ) {} + } else { + regs->command_bm.async_enable = 1; + while( 0 == regs->status_bm.async_status ) {} + } +} + //--------------------------------------------------------------------+ // HCD API //--------------------------------------------------------------------+ @@ -204,43 +226,6 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport) return (tusb_speed_t) ehci_data.regs->portsc_bm.nxp_port_speed; // NXP specific port speed } -static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr) { - ehci_link_t* prev = list_head; - - while (prev && !prev->terminate) { - ehci_qhd_t* qhd = (ehci_qhd_t*) (uintptr_t) list_next(prev); - - // done if loop back to head - if ( (uintptr_t) qhd == (uintptr_t) list_head) { - break; - } - - if ( qhd->dev_addr == dev_addr ) { - // TODO deactivate all TD, wait for QHD to inactive before removal - prev->address = qhd->next.address; - - // EHCI 4.8.2 link the removed qhd's next to async head (which always reachable by Host Controller) - qhd->next.address = ((uint32_t) list_head) | (EHCI_QTYPE_QHD << 1); - - if ( qhd->int_smask ) - { - // period list queue element is guarantee to be free in the next frame (1 ms) - qhd->used = 0; - }else - { - // async list use async advance handshake - // mark as removing, will completely re-usable when async advance isr occurs - qhd->removing = 1; - } - - hcd_dcache_clean(qhd, sizeof(ehci_qhd_t)); - hcd_dcache_clean(prev, sizeof(ehci_qhd_t)); - }else { - prev = list_next(prev); - } - } -} - // Close all opened endpoint belong to this device void hcd_device_close(uint8_t rhport, uint8_t daddr) { @@ -347,8 +332,7 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) regs->nxp_tt_control = 0; //------------- USB CMD Register -------------// - regs->command |= TU_BIT(EHCI_USBCMD_POS_RUN_STOP) | TU_BIT(EHCI_USBCMD_POS_ASYNC_ENABLE) | - TU_BIT(EHCI_USBCMD_POS_PERIOD_ENABLE) | // TODO enable period list only there is int/iso endpoint + regs->command |= EHCI_USBCMD_RUN_STOP | EHCI_USBCMD_PERIOD_SCHEDULE_ENABLE | EHCI_USBCMD_ASYNC_SCHEDULE_ENABLE | FRAMELIST_SIZE_USBCMD_VALUE; //------------- ConfigFlag Register (skip) -------------// @@ -358,7 +342,7 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) if (ehci_data.cap_regs->hcsparams_bm.port_power_control) { // mask out all change bits since they are Write 1 to clear uint32_t portsc = (regs->portsc & ~EHCI_PORTSC_MASK_W1C); - portsc |= ECHI_PORTSC_MASK_PORT_POWER; + portsc |= EHCI_PORTSC_MASK_PORT_POWER; regs->portsc = portsc; } @@ -455,20 +439,17 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - ehci_qhd_t* qhd; + ehci_qhd_t* qhd = qhd_get_from_addr(dev_addr, ep_addr); ehci_qtd_t* qtd; if (epnum == 0) { - qhd = qhd_control(dev_addr); qtd = qtd_control(dev_addr); - qtd_init(qtd, buffer, buflen); // first data toggle is always 1 (data & setup stage) qtd->data_toggle = 1; qtd->pid = dir ? EHCI_PID_IN : EHCI_PID_OUT; } else { - qhd = qhd_get_from_addr(dev_addr, ep_addr); qtd = qtd_find_free(); TU_ASSERT(qtd); @@ -491,20 +472,34 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { (void) rhport; - (void) dev_addr; - (void) ep_addr; - return false; + // TODO ISO not supported yet + ehci_qhd_t* qhd = qhd_get_from_addr(dev_addr, ep_addr); + ehci_qtd_t * volatile qtd = qhd->attached_qtd; + TU_VERIFY(qtd != NULL); // no queued transfer + + hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); + TU_VERIFY(qtd->active); // transfer is already complete + + // HC is still processing, disable HC list schedule before making changes + bool const is_period = (qhd->interval_ms > 0); + + ehci_disable_schedule(ehci_data.regs, is_period); + + // check active bit again just in case HC has just processed the TD + bool const still_active = qtd->active; + if (still_active) { + // remove TD from QH overlay + qhd->qtd_overlay.next.terminate = 1; + hcd_dcache_clean(qhd, sizeof(ehci_qhd_t)); + + // remove TD from QH software list + qhd_remove_qtd(qhd); + } -// uint8_t const epnum = tu_edpt_number(ep_addr); -// ehci_qhd_t* qhd; -// -// // TODO ISO not supported -// if (epnum == 0) { -// qhd = qhd_control(dev_addr); -// }else { -// qhd = qhd_get_from_addr(dev_addr, ep_addr); -// } + ehci_enable_schedule(ehci_data.regs, is_period); + + return still_active; // true if removed an active transfer } bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr) @@ -554,8 +549,12 @@ void port_connect_status_change_isr(uint8_t rhport) TU_ATTR_ALWAYS_INLINE static inline void qhd_xfer_complete_isr(ehci_qhd_t * qhd) { // examine TD attached to queue head - ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) qhd->attached_qtd; - if (qtd == NULL) return; // no TD attached + ehci_qtd_t * volatile qtd = qhd->attached_qtd; + + if (qtd == NULL) { + return; // no TD attached + } + hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); // TD is still active, no need to process @@ -572,9 +571,7 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) { } // remove and free TD before invoking callback - qhd->attached_qtd = NULL; - qhd->attached_buffer = 0; - qtd->used = 0; // free QTD + qhd_remove_qtd(qhd); // notify usbh uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir); @@ -677,9 +674,7 @@ void qhd_xfer_error_isr(ehci_qhd_t * qhd) } // remove and free TD before invoking callback - qhd->attached_qtd = NULL; - qhd->attached_buffer = 0; - qtd->used = 0; // free QTD + qhd_remove_qtd(qhd); if (0 == qhd->ep_number ) { // control cannot be halted @@ -822,18 +817,55 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhpo return qhd_control(0); // control qhd of dev0 is used as async head } -// insert at head -static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type) +TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next(ehci_link_t const *p_link) { + return (ehci_link_t*) tu_align32(p_link->address); +} + +TU_ATTR_ALWAYS_INLINE static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type) { new->address = current->address; current->address = ((uint32_t) new) | (new_type << 1); } -static inline ehci_link_t* list_next(ehci_link_t const *p_link) -{ - return (ehci_link_t*) tu_align32(p_link->address); +// Remove all queue head belong to this device address +static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr) { + ehci_link_t* prev = list_head; + + while (prev && !prev->terminate) { + ehci_qhd_t* qhd = (ehci_qhd_t*) (uintptr_t) list_next(prev); + + // done if loop back to head + if ( (uintptr_t) qhd == (uintptr_t) list_head) { + break; + } + + if ( qhd->dev_addr == dev_addr ) { + // TODO deactivate all TD, wait for QHD to inactive before removal + prev->address = qhd->next.address; + + // EHCI 4.8.2 link the removed qhd's next to async head (which always reachable by Host Controller) + qhd->next.address = ((uint32_t) list_head) | (EHCI_QTYPE_QHD << 1); + + if ( qhd->int_smask ) + { + // period list queue element is guarantee to be free in the next frame (1 ms) + qhd->used = 0; + }else + { + // async list use async advance handshake + // mark as removing, will completely re-usable when async advance isr occurs + qhd->removing = 1; + } + + hcd_dcache_clean(qhd, sizeof(ehci_qhd_t)); + hcd_dcache_clean(prev, sizeof(ehci_qhd_t)); + }else { + prev = list_next(prev); + } + } } + //--------------------------------------------------------------------+ // Queue Header helper //--------------------------------------------------------------------+ @@ -856,8 +888,12 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t *qhd_next(ehci_qhd_t const *p_qhd return (ehci_qhd_t *) tu_align32(p_qhd->next.address); } -// Get queue head from address +// Get queue head from device + endpoint address static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) { + if ( 0 == tu_edpt_number(ep_addr) ) { + return qhd_control(dev_addr); + } + ehci_qhd_t *qhd_pool = ehci_data.qhd_pool; for ( uint32_t i = 0; i < QHD_MAX; i++ ) { @@ -957,6 +993,16 @@ static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd) { hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); } +// Remove an attached TD from queue head +static void qhd_remove_qtd(ehci_qhd_t *qhd) { + ehci_qtd_t * volatile qtd = qhd->attached_qtd; + + qhd->attached_qtd = NULL; + qhd->attached_buffer = 0; + + qtd->used = 0; // free QTD +} + //--------------------------------------------------------------------+ // Queue TD helper //--------------------------------------------------------------------+ diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h index 8338fb419..05de80539 100644 --- a/src/portable/ehci/ehci.h +++ b/src/portable/ehci/ehci.h @@ -289,12 +289,17 @@ enum { }; enum { - EHCI_USBCMD_POS_RUN_STOP = 0, - EHCI_USBCMD_POS_FRAMELIST_SIZE = 2, - EHCI_USBCMD_POS_PERIOD_ENABLE = 4, - EHCI_USBCMD_POS_ASYNC_ENABLE = 5, - EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB = 15, - EHCI_USBCMD_POS_INTERRUPT_THRESHOLD = 16 + EHCI_USBCMD_FRAMELIST_SIZE_SHIFT = 2, // [2..3] + EHCI_USBCMD_CHIPIDEA_FRAMELIST_SIZE_MSB_SHIFT = 15, + EHCI_USBCMD_INTERRUPT_THRESHOLD_SHIFT = 16 +}; + +enum { + EHCI_USBCMD_RUN_STOP = TU_BIT(0), // [0..0] 1 = Run, 0 = Stop + EHCI_USBCMD_HCRESET = TU_BIT(1), // [1..1] SW write 1 to reset HC, clear by HC when complete + EHCI_USBCMD_PERIOD_SCHEDULE_ENABLE = TU_BIT(4), // [4..4] Enable periodic schedule + EHCI_USBCMD_ASYNC_SCHEDULE_ENABLE = TU_BIT(5), // [5..5] Enable async schedule + EHCI_USBCMD_INTR_ON_ASYNC_ADVANCE_DOORBELL = TU_BIT(6), // [6..6] Tell HC to interrupt next time it advances async list. Clear by HC }; enum { @@ -306,7 +311,7 @@ enum { EHCI_PORTSC_MASK_FORCE_RESUME = TU_BIT(6), EHCI_PORTSC_MASK_PORT_SUSPEND = TU_BIT(7), EHCI_PORTSC_MASK_PORT_RESET = TU_BIT(8), - ECHI_PORTSC_MASK_PORT_POWER = TU_BIT(12), + EHCI_PORTSC_MASK_PORT_POWER = TU_BIT(12), EHCI_PORTSC_MASK_W1C = EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE | -- cgit v1.3.1 From e2f28bc134446dc081766055171ca427afd4f564 Mon Sep 17 00:00:00 2001 From: emb4fun Date: Sun, 23 Jul 2023 10:53:22 +0200 Subject: Added support for the NXP K64 series --- hw/bsp/board_mcu.h | 2 +- src/common/tusb_mcu.h | 2 +- src/portable/nxp/khci/dcd_khci.c | 14 ++++++++++++++ src/tusb_option.h | 1 + 4 files changed, 17 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index e5d2bb608..3928435f0 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -47,7 +47,7 @@ #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX, OPT_MCU_MCXN9) #include "fsl_device_registers.h" -#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L) +#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K64) #include "fsl_device_registers.h" #elif CFG_TUSB_MCU == OPT_MCU_NRF5X diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 9f3be78fd..4a0c5acef 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -97,7 +97,7 @@ #define TUP_DCD_ENDPOINT_MAX 8 #define TUP_RHPORT_HIGHSPEED 1 -#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L) +#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K64) #define TUP_USBIP_CHIPIDEA_FS #define TUP_USBIP_CHIPIDEA_FS_KINETIS #define TUP_DCD_ENDPOINT_MAX 16 diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 52f4145f2..d957338ad 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -269,8 +269,22 @@ void dcd_init(uint8_t rhport) { (void) rhport; +#if (CFG_TUSB_MCU == OPT_MCU_KINETIS_K64) + uint32_t clk_recover_irc_en; + uint32_t clk_recover_ctrl; + + clk_recover_irc_en = KHCI->CLK_RECOVER_IRC_EN; + clk_recover_ctrl = KHCI->CLK_RECOVER_CTRL; + + KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK; + while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK); + + KHCI->CLK_RECOVER_IRC_EN = clk_recover_irc_en; + KHCI->CLK_RECOVER_CTRL |= clk_recover_ctrl; +#else KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK; while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK); +#endif tu_memclr(&_dcd, sizeof(_dcd)); KHCI->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */ diff --git a/src/tusb_option.h b/src/tusb_option.h index c792efe6a..bbaa2a53a 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -121,6 +121,7 @@ #define OPT_MCU_KINETIS_KL 1200 ///< NXP KL series #define OPT_MCU_KINETIS_K32L 1201 ///< NXP K32L series #define OPT_MCU_KINETIS_K32 1201 ///< Alias to K32L +#define OPT_MCU_KINETIS_K64 1202 ///< NXP K64 series #define OPT_MCU_MKL25ZXX 1200 ///< Alias to KL (obsolete) #define OPT_MCU_K32L2BXX 1201 ///< Alias to K32 (obsolete) -- cgit v1.3.1 From ef49b93532a7360703ae87d36cf463169f86f20b Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 24 Jul 2023 15:46:21 +0700 Subject: rename CFG_TUSB_MEM_SECTION to CFG_TUD_MEM_SECTION in device stack CFG_TUD_MEM_SECTION is default to CFG_TUSB_MEM_SECTION --- hw/bsp/lpc40/family.cmake | 1 + hw/bsp/lpc40/family.mk | 3 +- lib/networking/rndis_reports.c | 2 +- src/class/audio/audio_device.c | 44 ++++++++++++------------ src/class/bth/bth_device.c | 2 +- src/class/cdc/cdc_device.c | 2 +- src/class/dfu/dfu_device.c | 2 +- src/class/hid/hid_device.c | 2 +- src/class/midi/midi_device.c | 2 +- src/class/msc/msc_device.c | 4 +-- src/class/net/ecm_rndis_device.c | 12 +++---- src/class/net/ncm_device.c | 6 ++-- src/class/usbtmc/usbtmc_device.c | 2 +- src/class/vendor/vendor_device.c | 2 +- src/class/video/video_device.c | 4 +-- src/device/usbd_control.c | 2 +- src/portable/bridgetek/ft9xx/dcd_ft9xx.c | 2 +- src/portable/chipidea/ci_fs/dcd_ci_fs.c | 2 +- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 2 +- src/portable/microchip/pic/dcd_pic.c | 2 +- src/portable/microchip/samx7x/dcd_samx7x.c | 2 +- src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c | 2 +- src/portable/nxp/khci/dcd_khci.c | 2 +- src/portable/nxp/lpc17_40/dcd_lpc17_40.c | 2 +- src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 6 ++-- src/tusb_option.h | 42 ++++++---------------- 26 files changed, 68 insertions(+), 88 deletions(-) (limited to 'src') diff --git a/hw/bsp/lpc40/family.cmake b/hw/bsp/lpc40/family.cmake index 03caa4385..54410e1a7 100644 --- a/hw/bsp/lpc40/family.cmake +++ b/hw/bsp/lpc40/family.cmake @@ -38,6 +38,7 @@ function(add_board_target BOARD_TARGET) target_compile_definitions(${BOARD_TARGET} PUBLIC __USE_LPCOPEN CORE_M4 + CFG_TUSB_MEM_SECTION=__attribute__\(\(section\(\".data.$RAM2\"\)\)\) ) target_include_directories(${BOARD_TARGET} PUBLIC ${SDK_DIR}/inc diff --git a/hw/bsp/lpc40/family.mk b/hw/bsp/lpc40/family.mk index 47d25b885..0fc7095f5 100644 --- a/hw/bsp/lpc40/family.mk +++ b/hw/bsp/lpc40/family.mk @@ -9,8 +9,7 @@ CFLAGS += \ -nostdlib \ -DCORE_M4 \ -D__USE_LPCOPEN \ - -DCFG_TUD_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \ - -DCFG_TUH_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \ + -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \ -DCFG_TUSB_MCU=OPT_MCU_LPC40XX # mcu driver cause following warnings diff --git a/lib/networking/rndis_reports.c b/lib/networking/rndis_reports.c index cc14f174c..60afb8615 100644 --- a/lib/networking/rndis_reports.c +++ b/lib/networking/rndis_reports.c @@ -43,7 +43,7 @@ static usb_eth_stat_t usb_eth_stat = { 0, 0, 0, 0 }; static uint32_t oid_packet_filter = 0x0000000; static rndis_state_t rndis_state; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t ndis_report[8] = { 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }; +CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t ndis_report[8] = { 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }; static const uint32_t OIDSupportedList[] = { diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index e5dbe988a..1a7ce7870 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -113,21 +113,21 @@ // EP IN software buffers and mutexes #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ]; #if CFG_FIFO_MUTEX osal_mutex_def_t ep_in_ff_mutex_wr_1; // No need for read mutex as only USB driver reads from FIFO #endif #endif // CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ]; #if CFG_FIFO_MUTEX osal_mutex_def_t ep_in_ff_mutex_wr_2; // No need for read mutex as only USB driver reads from FIFO #endif #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ]; #if CFG_FIFO_MUTEX osal_mutex_def_t ep_in_ff_mutex_wr_3; // No need for read mutex as only USB driver reads from FIFO #endif @@ -139,36 +139,36 @@ // - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into #if CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING) #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX]; #endif #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX]; #endif #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX]; #endif #endif // CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING) // EP OUT software buffers and mutexes #if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ]; #if CFG_FIFO_MUTEX osal_mutex_def_t ep_out_ff_mutex_rd_1; // No need for write mutex as only USB driver writes into FIFO #endif #endif // CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ]; #if CFG_FIFO_MUTEX osal_mutex_def_t ep_out_ff_mutex_rd_2; // No need for write mutex as only USB driver writes into FIFO #endif #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ]; #if CFG_FIFO_MUTEX osal_mutex_def_t ep_out_ff_mutex_rd_3; // No need for write mutex as only USB driver writes into FIFO #endif @@ -180,27 +180,27 @@ // - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into #if CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING) #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX]; #endif #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX]; #endif #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX]; #endif #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING) // Control buffers -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_1[CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ]; +CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_1[CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ]; #if CFG_TUD_AUDIO > 1 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_2[CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ]; +CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_2[CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ]; #endif #if CFG_TUD_AUDIO > 2 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ]; +CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ]; #endif // Active alternate setting of interfaces @@ -217,7 +217,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT]; // Software encoding/decoding support FIFOs #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ]; tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; #if CFG_FIFO_MUTEX osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO @@ -225,7 +225,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT]; #endif #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ]; tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; #if CFG_FIFO_MUTEX osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO @@ -233,7 +233,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT]; #endif #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ]; tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; #if CFG_FIFO_MUTEX osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO @@ -243,7 +243,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT]; #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING #if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ]; tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; #if CFG_FIFO_MUTEX osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO @@ -251,7 +251,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT]; #endif #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ]; tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; #if CFG_FIFO_MUTEX osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO @@ -259,7 +259,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT]; #endif #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0 - CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ]; + CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ]; tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; #if CFG_FIFO_MUTEX osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO @@ -416,7 +416,7 @@ typedef struct //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION audiod_function_t _audiod_fct[CFG_TUD_AUDIO]; +CFG_TUD_MEM_SECTION audiod_function_t _audiod_fct[CFG_TUD_AUDIO]; #if CFG_TUD_AUDIO_ENABLE_EP_OUT static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t n_bytes_received); diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c index f96bb3552..c5c74d26a 100755 --- a/src/class/bth/bth_device.c +++ b/src/class/bth/bth_device.c @@ -55,7 +55,7 @@ typedef struct //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION btd_interface_t _btd_itf; +CFG_TUD_MEM_SECTION btd_interface_t _btd_itf; static bool bt_tx_data(uint8_t ep, void *data, uint16_t len) { diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index 5adce521d..f658df4d0 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -76,7 +76,7 @@ typedef struct //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION tu_static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC]; +CFG_TUD_MEM_SECTION tu_static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC]; static bool _prep_out_transaction (cdcd_interface_t* p_cdc) { diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c index 464c4bd6b..bffdb8376 100644 --- a/src/class/dfu/dfu_device.c +++ b/src/class/dfu/dfu_device.c @@ -56,7 +56,7 @@ typedef struct } dfu_state_ctx_t; // Only a single dfu state is allowed -CFG_TUSB_MEM_SECTION tu_static dfu_state_ctx_t _dfu_ctx; +CFG_TUD_MEM_SECTION tu_static dfu_state_ctx_t _dfu_ctx; static void reset_state(void) { diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c index 9240fe2ca..5637ea6b4 100644 --- a/src/class/hid/hid_device.c +++ b/src/class/hid/hid_device.c @@ -58,7 +58,7 @@ typedef struct tusb_hid_descriptor_hid_t const * hid_descriptor; } hidd_interface_t; -CFG_TUSB_MEM_SECTION tu_static hidd_interface_t _hidd_itf[CFG_TUD_HID]; +CFG_TUD_MEM_SECTION tu_static hidd_interface_t _hidd_itf[CFG_TUD_HID]; /*------------- Helpers -------------*/ static inline uint8_t get_index_by_itfnum(uint8_t itf_num) diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c index e3e7826da..052372a93 100644 --- a/src/class/midi/midi_device.c +++ b/src/class/midi/midi_device.c @@ -82,7 +82,7 @@ typedef struct //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION midid_interface_t _midid_itf[CFG_TUD_MIDI]; +CFG_TUD_MEM_SECTION midid_interface_t _midid_itf[CFG_TUD_MIDI]; bool tud_midi_n_mounted (uint8_t itf) { diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index a409c4e27..a602e9672 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -74,8 +74,8 @@ typedef struct uint8_t add_sense_qualifier; }mscd_interface_t; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static mscd_interface_t _mscd_itf; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE]; +CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static mscd_interface_t _mscd_itf; +CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE]; //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c index 8ac7cbd01..762425732 100644 --- a/src/class/net/ecm_rndis_device.c +++ b/src/class/net/ecm_rndis_device.c @@ -61,10 +61,10 @@ typedef struct #define CFG_TUD_NET_PACKET_PREFIX_LEN sizeof(rndis_data_packet_t) #define CFG_TUD_NET_PACKET_SUFFIX_LEN 0 -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static +CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static +CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; struct ecm_notify_struct @@ -94,8 +94,8 @@ tu_static const struct ecm_notify_struct ecm_notify_csc = .uplink = 9728000, }; -// TODO remove CFG_TUSB_MEM_SECTION, control internal buffer is already in this special section -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static union +// TODO remove CFG_TUD_MEM_SECTION, control internal buffer is already in this special section +CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static union { uint8_t rndis_buf[120]; struct ecm_notify_struct ecm_buf; @@ -104,8 +104,8 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static union //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -// TODO remove CFG_TUSB_MEM_SECTION -CFG_TUSB_MEM_SECTION tu_static netd_interface_t _netd_itf; +// TODO remove CFG_TUD_MEM_SECTION +CFG_TUD_MEM_SECTION tu_static netd_interface_t _netd_itf; tu_static bool can_xmit; diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c index 9e9580249..611dc3348 100644 --- a/src/class/net/ncm_device.c +++ b/src/class/net/ncm_device.c @@ -130,7 +130,7 @@ typedef struct // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_parameters = { +CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_parameters = { .wLength = sizeof(ntb_parameters_t), .bmNtbFormatsSupported = 0x01, .dwNtbInMaxSize = CFG_TUD_NCM_IN_NTB_MAX_SIZE, @@ -145,9 +145,9 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_par .wNtbOutMaxDatagrams = 0 }; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static transmit_ntb_t transmit_ntb[2]; +CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static transmit_ntb_t transmit_ntb[2]; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE]; +CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE]; tu_static ncm_interface_t ncm_interface; diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index 4e320a778..573654d58 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -143,7 +143,7 @@ typedef struct usbtmc_capabilities_specific_t const * capabilities; } usbtmc_interface_state_t; -CFG_TUSB_MEM_SECTION tu_static usbtmc_interface_state_t usbtmc_state = +CFG_TUD_MEM_SECTION tu_static usbtmc_interface_state_t usbtmc_state = { .itf_id = 0xFF, }; diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index 93596ee33..389a29696 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -59,7 +59,7 @@ typedef struct CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_VENDOR_EPSIZE]; } vendord_interface_t; -CFG_TUSB_MEM_SECTION tu_static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR]; +CFG_TUD_MEM_SECTION tu_static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR]; #define ITF_MEM_RESET_SIZE offsetof(vendord_interface_t, rx_ff) diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 91f452afc..e6fadf41b 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -130,8 +130,8 @@ typedef struct TU_ATTR_PACKED { //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUSB_MEM_SECTION tu_static videod_interface_t _videod_itf[CFG_TUD_VIDEO]; -CFG_TUSB_MEM_SECTION tu_static videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING]; +CFG_TUD_MEM_SECTION tu_static videod_interface_t _videod_itf[CFG_TUD_VIDEO]; +CFG_TUD_MEM_SECTION tu_static videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING]; tu_static uint8_t const _cap_get = 0x1u; /* support for GET */ tu_static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */ diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index c580e6ecf..76d062e40 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -55,7 +55,7 @@ typedef struct tu_static usbd_control_xfer_t _ctrl_xfer; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN +CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE]; //--------------------------------------------------------------------+ diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c index 95dfda49c..f02415904 100644 --- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c +++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c @@ -51,7 +51,7 @@ extern int8_t board_ft9xx_vbus(void); extern int board_uart_write(void const *buf, int len); // Static array to store an incoming SETUP request for processing by tinyusb. -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN +CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _ft9xx_setup_packet[8]; struct ft9xx_xfer_state diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c index 37265df8b..9327e09d8 100644 --- a/src/portable/chipidea/ci_fs/dcd_ci_fs.c +++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c @@ -116,7 +116,7 @@ typedef struct // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ // BDT(Buffer Descriptor Table) must be 256-byte aligned -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd; +CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd; TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" ); diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index f50550d33..f9ec666e5 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -175,7 +175,7 @@ typedef struct { dcd_qtd_t qtd[TUP_DCD_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(32); }dcd_data_t; -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048) +CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(2048) static dcd_data_t _dcd_data; //--------------------------------------------------------------------+ diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c index 6986c8317..ccc27c3c9 100644 --- a/src/portable/microchip/pic/dcd_pic.c +++ b/src/portable/microchip/pic/dcd_pic.c @@ -189,7 +189,7 @@ typedef struct // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ // BDT(Buffer Descriptor Table) must be 256-byte aligned -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) volatile static dcd_data_t _dcd; +CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(512) volatile static dcd_data_t _dcd; #if TU_PIC_INT_SIZE == 4 TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" ); diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c index 2bbb345d6..9586df84d 100644 --- a/src/portable/microchip/samx7x/dcd_samx7x.c +++ b/src/portable/microchip/samx7x/dcd_samx7x.c @@ -77,7 +77,7 @@ static tusb_speed_t get_speed(void); static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix); // DMA descriptors shouldn't be placed in ITCM ! -CFG_TUSB_MEM_SECTION static dma_desc_t dma_desc[6]; +CFG_TUD_MEM_SECTION static dma_desc_t dma_desc[6]; static xfer_ctl_t xfer_status[EP_MAX]; diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c index 39b09db68..c3d0c7297 100644 --- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c +++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c @@ -110,7 +110,7 @@ typedef struct // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ // BDT(Buffer Descriptor Table) must be 256-byte aligned -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd; +CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd; TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" ); diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 52f4145f2..5c65ea33d 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -114,7 +114,7 @@ typedef struct // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ // BDT(Buffer Descriptor Table) must be 256-byte aligned -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd; +CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd; TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" ); diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c index 86149afd8..b880c2870 100644 --- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c +++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c @@ -92,7 +92,7 @@ typedef struct } dcd_data_t; -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(128) static dcd_data_t _dcd; +CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(128) static dcd_data_t _dcd; //--------------------------------------------------------------------+ diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c index 5368ef868..7ca698a93 100644 --- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c +++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c @@ -176,11 +176,11 @@ typedef struct // EP list must be 256-byte aligned // Some MCU controller may require this variable to be placed in specific SRAM region. // For example: LPC55s69 port1 Highspeed must be USB_RAM (0x40100000) -// Use CFG_TUSB_MEM_SECTION to place it accordingly. -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd; +// Use CFG_TUD_MEM_SECTION to place it accordingly. +CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd; // Dummy buffer to fix ZLPs overwriting the buffer (probably an USB/DMA controller bug) -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8]; +CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8]; //--------------------------------------------------------------------+ // Multiple Controllers diff --git a/src/tusb_option.h b/src/tusb_option.h index c792efe6a..7a4cfe51c 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -295,15 +295,14 @@ #define CFG_TUSB_DEBUG 0 #endif -// TODO MEM_SECTION can be different for host and device controller -// should use CFG_TUD_MEM_SECTION, CFG_TUH_MEM_SECTION +// Memory section for placing buffer used for usb transferring. If MEM_SECTION is different for +// host and device use: CFG_TUD_MEM_SECTION, CFG_TUH_MEM_SECTION instead #ifndef CFG_TUSB_MEM_SECTION #define CFG_TUSB_MEM_SECTION #endif -// alignment requirement of buffer used for endpoint transferring -// TODO MEM_ALIGN can be different for host and device controller -// should use CFG_TUD_MEM_ALIGN, CFG_TUH_MEM_ALIGN +// Alignment requirement of buffer used for usb transferring. if MEM_ALIGN is different for +// host and device controller use: CFG_TUD_MEM_ALIGN, CFG_TUH_MEM_ALIGN instead #ifndef CFG_TUSB_MEM_ALIGN #define CFG_TUSB_MEM_ALIGN TU_ATTR_ALIGNED(4) #endif @@ -321,24 +320,14 @@ // Device Options (Default) //-------------------------------------------------------------------- -// Attribute to place data in accessible RAM for device controller -// default to CFG_TUSB_MEM_SECTION for backward-compatible +// Attribute to place data in accessible RAM for device controller (default: CFG_TUSB_MEM_SECTION) #ifndef CFG_TUD_MEM_SECTION - #ifdef CFG_TUSB_MEM_SECTION - #define CFG_TUD_MEM_SECTION CFG_TUSB_MEM_SECTION - #else - #define CFG_TUD_MEM_SECTION - #endif + #define CFG_TUD_MEM_SECTION CFG_TUSB_MEM_SECTION #endif -// Attribute to align memory for device controller -// default to CFG_TUSB_MEM_ALIGN for backward-compatible +// Attribute to align memory for device controller (default: CFG_TUSB_MEM_ALIGN) #ifndef CFG_TUD_MEM_ALIGN - #ifdef CFG_TUSB_MEM_ALIGN - #define CFG_TUD_MEM_ALIGN CFG_TUSB_MEM_ALIGN - #else - #define CFG_TUD_MEM_ALIGN TU_ATTR_ALIGNED(4) - #endif + #define CFG_TUD_MEM_ALIGN CFG_TUSB_MEM_ALIGN #endif #ifndef CFG_TUD_ENDPOINT0_SIZE @@ -419,23 +408,14 @@ #endif #endif // CFG_TUH_ENABLED -// Attribute to place data in accessible RAM for host controller -// default to CFG_TUSB_MEM_SECTION for backward-compatible +// Attribute to place data in accessible RAM for host controller (default: CFG_TUSB_MEM_SECTION) #ifndef CFG_TUH_MEM_SECTION - #ifdef CFG_TUSB_MEM_SECTION - #define CFG_TUH_MEM_SECTION CFG_TUSB_MEM_SECTION - #else - #define CFG_TUH_MEM_SECTION - #endif + #define CFG_TUH_MEM_SECTION CFG_TUSB_MEM_SECTION #endif // Attribute to align memory for host controller #ifndef CFG_TUH_MEM_ALIGN - #ifdef CFG_TUSB_MEM_ALIGN - #define CFG_TUH_MEM_ALIGN CFG_TUSB_MEM_ALIGN - #else - #define CFG_TUH_MEM_ALIGN TU_ATTR_ALIGNED(4) - #endif + #define CFG_TUH_MEM_ALIGN CFG_TUSB_MEM_ALIGN #endif //------------- CLASS -------------// -- cgit v1.3.1 From 14a7379799418c6e8ffb7231ee1703a0f95665da Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 24 Jul 2023 16:54:02 +0700 Subject: fix ohci warnings, and add freertosconfig for lpc4088 --- hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h | 165 +++++++++++++++++++++++++++ hw/bsp/lpc40/family.cmake | 2 + src/portable/ohci/ohci.c | 25 ++-- 3 files changed, 182 insertions(+), 10 deletions(-) create mode 100644 hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h (limited to 'src') diff --git a/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..96611ca1c --- /dev/null +++ b/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,165 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "chip.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 2 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* Define to trap errors during development. */ +// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) + #define configASSERT(_exp) \ + do {\ + if ( !(_exp) ) { \ + volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ + if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \ + taskDISABLE_INTERRUPTS(); \ + __asm("BKPT #0\n"); \ + }\ + }\ + } while(0) +#else + #define configASSERT( x ) +#endif + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS 5 + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<is_interrupt_xfer = (xfer_type == TUSB_XFER_INTERRUPT ? 1 : 0); } -static void gtd_init(ohci_gtd_t* p_td, uint8_t* data_ptr, uint16_t total_bytes) -{ +static void gtd_init(ohci_gtd_t *p_td, uint8_t *data_ptr, uint16_t total_bytes) { tu_memclr(p_td, sizeof(ohci_gtd_t)); - p_td->used = 1; - p_td->expected_bytes = total_bytes; + p_td->used = 1; + p_td->expected_bytes = total_bytes; + + p_td->buffer_rounding = 1; // less than queued length is not a error + p_td->delay_interrupt = OHCI_INT_ON_COMPLETE_NO; + p_td->condition_code = OHCI_CCODE_NOT_ACCESSED; - p_td->buffer_rounding = 1; // less than queued length is not a error - p_td->delay_interrupt = OHCI_INT_ON_COMPLETE_NO; - p_td->condition_code = OHCI_CCODE_NOT_ACCESSED; + uint8_t *cbp = (uint8_t *) _phys_addr(data_ptr); - p_td->current_buffer_pointer = _phys_addr(data_ptr); - p_td->buffer_end = total_bytes ? (_phys_addr(data_ptr + total_bytes - 1)) : (uint8_t *)p_td->current_buffer_pointer; + p_td->current_buffer_pointer = cbp; + if ( total_bytes ) { + p_td->buffer_end = _phys_addr(data_ptr + total_bytes - 1); + } else { + p_td->buffer_end = cbp; + } } static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr) @@ -487,7 +492,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet ohci_ed_t* ed = &ohci_data.control[dev_addr].ed; ohci_gtd_t *qtd = &ohci_data.control[dev_addr].gtd; - gtd_init(qtd, (uint8_t*) setup_packet, 8); + gtd_init(qtd, (uint8_t*)(uintptr_t) setup_packet, 8); qtd->index = dev_addr; qtd->pid = PID_SETUP; qtd->data_toggle = GTD_DT_DATA0; -- cgit v1.3.1 From d2542560470de242dd8988d0b3c10d7df0496bb0 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 24 Jul 2023 17:54:24 +0700 Subject: change dcache clean/invalidate return type to bool add tu_assert() check for aligned 32byte address for imxrt --- src/common/tusb_common.h | 13 +++++++------ src/host/hcd.h | 8 ++++---- src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 15 +++++++++------ src/portable/chipidea/ci_hs/hcd_ci_hs.c | 12 ++++++------ src/portable/ehci/ehci.c | 9 ++++++--- 5 files changed, 32 insertions(+), 25 deletions(-) (limited to 'src') diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 957491aa9..bae583c06 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -99,10 +99,9 @@ TU_ATTR_WEAK extern void* tusb_app_phys_to_virt(void *phys_addr); #define tu_varclr(_var) tu_memclr(_var, sizeof(*(_var))) // This is a backport of memset_s from c11 -TU_ATTR_ALWAYS_INLINE static inline int tu_memset_s(void *dest, size_t destsz, int ch, size_t count) -{ +TU_ATTR_ALWAYS_INLINE static inline int tu_memset_s(void *dest, size_t destsz, int ch, size_t count) { // TODO may check if desst and src is not NULL - if (count > destsz) { + if ( count > destsz ) { return -1; } memset(dest, ch, count); @@ -110,10 +109,9 @@ TU_ATTR_ALWAYS_INLINE static inline int tu_memset_s(void *dest, size_t destsz, i } // This is a backport of memcpy_s from c11 -TU_ATTR_ALWAYS_INLINE static inline int tu_memcpy_s(void *dest, size_t destsz, const void * src, size_t count ) -{ +TU_ATTR_ALWAYS_INLINE static inline int tu_memcpy_s(void *dest, size_t destsz, const void *src, size_t count) { // TODO may check if desst and src is not NULL - if (count > destsz) { + if ( count > destsz ) { return -1; } memcpy(dest, src, count); @@ -169,6 +167,9 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align32 (uint32_t value) { retur TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4k (uint32_t value) { return (value & 0xFFFFF000UL); } TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_offset4k(uint32_t value) { return (value & 0xFFFUL); } +TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned32(uint32_t value) { return (value & 0x1FUL) == 0; } +TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned64(uint64_t value) { return (value & 0x3FUL) == 0; } + //------------- Mathematics -------------// TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return (v + d -1)/d; } diff --git a/src/host/hcd.h b/src/host/hcd.h index 3355c18b2..52fcc834e 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -104,21 +104,21 @@ typedef struct uint8_t speed; } hcd_devtree_info_t; -//--------------------------------------------------------------------+ +//-------------------------------------------------------------- // Memory API //--------------------------------------------------------------------+ // clean/flush data cache: write cache -> memory. // Required before an DMA TX transfer to make sure data is in memory -void hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; // invalidate data cache: mark cache as invalid, next read will read from memory // Required BOTH before and after an DMA RX transfer -void hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; // clean and invalidate data cache // Required before an DMA transfer where memory is both read/write by DMA -void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; //--------------------------------------------------------------------+ // Controller API diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h index 96f0ba766..c59c107ff 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h +++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h @@ -68,31 +68,34 @@ TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uintptr_t addr) { return !(0x20000000 <= addr && addr < 0x20100000); } -TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean(void const* addr, uint32_t data_size) { +TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean(void const* addr, uint32_t data_size) { const uintptr_t addr32 = (uintptr_t) addr; if (imxrt_is_cache_mem(addr32)) { + TU_ASSERT(tu_is_aligned32(addr32)); SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size); } + return true; } -TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_invalidate(void const* addr, uint32_t data_size) { +TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_invalidate(void const* addr, uint32_t data_size) { const uintptr_t addr32 = (uintptr_t) addr; if (imxrt_is_cache_mem(addr32)) { // Invalidating does not push cached changes back to RAM so we need to be // *very* careful when we do it. If we're not aligned, then we risk resetting // values back to their RAM state. - // if (addr32 % 32 != 0) { - // TU_BREAKPOINT(); - // } + TU_ASSERT(tu_is_aligned32(addr32)); SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size); } + return true; } -TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean_invalidate(void const* addr, uint32_t data_size) { +TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean_invalidate(void const* addr, uint32_t data_size) { const uintptr_t addr32 = (uintptr_t) addr; if (imxrt_is_cache_mem(addr32)) { + TU_ASSERT(tu_is_aligned32(addr32)); SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size); } + return true; } #endif diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index 56167b8f6..6ee91e18e 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -41,16 +41,16 @@ #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX #include "ci_hs_imxrt.h" - void hcd_dcache_clean(void const* addr, uint32_t data_size) { - imxrt_dcache_clean(addr, data_size); + bool hcd_dcache_clean(void const* addr, uint32_t data_size) { + return imxrt_dcache_clean(addr, data_size); } - void hcd_dcache_invalidate(void const* addr, uint32_t data_size) { - imxrt_dcache_invalidate(addr, data_size); + bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) { + return imxrt_dcache_invalidate(addr, data_size); } - void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { - imxrt_dcache_clean_invalidate(addr, data_size); + bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { + return imxrt_dcache_clean_invalidate(addr, data_size); } #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 38711e382..6dfaab2a2 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -162,16 +162,19 @@ static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes) static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type); static inline ehci_link_t* list_next (ehci_link_t const *p_link); -TU_ATTR_WEAK void hcd_dcache_clean(void const* addr, uint32_t data_size) { +TU_ATTR_WEAK bool hcd_dcache_clean(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; + return true; } -TU_ATTR_WEAK void hcd_dcache_invalidate(void const* addr, uint32_t data_size) { +TU_ATTR_WEAK bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; + return true; } -TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { +TU_ATTR_WEAK bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; + return true; } //--------------------------------------------------------------------+ -- cgit v1.3.1 From fd29fd923a0a64be96fe4bdfa2a5fa9f184ea6c7 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 24 Jul 2023 20:53:44 +0700 Subject: clean up --- src/host/hcd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/host/hcd.h b/src/host/hcd.h index 52fcc834e..a98286053 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -104,7 +104,7 @@ typedef struct uint8_t speed; } hcd_devtree_info_t; -//-------------------------------------------------------------- +//--------------------------------------------------------------------+ // Memory API //--------------------------------------------------------------------+ -- cgit v1.3.1 From f295aaf1851eb270070af7292d1f100f7172daf4 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 24 Jul 2023 11:55:54 +0700 Subject: add hcd abort xfer for rp2040 pio usb --- hw/bsp/rp2040/board.h | 12 ++++++------ src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 7 ++----- tools/get_deps.py | 2 +- 3 files changed, 9 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h index 934e1c7ae..063c9580e 100644 --- a/hw/bsp/rp2040/board.h +++ b/hw/bsp/rp2040/board.h @@ -54,19 +54,19 @@ // default to pin on Adafruit Feather rp2040 USB Host or Tester if defined //--------------------------------------------------------------------+ -// #define USE_ADAFRUIT_RP2040_TESTER -#ifdef USE_ADAFRUIT_RP2040_TESTER -#define PICO_DEFAULT_PIO_USB_DP_PIN 20 -#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 22 +// #define USE_ADAFRUIT_FEATHER_RP2040_USBHOST +#ifdef USE_ADAFRUIT_FEATHER_RP2040_USBHOST +#define PICO_DEFAULT_PIO_USB_DP_PIN 16 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 18 #endif #ifndef PICO_DEFAULT_PIO_USB_DP_PIN -#define PICO_DEFAULT_PIO_USB_DP_PIN 16 +#define PICO_DEFAULT_PIO_USB_DP_PIN 20 #endif // VBUS enable pin and its active state #ifndef PICO_DEFAULT_PIO_USB_VBUSEN_PIN -#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 18 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 22 #endif // VBUS enable state diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c index fa285327c..bb41ad638 100644 --- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c @@ -139,11 +139,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * } bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { - (void) rhport; - (void) dev_addr; - (void) ep_addr; - // TODO not implemented yet - return false; + uint8_t const pio_rhport = RHPORT_PIO(rhport); + return pio_usb_host_endpoint_abort_transfer(pio_rhport, dev_addr, ep_addr); } bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) diff --git a/tools/get_deps.py b/tools/get_deps.py index 9b89c5e4c..d6505a1d9 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -54,7 +54,7 @@ deps_optional = { '950819b7de9b32f92c3edf396bc5ffb8d66e7009', 'kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'], 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git', - '58879cfa0eca5725d8db6443ec17f8896a321042', + 'd00a10a8c425d0d40f81b87169102944b01f3bb3', 'rp2040'], 'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git', '8dc14709f2a6518b43f71efad70d900b7718d9f1', -- cgit v1.3.1 From ef69da054e4d373636818a52df4e3433152fa3bf Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 25 Jul 2023 12:03:54 +0700 Subject: use standard EHCI USB INT instead of chipidea async/period interrupt to be compatible with other EHCI implementation --- src/portable/ehci/ehci.c | 24 ++++++++---------------- src/portable/ehci/ehci.h | 6 +----- 2 files changed, 9 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 241393a39..a9e184f22 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -307,8 +307,8 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) regs->status = (EHCI_INT_MASK_ALL & ~EHCI_INT_MASK_PORT_CHANGE); // Enable interrupts - regs->inten = EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE | EHCI_INT_MASK_ASYNC_ADVANCE | - EHCI_INT_MASK_NXP_PERIODIC | EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_FRAMELIST_ROLLOVER; + regs->inten = EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE | + EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_FRAMELIST_ROLLOVER; //------------- Asynchronous List -------------// ehci_qhd_t * const async_head = list_get_async_head(rhport); @@ -768,28 +768,20 @@ void hcd_int_handler(uint8_t rhport) regs->status = EHCI_INT_MASK_PORT_CHANGE; // Acknowledge } + // A USB transfer is completed with error if (int_status & EHCI_INT_MASK_ERROR) { xfer_error_isr(rhport); regs->status = EHCI_INT_MASK_ERROR; // Acknowledge } - //------------- some QTD/SITD/ITD with IOC set is completed -------------// - if (int_status & EHCI_INT_MASK_NXP_ASYNC) { - async_list_xfer_complete_isr(list_get_async_head(rhport)); - regs->status = EHCI_INT_MASK_NXP_ASYNC; // Acknowledge - } - - if (int_status & EHCI_INT_MASK_NXP_PERIODIC) - { - for (uint32_t i=1; i <= FRAMELIST_SIZE; i *= 2) - { + // A USB transfer is completed + if (int_status & EHCI_INT_MASK_USB) { + for ( uint32_t i = 1; i <= FRAMELIST_SIZE; i *= 2 ) { period_list_xfer_complete_isr(rhport, i); } - regs->status = EHCI_INT_MASK_NXP_PERIODIC; // Acknowledge - } - if (int_status & EHCI_INT_MASK_USB) { - // TODO standard EHCI xfer complete + async_list_xfer_complete_isr(list_get_async_head(rhport)); + regs->status = EHCI_INT_MASK_USB; // Acknowledge } diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h index 05de80539..457adc1d3 100644 --- a/src/portable/ehci/ehci.h +++ b/src/portable/ehci/ehci.h @@ -278,14 +278,10 @@ enum { EHCI_INT_MASK_PERIODIC_SCHED_STATUS = TU_BIT(14), EHCI_INT_MASK_ASYNC_SCHED_STATUS = TU_BIT(15), - EHCI_INT_MASK_NXP_ASYNC = TU_BIT(18), - EHCI_INT_MASK_NXP_PERIODIC = TU_BIT(19), - EHCI_INT_MASK_ALL = EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE | EHCI_INT_MASK_FRAMELIST_ROLLOVER | EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR | - EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_SOF | - EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_NXP_PERIODIC + EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_SOF }; enum { -- cgit v1.3.1 From dc74e634f93962512229ba7d4e14467c16125c0d Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 25 Jul 2023 12:35:40 +0700 Subject: fix unaligned hub status_change --- src/host/hub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/host/hub.c b/src/host/hub.c index 182bd6ce8..16dd534d2 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -45,8 +45,8 @@ typedef struct uint8_t itf_num; uint8_t ep_in; uint8_t port_count; - uint8_t status_change; // data from status change interrupt endpoint + CFG_TUH_MEM_ALIGN uint8_t status_change; CFG_TUH_MEM_ALIGN hub_port_status_response_t port_status; CFG_TUH_MEM_ALIGN hub_status_response_t hub_status; } hub_interface_t; -- cgit v1.3.1 From 4deea875793ce78a24b069491bb83e59e310c476 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 25 Jul 2023 15:07:21 +0700 Subject: improve processing usb complete and error isr. also merge them together --- hw/bsp/imxrt/family.cmake | 120 ++++++++++++------------ src/CMakeLists.txt | 1 + src/portable/ehci/ehci.c | 228 ++++++++++++---------------------------------- 3 files changed, 120 insertions(+), 229 deletions(-) (limited to 'src') diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index f1c5b0ab1..96ed4b030 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -22,69 +22,71 @@ set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "") #------------------------------------ # only need to be built ONCE for all examples function(add_board_target BOARD_TARGET) - if (NOT TARGET ${BOARD_TARGET}) - add_library(${BOARD_TARGET} STATIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/clock_config.c - #${SDK_DIR}/drivers/adc_12b1msps_sar/fsl_adc.c - ${SDK_DIR}/drivers/common/fsl_common.c - ${SDK_DIR}/drivers/igpio/fsl_gpio.c - ${SDK_DIR}/drivers/lpspi/fsl_lpspi.c - ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c - ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c - ${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c - ) - target_compile_definitions(${BOARD_TARGET} PUBLIC - __ARMVFP__=0 - __ARMFPV5__=0 - XIP_EXTERNAL_FLASH=1 - XIP_BOOT_HEADER_ENABLE=1 - ) - target_include_directories(${BOARD_TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board - ${CMSIS_DIR}/CMSIS/Core/Include - ${SDK_DIR}/devices/${MCU_VARIANT} - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers - #${SDK_DIR}/drivers/adc_12b1msps_sar - ${SDK_DIR}/drivers/common - ${SDK_DIR}/drivers/igpio - ${SDK_DIR}/drivers/lpspi - ${SDK_DIR}/drivers/lpuart - ) + if (TARGET ${BOARD_TARGET}) + return() + endif () - update_board(${BOARD_TARGET}) + add_library(${BOARD_TARGET} STATIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/clock_config.c + #${SDK_DIR}/drivers/adc_12b1msps_sar/fsl_adc.c + ${SDK_DIR}/drivers/common/fsl_common.c + ${SDK_DIR}/drivers/igpio/fsl_gpio.c + ${SDK_DIR}/drivers/lpspi/fsl_lpspi.c + ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c + ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c + ${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c + ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + __ARMVFP__=0 + __ARMFPV5__=0 + XIP_EXTERNAL_FLASH=1 + XIP_BOOT_HEADER_ENABLE=1 + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board + ${CMSIS_DIR}/CMSIS/Core/Include + ${SDK_DIR}/devices/${MCU_VARIANT} + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers + #${SDK_DIR}/drivers/adc_12b1msps_sar + ${SDK_DIR}/drivers/common + ${SDK_DIR}/drivers/igpio + ${SDK_DIR}/drivers/lpspi + ${SDK_DIR}/drivers/lpuart + ) - # LD_FILE and STARTUP_FILE can be defined in board.cmake - if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID}) - set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld) - #set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld) - endif () + update_board(${BOARD_TARGET}) - if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID}) - set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S) - #set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S) - endif () + # LD_FILE and STARTUP_FILE can be defined in board.cmake + if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID}) + set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld) + #set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld) + endif () - target_sources(${BOARD_TARGET} PUBLIC - ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} - ) + if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID}) + set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S) + #set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S) + endif () - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_GNU}" - # nanolib - --specs=nosys.specs - --specs=nano.specs - # force linker to look for these symbols - -Wl,-uimage_vector_table - -Wl,-ug_boot_data - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--config=${LD_FILE_IAR}" - ) - endif () + target_sources(${BOARD_TARGET} PUBLIC + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + # nanolib + --specs=nosys.specs + --specs=nano.specs + # force linker to look for these symbols + -Wl,-uimage_vector_table + -Wl,-ug_boot_data + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) endif () endfunction() @@ -114,7 +116,7 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET}-tinyusb PRIVATE ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c ${TOP}/src/portable/ehci/ehci.c diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 8f7f38589..076e1e1eb 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -64,6 +64,7 @@ function(add_tinyusb TARGET) -Wnull-dereference -Wuninitialized -Wunused + -Wunused-function -Wreturn-type -Wredundant-decls ) diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index a9e184f22..b84de5191 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -314,11 +314,11 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) ehci_qhd_t * const async_head = list_get_async_head(rhport); tu_memclr(async_head, sizeof(ehci_qhd_t)); - async_head->next.address = (uint32_t) async_head; // circular list, next is itself - async_head->next.type = EHCI_QTYPE_QHD; - async_head->head_list_flag = 1; - async_head->qtd_overlay.halted = 1; // inactive most of time - async_head->qtd_overlay.next.terminate = 1; // TODO removed if verified + async_head->next.address = (uint32_t) async_head; // circular list, next is itself + async_head->next.type = EHCI_QTYPE_QHD; + async_head->head_list_flag = 1; + async_head->qtd_overlay.halted = 1; // inactive most of time + async_head->qtd_overlay.next.terminate = 1; // TODO removed if verified regs->async_list_addr = (uint32_t) async_head; @@ -533,70 +533,74 @@ void async_advance_isr(uint8_t rhport) } TU_ATTR_ALWAYS_INLINE static inline -void port_connect_status_change_isr(uint8_t rhport) -{ +void port_connect_status_change_isr(uint8_t rhport) { // NOTE There is an sequence plug->unplug->…..-> plug if device is powering with pre-plugged device - if (ehci_data.regs->portsc_bm.current_connect_status) - { + if ( ehci_data.regs->portsc_bm.current_connect_status ) { hcd_port_reset(rhport); hcd_event_device_attach(rhport, true); - }else // device unplugged + } else // device unplugged { hcd_event_device_remove(rhport, true); } } +// Check queue head for potential transfer complete (successful or error) TU_ATTR_ALWAYS_INLINE static inline void qhd_xfer_complete_isr(ehci_qhd_t * qhd) { - // examine TD attached to queue head - ehci_qtd_t * volatile qtd = qhd->attached_qtd; + hcd_dcache_invalidate(qhd, sizeof(ehci_qhd_t)); // HC may have updated the overlay + volatile ehci_qtd_t *qtd_overlay = &qhd->qtd_overlay; - if (qtd == NULL) { - return; // no TD attached - } + // process non-active (completed) QHD with attached (scheduled) TD + if ( !qtd_overlay->active && qhd->attached_qtd != NULL ) { + xfer_result_t xfer_result; - hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); + if ( qtd_overlay->halted ) { + if (qtd_overlay->xact_err || qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err) { + // Error count = 0 often occurs when device disconnected, or other bus-related error + xfer_result = XFER_RESULT_FAILED; + TU_LOG3(" QHD xfer err count: %d\n", qtd_overlay->err_count); + // TU_BREAKPOINT(); // TODO skip unplugged device + }else { + // no error bits are set, endpoint is halted due to STALL + xfer_result = XFER_RESULT_STALLED; + } + } else { + xfer_result = XFER_RESULT_SUCCESS; + } - // TD is still active, no need to process - if (qtd->active) { - return; - } + ehci_qtd_t * volatile qtd = qhd->attached_qtd; + hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); // HC may have written back TD - uint8_t dir = (qtd->pid == EHCI_PID_IN) ? 1 : 0; - uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes; + uint8_t const dir = (qtd->pid == EHCI_PID_IN) ? 1 : 0; + uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes; - // invalidate dcache if IN transfer - if (dir == 1 && qhd->attached_buffer != 0 && xferred_bytes > 0) { - hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes); - } + // invalidate dcache if IN transfer with data + if (dir == 1 && qhd->attached_buffer != 0 && xferred_bytes > 0) { + hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes); + } - // remove and free TD before invoking callback - qhd_remove_qtd(qhd); + // remove and free TD before invoking callback + qhd_remove_qtd(qhd); - // notify usbh - uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir); - hcd_event_xfer_complete(qhd->dev_addr, ep_addr, xferred_bytes, XFER_RESULT_SUCCESS, true); + // notify usbh + uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir); + hcd_event_xfer_complete(qhd->dev_addr, ep_addr, xferred_bytes, xfer_result, true); + } } TU_ATTR_ALWAYS_INLINE static inline -void async_list_xfer_complete_isr(ehci_qhd_t * const async_head) +void proccess_async_xfer_isr(ehci_qhd_t * const list_head) { - ehci_qhd_t *p_qhd = async_head; - do - { - hcd_dcache_invalidate(p_qhd, sizeof(ehci_qhd_t)); - - // halted or error is processed in error isr - if ( !p_qhd->qtd_overlay.halted ) { - qhd_xfer_complete_isr(p_qhd); - } + ehci_qhd_t *qhd = list_head; - p_qhd = qhd_next(p_qhd); - }while(p_qhd != async_head); // async list traversal, stop if loop around + do { + qhd_xfer_complete_isr(qhd); + qhd = qhd_next(qhd); + } while ( qhd != list_head ); // async list traversal, stop if loop around } TU_ATTR_ALWAYS_INLINE static inline -void period_list_xfer_complete_isr(uint8_t rhport, uint32_t interval_ms) +void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms) { uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u); ehci_link_t next_link = *list_get_period_head(rhport, interval_ms); @@ -612,22 +616,13 @@ void period_list_xfer_complete_isr(uint8_t rhport, uint32_t interval_ms) switch (next_link.type) { case EHCI_QTYPE_QHD: { ehci_qhd_t *qhd = (ehci_qhd_t *) entry_addr; - hcd_dcache_invalidate(qhd, sizeof(ehci_qhd_t)); - - if (!qhd->qtd_overlay.halted) { - qhd_xfer_complete_isr(qhd); - } + qhd_xfer_complete_isr(qhd); } break; + // TODO support hs/fs ISO case EHCI_QTYPE_ITD: - // TODO support hs ISO - break; - case EHCI_QTYPE_SITD: - // TODO support split ISO - break; - case EHCI_QTYPE_FSTN: default: break; @@ -637,106 +632,6 @@ void period_list_xfer_complete_isr(uint8_t rhport, uint32_t interval_ms) } } -// TODO merge with qhd_xfer_complete_isr() -TU_ATTR_ALWAYS_INLINE static inline -void qhd_xfer_error_isr(ehci_qhd_t * qhd) -{ - volatile ehci_qtd_t *qtd_overlay = &qhd->qtd_overlay; - - // TD has error - if (qtd_overlay->halted) { - xfer_result_t xfer_result; - - if (qtd_overlay->xact_err || qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err) { - // Error count = 0 often occurs when device disconnected, or other bus-related error - xfer_result = XFER_RESULT_FAILED; - }else { - // no error bits are set, endpoint is halted due to STALL - xfer_result = XFER_RESULT_STALLED; - } - -// if (XFER_RESULT_FAILED == xfer_result ) { -// TU_LOG1(" QHD xfer err count: %d\n", qtd_overlay->err_count); -// TU_BREAKPOINT(); // TODO skip unplugged device -// } - - ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) qhd->attached_qtd; - TU_ASSERT(qtd, ); // No TD yet, probably a race condition or cache issue !? - - hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); - - uint8_t dir = (qtd->pid == EHCI_PID_IN) ? 1 : 0; - uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes; - - // invalidate dcache if IN transfer - if (dir == 1 && qhd->attached_buffer != 0 && xferred_bytes > 0) { - hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes); - } - - // remove and free TD before invoking callback - qhd_remove_qtd(qhd); - - if (0 == qhd->ep_number ) { - // control cannot be halted - qhd->qtd_overlay.next.terminate = 1; - qhd->qtd_overlay.alternate.terminate = 1; - qhd->qtd_overlay.halted = 0; - - hcd_dcache_clean(qhd, sizeof(ehci_qhd_t)); - } - - // notify usbh - uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir); - hcd_event_xfer_complete(qhd->dev_addr, ep_addr, xferred_bytes, xfer_result, true); - } -} - -TU_ATTR_ALWAYS_INLINE static inline -void xfer_error_isr(uint8_t rhport) -{ - //------------- async list -------------// - ehci_qhd_t * const async_head = list_get_async_head(rhport); - ehci_qhd_t *p_qhd = async_head; - do - { - hcd_dcache_invalidate(p_qhd, sizeof(ehci_qhd_t)); - qhd_xfer_error_isr( p_qhd ); - p_qhd = qhd_next(p_qhd); - }while(p_qhd != async_head); // async list traversal, stop if loop around - - //------------- TODO refractor period list -------------// - uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u); - for (uint32_t interval_ms=1; interval_ms <= FRAMELIST_SIZE; interval_ms *= 2) - { - ehci_link_t next_item = *list_get_period_head(rhport, interval_ms); - - // TODO abstract max loop guard for period - while( !next_item.terminate && - !(interval_ms > 1 && period_1ms_addr == tu_align32(next_item.address)) ) - { - switch ( next_item.type ) - { - case EHCI_QTYPE_QHD: - { - ehci_qhd_t *p_qhd_int = (ehci_qhd_t *) tu_align32(next_item.address); - hcd_dcache_invalidate(p_qhd_int, sizeof(ehci_qhd_t)); - - qhd_xfer_error_isr(p_qhd_int); - } - break; - - // TODO support hs/fs ISO - case EHCI_QTYPE_ITD: - case EHCI_QTYPE_SITD: - case EHCI_QTYPE_FSTN: - default: break; - } - - next_item = *list_next(&next_item); - } - } -} - //------------- Host Controller Driver's Interrupt Handler -------------// void hcd_int_handler(uint8_t rhport) { @@ -768,21 +663,16 @@ void hcd_int_handler(uint8_t rhport) regs->status = EHCI_INT_MASK_PORT_CHANGE; // Acknowledge } - // A USB transfer is completed with error - if (int_status & EHCI_INT_MASK_ERROR) { - xfer_error_isr(rhport); - regs->status = EHCI_INT_MASK_ERROR; // Acknowledge - } + // A USB transfer is completed (OK or error) + uint32_t const usb_int = int_status & (EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR); + if (usb_int) { + proccess_async_xfer_isr(list_get_async_head(rhport)); - // A USB transfer is completed - if (int_status & EHCI_INT_MASK_USB) { for ( uint32_t i = 1; i <= FRAMELIST_SIZE; i *= 2 ) { - period_list_xfer_complete_isr(rhport, i); + process_period_xfer_isr(rhport, i); } - async_list_xfer_complete_isr(list_get_async_head(rhport)); - - regs->status = EHCI_INT_MASK_USB; // Acknowledge + regs->status = usb_int; // Acknowledge } //------------- There is some removed async previously -------------// @@ -1011,8 +901,7 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t *qtd_find_free(void) { return NULL; } -static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes) -{ +static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes) { tu_memclr(qtd, sizeof(ehci_qtd_t)); qtd->used = 1; @@ -1026,8 +915,7 @@ static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes) qtd->expected_bytes = total_bytes; qtd->buffer[0] = (uint32_t) buffer; - for(uint8_t i=1; i<5; i++) - { + for(uint8_t i=1; i<5; i++) { qtd->buffer[i] |= tu_align4k(qtd->buffer[i - 1] ) + 4096; } } -- cgit v1.3.1 From fbaa148fe0f4a4b83f41efe9887a8909161710f6 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 18 Jul 2023 15:22:09 +0700 Subject: updating hcd rusb2 - make osal_task_delay() as weak function in usbh - implement osal_task_delay() in hcd rusb2 (may moved to other places) --- examples/device/cdc_msc_freertos/skip.txt | 1 + examples/device/hid_composite_freertos/skip.txt | 1 + examples/dual/host_hid_to_device_cdc/only.txt | 1 + hw/bsp/ra/boards/ra6m5_ek/board.cmake | 7 +- hw/bsp/ra/family.cmake | 2 +- src/host/usbh.c | 2 +- src/portable/renesas/rusb2/dcd_rusb2.c | 12 ++- src/portable/renesas/rusb2/hcd_rusb2.c | 123 +++++++++++------------- src/portable/renesas/rusb2/rusb2_ra.h | 7 -- 9 files changed, 78 insertions(+), 78 deletions(-) (limited to 'src') diff --git a/examples/device/cdc_msc_freertos/skip.txt b/examples/device/cdc_msc_freertos/skip.txt index 49b8ee57b..a6f96b288 100644 --- a/examples/device/cdc_msc_freertos/skip.txt +++ b/examples/device/cdc_msc_freertos/skip.txt @@ -8,5 +8,6 @@ mcu:RP2040 mcu:SAMD11 mcu:SAMX7X mcu:VALENTYUSB_EPTRI +mcu:RAXXX family:broadcom_32bit family:broadcom_64bit diff --git a/examples/device/hid_composite_freertos/skip.txt b/examples/device/hid_composite_freertos/skip.txt index 49b8ee57b..a6f96b288 100644 --- a/examples/device/hid_composite_freertos/skip.txt +++ b/examples/device/hid_composite_freertos/skip.txt @@ -8,5 +8,6 @@ mcu:RP2040 mcu:SAMD11 mcu:SAMX7X mcu:VALENTYUSB_EPTRI +mcu:RAXXX family:broadcom_32bit family:broadcom_64bit diff --git a/examples/dual/host_hid_to_device_cdc/only.txt b/examples/dual/host_hid_to_device_cdc/only.txt index 6ee8e3fde..d9700677f 100644 --- a/examples/dual/host_hid_to_device_cdc/only.txt +++ b/examples/dual/host_hid_to_device_cdc/only.txt @@ -1,3 +1,4 @@ board:mimxrt1060_evk board:mimxrt1064_evk mcu:RP2040 +mcu:ra6m5 diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake index 5a615f9b0..c91d48a32 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake +++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake @@ -3,15 +3,20 @@ set(MCU_VARIANT ra6m5) set(JLINK_DEVICE R7FA6M5BH) -# default to PORT1 Highspeed +# Device port default to PORT1 Highspeed if (NOT DEFINED PORT) set(PORT 1) endif() +# Host port will be the other port +set(HOST_PORT $) + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC BOARD_TUD_RHPORT=${PORT} + BOARD_TUH_RHPORT=${HOST_PORT} # port 0 is fullspeed, port 1 is highspeed BOARD_TUD_MAX_SPEED=$ + BOARD_TUH_MAX_SPEED=$ ) endfunction() diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index f09e86a72..2c45b8d71 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -13,7 +13,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(FAMILY_MCUS RAXXX CACHE INTERNAL "") +set(FAMILY_MCUS RAXXX ${MCU_VARIANT} CACHE INTERNAL "") #------------------------------------ # BOARD_TARGET diff --git a/src/host/usbh.c b/src/host/usbh.c index 184bda23b..1418cfb79 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -256,7 +256,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t #if CFG_TUSB_OS == OPT_OS_NONE // TODO rework time-related function later -void osal_task_delay(uint32_t msec) +TU_ATTR_WEAK void osal_task_delay(uint32_t msec) { const uint32_t start = hcd_frame_number(_usbh_controller); while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {} diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 358e5644b..6fee4edd7 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -27,12 +27,12 @@ #include "tusb_option.h" +#if CFG_TUD_ENABLED && defined(TUP_USBIP_RUSB2) + // Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) // We disable SOF for now until needed later on #define USE_SOF 0 -#if CFG_TUD_ENABLED && defined(TUP_USBIP_RUSB2) - #include "device/dcd.h" #include "rusb2_type.h" @@ -53,6 +53,13 @@ #error "Unsupported MCU" #endif +//--------------------------------------------------------------------+ +// Application API for setting IRQ number +//--------------------------------------------------------------------+ +void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) { + rusb2_controller[rhport].irqnum = irqnum; +} + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ @@ -681,7 +688,6 @@ static void enable_interrupt(uint32_t pswi) void dcd_init(uint8_t rhport) { rusb2_reg_t* rusb = RUSB2_REG(rhport); - rusb2_module_start(rhport, true); #ifdef RUSB2_SUPPORT_HIGHSPEED diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 4e5ff0359..656051e2b 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -27,8 +27,7 @@ #include "tusb_option.h" -#if CFG_TUH_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \ - TU_CHECK_MCU(OPT_MCU_RAXXX)) +#if CFG_TUH_ENABLED && defined(TUP_USBIP_RUSB2) #include "host/hcd.h" #include "rusb2_type.h" @@ -41,8 +40,14 @@ #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #include "rusb2_rx.h" + #elif TU_CHECK_MCU(OPT_MCU_RAXXX) #include "rusb2_ra.h" + + void osal_task_delay(uint32_t msec) { + R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS); + } + #else #error "Unsupported MCU" #endif @@ -67,19 +72,6 @@ TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN -typedef struct TU_ATTR_PACKED { - union { - struct { - uint16_t : 8; - uint16_t TRCLR: 1; - uint16_t TRENB: 1; - uint16_t : 0; - }; - uint16_t TRE; - }; - uint16_t TRN; -} reg_pipetre_t; - typedef union TU_ATTR_PACKED { struct { volatile uint16_t u8: 8; @@ -308,8 +300,9 @@ static bool pipe_xfer_out(unsigned num) pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } - if (len < mps) + if (len < mps) { RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + } RUSB2->D0FIFOSEL = 0; while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; @@ -488,60 +481,60 @@ static void enable_interrupt(uint32_t pswi) bool hcd_init(uint8_t rhport) { - (void)rhport; - -#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) - RUSB2->SYSCFG_b.HSE = 1; - RUSB2->PHYSET_b.HSEB = 0; - RUSB2->PHYSET_b.DIRPD = 0; - R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS); - RUSB2->PHYSET_b.PLLRESET = 0; - RUSB2->LPSTS_b.SUSPENDM = 1; - while (!RUSB2->PLLSTA_b.PLLLOCK); - RUSB2->SYSCFG_b.DRPD = 1; - RUSB2->SYSCFG_b.DCFM = 1; - RUSB2->SYSCFG_b.DPRPU = 0; - RUSB2->SYSCFG_b.CNEN = 1; - RUSB2->BUSWAIT |= 0x0F00U; - RUSB2->SOFCFG_b.INTL = 1; - RUSB2->DVSTCTR0_b.VBUSEN = 1; - RUSB2->CFIFOSEL_b.MBW = 1; - RUSB2->D0FIFOSEL_b.MBW = 1; - RUSB2->D1FIFOSEL_b.MBW = 1; - RUSB2->INTSTS0 = 0; - for (volatile int i = 0; i < 30000; ++i) ; - RUSB2->SYSCFG_b.USBE = 1; -#else - /* HOST DEVICE Full SPEED */ - RUSB2->SYSCFG_b.SCKE = 1; /* USB Clock enable */ - while (!RUSB2->SYSCFG_b.SCKE) ; - RUSB2->SYSCFG_b.DPRPU = 0; /* D+ pull up enable - 0/disable in host mode */ - RUSB2->SYSCFG_b.DRPD = 1; /* D+/D- pull down - 1/in Host mode (pag.834)*/ - RUSB2->SYSCFG_b.DCFM = 1; /* HOST or Device - 1/HOST */ - - RUSB2->DVSTCTR0_b.VBUSEN = 1; - - RUSB2->SYSCFG_b.DRPD = 1; - for (volatile int i = 0; i < 30000; ++i) ; - RUSB2->SYSCFG_b.USBE = 1; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + rusb2_module_start(rhport, true); + +#ifdef RUSB2_SUPPORT_HIGHSPEED + if (rusb2_is_highspeed_rhport(rhport) ) { + rusb->SYSCFG_b.HSE = 1; + rusb->PHYSET_b.HSEB = 0; + rusb->PHYSET_b.DIRPD = 0; + R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS); + rusb->PHYSET_b.PLLRESET = 0; + rusb->LPSTS_b.SUSPENDM = 1; + while ( !rusb->PLLSTA_b.PLLLOCK ); + rusb->SYSCFG_b.DRPD = 1; + rusb->SYSCFG_b.DCFM = 1; + rusb->SYSCFG_b.DPRPU = 0; + rusb->SYSCFG_b.CNEN = 1; + rusb->BUSWAIT |= 0x0F00U; + rusb->SOFCFG_b.INTL = 1; + rusb->DVSTCTR0_b.VBUSEN = 1; + rusb->CFIFOSEL_b.MBW = 1; + rusb->D0FIFOSEL_b.MBW = 1; + rusb->D1FIFOSEL_b.MBW = 1; + rusb->INTSTS0 = 0; + for ( volatile int i = 0; i < 30000; ++i ); + rusb->SYSCFG_b.USBE = 1; + } else #endif + { + rusb->SYSCFG_b.SCKE = 1; + while ( !rusb->SYSCFG_b.SCKE ) {} + rusb->SYSCFG_b.DCFM = 1; // Host function + rusb->SYSCFG_b.DPRPU = 0; // Disable D+ pull up + rusb->SYSCFG_b.DRPD = 1; // Enable D+/D- pull down - // MCU specific PHY init - rusb2_phy_init(); + rusb->DVSTCTR0_b.VBUSEN = 1; + for ( volatile int i = 0; i < 30000; ++i ) {} // FIXME do we need to wait here? how long ? + //R_BSP_SoftwareDelay(10, BSP_DELAY_UNITS_MILLISECONDS); + rusb->SYSCFG_b.USBE = 1; -#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST) - RUSB2->PHYSLEW = 0x5; - RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */ -#endif + // MCU specific PHY init + rusb2_phy_init(); + + rusb->PHYSLEW = 0x5; + rusb->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */ + } /* Setup default control pipe */ - RUSB2->DCPCFG = RUSB2_PIPECFG_SHTNAK_Msk; - RUSB2->DCPMAXP = 64; - RUSB2->INTENB0 = RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk; - RUSB2->INTENB1 = RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk; - RUSB2->BEMPENB = 1; - RUSB2->NRDYENB = 1; - RUSB2->BRDYENB = 1; + rusb->DCPCFG = RUSB2_PIPECFG_SHTNAK_Msk; + rusb->DCPMAXP = 64; + rusb->INTENB0 = RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk; + rusb->INTENB1 = RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk; + rusb->BEMPENB = 1; + rusb->NRDYENB = 1; + rusb->BRDYENB = 1; return true; } diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 28b690512..8a4d2ad36 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -106,13 +106,6 @@ TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) { TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) { } -//--------------------------------------------------------------------+ -// Application API for setting IRQ number -//--------------------------------------------------------------------+ -void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) { - rusb2_controller[rhport].irqnum = irqnum; -} - #ifdef __cplusplus } #endif -- cgit v1.3.1 From 6b6dcc6c099eeafaa6d76bf6133181874beabc0d Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 26 Jul 2023 19:50:50 +0700 Subject: refactored multiple ports for hcd rusb2 --- .idea/cmake.xml | 15 +- .idea/runConfigurations/ra6m5.xml | 2 +- hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug | 4 +- src/portable/renesas/rusb2/dcd_rusb2.c | 37 +-- src/portable/renesas/rusb2/hcd_rusb2.c | 452 ++++++++++++++------------- 5 files changed, 268 insertions(+), 242 deletions(-) (limited to 'src') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 864ff615b..519623b71 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -2,7 +2,6 @@ - @@ -26,27 +25,27 @@ - - - + + + - + + - - - + + \ No newline at end of file diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml index 02df11610..89f9787a0 100644 --- a/.idea/runConfigurations/ra6m5.xml +++ b/.idea/runConfigurations/ra6m5.xml @@ -1,5 +1,5 @@ - + diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug index aebb29162..7b8ee9c95 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug +++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug @@ -20,7 +20,9 @@ void OnProjectLoad (void) { Project.SetTraceSource ("Trace Pins"); Project.SetTracePortWidth (4); - File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ra6m5/cdc_msc.elf"); + //File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ra6m5/cdc_msc.elf"); + //File.Open ("../../../../../../examples/dual/cmake-build-ra6m5/host_hid_to_device_cdc/host_hid_to_device_cdc.elf"); + File.Open ("../../../../../../examples/cmake-build-ra6m5/host/cdc_msc_hid/cdc_msc_hid.elf"); } /********************************************************************* * diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 6fee4edd7..83f0fdc4a 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -83,6 +83,18 @@ typedef struct TU_ATTR_PACKED TU_ATTR_PACKED_END // End of definition of packed structs (used by the CCRX toolchain) TU_ATTR_BIT_FIELD_ORDER_END +typedef struct +{ + pipe_state_t pipe[10]; + uint8_t ep[2][16]; /* a lookup table for a pipe index from an endpoint address */ +} dcd_data_t; + +static dcd_data_t _dcd; + +//--------------------------------------------------------------------+ +// INTERNAL OBJECT & FUNCTION DECLARATION +//--------------------------------------------------------------------+ + // Transfer conditions specifiable for each pipe: // - Pipe 0: Control transfer with 64-byte single buffer // - Pipes 1 and 2: Bulk isochronous transfer continuous transfer mode with programmable buffer size up @@ -96,18 +108,6 @@ enum { PIPE_COUNT = 10, }; -typedef struct -{ - pipe_state_t pipe[10]; - uint8_t ep[2][16]; /* a lookup table for a pipe index from an endpoint address */ -} dcd_data_t; - -static dcd_data_t _dcd; - -//--------------------------------------------------------------------+ -// INTERNAL OBJECT & FUNCTION DECLARATION -//--------------------------------------------------------------------+ - static unsigned find_pipe(unsigned xfer) { switch (xfer) { @@ -746,20 +746,17 @@ void dcd_init(uint8_t rhport) } } -void dcd_int_enable(uint8_t rhport) -{ +void dcd_int_enable(uint8_t rhport) { rusb2_int_enable(rhport); } -void dcd_int_disable(uint8_t rhport) -{ +void dcd_int_disable(uint8_t rhport) { rusb2_int_disable(rhport); } -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) -{ - (void)rhport; - (void)dev_addr; +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { + (void) rhport; + (void) dev_addr; } void dcd_remote_wakeup(uint8_t rhport) diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 656051e2b..a4b534a05 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -52,23 +52,12 @@ #error "Unsupported MCU" #endif -#define TU_RUSB2_HCD_DBG 0 +#define TU_RUSB2_HCD_DBG 2 //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ -/* LINK core registers */ -#if defined(__CCRX__) - #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE) -#elif defined(__RX__) - #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE) -#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) - #define RUSB2 ((R_USB_HS0_Type*) R_USB_HS0_BASE) -#else - #define RUSB2 ((R_USB_FS0_Type*) R_USB_FS0_BASE) -#endif - TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN @@ -108,79 +97,97 @@ typedef struct //--------------------------------------------------------------------+ static hcd_data_t _hcd; -static unsigned find_pipe(unsigned xfer) -{ - switch (xfer) { - case TUSB_XFER_ISOCHRONOUS: - for (int i = 1; i <= 2; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_BULK: - for (int i = 3; i <= 5; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - for (int i = 1; i <= 2; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - break; - case TUSB_XFER_INTERRUPT: - for (int i = 6; i <= 9; ++i) { - if (0 == _hcd.pipe[i].ep) return i; - } - break; - default: - /* No support for control transfer */ - break; +// TODO merged with DCD +// Transfer conditions specifiable for each pipe: +// - Pipe 0: Control transfer with 64-byte single buffer +// - Pipes 1 and 2: Bulk isochronous transfer continuous transfer mode with programmable buffer size up +// to 2 KB and optional double buffer +// - Pipes 3 to 5: Bulk transfer continuous transfer mode with programmable buffer size up to 2 KB and +// optional double buffer +// - Pipes 6 to 9: Interrupt transfer with 64-byte single buffer +enum { + PIPE_1ST_BULK = 3, + PIPE_1ST_INTERRUPT = 6, + PIPE_COUNT = 10, +}; + +static unsigned find_pipe(unsigned xfer) { + switch ( xfer ) { + case TUSB_XFER_ISOCHRONOUS: + for (int i = 1; i < PIPE_1ST_BULK; ++i) { + if ( 0 == _hcd.pipe[i].ep ) return i; + } + break; + + case TUSB_XFER_BULK: + for (int i = PIPE_1ST_BULK; i < PIPE_1ST_INTERRUPT; ++i) { + if ( 0 == _hcd.pipe[i].ep ) return i; + } + for (int i = 1; i < PIPE_1ST_BULK; ++i) { + if ( 0 == _hcd.pipe[i].ep ) return i; + } + break; + + case TUSB_XFER_INTERRUPT: + for (int i = PIPE_1ST_INTERRUPT; i < PIPE_COUNT; ++i) { + if ( 0 == _hcd.pipe[i].ep ) return i; + } + break; + + default: + /* No support for control transfer */ + break; } return 0; } -static volatile uint16_t* get_pipectr(unsigned num) +static volatile uint16_t* get_pipectr(rusb2_reg_t *rusb, unsigned num) { if (num) { - return (volatile uint16_t*)&(RUSB2->PIPE_CTR[num - 1]); + return (volatile uint16_t*)&(rusb->PIPE_CTR[num - 1]); } else { - return (volatile uint16_t*)&(RUSB2->DCPCTR); + return (volatile uint16_t*)&(rusb->DCPCTR); } } -static volatile reg_pipetre_t* get_pipetre(unsigned num) +static volatile reg_pipetre_t* get_pipetre(rusb2_reg_t *rusb, unsigned num) { volatile reg_pipetre_t* tre = NULL; if ((1 <= num) && (num <= 5)) { - tre = (volatile reg_pipetre_t*)&(RUSB2->PIPE_TR[num - 1].E); + tre = (volatile reg_pipetre_t*)&(rusb->PIPE_TR[num - 1].E); } return tre; } -static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr) +static volatile uint16_t* addr_to_pipectr(uint8_t rhport, uint8_t dev_addr, unsigned ep_addr) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); const unsigned epn = tu_edpt_number(ep_addr); + if (epn) { const unsigned dir_in = tu_edpt_dir(ep_addr); const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1]; - return get_pipectr(num); + return get_pipectr(rusb, num); } else { - return get_pipectr(0); + return get_pipectr(rusb, 0); } } -static unsigned edpt0_max_packet_size(void) +static uint16_t edpt0_max_packet_size(rusb2_reg_t* rusb) { - return RUSB2->DCPMAXP_b.MXPS; + return rusb->DCPMAXP_b.MXPS; } -static unsigned edpt_max_packet_size(unsigned num) +static uint16_t edpt_max_packet_size(rusb2_reg_t *rusb, unsigned num) { - RUSB2->PIPESEL = num; - return RUSB2->PIPEMAXP_b.MXPS; + rusb->PIPESEL = num; + return rusb->PIPEMAXP_b.MXPS; } -static inline void pipe_wait_for_ready(unsigned num) +static inline void pipe_wait_for_ready(rusb2_reg_t* rusb, unsigned num) { - while (RUSB2->D0FIFOSEL_b.CURPIPE != num) ; - while (!RUSB2->D0FIFOCTR_b.FRDY) ; + while (rusb->D0FIFOSEL_b.CURPIPE != num) ; + while (!rusb->D0FIFOCTR_b.FRDY) {} } static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) @@ -205,33 +212,33 @@ static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) while (len--) *p++ = *reg; } -static bool pipe0_xfer_in(void) +static bool pipe0_xfer_in(rusb2_reg_t* rusb) { pipe_state_t *pipe = &_hcd.pipe[0]; const unsigned rem = pipe->remaining; - const unsigned mps = edpt0_max_packet_size(); - const unsigned vld = RUSB2->CFIFOCTR_b.DTLN; + const unsigned mps = edpt0_max_packet_size(rusb); + const unsigned vld = rusb->CFIFOCTR_b.DTLN; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { - RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; - pipe_read_packet(buf, (volatile void*)&RUSB2->CFIFO, len); + rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; + pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } if (len < mps) { - RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; + rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; } pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; return true; } - RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF; + rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF; return false; } -static bool pipe0_xfer_out(void) +static bool pipe0_xfer_out(rusb2_reg_t* rusb) { pipe_state_t *pipe = &_hcd.pipe[0]; const unsigned rem = pipe->remaining; @@ -239,40 +246,40 @@ static bool pipe0_xfer_out(void) pipe->buf = NULL; return true; } - const unsigned mps = edpt0_max_packet_size(); + const unsigned mps = edpt0_max_packet_size(rusb); const unsigned len = TU_MIN(mps, rem); void *buf = pipe->buf; if (len) { - pipe_write_packet(buf, (volatile void*)&RUSB2->CFIFO, len); + pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len); pipe->buf = (uint8_t*)buf + len; } if (len < mps) { - RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; } pipe->remaining = rem - len; return false; } -static bool pipe_xfer_in(unsigned num) +static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num) { pipe_state_t *pipe = &_hcd.pipe[num]; const unsigned rem = pipe->remaining; - RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT; - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); - const unsigned vld = RUSB2->D0FIFOCTR_b.DTLN; + rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT; + const unsigned mps = edpt_max_packet_size(rusb, num); + pipe_wait_for_ready(rusb, num); + const unsigned vld = rusb->D0FIFOCTR_b.DTLN; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { - pipe_read_packet(buf, (volatile void*)&RUSB2->D0FIFO, len); + pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } if (len < mps) { - RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; + rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; } - RUSB2->D0FIFOSEL = 0; - while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + rusb->D0FIFOSEL = 0; + while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; if ((len < mps) || (rem == len)) { pipe->buf = NULL; @@ -281,7 +288,7 @@ static bool pipe_xfer_in(unsigned num) return false; } -static bool pipe_xfer_out(unsigned num) +static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num) { pipe_state_t *pipe = &_hcd.pipe[num]; const unsigned rem = pipe->remaining; @@ -291,37 +298,39 @@ static bool pipe_xfer_out(unsigned num) return true; } - RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); - const unsigned mps = edpt_max_packet_size(num); - pipe_wait_for_ready(num); + rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); + const unsigned mps = edpt_max_packet_size(rusb, num); + pipe_wait_for_ready(rusb, num); const unsigned len = TU_MIN(rem, mps); void *buf = pipe->buf; if (len) { - pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len); + pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len); pipe->buf = (uint8_t*)buf + len; } if (len < mps) { - RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; } - RUSB2->D0FIFOSEL = 0; - while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ + rusb->D0FIFOSEL = 0; + while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ pipe->remaining = rem - len; return false; } -static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) +static bool process_pipe0_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) { (void)dev_addr; + + rusb2_reg_t* rusb = RUSB2_REG(rhport); const unsigned dir_in = tu_edpt_dir(ep_addr); /* configure fifo direction and access unit settings */ if (dir_in) { /* IN, a byte */ - RUSB2->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT; - while (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ; + rusb->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT; + while (rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ; } else { /* OUT, 2 bytes */ - RUSB2->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT | + rusb->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0); - while (!(RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ; + while (!(rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ; } pipe_state_t *pipe = &_hcd.pipe[0]; @@ -331,26 +340,28 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, if (buflen) { pipe->buf = buffer; if (!dir_in) { /* OUT */ - TU_ASSERT(RUSB2->DCPCTR_b.BSTS && (RUSB2->USBREQ & 0x80)); - pipe0_xfer_out(); + TU_ASSERT(rusb->DCPCTR_b.BSTS && (rusb->USBREQ & 0x80)); + pipe0_xfer_out(rusb); } } else { /* ZLP */ pipe->buf = NULL; if (!dir_in) { /* OUT */ - RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; } - if (dir_in == RUSB2->DCPCFG_b.DIR) { - TU_ASSERT(RUSB2_PIPE_CTR_PID_NAK == RUSB2->DCPCTR_b.PID); - RUSB2->DCPCTR_b.SQSET = 1; - RUSB2->DCPCFG_b.DIR = dir_in ^ 1; + if (dir_in == rusb->DCPCFG_b.DIR) { + TU_ASSERT(RUSB2_PIPE_CTR_PID_NAK == rusb->DCPCTR_b.PID); + rusb->DCPCTR_b.SQSET = 1; + rusb->DCPCFG_b.DIR = dir_in ^ 1; } } - RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF; + rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF; return true; } -static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen) +static bool process_pipe_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); + const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir_in = tu_edpt_dir(ep_addr); const unsigned num = _hcd.ep[dev_addr - 1][dir_in][epn - 1]; @@ -363,19 +374,19 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u pipe->remaining = buflen; if (!dir_in) { /* OUT */ if (buflen) { - pipe_xfer_out(num); + pipe_xfer_out(rusb, num); } else { /* ZLP */ - RUSB2->D0FIFOSEL = num; - pipe_wait_for_ready(num); - RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; - RUSB2->D0FIFOSEL = 0; - while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ + rusb->D0FIFOSEL = num; + pipe_wait_for_ready(rusb, num); + rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->D0FIFOSEL = 0; + while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ } } else { - volatile uint16_t *ctr = get_pipectr(num); - volatile reg_pipetre_t *pt = get_pipetre(num); + volatile uint16_t *ctr = get_pipectr(rusb, num); + volatile reg_pipetre_t *pt = get_pipetre(rusb, num); if (pt) { - const unsigned mps = edpt_max_packet_size(num); + const unsigned mps = edpt_max_packet_size(rusb, num); if (*ctr & 0x3) *ctr = RUSB2_PIPE_CTR_PID_NAK; pt->TRE = TU_BIT(8); pt->TRN = (buflen + mps - 1) / mps; @@ -386,20 +397,20 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u return true; } -static bool process_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) +static bool process_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen) { const unsigned epn = tu_edpt_number(ep_addr); if (0 == epn) { - return process_pipe0_xfer(dev_addr, ep_addr, buffer, buflen); + return process_pipe0_xfer(rhport, dev_addr, ep_addr, buffer, buflen); } else { - return process_pipe_xfer(dev_addr, ep_addr, buffer, buflen); + return process_pipe_xfer(rhport, dev_addr, ep_addr, buffer, buflen); } } static void process_pipe0_bemp(uint8_t rhport) { - (void)rhport; - bool completed = pipe0_xfer_out(); + rusb2_reg_t* rusb = RUSB2_REG(rhport); + bool completed = pipe0_xfer_out(rusb); if (completed) { pipe_state_t *pipe = &_hcd.pipe[0]; hcd_event_xfer_complete(pipe->dev, @@ -411,9 +422,9 @@ static void process_pipe0_bemp(uint8_t rhport) static void process_pipe_nrdy(uint8_t rhport, unsigned num) { - (void)rhport; + rusb2_reg_t* rusb = RUSB2_REG(rhport); xfer_result_t result; - uint16_t volatile *ctr = get_pipectr(num); + uint16_t volatile *ctr = get_pipectr(rusb, num); TU_LOG(TU_RUSB2_HCD_DBG, "NRDY %d %x\n", num, *ctr); switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) { default: return; @@ -429,19 +440,19 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num) static void process_pipe_brdy(uint8_t rhport, unsigned num) { - (void)rhport; + rusb2_reg_t* rusb = RUSB2_REG(rhport); pipe_state_t *pipe = &_hcd.pipe[num]; const unsigned dir_in = tu_edpt_dir(pipe->ep); bool completed; if (dir_in) { /* IN */ if (num) { - completed = pipe_xfer_in(num); + completed = pipe_xfer_in(rusb, num); } else { - completed = pipe0_xfer_in(); + completed = pipe0_xfer_in(rusb); } } else { - completed = pipe_xfer_out(num); + completed = pipe_xfer_out(rusb, num); } if (completed) { hcd_event_xfer_complete(pipe->dev, pipe->ep, @@ -539,86 +550,88 @@ bool hcd_init(uint8_t rhport) return true; } -void hcd_int_enable(uint8_t rhport) -{ +void hcd_int_enable(uint8_t rhport) { rusb2_int_enable(rhport); } -void hcd_int_disable(uint8_t rhport) -{ +void hcd_int_disable(uint8_t rhport) { rusb2_int_disable(rhport); } uint32_t hcd_frame_number(uint8_t rhport) { - (void)rhport; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + /* The device must be reset at least once after connection * in order to start the frame counter. */ if (_hcd.need_reset) hcd_port_reset(rhport); - return RUSB2->FRMNUM_b.FRNM; + return rusb->FRMNUM_b.FRNM; } /*--------------------------------------------------------------------+ * Port API *--------------------------------------------------------------------+*/ -bool hcd_port_connect_status(uint8_t rhport) -{ - (void)rhport; - return RUSB2->INTSTS1_b.ATTCH ? true : false; +bool hcd_port_connect_status(uint8_t rhport) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); + return rusb->INTSTS1_b.ATTCH ? true : false; } -void hcd_port_reset(uint8_t rhport) -{ - RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; - while (RUSB2->DCPCTR_b.PBUSY) ; +void hcd_port_reset(uint8_t rhport) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); + rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; + while (rusb->DCPCTR_b.PBUSY) {} + hcd_int_disable(rhport); - RUSB2->DVSTCTR0_b.UACT = 0; - if (RUSB2->DCPCTR_b.SUREQ) { - RUSB2->DCPCTR_b.SUREQCLR = 1; + rusb->DVSTCTR0_b.UACT = 0; + if (rusb->DCPCTR_b.SUREQ) { + rusb->DCPCTR_b.SUREQCLR = 1; } hcd_int_enable(rhport); + /* Reset should be asserted 10-20ms. */ - RUSB2->DVSTCTR0_b.USBRST = 1; - for (volatile int i = 0; i < 2400000; ++i) ; - RUSB2->DVSTCTR0_b.USBRST = 0; - RUSB2->DVSTCTR0_b.UACT = 1; + rusb->DVSTCTR0_b.USBRST = 1; + for (volatile int i = 0; i < 2400000; ++i) {} + rusb->DVSTCTR0_b.USBRST = 0; + + rusb->DVSTCTR0_b.UACT = 1; _hcd.need_reset = false; } -void hcd_port_reset_end(uint8_t rhport) -{ +void hcd_port_reset_end(uint8_t rhport) { (void) rhport; } -tusb_speed_t hcd_port_speed_get(uint8_t rhport) -{ - (void)rhport; - switch (RUSB2->DVSTCTR0_b.RHST) { - default: return TUSB_SPEED_INVALID; +tusb_speed_t hcd_port_speed_get(uint8_t rhport) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); + switch (rusb->DVSTCTR0_b.RHST) { + case RUSB2_DVSTCTR0_RHST_HS: return TUSB_SPEED_HIGH; case RUSB2_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL; - case RUSB2_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW; + case RUSB2_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW; + default: return TUSB_SPEED_INVALID; } } -void hcd_device_close(uint8_t rhport, uint8_t dev_addr) -{ - (void)rhport; +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { + rusb2_reg_t* rusb = RUSB2_REG(rhport); uint16_t volatile *ctr; + TU_ASSERT(dev_addr < 6,); /* USBa can only handle addresses from 0 to 5. */ if (!dev_addr) return; + _hcd.ctl_mps[dev_addr] = 0; uint8_t *ep = &_hcd.ep[dev_addr - 1][0][0]; + for (int i = 0; i < 2 * 15; ++i, ++ep) { unsigned num = *ep; if (!num || (dev_addr != _hcd.pipe[num].dev)) continue; - ctr = (uint16_t volatile*)&RUSB2->PIPE_CTR[num - 1]; + ctr = (uint16_t volatile*)&rusb->PIPE_CTR[num - 1]; *ctr = 0; - RUSB2->NRDYENB &= ~TU_BIT(num); - RUSB2->BRDYENB &= ~TU_BIT(num); - RUSB2->PIPESEL = num; - RUSB2->PIPECFG = 0; - RUSB2->PIPEMAXP = 0; + rusb->NRDYENB &= ~TU_BIT(num); + rusb->BRDYENB &= ~TU_BIT(num); + rusb->PIPESEL = num; + rusb->PIPECFG = 0; + rusb->PIPEMAXP = 0; _hcd.pipe[num].ep = 0; _hcd.pipe[num].dev = 0; @@ -631,52 +644,54 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) *--------------------------------------------------------------------+*/ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { - (void)rhport; - TU_LOG(TU_RUSB2_HCD_DBG, "S %d %x\n", dev_addr, RUSB2->DCPCTR); - TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ - TU_ASSERT(0 == RUSB2->DCPCTR_b.SUREQ); - RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; + rusb2_reg_t* rusb = RUSB2_REG(rhport); + TU_LOG(TU_RUSB2_HCD_DBG, "S %d %x\n", dev_addr, rusb->DCPCTR); + + TU_ASSERT(0 == rusb->DCPCTR_b.SUREQ); + + rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; _hcd.pipe[0].buf = NULL; _hcd.pipe[0].length = 8; _hcd.pipe[0].remaining = 0; _hcd.pipe[0].dev = dev_addr; - while (RUSB2->DCPCTR_b.PBUSY) ; - RUSB2->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr]; + while (rusb->DCPCTR_b.PBUSY) ; + rusb->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr]; /* Set direction in advance for DATA stage */ uint8_t const bmRequesttype = setup_packet[0]; - RUSB2->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1; + rusb->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1; uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0]; - RUSB2->USBREQ = tu_htole16(p[0]); - RUSB2->USBVAL = p[1]; - RUSB2->USBINDX = p[2]; - RUSB2->USBLENG = p[3]; + rusb->USBREQ = tu_htole16(p[0]); + rusb->USBVAL = p[1]; + rusb->USBINDX = p[2]; + rusb->USBLENG = p[3]; - RUSB2->DCPCTR_b.SUREQ = 1; + rusb->DCPCTR_b.SUREQ = 1; return true; } bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *ep_desc) { - (void)rhport; TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ + rusb2_reg_t* rusb = RUSB2_REG(rhport); const unsigned ep_addr = ep_desc->bEndpointAddress; const unsigned epn = tu_edpt_number(ep_addr); const unsigned mps = tu_edpt_packet_size(ep_desc); + if (0 == epn) { - RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; + rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; hcd_devtree_info_t devtree; hcd_devtree_get_info(dev_addr, &devtree); - uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &RUSB2->DEVADD[0]; + uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &rusb->DEVADD[0]; devadd += dev_addr; - while (RUSB2->DCPCTR_b.PBUSY) ; - RUSB2->DCPMAXP = (dev_addr << 12) | mps; + while (rusb->DCPCTR_b.PBUSY) {} + rusb->DCPMAXP = (dev_addr << 12) | mps; *devadd = (TUSB_SPEED_FULL == devtree.speed) ? RUSB2_DEVADD_USBSPD_FS : RUSB2_DEVADD_USBSPD_LS; _hcd.ctl_mps[dev_addr] = mps; return true; @@ -690,17 +705,20 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const } const unsigned num = find_pipe(xfer); if (!num) return false; + _hcd.pipe[num].dev = dev_addr; _hcd.pipe[num].ep = ep_addr; _hcd.ep[dev_addr - 1][dir_in][epn - 1] = num; /* setup pipe */ hcd_int_disable(rhport); - RUSB2->PIPESEL = num; - RUSB2->PIPEMAXP = (dev_addr << 12) | mps; - volatile uint16_t *ctr = get_pipectr(num); + + rusb->PIPESEL = num; + rusb->PIPEMAXP = (dev_addr << 12) | mps; + volatile uint16_t *ctr = get_pipectr(rusb, num); *ctr = RUSB2_PIPE_CTR_ACLRM_Msk | RUSB2_PIPE_CTR_SQCLR_Msk; *ctr = 0; + unsigned cfg = ((1 ^ dir_in) << 4) | epn; if (xfer == TUSB_XFER_BULK) { cfg |= RUSB2_PIPECFG_TYPE_BULK | RUSB2_PIPECFG_SHTNAK_Msk | RUSB2_PIPECFG_DBLB_Msk; @@ -709,13 +727,16 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const } else { cfg |= RUSB2_PIPECFG_TYPE_ISO | RUSB2_PIPECFG_DBLB_Msk; } - RUSB2->PIPECFG = cfg; - RUSB2->BRDYSTS = 0x1FFu ^ TU_BIT(num); - RUSB2->NRDYENB |= TU_BIT(num); - RUSB2->BRDYENB |= TU_BIT(num); + + rusb->PIPECFG = cfg; + rusb->BRDYSTS = 0x1FFu ^ TU_BIT(num); + rusb->NRDYENB |= TU_BIT(num); + rusb->BRDYENB |= TU_BIT(num); + if (!dir_in) { *ctr = RUSB2_PIPE_CTR_PID_BUF; } + hcd_int_enable(rhport); return true; @@ -726,14 +747,15 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b bool r; hcd_int_disable(rhport); TU_LOG(TU_RUSB2_HCD_DBG, "X %d %x %u\n", dev_addr, ep_addr, buflen); - r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen); + r = process_edpt_xfer(rhport, dev_addr, ep_addr, buffer, buflen); hcd_int_enable(rhport); return r; } bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) { - uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr); + uint8_t rhport = 0; // FIXME change API + uint16_t volatile *ctr = addr_to_pipectr(rhport, dev_addr, ep_addr); TU_ASSERT(ctr); const uint32_t pid = *ctr & 0x3; @@ -756,67 +778,73 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) //--------------------------------------------------------------------+ void hcd_int_handler(uint8_t rhport) { - (void)rhport; -#if defined(__CCRX__) - static const int Mod37BitPosition[] = { - -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4, - 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5, - 20, 8, 19, 18}; -#endif + rusb2_reg_t* rusb = RUSB2_REG(rhport); static unsigned char attach_attempt = 0; - unsigned is1 = RUSB2->INTSTS1; - unsigned is0 = RUSB2->INTSTS0; + unsigned is0 = rusb->INTSTS0; + unsigned is1 = rusb->INTSTS1; /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ - RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1); - RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0); - TU_LOG(TU_RUSB2_HCD_DBG, "IS %04x %04x\n", is0, is1); - is1 &= RUSB2->INTENB1; - is0 &= RUSB2->INTENB0; + rusb->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1); + rusb->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0); + + TU_LOG3("IS %04x %04x\n", is0, is1); + is1 &= rusb->INTENB1; + is0 &= rusb->INTENB0; if (is1 & RUSB2_INTSTS1_SACK_Msk) { /* Set DATA1 in advance for the next transfer. */ - RUSB2->DCPCTR_b.SQSET = 1; + rusb->DCPCTR_b.SQSET = 1; attach_attempt = 0; - hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); + hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); } + if (is1 & RUSB2_INTSTS1_SIGN_Msk) { - hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); + hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); if(attach_attempt > 0) { - RUSB2->DVSTCTR0_b.UACT = 1; + rusb->DVSTCTR0_b.UACT = 1; _hcd.need_reset = true; - RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; + rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; hcd_event_device_attach(rhport, true); } attach_attempt--; } + if (is1 & RUSB2_INTSTS1_ATTCH_Msk) { attach_attempt = 10; - RUSB2->DVSTCTR0_b.UACT = 1; + rusb->DVSTCTR0_b.UACT = 1; _hcd.need_reset = true; - RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; + rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; hcd_event_device_attach(rhport, true); } + if (is1 & RUSB2_INTSTS1_DTCH_Msk) { - RUSB2->DVSTCTR0_b.UACT = 0; - if (RUSB2->DCPCTR_b.SUREQ) { - RUSB2->DCPCTR_b.SUREQCLR = 1; + rusb->DVSTCTR0_b.UACT = 0; + if (rusb->DCPCTR_b.SUREQ) { + rusb->DCPCTR_b.SUREQCLR = 1; } - RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_DTCH_Msk) | RUSB2_INTSTS1_ATTCH_Msk; + rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_DTCH_Msk) | RUSB2_INTSTS1_ATTCH_Msk; hcd_event_device_remove(rhport, true); } if (is0 & RUSB2_INTSTS0_BEMP_Msk) { - const unsigned s = RUSB2->BEMPSTS; - RUSB2->BEMPSTS = 0; + const unsigned s = rusb->BEMPSTS; + rusb->BEMPSTS = 0; if (s & 1) { process_pipe0_bemp(rhport); } } + +#if defined(__CCRX__) + static const int Mod37BitPosition[] = { + -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4, + 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5, + 20, 8, 19, 18}; +#endif + if (is0 & RUSB2_INTSTS0_NRDY_Msk) { - const unsigned m = RUSB2->NRDYENB; - unsigned s = RUSB2->NRDYSTS & m; - RUSB2->NRDYSTS = ~s; + const unsigned m = rusb->NRDYENB; + unsigned s = rusb->NRDYSTS & m; + rusb->NRDYSTS = ~s; while (s) { #if defined(__CCRX__) const unsigned num = Mod37BitPosition[(-s & s) % 37]; @@ -828,10 +856,10 @@ void hcd_int_handler(uint8_t rhport) } } if (is0 & RUSB2_INTSTS0_BRDY_Msk) { - const unsigned m = RUSB2->BRDYENB; - unsigned s = RUSB2->BRDYSTS & m; + const unsigned m = rusb->BRDYENB; + unsigned s = rusb->BRDYSTS & m; /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */ - RUSB2->BRDYSTS = ~s; + rusb->BRDYSTS = ~s; while (s) { #if defined(__CCRX__) const unsigned num = Mod37BitPosition[(-s & s) % 37]; -- cgit v1.3.1 From c37a9571741cef0dcf0cd5a77e202ae741a2dd42 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 26 Jul 2023 19:56:48 +0700 Subject: correct hcd_edpt_clear_stall() API signature --- src/host/hcd.h | 2 +- src/portable/mentor/musb/hcd_musb.c | 4 ++-- src/portable/nxp/khci/hcd_khci.c | 4 ++-- src/portable/ohci/ohci.c | 4 ++-- src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 4 ++-- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 4 ++-- src/portable/renesas/rusb2/hcd_rusb2.c | 4 ++-- 7 files changed, 13 insertions(+), 13 deletions(-) (limited to 'src') diff --git a/src/host/hcd.h b/src/host/hcd.h index 50f1dcdcc..898e0c6a4 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -179,7 +179,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr); bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]); // clear stall, data toggle is also reset to DATA0 -bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr); +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t daddr, uint8_t ep_addr); //--------------------------------------------------------------------+ // USBH implemented API diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c index 5be67a186..5d1fba6d9 100644 --- a/src/portable/mentor/musb/hcd_musb.c +++ b/src/portable/mentor/musb/hcd_musb.c @@ -831,8 +831,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { } // clear stall, data toggle is also reset to DATA0 -bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) -{ +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; unsigned const pipenum = find_pipe(dev_addr, ep_addr); if (!pipenum) return false; hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1); diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index 6784049c5..928564e26 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -570,8 +570,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { return false; } -bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) -{ +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; if (!tu_edpt_number(ep_addr)) return true; int num = find_pipe(dev_addr, ep_addr); if (num < 0) return false; diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 9f3af4781..413e72037 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -556,8 +556,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { return false; } -bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) -{ +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; ohci_ed_t * const p_ed = ed_from_addr(dev_addr, ep_addr); p_ed->is_stalled = 0; diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c index bb41ad638..45a3e80ef 100644 --- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c @@ -163,8 +163,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet // return busy; //} -bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) -{ +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; (void) dev_addr; (void) ep_addr; diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 5091fa907..6db8e2a0a 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -625,8 +625,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet return true; } -bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) -{ +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; (void) dev_addr; (void) ep_addr; diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 0a75d0b47..292d40da8 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -718,8 +718,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { return false; } -bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) -{ +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr); TU_ASSERT(ctr); -- cgit v1.3.1 From 10575c1b380136ce9381393c33e982cea7ef4731 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 26 Jul 2023 20:48:18 +0700 Subject: mising ehci --- src/host/hcd.h | 2 +- src/portable/ehci/ehci.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/host/hcd.h b/src/host/hcd.h index 898e0c6a4..d77dd6e2f 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -179,7 +179,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr); bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]); // clear stall, data toggle is also reset to DATA0 -bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t daddr, uint8_t ep_addr); +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr); //--------------------------------------------------------------------+ // USBH implemented API diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 241393a39..979069cfa 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -502,8 +502,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { return still_active; // true if removed an active transfer } -bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr) -{ +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; ehci_qhd_t *qhd = qhd_get_from_addr(daddr, ep_addr); qhd->qtd_overlay.halted = 0; hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); -- cgit v1.3.1 From 5a29db2787fea0ff9fe236d2631b2dcbc94aea50 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 27 Jul 2023 15:52:55 +0700 Subject: add check for edpt_xfer() with halted, also reset data toggle when clear stall --- src/portable/ehci/ehci.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index b84de5191..02b843667 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -443,6 +443,11 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * ehci_qtd_t* qtd; if (epnum == 0) { + // Control endpoint never be stalled. Skip reset Data Toggle since it is fixed per stage + if (qhd->qtd_overlay.halted) { + qhd->qtd_overlay.halted = false; + } + qtd = qtd_control(dev_addr); qtd_init(qtd, buffer, buflen); @@ -450,6 +455,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * qtd->data_toggle = 1; qtd->pid = dir ? EHCI_PID_IN : EHCI_PID_OUT; } else { + // skip if endpoint is halted + TU_VERIFY(!qhd->qtd_overlay.halted); + qtd = qtd_find_free(); TU_ASSERT(qtd); @@ -506,8 +514,9 @@ bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr) { ehci_qhd_t *qhd = qhd_get_from_addr(daddr, ep_addr); qhd->qtd_overlay.halted = 0; + qhd->qtd_overlay.data_toggle = 0; hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t)); - // TODO reset data toggle ? + return true; } @@ -881,8 +890,10 @@ static void qhd_remove_qtd(ehci_qhd_t *qhd) { qhd->attached_qtd = NULL; qhd->attached_buffer = 0; + hcd_dcache_clean(qhd, sizeof(ehci_qhd_t)); qtd->used = 0; // free QTD + hcd_dcache_clean(qtd, sizeof(ehci_qtd_t)); } //--------------------------------------------------------------------+ -- cgit v1.3.1 From 6021803d584a95efac5bc10f89ed970b2c1fa60e Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 28 Jul 2023 11:33:26 +0700 Subject: fix ci --- src/portable/renesas/rusb2/dcd_rusb2.c | 13 ++++++------- src/portable/renesas/rusb2/rusb2_ra.h | 9 ++++++--- 2 files changed, 12 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 83f0fdc4a..0380f36b9 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -49,17 +49,16 @@ #define D0FIFOCTR CFIFOCTR #define D0FIFOCTR_b CFIFOCTR_b #endif + + // Application API for setting IRQ number + void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) { + rusb2_controller[rhport].irqnum = irqnum; + } + #else #error "Unsupported MCU" #endif -//--------------------------------------------------------------------+ -// Application API for setting IRQ number -//--------------------------------------------------------------------+ -void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) { - rusb2_controller[rhport].irqnum = irqnum; -} - //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 8a4d2ad36..7ff272bbc 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -64,8 +64,14 @@ typedef struct { #if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8) #define RUSB2_SUPPORT_HIGHSPEED #define RUSB2_CONTROLLER_COUNT 2 + + #define rusb2_is_highspeed_rhport(_p) (_p == 1) + #define rusb2_is_highspeed_reg(_reg) (_reg == RUSB2_REG(1)) #else #define RUSB2_CONTROLLER_COUNT 1 + + #define rusb2_is_highspeed_rhport(_p) (false) + #define rusb2_is_highspeed_reg(_reg) (false) #endif // USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP @@ -78,9 +84,6 @@ static rusb2_controller_t rusb2_controller[] = { #define RUSB2_REG(_p) ((rusb2_reg_t*) rusb2_controller[_p].reg_base) -#define rusb2_is_highspeed_rhport(_p) (_p == 1) -#define rusb2_is_highspeed_reg(_reg) (_reg == RUSB2_REG(1)) - //--------------------------------------------------------------------+ // RUSB2 API //--------------------------------------------------------------------+ -- cgit v1.3.1 From e56d5443a8a87e932b22bc6315f30cd537fe0edf Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 28 Jul 2023 12:42:40 +0700 Subject: - revert usb address - more clean up --- src/portable/renesas/rusb2/dcd_rusb2.c | 6 +++--- src/portable/renesas/rusb2/hcd_rusb2.c | 14 ++++---------- 2 files changed, 7 insertions(+), 13 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 0380f36b9..9383923bd 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -51,7 +51,7 @@ #endif // Application API for setting IRQ number - void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) { + void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) { rusb2_controller[rhport].irqnum = irqnum; } @@ -638,7 +638,7 @@ static void process_bus_reset(uint8_t rhport) static void process_set_address(uint8_t rhport) { rusb2_reg_t* rusb = RUSB2_REG(rhport); - const uint32_t addr = rusb->USBADDR & 0xFF; + const uint16_t addr = rusb->USBADDR_b.USBADDR; if (!addr) return; const tusb_control_request_t setup_packet = { @@ -821,7 +821,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) if ( rusb2_is_highspeed_rhport(rhport) ) { // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed - // depending on the allocation scheme + // depending on the allocation scheme rusb->PIPEBUF = 0x7C08; } diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index fef8bdf19..c5ed8ae55 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -32,21 +32,15 @@ #include "host/hcd.h" #include "rusb2_type.h" -#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE) -// fallback -#define CFG_TUSB_RHPORT0_MODE OPT_MODE_HOST -#define CFG_TUSB_RHPORT1_MODE 0 -#endif - #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #include "rusb2_rx.h" #elif TU_CHECK_MCU(OPT_MCU_RAXXX) #include "rusb2_ra.h" - void osal_task_delay(uint32_t msec) { - R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS); - } +// void osal_task_delay(uint32_t msec) { +// R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS); +// } #else #error "Unsupported MCU" @@ -785,7 +779,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { void hcd_int_handler(uint8_t rhport) { rusb2_reg_t* rusb = RUSB2_REG(rhport); - static unsigned char attach_attempt = 0; + static unsigned char attach_attempt = 0; // TODO remove later unsigned is0 = rusb->INTSTS0; unsigned is1 = rusb->INTSTS1; -- cgit v1.3.1 From feb58ebd54e68bc3b7f21b0d168417053c525f0a Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 28 Jul 2023 19:01:12 +0700 Subject: add uno r4 wih FLASH_IMAGE_START=0x4000, running but interrupt (systick) does not seems to work --- .idea/runConfigurations/ra4m1.xml | 2 +- .idea/runConfigurations/ra6m1.xml | 2 +- .idea/runConfigurations/ra6m5.xml | 2 +- .../ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 18 ++--- hw/bsp/ra/boards/uno_r4/board.cmake | 11 +++ hw/bsp/ra/boards/uno_r4/board.h | 53 +++++++++++++ hw/bsp/ra/boards/uno_r4/board.mk | 9 +++ hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h | 35 +++++++++ .../boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 ++ .../uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 +++ .../boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 87 ++++++++++++++++++++++ hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h | 21 ++++++ hw/bsp/ra/boards/uno_r4/uno_r4.ld | 25 +++++++ hw/bsp/ra/family.mk | 3 +- src/portable/renesas/rusb2/hcd_rusb2.c | 1 + 15 files changed, 272 insertions(+), 13 deletions(-) create mode 100644 hw/bsp/ra/boards/uno_r4/board.cmake create mode 100644 hw/bsp/ra/boards/uno_r4/board.h create mode 100644 hw/bsp/ra/boards/uno_r4/board.mk create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/uno_r4.ld (limited to 'src') diff --git a/.idea/runConfigurations/ra4m1.xml b/.idea/runConfigurations/ra4m1.xml index 22bb61949..149a157c4 100644 --- a/.idea/runConfigurations/ra4m1.xml +++ b/.idea/runConfigurations/ra4m1.xml @@ -1,5 +1,5 @@ - + diff --git a/.idea/runConfigurations/ra6m1.xml b/.idea/runConfigurations/ra6m1.xml index 438ac4063..57af9abd9 100644 --- a/.idea/runConfigurations/ra6m1.xml +++ b/.idea/runConfigurations/ra6m1.xml @@ -1,5 +1,5 @@ - + diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml index 89f9787a0..1a6358304 100644 --- a/.idea/runConfigurations/ra6m5.xml +++ b/.idea/runConfigurations/ra6m5.xml @@ -1,5 +1,5 @@ - + diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h index 3bde2db0d..72cdb89e6 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -12,16 +12,16 @@ #define BSP_MOCO_HZ (8000000) #define BSP_SUB_CLOCK_HZ (32768) #if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (24000000) + #define BSP_HOCO_HZ (24000000) #elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (32000000) - #elif BSP_CFG_HOCO_FREQUENCY == 4 - #define BSP_HOCO_HZ (48000000) - #elif BSP_CFG_HOCO_FREQUENCY == 5 - #define BSP_HOCO_HZ (64000000) - #else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" - #endif + #define BSP_HOCO_HZ (32000000) +#elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (48000000) +#elif BSP_CFG_HOCO_FREQUENCY == 5 + #define BSP_HOCO_HZ (64000000) +#else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) diff --git a/hw/bsp/ra/boards/uno_r4/board.cmake b/hw/bsp/ra/boards/uno_r4/board.cmake new file mode 100644 index 000000000..34780d776 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/board.cmake @@ -0,0 +1,11 @@ +set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(MCU_VARIANT ra4m1) + +set(JLINK_DEVICE R7FA4M1AB) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld) + +function(update_board TARGET) +# target_compile_definitions(${TARGET} PUBLIC) +# target_sources(${TARGET} PRIVATE) +# target_include_directories(${BOARD_TARGET} PUBLIC) +endfunction() diff --git a/hw/bsp/ra/boards/uno_r4/board.h b/hw/bsp/ra/boards/uno_r4/board.h new file mode 100644 index 000000000..72abda27f --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/board.h @@ -0,0 +1,53 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define LED1 BSP_IO_PORT_01_PIN_11 // D13 +#define LED_STATE_ON 1 + +#define SW1 BSP_IO_PORT_01_PIN_10 // D12 +#define BUTTON_STATE_ACTIVE 0 + +static const ioport_pin_cfg_t board_pin_cfg[] = { + {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT}, + {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT}, + // USB FS D+, D-, VBus + {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, + {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, + {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/ra/boards/uno_r4/board.mk b/hw/bsp/ra/boards/uno_r4/board.mk new file mode 100644 index 000000000..cbe6c782c --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/board.mk @@ -0,0 +1,9 @@ +CPU_CORE = cortex-m4 +MCU_VARIANT = ra4m1 + +LD_FILE = $(BOARD_PATH)/${BOARD}.ld + +# For flash-jlink target +JLINK_DEVICE = R7FA4M1AB + +flash: flash-jlink diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..c1d1022cc --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,35 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" + +#undef RA_NOT_DEFINED +#define BSP_CFG_RTOS (0) +#if defined(_RA_BOOT_IMAGE) +#define BSP_CFG_BOOT_IMAGE (1) +#endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x800) +#define BSP_CFG_HEAP_BYTES (0x1000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0) + +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0) +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..444d32e56 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (4) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..336918800 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4M1AB3CNE +#define BSP_MCU_FEATURE_SET ('A') +#define BSP_ROM_SIZE_BYTES (262144) +#define BSP_RAM_SIZE_BYTES (32768) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_QFN +#define BSP_PACKAGE_PINS (48) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..fc604eb3b --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,87 @@ +/* generated configuration header file through renesas e2 studio */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "bsp_mcu_info.h" +#include "bsp_clock_cfg.h" + +#define BSP_MCU_GROUP_RA4M1 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (24000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (32000000) +#elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (48000000) +#elif BSP_CFG_HOCO_FREQUENCY == 5 + #define BSP_HOCO_HZ (64000000) +#else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) +#define BSP_MCU_VBATT_SUPPORT (1) + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) +#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +/* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ +#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) + #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) + #else +/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h new file mode 100644 index 000000000..63618ec4b --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h @@ -0,0 +1,21 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (0) /* XTAL 0Hz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL Src: XTAL */ +#define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_4) /* PLL Div /4 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(12, 0) /* PLL Mul x12 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Src: SUBCLK */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* UCLK Src: HOCO */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/uno_r4.ld b/hw/bsp/ra/boards/uno_r4/uno_r4.ld new file mode 100644 index 000000000..45f11dfb1 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/uno_r4.ld @@ -0,0 +1,25 @@ +RAM_START = 0x20000000; +RAM_LENGTH = 0x8000; +FLASH_START = 0x00000000; +FLASH_LENGTH = 0x40000; +DATA_FLASH_START = 0x40100000; +DATA_FLASH_LENGTH = 0x2000; +OPTION_SETTING_START = 0x00000000; +OPTION_SETTING_LENGTH = 0x0; +OPTION_SETTING_S_START = 0x80000000; +OPTION_SETTING_S_LENGTH = 0x0; +ID_CODE_START = 0x01010018; +ID_CODE_LENGTH = 0x20; +SDRAM_START = 0x80010000; +SDRAM_LENGTH = 0x0; +QSPI_FLASH_START = 0x60000000; +QSPI_FLASH_LENGTH = 0x0; +OSPI_DEVICE_0_START = 0x80020000; +OSPI_DEVICE_0_LENGTH = 0x0; +OSPI_DEVICE_1_START = 0x80030000; +OSPI_DEVICE_1_LENGTH = 0x0; + +/* Uno R4 has bootloader */ +FLASH_IMAGE_START = 0x4000; + +INCLUDE fsp.ld diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index f5097460a..a5325306d 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -59,9 +59,10 @@ INC += \ ifndef LD_FILE LD_FILE = $(FAMILY_PATH)/linker/gcc/$(MCU_VARIANT).ld -LDFLAGS += -L$(TOP)/$(FAMILY_PATH)/linker/gcc endif +LDFLAGS += -L$(TOP)/$(FAMILY_PATH)/linker/gcc + # For freeRTOS port source # hack to use the port provided by renesas FREERTOS_PORTABLE_SRC = $(FSP_RA)/src/rm_freertos_port diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index c5ed8ae55..7f49dc8a9 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -186,6 +186,7 @@ static inline void pipe_wait_for_ready(rusb2_reg_t* rusb, unsigned num) static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { + // NOTE: unlike DCD, Highspeed 32-bit FIFO does not need to adjust the fifo address volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; uintptr_t addr = (uintptr_t)buf; while (len >= 2) { -- cgit v1.3.1 From 0d9973ef87a55276d14c2aa45647f92a8358e9a2 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 31 Jul 2023 16:21:19 +0700 Subject: enable_irq since uno bootloader can disable it. systick triggered, however usb still not work with uno --- hw/bsp/ra/family.c | 4 ++++ src/portable/renesas/rusb2/dcd_rusb2.c | 1 + 2 files changed, 5 insertions(+) (limited to 'src') diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index b78fdedc7..096f0d0ff 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -92,6 +92,10 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT //--------------------------------------------------------------------+ void board_init(void) { + // Enable global interrupts in CPSR register since board with bootloader such as Arduino Uno R4 + // can transfer CPU control with CPSR.I bit set to 0 (disable IRQ) + __enable_irq(); + /* Configure pins. */ R_IOPORT_Open(&port_ctrl, &family_pin_cfg); diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 9383923bd..37fd93497 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -740,6 +740,7 @@ void dcd_init(uint8_t rhport) rusb->BEMPENB = 1; rusb->BRDYENB = 1; + // If VBUS (detect) pin is not used, application need to call tud_connect() manually after tud_init() if (rusb->INTSTS0_b.VBSTS) { dcd_connect(rhport); } -- cgit v1.3.1 From cb47231518d8a33bb9c5ab710c819049274d443b Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 31 Jul 2023 17:13:21 +0700 Subject: revert out of scope changes --- src/host/usbh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index c8eb91be3..15c48be47 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -258,7 +258,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t #if CFG_TUSB_OS == OPT_OS_NONE // TODO rework time-related function later -TU_ATTR_WEAK void osal_task_delay(uint32_t msec) +void osal_task_delay(uint32_t msec) { const uint32_t start = hcd_frame_number(_usbh_controller); while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {} -- cgit v1.3.1 From 3f788a4e5a7758ce51cbcadef4ac21e427cc3c56 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 31 Jul 2023 19:09:40 +0700 Subject: enable USBMC for uno r4, add board_init_after_tusb() API add BOARD_UPPERCASE for board detection --- examples/device/audio_4_channel_mic/src/main.c | 4 ++++ examples/device/audio_test/src/main.c | 4 ++++ examples/device/audio_test_multi_rate/src/main.c | 4 ++++ examples/device/cdc_dual_ports/src/main.c | 4 ++++ examples/device/cdc_msc/src/main.c | 4 ++++ examples/device/cdc_msc_freertos/src/main.c | 4 ++++ examples/device/dfu/src/main.c | 4 ++++ examples/device/dfu_runtime/src/main.c | 4 ++++ examples/device/dynamic_configuration/src/main.c | 4 ++++ examples/device/hid_boot_interface/src/main.c | 4 ++++ examples/device/hid_composite/src/main.c | 4 ++++ examples/device/hid_composite_freertos/src/main.c | 4 ++++ examples/device/hid_generic_inout/src/main.c | 4 ++++ examples/device/hid_multiple_interface/src/main.c | 4 ++++ examples/device/midi_test/src/main.c | 4 ++++ examples/device/msc_dual_lun/src/main.c | 4 ++++ examples/device/net_lwip_webserver/src/main.c | 4 ++++ examples/device/uac2_headset/src/main.c | 4 ++++ examples/device/usbtmc/src/main.c | 4 ++++ examples/device/video_capture/src/main.c | 4 ++++ examples/device/webusb_serial/src/main.c | 4 ++++ examples/dual/host_hid_to_device_cdc/src/main.c | 4 ++++ examples/host/bare_api/src/main.c | 4 ++++ examples/host/cdc_msc_hid/src/main.c | 4 ++++ examples/host/hid_controller/src/main.c | 4 ++++ examples/host/msc_file_explorer/src/main.c | 5 +++++ examples/make.mk | 2 ++ hw/bsp/board.h | 3 +++ hw/bsp/family_support.cmake | 5 +++++ hw/bsp/ra/boards/uno_r4/board.mk | 2 +- hw/bsp/ra/family.c | 7 +++++++ src/portable/renesas/rusb2/dcd_rusb2.c | 2 -- 32 files changed, 123 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c index 2b9c5143d..f5fc884bd 100644 --- a/examples/device/audio_4_channel_mic/src/main.c +++ b/examples/device/audio_4_channel_mic/src/main.c @@ -84,6 +84,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + // Init values sampFreq = AUDIO_SAMPLE_RATE; clkValid = 1; diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c index b5ca41d36..6dc655416 100644 --- a/examples/device/audio_test/src/main.c +++ b/examples/device/audio_test/src/main.c @@ -85,6 +85,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + // Init values sampFreq = AUDIO_SAMPLE_RATE; clkValid = 1; diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c index 078e783eb..637be2d40 100644 --- a/examples/device/audio_test_multi_rate/src/main.c +++ b/examples/device/audio_test_multi_rate/src/main.c @@ -99,6 +99,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + // Init values sampFreq = sampleRatesList[0]; clkValid = 1; diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c index 70eaea85d..7ceff73b3 100644 --- a/examples/device/cdc_dual_ports/src/main.c +++ b/examples/device/cdc_dual_ports/src/main.c @@ -42,6 +42,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c index 6dad73cbf..87fc33181 100644 --- a/examples/device/cdc_msc/src/main.c +++ b/examples/device/cdc_msc/src/main.c @@ -58,6 +58,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index 0e8a24d02..6cfef9ef5 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -136,6 +136,10 @@ void usb_device_task(void* param) // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + // RTOS forever loop while (1) { diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c index 5f37f25e1..bcd5b4942 100644 --- a/examples/device/dfu/src/main.c +++ b/examples/device/dfu/src/main.c @@ -77,6 +77,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c index 4ec3cb188..beef1037d 100644 --- a/examples/device/dfu_runtime/src/main.c +++ b/examples/device/dfu_runtime/src/main.c @@ -72,6 +72,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c index 578f01d8c..6c7789138 100644 --- a/examples/device/dynamic_configuration/src/main.c +++ b/examples/device/dynamic_configuration/src/main.c @@ -59,6 +59,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c index 1a155996a..47f68f8fa 100644 --- a/examples/device/hid_boot_interface/src/main.c +++ b/examples/device/hid_boot_interface/src/main.c @@ -59,6 +59,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c index 8d0e6bece..d4c5f5b3e 100644 --- a/examples/device/hid_composite/src/main.c +++ b/examples/device/hid_composite/src/main.c @@ -60,6 +60,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c index ca02af100..bdbe26b86 100644 --- a/examples/device/hid_composite_freertos/src/main.c +++ b/examples/device/hid_composite_freertos/src/main.c @@ -138,6 +138,10 @@ void usb_device_task(void* param) // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + // RTOS forever loop while (1) { diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c index 5db8f5581..5b3e53b06 100644 --- a/examples/device/hid_generic_inout/src/main.c +++ b/examples/device/hid_generic_inout/src/main.c @@ -83,6 +83,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c index 72240b208..94f845a84 100644 --- a/examples/device/hid_multiple_interface/src/main.c +++ b/examples/device/hid_multiple_interface/src/main.c @@ -64,6 +64,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c index 2c3e9d954..c77207ca2 100644 --- a/examples/device/midi_test/src/main.c +++ b/examples/device/midi_test/src/main.c @@ -65,6 +65,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c index c7f6de7bf..d8abb5151 100644 --- a/examples/device/msc_dual_lun/src/main.c +++ b/examples/device/msc_dual_lun/src/main.c @@ -57,6 +57,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c index 19a0eae9d..22543880e 100644 --- a/examples/device/net_lwip_webserver/src/main.c +++ b/examples/device/net_lwip_webserver/src/main.c @@ -232,6 +232,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + /* initialize lwip, dhcp-server, dns-server, and http */ init_lwip(); while (!netif_is_up(&netif_data)); diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c index 19a3f7bae..c502eb10d 100644 --- a/examples/device/uac2_headset/src/main.c +++ b/examples/device/uac2_headset/src/main.c @@ -105,6 +105,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + TU_LOG1("Headset running\r\n"); while (1) diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c index 2bba336f1..fa7de7570 100644 --- a/examples/device/usbtmc/src/main.c +++ b/examples/device/usbtmc/src/main.c @@ -57,6 +57,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index 5654e0b61..b942dd30e 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -59,6 +59,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c index eaca78c73..f63d0ccea 100644 --- a/examples/device/webusb_serial/src/main.c +++ b/examples/device/webusb_serial/src/main.c @@ -96,6 +96,10 @@ int main(void) // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c index 817c63c70..5a31b9dda 100644 --- a/examples/dual/host_hid_to_device_cdc/src/main.c +++ b/examples/dual/host_hid_to_device_cdc/src/main.c @@ -83,6 +83,10 @@ int main(void) tud_init(BOARD_TUD_RHPORT); tuh_init(BOARD_TUH_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { tud_task(); // tinyusb device task diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c index bb7fa850e..7286befe0 100644 --- a/examples/host/bare_api/src/main.c +++ b/examples/host/bare_api/src/main.c @@ -67,6 +67,10 @@ int main(void) // init host stack on configured roothub port tuh_init(BOARD_TUH_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { // tinyusb host task diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c index 1f4acb822..51251be5c 100644 --- a/examples/host/cdc_msc_hid/src/main.c +++ b/examples/host/cdc_msc_hid/src/main.c @@ -48,6 +48,10 @@ int main(void) // init host stack on configured roothub port tuh_init(BOARD_TUH_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { // tinyusb host task diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c index 4dcc92587..a4ab2f711 100644 --- a/examples/host/hid_controller/src/main.c +++ b/examples/host/hid_controller/src/main.c @@ -54,6 +54,10 @@ int main(void) // init host stack on configured roothub port tuh_init(BOARD_TUH_RHPORT); + if (board_init_after_tusb) { + board_init_after_tusb(); + } + while (1) { // tinyusb host task diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c index 7b1c2ef27..fc4b4e669 100644 --- a/examples/host/msc_file_explorer/src/main.c +++ b/examples/host/msc_file_explorer/src/main.c @@ -80,6 +80,11 @@ int main(void) // init host stack on configured roothub port tuh_init(BOARD_TUH_RHPORT); + + if (board_init_after_tusb) { + board_init_after_tusb(); + } + msc_app_init(); while (1) diff --git a/examples/make.mk b/examples/make.mk index 3c3a920cc..4001a5359 100644 --- a/examples/make.mk +++ b/examples/make.mk @@ -116,6 +116,8 @@ INC += \ $(TOP)/$(FAMILY_PATH) \ $(TOP)/src \ +BOARD_UPPER = $(shell echo $(BOARD) | tr a-z A-Z) +CFLAGS += -DBOARD_$(BOARD_UPPER) # Log level is mapped to TUSB DEBUG option ifneq ($(LOG),) diff --git a/hw/bsp/board.h b/hw/bsp/board.h index 036556731..d782013bb 100644 --- a/hw/bsp/board.h +++ b/hw/bsp/board.h @@ -54,6 +54,9 @@ // Initialize on-board peripherals : led, button, uart and USB void board_init(void); +// Init board after tinyusb is initialized +void board_init_after_tusb(void) TU_ATTR_WEAK; + // Turn LED on or off void board_led_write(bool state); diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index d8298c8ad..db1ce988e 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -181,6 +181,11 @@ endfunction() function(family_configure_common TARGET RTOS) family_add_rtos(${TARGET} ${RTOS}) + string(TOUPPER ${BOARD} BOARD_UPPER) + target_compile_definitions(${TARGET} PUBLIC + BOARD_${BOARD_UPPER} + ) + # run size after build add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_SIZE} $ diff --git a/hw/bsp/ra/boards/uno_r4/board.mk b/hw/bsp/ra/boards/uno_r4/board.mk index cbe6c782c..b7075eec0 100644 --- a/hw/bsp/ra/boards/uno_r4/board.mk +++ b/hw/bsp/ra/boards/uno_r4/board.mk @@ -1,7 +1,7 @@ CPU_CORE = cortex-m4 MCU_VARIANT = ra4m1 -LD_FILE = $(BOARD_PATH)/${BOARD}.ld +LD_FILE = ${BOARD_PATH}/${BOARD}.ld # For flash-jlink target JLINK_DEVICE = R7FA4M1AB diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 096f0d0ff..e6213061d 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -124,6 +124,13 @@ void board_init(void) { board_led_write(false); } +void board_init_after_tusb(void) { + // For board that use USB LDO regulator +#if defined(BOARD_UNO_R4) + R_USB_FS0->USBMC |= R_USB_FS0_USBMC_VDCEN_Msk; +#endif +} + void board_led_write(bool state) { R_IOPORT_PinWrite(&port_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON); } diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 37fd93497..9a3983f56 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -726,8 +726,6 @@ void dcd_init(uint8_t rhport) rusb->PHYSLEW = 0x5; rusb->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */ - - // rusb2->USBMC = (uint16_t) (rusb2->USBMC | RUSB2_USBMC_VDCEN_Msk); } /* Setup default control pipe */ -- cgit v1.3.1 From 965627e81c63a76bb80d8319cbd9adf931a00595 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 1 Aug 2023 11:41:33 +0200 Subject: rusb2: move dynamic irq function to c file --- hw/bsp/ra/family.cmake | 5 +++-- hw/bsp/ra/family.mk | 1 + src/portable/renesas/rusb2/dcd_rusb2.c | 5 ----- src/portable/renesas/rusb2/rusb2_ra.c | 16 ++++++++++++++++ src/portable/renesas/rusb2/rusb2_ra.h | 9 +-------- 5 files changed, 21 insertions(+), 15 deletions(-) create mode 100644 src/portable/renesas/rusb2/rusb2_ra.c (limited to 'src') diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 307e01da8..2d079dc94 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -114,8 +114,9 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_RAXXX ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c - ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c + ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c + ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c + ${TOP}/src/portable/renesas/rusb2/rusb2_ra.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index cf8e5d9e9..3394d41b4 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -32,6 +32,7 @@ endif SRC_C += \ src/portable/renesas/rusb2/dcd_rusb2.c \ src/portable/renesas/rusb2/hcd_rusb2.c \ + src/portable/renesas/rusb2/rusb2_ra.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \ $(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \ diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 9a3983f56..3ec1b70b5 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -50,11 +50,6 @@ #define D0FIFOCTR_b CFIFOCTR_b #endif - // Application API for setting IRQ number - void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) { - rusb2_controller[rhport].irqnum = irqnum; - } - #else #error "Unsupported MCU" #endif diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c new file mode 100644 index 000000000..bbffd712e --- /dev/null +++ b/src/portable/renesas/rusb2/rusb2_ra.c @@ -0,0 +1,16 @@ +#include "tusb_option.h" +#include "device/dcd.h" +#include "rusb2_type.h" +#include "rusb2_ra.h" + +rusb2_controller_t rusb2_controller[] = { + { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn }, + #ifdef RUSB2_SUPPORT_HIGHSPEED + { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn }, + #endif +}; + +// Application API for setting IRQ number +void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) { + rusb2_controller[rhport].irqnum = irqnum; +} \ No newline at end of file diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 7ff272bbc..4774d2e2c 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -74,14 +74,7 @@ typedef struct { #define rusb2_is_highspeed_reg(_reg) (false) #endif -// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP -static rusb2_controller_t rusb2_controller[] = { - { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn }, - #ifdef RUSB2_SUPPORT_HIGHSPEED - { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn }, - #endif -}; - +extern rusb2_controller_t rusb2_controller[]; #define RUSB2_REG(_p) ((rusb2_reg_t*) rusb2_controller[_p].reg_base) //--------------------------------------------------------------------+ -- cgit v1.3.1 From 04f1a34c39e109002c89e464103ebed6128c2903 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 1 Aug 2023 17:03:07 +0700 Subject: add rusb2_common.c for dynami irq --- hw/bsp/ra/family.cmake | 1 + hw/bsp/ra/family.mk | 1 + src/portable/renesas/rusb2/dcd_rusb2.c | 5 --- src/portable/renesas/rusb2/hcd_rusb2.c | 6 --- src/portable/renesas/rusb2/rusb2_common.c | 61 +++++++++++++++++++++++++++++++ src/portable/renesas/rusb2/rusb2_ra.h | 8 +--- src/portable/renesas/rusb2/rusb2_type.h | 1 + 7 files changed, 65 insertions(+), 18 deletions(-) create mode 100644 src/portable/renesas/rusb2/rusb2_common.c (limited to 'src') diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 307e01da8..11bc7c668 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -116,6 +116,7 @@ function(family_configure_example TARGET RTOS) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c + ${TOP}/src/portable/renesas/rusb2/rusb2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index 901808958..9afb38e06 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -34,6 +34,7 @@ endif SRC_C += \ src/portable/renesas/rusb2/dcd_rusb2.c \ src/portable/renesas/rusb2/hcd_rusb2.c \ + src/portable/renesas/rusb2/rusb2_common.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \ $(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \ diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 9a3983f56..3ec1b70b5 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -50,11 +50,6 @@ #define D0FIFOCTR_b CFIFOCTR_b #endif - // Application API for setting IRQ number - void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) { - rusb2_controller[rhport].irqnum = irqnum; - } - #else #error "Unsupported MCU" #endif diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 7f49dc8a9..621320095 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -34,14 +34,8 @@ #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #include "rusb2_rx.h" - #elif TU_CHECK_MCU(OPT_MCU_RAXXX) #include "rusb2_ra.h" - -// void osal_task_delay(uint32_t msec) { -// R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS); -// } - #else #error "Unsupported MCU" #endif diff --git a/src/portable/renesas/rusb2/rusb2_common.c b/src/portable/renesas/rusb2/rusb2_common.c new file mode 100644 index 000000000..850060777 --- /dev/null +++ b/src/portable/renesas/rusb2/rusb2_common.c @@ -0,0 +1,61 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if defined(TUP_USBIP_RUSB2) && (CFG_TUH_ENABLED || CFG_TUD_ENABLED) + +#include "rusb2_type.h" + +#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) +#include "rusb2_rx.h" + +#elif TU_CHECK_MCU(OPT_MCU_RAXXX) +#include "rusb2_ra.h" + +// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP +rusb2_controller_t rusb2_controller[] = { + { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn }, + #ifdef RUSB2_SUPPORT_HIGHSPEED + { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn }, + #endif +}; + +// Application API for setting IRQ number. May throw warnings for missing prototypes. +void tusb_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) { + rusb2_controller[rhport].irqnum = irqnum; +} + +// void osal_task_delay(uint32_t msec) { +// R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS); +// } + +#else + #error "Unsupported MCU" +#endif + + +#endif diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h index 7ff272bbc..259d3cbdb 100644 --- a/src/portable/renesas/rusb2/rusb2_ra.h +++ b/src/portable/renesas/rusb2/rusb2_ra.h @@ -74,13 +74,7 @@ typedef struct { #define rusb2_is_highspeed_reg(_reg) (false) #endif -// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP -static rusb2_controller_t rusb2_controller[] = { - { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn }, - #ifdef RUSB2_SUPPORT_HIGHSPEED - { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn }, - #endif -}; +extern rusb2_controller_t rusb2_controller[]; #define RUSB2_REG(_p) ((rusb2_reg_t*) rusb2_controller[_p].reg_base) diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index 005d7f2be..dd88f66a7 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -28,6 +28,7 @@ #define _TUSB_RUSB2_TYPE_H_ #include +#include #ifdef __cplusplus extern "C" { -- cgit v1.3.1 From edee46e7941f56f5024bf60d56921cfe10d1f7a5 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 1 Aug 2023 15:21:31 +0200 Subject: renesas: host: remove attach_attempt logic --- src/portable/renesas/rusb2/hcd_rusb2.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 621320095..f6683529a 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -774,7 +774,6 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { void hcd_int_handler(uint8_t rhport) { rusb2_reg_t* rusb = RUSB2_REG(rhport); - static unsigned char attach_attempt = 0; // TODO remove later unsigned is0 = rusb->INTSTS0; unsigned is1 = rusb->INTSTS1; @@ -789,23 +788,14 @@ void hcd_int_handler(uint8_t rhport) if (is1 & RUSB2_INTSTS1_SACK_Msk) { /* Set DATA1 in advance for the next transfer. */ rusb->DCPCTR_b.SQSET = 1; - attach_attempt = 0; hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true); } if (is1 & RUSB2_INTSTS1_SIGN_Msk) { hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true); - if(attach_attempt > 0) { - rusb->DVSTCTR0_b.UACT = 1; - _hcd.need_reset = true; - rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; - hcd_event_device_attach(rhport, true); - } - attach_attempt--; } if (is1 & RUSB2_INTSTS1_ATTCH_Msk) { - attach_attempt = 10; rusb->DVSTCTR0_b.UACT = 1; _hcd.need_reset = true; rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk; -- cgit v1.3.1 From 979bf32266d379ec493ad31001b815d6a597b91e Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 2 Aug 2023 15:34:18 +0700 Subject: default class driver log level to CFG_TUH/TUD_LOG_LEVEL allow application to selectively disable usbd/usbh or driver log --- src/class/cdc/cdc_device.c | 15 +++++++++++---- src/class/cdc/cdc_host.c | 9 ++++++--- src/class/dfu/dfu_device.c | 11 +++++++++-- src/class/dfu/dfu_rt_device.c | 13 ++++++++++--- src/class/hid/hid_host.c | 8 +++++--- src/class/msc/msc_device.c | 2 +- src/class/msc/msc_host.c | 19 +++++++++++-------- src/class/net/ncm_device.c | 11 +++++++++-- src/class/video/video_device.c | 23 +++++++++++++++-------- src/host/usbh.c | 7 ------- src/host/usbh_classdriver.h | 7 +++++++ 11 files changed, 84 insertions(+), 41 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index f658df4d0..70d9c2e24 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -33,6 +33,13 @@ #include "cdc_device.h" +// Level where CFG_TUSB_DEBUG must be at least for this driver is logged +#ifndef CFG_TUD_CDC_LOG_LEVEL + #define CFG_TUD_CDC_LOG_LEVEL CFG_TUD_LOG_LEVEL +#endif + +#define TU_LOG_DRV(...) TU_LOG(CFG_TUD_CDC_LOG_LEVEL, __VA_ARGS__) + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ @@ -353,7 +360,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t case CDC_REQUEST_SET_LINE_CODING: if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Set Line Coding\r\n"); + TU_LOG_DRV(" Set Line Coding\r\n"); tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t)); } else if ( stage == CONTROL_STAGE_ACK) @@ -365,7 +372,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t case CDC_REQUEST_GET_LINE_CODING: if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Get Line Coding\r\n"); + TU_LOG_DRV(" Get Line Coding\r\n"); tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t)); } break; @@ -390,7 +397,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t // Disable fifo overwriting if DTR bit is set tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr); - TU_LOG2(" Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts); + TU_LOG_DRV(" Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts); // Invoke callback if ( tud_cdc_line_state_cb ) tud_cdc_line_state_cb(itf, dtr, rts); @@ -403,7 +410,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t } else if (stage == CONTROL_STAGE_ACK) { - TU_LOG2(" Send Break\r\n"); + TU_LOG_DRV(" Send Break\r\n"); if ( tud_cdc_send_break_cb ) tud_cdc_send_break_cb(itf, request->wValue); } break; diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index ce9f27c33..7f9ed18b3 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -33,9 +33,12 @@ #include "cdc_host.h" -// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message -#define CDCH_DEBUG 2 -#define TU_LOG_DRV(...) TU_LOG(CDCH_DEBUG, __VA_ARGS__) +// Level where CFG_TUSB_DEBUG must be at least for this driver is logged +#ifndef CFG_TUH_CDC_LOG_LEVEL + #define CFG_TUH_CDC_LOG_LEVEL CFG_TUH_LOG_LEVEL +#endif + +#define TU_LOG_DRV(...) TU_LOG(CFG_TUH_CDC_LOG_LEVEL, __VA_ARGS__) //--------------------------------------------------------------------+ // Host CDC Interface diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c index bffdb8376..3e7c13dea 100644 --- a/src/class/dfu/dfu_device.c +++ b/src/class/dfu/dfu_device.c @@ -37,6 +37,13 @@ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ +// Level where CFG_TUSB_DEBUG must be at least for this driver is logged +#ifndef CFG_TUD_DFU_LOG_LEVEL + #define CFG_TUD_DFU_LOG_LEVEL CFG_TUD_LOG_LEVEL +#endif + +#define TU_LOG_DRV(...) TU_LOG(CFG_TUD_DFU_LOG_LEVEL, __VA_ARGS__) + //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ @@ -205,7 +212,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque { TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE); - TU_LOG2(" DFU State : %s, Status: %s\r\n", tu_lookup_find(&_dfu_state_table, _dfu_ctx.state), tu_lookup_find(&_dfu_status_table, _dfu_ctx.status)); + TU_LOG_DRV(" DFU State : %s, Status: %s\r\n", tu_lookup_find(&_dfu_state_table, _dfu_ctx.state), tu_lookup_find(&_dfu_status_table, _dfu_ctx.status)); if ( request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD ) { @@ -235,7 +242,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque } else if ( request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS ) { - TU_LOG2(" DFU Request: %s\r\n", tu_lookup_find(&_dfu_request_table, request->bRequest)); + TU_LOG_DRV(" DFU Request: %s\r\n", tu_lookup_find(&_dfu_request_table, request->bRequest)); // Class request switch ( request->bRequest ) diff --git a/src/class/dfu/dfu_rt_device.c b/src/class/dfu/dfu_rt_device.c index 7b77b3f8f..a940d8d62 100644 --- a/src/class/dfu/dfu_rt_device.c +++ b/src/class/dfu/dfu_rt_device.c @@ -37,6 +37,13 @@ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ +// Level where CFG_TUSB_DEBUG must be at least for this driver is logged +#ifndef CFG_TUD_DFU_RUNTIME_LOG_LEVEL + #define CFG_TUD_DFU_RUNTIME_LOG_LEVEL CFG_TUD_LOG_LEVEL +#endif + +#define TU_LOG_DRV(...) TU_LOG(CFG_TUD_DFU_RUNTIME_LOG_LEVEL, __VA_ARGS__) + //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ @@ -99,7 +106,7 @@ bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request { case DFU_REQUEST_DETACH: { - TU_LOG2(" DFU RT Request: DETACH\r\n"); + TU_LOG_DRV(" DFU RT Request: DETACH\r\n"); tud_control_status(rhport, request); tud_dfu_runtime_reboot_to_dfu_cb(); } @@ -107,7 +114,7 @@ bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request case DFU_REQUEST_GETSTATUS: { - TU_LOG2(" DFU RT Request: GETSTATUS\r\n"); + TU_LOG_DRV(" DFU RT Request: GETSTATUS\r\n"); dfu_status_response_t resp; // Status = OK, Poll timeout is ignored during RT, State = APP_IDLE, IString = 0 TU_VERIFY(tu_memset_s(&resp, sizeof(resp), 0x00, sizeof(resp))==0); @@ -117,7 +124,7 @@ bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request default: { - TU_LOG2(" DFU RT Unexpected Request: %d\r\n", request->bRequest); + TU_LOG_DRV(" DFU RT Unexpected Request: %d\r\n", request->bRequest); return false; // stall unsupported request } } diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 6abe298e5..4253170d4 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -33,10 +33,12 @@ #include "hid_host.h" -// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message -#define HIDH_DEBUG 2 -#define TU_LOG_DRV(...) TU_LOG(HIDH_DEBUG, __VA_ARGS__) +// Level where CFG_TUSB_DEBUG must be at least for this driver is logged +#ifndef CFG_TUH_HID_LOG_LEVEL + #define CFG_TUH_HID_LOG_LEVEL CFG_TUH_LOG_LEVEL +#endif +#define TU_LOG_DRV(...) TU_LOG(CFG_TUH_HID_LOG_LEVEL, __VA_ARGS__) //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index a602e9672..2589dcd2c 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -36,7 +36,7 @@ // Level where CFG_TUSB_DEBUG must be at least for this driver is logged #ifndef CFG_TUD_MSC_LOG_LEVEL - #define CFG_TUD_MSC_LOG_LEVEL 2 + #define CFG_TUD_MSC_LOG_LEVEL CFG_TUD_LOG_LEVEL #endif #define TU_LOG_DRV(...) TU_LOG(CFG_TUD_MSC_LOG_LEVEL, __VA_ARGS__) diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c index d32c0adb0..a65208d69 100644 --- a/src/class/msc/msc_host.c +++ b/src/class/msc/msc_host.c @@ -33,9 +33,12 @@ #include "msc_host.h" -// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message -#define MSCH_DEBUG 2 -#define TU_LOG_MSCH(...) TU_LOG(MSCH_DEBUG, __VA_ARGS__) +// Level where CFG_TUSB_DEBUG must be at least for this driver is logged +#ifndef CFG_TUH_MSC_LOG_LEVEL + #define CFG_TUH_MSC_LOG_LEVEL CFG_TUH_LOG_LEVEL +#endif + +#define TU_LOG_DRV(...) TU_LOG(CFG_TUH_MSC_LOG_LEVEL, __VA_ARGS__) //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF @@ -308,7 +311,7 @@ void msch_close(uint8_t dev_addr) msch_interface_t* p_msc = get_itf(dev_addr); TU_VERIFY(p_msc->configured, ); - TU_LOG_MSCH(" MSCh close addr = %d\r\n", dev_addr); + TU_LOG_DRV(" MSCh close addr = %d\r\n", dev_addr); // invoke Application Callback if (p_msc->mounted) { @@ -426,7 +429,7 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num) p_msc->configured = true; //------------- Get Max Lun -------------// - TU_LOG_MSCH("MSC Get Max Lun\r\n"); + TU_LOG_DRV("MSC Get Max Lun\r\n"); tusb_control_request_t const request = { .bmRequestType_bit = @@ -465,7 +468,7 @@ static void config_get_maxlun_complete (tuh_xfer_t* xfer) p_msc->max_lun++; // MAX LUN is minus 1 by specs // TODO multiple LUN support - TU_LOG_MSCH("SCSI Test Unit Ready\r\n"); + TU_LOG_DRV("SCSI Test Unit Ready\r\n"); uint8_t const lun = 0; tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete, 0); } @@ -478,14 +481,14 @@ static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_d if (csw->status == 0) { // Unit is ready, read its capacity - TU_LOG_MSCH("SCSI Read Capacity\r\n"); + TU_LOG_DRV("SCSI Read Capacity\r\n"); tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer), config_read_capacity_complete, 0); }else { // Note: During enumeration, some device fails Test Unit Ready and require a few retries // with Request Sense to start working !! // TODO limit number of retries - TU_LOG_MSCH("SCSI Request Sense\r\n"); + TU_LOG_DRV("SCSI Request Sense\r\n"); TU_ASSERT(tuh_msc_request_sense(dev_addr, cbw->lun, _msch_buffer, config_request_sense_complete, 0)); } diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c index 611dc3348..226c42c4e 100644 --- a/src/class/net/ncm_device.c +++ b/src/class/net/ncm_device.c @@ -34,6 +34,13 @@ #include "device/usbd_pvt.h" #include "net_device.h" +// Level where CFG_TUSB_DEBUG must be at least for this driver is logged +#ifndef CFG_TUD_NCM_LOG_LEVEL + #define CFG_TUD_NCM_LOG_LEVEL CFG_TUD_LOG_LEVEL +#endif + +#define TU_LOG_DRV(...) TU_LOG(CFG_TUD_NCM_LOG_LEVEL, __VA_ARGS__) + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ @@ -473,13 +480,13 @@ bool tud_network_can_xmit(uint16_t size) TU_VERIFY(ncm_interface.itf_data_alt == 1); if (ncm_interface.datagram_count >= ncm_interface.max_datagrams_per_ntb) { - TU_LOG2("NTB full [by count]\r\n"); + TU_LOG_DRV("NTB full [by count]\r\n"); return false; } size_t next_datagram_offset = ncm_interface.next_datagram_offset; if (next_datagram_offset + size > ncm_interface.ntb_in_size) { - TU_LOG2("ntb full [by size]\r\n"); + TU_LOG_DRV("ntb full [by size]\r\n"); return false; } diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index e6fadf41b..abc43ccff 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -34,6 +34,13 @@ #include "video_device.h" +// Level where CFG_TUSB_DEBUG must be at least for this driver is logged +#ifndef CFG_TUD_VIDEO_LOG_LEVEL + #define CFG_TUD_VIDEO_LOG_LEVEL CFG_TUD_LOG_LEVEL +#endif + +#define TU_LOG_DRV(...) TU_LOG(CFG_TUD_VIDEO_LOG_LEVEL, __VA_ARGS__) + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ @@ -609,17 +616,17 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) * @param[in] altnum The target alternate setting number. */ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum) { - TU_LOG2(" open VC %d\n", altnum); + TU_LOG_DRV(" open VC %d\n", altnum); uint8_t const *beg = self->beg; uint8_t const *end = beg + self->len; /* The first descriptor is a video control interface descriptor. */ uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); - TU_LOG2(" cur %d\n", cur - beg); + TU_LOG_DRV(" cur %d\n", cur - beg); TU_VERIFY(cur < end); tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur; - TU_LOG2(" bInCollection %d\n", vc->ctl.bInCollection); + TU_LOG_DRV(" bInCollection %d\n", vc->ctl.bInCollection); /* Support for up to 2 streaming interfaces only. */ TU_ASSERT(vc->ctl.bInCollection <= CFG_TUD_VIDEO_STREAMING); @@ -628,7 +635,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t /* Advance to the next descriptor after the class-specific VC interface header descriptor. */ cur += vc->std.bLength + vc->ctl.bLength; - TU_LOG2(" bNumEndpoints %d\n", vc->std.bNumEndpoints); + TU_LOG_DRV(" bNumEndpoints %d\n", vc->std.bNumEndpoints); /* Open the notification endpoint if it exist. */ if (vc->std.bNumEndpoints) { /* Support for 1 endpoint only. */ @@ -662,7 +669,7 @@ static bool _init_vs_configuration(videod_streaming_interface_t *stm) static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint_fast8_t altnum) { uint_fast8_t i; - TU_LOG2(" reopen VS %d\n", altnum); + TU_LOG_DRV(" reopen VS %d\n", altnum); uint8_t const *desc = _videod_itf[stm->index_vc].beg; /* Close endpoints of previous settings. */ @@ -672,7 +679,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint uint8_t ep_adr = _desc_ep_addr(desc + ofs_ep); usbd_edpt_close(rhport, ep_adr); stm->desc.ep[i] = 0; - TU_LOG2(" close EP%02x\n", ep_adr); + TU_LOG_DRV(" close EP%02x\n", ep_adr); } /* clear transfer management information */ @@ -709,12 +716,12 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint } TU_ASSERT(usbd_edpt_open(rhport, ep)); stm->desc.ep[i] = (uint16_t) (cur - desc); - TU_LOG2(" open EP%02x\n", _desc_ep_addr(cur)); + TU_LOG_DRV(" open EP%02x\n", _desc_ep_addr(cur)); } if (altnum) { stm->state = VS_STATE_STREAMING; } - TU_LOG2(" done\n"); + TU_LOG_DRV(" done\n"); return true; } diff --git a/src/host/usbh.c b/src/host/usbh.c index c8eb91be3..49f8c78f1 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -45,13 +45,6 @@ #define CFG_TUH_INTERFACE_MAX 8 #endif -// Level where CFG_TUSB_DEBUG must be at least for USBH is logged -#ifndef CFG_TUH_LOG_LEVEL - #define CFG_TUH_LOG_LEVEL 2 -#endif - -#define TU_LOG_USBH(...) TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__) - //--------------------------------------------------------------------+ // USBH-HCD common data structure //--------------------------------------------------------------------+ diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h index be9811641..308b4418a 100644 --- a/src/host/usbh_classdriver.h +++ b/src/host/usbh_classdriver.h @@ -35,6 +35,13 @@ extern "C" { #endif +// Level where CFG_TUSB_DEBUG must be at least for USBH is logged +#ifndef CFG_TUH_LOG_LEVEL + #define CFG_TUH_LOG_LEVEL 2 +#endif + +#define TU_LOG_USBH(...) TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__) + enum { USBH_EPSIZE_BULK_MAX = (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS) }; -- cgit v1.3.1 From 9560d0813f0872a1b8dfb337922b0ab5cc4cb811 Mon Sep 17 00:00:00 2001 From: Rocky04 Date: Wed, 2 Aug 2023 15:25:08 +0200 Subject: Set unmounted on configuration reset --- src/device/usbd.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index 9429cf664..b4ca63c9c 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -965,7 +965,14 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num) } // invoke callback - if (tud_mount_cb) tud_mount_cb(); + if (cfg_num) + { + if (tud_mount_cb) tud_mount_cb(); + } + else + { + if (tud_umount_cb) tud_umount_cb(); + } return true; } -- cgit v1.3.1 From d09604d6364f4840669eda66a75f5df0926bb3e0 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 3 Aug 2023 11:07:23 +0700 Subject: Revert "Name queues for easier FreeRTOS debugging with task- and queue-aware debuggers" This reverts commit 11fba59319d81fb9502fbf399abb4fe27cf3fa29. --- src/device/usbd.c | 4 ++-- src/host/usbh.c | 4 ++-- src/osal/osal_freertos.h | 5 ++--- 3 files changed, 6 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index b6c679b22..44c2530ce 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -279,7 +279,7 @@ tu_static uint8_t _usbd_rhport = RHPORT_INVALID; // Event queue // usbd_int_set() is used as mutex in OS NONE config -OSAL_QUEUE_DEF(usbd_int_set, usbd_events, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t); +OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t); tu_static osal_queue_t _usbd_q; // Mutex for claiming endpoint @@ -410,7 +410,7 @@ bool tud_init (uint8_t rhport) #endif // Init device queue & task - _usbd_q = osal_queue_create(&usbd_events); + _usbd_q = osal_queue_create(&_usbd_qdef); TU_ASSERT(_usbd_q); // Get application driver if available diff --git a/src/host/usbh.c b/src/host/usbh.c index 987ff7a6e..f3e9d3858 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -219,7 +219,7 @@ static usbh_device_t _usbh_devices[TOTAL_DEVICES]; // Event queue // usbh_int_set is used as mutex in OS NONE config -OSAL_QUEUE_DEF(usbh_int_set, usbh_events, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t); +OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t); static osal_queue_t _usbh_q; CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN @@ -330,7 +330,7 @@ bool tuh_init(uint8_t controller_id) TU_LOG_INT(USBH_DEBUG, sizeof(tu_edpt_stream_t)); // Event queue - _usbh_q = osal_queue_create( &usbh_events ); + _usbh_q = osal_queue_create( &_usbh_qdef ); TU_ASSERT(_usbh_q != NULL); #if OSAL_MUTEX_REQUIRED diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index e83277eb3..0b1b11589 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -56,7 +56,7 @@ typedef SemaphoreHandle_t osal_mutex_t; // _int_set is not used with an RTOS #define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \ static _type _name##_##buf[_depth];\ - osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, .pQueueName = #_name }; + osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf }; typedef struct { @@ -66,7 +66,6 @@ typedef struct #if configSUPPORT_STATIC_ALLOCATION StaticQueue_t sq; #endif - const char* pQueueName; }osal_queue_def_t; typedef QueueHandle_t osal_queue_t; @@ -177,7 +176,7 @@ TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_de q = xQueueCreate(qdef->depth, qdef->item_sz); #endif #if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0) - vQueueAddToRegistry(q, qdef->pQueueName); + vQueueAddToRegistry(q, "tinyUSB"); #endif return q; } -- cgit v1.3.1 From 473f37df958f74153f15c050c20d63f8defe89ed Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 3 Aug 2023 12:05:21 +0700 Subject: add osal queue name if needed also mass change configQUEUE_REGISTRY_SIZE = 4 --- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- src/osal/osal_freertos.h | 108 ++++++++++----------- 18 files changed, 68 insertions(+), 74 deletions(-) (limited to 'src') diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index 9bef9bbbf..69d638288 100644 --- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -81,7 +81,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index 9bef9bbbf..69d638288 100644 --- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -81,7 +81,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h index f95927069..b65d8f1f9 100644 --- a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h @@ -66,7 +66,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h index a46af1759..2a2bce261 100644 --- a/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h @@ -66,7 +66,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h index 1b3c64e0b..ea568dfc9 100644 --- a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h @@ -66,7 +66,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 3 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h index 96611ca1c..a48b54576 100644 --- a/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h @@ -66,7 +66,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h index b1cef793e..fc0ab1f2d 100644 --- a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h @@ -66,7 +66,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h index b1cef793e..fc0ab1f2d 100644 --- a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h @@ -66,7 +66,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h index a56f243ea..efd26a3a7 100644 --- a/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h @@ -66,7 +66,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h index 8c39a2fb8..4ef5dd883 100644 --- a/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h @@ -81,7 +81,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h index fc2f9fc67..33440d288 100644 --- a/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h @@ -66,7 +66,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h index 5a6b2300b..580fe02bb 100644 --- a/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h @@ -66,7 +66,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h index 815e567dd..4615640ed 100644 --- a/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h @@ -66,7 +66,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h index c8736f6d1..02bfaf97a 100644 --- a/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h @@ -66,7 +66,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h index 95fcbb08a..17c2a0c5c 100644 --- a/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h @@ -66,7 +66,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h index 6881385a8..6a1f6c043 100644 --- a/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h @@ -66,7 +66,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h index e6a735ddd..c12b0dc85 100644 --- a/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h @@ -66,7 +66,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index 0b1b11589..501e0bddd 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -52,53 +52,60 @@ extern "C" { typedef SemaphoreHandle_t osal_semaphore_t; typedef SemaphoreHandle_t osal_mutex_t; - -// _int_set is not used with an RTOS -#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \ - static _type _name##_##buf[_depth];\ - osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf }; +typedef QueueHandle_t osal_queue_t; typedef struct { uint16_t depth; uint16_t item_sz; void* buf; + +#if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0) + char const* name; +#endif + #if configSUPPORT_STATIC_ALLOCATION StaticQueue_t sq; #endif -}osal_queue_def_t; +} osal_queue_def_t; -typedef QueueHandle_t osal_queue_t; +#if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0) + #define _OSAL_Q_NAME(_name) .name = #_name +#else + #define _OSAL_Q_NAME(_name) +#endif + +// _int_set is not used with an RTOS +#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \ + static _type _name##_##buf[_depth];\ + osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, _OSAL_Q_NAME(_name) }; //--------------------------------------------------------------------+ // TASK API //--------------------------------------------------------------------+ -TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec) -{ - if (msec == OSAL_TIMEOUT_WAIT_FOREVER) return portMAX_DELAY; - if (msec == 0) return 0; +TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec) { + if ( msec == OSAL_TIMEOUT_WAIT_FOREVER ) return portMAX_DELAY; + if ( msec == 0 ) return 0; uint32_t ticks = pdMS_TO_TICKS(msec); // configTICK_RATE_HZ is less than 1000 and 1 tick > 1 ms // we still need to delay at least 1 tick - if (ticks == 0) ticks =1 ; + if ( ticks == 0 ) ticks = 1; return ticks; } -TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) -{ - vTaskDelay( pdMS_TO_TICKS(msec) ); +TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { + vTaskDelay(pdMS_TO_TICKS(msec)); } //--------------------------------------------------------------------+ // Semaphore API //--------------------------------------------------------------------+ -TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) { #if configSUPPORT_STATIC_ALLOCATION return xSemaphoreCreateBinaryStatic(semdef); #else @@ -107,14 +114,10 @@ TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_ #endif } -TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) -{ - if ( !in_isr ) - { +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) { + if ( !in_isr ) { return xSemaphoreGive(sem_hdl) != 0; - } - else - { + } else { BaseType_t xHigherPriorityTaskWoken = pdFALSE; BaseType_t res = xSemaphoreGiveFromISR(sem_hdl, &xHigherPriorityTaskWoken); @@ -129,13 +132,11 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t se } } -TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) { return xSemaphoreTake(sem_hdl, _osal_ms2tick(msec)); } -TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) -{ +TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) { xQueueReset(sem_hdl); } @@ -143,8 +144,7 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t c // MUTEX API (priority inheritance) //--------------------------------------------------------------------+ -TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) { #if configSUPPORT_STATIC_ALLOCATION return xSemaphoreCreateMutexStatic(mdef); #else @@ -153,13 +153,11 @@ TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_de #endif } -TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) { return osal_semaphore_wait(mutex_hdl, msec); } -TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) { return xSemaphoreGive(mutex_hdl); } @@ -167,38 +165,35 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd // QUEUE API //--------------------------------------------------------------------+ -TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) { osal_queue_t q; - #if configSUPPORT_STATIC_ALLOCATION - q = xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq); - #else - q = xQueueCreate(qdef->depth, qdef->item_sz); - #endif - #if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0) - vQueueAddToRegistry(q, "tinyUSB"); - #endif + +#if configSUPPORT_STATIC_ALLOCATION + q = xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq); +#else + q = xQueueCreate(qdef->depth, qdef->item_sz); +#endif + +#if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0) + vQueueAddToRegistry(q, qdef->name); +#endif + return q; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) { return xQueueReceive(qhdl, data, _osal_ms2tick(msec)); } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) -{ - if ( !in_isr ) - { +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) { + if ( !in_isr ) { return xQueueSendToBack(qhdl, data, OSAL_TIMEOUT_WAIT_FOREVER) != 0; - } - else - { + } else { BaseType_t xHigherPriorityTaskWoken = pdFALSE; BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &xHigherPriorityTaskWoken); #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 - // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7 + // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7 (IDF v5) if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR(); #else portYIELD_FROM_ISR(xHigherPriorityTaskWoken); @@ -208,13 +203,12 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void } } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) { return uxQueueMessagesWaiting(qhdl) == 0; } #ifdef __cplusplus - } +} #endif #endif -- cgit v1.3.1 From a160da1f2b941741234f429417798b8df5c33294 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 3 Aug 2023 17:19:47 +0700 Subject: add lpc43 family --- .github/workflows/cmake_arm.yml | 2 +- examples/device/hid_boot_interface/src/main.c | 2 +- examples/typec/power_delivery/src/main.c | 2 +- hw/bsp/board_api.h | 6 +- hw/bsp/ea4357/board.mk | 48 ---- hw/bsp/ea4357/ea4357.c | 301 ---------------------- hw/bsp/ea4357/lpc4357.ld | 324 ------------------------ hw/bsp/ea4357/pca9532.c | 352 -------------------------- hw/bsp/ea4357/pca9532.h | 94 ------- hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h | 165 ++++++++++++ hw/bsp/lpc43/boards/ea4357/board.cmake | 16 ++ hw/bsp/lpc43/boards/ea4357/board.h | 40 +++ hw/bsp/lpc43/boards/ea4357/board.mk | 11 + hw/bsp/lpc43/boards/ea4357/lpc4357.ld | 324 ++++++++++++++++++++++++ hw/bsp/lpc43/boards/ea4357/pca9532.c | 352 ++++++++++++++++++++++++++ hw/bsp/lpc43/boards/ea4357/pca9532.h | 94 +++++++ hw/bsp/lpc43/family.c | 312 +++++++++++++++++++++++ hw/bsp/lpc43/family.cmake | 97 +++++++ hw/bsp/lpc43/family.mk | 34 +++ src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h | 9 + 20 files changed, 1462 insertions(+), 1123 deletions(-) delete mode 100644 hw/bsp/ea4357/board.mk delete mode 100644 hw/bsp/ea4357/ea4357.c delete mode 100644 hw/bsp/ea4357/lpc4357.ld delete mode 100644 hw/bsp/ea4357/pca9532.c delete mode 100644 hw/bsp/ea4357/pca9532.h create mode 100644 hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/lpc43/boards/ea4357/board.cmake create mode 100644 hw/bsp/lpc43/boards/ea4357/board.h create mode 100644 hw/bsp/lpc43/boards/ea4357/board.mk create mode 100644 hw/bsp/lpc43/boards/ea4357/lpc4357.ld create mode 100644 hw/bsp/lpc43/boards/ea4357/pca9532.c create mode 100644 hw/bsp/lpc43/boards/ea4357/pca9532.h create mode 100644 hw/bsp/lpc43/family.c create mode 100644 hw/bsp/lpc43/family.cmake create mode 100644 hw/bsp/lpc43/family.mk (limited to 'src') diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml index 276360650..5203337ec 100644 --- a/.github/workflows/cmake_arm.yml +++ b/.github/workflows/cmake_arm.yml @@ -35,7 +35,7 @@ jobs: # Alphabetical order - 'imxrt' - 'kinetis_kl' - - 'lpc18 lpc40' + - 'lpc18 lpc40 lpc43' - 'lpc55' - 'mcx' - 'ra' diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c index 1a155996a..18f301ff0 100644 --- a/examples/device/hid_boot_interface/src/main.c +++ b/examples/device/hid_boot_interface/src/main.c @@ -27,7 +27,7 @@ #include #include -#include "bsp/board.h" +#include "bsp/board_api.h" #include "tusb.h" #include "usb_descriptors.h" diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c index 08590aa74..489d01aa1 100644 --- a/examples/typec/power_delivery/src/main.c +++ b/examples/typec/power_delivery/src/main.c @@ -27,7 +27,7 @@ #include #include -#include "bsp/board.h" +#include "bsp/board_api.h" #include "tusb.h" //--------------------------------------------------------------------+ diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h index a7f3826d1..7249f618d 100644 --- a/hw/bsp/board_api.h +++ b/hw/bsp/board_api.h @@ -112,10 +112,14 @@ static inline void board_led_off(void) { static inline void board_delay(uint32_t ms) { uint32_t start_ms = board_millis(); while ( board_millis() - start_ms < ms ) { - #if CFG_TUD_ENABLED // take chance to run usb background + #if CFG_TUD_ENABLED tud_task(); #endif + + #if CFG_TUH_ENABLED + tuh_task(); + #endif } } diff --git a/hw/bsp/ea4357/board.mk b/hw/bsp/ea4357/board.mk deleted file mode 100644 index 6fd229166..000000000 --- a/hw/bsp/ea4357/board.mk +++ /dev/null @@ -1,48 +0,0 @@ -DEPS_SUBMODULES += hw/mcu/nxp/lpcopen - -CFLAGS += \ - -flto \ - -mthumb \ - -mabi=aapcs \ - -mcpu=cortex-m4 \ - -mfloat-abi=hard \ - -mfpu=fpv4-sp-d16 \ - -nostdlib \ - -DCORE_M4 \ - -D__USE_LPCOPEN \ - -DCFG_TUSB_MCU=OPT_MCU_LPC43XX - -# mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes -Wno-error=cast-qual - -MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx - -# All source paths should be relative to the top level. -LD_FILE = hw/bsp/$(BOARD)/lpc4357.ld - -SRC_C += \ - src/portable/chipidea/ci_hs/dcd_ci_hs.c \ - src/portable/chipidea/ci_hs/hcd_ci_hs.c \ - src/portable/ehci/ehci.c \ - $(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \ - $(MCU_DIR)/src/chip_18xx_43xx.c \ - $(MCU_DIR)/src/clock_18xx_43xx.c \ - $(MCU_DIR)/src/gpio_18xx_43xx.c \ - $(MCU_DIR)/src/sysinit_18xx_43xx.c \ - $(MCU_DIR)/src/i2c_18xx_43xx.c \ - $(MCU_DIR)/src/i2cm_18xx_43xx.c \ - $(MCU_DIR)/src/uart_18xx_43xx.c \ - $(MCU_DIR)/src/fpu_init.c - -INC += \ - $(TOP)/$(MCU_DIR)/inc \ - $(TOP)/$(MCU_DIR)/inc/config_43xx - -# For freeRTOS port source -FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F - -# For flash-jlink target -JLINK_DEVICE = LPC4357_M4 - -# flash using jlink -flash: flash-jlink diff --git a/hw/bsp/ea4357/ea4357.c b/hw/bsp/ea4357/ea4357.c deleted file mode 100644 index 06975b8cc..000000000 --- a/hw/bsp/ea4357/ea4357.c +++ /dev/null @@ -1,301 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "chip.h" -#include "../board_api.h" -#include "pca9532.h" - -#define UART_DEV LPC_USART0 -#define UART_PORT 0x0f -#define UART_PIN_TX 10 -#define UART_PIN_RX 11 - -// P9_1 joystick down -#define BUTTON_PORT 4 -#define BUTTON_PIN 13 - -//static const struct { -// uint8_t mux_port; -// uint8_t mux_pin; -// -// uint8_t gpio_port; -// uint8_t gpio_pin; -//}buttons[] = -//{ -// {0x0a, 3, 4, 10 }, // Joystick up -// {0x09, 1, 4, 13 }, // Joystick down -// {0x0a, 2, 4, 9 }, // Joystick left -// {0x09, 0, 4, 12 }, // Joystick right -// {0x0a, 1, 4, 8 }, // Joystick press -// {0x02, 7, 0, 7 }, // SW6 -//}; - -#ifdef BOARD_TUD_RHPORT - #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n) -#else - #define PORT_SUPPORT_DEVICE(_n) 0 -#endif - -#ifdef BOARD_TUH_RHPORT - #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n) -#else - #define PORT_SUPPORT_HOST(_n) 0 -#endif - -/*------------------------------------------------------------------*/ -/* BOARD API - *------------------------------------------------------------------*/ - -/* System configuration variables used by chip driver */ -const uint32_t OscRateIn = 12000000; -const uint32_t ExtRateIn = 0; - -static const PINMUX_GRP_T pinmuxing[] = -{ - // Button ( Joystick down ) - {0x9, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLUP)}, - - // UART - {UART_PORT, UART_PIN_TX, SCU_MODE_PULLDOWN | SCU_MODE_FUNC1}, - {UART_PORT, UART_PIN_RX, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1}, - - // USB -}; - -/* Pin clock mux values, re-used structure, value in first index is meaningless */ -static const PINMUX_GRP_T pinclockmuxing[] = -{ - {0, 0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)}, - {0, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)}, - {0, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)}, - {0, 3, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)}, -}; - -// Invoked by startup code -void SystemInit(void) -{ -#ifdef __USE_LPCOPEN - extern void (* const g_pfnVectors[])(void); - unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08; - *pSCB_VTOR = (unsigned int) g_pfnVectors; - -#if __FPU_USED == 1 - fpuInit(); -#endif -#endif // __USE_LPCOPEN - - /* Setup system level pin muxing */ - Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T)); - - /* Clock pins only, group field not used */ - for (int i = 0; i <(int) (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++) - { - Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc); - } - - Chip_SetupXtalClocking(); -} - -void board_init(void) -{ - SystemCoreClockUpdate(); - -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#endif - - Chip_GPIO_Init(LPC_GPIO_PORT); - - // LED via pca9532 I2C - Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE); - Chip_I2C_Init(I2C0); - Chip_I2C_SetClockRate(I2C0, 100000); - Chip_I2C_SetMasterEventHandler(I2C0, Chip_I2C_EventHandlerPolling); - - pca9532_init(); - - // Button - Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN); - - //------------- UART -------------// - Chip_UART_Init(UART_DEV); - Chip_UART_SetBaud(UART_DEV, CFG_BOARD_UART_BAUDRATE); - Chip_UART_ConfigData(UART_DEV, UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS); - Chip_UART_TXEnable(UART_DEV); - - //------------- USB -------------// - enum { - USBMODE_DEVICE = 2, - USBMODE_HOST = 3 - }; - - enum { - USBMODE_VBUS_LOW = 0, - USBMODE_VBUS_HIGH = 1 - }; - - /* From EA4357 user manual - * - * USB0 Device operation: - * - Insert jumpers in position 1-2 in JP17/JP18/JP19. - * - GPIO28 controls USB connect functionality - * - LED32 lights when the USB Device is connected. SJ4 has pads 1-2 shorted by default. - * - LED33 is controlled by GPIO27 and signals USB-up state. GPIO54 is used for VBUS - * sensing. - * - * USB0 Host operation: - * - insert jumpers in position 2-3 in JP17/JP18/JP19. - * - USB Host power is controlled via distribution switch U20 (found in schematic page 11). - * - Signal GPIO26 is active low and enables +5V on VBUS2. - * - LED35 light whenever +5V is present on VBUS2. - * - GPIO55 is connected to status feedback from the distribution switch. - * - GPIO54 is used for VBUS sensing. 15Kohm pull-down resistors are always active - * - * Note: - * - Insert jumpers in position 2-3 in JP17/JP18/JP19 - * - Insert jumpers in JP31 (OTG) - */ -#if PORT_SUPPORT_DEVICE(0) || PORT_SUPPORT_HOST(0) - Chip_USB0_Init(); -#endif - - /* From EA4357 user manual - * - * For USB1 Device: - * - a 1.5Kohm pull-up resistor is needed on the USB DP data signal. There are two methods to create this. - * JP15 is inserted and the pull-up resistor is always enabled. Alternatively, the pull-up resistor is activated - * inside the USB OTG chip (U31), and this has to be done via the I2C interface of GPIO52/GPIO53. In the latter case, - * JP15 shall not be inserted. - * - J19 is the connector to use when USB Device is used. Normally it should be a USB-B connector for - * creating a USB Device interface, but the mini-AB connector can also be used in this case. The status - * of VBUS can be read via U31. - * - JP16 shall not be inserted. - * - * For USB1 Host: - * - 15Kohm pull-down resistors are needed on the USB data signals. These are activated inside the USB OTG chip (U31), - * and this has to be done via the I2C interface of GPIO52/GPIO53. - * - J20 is the connector to use when USB Host is used. In order to provide +5V to the external USB - * device connected to this connector (J20), channel A of U20 must be enabled. It is enabled by default - * since SJ5 is normally connected between pin 1-2. - * - LED34 lights green when +5V is available on J20. - * - JP15 shall not be inserted. JP16 has no effect - */ -#if PORT_SUPPORT_DEVICE(1) || PORT_SUPPORT_HOST(1) - Chip_USB1_Init(); -#endif - - // USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board) - Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7); - - #if PORT_SUPPORT_DEVICE(0) - // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low. - Chip_SCU_PinMuxSet(9, 5, SCU_MODE_PULLDOWN | SCU_MODE_FUNC4); - Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 18); - #endif - - // USB1 Power: EA4357 channel A U20 is enabled by SJ5 connected to pad 1-2, no more action required - // TODO Remove R170, R171, solder a pair of 15K to USB1 D+/D- to test with USB1 Host -} - -//--------------------------------------------------------------------+ -// USB Interrupt Handler -//--------------------------------------------------------------------+ -void USB0_IRQHandler(void) -{ - #if PORT_SUPPORT_DEVICE(0) - tud_int_handler(0); - #endif - - #if PORT_SUPPORT_HOST(0) - tuh_int_handler(0); - #endif -} - -void USB1_IRQHandler(void) -{ - #if PORT_SUPPORT_DEVICE(1) - tud_int_handler(1); - #endif - - #if PORT_SUPPORT_HOST(1) - tuh_int_handler(1); - #endif -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - if (state) - { - pca9532_setLeds( LED1, 0 ); - }else - { - pca9532_setLeds( 0, LED1); - } -} - -uint32_t board_button_read(void) -{ - // active low - return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1; -} - -int board_uart_read(uint8_t* buf, int len) -{ - return Chip_UART_Read(UART_DEV, buf, len); -} - -int board_uart_write(void const * buf, int len) -{ - uint8_t const* buf8 = (uint8_t const*) buf; - for(int i=0; i MFlashB512 - - /* MAIN TEXT SECTION */ - .text : ALIGN(4) - { - FILL(0xff) - __vectors_start__ = ABSOLUTE(.) ; - KEEP(*(.isr_vector)) - /* Global Section Table */ - . = ALIGN(4) ; - __section_table_start = .; - __data_section_table = .; - LONG(LOADADDR(.data)); - LONG( ADDR(.data)); - LONG( SIZEOF(.data)); - LONG(LOADADDR(.data_RAM2)); - LONG( ADDR(.data_RAM2)); - LONG( SIZEOF(.data_RAM2)); - LONG(LOADADDR(.data_RAM3)); - LONG( ADDR(.data_RAM3)); - LONG( SIZEOF(.data_RAM3)); - LONG(LOADADDR(.data_RAM4)); - LONG( ADDR(.data_RAM4)); - LONG( SIZEOF(.data_RAM4)); - LONG(LOADADDR(.data_RAM5)); - LONG( ADDR(.data_RAM5)); - LONG( SIZEOF(.data_RAM5)); - __data_section_table_end = .; - __bss_section_table = .; - LONG( ADDR(.bss)); - LONG( SIZEOF(.bss)); - LONG( ADDR(.bss_RAM2)); - LONG( SIZEOF(.bss_RAM2)); - LONG( ADDR(.bss_RAM3)); - LONG( SIZEOF(.bss_RAM3)); - LONG( ADDR(.bss_RAM4)); - LONG( SIZEOF(.bss_RAM4)); - LONG( ADDR(.bss_RAM5)); - LONG( SIZEOF(.bss_RAM5)); - __bss_section_table_end = .; - __section_table_end = . ; - /* End of Global Section Table */ - - *(.after_vectors*) - - } > MFlashA512 - - .text : ALIGN(4) - { - *(.text*) - *(.rodata .rodata.* .constdata .constdata.*) - . = ALIGN(4); - } > MFlashA512 - /* - * for exception handling/unwind - some Newlib functions (in common - * with C++ and STDC++) use this. - */ - .ARM.extab : ALIGN(4) - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > MFlashA512 - - __exidx_start = .; - - .ARM.exidx : ALIGN(4) - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > MFlashA512 - __exidx_end = .; - - _etext = .; - - /* DATA section for RamLoc40 */ - - .data_RAM2 : ALIGN(4) - { - FILL(0xff) - PROVIDE(__start_data_RAM2 = .) ; - *(.ramfunc.$RAM2) - *(.ramfunc.$RamLoc40) - *(.data.$RAM2*) - *(.data.$RamLoc40*) - . = ALIGN(4) ; - PROVIDE(__end_data_RAM2 = .) ; - } > RamLoc40 AT>MFlashA512 - /* DATA section for RamAHB32 */ - - .data_RAM3 : ALIGN(4) - { - FILL(0xff) - PROVIDE(__start_data_RAM3 = .) ; - *(.ramfunc.$RAM3) - *(.ramfunc.$RamAHB32) - *(.data.$RAM3*) - *(.data.$RamAHB32*) - . = ALIGN(4) ; - PROVIDE(__end_data_RAM3 = .) ; - } > RamAHB32 AT>MFlashA512 - /* DATA section for RamAHB16 */ - - .data_RAM4 : ALIGN(4) - { - FILL(0xff) - PROVIDE(__start_data_RAM4 = .) ; - *(.ramfunc.$RAM4) - *(.ramfunc.$RamAHB16) - *(.data.$RAM4*) - *(.data.$RamAHB16*) - . = ALIGN(4) ; - PROVIDE(__end_data_RAM4 = .) ; - } > RamAHB16 AT>MFlashA512 - /* DATA section for RamAHB_ETB16 */ - - .data_RAM5 : ALIGN(4) - { - FILL(0xff) - PROVIDE(__start_data_RAM5 = .) ; - *(.ramfunc.$RAM5) - *(.ramfunc.$RamAHB_ETB16) - *(.data.$RAM5*) - *(.data.$RamAHB_ETB16*) - . = ALIGN(4) ; - PROVIDE(__end_data_RAM5 = .) ; - } > RamAHB_ETB16 AT>MFlashA512 - /* MAIN DATA SECTION */ - .uninit_RESERVED : ALIGN(4) - { - KEEP(*(.bss.$RESERVED*)) - . = ALIGN(4) ; - _end_uninit_RESERVED = .; - } > RamLoc32 - - /* Main DATA section (RamLoc32) */ - .data : ALIGN(4) - { - FILL(0xff) - _data = . ; - *(vtable) - *(.ramfunc*) - *(.data*) - . = ALIGN(4) ; - _edata = . ; - } > RamLoc32 AT>MFlashA512 - - /* BSS section for RamLoc40 */ - .bss_RAM2 : ALIGN(4) - { - PROVIDE(__start_bss_RAM2 = .) ; - *(.bss.$RAM2*) - *(.bss.$RamLoc40*) - . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ - PROVIDE(__end_bss_RAM2 = .) ; - } > RamLoc40 - - /* BSS section for RamAHB32 */ - .bss_RAM3 : ALIGN(4) - { - PROVIDE(__start_bss_RAM3 = .) ; - *(.bss.$RAM3*) - *(.bss.$RamAHB32*) - . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ - PROVIDE(__end_bss_RAM3 = .) ; - } > RamAHB32 - - /* BSS section for RamAHB16 */ - .bss_RAM4 : ALIGN(4) - { - PROVIDE(__start_bss_RAM4 = .) ; - *(.bss.$RAM4*) - *(.bss.$RamAHB16*) - . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ - PROVIDE(__end_bss_RAM4 = .) ; - } > RamAHB16 - - /* BSS section for RamAHB_ETB16 */ - .bss_RAM5 : ALIGN(4) - { - PROVIDE(__start_bss_RAM5 = .) ; - *(.bss.$RAM5*) - *(.bss.$RamAHB_ETB16*) - . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ - PROVIDE(__end_bss_RAM5 = .) ; - } > RamAHB_ETB16 - - /* MAIN BSS SECTION */ - .bss : ALIGN(4) - { - _bss = .; - *(.bss*) - *(COMMON) - . = ALIGN(4) ; - _ebss = .; - PROVIDE(end = .); - } > RamLoc32 - - /* NOINIT section for RamLoc40 */ - .noinit_RAM2 (NOLOAD) : ALIGN(4) - { - *(.noinit.$RAM2*) - *(.noinit.$RamLoc40*) - . = ALIGN(4) ; - } > RamLoc40 - - /* NOINIT section for RamAHB32 */ - .noinit_RAM3 (NOLOAD) : ALIGN(4) - { - *(.noinit.$RAM3*) - *(.noinit.$RamAHB32*) - . = ALIGN(4) ; - } > RamAHB32 - - /* NOINIT section for RamAHB16 */ - .noinit_RAM4 (NOLOAD) : ALIGN(4) - { - *(.noinit.$RAM4*) - *(.noinit.$RamAHB16*) - . = ALIGN(4) ; - } > RamAHB16 - - /* NOINIT section for RamAHB_ETB16 */ - .noinit_RAM5 (NOLOAD) : ALIGN(4) - { - *(.noinit.$RAM5*) - *(.noinit.$RamAHB_ETB16*) - . = ALIGN(4) ; - } > RamAHB_ETB16 - - /* DEFAULT NOINIT SECTION */ - .noinit (NOLOAD): ALIGN(4) - { - _noinit = .; - *(.noinit*) - . = ALIGN(4) ; - _end_noinit = .; - } > RamLoc32 - PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .); - PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0); - - /* ## Create checksum value (used in startup) ## */ - PROVIDE(__valid_user_code_checksum = 0 - - (_vStackTop - + (ResetISR + 1) - + (NMI_Handler + 1) - + (HardFault_Handler + 1) - + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */ - + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */ - + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */ - ) ); - - /* Provide basic symbols giving location and size of main text - * block, including initial values of RW data sections. Note that - * these will need extending to give a complete picture with - * complex images (e.g multiple Flash banks). - */ - _image_start = LOADADDR(.text); - _image_end = LOADADDR(.data) + SIZEOF(.data); - _image_size = _image_end - _image_start; -} diff --git a/hw/bsp/ea4357/pca9532.c b/hw/bsp/ea4357/pca9532.c deleted file mode 100644 index 150167cde..000000000 --- a/hw/bsp/ea4357/pca9532.c +++ /dev/null @@ -1,352 +0,0 @@ -/***************************************************************************** - * - * Copyright(C) 2011, Embedded Artists AB - * All rights reserved. - * - ****************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * Embedded Artists AB assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. Embedded Artists AB - * reserves the right to make changes in the software without - * notification. Embedded Artists AB also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. - *****************************************************************************/ - -/* - * NOTE: I2C must have been initialized before calling any functions in this - * file. - */ - -/****************************************************************************** - * Includes - *****************************************************************************/ - -//#include "board.h" -#include "chip.h" - -#include "pca9532.h" - -/****************************************************************************** - * Defines and typedefs - *****************************************************************************/ - -#define I2C_PORT (LPC_I2C0) - -#define LS_MODE_ON 0x01 -#define LS_MODE_BLINK0 0x02 -#define LS_MODE_BLINK1 0x03 - -/****************************************************************************** - * External global variables - *****************************************************************************/ - - -/****************************************************************************** - * Local variables - *****************************************************************************/ - -static uint16_t blink0Shadow = 0; -static uint16_t blink1Shadow = 0; -static uint16_t ledStateShadow = 0; - -/****************************************************************************** - * Local Functions - *****************************************************************************/ - -static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len) -{ - I2CM_XFER_T i2cData; - - i2cData.slaveAddr = addr; - i2cData.options = 0; - i2cData.status = 0; - i2cData.txBuff = buf; - i2cData.txSz = len; - i2cData.rxBuff = NULL; - i2cData.rxSz = 0; - - if (Chip_I2CM_XferBlocking(LPC_I2C0, &i2cData) == 0) { - return ERROR; - } - return SUCCESS; -} - -static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len) -{ - I2CM_XFER_T i2cData; - - i2cData.slaveAddr = addr; - i2cData.options = 0; - i2cData.status = 0; - i2cData.txBuff = NULL; - i2cData.txSz = 0; - i2cData.rxBuff = buf; - i2cData.rxSz = len; - - if (Chip_I2CM_XferBlocking(LPC_I2C0, &i2cData) == 0) { - return ERROR; - } - return SUCCESS; -} - -static void setLsStates(uint16_t states, uint8_t* ls, uint8_t mode) -{ -#define IS_LED_SET(bit, x) ( ( ((x) & (bit)) != 0 ) ? 1 : 0 ) - - int i = 0; - - for (i = 0; i < 4; i++) { - - ls[i] |= ( (IS_LED_SET(0x0001, states)*mode << 0) - | (IS_LED_SET(0x0002, states)*mode << 2) - | (IS_LED_SET(0x0004, states)*mode << 4) - | (IS_LED_SET(0x0008, states)*mode << 6) ); - - states >>= 4; - } -} - -static void setLeds(void) -{ - uint8_t buf[5]; - uint8_t ls[4] = {0,0,0,0}; - uint16_t states = ledStateShadow; - - /* LEDs in On/Off state */ - setLsStates(states, ls, LS_MODE_ON); - - /* set the LEDs that should blink */ - setLsStates(blink0Shadow, ls, LS_MODE_BLINK0); - setLsStates(blink1Shadow, ls, LS_MODE_BLINK1); - - - buf[0] = PCA9532_LS0 | PCA9532_AUTO_INC; - buf[1] = ls[0]; - buf[2] = ls[1]; - buf[3] = ls[2]; - buf[4] = ls[3]; - I2CWrite(PCA9532_I2C_ADDR, buf, 5); -} - -/****************************************************************************** - * Public Functions - *****************************************************************************/ - -/****************************************************************************** - * - * Description: - * Initialize the PCA9532 Device - * - *****************************************************************************/ -void pca9532_init (void) -{ - /* nothing to initialize */ -} - -/****************************************************************************** - * - * Description: - * Get the LED states - * - * Params: - * [in] shadow - TRUE if the states should be retrieved from the shadow - * variables. The shadow variable are updated when any - * of setLeds, setBlink0Leds and/or setBlink1Leds are - * called. - * - * FALSE if the state should be retrieved from the PCA9532 - * device. A blinkin LED may be reported as on or off - * depending on the state when calling the function. - * - * Returns: - * A mask where a 1 indicates that a LED is on (or blinking). - * - *****************************************************************************/ -uint16_t pca9532_getLedState (uint32_t shadow) -{ - uint8_t buf[2]; - uint16_t ret = 0; - - if (shadow) { - /* a blink LED is reported as on*/ - ret = (ledStateShadow | blink0Shadow | blink1Shadow); - } - else { - - /* - * A blinking LED may be reported as on or off depending on - * its state when reading the Input register. - */ - - buf[0] = PCA9532_INPUT0; - I2CWrite(PCA9532_I2C_ADDR, buf, 1); - - I2CRead(PCA9532_I2C_ADDR, buf, 1); - ret = buf[0]; - - - buf[0] = PCA9532_INPUT1; - I2CWrite(PCA9532_I2C_ADDR, buf, 1); - - I2CRead(PCA9532_I2C_ADDR, buf, 1); - ret |= (buf[0] << 8); - - - /* invert since LEDs are active low */ - ret = ((~ret) & 0xFFFF); - } - - return (ret & ~PCA9532_NOT_USED); -} - - -/****************************************************************************** - * - * Description: - * Set LED states (on or off). - * - * Params: - * [in] ledOnMask - The LEDs that should be turned on. This mask has - * priority over ledOffMask - * [in] ledOffMask - The LEDs that should be turned off. - * - *****************************************************************************/ -void pca9532_setLeds (uint16_t ledOnMask, uint16_t ledOffMask) -{ - /* turn off leds */ - ledStateShadow &= (~(ledOffMask) & 0xffff); - - /* ledOnMask has priority over ledOffMask */ - ledStateShadow |= ledOnMask; - - /* turn off blinking */ - blink0Shadow &= (~(ledOffMask) & 0xffff); - blink1Shadow &= (~(ledOffMask) & 0xffff); - - setLeds(); -} - -/****************************************************************************** - * - * Description: - * Set the blink period for PWM0. Valid values are 0 - 255 where 0 - * means 152 Hz and 255 means 0.59 Hz. A value of 151 means 1 Hz. - * - * Params: - * [in] period - the period for pwm0 - * - *****************************************************************************/ -void pca9532_setBlink0Period(uint8_t period) -{ - uint8_t buf[2]; - - buf[0] = PCA9532_PSC0; - buf[1] = period; - I2CWrite(PCA9532_I2C_ADDR, buf, 2); -} - -/****************************************************************************** - * - * Description: - * Set the duty cycle for PWM0. Valid values are 0 - 100. 25 means the LED - * is on 25% of the period. - * - * Params: - * [in] duty - duty cycle - * - *****************************************************************************/ -void pca9532_setBlink0Duty(uint8_t duty) -{ - uint8_t buf[2]; - uint32_t tmp = duty; - if (tmp > 100) { - tmp = 100; - } - - tmp = (256 * tmp)/100; - - buf[0] = PCA9532_PWM0; - buf[1] = tmp; - I2CWrite(PCA9532_I2C_ADDR, buf, 2); -} - -/****************************************************************************** - * - * Description: - * Set the LEDs that should blink with rate and duty cycle from PWM0. - * Blinking is turned off with pca9532_setLeds. - * - * Params: - * [in] ledMask - LEDs that should blink. - * - *****************************************************************************/ -void pca9532_setBlink0Leds(uint16_t ledMask) -{ - blink0Shadow |= ledMask; - setLeds(); -} - -/****************************************************************************** - * - * Description: - * Set the blink period for PWM1. Valid values are 0 - 255 where 0 - * means 152 Hz and 255 means 0.59 Hz. A value of 151 means 1 Hz. - * - * Params: - * [in] period - The period for PWM1 - * - *****************************************************************************/ -void pca9532_setBlink1Period(uint8_t period) -{ - uint8_t buf[2]; - - buf[0] = PCA9532_PSC1; - buf[1] = period; - I2CWrite(PCA9532_I2C_ADDR, buf, 2); -} - -/****************************************************************************** - * - * Description: - * Set the duty cycle for PWM1. Valid values are 0 - 100. 25 means the LED - * is on 25% of the period. - * - * Params: - * [in] duty - duty cycle. - * - *****************************************************************************/ -void pca9532_setBlink1Duty(uint8_t duty) -{ - uint8_t buf[2]; - - uint32_t tmp = duty; - if (tmp > 100) { - tmp = 100; - } - - tmp = (256 * tmp)/100; - - buf[0] = PCA9532_PWM1; - buf[1] = tmp; - I2CWrite(PCA9532_I2C_ADDR, buf, 2); -} - -/****************************************************************************** - * - * Description: - * Set the LEDs that should blink with rate and duty cycle from PWM1. - * Blinking is turned off with pca9532_setLeds. - * - * Params: - * [in] ledMask - LEDs that should blink. - * - *****************************************************************************/ -void pca9532_setBlink1Leds(uint16_t ledMask) -{ - blink1Shadow |= ledMask; - setLeds(); -} diff --git a/hw/bsp/ea4357/pca9532.h b/hw/bsp/ea4357/pca9532.h deleted file mode 100644 index f21c1ff09..000000000 --- a/hw/bsp/ea4357/pca9532.h +++ /dev/null @@ -1,94 +0,0 @@ -/***************************************************************************** - * - * Copyright(C) 2011, Embedded Artists AB - * All rights reserved. - * - ****************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * Embedded Artists AB assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. Embedded Artists AB - * reserves the right to make changes in the software without - * notification. Embedded Artists AB also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. - *****************************************************************************/ -#ifndef __PCA9532C_H -#define __PCA9532C_H - - -#define PCA9532_I2C_ADDR (0xC0>>1) - -#define PCA9532_INPUT0 0x00 -#define PCA9532_INPUT1 0x01 -#define PCA9532_PSC0 0x02 -#define PCA9532_PWM0 0x03 -#define PCA9532_PSC1 0x04 -#define PCA9532_PWM1 0x05 -#define PCA9532_LS0 0x06 -#define PCA9532_LS1 0x07 -#define PCA9532_LS2 0x08 -#define PCA9532_LS3 0x09 - -#define PCA9532_AUTO_INC 0x10 - - -/* - * The Keys on the base board are mapped to LED0 -> LED3 on - * the PCA9532. - */ - -#define KEY1 0x0001 -#define KEY2 0x0002 -#define KEY3 0x0004 -#define KEY4 0x0008 - -#define KEY_MASK 0x000F - -/* - * MMC Card Detect and MMC Write Protect are mapped to LED4 - * and LED5 on the PCA9532. Please note that WP is active low. - */ - -#define MMC_CD 0x0010 -#define MMC_WP 0x0020 - -#define MMC_MASK 0x30 - -/* NOTE: LED6 and LED7 on PCA9532 are not connected to anything */ -#define PCA9532_NOT_USED 0xC0 - -/* - * Below are the LED constants to use when enabling/disabling a LED. - * The LED names are the names printed on the base board and not - * the names from the PCA9532 device. base_LED1 -> LED8 on PCA9532, - * base_LED2 -> LED9, and so on. - */ - -#define LED1 0x0100 -#define LED2 0x0200 -#define LED3 0x0400 -#define LED4 0x0800 -#define LED5 0x1000 -#define LED6 0x2000 -#define LED7 0x4000 -#define LED8 0x8000 - -#define LED_MASK 0xFF00 - -void pca9532_init (void); -uint16_t pca9532_getLedState (uint32_t shadow); -void pca9532_setLeds (uint16_t ledOnMask, uint16_t ledOffMask); -void pca9532_setBlink0Period(uint8_t period); -void pca9532_setBlink0Duty(uint8_t duty); -void pca9532_setBlink0Leds(uint16_t ledMask); -void pca9532_setBlink1Period(uint8_t period); -void pca9532_setBlink1Duty(uint8_t duty); -void pca9532_setBlink1Leds(uint16_t ledMask); - -#endif /* end __PCA9532C_H */ -/**************************************************************************** -** End Of File -*****************************************************************************/ diff --git a/hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..6f80413c0 --- /dev/null +++ b/hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,165 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "chip.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* Define to trap errors during development. */ +// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) + #define configASSERT(_exp) \ + do {\ + if ( !(_exp) ) { \ + volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ + if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \ + taskDISABLE_INTERRUPTS(); \ + __asm("BKPT #0\n"); \ + }\ + }\ + } while(0) +#else + #define configASSERT( x ) +#endif + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS 3 + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< MFlashB512 + + /* MAIN TEXT SECTION */ + .text : ALIGN(4) + { + FILL(0xff) + __vectors_start__ = ABSOLUTE(.) ; + KEEP(*(.isr_vector)) + /* Global Section Table */ + . = ALIGN(4) ; + __section_table_start = .; + __data_section_table = .; + LONG(LOADADDR(.data)); + LONG( ADDR(.data)); + LONG( SIZEOF(.data)); + LONG(LOADADDR(.data_RAM2)); + LONG( ADDR(.data_RAM2)); + LONG( SIZEOF(.data_RAM2)); + LONG(LOADADDR(.data_RAM3)); + LONG( ADDR(.data_RAM3)); + LONG( SIZEOF(.data_RAM3)); + LONG(LOADADDR(.data_RAM4)); + LONG( ADDR(.data_RAM4)); + LONG( SIZEOF(.data_RAM4)); + LONG(LOADADDR(.data_RAM5)); + LONG( ADDR(.data_RAM5)); + LONG( SIZEOF(.data_RAM5)); + __data_section_table_end = .; + __bss_section_table = .; + LONG( ADDR(.bss)); + LONG( SIZEOF(.bss)); + LONG( ADDR(.bss_RAM2)); + LONG( SIZEOF(.bss_RAM2)); + LONG( ADDR(.bss_RAM3)); + LONG( SIZEOF(.bss_RAM3)); + LONG( ADDR(.bss_RAM4)); + LONG( SIZEOF(.bss_RAM4)); + LONG( ADDR(.bss_RAM5)); + LONG( SIZEOF(.bss_RAM5)); + __bss_section_table_end = .; + __section_table_end = . ; + /* End of Global Section Table */ + + *(.after_vectors*) + + } > MFlashA512 + + .text : ALIGN(4) + { + *(.text*) + *(.rodata .rodata.* .constdata .constdata.*) + . = ALIGN(4); + } > MFlashA512 + /* + * for exception handling/unwind - some Newlib functions (in common + * with C++ and STDC++) use this. + */ + .ARM.extab : ALIGN(4) + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > MFlashA512 + + __exidx_start = .; + + .ARM.exidx : ALIGN(4) + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > MFlashA512 + __exidx_end = .; + + _etext = .; + + /* DATA section for RamLoc40 */ + + .data_RAM2 : ALIGN(4) + { + FILL(0xff) + PROVIDE(__start_data_RAM2 = .) ; + *(.ramfunc.$RAM2) + *(.ramfunc.$RamLoc40) + *(.data.$RAM2*) + *(.data.$RamLoc40*) + . = ALIGN(4) ; + PROVIDE(__end_data_RAM2 = .) ; + } > RamLoc40 AT>MFlashA512 + /* DATA section for RamAHB32 */ + + .data_RAM3 : ALIGN(4) + { + FILL(0xff) + PROVIDE(__start_data_RAM3 = .) ; + *(.ramfunc.$RAM3) + *(.ramfunc.$RamAHB32) + *(.data.$RAM3*) + *(.data.$RamAHB32*) + . = ALIGN(4) ; + PROVIDE(__end_data_RAM3 = .) ; + } > RamAHB32 AT>MFlashA512 + /* DATA section for RamAHB16 */ + + .data_RAM4 : ALIGN(4) + { + FILL(0xff) + PROVIDE(__start_data_RAM4 = .) ; + *(.ramfunc.$RAM4) + *(.ramfunc.$RamAHB16) + *(.data.$RAM4*) + *(.data.$RamAHB16*) + . = ALIGN(4) ; + PROVIDE(__end_data_RAM4 = .) ; + } > RamAHB16 AT>MFlashA512 + /* DATA section for RamAHB_ETB16 */ + + .data_RAM5 : ALIGN(4) + { + FILL(0xff) + PROVIDE(__start_data_RAM5 = .) ; + *(.ramfunc.$RAM5) + *(.ramfunc.$RamAHB_ETB16) + *(.data.$RAM5*) + *(.data.$RamAHB_ETB16*) + . = ALIGN(4) ; + PROVIDE(__end_data_RAM5 = .) ; + } > RamAHB_ETB16 AT>MFlashA512 + /* MAIN DATA SECTION */ + .uninit_RESERVED : ALIGN(4) + { + KEEP(*(.bss.$RESERVED*)) + . = ALIGN(4) ; + _end_uninit_RESERVED = .; + } > RamLoc32 + + /* Main DATA section (RamLoc32) */ + .data : ALIGN(4) + { + FILL(0xff) + _data = . ; + *(vtable) + *(.ramfunc*) + *(.data*) + . = ALIGN(4) ; + _edata = . ; + } > RamLoc32 AT>MFlashA512 + + /* BSS section for RamLoc40 */ + .bss_RAM2 : ALIGN(4) + { + PROVIDE(__start_bss_RAM2 = .) ; + *(.bss.$RAM2*) + *(.bss.$RamLoc40*) + . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ + PROVIDE(__end_bss_RAM2 = .) ; + } > RamLoc40 + + /* BSS section for RamAHB32 */ + .bss_RAM3 : ALIGN(4) + { + PROVIDE(__start_bss_RAM3 = .) ; + *(.bss.$RAM3*) + *(.bss.$RamAHB32*) + . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ + PROVIDE(__end_bss_RAM3 = .) ; + } > RamAHB32 + + /* BSS section for RamAHB16 */ + .bss_RAM4 : ALIGN(4) + { + PROVIDE(__start_bss_RAM4 = .) ; + *(.bss.$RAM4*) + *(.bss.$RamAHB16*) + . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ + PROVIDE(__end_bss_RAM4 = .) ; + } > RamAHB16 + + /* BSS section for RamAHB_ETB16 */ + .bss_RAM5 : ALIGN(4) + { + PROVIDE(__start_bss_RAM5 = .) ; + *(.bss.$RAM5*) + *(.bss.$RamAHB_ETB16*) + . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */ + PROVIDE(__end_bss_RAM5 = .) ; + } > RamAHB_ETB16 + + /* MAIN BSS SECTION */ + .bss : ALIGN(4) + { + _bss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4) ; + _ebss = .; + PROVIDE(end = .); + } > RamLoc32 + + /* NOINIT section for RamLoc40 */ + .noinit_RAM2 (NOLOAD) : ALIGN(4) + { + *(.noinit.$RAM2*) + *(.noinit.$RamLoc40*) + . = ALIGN(4) ; + } > RamLoc40 + + /* NOINIT section for RamAHB32 */ + .noinit_RAM3 (NOLOAD) : ALIGN(4) + { + *(.noinit.$RAM3*) + *(.noinit.$RamAHB32*) + . = ALIGN(4) ; + } > RamAHB32 + + /* NOINIT section for RamAHB16 */ + .noinit_RAM4 (NOLOAD) : ALIGN(4) + { + *(.noinit.$RAM4*) + *(.noinit.$RamAHB16*) + . = ALIGN(4) ; + } > RamAHB16 + + /* NOINIT section for RamAHB_ETB16 */ + .noinit_RAM5 (NOLOAD) : ALIGN(4) + { + *(.noinit.$RAM5*) + *(.noinit.$RamAHB_ETB16*) + . = ALIGN(4) ; + } > RamAHB_ETB16 + + /* DEFAULT NOINIT SECTION */ + .noinit (NOLOAD): ALIGN(4) + { + _noinit = .; + *(.noinit*) + . = ALIGN(4) ; + _end_noinit = .; + } > RamLoc32 + PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .); + PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0); + + /* ## Create checksum value (used in startup) ## */ + PROVIDE(__valid_user_code_checksum = 0 - + (_vStackTop + + (ResetISR + 1) + + (NMI_Handler + 1) + + (HardFault_Handler + 1) + + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */ + + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */ + + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */ + ) ); + + /* Provide basic symbols giving location and size of main text + * block, including initial values of RW data sections. Note that + * these will need extending to give a complete picture with + * complex images (e.g multiple Flash banks). + */ + _image_start = LOADADDR(.text); + _image_end = LOADADDR(.data) + SIZEOF(.data); + _image_size = _image_end - _image_start; +} diff --git a/hw/bsp/lpc43/boards/ea4357/pca9532.c b/hw/bsp/lpc43/boards/ea4357/pca9532.c new file mode 100644 index 000000000..150167cde --- /dev/null +++ b/hw/bsp/lpc43/boards/ea4357/pca9532.c @@ -0,0 +1,352 @@ +/***************************************************************************** + * + * Copyright(C) 2011, Embedded Artists AB + * All rights reserved. + * + ****************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * Embedded Artists AB assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. Embedded Artists AB + * reserves the right to make changes in the software without + * notification. Embedded Artists AB also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + *****************************************************************************/ + +/* + * NOTE: I2C must have been initialized before calling any functions in this + * file. + */ + +/****************************************************************************** + * Includes + *****************************************************************************/ + +//#include "board.h" +#include "chip.h" + +#include "pca9532.h" + +/****************************************************************************** + * Defines and typedefs + *****************************************************************************/ + +#define I2C_PORT (LPC_I2C0) + +#define LS_MODE_ON 0x01 +#define LS_MODE_BLINK0 0x02 +#define LS_MODE_BLINK1 0x03 + +/****************************************************************************** + * External global variables + *****************************************************************************/ + + +/****************************************************************************** + * Local variables + *****************************************************************************/ + +static uint16_t blink0Shadow = 0; +static uint16_t blink1Shadow = 0; +static uint16_t ledStateShadow = 0; + +/****************************************************************************** + * Local Functions + *****************************************************************************/ + +static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len) +{ + I2CM_XFER_T i2cData; + + i2cData.slaveAddr = addr; + i2cData.options = 0; + i2cData.status = 0; + i2cData.txBuff = buf; + i2cData.txSz = len; + i2cData.rxBuff = NULL; + i2cData.rxSz = 0; + + if (Chip_I2CM_XferBlocking(LPC_I2C0, &i2cData) == 0) { + return ERROR; + } + return SUCCESS; +} + +static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len) +{ + I2CM_XFER_T i2cData; + + i2cData.slaveAddr = addr; + i2cData.options = 0; + i2cData.status = 0; + i2cData.txBuff = NULL; + i2cData.txSz = 0; + i2cData.rxBuff = buf; + i2cData.rxSz = len; + + if (Chip_I2CM_XferBlocking(LPC_I2C0, &i2cData) == 0) { + return ERROR; + } + return SUCCESS; +} + +static void setLsStates(uint16_t states, uint8_t* ls, uint8_t mode) +{ +#define IS_LED_SET(bit, x) ( ( ((x) & (bit)) != 0 ) ? 1 : 0 ) + + int i = 0; + + for (i = 0; i < 4; i++) { + + ls[i] |= ( (IS_LED_SET(0x0001, states)*mode << 0) + | (IS_LED_SET(0x0002, states)*mode << 2) + | (IS_LED_SET(0x0004, states)*mode << 4) + | (IS_LED_SET(0x0008, states)*mode << 6) ); + + states >>= 4; + } +} + +static void setLeds(void) +{ + uint8_t buf[5]; + uint8_t ls[4] = {0,0,0,0}; + uint16_t states = ledStateShadow; + + /* LEDs in On/Off state */ + setLsStates(states, ls, LS_MODE_ON); + + /* set the LEDs that should blink */ + setLsStates(blink0Shadow, ls, LS_MODE_BLINK0); + setLsStates(blink1Shadow, ls, LS_MODE_BLINK1); + + + buf[0] = PCA9532_LS0 | PCA9532_AUTO_INC; + buf[1] = ls[0]; + buf[2] = ls[1]; + buf[3] = ls[2]; + buf[4] = ls[3]; + I2CWrite(PCA9532_I2C_ADDR, buf, 5); +} + +/****************************************************************************** + * Public Functions + *****************************************************************************/ + +/****************************************************************************** + * + * Description: + * Initialize the PCA9532 Device + * + *****************************************************************************/ +void pca9532_init (void) +{ + /* nothing to initialize */ +} + +/****************************************************************************** + * + * Description: + * Get the LED states + * + * Params: + * [in] shadow - TRUE if the states should be retrieved from the shadow + * variables. The shadow variable are updated when any + * of setLeds, setBlink0Leds and/or setBlink1Leds are + * called. + * + * FALSE if the state should be retrieved from the PCA9532 + * device. A blinkin LED may be reported as on or off + * depending on the state when calling the function. + * + * Returns: + * A mask where a 1 indicates that a LED is on (or blinking). + * + *****************************************************************************/ +uint16_t pca9532_getLedState (uint32_t shadow) +{ + uint8_t buf[2]; + uint16_t ret = 0; + + if (shadow) { + /* a blink LED is reported as on*/ + ret = (ledStateShadow | blink0Shadow | blink1Shadow); + } + else { + + /* + * A blinking LED may be reported as on or off depending on + * its state when reading the Input register. + */ + + buf[0] = PCA9532_INPUT0; + I2CWrite(PCA9532_I2C_ADDR, buf, 1); + + I2CRead(PCA9532_I2C_ADDR, buf, 1); + ret = buf[0]; + + + buf[0] = PCA9532_INPUT1; + I2CWrite(PCA9532_I2C_ADDR, buf, 1); + + I2CRead(PCA9532_I2C_ADDR, buf, 1); + ret |= (buf[0] << 8); + + + /* invert since LEDs are active low */ + ret = ((~ret) & 0xFFFF); + } + + return (ret & ~PCA9532_NOT_USED); +} + + +/****************************************************************************** + * + * Description: + * Set LED states (on or off). + * + * Params: + * [in] ledOnMask - The LEDs that should be turned on. This mask has + * priority over ledOffMask + * [in] ledOffMask - The LEDs that should be turned off. + * + *****************************************************************************/ +void pca9532_setLeds (uint16_t ledOnMask, uint16_t ledOffMask) +{ + /* turn off leds */ + ledStateShadow &= (~(ledOffMask) & 0xffff); + + /* ledOnMask has priority over ledOffMask */ + ledStateShadow |= ledOnMask; + + /* turn off blinking */ + blink0Shadow &= (~(ledOffMask) & 0xffff); + blink1Shadow &= (~(ledOffMask) & 0xffff); + + setLeds(); +} + +/****************************************************************************** + * + * Description: + * Set the blink period for PWM0. Valid values are 0 - 255 where 0 + * means 152 Hz and 255 means 0.59 Hz. A value of 151 means 1 Hz. + * + * Params: + * [in] period - the period for pwm0 + * + *****************************************************************************/ +void pca9532_setBlink0Period(uint8_t period) +{ + uint8_t buf[2]; + + buf[0] = PCA9532_PSC0; + buf[1] = period; + I2CWrite(PCA9532_I2C_ADDR, buf, 2); +} + +/****************************************************************************** + * + * Description: + * Set the duty cycle for PWM0. Valid values are 0 - 100. 25 means the LED + * is on 25% of the period. + * + * Params: + * [in] duty - duty cycle + * + *****************************************************************************/ +void pca9532_setBlink0Duty(uint8_t duty) +{ + uint8_t buf[2]; + uint32_t tmp = duty; + if (tmp > 100) { + tmp = 100; + } + + tmp = (256 * tmp)/100; + + buf[0] = PCA9532_PWM0; + buf[1] = tmp; + I2CWrite(PCA9532_I2C_ADDR, buf, 2); +} + +/****************************************************************************** + * + * Description: + * Set the LEDs that should blink with rate and duty cycle from PWM0. + * Blinking is turned off with pca9532_setLeds. + * + * Params: + * [in] ledMask - LEDs that should blink. + * + *****************************************************************************/ +void pca9532_setBlink0Leds(uint16_t ledMask) +{ + blink0Shadow |= ledMask; + setLeds(); +} + +/****************************************************************************** + * + * Description: + * Set the blink period for PWM1. Valid values are 0 - 255 where 0 + * means 152 Hz and 255 means 0.59 Hz. A value of 151 means 1 Hz. + * + * Params: + * [in] period - The period for PWM1 + * + *****************************************************************************/ +void pca9532_setBlink1Period(uint8_t period) +{ + uint8_t buf[2]; + + buf[0] = PCA9532_PSC1; + buf[1] = period; + I2CWrite(PCA9532_I2C_ADDR, buf, 2); +} + +/****************************************************************************** + * + * Description: + * Set the duty cycle for PWM1. Valid values are 0 - 100. 25 means the LED + * is on 25% of the period. + * + * Params: + * [in] duty - duty cycle. + * + *****************************************************************************/ +void pca9532_setBlink1Duty(uint8_t duty) +{ + uint8_t buf[2]; + + uint32_t tmp = duty; + if (tmp > 100) { + tmp = 100; + } + + tmp = (256 * tmp)/100; + + buf[0] = PCA9532_PWM1; + buf[1] = tmp; + I2CWrite(PCA9532_I2C_ADDR, buf, 2); +} + +/****************************************************************************** + * + * Description: + * Set the LEDs that should blink with rate and duty cycle from PWM1. + * Blinking is turned off with pca9532_setLeds. + * + * Params: + * [in] ledMask - LEDs that should blink. + * + *****************************************************************************/ +void pca9532_setBlink1Leds(uint16_t ledMask) +{ + blink1Shadow |= ledMask; + setLeds(); +} diff --git a/hw/bsp/lpc43/boards/ea4357/pca9532.h b/hw/bsp/lpc43/boards/ea4357/pca9532.h new file mode 100644 index 000000000..f21c1ff09 --- /dev/null +++ b/hw/bsp/lpc43/boards/ea4357/pca9532.h @@ -0,0 +1,94 @@ +/***************************************************************************** + * + * Copyright(C) 2011, Embedded Artists AB + * All rights reserved. + * + ****************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * Embedded Artists AB assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. Embedded Artists AB + * reserves the right to make changes in the software without + * notification. Embedded Artists AB also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + *****************************************************************************/ +#ifndef __PCA9532C_H +#define __PCA9532C_H + + +#define PCA9532_I2C_ADDR (0xC0>>1) + +#define PCA9532_INPUT0 0x00 +#define PCA9532_INPUT1 0x01 +#define PCA9532_PSC0 0x02 +#define PCA9532_PWM0 0x03 +#define PCA9532_PSC1 0x04 +#define PCA9532_PWM1 0x05 +#define PCA9532_LS0 0x06 +#define PCA9532_LS1 0x07 +#define PCA9532_LS2 0x08 +#define PCA9532_LS3 0x09 + +#define PCA9532_AUTO_INC 0x10 + + +/* + * The Keys on the base board are mapped to LED0 -> LED3 on + * the PCA9532. + */ + +#define KEY1 0x0001 +#define KEY2 0x0002 +#define KEY3 0x0004 +#define KEY4 0x0008 + +#define KEY_MASK 0x000F + +/* + * MMC Card Detect and MMC Write Protect are mapped to LED4 + * and LED5 on the PCA9532. Please note that WP is active low. + */ + +#define MMC_CD 0x0010 +#define MMC_WP 0x0020 + +#define MMC_MASK 0x30 + +/* NOTE: LED6 and LED7 on PCA9532 are not connected to anything */ +#define PCA9532_NOT_USED 0xC0 + +/* + * Below are the LED constants to use when enabling/disabling a LED. + * The LED names are the names printed on the base board and not + * the names from the PCA9532 device. base_LED1 -> LED8 on PCA9532, + * base_LED2 -> LED9, and so on. + */ + +#define LED1 0x0100 +#define LED2 0x0200 +#define LED3 0x0400 +#define LED4 0x0800 +#define LED5 0x1000 +#define LED6 0x2000 +#define LED7 0x4000 +#define LED8 0x8000 + +#define LED_MASK 0xFF00 + +void pca9532_init (void); +uint16_t pca9532_getLedState (uint32_t shadow); +void pca9532_setLeds (uint16_t ledOnMask, uint16_t ledOffMask); +void pca9532_setBlink0Period(uint8_t period); +void pca9532_setBlink0Duty(uint8_t duty); +void pca9532_setBlink0Leds(uint16_t ledMask); +void pca9532_setBlink1Period(uint8_t period); +void pca9532_setBlink1Duty(uint8_t duty); +void pca9532_setBlink1Leds(uint16_t ledMask); + +#endif /* end __PCA9532C_H */ +/**************************************************************************** +** End Of File +*****************************************************************************/ diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c new file mode 100644 index 000000000..ba3191d5f --- /dev/null +++ b/hw/bsp/lpc43/family.c @@ -0,0 +1,312 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +// Suppress warning caused by mcu driver +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#include "chip.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "bsp/board_api.h" +#include "board.h" + +#define UART_DEV LPC_USART0 +#define UART_PORT 0x0f +#define UART_PIN_TX 10 +#define UART_PIN_RX 11 + +// P9_1 joystick down +#define BUTTON_PORT 4 +#define BUTTON_PIN 13 + +//static const struct { +// uint8_t mux_port; +// uint8_t mux_pin; +// +// uint8_t gpio_port; +// uint8_t gpio_pin; +//}buttons[] = +//{ +// {0x0a, 3, 4, 10 }, // Joystick up +// {0x09, 1, 4, 13 }, // Joystick down +// {0x0a, 2, 4, 9 }, // Joystick left +// {0x09, 0, 4, 12 }, // Joystick right +// {0x0a, 1, 4, 8 }, // Joystick press +// {0x02, 7, 0, 7 }, // SW6 +//}; + +#ifdef BOARD_TUD_RHPORT + #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n) +#else + #define PORT_SUPPORT_DEVICE(_n) 0 +#endif + +#ifdef BOARD_TUH_RHPORT + #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n) +#else + #define PORT_SUPPORT_HOST(_n) 0 +#endif + +/*------------------------------------------------------------------*/ +/* BOARD API + *------------------------------------------------------------------*/ + +/* System configuration variables used by chip driver */ +const uint32_t OscRateIn = 12000000; +const uint32_t ExtRateIn = 0; + +static const PINMUX_GRP_T pinmuxing[] = +{ + // Button ( Joystick down ) + {0x9, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLUP)}, + + // UART + {UART_PORT, UART_PIN_TX, SCU_MODE_PULLDOWN | SCU_MODE_FUNC1}, + {UART_PORT, UART_PIN_RX, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1}, + + // USB +}; + +/* Pin clock mux values, re-used structure, value in first index is meaningless */ +static const PINMUX_GRP_T pinclockmuxing[] = +{ + {0, 0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)}, + {0, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)}, + {0, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)}, + {0, 3, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)}, +}; + +// Invoked by startup code +void SystemInit(void) +{ +#ifdef __USE_LPCOPEN + extern void (* const g_pfnVectors[])(void); + unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08; + *pSCB_VTOR = (unsigned int) g_pfnVectors; + +#if __FPU_USED == 1 + fpuInit(); +#endif +#endif // __USE_LPCOPEN + + /* Setup system level pin muxing */ + Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T)); + + /* Clock pins only, group field not used */ + for (int i = 0; i <(int) (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++) + { + Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc); + } + + Chip_SetupXtalClocking(); +} + +void board_init(void) +{ + SystemCoreClockUpdate(); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + + Chip_GPIO_Init(LPC_GPIO_PORT); + + // LED via pca9532 I2C + Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE); + Chip_I2C_Init(I2C0); + Chip_I2C_SetClockRate(I2C0, 100000); + Chip_I2C_SetMasterEventHandler(I2C0, Chip_I2C_EventHandlerPolling); + + pca9532_init(); + + // Button + Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN); + + //------------- UART -------------// + Chip_UART_Init(UART_DEV); + Chip_UART_SetBaud(UART_DEV, CFG_BOARD_UART_BAUDRATE); + Chip_UART_ConfigData(UART_DEV, UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS); + Chip_UART_TXEnable(UART_DEV); + + //------------- USB -------------// + enum { + USBMODE_DEVICE = 2, + USBMODE_HOST = 3 + }; + + enum { + USBMODE_VBUS_LOW = 0, + USBMODE_VBUS_HIGH = 1 + }; + + /* From EA4357 user manual + * + * USB0 Device operation: + * - Insert jumpers in position 1-2 in JP17/JP18/JP19. + * - GPIO28 controls USB connect functionality + * - LED32 lights when the USB Device is connected. SJ4 has pads 1-2 shorted by default. + * - LED33 is controlled by GPIO27 and signals USB-up state. GPIO54 is used for VBUS + * sensing. + * + * USB0 Host operation: + * - insert jumpers in position 2-3 in JP17/JP18/JP19. + * - USB Host power is controlled via distribution switch U20 (found in schematic page 11). + * - Signal GPIO26 is active low and enables +5V on VBUS2. + * - LED35 light whenever +5V is present on VBUS2. + * - GPIO55 is connected to status feedback from the distribution switch. + * - GPIO54 is used for VBUS sensing. 15Kohm pull-down resistors are always active + * + * Note: + * - Insert jumpers in position 2-3 in JP17/JP18/JP19 + * - Insert jumpers in JP31 (OTG) + */ +#if PORT_SUPPORT_DEVICE(0) || PORT_SUPPORT_HOST(0) + Chip_USB0_Init(); +#endif + + /* From EA4357 user manual + * + * For USB1 Device: + * - a 1.5Kohm pull-up resistor is needed on the USB DP data signal. There are two methods to create this. + * JP15 is inserted and the pull-up resistor is always enabled. Alternatively, the pull-up resistor is activated + * inside the USB OTG chip (U31), and this has to be done via the I2C interface of GPIO52/GPIO53. In the latter case, + * JP15 shall not be inserted. + * - J19 is the connector to use when USB Device is used. Normally it should be a USB-B connector for + * creating a USB Device interface, but the mini-AB connector can also be used in this case. The status + * of VBUS can be read via U31. + * - JP16 shall not be inserted. + * + * For USB1 Host: + * - 15Kohm pull-down resistors are needed on the USB data signals. These are activated inside the USB OTG chip (U31), + * and this has to be done via the I2C interface of GPIO52/GPIO53. + * - J20 is the connector to use when USB Host is used. In order to provide +5V to the external USB + * device connected to this connector (J20), channel A of U20 must be enabled. It is enabled by default + * since SJ5 is normally connected between pin 1-2. + * - LED34 lights green when +5V is available on J20. + * - JP15 shall not be inserted. JP16 has no effect + */ +#if PORT_SUPPORT_DEVICE(1) || PORT_SUPPORT_HOST(1) + Chip_USB1_Init(); +#endif + + // USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board) + Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7); + + #if PORT_SUPPORT_DEVICE(0) + // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low. + Chip_SCU_PinMuxSet(9, 5, SCU_MODE_PULLDOWN | SCU_MODE_FUNC4); + Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 18); + #endif + + // USB1 Power: EA4357 channel A U20 is enabled by SJ5 connected to pad 1-2, no more action required + // TODO Remove R170, R171, solder a pair of 15K to USB1 D+/D- to test with USB1 Host +} + +//--------------------------------------------------------------------+ +// USB Interrupt Handler +//--------------------------------------------------------------------+ +void USB0_IRQHandler(void) +{ + #if PORT_SUPPORT_DEVICE(0) + tud_int_handler(0); + #endif + + #if PORT_SUPPORT_HOST(0) + tuh_int_handler(0); + #endif +} + +void USB1_IRQHandler(void) +{ + #if PORT_SUPPORT_DEVICE(1) + tud_int_handler(1); + #endif + + #if PORT_SUPPORT_HOST(1) + tuh_int_handler(1); + #endif +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + if (state) + { + pca9532_setLeds( LED1, 0 ); + }else + { + pca9532_setLeds( 0, LED1); + } +} + +uint32_t board_button_read(void) +{ + // active low + return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1; +} + +int board_uart_read(uint8_t* buf, int len) +{ + return Chip_UART_Read(UART_DEV, buf, len); +} + +int board_uart_write(void const * buf, int len) +{ + uint8_t const* buf8 = (uint8_t const*) buf; + for(int i=0; i Date: Tue, 18 Jul 2023 14:23:41 +0200 Subject: clean(ra_hcd): fix typos in the hcd library --- src/portable/renesas/rusb2/hcd_rusb2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 55bf6de4d..790cd6b32 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -265,7 +265,7 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num) pipe->buf = (uint8_t*)buf + len; } if (len < mps) { - rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk; + rusb->D0FIFOCTR = RUSB2_D0FIFOCTR_BCLR_Msk; } rusb->D0FIFOSEL = 0; while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ @@ -297,7 +297,7 @@ static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num) pipe->buf = (uint8_t*)buf + len; } if (len < mps) { - rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->D0FIFOCTR = RUSB2_D0FIFOCTR_BVAL_Msk; } rusb->D0FIFOSEL = 0; while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */ @@ -367,7 +367,7 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, } else { /* ZLP */ rusb->D0FIFOSEL = num; pipe_wait_for_ready(rusb, num); - rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk; + rusb->D0FIFOCTR = RUSB2_D0FIFOCTR_BVAL_Msk; rusb->D0FIFOSEL = 0; while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */ } -- cgit v1.3.1 From 1f95a417f271e627ec981be3d211eed8c37cb052 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 7 Aug 2023 18:22:28 +0700 Subject: Add tuh_rhport_is_active() and tuh_rhport_reset_bus() - also improve ehci bus reset - seperate bus reset delay and contact debouncing delay in enumeration --- src/host/hcd.h | 5 +- src/host/hub.c | 2 +- src/host/usbh.c | 118 +++++++++++++++++--------------- src/host/usbh.h | 39 ++++++----- src/portable/chipidea/ci_hs/hcd_ci_hs.c | 43 ++++++------ src/portable/ehci/ehci.c | 24 +++++-- 6 files changed, 128 insertions(+), 103 deletions(-) (limited to 'src') diff --git a/src/host/hcd.h b/src/host/hcd.h index d77dd6e2f..9bcc1c6df 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -149,10 +149,11 @@ uint32_t hcd_frame_number(uint8_t rhport); // Get the current connect status of roothub port bool hcd_port_connect_status(uint8_t rhport); -// Reset USB bus on the port +// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete. +// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence. void hcd_port_reset(uint8_t rhport); -// TODO implement later +// Complete bus reset sequence, may be required by some controllers void hcd_port_reset_end(uint8_t rhport); // Get port link speed diff --git a/src/host/hub.c b/src/host/hub.c index 16dd534d2..ec30eb96a 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -330,7 +330,7 @@ static void connection_port_reset_complete (tuh_xfer_t* xfer); bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { (void) xferred_bytes; // TODO can be more than 1 for hub with lots of ports (void) ep_addr; - TU_ASSERT(result == XFER_RESULT_SUCCESS); + TU_VERIFY(result == XFER_RESULT_SUCCESS); hub_interface_t* p_hub = get_itf(dev_addr); diff --git a/src/host/usbh.c b/src/host/usbh.c index 49f8c78f1..cc7e38b45 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -181,9 +181,6 @@ static usbh_class_driver_t const usbh_class_drivers[] = }; enum { USBH_CLASS_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) }; - -enum { RESET_DELAY = 500 }; // 200 USB specs say only 50ms but many devices require much longer - enum { CONFIG_NUM = 1 }; // default to use configuration 1 @@ -251,40 +248,27 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t #if CFG_TUSB_OS == OPT_OS_NONE // TODO rework time-related function later -TU_ATTR_WEAK void osal_task_delay(uint32_t msec) -{ +// weak and overridable +TU_ATTR_WEAK void osal_task_delay(uint32_t msec) { const uint32_t start = hcd_frame_number(_usbh_controller); while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {} } #endif //--------------------------------------------------------------------+ -// PUBLIC API (Parameter Verification is required) +// Device API //--------------------------------------------------------------------+ -bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) -{ - if (hcd_configure) - { - return hcd_configure(rhport, cfg_id, cfg_param); - }else - { - return false; - } -} - -bool tuh_mounted(uint8_t dev_addr) -{ - usbh_device_t* dev = get_device(dev_addr); +bool tuh_mounted(uint8_t dev_addr) { + usbh_device_t *dev = get_device(dev_addr); TU_VERIFY(dev); return dev->configured; } -bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid) -{ +bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t *vid, uint16_t *pid) { *vid = *pid = 0; - usbh_device_t const* dev = get_device(dev_addr); + usbh_device_t const *dev = get_device(dev_addr); TU_VERIFY(dev && dev->addressed && dev->vid != 0); *vid = dev->vid; @@ -293,26 +277,48 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid) return true; } -tusb_speed_t tuh_speed_get (uint8_t dev_addr) -{ - usbh_device_t* dev = get_device(dev_addr); +tusb_speed_t tuh_speed_get(uint8_t dev_addr) { + usbh_device_t *dev = get_device(dev_addr); return (tusb_speed_t) (dev ? get_device(dev_addr)->speed : _dev0.speed); } -static void clear_device(usbh_device_t* dev) -{ +bool tuh_rhport_is_active(uint8_t rhport) { + return _usbh_controller == rhport; +} + +bool tuh_rhport_reset_bus(uint8_t rhport, bool active) { + TU_VERIFY(tuh_rhport_is_active(rhport)); + if ( active ) { + hcd_port_reset(rhport); + } else { + hcd_port_reset_end(rhport); + } + return true; +} + +//--------------------------------------------------------------------+ +// PUBLIC API (Parameter Verification is required) +//--------------------------------------------------------------------+ + +bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void *cfg_param) { + if ( hcd_configure ) { + return hcd_configure(rhport, cfg_id, cfg_param); + } else { + return false; + } +} + +static void clear_device(usbh_device_t* dev) { tu_memclr(dev, sizeof(usbh_device_t)); memset(dev->itf2drv, TUSB_INDEX_INVALID_8, sizeof(dev->itf2drv)); // invalid mapping memset(dev->ep2drv , TUSB_INDEX_INVALID_8, sizeof(dev->ep2drv )); // invalid mapping } -bool tuh_inited(void) -{ +bool tuh_inited(void) { return _usbh_controller != TUSB_INDEX_INVALID_8; } -bool tuh_init(uint8_t controller_id) -{ +bool tuh_init(uint8_t controller_id) { // skip if already initialized if ( tuh_inited() ) return true; @@ -359,8 +365,7 @@ bool tuh_init(uint8_t controller_id) return true; } -bool tuh_task_event_ready(void) -{ +bool tuh_task_event_ready(void) { // Skip if stack is not initialized if ( !tuh_inited() ) return false; @@ -385,8 +390,7 @@ bool tuh_task_event_ready(void) } @endcode */ -void tuh_task_ext(uint32_t timeout_ms, bool in_isr) -{ +void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { (void) in_isr; // not implemented yet // Skip if stack is not initialized @@ -403,8 +407,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) case HCD_EVENT_DEVICE_ATTACH: // due to the shared _usbh_ctrl_buf, we must complete enumerating // one device before enumerating another one. - if ( _dev0.enumerating ) - { + if ( _dev0.enumerating ) { TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport); bool is_empty = osal_queue_empty(_usbh_q); @@ -414,8 +417,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) // Exit if this is the only event in the queue, otherwise we may loop forever return; } - }else - { + }else { TU_LOG_USBH("[%u:] USBH DEVICE ATTACH\r\n", event.rhport); _dev0.enumerating = 1; enum_new_device(&event); @@ -428,8 +430,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) #if CFG_TUH_HUB // TODO remove - if ( event.connection.hub_addr != 0) - { + if ( event.connection.hub_addr != 0) { // done with hub, waiting for next data on status pipe (void) hub_edpt_status_xfer( event.connection.hub_addr ); } @@ -1230,6 +1231,12 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu // one device before enumerating another one. //--------------------------------------------------------------------+ +enum { + ENUM_RESET_DELAY = 50, // USB specs: 10 to 50ms + ENUM_CONTACT_DEBOUNCING_DELAY = 450, // when plug/unplug a device, physical connection can be bouncing and may + // generate a series of attach/detach event. This delay wait for stable connection +}; + enum { ENUM_IDLE, ENUM_RESET_1, // 1st reset when attached @@ -1311,7 +1318,7 @@ static void process_enumeration(tuh_xfer_t* xfer) break; case ENUM_HUB_GET_STATUS_2: - osal_task_delay(RESET_DELAY); + osal_task_delay(ENUM_RESET_DELAY); TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, process_enumeration, ENUM_HUB_CLEAR_RESET_2), ); break; @@ -1468,12 +1475,14 @@ static bool enum_new_device(hcd_event_t* event) if (_dev0.hub_addr == 0) { // connected/disconnected directly with roothub - // wait until device is stable TODO non blocking hcd_port_reset(_dev0.rhport); - osal_task_delay(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since - // sof of controller may not running while resetting + osal_task_delay(ENUM_RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since + // sof of controller may not running while resetting hcd_port_reset_end( _dev0.rhport); + // wait until device connection is stable TODO non blocking + osal_task_delay(ENUM_CONTACT_DEBOUNCING_DELAY); + // device unplugged while delaying if ( !hcd_port_connect_status(_dev0.rhport) ) { enum_full_complete(); @@ -1489,6 +1498,7 @@ static bool enum_new_device(hcd_event_t* event) xfer.result = XFER_RESULT_SUCCESS; xfer.user_data = ENUM_ADDR0_DEVICE_DESC; + process_enumeration(&xfer); } @@ -1496,8 +1506,8 @@ static bool enum_new_device(hcd_event_t* event) else { // connected/disconnected via external hub - // wait until device is stable - osal_task_delay(RESET_DELAY); + // wait until device connection is stable TODO non blocking + osal_task_delay(ENUM_CONTACT_DEBOUNCING_DELAY); // ENUM_HUB_GET_STATUS //TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status0_complete, 0) ); @@ -1508,23 +1518,19 @@ static bool enum_new_device(hcd_event_t* event) return true; } -static uint8_t get_new_address(bool is_hub) -{ +static uint8_t get_new_address(bool is_hub) { uint8_t start; uint8_t end; - if ( is_hub ) - { + if ( is_hub ) { start = CFG_TUH_DEVICE_MAX; end = start + CFG_TUH_HUB; - }else - { + }else { start = 0; end = start + CFG_TUH_DEVICE_MAX; } - for (uint8_t idx = start; idx < end; idx++) - { + for (uint8_t idx = start; idx < end; idx++) { if (!_usbh_devices[idx].connected) return (idx+1); } diff --git a/src/host/usbh.h b/src/host/usbh.h index 0d56f40c9..684e8240e 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -47,8 +47,7 @@ typedef void (*tuh_xfer_cb_t)(tuh_xfer_t* xfer); // it is advised to initialize it using member name // Note2: not all field is available/meaningful in callback, // some info is not saved by usbh to save SRAM -struct tuh_xfer_s -{ +struct tuh_xfer_s { uint8_t daddr; uint8_t ep_addr; uint8_t TU_RESERVED; // reserved @@ -56,8 +55,7 @@ struct tuh_xfer_s uint32_t actual_len; // excluding setup packet - union - { + union { tusb_control_request_t const* setup; // setup packet pointer if control transfer uint32_t buflen; // expected length if not control transfer (not available in callback) }; @@ -70,15 +68,13 @@ struct tuh_xfer_s }; // Subject to change -typedef struct -{ +typedef struct { uint8_t daddr; tusb_desc_interface_t desc; } tuh_itf_info_t; // ConfigID for tuh_config() -enum -{ +enum { TUH_CFGID_RPI_PIO_USB_CONFIGURATION = OPT_MCU_RP2040 << 8 // cfg_param: pio_usb_configuration_t }; @@ -105,12 +101,12 @@ TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr); // Should be called before tuh_init() // - cfg_id : configure ID (TBD) // - cfg_param: configure data, structure depends on the ID -bool tuh_configure(uint8_t controller_id, uint32_t cfg_id, const void* cfg_param); +bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param); // Init host stack -bool tuh_init(uint8_t controller_id); +bool tuh_init(uint8_t rhport); -// Check if host stack is already initialized +// Check if host stack is already initialized with any roothub ports bool tuh_inited(void); // Task function should be called in main/rtos loop, extended version of tuh_task() @@ -120,8 +116,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr); // Task function should be called in main/rtos loop TU_ATTR_ALWAYS_INLINE static inline -void tuh_task(void) -{ +void tuh_task(void) { tuh_task_ext(UINT32_MAX, false); } @@ -135,8 +130,20 @@ extern void hcd_int_handler(uint8_t rhport); // Interrupt handler, name alias to HCD #define tuh_int_handler hcd_int_handler +// Check if roothub port is initialized and active as a host +bool tuh_rhport_is_active(uint8_t rhport); + +// Assert/de-assert Bus Reset signal to roothub port. USB specs: it should last 10-50ms +bool tuh_rhport_reset_bus(uint8_t rhport, bool active); + +//--------------------------------------------------------------------+ +// Device API +//--------------------------------------------------------------------+ + +// Get VID/PID of device bool tuh_vid_pid_get(uint8_t daddr, uint16_t* vid, uint16_t* pid); +// Get speed of device tusb_speed_t tuh_speed_get(uint8_t daddr); // Check if device is connected and configured @@ -144,8 +151,7 @@ bool tuh_mounted(uint8_t daddr); // Check if device is suspended TU_ATTR_ALWAYS_INLINE static inline -bool tuh_suspended(uint8_t daddr) -{ +bool tuh_suspended(uint8_t daddr) { // TODO implement suspend & resume on host (void) daddr; return false; @@ -153,8 +159,7 @@ bool tuh_suspended(uint8_t daddr) // Check if device is ready to communicate with TU_ATTR_ALWAYS_INLINE static inline -bool tuh_ready(uint8_t daddr) -{ +bool tuh_ready(uint8_t daddr) { return tuh_mounted(daddr) && !tuh_suspended(daddr); } diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index 6ee91e18e..462cbd301 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -39,24 +39,27 @@ #include "ci_hs_type.h" #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX - #include "ci_hs_imxrt.h" - bool hcd_dcache_clean(void const* addr, uint32_t data_size) { - return imxrt_dcache_clean(addr, data_size); - } +#include "ci_hs_imxrt.h" - bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) { - return imxrt_dcache_invalidate(addr, data_size); - } +bool hcd_dcache_clean(void const* addr, uint32_t data_size) { + return imxrt_dcache_clean(addr, data_size); +} + +bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) { + return imxrt_dcache_invalidate(addr, data_size); +} - bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { - return imxrt_dcache_clean_invalidate(addr, data_size); - } +bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { + return imxrt_dcache_clean_invalidate(addr, data_size); +} #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) - #include "ci_hs_lpc18_43.h" + +#include "ci_hs_lpc18_43.h" + #else - #error "Unsupported MCUs" +#error "Unsupported MCUs" #endif //--------------------------------------------------------------------+ @@ -67,25 +70,25 @@ // Controller API //--------------------------------------------------------------------+ -bool hcd_init(uint8_t rhport) -{ - ci_hs_regs_t* hcd_reg = CI_HS_REG(rhport); +bool hcd_init(uint8_t rhport) { + ci_hs_regs_t *hcd_reg = CI_HS_REG(rhport); // Reset controller hcd_reg->USBCMD |= USBCMD_RESET; - while( hcd_reg->USBCMD & USBCMD_RESET ) {} + while ( hcd_reg->USBCMD & USBCMD_RESET ) {} // Set mode to device, must be set immediately after reset #if CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX // LPC18XX/43XX need to set VBUS Power Select to HIGH // RHPORT1 is fullspeed only (need external PHY for Highspeed) hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT; - if (rhport == 1) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED; + if ( rhport == 1 ) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED; #else hcd_reg->USBMODE = USBMODE_CM_HOST; #endif // FIXME force full speed, still have issue with Highspeed enumeration + // probably due to physical connection bouncing when plug/unplug // 1. Have issue when plug/unplug devices, maybe the port is not reset properly // 2. Also does not seems to detect disconnection hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED; @@ -93,13 +96,11 @@ bool hcd_init(uint8_t rhport) return ehci_init(rhport, (uint32_t) &hcd_reg->CAPLENGTH, (uint32_t) &hcd_reg->USBCMD); } -void hcd_int_enable(uint8_t rhport) -{ +void hcd_int_enable(uint8_t rhport) { CI_HCD_INT_ENABLE(rhport); } -void hcd_int_disable(uint8_t rhport) -{ +void hcd_int_disable(uint8_t rhport) { CI_HCD_INT_DISABLE(rhport); } diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 9be24c888..79811985c 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -188,6 +188,11 @@ void hcd_port_reset(uint8_t rhport) ehci_registers_t* regs = ehci_data.regs; + // skip if already in reset + if (regs->portsc_bm.port_reset) { + return; + } + // mask out Write-1-to-Clear bits uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_W1C; @@ -202,16 +207,18 @@ void hcd_port_reset(uint8_t rhport) void hcd_port_reset_end(uint8_t rhport) { (void) rhport; - -#if 0 // TODO check if this is necessary ehci_registers_t* regs = ehci_data.regs; + // skip if reset is already complete + if (!regs->portsc_bm.port_reset) { + return; + } + // mask out all change bits since they are Write 1 to clear - uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL; - portsc &= ~(EHCI_PORTSC_MASK_PORT_RESET); + uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_W1C; + portsc &= ~EHCI_PORTSC_MASK_PORT_RESET; regs->portsc = portsc; -#endif } bool hcd_port_connect_status(uint8_t rhport) @@ -426,6 +433,11 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet hcd_dcache_clean(setup_packet, 8); + // Control endpoint never be stalled. Skip reset Data Toggle since it is fixed per stage + if (qhd->qtd_overlay.halted) { + qhd->qtd_overlay.halted = false; + } + // attach TD to QHD -> start transferring qhd_attach_qtd(qhd, td); @@ -662,7 +674,7 @@ void hcd_int_handler(uint8_t rhport) if (int_status & EHCI_INT_MASK_PORT_CHANGE) { // Including: Force port resume, over-current change, enable/disable change and connect status change. uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_W1C; - print_portsc(regs); + // print_portsc(regs); if (regs->portsc_bm.connect_status_change) { port_connect_status_change_isr(rhport); -- cgit v1.3.1 From 18646179d0c784660ca261fb675e21787451655b Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 7 Aug 2023 18:23:16 +0700 Subject: fix host msc get maxlun not using aligned section memory --- src/class/msc/msc_host.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c index a65208d69..90a58d3d0 100644 --- a/src/class/msc/msc_host.c +++ b/src/class/msc/msc_host.c @@ -421,8 +421,7 @@ bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de return true; } -bool msch_set_config(uint8_t dev_addr, uint8_t itf_num) -{ +bool msch_set_config(uint8_t dev_addr, uint8_t itf_num) { msch_interface_t* p_msc = get_itf(dev_addr); TU_ASSERT(p_msc->itf_num == itf_num); @@ -430,10 +429,8 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num) //------------- Get Max Lun -------------// TU_LOG_DRV("MSC Get Max Lun\r\n"); - tusb_control_request_t const request = - { - .bmRequestType_bit = - { + tusb_control_request_t const request = { + .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_IN @@ -444,12 +441,11 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num) .wLength = 1 }; - tuh_xfer_t xfer = - { + tuh_xfer_t xfer = { .daddr = dev_addr, .ep_addr = 0, .setup = &request, - .buffer = &p_msc->max_lun, + .buffer = _msch_buffer, .complete_cb = config_get_maxlun_complete, .user_data = 0 }; @@ -467,6 +463,8 @@ static void config_get_maxlun_complete (tuh_xfer_t* xfer) p_msc->max_lun = (XFER_RESULT_SUCCESS == xfer->result) ? _msch_buffer[0] : 0; p_msc->max_lun++; // MAX LUN is minus 1 by specs + TU_LOG_DRV(" Max LUN = %u\r\n", p_msc->max_lun); + // TODO multiple LUN support TU_LOG_DRV("SCSI Test Unit Ready\r\n"); uint8_t const lun = 0; -- cgit v1.3.1 From 4938971aad2f2a6adb71f4d8ce76e1d4b664092d Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 7 Aug 2023 19:09:36 +0700 Subject: code format --- hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug | 5 +- src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 73 +++++++++--------------- 2 files changed, 29 insertions(+), 49 deletions(-) (limited to 'src') diff --git a/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug b/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug index 6e298c62d..f94960f09 100644 --- a/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug +++ b/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug @@ -10,7 +10,7 @@ */ void OnProjectLoad (void) { Project.AddSvdFile ("Cortex-M3.svd"); - Project.AddSvdFile ("./LPC18xx.svd"); + Project.AddSvdFile ("../../../../../../../cmsis-svd/data/NXP/LPC18xx.svd"); Project.SetDevice ("LPC1857"); Project.SetHostIF ("USB", ""); @@ -20,7 +20,8 @@ void OnProjectLoad (void) { Project.SetTraceSource ("Trace Pins"); Project.SetTracePortWidth (4); - File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-mcb1800/cdc_msc.elf"); + //File.Open ("../../../../../../examples/cmake-build-mcb1800/device/cdc_msc/cdc_msc.elf"); + File.Open ("../../../../../../examples/cmake-build-mcb1800/host/cdc_msc_hid/cdc_msc_hid.elf"); } /********************************************************************* * diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c index adb83e97d..93bc1bf43 100644 --- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c @@ -48,16 +48,14 @@ static pio_usb_configuration_t pio_host_cfg = PIO_USB_DEFAULT_CONFIG; //--------------------------------------------------------------------+ // HCD API //--------------------------------------------------------------------+ -bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) -{ +bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void *cfg_param) { (void) rhport; TU_VERIFY(cfg_id == TUH_CFGID_RPI_PIO_USB_CONFIGURATION); memcpy(&pio_host_cfg, cfg_param, sizeof(pio_usb_configuration_t)); return true; } -bool hcd_init(uint8_t rhport) -{ +bool hcd_init(uint8_t rhport) { (void) rhport; // To run USB SOF interrupt in core1, call this init in core1 @@ -66,20 +64,17 @@ bool hcd_init(uint8_t rhport) return true; } -void hcd_port_reset(uint8_t rhport) -{ +void hcd_port_reset(uint8_t rhport) { uint8_t const pio_rhport = RHPORT_PIO(rhport); pio_usb_host_port_reset_start(pio_rhport); } -void hcd_port_reset_end(uint8_t rhport) -{ +void hcd_port_reset_end(uint8_t rhport) { uint8_t const pio_rhport = RHPORT_PIO(rhport); pio_usb_host_port_reset_end(pio_rhport); } -bool hcd_port_connect_status(uint8_t rhport) -{ +bool hcd_port_connect_status(uint8_t rhport) { uint8_t const pio_rhport = RHPORT_PIO(rhport); root_port_t *root = PIO_USB_ROOT_PORT(pio_rhport); @@ -88,33 +83,28 @@ bool hcd_port_connect_status(uint8_t rhport) return line_state != PORT_PIN_SE0; } -tusb_speed_t hcd_port_speed_get(uint8_t rhport) -{ +tusb_speed_t hcd_port_speed_get(uint8_t rhport) { // TODO determine link speed uint8_t const pio_rhport = RHPORT_PIO(rhport); return PIO_USB_ROOT_PORT(pio_rhport)->is_fullspeed ? TUSB_SPEED_FULL : TUSB_SPEED_LOW; } // Close all opened endpoint belong to this device -void hcd_device_close(uint8_t rhport, uint8_t dev_addr) -{ +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { uint8_t const pio_rhport = RHPORT_PIO(rhport); pio_usb_host_close_device(pio_rhport, dev_addr); } -uint32_t hcd_frame_number(uint8_t rhport) -{ +uint32_t hcd_frame_number(uint8_t rhport) { (void) rhport; return pio_usb_host_get_frame_number(); } -void hcd_int_enable(uint8_t rhport) -{ +void hcd_int_enable(uint8_t rhport) { (void) rhport; } -void hcd_int_disable(uint8_t rhport) -{ +void hcd_int_disable(uint8_t rhport) { (void) rhport; } @@ -122,18 +112,16 @@ void hcd_int_disable(uint8_t rhport) // Endpoint API //--------------------------------------------------------------------+ -bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep) -{ +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *desc_ep) { hcd_devtree_info_t dev_tree; hcd_devtree_get_info(dev_addr, &dev_tree); bool const need_pre = (dev_tree.hub_addr && dev_tree.speed == TUSB_SPEED_LOW); uint8_t const pio_rhport = RHPORT_PIO(rhport); - return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const*) desc_ep, need_pre); + return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const *) desc_ep, need_pre); } -bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) -{ +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) { uint8_t const pio_rhport = RHPORT_PIO(rhport); return pio_usb_host_endpoint_transfer(pio_rhport, dev_addr, ep_addr, buffer, buflen); } @@ -143,8 +131,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { return pio_usb_host_endpoint_abort_transfer(pio_rhport, dev_addr, ep_addr); } -bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) -{ +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { uint8_t const pio_rhport = RHPORT_PIO(rhport); return pio_usb_host_send_setup(pio_rhport, dev_addr, setup_packet); } @@ -171,18 +158,16 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { return true; } -static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* rport, xfer_result_t result, volatile uint32_t* ep_reg) -{ +static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t *rport, xfer_result_t result, + volatile uint32_t *ep_reg) { (void) rport; const uint32_t ep_all = *ep_reg; - for(uint8_t ep_idx = 0; ep_idx < PIO_USB_EP_POOL_CNT; ep_idx++) - { + for ( uint8_t ep_idx = 0; ep_idx < PIO_USB_EP_POOL_CNT; ep_idx++ ) { uint32_t const mask = (1u << ep_idx); - if (ep_all & mask) - { - endpoint_t* ep = PIO_USB_ENDPOINT(ep_idx); + if ( ep_all & mask ) { + endpoint_t * ep = PIO_USB_ENDPOINT(ep_idx); hcd_event_xfer_complete(ep->dev_addr, ep->ep_num, ep->actual_len, result, true); } } @@ -192,34 +177,28 @@ static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* rpor } // IRQ Handler -void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id) -{ +void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id) { uint8_t const tu_rhport = root_id + 1; - root_port_t* rport = PIO_USB_ROOT_PORT(root_id); + root_port_t *rport = PIO_USB_ROOT_PORT(root_id); uint32_t const ints = rport->ints; - if ( ints & PIO_USB_INTS_CONNECT_BITS ) - { + if ( ints & PIO_USB_INTS_CONNECT_BITS ) { hcd_event_device_attach(tu_rhport, true); } - if ( ints & PIO_USB_INTS_DISCONNECT_BITS ) - { + if ( ints & PIO_USB_INTS_DISCONNECT_BITS ) { hcd_event_device_remove(tu_rhport, true); } - if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS ) - { + if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS ) { handle_endpoint_irq(rport, XFER_RESULT_SUCCESS, &rport->ep_complete); } - if ( ints & PIO_USB_INTS_ENDPOINT_STALLED_BITS ) - { + if ( ints & PIO_USB_INTS_ENDPOINT_STALLED_BITS ) { handle_endpoint_irq(rport, XFER_RESULT_STALLED, &rport->ep_stalled); } - if ( ints & PIO_USB_INTS_ENDPOINT_ERROR_BITS ) - { + if ( ints & PIO_USB_INTS_ENDPOINT_ERROR_BITS ) { handle_endpoint_irq(rport, XFER_RESULT_FAILED, &rport->ep_error); } -- cgit v1.3.1 From c959e65edde0b07b80c3e12f177afd938abbdcd6 Mon Sep 17 00:00:00 2001 From: Rocky04 Date: Mon, 7 Aug 2023 21:16:41 +0200 Subject: Fixing wrong callback placement --- src/device/usbd.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index b4ca63c9c..2daf91d77 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -711,7 +711,16 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const } // switch to new configuration if not zero - if ( cfg_num ) TU_ASSERT( process_set_config(rhport, cfg_num) ); + if ( cfg_num ) + { + TU_ASSERT( process_set_config(rhport, cfg_num) ); + + if ( tud_mount_cb ) tud_mount_cb(); + } + else + { + if ( tud_umount_cb ) tud_umount_cb(); + } } _usbd_dev.cfg_num = cfg_num; @@ -964,16 +973,6 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num) TU_ASSERT(drv_id < TOTAL_DRIVER_COUNT); } - // invoke callback - if (cfg_num) - { - if (tud_mount_cb) tud_mount_cb(); - } - else - { - if (tud_umount_cb) tud_umount_cb(); - } - return true; } -- cgit v1.3.1 From 9602c06f8d52212b55b02533e188e91b7192c080 Mon Sep 17 00:00:00 2001 From: Rocky04 Date: Mon, 7 Aug 2023 21:25:50 +0200 Subject: Correcting comments --- src/device/usbd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index 2daf91d77..156b92ce1 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -710,9 +710,10 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const _usbd_dev.speed = speed; // restore speed } - // switch to new configuration if not zero + // Handle the new configuration and execute the corresponding callback if ( cfg_num ) { + // switch to new configuration if not zero TU_ASSERT( process_set_config(rhport, cfg_num) ); if ( tud_mount_cb ) tud_mount_cb(); -- cgit v1.3.1 From 6d877c31705e4343d30e2a6b65cbd230a3fe2001 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 8 Aug 2023 18:50:24 +0700 Subject: added cmake for lpc54, update lpc55 --- hw/bsp/lpc54/boards/lpcxpresso54608/board.h | 59 ++++++++ hw/bsp/lpc54/boards/lpcxpresso54608/board.mk | 18 +++ hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake | 22 +++ hw/bsp/lpc54/family.cmake | 157 +++++++++++++++++++++ hw/bsp/lpc55/boards/double_m33_express/board.cmake | 7 +- hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake | 5 + hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake | 7 +- hw/bsp/lpc55/family.cmake | 134 +++++++++++------- src/tusb_option.h | 7 +- 9 files changed, 356 insertions(+), 60 deletions(-) create mode 100644 hw/bsp/lpc54/boards/lpcxpresso54608/board.h create mode 100644 hw/bsp/lpc54/boards/lpcxpresso54608/board.mk create mode 100644 hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake create mode 100644 hw/bsp/lpc54/family.cmake (limited to 'src') diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h new file mode 100644 index 000000000..8bbe18155 --- /dev/null +++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h @@ -0,0 +1,59 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_LPCXPRESSO54608_H_ +#define BOARD_LPCXPRESSO54608_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// LED +#define LED_PORT 2 +#define LED_PIN 2 +#define LED_STATE_ON 0 + +// WAKE button +#define BUTTON_PORT 1 +#define BUTTON_PIN 1 +#define BUTTON_STATE_ACTIVE 0 + +// UART +#define UART_DEV USART0 +#define UART_RX_PINMUX 0, 29, IOCON_PIO_DIG_FUNC1_EN +#define UART_TX_PINMUX 0, 30, IOCON_PIO_DIG_FUNC1_EN + +// USB0 VBUS +#define USB0_VBUS_PINMUX 0, 22, IOCON_PIO_DIG_FUNC7_EN + +// XTAL +//#define XTAL0_CLK_HZ (16 * 1000 * 1000U) + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.mk b/hw/bsp/lpc54/boards/lpcxpresso54608/board.mk new file mode 100644 index 000000000..af2eaf507 --- /dev/null +++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.mk @@ -0,0 +1,18 @@ +MCU_VARIANT = LPC54608 +MCU_CORE = LPC54608 + +PORT ?= 1 + +CFLAGS += -DCPU_LPC54608J512ET180 +CFLAGS += -Wno-error=double-promotion + +LD_FILE = $(MCU_DIR)/gcc/LPC54608J512_flash.ld + +LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a + +JLINK_DEVICE = LPC54608J512 +PYOCD_TARGET = LPC54608 + +#flash: flash-pyocd + +flash: flash-jlink diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake new file mode 100644 index 000000000..1dea6f353 --- /dev/null +++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake @@ -0,0 +1,22 @@ +set(MCU_VARIANT LPC54628) +set(MCU_CORE LPC54628) + +set(JLINK_DEVICE LPC54628J512) +set(PYOCD_TARGET LPC54628) +set(NXPLINK_DEVICE LPC54628:LPCXpresso54628) + +set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54628J512_flash.ld) + +# Device port default to PORT1 Highspeed +if (NOT DEFINED PORT) + set(PORT 1) +endif() + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + CPU_LPC54628J512ET180 + ) + target_link_libraries(${TARGET} PUBLIC + ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower_hardabi.a + ) +endfunction() diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake new file mode 100644 index 000000000..0512fe31f --- /dev/null +++ b/hw/bsp/lpc54/family.cmake @@ -0,0 +1,157 @@ +include_guard() + +if (NOT BOARD) + message(FATAL_ERROR "BOARD not specified") +endif () + +set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk) +set(CMSIS_DIR ${TOP}/lib/CMSIS_5) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS LPC54 CACHE INTERNAL "") + +if (NOT DEFINED PORT) + set(PORT 0) +endif() + +# Host port will be the other port if available +set(HOST_PORT $) + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (NOT TARGET ${BOARD_TARGET}) + add_library(${BOARD_TARGET} STATIC + # driver + ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c + ${SDK_DIR}/drivers/common/fsl_common_arm.c + ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c + ${SDK_DIR}/drivers/flexcomm/fsl_usart.c + # mcu + ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c + ) + + target_compile_definitions(${BOARD_TARGET} PUBLIC + CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\) + BOARD_TUD_RHPORT=${PORT} + BOARD_TUH_RHPORT=${HOST_PORT} + ) + # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM + if (PORT EQUAL 1) + target_compile_definitions(${BOARD_TARGET} PUBLIC + BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED + CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) + ) + else () + target_compile_definitions(${BOARD_TARGET} PUBLIC + BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED + BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED + CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) + ) + endif () + + target_include_directories(${BOARD_TARGET} PUBLIC + ${TOP}/lib/sct_neopixel + # driver + ${SDK_DIR}/drivers/common + ${SDK_DIR}/drivers/flexcomm + ${SDK_DIR}/drivers/lpc_iocon + ${SDK_DIR}/drivers/lpc_gpio + ${SDK_DIR}/drivers/lpuart + ${SDK_DIR}/drivers/sctimer + # mcu + ${CMSIS_DIR}/CMSIS/Core/Include + ${SDK_DIR}/devices/${MCU_VARIANT} + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers + ) + + update_board(${BOARD_TARGET}) + + if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID}) + set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) + endif () + + if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID}) + set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S) + endif () + + target_sources(${BOARD_TARGET} PUBLIC + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + # linker file + "LINKER:--script=${LD_FILE_GNU}" + # nanolib + --specs=nosys.specs + --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + # external driver + ${TOP}/lib/sct_neopixel/sct_neopixel.c + ) + + # https://github.com/gsteiert/sct_neopixel/pull/1 + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + set_source_files_properties(${TOP}/lib/sct_neopixel/sct_neopixel.c PROPERTIES + COMPILE_FLAGS "-Wno-unused-parameter") + endif () + + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_LPC54 ${RTOS}) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + + # Link dependencies + target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + + # Flashing + family_flash_jlink(${TARGET}) + #family_flash_nxplink(${TARGET}) + #family_flash_pyocd(${TARGET}) +endfunction() diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.cmake b/hw/bsp/lpc55/boards/double_m33_express/board.cmake index f84e629c7..3324ce888 100644 --- a/hw/bsp/lpc55/boards/double_m33_express/board.cmake +++ b/hw/bsp/lpc55/boards/double_m33_express/board.cmake @@ -7,10 +7,13 @@ set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69) set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/LPC55S69_cm33_core0_uf2.ld) +# Device port default to PORT1 Highspeed +if (NOT DEFINED PORT) + set(PORT 1) +endif() + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC CPU_LPC55S69JBD100_cm33_core0 - # port 1 is highspeed - BOARD_TUD_RHPORT=1 ) endfunction() diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake index d935b70e6..b3d0c3349 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake @@ -5,6 +5,11 @@ set(JLINK_DEVICE LPC55S28) set(PYOCD_TARGET LPC55S28) set(NXPLINK_DEVICE LPC55S28:LPCXpresso55S28) +# Device port default to PORT1 Highspeed +if (NOT DEFINED PORT) + set(PORT 1) +endif() + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC CPU_LPC55S28JBD100 diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake index fd7cb6de6..3af6034ad 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake @@ -5,10 +5,13 @@ set(JLINK_DEVICE LPC55S69) set(PYOCD_TARGET LPC55S69) set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69) +# Device port default to PORT1 Highspeed +if (NOT DEFINED PORT) + set(PORT 1) +endif() + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC CPU_LPC55S69JBD100_cm33_core0 - # port 1 is highspeed - # BOARD_TUD_RHPORT=1 ) endfunction() diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake index dfd08a732..dce197b2d 100644 --- a/hw/bsp/lpc55/family.cmake +++ b/hw/bsp/lpc55/family.cmake @@ -7,79 +7,105 @@ endif () set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk) set(CMSIS_DIR ${TOP}/lib/CMSIS_5) +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + # toolchain set up set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(FAMILY_MCUS LPC55XX CACHE INTERNAL "") +set(FAMILY_MCUS LPC55 CACHE INTERNAL "") -# include board specific -include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) +if (NOT DEFINED PORT) + set(PORT 0) +endif() +# Host port will be the other port if available +set(HOST_PORT $) #------------------------------------ # BOARD_TARGET #------------------------------------ # only need to be built ONCE for all examples function(add_board_target BOARD_TARGET) - if (NOT TARGET ${BOARD_TARGET}) - add_library(${BOARD_TARGET} STATIC - # driver - ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c - ${SDK_DIR}/drivers/common/fsl_common_arm.c - ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c - ${SDK_DIR}/drivers/flexcomm/fsl_usart.c - # mcu - ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c - ) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + add_library(${BOARD_TARGET} STATIC + # driver + ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c + ${SDK_DIR}/drivers/common/fsl_common_arm.c + ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c + ${SDK_DIR}/drivers/flexcomm/fsl_usart.c + # mcu + ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c + ) + + target_compile_definitions(${BOARD_TARGET} PUBLIC + CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\) + BOARD_TUD_RHPORT=${PORT} + BOARD_TUH_RHPORT=${HOST_PORT} + ) + # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM + if (PORT EQUAL 1) target_compile_definitions(${BOARD_TARGET} PUBLIC - CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\) + BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED + CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) ) - target_include_directories(${BOARD_TARGET} PUBLIC - ${TOP}/lib/sct_neopixel - # driver - ${SDK_DIR}/drivers/common - ${SDK_DIR}/drivers/flexcomm - ${SDK_DIR}/drivers/lpc_iocon - ${SDK_DIR}/drivers/lpc_gpio - ${SDK_DIR}/drivers/lpuart - ${SDK_DIR}/drivers/sctimer - # mcu - ${CMSIS_DIR}/CMSIS/Core/Include - ${SDK_DIR}/devices/${MCU_VARIANT} - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers + else () + target_compile_definitions(${BOARD_TARGET} PUBLIC + BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED + BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED + CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) ) + endif () - update_board(${BOARD_TARGET}) + target_include_directories(${BOARD_TARGET} PUBLIC + ${TOP}/lib/sct_neopixel + # driver + ${SDK_DIR}/drivers/common + ${SDK_DIR}/drivers/flexcomm + ${SDK_DIR}/drivers/lpc_iocon + ${SDK_DIR}/drivers/lpc_gpio + ${SDK_DIR}/drivers/lpuart + ${SDK_DIR}/drivers/sctimer + # mcu + ${CMSIS_DIR}/CMSIS/Core/Include + ${SDK_DIR}/devices/${MCU_VARIANT} + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers + ) - if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID}) - set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) - endif () + update_board(${BOARD_TARGET}) - if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID}) - set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S) - endif () + if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID}) + set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) + endif () - target_sources(${BOARD_TARGET} PUBLIC - ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} - ) + if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID}) + set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S) + endif () - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${BOARD_TARGET} PUBLIC - # linker file - "LINKER:--script=${LD_FILE_GNU}" - # nanolib - --specs=nosys.specs - --specs=nano.specs - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--config=${LD_FILE_IAR}" - ) - endif () + target_sources(${BOARD_TARGET} PUBLIC + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + # linker file + "LINKER:--script=${LD_FILE_GNU}" + # nanolib + --specs=nosys.specs + --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) endif () endfunction() @@ -117,7 +143,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC55XX ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_LPC55 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) diff --git a/src/tusb_option.h b/src/tusb_option.h index 7a4cfe51c..c72117850 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -51,8 +51,11 @@ #define OPT_MCU_LPC40XX 7 ///< NXP LPC40xx #define OPT_MCU_LPC43XX 8 ///< NXP LPC43xx #define OPT_MCU_LPC51UXX 9 ///< NXP LPC51U6x -#define OPT_MCU_LPC54XXX 10 ///< NXP LPC54xxx -#define OPT_MCU_LPC55XX 11 ///< NXP LPC55xx +#define OPT_MCU_LPC54 10 ///< NXP LPC54 +#define OPT_MCU_LPC55 11 ///< NXP LPC55 +// legacy naming +#define OPT_MCU_LPC54XXX OPT_MCU_LPC54 +#define OPT_MCU_LPC55XX OPT_MCU_LPC55 // NRF #define OPT_MCU_NRF5X 100 ///< Nordic nRF5x series -- cgit v1.3.1 From b8b01c10758043d318716569e693912f3e02c75b Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 8 Aug 2023 21:59:36 +0700 Subject: update to dcd ip3511 to add work-around for lpc54628 usb hs errata USB.1 and USB.2 msc is mounted, but device couldn't work reliably and got constant reset due to other errata probably. --- .idea/cmake.xml | 4 +- hw/bsp/lpc54/family.c | 6 +- hw/bsp/lpc54/family.cmake | 1 + src/common/tusb_common.h | 5 +- src/common/tusb_mcu.h | 8 +- src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 266 ++++++++++++++++----------- 6 files changed, 170 insertions(+), 120 deletions(-) (limited to 'src') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 76143ba10..4a69d02cf 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -30,7 +30,8 @@ - + + @@ -51,6 +52,7 @@ + \ No newline at end of file diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c index 108a7d783..7411c72d4 100644 --- a/hw/bsp/lpc54/family.c +++ b/hw/bsp/lpc54/family.c @@ -70,13 +70,11 @@ //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void USB0_IRQHandler(void) -{ +void USB0_IRQHandler(void) { tud_int_handler(0); } -void USB1_IRQHandler(void) -{ +void USB1_IRQHandler(void) { tud_int_handler(1); } diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake index 0512fe31f..b016441c1 100644 --- a/hw/bsp/lpc54/family.cmake +++ b/hw/bsp/lpc54/family.cmake @@ -59,6 +59,7 @@ function(add_board_target BOARD_TARGET) BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) + #CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) ) endif () diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 25f85e501..c303c6eaf 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -159,11 +159,12 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_max16 (uint16_t x, uint16_t y) { TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_max32 (uint32_t x, uint32_t y) { return (x > y) ? x : y; } //------------- Align -------------// -TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t alignment) -{ +TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t alignment) { return value & ((uint32_t) ~(alignment-1)); } +TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4 (uint32_t value) { return (value & 0xFFFFFFFCUL); } +TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align8 (uint32_t value) { return (value & 0xFFFFFFF8UL); } TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align16 (uint32_t value) { return (value & 0xFFFFFFF0UL); } TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align32 (uint32_t value) { return (value & 0xFFFFFFE0UL); } TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4k (uint32_t value) { return (value & 0xFFFFF000UL); } diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 89f89182e..35f94efbc 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -58,6 +58,7 @@ // NXP //--------------------------------------------------------------------+ #if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX) + #define TUP_USBIP_IP3511 #define TUP_DCD_ENDPOINT_MAX 5 #elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX) @@ -66,14 +67,17 @@ #define TUP_OHCI_RHPORTS 2 #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX) + #define TUP_USBIP_IP3511 #define TUP_DCD_ENDPOINT_MAX 5 -#elif TU_CHECK_MCU(OPT_MCU_LPC54XXX) +#elif TU_CHECK_MCU(OPT_MCU_LPC54) // TODO USB0 has 5, USB1 has 6 + #define TUP_USBIP_IP3511 #define TUP_DCD_ENDPOINT_MAX 6 -#elif TU_CHECK_MCU(OPT_MCU_LPC55XX) +#elif TU_CHECK_MCU(OPT_MCU_LPC55) // TODO USB0 has 5, USB1 has 6 + #define TUP_USBIP_IP3511 #define TUP_DCD_ENDPOINT_MAX 6 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c index 7ca698a93..f4ed09d83 100644 --- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c +++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c @@ -34,18 +34,13 @@ * - LPC54114 * - LPC55s69 */ -#if CFG_TUD_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_LPC11UXX || \ - CFG_TUSB_MCU == OPT_MCU_LPC13XX || \ - CFG_TUSB_MCU == OPT_MCU_LPC15XX || \ - CFG_TUSB_MCU == OPT_MCU_LPC51UXX || \ - CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \ - CFG_TUSB_MCU == OPT_MCU_LPC55XX) +#if CFG_TUD_ENABLED && defined(TUP_USBIP_IP3511) //--------------------------------------------------------------------+ // INCLUDE //--------------------------------------------------------------------+ -#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX || CFG_TUSB_MCU == OPT_MCU_LPC15XX +#if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX) // LPCOpen #include "chip.h" #else @@ -80,7 +75,7 @@ typedef struct { enum { NBYTES_ISO_FS_MAX = 1023, // FS ISO NBYTES_ISO_HS_MAX = 1024, // HS ISO - NBYTES_CBI_FS_MAX = 64, // FS control/bulk/interrupt + NBYTES_CBI_FS_MAX = 64, // FS control/bulk/interrupt. TODO some FS can do burst with higher size e.g 1024. Need to test NBYTES_CBI_HS_MAX = 32767 // can be up to all 15-bit, but only tested with 4096 }; @@ -90,26 +85,36 @@ enum { }; enum { - CMDSTAT_DEVICE_ADDR_MASK = TU_BIT(7 )-1, - CMDSTAT_DEVICE_ENABLE_MASK = TU_BIT(7 ), - CMDSTAT_SETUP_RECEIVED_MASK = TU_BIT(8 ), - CMDSTAT_DEVICE_CONNECT_MASK = TU_BIT(16), // reflect the soft-connect only, does not reflect the actual attached state - CMDSTAT_DEVICE_SUSPEND_MASK = TU_BIT(17), - // 23-22 is link speed (only available for HighSpeed port) - CMDSTAT_CONNECT_CHANGE_MASK = TU_BIT(24), - CMDSTAT_SUSPEND_CHANGE_MASK = TU_BIT(25), - CMDSTAT_RESET_CHANGE_MASK = TU_BIT(26), - CMDSTAT_VBUS_DEBOUNCED_MASK = TU_BIT(28), + DEVCMDSTAT_DEVICE_ADDR_MASK = TU_BIT(7 )-1, + DEVCMDSTAT_DEVICE_ENABLE_MASK = TU_BIT(7 ), + DEVCMDSTAT_SETUP_RECEIVED_MASK = TU_BIT(8 ), + DEVCMDSTAT_DEVICE_CONNECT_MASK = TU_BIT(16), // reflect the soft-connect only, does not reflect the actual attached state + DEVCMDSTAT_DEVICE_SUSPEND_MASK = TU_BIT(17), + // 23-22 is link speed (only available for HighSpeed port) + DEVCMDSTAT_CONNECT_CHANGE_MASK = TU_BIT(24), + DEVCMDSTAT_SUSPEND_CHANGE_MASK = TU_BIT(25), + DEVCMDSTAT_RESET_CHANGE_MASK = TU_BIT(26), + DEVCMDSTAT_VBUS_DEBOUNCED_MASK = TU_BIT(28), }; enum { - CMDSTAT_SPEED_SHIFT = 22 + DEVCMDSTAT_SPEED_SHIFT = 22 }; //--------------------------------------------------------------------+ // Endpoint Command/Status List //--------------------------------------------------------------------+ +// EP Command/Status field definition +enum { + EPCS_TYPE = TU_BIT(26), + EPCS_RF_TV = TU_BIT(27), + EPCS_TOGGLE_RESET = TU_BIT(28), + EPCS_STALL = TU_BIT(29), + EPCS_DISABLED = TU_BIT(30), + EPCS_ACTIVE = TU_BIT(31), +}; + // Endpoint Command/Status typedef union TU_ATTR_PACKED { @@ -133,8 +138,8 @@ typedef union TU_ATTR_PACKED volatile struct { uint32_t TU_RESERVED : 26; - uint32_t is_iso : 1 ; - uint32_t toggle_mode : 1 ; + uint32_t type : 1 ; + uint32_t rf_tv : 1 ; // rate feedback or toggle value uint32_t toggle_reset : 1 ; uint32_t stall : 1 ; uint32_t disable : 1 ; @@ -180,6 +185,7 @@ typedef struct CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd; // Dummy buffer to fix ZLPs overwriting the buffer (probably an USB/DMA controller bug) +// TODO find way to save memory CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8]; //--------------------------------------------------------------------+ @@ -188,59 +194,73 @@ CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8]; typedef struct { - dcd_registers_t* regs; // registers - const tusb_speed_t max_speed; // max link speed - const IRQn_Type irqnum; // IRQ number - const uint8_t ep_pairs; // Max bi-directional Endpoints + dcd_registers_t* regs; // registers + const bool is_highspeed; // max link speed + const IRQn_Type irqnum; // IRQ number + const uint8_t ep_pairs; // Max bi-directional Endpoints }dcd_controller_t; #ifdef INCLUDE_FSL_DEVICE_REGISTERS -static const dcd_controller_t _dcd_controller[] = -{ - { .regs = (dcd_registers_t*) USB0_BASE , .max_speed = TUSB_SPEED_FULL, .irqnum = USB0_IRQn, .ep_pairs = FSL_FEATURE_USB_EP_NUM }, +static const dcd_controller_t _dcd_controller[] = { + { .regs = (dcd_registers_t*) USB0_BASE , .is_highspeed = false, .irqnum = USB0_IRQn, .ep_pairs = FSL_FEATURE_USB_EP_NUM }, #if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT - { .regs = (dcd_registers_t*) USBHSD_BASE, .max_speed = TUSB_SPEED_HIGH, .irqnum = USB1_IRQn, .ep_pairs = FSL_FEATURE_USBHSD_EP_NUM } + { .regs = (dcd_registers_t*) USBHSD_BASE, .is_highspeed = true, .irqnum = USB1_IRQn, .ep_pairs = FSL_FEATURE_USBHSD_EP_NUM } #endif }; #else -static const dcd_controller_t _dcd_controller[] = -{ - { .regs = (dcd_registers_t*) LPC_USB0_BASE, .max_speed = TUSB_SPEED_FULL, .irqnum = USB0_IRQn, .ep_pairs = 5 }, +static const dcd_controller_t _dcd_controller[] = { + { .regs = (dcd_registers_t*) LPC_USB0_BASE, .is_highspeed = false, .irqnum = USB0_IRQn, .ep_pairs = 5 }, }; #endif +#if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT + #define IP3511_HAS_HIGHSPEED +#endif + //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -static inline uint16_t get_buf_offset(void const * buffer) -{ +TU_ATTR_ALWAYS_INLINE static inline uint16_t get_buf_offset(void const * buffer) { uint32_t addr = (uint32_t) buffer; TU_ASSERT( (addr & 0x3f) == 0, 0 ); return ( (addr >> 6) & 0xFFFFUL ) ; } -static inline uint8_t ep_addr2id(uint8_t ep_addr) -{ +TU_ATTR_ALWAYS_INLINE static inline uint8_t ep_addr2id(uint8_t ep_addr) { return 2*(ep_addr & 0x0F) + ((ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0); } +TU_ATTR_ALWAYS_INLINE static inline bool ep_is_iso(ep_cmd_sts_t* ep_cs, bool is_highspeed) { + return is_highspeed ? (ep_cs[0].cmd_sts.type && !ep_cs[0].cmd_sts.rf_tv) : ep_cs->cmd_sts.type; +} + +TU_ATTR_ALWAYS_INLINE static inline bool ep_is_bulk(ep_cmd_sts_t* ep_cs) { + return (ep_cs[0].cmd_sts.type == 0) && (ep_cs[0].cmd_sts.rf_tv == 0); +} + +TU_ATTR_ALWAYS_INLINE static inline ep_cmd_sts_t* get_ep_cs(uint8_t ep_id) { + return _dcd.ep[ep_id]; +} + +TU_ATTR_ALWAYS_INLINE static inline bool rhport_is_highspeed(uint8_t rhport) { + return _dcd_controller[rhport].is_highspeed; +} + //--------------------------------------------------------------------+ // CONTROLLER API //--------------------------------------------------------------------+ -static void prepare_setup_packet(uint8_t rhport) -{ - if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL ) - { - _dcd.ep[0][1].buffer_fs.offset = get_buf_offset(_dcd.setup_packet); - }else - { - _dcd.ep[0][1].buffer_hs.offset = get_buf_offset(_dcd.setup_packet); +static void prepare_setup_packet(uint8_t rhport) { + uint16_t const buf_offset = get_buf_offset(_dcd.setup_packet); + if ( _dcd_controller[rhport].is_highspeed ) { + _dcd.ep[0][1].buffer_hs.offset = buf_offset; + } else { + _dcd.ep[0][1].buffer_fs.offset = buf_offset; } } @@ -268,8 +288,8 @@ void dcd_init(uint8_t rhport) dcd_reg->DATABUFSTART = tu_align((uint32_t) &_dcd, TU_BIT(22)); // 22-bit alignment dcd_reg->INTSTAT |= dcd_reg->INTSTAT; // clear all pending interrupt dcd_reg->INTEN = INT_DEVICE_STATUS_MASK; - dcd_reg->DEVCMDSTAT |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK | - CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK; + dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_DEVICE_ENABLE_MASK | DEVCMDSTAT_DEVICE_CONNECT_MASK | + DEVCMDSTAT_RESET_CHANGE_MASK | DEVCMDSTAT_CONNECT_CHANGE_MASK | DEVCMDSTAT_SUSPEND_CHANGE_MASK; NVIC_ClearPendingIRQ(_dcd_controller[rhport].irqnum); } @@ -291,7 +311,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) // Response with status first before changing device address dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); - dcd_reg->DEVCMDSTAT &= ~CMDSTAT_DEVICE_ADDR_MASK; + dcd_reg->DEVCMDSTAT &= ~DEVCMDSTAT_DEVICE_ADDR_MASK; dcd_reg->DEVCMDSTAT |= dev_addr; } @@ -303,13 +323,13 @@ void dcd_remote_wakeup(uint8_t rhport) void dcd_connect(uint8_t rhport) { dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - dcd_reg->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK; + dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_DEVICE_CONNECT_MASK; } void dcd_disconnect(uint8_t rhport) { dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - dcd_reg->DEVCMDSTAT &= ~CMDSTAT_DEVICE_CONNECT_MASK; + dcd_reg->DEVCMDSTAT &= ~DEVCMDSTAT_DEVICE_CONNECT_MASK; } void dcd_sof_enable(uint8_t rhport, bool en) @@ -340,19 +360,39 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) _dcd.ep[ep_id][0].cmd_sts.stall = 0; _dcd.ep[ep_id][0].cmd_sts.toggle_reset = 1; - _dcd.ep[ep_id][0].cmd_sts.toggle_mode = 0; + _dcd.ep[ep_id][0].cmd_sts.rf_tv = 0; } bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { //------------- Prepare Queue Head -------------// uint8_t ep_id = ep_addr2id(p_endpoint_desc->bEndpointAddress); + ep_cmd_sts_t* ep_cs = get_ep_cs(ep_id); // Check if endpoint is available - TU_ASSERT( _dcd.ep[ep_id][0].cmd_sts.disable && _dcd.ep[ep_id][1].cmd_sts.disable ); + TU_ASSERT( ep_cs[0].cmd_sts.disable && ep_cs[1].cmd_sts.disable ); edpt_reset(rhport, ep_id); - _dcd.ep[ep_id][0].cmd_sts.is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS); + + switch (p_endpoint_desc->bmAttributes.xfer) { + case TUSB_XFER_ISOCHRONOUS: + ep_cs[0].cmd_sts.type = 1; + break; + + case TUSB_XFER_INTERRUPT: + // What is interrupt endpoint in rate feedback mode ? + if ( rhport_is_highspeed(rhport) ) { + ep_cs[0].cmd_sts.type = 1; + ep_cs[0].cmd_sts.rf_tv = 1; + } + break; + + case TUSB_XFER_BULK: + // nothing to do both type and rf_tv are 0 + break; + + default: break; + } // Enable EP interrupt dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; @@ -379,42 +419,50 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) _dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1; } -static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes) -{ +static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes) { uint16_t nbytes; - - if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL ) - { - nbytes = tu_min16(total_bytes, _dcd.ep[ep_id][0].cmd_sts.is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX); - _dcd.ep[ep_id][0].buffer_fs.offset = buf_offset; - _dcd.ep[ep_id][0].buffer_fs.nbytes = nbytes; - }else - { - nbytes = tu_min16(total_bytes, NBYTES_CBI_HS_MAX); - _dcd.ep[ep_id][0].buffer_hs.offset = buf_offset; - _dcd.ep[ep_id][0].buffer_hs.nbytes = nbytes; + ep_cmd_sts_t* ep_cs = get_ep_cs(ep_id); + + const bool is_iso = ep_is_iso(ep_cs, _dcd_controller[rhport].is_highspeed); + + if ( rhport_is_highspeed(rhport) ) { + nbytes = tu_min16(total_bytes, is_iso ? NBYTES_ISO_HS_MAX : NBYTES_CBI_HS_MAX); + #if TU_CHECK_MCU(OPT_MCU_LPC54) + // LPC54 Errata USB.1: In USB high-speed device mode, the NBytes field does not decrement after BULK OUT transfer. + // Suggested Work-around: Program the NByte to the max packet size (512) + // Actual Work-around: round up NByte to multiple of 4. + // Note: this can cause buffer overflowed and corrupt data if host send more data than total_bytes + if ( (ep_id > 1) && (ep_id & 0x01) == 0 && ep_is_bulk(ep_cs) ) { + if ( nbytes & 0x03 ) { + nbytes = tu_align4(nbytes) + 4; + } + } + #endif + + ep_cs[0].buffer_hs.offset = buf_offset; + ep_cs[0].buffer_hs.nbytes = nbytes; + }else { + nbytes = tu_min16(total_bytes, is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX); + ep_cs[0].buffer_fs.offset = buf_offset; + ep_cs[0].buffer_fs.nbytes = nbytes; } _dcd.dma[ep_id].nbytes = nbytes; - - _dcd.ep[ep_id][0].cmd_sts.active = 1; + ep_cs[0].cmd_sts.active = 1; } -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) -{ +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { uint8_t const ep_id = ep_addr2id(ep_addr); + if (!buffer || total_bytes == 0) { + // Although having no data, ZLPs can cause buffer overwritten to zeroes. Probably due to USB/DMA controller side + // effect/bug. Assigned buffer offset to (valid) dummy to prevent overwriting to DATABUFSTART + buffer = (uint8_t *) (uint32_t) dummy; + } + tu_memclr(&_dcd.dma[ep_id], sizeof(xfer_dma_t)); _dcd.dma[ep_id].total_bytes = total_bytes; - if (!buffer) - { - // Although having no data, ZLPs can cause buffer overwritten to zeroes. - // Probably due to USB/DMA controller side effect/bug. - // Assigned buffer offset to (valid) dummy to prevent overwriting to DATABUFSTART - buffer = (uint8_t*)(uint32_t)dummy; - } - prepare_ep_xfer(rhport, ep_id, get_buf_offset(buffer), total_bytes); return true; @@ -441,23 +489,19 @@ static void bus_reset(uint8_t rhport) dcd_reg->EPSKIP = 0xFFFFFFFF; dcd_reg->INTSTAT = dcd_reg->INTSTAT; // clear all pending interrupt - dcd_reg->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK; // clear setup received interrupt + dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_SETUP_RECEIVED_MASK; // clear setup received interrupt dcd_reg->INTEN = INT_DEVICE_STATUS_MASK | TU_BIT(0) | TU_BIT(1); // enable device status & control endpoints } -static void process_xfer_isr(uint8_t rhport, uint32_t int_status) -{ +static void process_xfer_isr(uint8_t rhport, uint32_t int_status) { uint8_t const max_ep = 2*_dcd_controller[rhport].ep_pairs; - for(uint8_t ep_id = 0; ep_id < max_ep; ep_id++ ) - { - if ( tu_bit_test(int_status, ep_id) ) - { + for(uint8_t ep_id = 0; ep_id < max_ep; ep_id++ ) { + if ( tu_bit_test(int_status, ep_id) ) { ep_cmd_sts_t * ep_cs = &_dcd.ep[ep_id][0]; xfer_dma_t* xfer_dma = &_dcd.dma[ep_id]; - if ( ep_id == 0 || ep_id == 1) - { + if ( ep_id <= 1 ) { // For control endpoint, we need to manually clear Active bit ep_cs->cmd_sts.active = 0; } @@ -465,26 +509,29 @@ static void process_xfer_isr(uint8_t rhport, uint32_t int_status) uint16_t buf_offset; uint16_t buf_nbytes; - if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL) - { - buf_offset = ep_cs->buffer_fs.offset; - buf_nbytes = ep_cs->buffer_fs.nbytes; - }else - { + if ( rhport_is_highspeed(rhport) ) { buf_offset = ep_cs->buffer_hs.offset; buf_nbytes = ep_cs->buffer_hs.nbytes; + + #if TU_CHECK_MCU(OPT_MCU_LPC54) + // LPC54 Errata USB.2: In USB high-speed device mode, the NBytes field is not correct after BULK IN transfer + // There is no work-around. For EP in transfer, the NByte value can be ignored after a packet is transmitted. + if ( (ep_id > 1) && (ep_id & 0x01) == 1 && ep_is_bulk(ep_cs) ) { + buf_nbytes = 0; + } + #endif + } else { + buf_offset = ep_cs->buffer_fs.offset; + buf_nbytes = ep_cs->buffer_fs.nbytes; } xfer_dma->xferred_bytes += xfer_dma->nbytes - buf_nbytes; - if ( (buf_nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) ) - { + if ( (buf_nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) ) { // There is more data to transfer // buff_offset has been already increased by hw to correct value for next transfer prepare_ep_xfer(rhport, ep_id, buf_offset, xfer_dma->total_bytes - xfer_dma->xferred_bytes); - } - else - { + } else { // for detecting ZLP xfer_dma->total_bytes = xfer_dma->xferred_bytes; @@ -511,19 +558,16 @@ void dcd_int_handler(uint8_t rhport) //------------- Device Status -------------// if ( int_status & INT_DEVICE_STATUS_MASK ) { - dcd_reg->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK; + dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_RESET_CHANGE_MASK | DEVCMDSTAT_CONNECT_CHANGE_MASK | DEVCMDSTAT_SUSPEND_CHANGE_MASK; - if ( cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset + if ( cmd_stat & DEVCMDSTAT_RESET_CHANGE_MASK) // bus reset { bus_reset(rhport); tusb_speed_t speed = TUSB_SPEED_FULL; - - if (_dcd_controller[rhport].max_speed == TUSB_SPEED_HIGH) - { + if ( _dcd_controller[rhport].is_highspeed ) { // 0 : reserved, 1 : full, 2 : high, 3: super - if ( 2 == ((cmd_stat >> CMDSTAT_SPEED_SHIFT) & 0x3UL) ) - { + if ( 2 == ((cmd_stat >> DEVCMDSTAT_SPEED_SHIFT) & 0x3UL) ) { speed= TUSB_SPEED_HIGH; } } @@ -531,35 +575,35 @@ void dcd_int_handler(uint8_t rhport) dcd_event_bus_reset(rhport, speed, true); } - if (cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK) + if (cmd_stat & DEVCMDSTAT_CONNECT_CHANGE_MASK) { // device disconnect - if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK) + if (cmd_stat & DEVCMDSTAT_DEVICE_ADDR_MASK) { // debouncing as this can be set when device is powering dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); } } - if (cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK) + if (cmd_stat & DEVCMDSTAT_SUSPEND_CHANGE_MASK) { // suspend signal, bus idle for more than 3ms // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration. - if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK) + if (cmd_stat & DEVCMDSTAT_DEVICE_ADDR_MASK) { - dcd_event_bus_signal(rhport, (cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK) ? DCD_EVENT_SUSPEND : DCD_EVENT_RESUME, true); + dcd_event_bus_signal(rhport, (cmd_stat & DEVCMDSTAT_DEVICE_SUSPEND_MASK) ? DCD_EVENT_SUSPEND : DCD_EVENT_RESUME, true); } } } // Setup Receive - if ( tu_bit_test(int_status, 0) && (cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) ) + if ( tu_bit_test(int_status, 0) && (cmd_stat & DEVCMDSTAT_SETUP_RECEIVED_MASK) ) { // Follow UM flowchart to clear Active & Stall on both Control IN/OUT endpoints _dcd.ep[0][0].cmd_sts.active = _dcd.ep[1][0].cmd_sts.active = 0; _dcd.ep[0][0].cmd_sts.stall = _dcd.ep[1][0].cmd_sts.stall = 0; - dcd_reg->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK; + dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_SETUP_RECEIVED_MASK; dcd_event_setup_received(rhport, _dcd.setup_packet, true); -- cgit v1.3.1 From bd51afb091f29cdab6520479a1a504409d95aac8 Mon Sep 17 00:00:00 2001 From: tswan-quasi Date: Mon, 14 Aug 2023 08:49:52 -0400 Subject: min on cdc r/w --- src/class/cdc/cdc_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index 70d9c2e24..2c1fda4ff 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -150,7 +150,7 @@ uint32_t tud_cdc_n_available(uint8_t itf) uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize) { cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; - uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) bufsize); + uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) TU_MIN(bufsize, 65535)); _prep_out_transaction(p_cdc); return num_read; } @@ -173,7 +173,7 @@ void tud_cdc_n_read_flush (uint8_t itf) uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize) { cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; - uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) bufsize); + uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, 65535)); // flush if queue more than packet size // may need to suppress -Wunreachable-code since most of the time CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE -- cgit v1.3.1 From b5ba12119dccb123aa6e8798dc86d639af6703b9 Mon Sep 17 00:00:00 2001 From: tswan-quasi Date: Mon, 14 Aug 2023 09:01:30 -0400 Subject: UINT16_MAX stdint macro usage --- src/class/cdc/cdc_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index 2c1fda4ff..c26264e60 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -150,7 +150,7 @@ uint32_t tud_cdc_n_available(uint8_t itf) uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize) { cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; - uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) TU_MIN(bufsize, 65535)); + uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX)); _prep_out_transaction(p_cdc); return num_read; } @@ -173,7 +173,7 @@ void tud_cdc_n_read_flush (uint8_t itf) uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize) { cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; - uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, 65535)); + uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX)); // flush if queue more than packet size // may need to suppress -Wunreachable-code since most of the time CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE -- cgit v1.3.1 From 9d942967414d7b95f3a132c284ef83f386a0c467 Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Mon, 14 Aug 2023 15:38:48 -0700 Subject: fix issue 2188: support usbh_app_driver_get_cb() --- README.rst | 2 ++ src/host/usbh.c | 86 ++++++++++++++++++++++++++++++++------------- src/host/usbh_classdriver.h | 8 +++++ 3 files changed, 72 insertions(+), 24 deletions(-) (limited to 'src') diff --git a/README.rst b/README.rst index 78e8d87b0..d72cdb149 100644 --- a/README.rst +++ b/README.rst @@ -89,6 +89,8 @@ Host Stack - Mass Storage Class (MSC) - Hub with multiple-level support +Similar to the Device Stack, if you have a special requirement, `usbh_app_driver_get_cb()` can be used to write your own class driver without modifying the stack. + TypeC PD Stack ============== diff --git a/src/host/usbh.c b/src/host/usbh.c index cc7e38b45..af8142be3 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -180,7 +180,7 @@ static usbh_class_driver_t const usbh_class_drivers[] = #endif }; -enum { USBH_CLASS_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) }; +enum { USBH_BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) }; enum { CONFIG_NUM = 1 }; // default to use configuration 1 @@ -246,6 +246,21 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size); static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); +// Additional class drivers implemented by application +tu_static usbh_class_driver_t const * _app_driver = NULL; +tu_static uint8_t _app_driver_count = 0; +tu_static uint8_t _total_driver_count = USBH_BUILTIN_DRIVER_COUNT; + +static usbh_class_driver_t const * usbh_get_driver(uint8_t drv_id) +{ + usbh_class_driver_t const * driver = NULL; + if ( drv_id < _app_driver_count ) + driver = &_app_driver[drv_id]; + else if ( drv_id < _total_driver_count ) + driver = &usbh_class_drivers[drv_id - _app_driver_count]; + return driver; +} + #if CFG_TUSB_OS == OPT_OS_NONE // TODO rework time-related function later // weak and overridable @@ -339,6 +354,12 @@ bool tuh_init(uint8_t controller_id) { _usbh_mutex = osal_mutex_create(&_usbh_mutexdef); TU_ASSERT(_usbh_mutex); #endif + // Get application driver if available + if ( usbh_app_driver_get_cb ) + { + _app_driver = usbh_app_driver_get_cb(&_app_driver_count); + _total_driver_count = USBH_BUILTIN_DRIVER_COUNT + _app_driver_count; + } // Device tu_memclr(&_dev0, sizeof(_dev0)); @@ -351,10 +372,14 @@ bool tuh_init(uint8_t controller_id) { } // Class drivers - for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) + for (uint8_t drv_id = 0; drv_id < _total_driver_count; drv_id++) { - TU_LOG_USBH("%s init\r\n", usbh_class_drivers[drv_id].name); - usbh_class_drivers[drv_id].init(); + usbh_class_driver_t const * driver = usbh_get_driver(drv_id); + if ( driver ) + { + TU_LOG_USBH("%s init\r\n", driver->name); + driver->init(); + } } _usbh_controller = controller_id;; @@ -482,12 +507,16 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { }else #endif { - uint8_t const drv_id = dev->ep2drv[epnum][ep_dir]; - if ( drv_id < USBH_CLASS_DRIVER_COUNT ) { - TU_LOG_USBH("%s xfer callback\r\n", usbh_class_drivers[drv_id].name); - usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, + uint8_t drv_id = dev->ep2drv[epnum][ep_dir]; + usbh_class_driver_t const * driver = usbh_get_driver(drv_id); + if ( driver ) + { + TU_LOG_USBH("%s xfer callback\r\n", driver->name); + driver->xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len); - } else { + } + else + { // no driver/callback responsible for this transfer TU_ASSERT(false,); } @@ -1183,17 +1212,20 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu uint8_t nop_count = 0; #endif - for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) { + for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) + { usbh_device_t *dev = &_usbh_devices[dev_id]; uint8_t const daddr = dev_id + 1; // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub if (dev->rhport == rhport && dev->connected && (hub_addr == 0 || dev->hub_addr == hub_addr) && - (hub_port == 0 || dev->hub_port == hub_port)) { + (hub_port == 0 || dev->hub_port == hub_port)) + { TU_LOG_USBH("Device unplugged address = %u\r\n", daddr); - if (is_hub_addr(daddr)) { + if (is_hub_addr(daddr)) + { TU_LOG(CFG_TUH_LOG_LEVEL, " is a HUB device %u\r\n", daddr); // Submit removed event If the device itself is a hub (un-rolled recursive) @@ -1211,10 +1243,14 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu } // Close class driver - for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) { - usbh_class_drivers[drv_id].close(daddr); + for (uint8_t drv_id = 0; drv_id < _total_driver_count; drv_id++) + { + usbh_class_driver_t const * driver = usbh_get_driver(drv_id); + if ( driver ) + { + driver->close(daddr); + } } - hcd_device_close(rhport, daddr); clear_device(dev); // abort on-going control xfer if any @@ -1643,11 +1679,12 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t)); // Find driver for this interface - for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) + uint8_t drv_id = 0; + for (; drv_id < _total_driver_count; drv_id++) { - usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id]; + usbh_class_driver_t const * driver = usbh_get_driver(drv_id); - if ( driver->open(dev->rhport, dev_addr, desc_itf, drv_len) ) + if (driver && driver->open(dev->rhport, dev_addr, desc_itf, drv_len) ) { // open successfully TU_LOG_USBH(" %s opened\r\n", driver->name); @@ -1668,11 +1705,12 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur break; // exit driver find loop } - if( drv_id >= USBH_CLASS_DRIVER_COUNT ) - { - TU_LOG(CFG_TUH_LOG_LEVEL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n", - desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol); - } + } + + if( drv_id >= _total_driver_count ) + { + TU_LOG(CFG_TUH_LOG_LEVEL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n", + desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol); } // next Interface or IAD descriptor @@ -1694,7 +1732,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) uint8_t const drv_id = dev->itf2drv[itf_num]; if (drv_id != TUSB_INDEX_INVALID_8) { - usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id]; + usbh_class_driver_t const * driver = usbh_get_driver(drv_id); TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num); driver->set_config(dev_addr, itf_num); break; diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h index 308b4418a..7443b2d90 100644 --- a/src/host/usbh_classdriver.h +++ b/src/host/usbh_classdriver.h @@ -96,6 +96,14 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr); // Check if endpoint transferring is complete bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr); +//--------------------------------------------------------------------+ +// USBH application additional driver API +//--------------------------------------------------------------------+ +// Invoked when initializing host stack to get additional class drivers. +// Can optionally implemented by application to extend/overwrite class driver support. +// Note: The drivers array must be accessible at all time when stack is active +usbh_class_driver_t const* usbh_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK; + #ifdef __cplusplus } #endif -- cgit v1.3.1 From 1b33a315365184a74a8b5bbce5fdbdfc4dfe6f69 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 15 Aug 2023 22:51:21 +0700 Subject: more minor clean up - also rename usbh_classdriver.h to usbh_pvt.h to consitent with usbd --- src/class/cdc/cdc_host.c | 2 +- src/class/hid/hid_host.c | 2 +- src/class/msc/msc_host.c | 2 +- src/device/usbd.c | 31 +++++-------- src/device/usbd_pvt.h | 2 +- src/host/hub.c | 2 +- src/host/usbh.c | 84 ++++++++++++++++----------------- src/host/usbh_classdriver.h | 111 -------------------------------------------- src/host/usbh_pvt.h | 108 ++++++++++++++++++++++++++++++++++++++++++ src/tusb.c | 2 +- 10 files changed, 164 insertions(+), 182 deletions(-) delete mode 100644 src/host/usbh_classdriver.h create mode 100644 src/host/usbh_pvt.h (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 40ebd331d..53e15710e 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -29,7 +29,7 @@ #if (CFG_TUH_ENABLED && CFG_TUH_CDC) #include "host/usbh.h" -#include "host/usbh_classdriver.h" +#include "host/usbh_pvt.h" #include "cdc_host.h" diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 4253170d4..a3551c85a 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -29,7 +29,7 @@ #if (CFG_TUH_ENABLED && CFG_TUH_HID) #include "host/usbh.h" -#include "host/usbh_classdriver.h" +#include "host/usbh_pvt.h" #include "hid_host.h" diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c index 90a58d3d0..da264142c 100644 --- a/src/class/msc/msc_host.c +++ b/src/class/msc/msc_host.c @@ -29,7 +29,7 @@ #if CFG_TUH_ENABLED && CFG_TUH_MSC #include "host/usbh.h" -#include "host/usbh_classdriver.h" +#include "host/usbh_pvt.h" #include "msc_host.h" diff --git a/src/device/usbd.c b/src/device/usbd.c index 156b92ce1..f0d9fba52 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -238,34 +238,25 @@ enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) }; tu_static usbd_class_driver_t const * _app_driver = NULL; tu_static uint8_t _app_driver_count = 0; +#define TOTAL_DRIVER_COUNT (_app_driver_count + BUILTIN_DRIVER_COUNT) + // virtually joins built-in and application drivers together. // Application is positioned first to allow overwriting built-in ones. static inline usbd_class_driver_t const * get_driver(uint8_t drvid) { - // Application drivers - if ( usbd_app_driver_get_cb ) - { - if ( drvid < _app_driver_count ) return &_app_driver[drvid]; - drvid -= _app_driver_count; - } - - // when there is no built-in drivers BUILTIN_DRIVER_COUNT = 0 will cause -Wtype-limits warning -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wtype-limits" -#endif - - // Built-in drivers - if (drvid < BUILTIN_DRIVER_COUNT) return &_usbd_driver[drvid]; + usbd_class_driver_t const * driver = NULL; -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif + if ( drvid < _app_driver_count ) { + // Application drivers + driver = &_app_driver[drvid]; + } else if ( drvid < TOTAL_DRIVER_COUNT && BUILTIN_DRIVER_COUNT > 0 ){ + driver = &_usbd_driver[drvid - _app_driver_count]; + } - return NULL; + return driver; } -#define TOTAL_DRIVER_COUNT (_app_driver_count + BUILTIN_DRIVER_COUNT) + //--------------------------------------------------------------------+ // DCD Event diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h index 940b2858b..16585167f 100644 --- a/src/device/usbd_pvt.h +++ b/src/device/usbd_pvt.h @@ -59,7 +59,7 @@ typedef struct } usbd_class_driver_t; // Invoked when initializing device stack to get additional class drivers. -// Can optionally implemented by application to extend/overwrite class driver support. +// Can be implemented by application to extend/overwrite class driver support. // Note: The drivers array must be accessible at all time when stack is active usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK; diff --git a/src/host/hub.c b/src/host/hub.c index ec30eb96a..32f5e0ac7 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -30,7 +30,7 @@ #include "hcd.h" #include "usbh.h" -#include "usbh_classdriver.h" +#include "usbh_pvt.h" #include "hub.h" // Debug level, TUSB_CFG_DEBUG must be at least this level for debug message diff --git a/src/host/usbh.c b/src/host/usbh.c index af8142be3..739157b56 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -30,7 +30,7 @@ #include "host/hcd.h" #include "tusb.h" -#include "host/usbh_classdriver.h" +#include "host/usbh_pvt.h" #include "hub.h" //--------------------------------------------------------------------+ @@ -183,6 +183,23 @@ static usbh_class_driver_t const usbh_class_drivers[] = enum { USBH_BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) }; enum { CONFIG_NUM = 1 }; // default to use configuration 1 +// Additional class drivers implemented by application +tu_static usbh_class_driver_t const * _app_driver = NULL; +tu_static uint8_t _app_driver_count = 0; + +#define TOTAL_DRIVER_COUNT (_app_driver_count + USBH_BUILTIN_DRIVER_COUNT) + +static inline usbh_class_driver_t const *get_driver(uint8_t drv_id) { + usbh_class_driver_t const *driver = NULL; + + if ( drv_id < _app_driver_count ) { + driver = &_app_driver[drv_id]; + } else if ( drv_id < TOTAL_DRIVER_COUNT && USBH_BUILTIN_DRIVER_COUNT > 0) { + driver = &usbh_class_drivers[drv_id - _app_driver_count]; + } + + return driver; +} //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION @@ -246,21 +263,6 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size); static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); -// Additional class drivers implemented by application -tu_static usbh_class_driver_t const * _app_driver = NULL; -tu_static uint8_t _app_driver_count = 0; -tu_static uint8_t _total_driver_count = USBH_BUILTIN_DRIVER_COUNT; - -static usbh_class_driver_t const * usbh_get_driver(uint8_t drv_id) -{ - usbh_class_driver_t const * driver = NULL; - if ( drv_id < _app_driver_count ) - driver = &_app_driver[drv_id]; - else if ( drv_id < _total_driver_count ) - driver = &usbh_class_drivers[drv_id - _app_driver_count]; - return driver; -} - #if CFG_TUSB_OS == OPT_OS_NONE // TODO rework time-related function later // weak and overridable @@ -354,11 +356,10 @@ bool tuh_init(uint8_t controller_id) { _usbh_mutex = osal_mutex_create(&_usbh_mutexdef); TU_ASSERT(_usbh_mutex); #endif + // Get application driver if available - if ( usbh_app_driver_get_cb ) - { + if ( usbh_app_driver_get_cb ) { _app_driver = usbh_app_driver_get_cb(&_app_driver_count); - _total_driver_count = USBH_BUILTIN_DRIVER_COUNT + _app_driver_count; } // Device @@ -372,9 +373,9 @@ bool tuh_init(uint8_t controller_id) { } // Class drivers - for (uint8_t drv_id = 0; drv_id < _total_driver_count; drv_id++) + for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) { - usbh_class_driver_t const * driver = usbh_get_driver(drv_id); + usbh_class_driver_t const * driver = get_driver(drv_id); if ( driver ) { TU_LOG_USBH("%s init\r\n", driver->name); @@ -508,12 +509,12 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { #endif { uint8_t drv_id = dev->ep2drv[epnum][ep_dir]; - usbh_class_driver_t const * driver = usbh_get_driver(drv_id); + usbh_class_driver_t const * driver = get_driver(drv_id); if ( driver ) { TU_LOG_USBH("%s xfer callback\r\n", driver->name); driver->xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, - event.xfer_complete.len); + event.xfer_complete.len); } else { @@ -1220,12 +1221,10 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub if (dev->rhport == rhport && dev->connected && (hub_addr == 0 || dev->hub_addr == hub_addr) && - (hub_port == 0 || dev->hub_port == hub_port)) - { + (hub_port == 0 || dev->hub_port == hub_port)) { TU_LOG_USBH("Device unplugged address = %u\r\n", daddr); - if (is_hub_addr(daddr)) - { + if (is_hub_addr(daddr)) { TU_LOG(CFG_TUH_LOG_LEVEL, " is a HUB device %u\r\n", daddr); // Submit removed event If the device itself is a hub (un-rolled recursive) @@ -1243,14 +1242,11 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu } // Close class driver - for (uint8_t drv_id = 0; drv_id < _total_driver_count; drv_id++) - { - usbh_class_driver_t const * driver = usbh_get_driver(drv_id); - if ( driver ) - { - driver->close(daddr); - } + for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) { + usbh_class_driver_t const * driver = get_driver(drv_id); + if ( driver ) driver->close(daddr); } + hcd_device_close(rhport, daddr); clear_device(dev); // abort on-going control xfer if any @@ -1679,10 +1675,9 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t)); // Find driver for this interface - uint8_t drv_id = 0; - for (; drv_id < _total_driver_count; drv_id++) + for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) { - usbh_class_driver_t const * driver = usbh_get_driver(drv_id); + usbh_class_driver_t const * driver = get_driver(drv_id); if (driver && driver->open(dev->rhport, dev_addr, desc_itf, drv_len) ) { @@ -1705,12 +1700,11 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur break; // exit driver find loop } - } - - if( drv_id >= _total_driver_count ) - { - TU_LOG(CFG_TUH_LOG_LEVEL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n", - desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol); + if ( drv_id == TOTAL_DRIVER_COUNT - 1 ) + { + TU_LOG(CFG_TUH_LOG_LEVEL, "[%u:%u] Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n", + dev->rhport, dev_addr, desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol); + } } // next Interface or IAD descriptor @@ -1730,9 +1724,9 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) // IAD binding interface such as CDCs should return itf_num + 1 when complete // with usbh_driver_set_config_complete() uint8_t const drv_id = dev->itf2drv[itf_num]; - if (drv_id != TUSB_INDEX_INVALID_8) + usbh_class_driver_t const * driver = get_driver(drv_id); + if (driver) { - usbh_class_driver_t const * driver = usbh_get_driver(drv_id); TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num); driver->set_config(dev_addr, itf_num); break; diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h deleted file mode 100644 index 7443b2d90..000000000 --- a/src/host/usbh_classdriver.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2021, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef _TUSB_USBH_CLASSDRIVER_H_ -#define _TUSB_USBH_CLASSDRIVER_H_ - -#include "osal/osal.h" -#include "common/tusb_fifo.h" -#include "common/tusb_private.h" - -#ifdef __cplusplus - extern "C" { -#endif - -// Level where CFG_TUSB_DEBUG must be at least for USBH is logged -#ifndef CFG_TUH_LOG_LEVEL - #define CFG_TUH_LOG_LEVEL 2 -#endif - -#define TU_LOG_USBH(...) TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__) - -enum { - USBH_EPSIZE_BULK_MAX = (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS) -}; - -//--------------------------------------------------------------------+ -// Class Driver API -//--------------------------------------------------------------------+ - -typedef struct { - #if CFG_TUSB_DEBUG >= 2 - char const* name; - #endif - - void (* const init )(void); - bool (* const open )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); - bool (* const set_config )(uint8_t dev_addr, uint8_t itf_num); - bool (* const xfer_cb )(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); - void (* const close )(uint8_t dev_addr); -} usbh_class_driver_t; - -// Call by class driver to tell USBH that it has complete the enumeration -void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num); - -uint8_t usbh_get_rhport(uint8_t dev_addr); - -uint8_t* usbh_get_enum_buf(void); - -void usbh_int_set(bool enabled); - -//--------------------------------------------------------------------+ -// USBH Endpoint API -//--------------------------------------------------------------------+ - -// Submit a usb transfer with callback support, require CFG_TUH_API_EDPT_XFER -bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes, - tuh_xfer_cb_t complete_cb, uintptr_t user_data); - -TU_ATTR_ALWAYS_INLINE -static inline bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) -{ - return usbh_edpt_xfer_with_callback(dev_addr, ep_addr, buffer, total_bytes, NULL, 0); -} - - -// Claim an endpoint before submitting a transfer. -// If caller does not make any transfer, it must release endpoint for others. -bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr); - -// Release claimed endpoint without submitting a transfer -bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr); - -// Check if endpoint transferring is complete -bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr); - -//--------------------------------------------------------------------+ -// USBH application additional driver API -//--------------------------------------------------------------------+ -// Invoked when initializing host stack to get additional class drivers. -// Can optionally implemented by application to extend/overwrite class driver support. -// Note: The drivers array must be accessible at all time when stack is active -usbh_class_driver_t const* usbh_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK; - -#ifdef __cplusplus - } -#endif - -#endif diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h new file mode 100644 index 000000000..0b58a91bc --- /dev/null +++ b/src/host/usbh_pvt.h @@ -0,0 +1,108 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_USBH_CLASSDRIVER_H_ +#define _TUSB_USBH_CLASSDRIVER_H_ + +#include "osal/osal.h" +#include "common/tusb_fifo.h" +#include "common/tusb_private.h" + +#ifdef __cplusplus + extern "C" { +#endif + +// Level where CFG_TUSB_DEBUG must be at least for USBH is logged +#ifndef CFG_TUH_LOG_LEVEL + #define CFG_TUH_LOG_LEVEL 2 +#endif + +#define TU_LOG_USBH(...) TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__) + +enum { + USBH_EPSIZE_BULK_MAX = (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS) +}; + +//--------------------------------------------------------------------+ +// Class Driver API +//--------------------------------------------------------------------+ + +typedef struct { + #if CFG_TUSB_DEBUG >= 2 + char const* name; + #endif + + void (* const init )(void); + bool (* const open )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); + bool (* const set_config )(uint8_t dev_addr, uint8_t itf_num); + bool (* const xfer_cb )(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); + void (* const close )(uint8_t dev_addr); +} usbh_class_driver_t; + +// Invoked when initializing host stack to get additional class drivers. +// Can be implemented by application to extend/overwrite class driver support. +// Note: The drivers array must be accessible at all time when stack is active +usbh_class_driver_t const* usbh_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK; + +// Call by class driver to tell USBH that it has complete the enumeration +void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num); + +uint8_t usbh_get_rhport(uint8_t dev_addr); + +uint8_t* usbh_get_enum_buf(void); + +void usbh_int_set(bool enabled); + +//--------------------------------------------------------------------+ +// USBH Endpoint API +//--------------------------------------------------------------------+ + +// Submit a usb transfer with callback support, require CFG_TUH_API_EDPT_XFER +bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes, + tuh_xfer_cb_t complete_cb, uintptr_t user_data); + +TU_ATTR_ALWAYS_INLINE +static inline bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) +{ + return usbh_edpt_xfer_with_callback(dev_addr, ep_addr, buffer, total_bytes, NULL, 0); +} + + +// Claim an endpoint before submitting a transfer. +// If caller does not make any transfer, it must release endpoint for others. +bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr); + +// Release claimed endpoint without submitting a transfer +bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr); + +// Check if endpoint transferring is complete +bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr); + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/src/tusb.c b/src/tusb.c index 465b608b0..7b0a669a0 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -36,7 +36,7 @@ #endif #if CFG_TUH_ENABLED -#include "host/usbh_classdriver.h" +#include "host/usbh_pvt.h" #endif //--------------------------------------------------------------------+ -- cgit v1.3.1 From 67a374d932cbe14bf1651bdd6fea82c2e2ecfa10 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 15 Aug 2023 22:57:05 +0700 Subject: more rename --- src/host/usbh.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 739157b56..7cdcbda5e 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -180,21 +180,21 @@ static usbh_class_driver_t const usbh_class_drivers[] = #endif }; -enum { USBH_BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) }; +enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) }; enum { CONFIG_NUM = 1 }; // default to use configuration 1 // Additional class drivers implemented by application tu_static usbh_class_driver_t const * _app_driver = NULL; tu_static uint8_t _app_driver_count = 0; -#define TOTAL_DRIVER_COUNT (_app_driver_count + USBH_BUILTIN_DRIVER_COUNT) +#define TOTAL_DRIVER_COUNT (_app_driver_count + BUILTIN_DRIVER_COUNT) static inline usbh_class_driver_t const *get_driver(uint8_t drv_id) { usbh_class_driver_t const *driver = NULL; if ( drv_id < _app_driver_count ) { driver = &_app_driver[drv_id]; - } else if ( drv_id < TOTAL_DRIVER_COUNT && USBH_BUILTIN_DRIVER_COUNT > 0) { + } else if ( drv_id < TOTAL_DRIVER_COUNT && BUILTIN_DRIVER_COUNT > 0) { driver = &usbh_class_drivers[drv_id - _app_driver_count]; } -- cgit v1.3.1 From b3c7fe1023d14d1e07eb21ca9a61438bff49a788 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 15 Aug 2023 00:09:31 +0700 Subject: clear qhd halted bit if not caused by STALL protocol, allow for next transfer --- src/portable/ehci/ehci.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 79811985c..c5036b5a3 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -579,6 +579,7 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) { if (qtd_overlay->xact_err || qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err) { // Error count = 0 often occurs when device disconnected, or other bus-related error xfer_result = XFER_RESULT_FAILED; + qtd_overlay->halted = false; // clear halted bit if it is not caused by STALL TU_LOG3(" QHD xfer err count: %d\n", qtd_overlay->err_count); // TU_BREAKPOINT(); // TODO skip unplugged device }else { -- cgit v1.3.1 From 0109ffbdcb22a358ecbc1476fbfb4e370e5bb4cc Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 16 Aug 2023 14:31:14 +0700 Subject: fix abort transfer does not release endpoint, also reset state if it is control transfer --- src/host/usbh.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 7cdcbda5e..5423df669 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -738,19 +738,27 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) { usbh_device_t* dev = get_device(daddr); TU_VERIFY(dev); + TU_LOG_USBH("[%u] Aborted transfer on EP %02X\r\n", daddr, ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - // skip if not busy - TU_VERIFY(dev->ep_status[epnum][dir].busy); - - bool const ret = hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr); - if (ret) { - // mark as ready if transfer is aborted + if ( epnum == 0 ) { + // control transfer: only 1 control at a time, check if we are aborting the current one + TU_VERIFY(daddr == _ctrl_xfer.daddr && _ctrl_xfer.stage != CONTROL_STAGE_IDLE); + TU_VERIFY(hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr)); + // reset control transfer state to idle + _set_control_xfer_stage(CONTROL_STAGE_IDLE); + } else { + // non-control skip if not busy + TU_VERIFY(dev->ep_status[epnum][dir].busy); + TU_VERIFY(hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr)); + // mark as ready and release endpoint if transfer is aborted dev->ep_status[epnum][dir].busy = false; + usbh_edpt_release(daddr, ep_addr); } - return ret; + return true; } //--------------------------------------------------------------------+ -- cgit v1.3.1 From f4845e4e6cc2faca4e60cd83959850f27d3f3076 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 16 Aug 2023 14:43:58 +0700 Subject: minor comment --- src/portable/ehci/ehci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index c5036b5a3..c93c33fc0 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -578,8 +578,9 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) { if ( qtd_overlay->halted ) { if (qtd_overlay->xact_err || qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err) { // Error count = 0 often occurs when device disconnected, or other bus-related error + // clear halted bit if not caused by STALL to allow more transfer xfer_result = XFER_RESULT_FAILED; - qtd_overlay->halted = false; // clear halted bit if it is not caused by STALL + qtd_overlay->halted = false; TU_LOG3(" QHD xfer err count: %d\n", qtd_overlay->err_count); // TU_BREAKPOINT(); // TODO skip unplugged device }else { -- cgit v1.3.1 From 9257a0f562a1cb939a902e7c41de5032b0f7de19 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 18 Aug 2023 12:48:12 +0700 Subject: - update nrf52 bsp for cmake - add empty tuh_int_handler/tud_int_handler if corresponidng stack not enabled - add hcd_template.c --- hw/bsp/nrf/boards/adafruit_clue/board.cmake | 5 + hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake | 5 + .../boards/circuitplayground_bluefruit/board.cmake | 5 + .../boards/feather_nrf52840_express/board.cmake | 6 + .../nrf/boards/feather_nrf52840_sense/board.cmake | 5 + hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake | 5 + hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake | 5 + hw/bsp/nrf/boards/pca10056/board.cmake | 3 - hw/bsp/nrf/boards/pca10059/board.cmake | 5 + hw/bsp/nrf/boards/pca10095/board.cmake | 4 - hw/bsp/nrf/boards/pca10100/board.cmake | 5 + hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake | 5 + hw/bsp/nrf/family.cmake | 14 +- src/device/usbd.h | 6 +- src/host/hcd.h | 12 +- src/portable/template/dcd_template.c | 4 +- src/portable/template/hcd_template.c | 162 +++++++++++++++++++++ src/tusb.h | 9 +- 18 files changed, 241 insertions(+), 24 deletions(-) create mode 100644 hw/bsp/nrf/boards/adafruit_clue/board.cmake create mode 100644 hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake create mode 100644 hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake create mode 100644 hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake create mode 100644 hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake create mode 100644 hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake create mode 100644 hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake create mode 100644 hw/bsp/nrf/boards/pca10059/board.cmake create mode 100644 hw/bsp/nrf/boards/pca10100/board.cmake create mode 100644 hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake create mode 100644 src/portable/template/hcd_template.c (limited to 'src') diff --git a/hw/bsp/nrf/boards/adafruit_clue/board.cmake b/hw/bsp/nrf/boards/adafruit_clue/board.cmake new file mode 100644 index 000000000..eb97e5c55 --- /dev/null +++ b/hw/bsp/nrf/boards/adafruit_clue/board.cmake @@ -0,0 +1,5 @@ +set(MCU_VARIANT nrf52840) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake b/hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake new file mode 100644 index 000000000..93647063a --- /dev/null +++ b/hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake @@ -0,0 +1,5 @@ +set(MCU_VARIANT nrf52840) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/arduino_nano33_ble.ld) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake new file mode 100644 index 000000000..eb97e5c55 --- /dev/null +++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake @@ -0,0 +1,5 @@ +set(MCU_VARIANT nrf52840) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake new file mode 100644 index 000000000..0acbecf7a --- /dev/null +++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake @@ -0,0 +1,6 @@ +set(MCU_VARIANT nrf52840) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld) +# set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake new file mode 100644 index 000000000..eb97e5c55 --- /dev/null +++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake @@ -0,0 +1,5 @@ +set(MCU_VARIANT nrf52840) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake new file mode 100644 index 000000000..eb97e5c55 --- /dev/null +++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake @@ -0,0 +1,5 @@ +set(MCU_VARIANT nrf52840) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake new file mode 100644 index 000000000..ffa5932c1 --- /dev/null +++ b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake @@ -0,0 +1,5 @@ +set(MCU_VARIANT nrf52840) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/nrf52840_mdk_dongle.ld) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/nrf/boards/pca10056/board.cmake b/hw/bsp/nrf/boards/pca10056/board.cmake index b4fe39fc0..693d7beed 100644 --- a/hw/bsp/nrf/boards/pca10056/board.cmake +++ b/hw/bsp/nrf/boards/pca10056/board.cmake @@ -2,7 +2,4 @@ set(MCU_VARIANT nrf52840) set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld) function(update_board TARGET) - target_compile_definitions(${TARGET} PUBLIC - NRF52840_XXAA - ) endfunction() diff --git a/hw/bsp/nrf/boards/pca10059/board.cmake b/hw/bsp/nrf/boards/pca10059/board.cmake new file mode 100644 index 000000000..c79eb5964 --- /dev/null +++ b/hw/bsp/nrf/boards/pca10059/board.cmake @@ -0,0 +1,5 @@ +set(MCU_VARIANT nrf52840) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/pca10059.ld) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake index 1e72243c9..ca5399a3a 100644 --- a/hw/bsp/nrf/boards/pca10095/board.cmake +++ b/hw/bsp/nrf/boards/pca10095/board.cmake @@ -2,10 +2,6 @@ set(MCU_VARIANT nrf5340_application) set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf5340_xxaa_application.ld) function(update_board TARGET) - target_compile_definitions(${TARGET} PUBLIC - NRF5340_XXAA - NRF5340_XXAA_APPLICATION - ) target_sources(${TARGET} PRIVATE ${NRFX_DIR}/drivers/src/nrfx_usbreg.c ) diff --git a/hw/bsp/nrf/boards/pca10100/board.cmake b/hw/bsp/nrf/boards/pca10100/board.cmake new file mode 100644 index 000000000..c30026815 --- /dev/null +++ b/hw/bsp/nrf/boards/pca10100/board.cmake @@ -0,0 +1,5 @@ +set(MCU_VARIANT nrf52833) +set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52833_xxaa.ld) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake new file mode 100644 index 000000000..693d7beed --- /dev/null +++ b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake @@ -0,0 +1,5 @@ +set(MCU_VARIANT nrf52840) +set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 2b13249f4..6c24d3658 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -33,13 +33,20 @@ function(add_board_target BOARD_TARGET) add_library(${BOARD_TARGET} STATIC # driver ${NRFX_DIR}/drivers/src/nrfx_power.c + ${NRFX_DIR}/drivers/src/nrfx_spim.c ${NRFX_DIR}/drivers/src/nrfx_uarte.c # mcu ${NRFX_DIR}/mdk/system_${MCU_VARIANT}.c ) - target_compile_definitions(${BOARD_TARGET} PUBLIC - CONFIG_GPIO_AS_PINRESET - ) + target_compile_definitions(${BOARD_TARGET} PUBLIC CONFIG_GPIO_AS_PINRESET) + + if (MCU_VARIANT STREQUAL "nrf52840") + target_compile_definitions(${BOARD_TARGET} PUBLIC NRF52840_XXAA) + elseif (MCU_VARIANT STREQUAL "nrf52833") + target_compile_definitions(${BOARD_TARGET} PUBLIC NRF52833_XXAA) + elseif (MCU_VARIANT STREQUAL "nrf5340_application") + target_compile_definitions(${BOARD_TARGET} PUBLIC NRF5340_XXAA NRF5340_XXAA_APPLICATION) + endif () if (TRACE_ETM STREQUAL "1") # ENABLE_TRACE will cause system_nrf5x.c to set up ETM trace @@ -115,6 +122,7 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c + #${TOP}/src/portable/analog/max3421e/hcd_max3421e.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/src/device/usbd.h b/src/device/usbd.h index b11c1a09d..782f538fd 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -50,8 +50,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr); // Task function should be called in main/rtos loop TU_ATTR_ALWAYS_INLINE static inline -void tud_task (void) -{ +void tud_task (void) { tud_task_ext(UINT32_MAX, false); } @@ -80,8 +79,7 @@ bool tud_suspended(void); // Check if device is ready to transfer TU_ATTR_ALWAYS_INLINE static inline -bool tud_ready(void) -{ +bool tud_ready(void) { return tud_mounted() && !tud_suspended(); } diff --git a/src/host/hcd.h b/src/host/hcd.h index 9bcc1c6df..1b5038ef4 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -198,8 +198,7 @@ extern void hcd_event_handler(hcd_event_t const* event, bool in_isr); // Helper to send device attach event TU_ATTR_ALWAYS_INLINE static inline -void hcd_event_device_attach(uint8_t rhport, bool in_isr) -{ +void hcd_event_device_attach(uint8_t rhport, bool in_isr) { hcd_event_t event; event.rhport = rhport; event.event_id = HCD_EVENT_DEVICE_ATTACH; @@ -211,8 +210,7 @@ void hcd_event_device_attach(uint8_t rhport, bool in_isr) // Helper to send device removal event TU_ATTR_ALWAYS_INLINE static inline -void hcd_event_device_remove(uint8_t rhport, bool in_isr) -{ +void hcd_event_device_remove(uint8_t rhport, bool in_isr) { hcd_event_t event; event.rhport = rhport; event.event_id = HCD_EVENT_DEVICE_REMOVE; @@ -224,10 +222,8 @@ void hcd_event_device_remove(uint8_t rhport, bool in_isr) // Helper to send USB transfer event TU_ATTR_ALWAYS_INLINE static inline -void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr) -{ - hcd_event_t event = - { +void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr) { + hcd_event_t event = { .rhport = 0, // TODO correct rhport .event_id = HCD_EVENT_XFER_COMPLETE, .dev_addr = dev_addr, diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c index 590dd9fcf..12d610bd6 100644 --- a/src/portable/template/dcd_template.c +++ b/src/portable/template/dcd_template.c @@ -26,7 +26,7 @@ #include "tusb_option.h" -#if CFG_TUSB_MCU == OPT_MCU_NONE +#if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_NONE #include "device/dcd.h" @@ -141,4 +141,6 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) (void) ep_addr; } + + #endif diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c new file mode 100644 index 000000000..3e3b91558 --- /dev/null +++ b/src/portable/template/hcd_template.c @@ -0,0 +1,162 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUH_ENABLED && CFG_TUSB_MCU == OPT_MCU_NONE + +#include "host/hcd.h" + +//--------------------------------------------------------------------+ +// Controller API +//--------------------------------------------------------------------+ + +// optional hcd configuration, called by tuh_configure() +bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { + (void) rhport; + (void) cfg_id; + (void) cfg_param; + + return false; +} + +// Initialize controller to host mode +bool hcd_init(uint8_t rhport) { + (void) rhport; + + return false; +} + +// Interrupt Handler +void hcd_int_handler(uint8_t rhport) { + (void) rhport; +} + +// Enable USB interrupt +void hcd_int_enable (uint8_t rhport) { + (void) rhport; +} + +// Disable USB interrupt +void hcd_int_disable(uint8_t rhport) { + (void) rhport; +} + +// Get frame number (1ms) +uint32_t hcd_frame_number(uint8_t rhport) { + (void) rhport; + + return 0; +} + +//--------------------------------------------------------------------+ +// Port API +//--------------------------------------------------------------------+ + +// Get the current connect status of roothub port +bool hcd_port_connect_status(uint8_t rhport) { + (void) rhport; + + return false; +} + +// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete. +// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence. +void hcd_port_reset(uint8_t rhport) { + (void) rhport; +} + +// Complete bus reset sequence, may be required by some controllers +void hcd_port_reset_end(uint8_t rhport) { + (void) rhport; +} + +// Get port link speed +tusb_speed_t hcd_port_speed_get(uint8_t rhport) { + (void) rhport; + + return TUSB_SPEED_FULL; +} + +// HCD closes all opened endpoints belong to this device +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { + (void) rhport; + (void) dev_addr; +} + +//--------------------------------------------------------------------+ +// Endpoints API +//--------------------------------------------------------------------+ + +// Open an endpoint +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { + (void) rhport; + (void) dev_addr; + (void) ep_desc; + + return false; +} + +// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + (void) buffer; + (void) buflen; + + return false; +} + +// Abort a queued transfer. Note: it can only abort transfer that has not been started +// Return true if a queued transfer is aborted, false if there is no transfer to abort +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + + return false; +} + +// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { + (void) rhport; + (void) dev_addr; + (void) setup_packet; + + return false; +} + +// clear stall, data toggle is also reset to DATA0 +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + + return false; +} + +#endif diff --git a/src/tusb.h b/src/tusb.h index 37a521fa8..d6534ca28 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -64,7 +64,10 @@ #if CFG_TUH_VENDOR #include "class/vendor/vendor_host.h" #endif - +#else + #ifndef tuh_int_handler + #define tuh_int_handler(_x) + #endif #endif //------------- DEVICE -------------// @@ -118,6 +121,10 @@ #if CFG_TUD_BTH #include "class/bth/bth_device.h" #endif +#else + #ifndef tud_int_handler + #define tud_int_handler(_x) + #endif #endif -- cgit v1.3.1 From 824e585e2b1f62d1ed03f480439e62e5410636b6 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 18 Aug 2023 14:06:57 +0700 Subject: ground works for hcd max3421e --- .../boards/feather_nrf52840_express/board.cmake | 4 +- hw/bsp/nrf/boards/feather_nrf52840_express/board.h | 7 + hw/bsp/nrf/family.c | 80 ++++-- hw/bsp/nrf/family.cmake | 2 +- hw/bsp/nrf/nrfx_config.h | 5 +- src/portable/analog/max3421e/hcd_max3421e.c | 302 +++++++++++++++++++++ 6 files changed, 369 insertions(+), 31 deletions(-) create mode 100644 src/portable/analog/max3421e/hcd_max3421e.c (limited to 'src') diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake index 0acbecf7a..78ed98225 100644 --- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake +++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake @@ -1,6 +1,6 @@ set(MCU_VARIANT nrf52840) -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld) -# set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld) +#set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld) +set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld) function(update_board TARGET) endfunction() diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h index 8e6ce3230..e19f88a3c 100644 --- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h +++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h @@ -45,6 +45,13 @@ #define UART_RX_PIN 24 #define UART_TX_PIN 25 +// SPI for USB host shield +#define SPI_SCK_PIN 14 +#define SPI_MOSI_PIN 13 +#define SPI_MISO_PIN 15 +#define SPI_CS_PIN 27 +#define MAX3241E_INT_PIN 26 + #ifdef __cplusplus } #endif diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index 9ca666e36..b6ed15122 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -40,6 +40,7 @@ #include "hal/nrf_gpio.h" #include "drivers/include/nrfx_power.h" #include "drivers/include/nrfx_uarte.h" +#include "drivers/include/nrfx_spim.h" #ifdef SOFTDEVICE_PRESENT #include "nrf_sdm.h" @@ -54,8 +55,7 @@ //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void USBD_IRQHandler(void) -{ +void USBD_IRQHandler(void) { tud_int_handler(0); } @@ -81,6 +81,7 @@ enum { #endif static nrfx_uarte_t _uart_id = NRFX_UARTE_INSTANCE(0); +static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0); // tinyusb function that handles power event (detected, ready, removed) // We must call it within SD's SOC event handler, or set it as power event handler if SD is not enabled. @@ -88,13 +89,11 @@ extern void tusb_hal_nrf_power_event(uint32_t event); // nrf power callback, could be unused if SD is enabled or usb is disabled (board_test example) -TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) -{ +TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) { tusb_hal_nrf_power_event((uint32_t) event); } -void board_init(void) -{ +void board_init(void) { // stop LF clock just in case we jump from application without reset NRF_CLOCK->TASKS_LFCLKSTOP = 1UL; @@ -113,8 +112,7 @@ void board_init(void) SysTick_Config(SystemCoreClock/1000); // UART - nrfx_uarte_config_t uart_cfg = - { + nrfx_uarte_config_t uart_cfg = { .pseltxd = UART_TX_PIN, .pselrxd = UART_RX_PIN, .pselcts = NRF_UARTE_PSEL_DISCONNECTED, @@ -175,45 +173,78 @@ void board_init(void) if ( usb_reg & VBUSDETECT_Msk ) tusb_hal_nrf_power_event(USB_EVT_DETECTED); if ( usb_reg & OUTPUTRDY_Msk ) tusb_hal_nrf_power_event(USB_EVT_READY); #endif + + (void) _spi; +#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E + // USB host using max3421e usb controller via SPI + nrfx_spim_config_t cfg = { + .sck_pin = SPI_SCK_PIN, + .mosi_pin = SPI_MOSI_PIN, + .miso_pin = SPI_MISO_PIN, + .ss_pin = SPI_CS_PIN, + .ss_active_high = false, + .irq_priority = 3, + .orc = 0xFF, + // default setting 4 Mhz, Mode 0, MSB first + .frequency = NRF_SPIM_FREQ_4M, + .mode = NRF_SPIM_MODE_0, + .bit_order = NRF_SPIM_BIT_ORDER_MSB_FIRST, + }; + + // no handler --> blocking + nrfx_spim_init(&_spi, &cfg, NULL, NULL); +#endif + } //--------------------------------------------------------------------+ // Board porting API //--------------------------------------------------------------------+ -void board_led_write(bool state) -{ - nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); +void board_led_write(bool state) { + nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); } -uint32_t board_button_read(void) -{ +uint32_t board_button_read(void) { return BUTTON_STATE_ACTIVE == nrf_gpio_pin_read(BUTTON_PIN); } -int board_uart_read(uint8_t* buf, int len) -{ - (void) buf; (void) len; +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; return 0; // return NRFX_SUCCESS == nrfx_uart_rx(&_uart_id, buf, (size_t) len) ? len : 0; } -int board_uart_write(void const * buf, int len) -{ - return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len)) ? len : 0; +int board_uart_write(void const *buf, int len) { + return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const *) buf, (size_t) len)) ? len : 0; } #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; -void SysTick_Handler (void) -{ + +void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) -{ +uint32_t board_millis(void) { return system_ticks; } + +#endif + +#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E +// API: SPI transfer with MAX3421E, must be implemented by application +bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) { + (void) rhport; + nrfx_spim_xfer_desc_t xfer = { + .p_tx_buffer = tx_buf, + .tx_length = tx_len, + .p_rx_buffer = rx_buf, + .rx_length = rx_len, + }; + return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS; +} #endif #ifdef SOFTDEVICE_PRESENT @@ -251,8 +282,7 @@ void SD_EVT_IRQHandler(void) } } -void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) -{ +void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) { (void) id; (void) pc; (void) info; diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 6c24d3658..527251e71 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -122,7 +122,7 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c - #${TOP}/src/portable/analog/max3421e/hcd_max3421e.c + ${TOP}/src/portable/analog/max3421e/hcd_max3421e.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/nrf/nrfx_config.h b/hw/bsp/nrf/nrfx_config.h index 696a3fb04..d0f718c6c 100644 --- a/hw/bsp/nrf/nrfx_config.h +++ b/hw/bsp/nrf/nrfx_config.h @@ -9,9 +9,8 @@ #define NRFX_UARTE_ENABLED 1 #define NRFX_UARTE0_ENABLED 1 -#define NRFX_UARTE1_ENABLED 0 -#define NRFX_UARTE2_ENABLED 0 -#define NRFX_UARTE3_ENABLED 0 +#define NRFX_SPIM_ENABLED 1 +#define NRFX_SPIM0_ENABLED 1 #define NRFX_PRS_ENABLED 0 #define NRFX_USBREG_ENABLED 1 diff --git a/src/portable/analog/max3421e/hcd_max3421e.c b/src/portable/analog/max3421e/hcd_max3421e.c new file mode 100644 index 000000000..7b9d73e4e --- /dev/null +++ b/src/portable/analog/max3421e/hcd_max3421e.c @@ -0,0 +1,302 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E + +#include "host/hcd.h" + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +// Command format is +// Reg [7:3] | 0 [2] | Dir [1] | Ack [0] + +enum { + CMDBYTE_WRITE = 0x02, +}; + +enum { + RCVVFIFO_ADDR = 1u << 3, // 0x08 + SNDFIFO_ADDR = 2u << 3, // 0x10 + SUDFIFO_ADDR = 4u << 3, // 0x20 + RCVBC_ADDR = 6u << 3, // 0x30 + SNDBC_ADDR = 7u << 3, // 0x38 + USBIRQ_ADDR = 13u << 3, // 0x68 + USBIEN_ADDR = 14u << 3, // 0x70 + USBCTL_ADDR = 15u << 3, // 0x78 + CPUCTL_ADDR = 16u << 3, // 0x80 + PINCTL_ADDR = 17u << 3, // 0x88 + REVISION_ADDR = 18u << 3, // 0x90 + HIRQ_ADDR = 25u << 3, // 0xC8 + HIEN_ADDR = 26u << 3, // 0xD0 + MODE_ADDR = 27u << 3, // 0xD8 + PERADDR_ADDR = 28u << 3, // 0xE0 + HCTL_ADDR = 29u << 3, // 0xE8 + HXFR_ADDR = 30u << 3, // 0xF0 + HRSL_ADDR = 31u << 3, // 0xF8 +}; + +enum { + USBIRQ_OSCOK_IRQ = 1u << 0, + USBIRQ_NOVBUS_IRQ = 1u << 5, + USBIRQ_VBUS_IRQ = 1u << 6, +}; + +enum { + USBCTL_PWRDOWN = 1u << 4, + USBCTL_CHIPRES = 1u << 5, +}; + +enum { + CPUCTL_IE = 1u << 0, + CPUCTL_PULSEWID0 = 1u << 6, + CPUCTL_PULSEWID1 = 1u << 7, +}; + +enum { + PINCTL_GPXA = 1u << 0, + PINCTL_GPXB = 1u << 1, + PINCTL_POSINT = 1u << 2, + PINCTL_INTLEVEL = 1u << 3, + PINCTL_FDUPSPI = 1u << 4, +}; + +enum { + HIRQ_BUSEVENT_IRQ = 1u << 0, + HIRQ_RWU_IRQ = 1u << 1, + HIRQ_RCVDAV_IRQ = 1u << 2, + HIRQ_SNDBAV_IRQ = 1u << 3, + HIRQ_SUSDN_IRQ = 1u << 4, + HIRQ_CONDET_IRQ = 1u << 5, + HIRQ_FRAME_IRQ = 1u << 6, + HIRQ_HXFRDN_IRQ = 1u << 7, +}; + +enum { + MODE_HOST = 1u << 0, + MODE_LOWSPEED = 1u << 1, + MODE_HUBPRE = 1u << 2, + MODE_SOFKAENAB = 1u << 3, + MODE_SEPIRQ = 1u << 4, + MODE_DELAYISO = 1u << 5, + MODE_DMPULLDN = 1u << 6, + MODE_DPPULLDN = 1u << 7, +}; + +enum { + HCTL_BUSRST = 1u << 1, + HCTL_FRMRST = 1u << 2, + HCTL_SAMPLEBUS = 1u << 3, + HCTL_SIGRSM = 1u << 4, + HCTL_RCVTOG0 = 1u << 5, + HCTL_RCVTOG1 = 1u << 6, + HCTL_SNDTOG0 = 1u << 7, + HCTL_SNDTOG1 = 1u << 8, +}; + +enum { + HXFR_EPNUM_MASK = 0x0f, + HXFR_SETUP = 1u << 4, + HXFR_OUT_NIN = 1u << 5, + HXFR_ISO = 1u << 6, + HXFR_HS = 1u << 7, +}; + +enum { + HRSL_RESULT_MASK = 0x0f, + HRSL_RCVTOGRD = 1u << 4, + HRSL_SNDTOGRD = 1u << 5, + HRSL_KSTATUS = 1u << 6, + HRSL_JSTATUS = 1u << 7, +}; + +// API: SPI transfer with MAX3421E, must be implemented by application +bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len); + +// return HIRQ register since we are in full-duplex mode +static uint8_t reg_write(uint8_t reg, uint8_t data) { + uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data}; + uint8_t rx_buf[2] = {0, 0}; + tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2); + return rx_buf[0]; +} + +static uint8_t reg_read(uint8_t reg) { + uint8_t tx_buf[2] = {reg, 0}; + uint8_t rx_buf[2] = {0, 0}; + return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2) ? rx_buf[1] : 0; +} + + +//--------------------------------------------------------------------+ +// Controller API +//--------------------------------------------------------------------+ + +// optional hcd configuration, called by tuh_configure() +bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { + (void) rhport; + (void) cfg_id; + (void) cfg_param; + + return false; +} + +// Initialize controller to host mode +bool hcd_init(uint8_t rhport) { + (void) rhport; + + // full duplex, interrupt level (should be configurable) + reg_write(PINCTL_ADDR, PINCTL_FDUPSPI | PINCTL_INTLEVEL); + + // reset + reg_write(USBCTL_ADDR, USBCTL_CHIPRES); + reg_write(USBCTL_ADDR, 0); + while( !(reg_read(USBIRQ_ADDR) & USBIRQ_OSCOK_IRQ) ) { + // wait for oscillator to stabilize + } + + // Mode: Host and DP/DM pull down + reg_write(MODE_ADDR, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST); + + // Connection detection + reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ /*| HIRQ_FRAME_IRQ */); + + return false; +} + +// Interrupt Handler +void hcd_int_handler(uint8_t rhport) { + (void) rhport; +} + +// Enable USB interrupt +void hcd_int_enable (uint8_t rhport) { + (void) rhport; +} + +// Disable USB interrupt +void hcd_int_disable(uint8_t rhport) { + (void) rhport; +} + +// Get frame number (1ms) +uint32_t hcd_frame_number(uint8_t rhport) { + (void) rhport; + + return 0; +} + +//--------------------------------------------------------------------+ +// Port API +//--------------------------------------------------------------------+ + +// Get the current connect status of roothub port +bool hcd_port_connect_status(uint8_t rhport) { + (void) rhport; + + return false; +} + +// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete. +// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence. +void hcd_port_reset(uint8_t rhport) { + (void) rhport; +} + +// Complete bus reset sequence, may be required by some controllers +void hcd_port_reset_end(uint8_t rhport) { + (void) rhport; +} + +// Get port link speed +tusb_speed_t hcd_port_speed_get(uint8_t rhport) { + (void) rhport; + + return TUSB_SPEED_FULL; +} + +// HCD closes all opened endpoints belong to this device +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { + (void) rhport; + (void) dev_addr; +} + +//--------------------------------------------------------------------+ +// Endpoints API +//--------------------------------------------------------------------+ + +// Open an endpoint +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { + (void) rhport; + (void) dev_addr; + (void) ep_desc; + + return false; +} + +// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + (void) buffer; + (void) buflen; + + return false; +} + +// Abort a queued transfer. Note: it can only abort transfer that has not been started +// Return true if a queued transfer is aborted, false if there is no transfer to abort +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + + return false; +} + +// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { + (void) rhport; + (void) dev_addr; + (void) setup_packet; + + return false; +} + +// clear stall, data toggle is also reset to DATA0 +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + + return false; +} + +#endif -- cgit v1.3.1 From cacc96b25dc04865389357467b7a6d92d040ef36 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 18 Aug 2023 17:39:10 +0700 Subject: adding connection event handling, add nrf gpio interrupt for max2341e interrupt pin --- hw/bsp/nrf/boards/feather_nrf52840_express/board.h | 2 +- hw/bsp/nrf/family.c | 55 +++++++++++----- hw/bsp/nrf/family.cmake | 2 + hw/bsp/nrf/nrfx_config.h | 2 +- hw/bsp/nrf/nrfx_glue.h | 69 ++++++++++++++++++++ src/portable/analog/max3421e/hcd_max3421e.c | 76 +++++++++++++++++++++- 6 files changed, 184 insertions(+), 22 deletions(-) (limited to 'src') diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h index e19f88a3c..7f042142e 100644 --- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h +++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h @@ -50,7 +50,7 @@ #define SPI_MOSI_PIN 13 #define SPI_MISO_PIN 15 #define SPI_CS_PIN 27 -#define MAX3241E_INT_PIN 26 +#define MAX3241E_INTR_PIN 26 #ifdef __cplusplus } diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index b6ed15122..e58ee845b 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -38,6 +38,7 @@ #include "nrfx.h" #include "hal/nrf_gpio.h" +#include "drivers/include/nrfx_gpiote.h" #include "drivers/include/nrfx_power.h" #include "drivers/include/nrfx_uarte.h" #include "drivers/include/nrfx_spim.h" @@ -81,18 +82,45 @@ enum { #endif static nrfx_uarte_t _uart_id = NRFX_UARTE_INSTANCE(0); -static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0); // tinyusb function that handles power event (detected, ready, removed) // We must call it within SD's SOC event handler, or set it as power event handler if SD is not enabled. extern void tusb_hal_nrf_power_event(uint32_t event); - // nrf power callback, could be unused if SD is enabled or usb is disabled (board_test example) TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) { tusb_hal_nrf_power_event((uint32_t) event); } +//------------- Host using MAX2341E -------------// +#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E +static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0); + +void max2342e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { + if ( !(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO) ) return; + + tuh_int_handler(1); +} + +// API: SPI transfer with MAX3421E, must be implemented by application +bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) { + (void) rhport; + nrfx_spim_xfer_desc_t xfer = { + .p_tx_buffer = tx_buf, + .tx_length = tx_len, + .p_rx_buffer = rx_buf, + .rx_length = rx_len, + }; + return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS; +} + +#endif + + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + void board_init(void) { // stop LF clock just in case we jump from application without reset NRF_CLOCK->TASKS_LFCLKSTOP = 1UL; @@ -174,7 +202,6 @@ void board_init(void) { if ( usb_reg & OUTPUTRDY_Msk ) tusb_hal_nrf_power_event(USB_EVT_READY); #endif - (void) _spi; #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E // USB host using max3421e usb controller via SPI nrfx_spim_config_t cfg = { @@ -193,6 +220,14 @@ void board_init(void) { // no handler --> blocking nrfx_spim_init(&_spi, &cfg, NULL, NULL); + + // max3421e interrupt pin + nrfx_gpiote_init(1); + nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true); + in_config.pull = NRF_GPIO_PIN_PULLUP; + + nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max2342e_int_handler); + nrfx_gpiote_in_event_enable(MAX3241E_INTR_PIN, true); #endif } @@ -233,20 +268,6 @@ uint32_t board_millis(void) { #endif -#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E -// API: SPI transfer with MAX3421E, must be implemented by application -bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) { - (void) rhport; - nrfx_spim_xfer_desc_t xfer = { - .p_tx_buffer = tx_buf, - .tx_length = tx_len, - .p_rx_buffer = rx_buf, - .rx_length = rx_len, - }; - return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS; -} -#endif - #ifdef SOFTDEVICE_PRESENT // process SOC event from SD uint32_t proc_soc(void) diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 527251e71..8bf7bcb52 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -32,6 +32,8 @@ function(add_board_target BOARD_TARGET) if (NOT TARGET ${BOARD_TARGET}) add_library(${BOARD_TARGET} STATIC # driver + ${NRFX_DIR}/helpers/nrfx_flag32_allocator.c + ${NRFX_DIR}/drivers/src/nrfx_gpiote.c ${NRFX_DIR}/drivers/src/nrfx_power.c ${NRFX_DIR}/drivers/src/nrfx_spim.c ${NRFX_DIR}/drivers/src/nrfx_uarte.c diff --git a/hw/bsp/nrf/nrfx_config.h b/hw/bsp/nrf/nrfx_config.h index d0f718c6c..e3d0ea91b 100644 --- a/hw/bsp/nrf/nrfx_config.h +++ b/hw/bsp/nrf/nrfx_config.h @@ -5,6 +5,7 @@ #define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7 #define NRFX_CLOCK_ENABLED 0 +#define NRFX_GPIOTE_ENABLED 1 #define NRFX_UARTE_ENABLED 1 #define NRFX_UARTE0_ENABLED 1 @@ -41,5 +42,4 @@ #error "Unknown device." #endif - #endif // NRFX_CONFIG_H__ diff --git a/hw/bsp/nrf/nrfx_glue.h b/hw/bsp/nrf/nrfx_glue.h index cdf49b4ab..ef756c670 100644 --- a/hw/bsp/nrf/nrfx_glue.h +++ b/hw/bsp/nrf/nrfx_glue.h @@ -220,6 +220,75 @@ static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number) /** @} */ +//------------------------------------------------------------------------------ + +#include + +/** + * @brief Atomic 32 bit unsigned type. + */ +#define nrfx_atomic_t nrfx_atomic_u32_t + +/** + * @brief Stores value to an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value to store. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_STORE(p_data, value) nrfx_atomic_u32_fetch_store(p_data, value) + +/** + * @brief Performs logical OR operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of OR operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_OR(p_data, value) nrfx_atomic_u32_fetch_or(p_data, value) + +/** + * @brief Performs logical AND operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of AND operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_AND(p_data, value) nrfx_atomic_u32_fetch_and(p_data, value) + +/** + * @brief Performs logical XOR operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of XOR operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_XOR(p_data, value) nrfx_atomic_u32_fetch_xor(p_data, value) + +/** + * @brief Performs logical ADD operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of ADD operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_ADD(p_data, value) nrfx_atomic_u32_fetch_add(p_data, value) + +/** + * @brief Performs logical SUB operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of SUB operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_SUB(p_data, value) nrfx_atomic_u32_fetch_sub(p_data, value) + #ifdef __cplusplus } #endif diff --git a/src/portable/analog/max3421e/hcd_max3421e.c b/src/portable/analog/max3421e/hcd_max3421e.c index 7b9d73e4e..a89581b9c 100644 --- a/src/portable/analog/max3421e/hcd_max3421e.c +++ b/src/portable/analog/max3421e/hcd_max3421e.c @@ -136,6 +136,20 @@ enum { HRSL_JSTATUS = 1u << 7, }; +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +//typedef struct { +// uint8_t mode +//} max2341e_data_t; +// +//max2341e_data_t max2341e_data; + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + // API: SPI transfer with MAX3421E, must be implemented by application bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len); @@ -144,6 +158,7 @@ static uint8_t reg_write(uint8_t reg, uint8_t data) { uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data}; uint8_t rx_buf[2] = {0, 0}; tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2); + TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]); return rx_buf[0]; } @@ -167,6 +182,48 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { return false; } +tusb_speed_t handle_connect_irq(uint8_t rhport) { + (void) rhport; + + uint8_t const hrsl = reg_read(HRSL_ADDR); + uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS); + + tusb_speed_t speed; + uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST; + + switch(jk) { + case 0x00: + // SEO is disconnected + speed = TUSB_SPEED_INVALID; + break; + + case (HRSL_JSTATUS | HRSL_KSTATUS): + // SE1 is illegal + speed = TUSB_SPEED_INVALID; + break; + + default: { + // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State) + uint8_t const mode = reg_read(MODE_ADDR); + uint8_t const ls_bit = mode & MODE_LOWSPEED; + + if ( (ls_bit && (jk == HRSL_JSTATUS)) || (!ls_bit && (jk == HRSL_KSTATUS)) ) { + speed = TUSB_SPEED_LOW; + new_mode |= MODE_LOWSPEED; + } else { + speed = TUSB_SPEED_FULL; + } + + new_mode |= MODE_SOFKAENAB; // enable SOF since there is new device + + break; + } + } + + reg_write(MODE_ADDR, new_mode); + return speed; +} + // Initialize controller to host mode bool hcd_init(uint8_t rhport) { (void) rhport; @@ -184,15 +241,28 @@ bool hcd_init(uint8_t rhport) { // Mode: Host and DP/DM pull down reg_write(MODE_ADDR, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST); - // Connection detection - reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ /*| HIRQ_FRAME_IRQ */); + // Enable Connection IRQ + reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ); - return false; + // Note: if device is already connected, CONDET IRQ may not be triggered. We need to detect it by sampling bus signal + reg_write(HCTL_ADDR, HCTL_SAMPLEBUS); + while( !(reg_read(HCTL_ADDR) & HCTL_SAMPLEBUS) ) {} + + handle_connect_irq(rhport); + reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ); + + // Enable Interrupt pin + reg_write(CPUCTL_ADDR, CPUCTL_IE); + + return true; } // Interrupt Handler void hcd_int_handler(uint8_t rhport) { (void) rhport; + + uint8_t hirq = reg_read(HIRQ_ADDR); + TU_LOG3_INT(hirq); } // Enable USB interrupt -- cgit v1.3.1 From b4134394166c1f77463b5cb62f28cff465fde174 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 22 Aug 2023 19:57:59 +0700 Subject: able to detect new device and start enumerating --- src/portable/analog/max3421e/hcd_max3421e.c | 70 +++++++++++++++++++++-------- 1 file changed, 51 insertions(+), 19 deletions(-) (limited to 'src') diff --git a/src/portable/analog/max3421e/hcd_max3421e.c b/src/portable/analog/max3421e/hcd_max3421e.c index a89581b9c..870c616a9 100644 --- a/src/portable/analog/max3421e/hcd_max3421e.c +++ b/src/portable/analog/max3421e/hcd_max3421e.c @@ -140,11 +140,13 @@ enum { // //--------------------------------------------------------------------+ -//typedef struct { -// uint8_t mode -//} max2341e_data_t; -// -//max2341e_data_t max2341e_data; +typedef struct { + uint8_t mode; + + volatile uint16_t frame_count; +} max2341e_data_t; + +static max2341e_data_t _hcd_data; //--------------------------------------------------------------------+ // @@ -168,6 +170,11 @@ static uint8_t reg_read(uint8_t reg) { return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2) ? rx_buf[1] : 0; } +static inline uint8_t mode_write(uint8_t data) { + _hcd_data.mode = data; + return reg_write(MODE_ADDR, data); +} + //--------------------------------------------------------------------+ // Controller API @@ -220,7 +227,8 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) { } } - reg_write(MODE_ADDR, new_mode); + mode_write(new_mode); + TU_LOG2_INT(speed); return speed; } @@ -228,6 +236,8 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) { bool hcd_init(uint8_t rhport) { (void) rhport; + tu_memclr(&_hcd_data, sizeof(_hcd_data)); + // full duplex, interrupt level (should be configurable) reg_write(PINCTL_ADDR, PINCTL_FDUPSPI | PINCTL_INTLEVEL); @@ -239,17 +249,21 @@ bool hcd_init(uint8_t rhport) { } // Mode: Host and DP/DM pull down - reg_write(MODE_ADDR, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST); + mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST); // Enable Connection IRQ - reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ); + reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ); - // Note: if device is already connected, CONDET IRQ may not be triggered. We need to detect it by sampling bus signal + #if 0 + // Note: if device is already connected, CONDET IRQ may not be triggered. + // We need to detect it by sampling bus signal. FIXME not working reg_write(HCTL_ADDR, HCTL_SAMPLEBUS); - while( !(reg_read(HCTL_ADDR) & HCTL_SAMPLEBUS) ) {} + while ( reg_read(HCTL_ADDR) & HCTL_SAMPLEBUS ) {} - handle_connect_irq(rhport); - reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ); + if ( TUSB_SPEED_INVALID != handle_connect_irq(rhport) ) { + reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ); // clear connect irq + } + #endif // Enable Interrupt pin reg_write(CPUCTL_ADDR, CPUCTL_IE); @@ -262,7 +276,26 @@ void hcd_int_handler(uint8_t rhport) { (void) rhport; uint8_t hirq = reg_read(HIRQ_ADDR); - TU_LOG3_INT(hirq); + TU_LOG3_HEX(hirq); + + if (hirq & HIRQ_CONDET_IRQ) { + tusb_speed_t speed = handle_connect_irq(rhport); + + if (speed == TUSB_SPEED_INVALID) { + hcd_event_device_remove(rhport, true); + }else { + hcd_event_device_attach(rhport, true); + } + } + + if (hirq & HIRQ_FRAME_IRQ) { + _hcd_data.frame_count++; + } + + // clear all interrupt + if ( hirq ) { + reg_write(HIRQ_ADDR, hirq); + } } // Enable USB interrupt @@ -278,8 +311,7 @@ void hcd_int_disable(uint8_t rhport) { // Get frame number (1ms) uint32_t hcd_frame_number(uint8_t rhport) { (void) rhport; - - return 0; + return (uint32_t ) _hcd_data.frame_count; } //--------------------------------------------------------------------+ @@ -289,26 +321,26 @@ uint32_t hcd_frame_number(uint8_t rhport) { // Get the current connect status of roothub port bool hcd_port_connect_status(uint8_t rhport) { (void) rhport; - - return false; + return (_hcd_data.mode & MODE_SOFKAENAB) ? true : false; } // Reset USB bus on the port. Return immediately, bus reset sequence may not be complete. // Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence. void hcd_port_reset(uint8_t rhport) { (void) rhport; + reg_write(HCTL_ADDR, HCTL_BUSRST); } // Complete bus reset sequence, may be required by some controllers void hcd_port_reset_end(uint8_t rhport) { (void) rhport; + reg_write(HCTL_ADDR, 0); } // Get port link speed tusb_speed_t hcd_port_speed_get(uint8_t rhport) { (void) rhport; - - return TUSB_SPEED_FULL; + return (_hcd_data.mode & MODE_LOWSPEED) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL; } // HCD closes all opened endpoints belong to this device -- cgit v1.3.1 From 274578ff46c31b231b3553dc9a20895646313130 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 22 Aug 2023 23:17:12 +0700 Subject: able to send setup packet --- hw/bsp/nrf/boards/feather_nrf52840_express/board.h | 8 +- hw/bsp/nrf/family.c | 36 ++++- src/host/hcd.h | 2 +- src/host/usbh.c | 32 ++-- src/portable/analog/max3421e/hcd_max3421e.c | 173 ++++++++++++++++----- 5 files changed, 179 insertions(+), 72 deletions(-) (limited to 'src') diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h index 7f042142e..e6e7590ac 100644 --- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h +++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h @@ -46,10 +46,10 @@ #define UART_TX_PIN 25 // SPI for USB host shield -#define SPI_SCK_PIN 14 -#define SPI_MOSI_PIN 13 -#define SPI_MISO_PIN 15 -#define SPI_CS_PIN 27 +#define MAX3421E_SCK_PIN 14 +#define MAX3421E_MOSI_PIN 13 +#define MAX3421E_MISO_PIN 15 +#define MAX3421E_CS_PIN 27 #define MAX3241E_INTR_PIN 26 #ifdef __cplusplus diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index e58ee845b..862f67bc7 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -96,22 +96,38 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) { #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0); -void max2342e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { +void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { if ( !(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO) ) return; tuh_int_handler(1); } +static inline void max3421e_cs_assert(bool active) { + nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1); +} + +//--------------------------------------------------------------------+ // API: SPI transfer with MAX3421E, must be implemented by application -bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) { +//--------------------------------------------------------------------+ + +bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, + uint8_t * rx_buf, size_t rx_len, bool keep_cs) { (void) rhport; + + max3421e_cs_assert(true); + nrfx_spim_xfer_desc_t xfer = { .p_tx_buffer = tx_buf, .tx_length = tx_len, .p_rx_buffer = rx_buf, .rx_length = rx_len, }; - return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS; + + bool ret = (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS); + + if ( !keep_cs ) max3421e_cs_assert(false); + + return ret; } #endif @@ -203,12 +219,16 @@ void board_init(void) { #endif #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E + // manually manage CS + nrf_gpio_cfg_output(MAX3421E_CS_PIN); + max3421e_cs_assert(false); + // USB host using max3421e usb controller via SPI nrfx_spim_config_t cfg = { - .sck_pin = SPI_SCK_PIN, - .mosi_pin = SPI_MOSI_PIN, - .miso_pin = SPI_MISO_PIN, - .ss_pin = SPI_CS_PIN, + .sck_pin = MAX3421E_SCK_PIN, + .mosi_pin = MAX3421E_MOSI_PIN, + .miso_pin = MAX3421E_MISO_PIN, + .ss_pin = NRFX_SPIM_PIN_NOT_USED, .ss_active_high = false, .irq_priority = 3, .orc = 0xFF, @@ -226,7 +246,7 @@ void board_init(void) { nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true); in_config.pull = NRF_GPIO_PIN_PULLUP; - nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max2342e_int_handler); + nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max3421e_int_handler); nrfx_gpiote_in_event_enable(MAX3241E_INTR_PIN, true); #endif diff --git a/src/host/hcd.h b/src/host/hcd.h index 1b5038ef4..079877b79 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -177,7 +177,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr); // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked -bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]); +bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]); // clear stall, data toggle is also reset to DATA0 bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr); diff --git a/src/host/usbh.c b/src/host/usbh.c index 5423df669..7a09f5b6e 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -552,8 +552,7 @@ static void _control_blocking_complete_cb(tuh_xfer_t* xfer) } // TODO timeout_ms is not supported yet -bool tuh_control_xfer (tuh_xfer_t* xfer) -{ +bool tuh_control_xfer (tuh_xfer_t* xfer) { // EP0 with setup packet TU_VERIFY(xfer->ep_addr == 0 && xfer->setup); @@ -565,8 +564,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); bool const is_idle = (_ctrl_xfer.stage == CONTROL_STAGE_IDLE); - if (is_idle) - { + if (is_idle) { _ctrl_xfer.stage = CONTROL_STAGE_SETUP; _ctrl_xfer.daddr = daddr; _ctrl_xfer.actual_len = 0; @@ -588,11 +586,9 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) TU_LOG_PTR(CFG_TUH_LOG_LEVEL, xfer->setup); TU_LOG_USBH("\r\n"); - if (xfer->complete_cb) - { + if (xfer->complete_cb) { TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) ); - }else - { + }else { // blocking if complete callback is not provided // change callback to internal blocking, and result as user argument volatile xfer_result_t result = XFER_RESULT_INVALID; @@ -656,15 +652,13 @@ static void _xfer_complete(uint8_t daddr, xfer_result_t result) } } -static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) -{ +static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { (void) ep_addr; const uint8_t rhport = usbh_get_rhport(dev_addr); tusb_control_request_t const * request = &_ctrl_xfer.request; - if (XFER_RESULT_SUCCESS != result) - { + if (XFER_RESULT_SUCCESS != result) { TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes); #if CFG_TUSB_DEBUG == 1 TU_LOG1_PTR(request); @@ -673,13 +667,10 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result // terminate transfer if any stage failed _xfer_complete(dev_addr, result); - }else - { - switch(_ctrl_xfer.stage) - { + }else { + switch(_ctrl_xfer.stage) { case CONTROL_STAGE_SETUP: - if (request->wLength) - { + if (request->wLength) { // DATA stage: initial data toggle is always 1 _set_control_xfer_stage(CONTROL_STAGE_DATA); TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength) ); @@ -688,8 +679,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result TU_ATTR_FALLTHROUGH; case CONTROL_STAGE_DATA: - if (request->wLength) - { + if (request->wLength) { TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, dev_addr); TU_LOG_MEM(CFG_TUH_LOG_LEVEL, _ctrl_xfer.buffer, xferred_bytes, 2); } @@ -1538,9 +1528,7 @@ static bool enum_new_device(hcd_event_t* event) xfer.result = XFER_RESULT_SUCCESS; xfer.user_data = ENUM_ADDR0_DEVICE_DESC; - process_enumeration(&xfer); - } #if CFG_TUH_HUB else diff --git a/src/portable/analog/max3421e/hcd_max3421e.c b/src/portable/analog/max3421e/hcd_max3421e.c index 870c616a9..c9596f695 100644 --- a/src/portable/analog/max3421e/hcd_max3421e.c +++ b/src/portable/analog/max3421e/hcd_max3421e.c @@ -136,30 +136,64 @@ enum { HRSL_JSTATUS = 1u << 7, }; +enum { + HRSL_SUCCESS = 0, + HRSL_BUSY, + HRSL_BAD_REQ, + HRSL_UNDEF, + HRSL_NAK, + HRSL_STALL, + HRSL_TOG_ERR, + HRSL_WRONG_PID, + HRSL_BAD_BYTECOUNT, + HRSL_PID_ERR, + HRSL_PKT_ERR, + HRSL_CRC_ERR, + HRSL_K_ERR, + HRSL_J_ERR, + HRSL_TIMEOUT, + HRSL_BABBLE, +}; + + //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ typedef struct { + // cached register uint8_t mode; + uint8_t peraddr; + uint8_t hxfr; volatile uint16_t frame_count; + + struct { + uint16_t packet_size; + uint16_t total_len; + uint8_t xfer_type; + }ep[8][2]; } max2341e_data_t; static max2341e_data_t _hcd_data; //--------------------------------------------------------------------+ -// +// API: SPI transfer with MAX3421E, must be implemented by application //--------------------------------------------------------------------+ -// API: SPI transfer with MAX3421E, must be implemented by application -bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len); +bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, + uint8_t * rx_buf, size_t rx_len, bool keep_cs); +//void tuh_max3421e_int_enable(uint8_t rhport, bool enabled); + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ // return HIRQ register since we are in full-duplex mode static uint8_t reg_write(uint8_t reg, uint8_t data) { uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data}; uint8_t rx_buf[2] = {0, 0}; - tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2); + tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2, false); TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]); return rx_buf[0]; } @@ -167,7 +201,7 @@ static uint8_t reg_write(uint8_t reg, uint8_t data) { static uint8_t reg_read(uint8_t reg) { uint8_t tx_buf[2] = {reg, 0}; uint8_t rx_buf[2] = {0, 0}; - return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2) ? rx_buf[1] : 0; + return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2, false) ? rx_buf[1] : 0; } static inline uint8_t mode_write(uint8_t data) { @@ -175,6 +209,24 @@ static inline uint8_t mode_write(uint8_t data) { return reg_write(MODE_ADDR, data); } +static inline uint8_t peraddr_write(uint8_t data) { + if ( _hcd_data.peraddr == data ) return 0; // no need to change address + + _hcd_data.peraddr = data; + return reg_write(PERADDR_ADDR, data); +} + +static inline uint8_t hxfr_write(uint8_t data) { + _hcd_data.hxfr = data; + return reg_write(HXFR_ADDR, data); +} + +static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) { + uint8_t tx_buf[1] = {reg | CMDBYTE_WRITE}; + tuh_max3421e_spi_xfer_api(0, tx_buf, 1, NULL, 0, true); + tuh_max3421e_spi_xfer_api(0, buffer, len, NULL, 0, false); +} + //--------------------------------------------------------------------+ // Controller API @@ -252,7 +304,7 @@ bool hcd_init(uint8_t rhport) { mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST); // Enable Connection IRQ - reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ); + reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ); #if 0 // Note: if device is already connected, CONDET IRQ may not be triggered. @@ -271,33 +323,6 @@ bool hcd_init(uint8_t rhport) { return true; } -// Interrupt Handler -void hcd_int_handler(uint8_t rhport) { - (void) rhport; - - uint8_t hirq = reg_read(HIRQ_ADDR); - TU_LOG3_HEX(hirq); - - if (hirq & HIRQ_CONDET_IRQ) { - tusb_speed_t speed = handle_connect_irq(rhport); - - if (speed == TUSB_SPEED_INVALID) { - hcd_event_device_remove(rhport, true); - }else { - hcd_event_device_attach(rhport, true); - } - } - - if (hirq & HIRQ_FRAME_IRQ) { - _hcd_data.frame_count++; - } - - // clear all interrupt - if ( hirq ) { - reg_write(HIRQ_ADDR, hirq); - } -} - // Enable USB interrupt void hcd_int_enable (uint8_t rhport) { (void) rhport; @@ -359,7 +384,12 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const (void) dev_addr; (void) ep_desc; - return false; + uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress); + uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress); + + _hcd_data.ep[ep_num][ep_dir].packet_size = tu_edpt_packet_size(ep_desc); + + return true; } // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked @@ -384,12 +414,18 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { } // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked -bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { +bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]) { (void) rhport; - (void) dev_addr; + (void) daddr; (void) setup_packet; - return false; + _hcd_data.ep[0][0].total_len = 8; + + peraddr_write(daddr); + fifo_write(SUDFIFO_ADDR, setup_packet, 8); + hxfr_write(HXFR_SETUP); + + return true; } // clear stall, data toggle is also reset to DATA0 @@ -401,4 +437,67 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { return false; } +// Interrupt Handler +void hcd_int_handler(uint8_t rhport) { + uint8_t hirq = reg_read(HIRQ_ADDR); + TU_LOG3_HEX(hirq); + + if (hirq & HIRQ_CONDET_IRQ) { + tusb_speed_t speed = handle_connect_irq(rhport); + + if (speed == TUSB_SPEED_INVALID) { + hcd_event_device_remove(rhport, true); + }else { + hcd_event_device_attach(rhport, true); + } + } + + if (hirq & HIRQ_FRAME_IRQ) { + _hcd_data.frame_count++; + } + + if (hirq & HIRQ_HXFRDN_IRQ) { + uint8_t const hrsl = reg_read(HRSL_ADDR); + uint8_t const result = hrsl & HRSL_RESULT_MASK; + uint8_t xfer_result; + + TU_LOG3("HRSL: %02X\r\n", hrsl); + switch(result) { + case HRSL_SUCCESS: + xfer_result = XFER_RESULT_SUCCESS; + break; + + case HRSL_STALL: + xfer_result = XFER_RESULT_STALLED; + break; + + default: + xfer_result = XFER_RESULT_FAILED; + break; + } + + uint8_t ep_dir = 0; + uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; + uint8_t const xfer_type = _hcd_data.hxfr & 0xf0; + + if ( xfer_type & HXFR_SETUP ) { + // SETUP transfer + ep_dir = 0; + }else if ( !(xfer_type & HXFR_OUT_NIN) ) { + // IN transfer + ep_dir = 1; + } + + uint8_t const ep_addr = tu_edpt_addr(ep_num, ep_dir); + uint16_t xferred_len = _hcd_data.ep[ep_num][ep_dir].total_len; + + hcd_event_xfer_complete(_hcd_data.peraddr, ep_addr, xferred_len, xfer_result, true); + } + + // clear all interrupt + if ( hirq ) { + reg_write(HIRQ_ADDR, hirq); + } +} + #endif -- cgit v1.3.1 From e3f3179924f7c84c4bb3e69234720f9afc178727 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 23 Aug 2023 15:08:12 +0700 Subject: able to get 8 byte descriptor, but read(RCVBC) always return 0 - rename max3421e to max3421 - fix incorrect bitmask for HCTL, fix initial device connect - fix bus reset cause connect IRQ --- hw/bsp/nrf/family.c | 24 +- hw/bsp/nrf/family.cmake | 2 +- src/host/hcd.h | 2 +- src/portable/analog/max3421/hcd_max3421.c | 613 ++++++++++++++++++++++++++++ src/portable/analog/max3421e/hcd_max3421e.c | 503 ----------------------- 5 files changed, 624 insertions(+), 520 deletions(-) create mode 100644 src/portable/analog/max3421/hcd_max3421.c delete mode 100644 src/portable/analog/max3421e/hcd_max3421e.c (limited to 'src') diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index 862f67bc7..45a5166a7 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -93,7 +93,7 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) { } //------------- Host using MAX2341E -------------// -#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E +#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0); void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { @@ -102,19 +102,17 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { tuh_int_handler(1); } -static inline void max3421e_cs_assert(bool active) { - nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1); -} - //--------------------------------------------------------------------+ // API: SPI transfer with MAX3421E, must be implemented by application //--------------------------------------------------------------------+ -bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, - uint8_t * rx_buf, size_t rx_len, bool keep_cs) { +void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) { (void) rhport; + nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1); +} - max3421e_cs_assert(true); +bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) { + (void) rhport; nrfx_spim_xfer_desc_t xfer = { .p_tx_buffer = tx_buf, @@ -123,11 +121,7 @@ bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx .rx_length = rx_len, }; - bool ret = (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS); - - if ( !keep_cs ) max3421e_cs_assert(false); - - return ret; + return (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS); } #endif @@ -218,10 +212,10 @@ void board_init(void) { if ( usb_reg & OUTPUTRDY_Msk ) tusb_hal_nrf_power_event(USB_EVT_READY); #endif -#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E +#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 // manually manage CS nrf_gpio_cfg_output(MAX3421E_CS_PIN); - max3421e_cs_assert(false); + tuh_max3421_spi_cs_api(0, false); // USB host using max3421e usb controller via SPI nrfx_spim_config_t cfg = { diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 8bf7bcb52..ff6b882ce 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -124,7 +124,7 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c - ${TOP}/src/portable/analog/max3421e/hcd_max3421e.c + ${TOP}/src/portable/analog/max3421/hcd_max3421.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/src/host/hcd.h b/src/host/hcd.h index 079877b79..1f01a1a2f 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -170,7 +170,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr); bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc); // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked -bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen); +bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen); // Abort a queued transfer. Note: it can only abort transfer that has not been started // Return true if a queued transfer is aborted, false if there is no transfer to abort diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c new file mode 100644 index 000000000..edcb6ca6f --- /dev/null +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -0,0 +1,613 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 + +#include "host/hcd.h" + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +// Command format is +// Reg [7:3] | 0 [2] | Dir [1] | Ack [0] + +enum { + CMDBYTE_WRITE = 0x02, +}; + +enum { + RCVVFIFO_ADDR = 1u << 3, // 0x08 + SNDFIFO_ADDR = 2u << 3, // 0x10 + SUDFIFO_ADDR = 4u << 3, // 0x20 + RCVBC_ADDR = 6u << 3, // 0x30 + SNDBC_ADDR = 7u << 3, // 0x38 + USBIRQ_ADDR = 13u << 3, // 0x68 + USBIEN_ADDR = 14u << 3, // 0x70 + USBCTL_ADDR = 15u << 3, // 0x78 + CPUCTL_ADDR = 16u << 3, // 0x80 + PINCTL_ADDR = 17u << 3, // 0x88 + REVISION_ADDR = 18u << 3, // 0x90 + HIRQ_ADDR = 25u << 3, // 0xC8 + HIEN_ADDR = 26u << 3, // 0xD0 + MODE_ADDR = 27u << 3, // 0xD8 + PERADDR_ADDR = 28u << 3, // 0xE0 + HCTL_ADDR = 29u << 3, // 0xE8 + HXFR_ADDR = 30u << 3, // 0xF0 + HRSL_ADDR = 31u << 3, // 0xF8 +}; + +enum { + USBIRQ_OSCOK_IRQ = 1u << 0, + USBIRQ_NOVBUS_IRQ = 1u << 5, + USBIRQ_VBUS_IRQ = 1u << 6, +}; + +enum { + USBCTL_PWRDOWN = 1u << 4, + USBCTL_CHIPRES = 1u << 5, +}; + +enum { + CPUCTL_IE = 1u << 0, + CPUCTL_PULSEWID0 = 1u << 6, + CPUCTL_PULSEWID1 = 1u << 7, +}; + +enum { + PINCTL_GPXA = 1u << 0, + PINCTL_GPXB = 1u << 1, + PINCTL_POSINT = 1u << 2, + PINCTL_INTLEVEL = 1u << 3, + PINCTL_FDUPSPI = 1u << 4, +}; + +enum { + HIRQ_BUSEVENT_IRQ = 1u << 0, + HIRQ_RWU_IRQ = 1u << 1, + HIRQ_RCVDAV_IRQ = 1u << 2, + HIRQ_SNDBAV_IRQ = 1u << 3, + HIRQ_SUSDN_IRQ = 1u << 4, + HIRQ_CONDET_IRQ = 1u << 5, + HIRQ_FRAME_IRQ = 1u << 6, + HIRQ_HXFRDN_IRQ = 1u << 7, +}; + +enum { + MODE_HOST = 1u << 0, + MODE_LOWSPEED = 1u << 1, + MODE_HUBPRE = 1u << 2, + MODE_SOFKAENAB = 1u << 3, + MODE_SEPIRQ = 1u << 4, + MODE_DELAYISO = 1u << 5, + MODE_DMPULLDN = 1u << 6, + MODE_DPPULLDN = 1u << 7, +}; + +enum { + HCTL_BUSRST = 1u << 0, + HCTL_FRMRST = 1u << 1, + HCTL_SAMPLEBUS = 1u << 2, + HCTL_SIGRSM = 1u << 3, + HCTL_RCVTOG0 = 1u << 4, + HCTL_RCVTOG1 = 1u << 5, + HCTL_SNDTOG0 = 1u << 6, + HCTL_SNDTOG1 = 1u << 7, +}; + +enum { + HXFR_EPNUM_MASK = 0x0f, + HXFR_SETUP = 1u << 4, + HXFR_OUT_NIN = 1u << 5, + HXFR_ISO = 1u << 6, + HXFR_HS = 1u << 7, +}; + +enum { + HRSL_RESULT_MASK = 0x0f, + HRSL_RCVTOGRD = 1u << 4, + HRSL_SNDTOGRD = 1u << 5, + HRSL_KSTATUS = 1u << 6, + HRSL_JSTATUS = 1u << 7, +}; + +enum { + HRSL_SUCCESS = 0, + HRSL_BUSY, + HRSL_BAD_REQ, + HRSL_UNDEF, + HRSL_NAK, + HRSL_STALL, + HRSL_TOG_ERR, + HRSL_WRONG_PID, + HRSL_BAD_BYTECOUNT, + HRSL_PID_ERR, + HRSL_PKT_ERR, + HRSL_CRC_ERR, + HRSL_K_ERR, + HRSL_J_ERR, + HRSL_TIMEOUT, + HRSL_BABBLE, +}; + +enum { + DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ +}; + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +typedef struct { + uint8_t xfer_type; + uint8_t data_toggle; + uint16_t packet_size; + + uint16_t total_len; + uint16_t xferred_len; + uint8_t* buf; +} hcd_ep_t; + +typedef struct { + bool inited; + + // cached register + uint8_t sndbc; + uint8_t mode; + uint8_t peraddr; + uint8_t hxfr; + + volatile uint16_t frame_count; + + hcd_ep_t ep[8][2]; +} max2341_data_t; + +static max2341_data_t _hcd_data; + +//--------------------------------------------------------------------+ +// API: SPI transfer with MAX3421E, must be implemented by application +//--------------------------------------------------------------------+ + +void tuh_max3421_spi_cs_api(uint8_t rhport, bool active); +bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len); + +//void tuh_max3421e_int_enable(uint8_t rhport, bool enabled); + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) { + reg |= CMDBYTE_WRITE; + + tuh_max3421_spi_cs_api(0, true); + + tuh_max3421_spi_xfer_api(0, ®, 1, NULL, 0); + tuh_max3421_spi_xfer_api(0, buffer, len, NULL, 0); + + tuh_max3421_spi_cs_api(0, false); +} + +// return HIRQ register since we are in full-duplex mode +static uint8_t reg_write(uint8_t reg, uint8_t data) { + uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data}; + uint8_t rx_buf[2] = {0, 0}; + + tuh_max3421_spi_cs_api(0, true); + tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2); + tuh_max3421_spi_cs_api(0, false); + + TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]); + return rx_buf[0]; +} + +static uint8_t reg_read(uint8_t reg) { + uint8_t tx_buf[2] = {reg, 0}; + uint8_t rx_buf[2] = {0, 0}; + + tuh_max3421_spi_cs_api(0, true); + bool ret = tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2); + tuh_max3421_spi_cs_api(0, false); + + return ret ? rx_buf[1] : 0; +} + +static inline uint8_t mode_write(uint8_t data) { + _hcd_data.mode = data; + return reg_write(MODE_ADDR, data); +} + +static inline uint8_t peraddr_write(uint8_t data) { + if ( _hcd_data.peraddr == data ) return 0; // no need to change address + + _hcd_data.peraddr = data; + return reg_write(PERADDR_ADDR, data); +} + +static inline uint8_t hxfr_write(uint8_t data) { + _hcd_data.hxfr = data; + return reg_write(HXFR_ADDR, data); +} + +static inline uint8_t sndbc_write(uint8_t data) { + _hcd_data.sndbc = data; + return reg_write(SNDBC_ADDR, data); +} + + +//--------------------------------------------------------------------+ +// Controller API +//--------------------------------------------------------------------+ + +// optional hcd configuration, called by tuh_configure() +bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { + (void) rhport; + (void) cfg_id; + (void) cfg_param; + + return false; +} + +tusb_speed_t handle_connect_irq(uint8_t rhport) { + (void) rhport; + + uint8_t const hrsl = reg_read(HRSL_ADDR); + uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS); + + tusb_speed_t speed; + uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST; + + switch(jk) { + case 0x00: + // SEO is disconnected + speed = TUSB_SPEED_INVALID; + break; + + case (HRSL_JSTATUS | HRSL_KSTATUS): + // SE1 is illegal + speed = TUSB_SPEED_INVALID; + break; + + default: { + // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State) + uint8_t const mode = reg_read(MODE_ADDR); + uint8_t const ls_bit = mode & MODE_LOWSPEED; + + if ( (ls_bit && (jk == HRSL_JSTATUS)) || (!ls_bit && (jk == HRSL_KSTATUS)) ) { + speed = TUSB_SPEED_LOW; + new_mode |= MODE_LOWSPEED; + } else { + speed = TUSB_SPEED_FULL; + } + + new_mode |= MODE_SOFKAENAB; // enable SOF since there is new device + + break; + } + } + + mode_write(new_mode); + TU_LOG2_INT(speed); + return speed; +} + +// Initialize controller to host mode +bool hcd_init(uint8_t rhport) { + (void) rhport; + + tu_memclr(&_hcd_data, sizeof(_hcd_data)); + + // full duplex, interrupt negative edge + reg_write(PINCTL_ADDR, PINCTL_FDUPSPI); + + // reset + reg_write(USBCTL_ADDR, USBCTL_CHIPRES); + reg_write(USBCTL_ADDR, 0); + while( !(reg_read(USBIRQ_ADDR) & USBIRQ_OSCOK_IRQ) ) { + // wait for oscillator to stabilize + } + + // Mode: Host and DP/DM pull down + mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST); + + // bus reset, this will trigger CONDET IRQ if device is already connected + reg_write(HCTL_ADDR, HCTL_BUSRST); + + // clear all previously pending IRQ + reg_write(HIRQ_ADDR, 0xff); + + _hcd_data.inited = true; + + // Enable Connection IRQ + reg_write(HIEN_ADDR, DEFAULT_HIEN); + + // Enable Interrupt pin + reg_write(CPUCTL_ADDR, CPUCTL_IE); + + return true; +} + +// Enable USB interrupt +void hcd_int_enable (uint8_t rhport) { + (void) rhport; +} + +// Disable USB interrupt +void hcd_int_disable(uint8_t rhport) { + (void) rhport; +} + +// Get frame number (1ms) +uint32_t hcd_frame_number(uint8_t rhport) { + (void) rhport; + return (uint32_t ) _hcd_data.frame_count; +} + +//--------------------------------------------------------------------+ +// Port API +//--------------------------------------------------------------------+ + +// Get the current connect status of roothub port +bool hcd_port_connect_status(uint8_t rhport) { + (void) rhport; + return (_hcd_data.mode & MODE_SOFKAENAB) ? true : false; +} + +// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete. +// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence. +void hcd_port_reset(uint8_t rhport) { + (void) rhport; + // Bus reset will also trigger CONDET IRQ, disable it + uint8_t hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ; + reg_write(HIEN_ADDR, hien); + + reg_write(HCTL_ADDR, HCTL_BUSRST); +} + +// Complete bus reset sequence, may be required by some controllers +void hcd_port_reset_end(uint8_t rhport) { + (void) rhport; + reg_write(HCTL_ADDR, 0); + + // Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset + reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ); + reg_write(HIEN_ADDR, DEFAULT_HIEN); +} + +// Get port link speed +tusb_speed_t hcd_port_speed_get(uint8_t rhport) { + (void) rhport; + return (_hcd_data.mode & MODE_LOWSPEED) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL; +} + +// HCD closes all opened endpoints belong to this device +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { + (void) rhport; + (void) dev_addr; +} + +//--------------------------------------------------------------------+ +// Endpoints API +//--------------------------------------------------------------------+ + +// Open an endpoint +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { + (void) rhport; + (void) dev_addr; + (void) ep_desc; + + uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress); + uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress); + + _hcd_data.ep[ep_num][ep_dir].packet_size = tu_edpt_packet_size(ep_desc); + + return true; +} + +// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked +bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { + (void) rhport; + + uint8_t const ep_num = tu_edpt_number(ep_addr); + uint8_t const ep_dir = tu_edpt_dir(ep_addr); + + hcd_ep_t* ep = &_hcd_data.ep[ep_num][ep_dir]; + + ep->buf = buffer; + ep->total_len = buflen; + ep->xferred_len = 0; + + uint8_t hirq = peraddr_write(daddr); + + uint8_t hctl = 0; + uint8_t hxfr = ep_num; + if ( ep_num == 0 ) { + ep->data_toggle = 1; + if ( buffer == NULL || buflen == 0 ) { + // ZLP for ACK stage + hxfr |= HXFR_HS; + } + } else if ( ep->xfer_type == TUSB_XFER_ISOCHRONOUS ) { + hxfr |= HXFR_ISO; + } + + if ( 0 == ep_dir ) { + // Page 12: Programming BULK-OUT Transfers + TU_ASSERT(hirq & HIRQ_RCVDAV_IRQ); + + uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size); + fifo_write(SNDFIFO_ADDR, buffer, xact_len); + reg_write(SNDBC_ADDR, xact_len); + + hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0); + hxfr |= HXFR_OUT_NIN; + } else { + // Page 13: Programming BULK-IN Transfers + hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0); + } + + reg_write(HCTL_ADDR, hctl); + hxfr_write(hxfr); + + return true; +} + +// Abort a queued transfer. Note: it can only abort transfer that has not been started +// Return true if a queued transfer is aborted, false if there is no transfer to abort +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + + return false; +} + +// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked +bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]) { + (void) rhport; + + hcd_ep_t* ep = &_hcd_data.ep[0][0]; + ep->total_len = 8; + ep->xferred_len = 0; + + peraddr_write(daddr); + fifo_write(SUDFIFO_ADDR, setup_packet, 8); + hxfr_write(HXFR_SETUP); + + return true; +} + +// clear stall, data toggle is also reset to DATA0 +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + + return false; +} + +static void handle_xfer_done(uint8_t rhport) { + (void) rhport; + + uint8_t const hrsl = reg_read(HRSL_ADDR); + uint8_t const result = hrsl & HRSL_RESULT_MASK; + uint8_t xfer_result; + + TU_LOG3("HRSL: %02X\r\n", hrsl); + switch(result) { + case HRSL_SUCCESS: + xfer_result = XFER_RESULT_SUCCESS; + break; + + case HRSL_STALL: + xfer_result = XFER_RESULT_STALLED; + break; + + case HRSL_BAD_REQ: + // occurred when initialized without any pending transfer. Skip for now + return; + + default: + xfer_result = XFER_RESULT_FAILED; + break; + } + + uint8_t ep_dir = 0; + uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; + uint8_t const xfer_type = _hcd_data.hxfr & 0xf0; + + hcd_ep_t * ep; + + if ( (xfer_type & HXFR_SETUP) || (xfer_type & HXFR_OUT_NIN) ) { + // SETUP or OUT transfer + ep_dir = 0; + ep = &_hcd_data.ep[ep_num][ep_dir]; + + uint8_t const xact_len = (xfer_type & HXFR_SETUP) ? 8 : _hcd_data.sndbc; + ep->xferred_len += xact_len; + + if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) { + hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true); + }else { + // more to transfer + } + } else { + // IN transfer + ep_dir = 1; + ep = &_hcd_data.ep[ep_num][ep_dir]; + uint8_t const xact_len = reg_read(RCVBC_ADDR); + ep->xferred_len += xact_len; + + // short packet or all bytes transferred + if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) { + hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true); + }else { + // more to transfer + } + } +} + +// Interrupt Handler +void hcd_int_handler(uint8_t rhport) { + // not initialized, do nothing + if ( !_hcd_data.inited ) return; + + uint8_t hirq = reg_read(HIRQ_ADDR); + TU_LOG3_HEX(hirq); + + if (hirq & HIRQ_FRAME_IRQ) { + _hcd_data.frame_count++; + } + + if (hirq & HIRQ_CONDET_IRQ) { + tusb_speed_t speed = handle_connect_irq(rhport); + + if (speed == TUSB_SPEED_INVALID) { + hcd_event_device_remove(rhport, true); + }else { + hcd_event_device_attach(rhport, true); + } + } + + if (hirq & HIRQ_HXFRDN_IRQ) { + handle_xfer_done(rhport); + } + + if ( hirq & HIRQ_RCVDAV_IRQ ) { + TU_LOG3("RCVDAV\r\n"); + TU_LOG3_INT(reg_read(RCVBC_ADDR)); + } + + // clear all interrupt execept SNDBAV_IRQ + hirq &= ~HIRQ_SNDBAV_IRQ; + if ( hirq ) { + reg_write(HIRQ_ADDR, hirq); + } +} + +#endif diff --git a/src/portable/analog/max3421e/hcd_max3421e.c b/src/portable/analog/max3421e/hcd_max3421e.c deleted file mode 100644 index c9596f695..000000000 --- a/src/portable/analog/max3421e/hcd_max3421e.c +++ /dev/null @@ -1,503 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2023 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E - -#include "host/hcd.h" - -//--------------------------------------------------------------------+ -// -//--------------------------------------------------------------------+ - -// Command format is -// Reg [7:3] | 0 [2] | Dir [1] | Ack [0] - -enum { - CMDBYTE_WRITE = 0x02, -}; - -enum { - RCVVFIFO_ADDR = 1u << 3, // 0x08 - SNDFIFO_ADDR = 2u << 3, // 0x10 - SUDFIFO_ADDR = 4u << 3, // 0x20 - RCVBC_ADDR = 6u << 3, // 0x30 - SNDBC_ADDR = 7u << 3, // 0x38 - USBIRQ_ADDR = 13u << 3, // 0x68 - USBIEN_ADDR = 14u << 3, // 0x70 - USBCTL_ADDR = 15u << 3, // 0x78 - CPUCTL_ADDR = 16u << 3, // 0x80 - PINCTL_ADDR = 17u << 3, // 0x88 - REVISION_ADDR = 18u << 3, // 0x90 - HIRQ_ADDR = 25u << 3, // 0xC8 - HIEN_ADDR = 26u << 3, // 0xD0 - MODE_ADDR = 27u << 3, // 0xD8 - PERADDR_ADDR = 28u << 3, // 0xE0 - HCTL_ADDR = 29u << 3, // 0xE8 - HXFR_ADDR = 30u << 3, // 0xF0 - HRSL_ADDR = 31u << 3, // 0xF8 -}; - -enum { - USBIRQ_OSCOK_IRQ = 1u << 0, - USBIRQ_NOVBUS_IRQ = 1u << 5, - USBIRQ_VBUS_IRQ = 1u << 6, -}; - -enum { - USBCTL_PWRDOWN = 1u << 4, - USBCTL_CHIPRES = 1u << 5, -}; - -enum { - CPUCTL_IE = 1u << 0, - CPUCTL_PULSEWID0 = 1u << 6, - CPUCTL_PULSEWID1 = 1u << 7, -}; - -enum { - PINCTL_GPXA = 1u << 0, - PINCTL_GPXB = 1u << 1, - PINCTL_POSINT = 1u << 2, - PINCTL_INTLEVEL = 1u << 3, - PINCTL_FDUPSPI = 1u << 4, -}; - -enum { - HIRQ_BUSEVENT_IRQ = 1u << 0, - HIRQ_RWU_IRQ = 1u << 1, - HIRQ_RCVDAV_IRQ = 1u << 2, - HIRQ_SNDBAV_IRQ = 1u << 3, - HIRQ_SUSDN_IRQ = 1u << 4, - HIRQ_CONDET_IRQ = 1u << 5, - HIRQ_FRAME_IRQ = 1u << 6, - HIRQ_HXFRDN_IRQ = 1u << 7, -}; - -enum { - MODE_HOST = 1u << 0, - MODE_LOWSPEED = 1u << 1, - MODE_HUBPRE = 1u << 2, - MODE_SOFKAENAB = 1u << 3, - MODE_SEPIRQ = 1u << 4, - MODE_DELAYISO = 1u << 5, - MODE_DMPULLDN = 1u << 6, - MODE_DPPULLDN = 1u << 7, -}; - -enum { - HCTL_BUSRST = 1u << 1, - HCTL_FRMRST = 1u << 2, - HCTL_SAMPLEBUS = 1u << 3, - HCTL_SIGRSM = 1u << 4, - HCTL_RCVTOG0 = 1u << 5, - HCTL_RCVTOG1 = 1u << 6, - HCTL_SNDTOG0 = 1u << 7, - HCTL_SNDTOG1 = 1u << 8, -}; - -enum { - HXFR_EPNUM_MASK = 0x0f, - HXFR_SETUP = 1u << 4, - HXFR_OUT_NIN = 1u << 5, - HXFR_ISO = 1u << 6, - HXFR_HS = 1u << 7, -}; - -enum { - HRSL_RESULT_MASK = 0x0f, - HRSL_RCVTOGRD = 1u << 4, - HRSL_SNDTOGRD = 1u << 5, - HRSL_KSTATUS = 1u << 6, - HRSL_JSTATUS = 1u << 7, -}; - -enum { - HRSL_SUCCESS = 0, - HRSL_BUSY, - HRSL_BAD_REQ, - HRSL_UNDEF, - HRSL_NAK, - HRSL_STALL, - HRSL_TOG_ERR, - HRSL_WRONG_PID, - HRSL_BAD_BYTECOUNT, - HRSL_PID_ERR, - HRSL_PKT_ERR, - HRSL_CRC_ERR, - HRSL_K_ERR, - HRSL_J_ERR, - HRSL_TIMEOUT, - HRSL_BABBLE, -}; - - -//--------------------------------------------------------------------+ -// -//--------------------------------------------------------------------+ - -typedef struct { - // cached register - uint8_t mode; - uint8_t peraddr; - uint8_t hxfr; - - volatile uint16_t frame_count; - - struct { - uint16_t packet_size; - uint16_t total_len; - uint8_t xfer_type; - }ep[8][2]; -} max2341e_data_t; - -static max2341e_data_t _hcd_data; - -//--------------------------------------------------------------------+ -// API: SPI transfer with MAX3421E, must be implemented by application -//--------------------------------------------------------------------+ - -bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, - uint8_t * rx_buf, size_t rx_len, bool keep_cs); -//void tuh_max3421e_int_enable(uint8_t rhport, bool enabled); - -//--------------------------------------------------------------------+ -// -//--------------------------------------------------------------------+ - -// return HIRQ register since we are in full-duplex mode -static uint8_t reg_write(uint8_t reg, uint8_t data) { - uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data}; - uint8_t rx_buf[2] = {0, 0}; - tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2, false); - TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]); - return rx_buf[0]; -} - -static uint8_t reg_read(uint8_t reg) { - uint8_t tx_buf[2] = {reg, 0}; - uint8_t rx_buf[2] = {0, 0}; - return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2, false) ? rx_buf[1] : 0; -} - -static inline uint8_t mode_write(uint8_t data) { - _hcd_data.mode = data; - return reg_write(MODE_ADDR, data); -} - -static inline uint8_t peraddr_write(uint8_t data) { - if ( _hcd_data.peraddr == data ) return 0; // no need to change address - - _hcd_data.peraddr = data; - return reg_write(PERADDR_ADDR, data); -} - -static inline uint8_t hxfr_write(uint8_t data) { - _hcd_data.hxfr = data; - return reg_write(HXFR_ADDR, data); -} - -static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) { - uint8_t tx_buf[1] = {reg | CMDBYTE_WRITE}; - tuh_max3421e_spi_xfer_api(0, tx_buf, 1, NULL, 0, true); - tuh_max3421e_spi_xfer_api(0, buffer, len, NULL, 0, false); -} - - -//--------------------------------------------------------------------+ -// Controller API -//--------------------------------------------------------------------+ - -// optional hcd configuration, called by tuh_configure() -bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { - (void) rhport; - (void) cfg_id; - (void) cfg_param; - - return false; -} - -tusb_speed_t handle_connect_irq(uint8_t rhport) { - (void) rhport; - - uint8_t const hrsl = reg_read(HRSL_ADDR); - uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS); - - tusb_speed_t speed; - uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST; - - switch(jk) { - case 0x00: - // SEO is disconnected - speed = TUSB_SPEED_INVALID; - break; - - case (HRSL_JSTATUS | HRSL_KSTATUS): - // SE1 is illegal - speed = TUSB_SPEED_INVALID; - break; - - default: { - // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State) - uint8_t const mode = reg_read(MODE_ADDR); - uint8_t const ls_bit = mode & MODE_LOWSPEED; - - if ( (ls_bit && (jk == HRSL_JSTATUS)) || (!ls_bit && (jk == HRSL_KSTATUS)) ) { - speed = TUSB_SPEED_LOW; - new_mode |= MODE_LOWSPEED; - } else { - speed = TUSB_SPEED_FULL; - } - - new_mode |= MODE_SOFKAENAB; // enable SOF since there is new device - - break; - } - } - - mode_write(new_mode); - TU_LOG2_INT(speed); - return speed; -} - -// Initialize controller to host mode -bool hcd_init(uint8_t rhport) { - (void) rhport; - - tu_memclr(&_hcd_data, sizeof(_hcd_data)); - - // full duplex, interrupt level (should be configurable) - reg_write(PINCTL_ADDR, PINCTL_FDUPSPI | PINCTL_INTLEVEL); - - // reset - reg_write(USBCTL_ADDR, USBCTL_CHIPRES); - reg_write(USBCTL_ADDR, 0); - while( !(reg_read(USBIRQ_ADDR) & USBIRQ_OSCOK_IRQ) ) { - // wait for oscillator to stabilize - } - - // Mode: Host and DP/DM pull down - mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST); - - // Enable Connection IRQ - reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ); - - #if 0 - // Note: if device is already connected, CONDET IRQ may not be triggered. - // We need to detect it by sampling bus signal. FIXME not working - reg_write(HCTL_ADDR, HCTL_SAMPLEBUS); - while ( reg_read(HCTL_ADDR) & HCTL_SAMPLEBUS ) {} - - if ( TUSB_SPEED_INVALID != handle_connect_irq(rhport) ) { - reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ); // clear connect irq - } - #endif - - // Enable Interrupt pin - reg_write(CPUCTL_ADDR, CPUCTL_IE); - - return true; -} - -// Enable USB interrupt -void hcd_int_enable (uint8_t rhport) { - (void) rhport; -} - -// Disable USB interrupt -void hcd_int_disable(uint8_t rhport) { - (void) rhport; -} - -// Get frame number (1ms) -uint32_t hcd_frame_number(uint8_t rhport) { - (void) rhport; - return (uint32_t ) _hcd_data.frame_count; -} - -//--------------------------------------------------------------------+ -// Port API -//--------------------------------------------------------------------+ - -// Get the current connect status of roothub port -bool hcd_port_connect_status(uint8_t rhport) { - (void) rhport; - return (_hcd_data.mode & MODE_SOFKAENAB) ? true : false; -} - -// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete. -// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence. -void hcd_port_reset(uint8_t rhport) { - (void) rhport; - reg_write(HCTL_ADDR, HCTL_BUSRST); -} - -// Complete bus reset sequence, may be required by some controllers -void hcd_port_reset_end(uint8_t rhport) { - (void) rhport; - reg_write(HCTL_ADDR, 0); -} - -// Get port link speed -tusb_speed_t hcd_port_speed_get(uint8_t rhport) { - (void) rhport; - return (_hcd_data.mode & MODE_LOWSPEED) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL; -} - -// HCD closes all opened endpoints belong to this device -void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { - (void) rhport; - (void) dev_addr; -} - -//--------------------------------------------------------------------+ -// Endpoints API -//--------------------------------------------------------------------+ - -// Open an endpoint -bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { - (void) rhport; - (void) dev_addr; - (void) ep_desc; - - uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress); - uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress); - - _hcd_data.ep[ep_num][ep_dir].packet_size = tu_edpt_packet_size(ep_desc); - - return true; -} - -// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked -bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { - (void) rhport; - (void) dev_addr; - (void) ep_addr; - (void) buffer; - (void) buflen; - - return false; -} - -// Abort a queued transfer. Note: it can only abort transfer that has not been started -// Return true if a queued transfer is aborted, false if there is no transfer to abort -bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { - (void) rhport; - (void) dev_addr; - (void) ep_addr; - - return false; -} - -// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked -bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]) { - (void) rhport; - (void) daddr; - (void) setup_packet; - - _hcd_data.ep[0][0].total_len = 8; - - peraddr_write(daddr); - fifo_write(SUDFIFO_ADDR, setup_packet, 8); - hxfr_write(HXFR_SETUP); - - return true; -} - -// clear stall, data toggle is also reset to DATA0 -bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { - (void) rhport; - (void) dev_addr; - (void) ep_addr; - - return false; -} - -// Interrupt Handler -void hcd_int_handler(uint8_t rhport) { - uint8_t hirq = reg_read(HIRQ_ADDR); - TU_LOG3_HEX(hirq); - - if (hirq & HIRQ_CONDET_IRQ) { - tusb_speed_t speed = handle_connect_irq(rhport); - - if (speed == TUSB_SPEED_INVALID) { - hcd_event_device_remove(rhport, true); - }else { - hcd_event_device_attach(rhport, true); - } - } - - if (hirq & HIRQ_FRAME_IRQ) { - _hcd_data.frame_count++; - } - - if (hirq & HIRQ_HXFRDN_IRQ) { - uint8_t const hrsl = reg_read(HRSL_ADDR); - uint8_t const result = hrsl & HRSL_RESULT_MASK; - uint8_t xfer_result; - - TU_LOG3("HRSL: %02X\r\n", hrsl); - switch(result) { - case HRSL_SUCCESS: - xfer_result = XFER_RESULT_SUCCESS; - break; - - case HRSL_STALL: - xfer_result = XFER_RESULT_STALLED; - break; - - default: - xfer_result = XFER_RESULT_FAILED; - break; - } - - uint8_t ep_dir = 0; - uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; - uint8_t const xfer_type = _hcd_data.hxfr & 0xf0; - - if ( xfer_type & HXFR_SETUP ) { - // SETUP transfer - ep_dir = 0; - }else if ( !(xfer_type & HXFR_OUT_NIN) ) { - // IN transfer - ep_dir = 1; - } - - uint8_t const ep_addr = tu_edpt_addr(ep_num, ep_dir); - uint16_t xferred_len = _hcd_data.ep[ep_num][ep_dir].total_len; - - hcd_event_xfer_complete(_hcd_data.peraddr, ep_addr, xferred_len, xfer_result, true); - } - - // clear all interrupt - if ( hirq ) { - reg_write(HIRQ_ADDR, hirq); - } -} - -#endif -- cgit v1.3.1 From 2c237b1ae4b3ffd38fc74df29da63b01348afd1d Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 23 Aug 2023 17:49:28 +0700 Subject: able to complete 1st get device descriptor and set address --- src/portable/analog/max3421/hcd_max3421.c | 180 +++++++++++++++++++++--------- 1 file changed, 126 insertions(+), 54 deletions(-) (limited to 'src') diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index edcb6ca6f..467d7410a 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -156,7 +156,7 @@ enum { }; enum { - DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ + DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ | HIRQ_RCVDAV_IRQ }; //--------------------------------------------------------------------+ @@ -178,6 +178,8 @@ typedef struct { // cached register uint8_t sndbc; + uint8_t hirq; + uint8_t hien; uint8_t mode; uint8_t peraddr; uint8_t hxfr; @@ -203,60 +205,86 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_ //--------------------------------------------------------------------+ static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) { + uint8_t const rhport = 0; + uint8_t hirq; reg |= CMDBYTE_WRITE; - tuh_max3421_spi_cs_api(0, true); + tuh_max3421_spi_cs_api(rhport, true); - tuh_max3421_spi_xfer_api(0, ®, 1, NULL, 0); - tuh_max3421_spi_xfer_api(0, buffer, len, NULL, 0); + tuh_max3421_spi_xfer_api(rhport, ®, 1, &hirq, 1); + _hcd_data.hirq = hirq; + tuh_max3421_spi_xfer_api(rhport, buffer, len, NULL, 0); + + tuh_max3421_spi_cs_api(rhport, false); - tuh_max3421_spi_cs_api(0, false); } -// return HIRQ register since we are in full-duplex mode -static uint8_t reg_write(uint8_t reg, uint8_t data) { +static void fifo_read(uint8_t * buffer, uint16_t len) { + uint8_t const rhport = 0; + uint8_t hirq; + uint8_t const reg = RCVVFIFO_ADDR; + + tuh_max3421_spi_cs_api(rhport, true); + + tuh_max3421_spi_xfer_api(rhport, ®, 1, &hirq, 0); + _hcd_data.hirq = hirq; + tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len); + + tuh_max3421_spi_cs_api(rhport, false); +} + +static void reg_write(uint8_t reg, uint8_t data) { + uint8_t const rhport = 0; uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data}; uint8_t rx_buf[2] = {0, 0}; - tuh_max3421_spi_cs_api(0, true); - tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2); - tuh_max3421_spi_cs_api(0, false); + tuh_max3421_spi_cs_api(rhport, true); + tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2); + tuh_max3421_spi_cs_api(rhport, false); - TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]); - return rx_buf[0]; + // HIRQ register since we are in full-duplex mode + _hcd_data.hirq = rx_buf[0]; + TU_LOG3_HEX(_hcd_data.hirq); } static uint8_t reg_read(uint8_t reg) { + uint8_t const rhport = 0; uint8_t tx_buf[2] = {reg, 0}; uint8_t rx_buf[2] = {0, 0}; - tuh_max3421_spi_cs_api(0, true); - bool ret = tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2); - tuh_max3421_spi_cs_api(0, false); + tuh_max3421_spi_cs_api(rhport, true); + bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2); + tuh_max3421_spi_cs_api(rhport, false); + _hcd_data.hirq = rx_buf[0]; return ret ? rx_buf[1] : 0; } -static inline uint8_t mode_write(uint8_t data) { +static inline void hien_write(uint8_t data) { + _hcd_data.hien = data; + reg_write(HIEN_ADDR, data); +} + +static inline void mode_write(uint8_t data) { _hcd_data.mode = data; - return reg_write(MODE_ADDR, data); + reg_write(MODE_ADDR, data); } -static inline uint8_t peraddr_write(uint8_t data) { - if ( _hcd_data.peraddr == data ) return 0; // no need to change address +static inline void peraddr_write(uint8_t data) { + if ( _hcd_data.peraddr == data ) return; // no need to change address _hcd_data.peraddr = data; - return reg_write(PERADDR_ADDR, data); + reg_write(PERADDR_ADDR, data); } -static inline uint8_t hxfr_write(uint8_t data) { +static inline void hxfr_write(uint8_t data) { _hcd_data.hxfr = data; - return reg_write(HXFR_ADDR, data); + reg_write(HXFR_ADDR, data); } -static inline uint8_t sndbc_write(uint8_t data) { +static inline void sndbc_write(uint8_t data) { _hcd_data.sndbc = data; - return reg_write(SNDBC_ADDR, data); + reg_write(SNDBC_ADDR, data); } @@ -335,16 +363,16 @@ bool hcd_init(uint8_t rhport) { // Mode: Host and DP/DM pull down mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST); - // bus reset, this will trigger CONDET IRQ if device is already connected - reg_write(HCTL_ADDR, HCTL_BUSRST); + // frame reset & bus reset, this will trigger CONDET IRQ if device is already connected + reg_write(HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST); // clear all previously pending IRQ reg_write(HIRQ_ADDR, 0xff); _hcd_data.inited = true; - // Enable Connection IRQ - reg_write(HIEN_ADDR, DEFAULT_HIEN); + // Enable IRQ + hien_write(DEFAULT_HIEN); // Enable Interrupt pin reg_write(CPUCTL_ADDR, CPUCTL_IE); @@ -383,8 +411,8 @@ bool hcd_port_connect_status(uint8_t rhport) { void hcd_port_reset(uint8_t rhport) { (void) rhport; // Bus reset will also trigger CONDET IRQ, disable it - uint8_t hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ; - reg_write(HIEN_ADDR, hien); + uint8_t const hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ; + hien_write(hien); reg_write(HCTL_ADDR, HCTL_BUSRST); } @@ -396,7 +424,7 @@ void hcd_port_reset_end(uint8_t rhport) { // Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ); - reg_write(HIEN_ADDR, DEFAULT_HIEN); + hien_write(DEFAULT_HIEN); } // Get port link speed @@ -426,6 +454,10 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const _hcd_data.ep[ep_num][ep_dir].packet_size = tu_edpt_packet_size(ep_desc); + if (ep_desc->bEndpointAddress == 0) { + _hcd_data.ep[ep_num][1].packet_size = tu_edpt_packet_size(ep_desc); + } + return true; } @@ -442,15 +474,18 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf ep->total_len = buflen; ep->xferred_len = 0; - uint8_t hirq = peraddr_write(daddr); + peraddr_write(daddr); uint8_t hctl = 0; uint8_t hxfr = ep_num; if ( ep_num == 0 ) { ep->data_toggle = 1; if ( buffer == NULL || buflen == 0 ) { - // ZLP for ACK stage + // ZLP for ACK stage, use HS hxfr |= HXFR_HS; + hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN); + hxfr_write(hxfr); + return true; } } else if ( ep->xfer_type == TUSB_XFER_ISOCHRONOUS ) { hxfr |= HXFR_ISO; @@ -458,7 +493,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf if ( 0 == ep_dir ) { // Page 12: Programming BULK-OUT Transfers - TU_ASSERT(hirq & HIRQ_RCVDAV_IRQ); + TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ); uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size); fifo_write(SNDFIFO_ADDR, buffer, xact_len); @@ -516,7 +551,7 @@ static void handle_xfer_done(uint8_t rhport) { uint8_t const hrsl = reg_read(HRSL_ADDR); uint8_t const result = hrsl & HRSL_RESULT_MASK; - uint8_t xfer_result; + xfer_result_t xfer_result; TU_LOG3("HRSL: %02X\r\n", hrsl); switch(result) { @@ -537,18 +572,21 @@ static void handle_xfer_done(uint8_t rhport) { break; } - uint8_t ep_dir = 0; uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; uint8_t const xfer_type = _hcd_data.hxfr & 0xf0; - hcd_ep_t * ep; - if ( (xfer_type & HXFR_SETUP) || (xfer_type & HXFR_OUT_NIN) ) { // SETUP or OUT transfer - ep_dir = 0; - ep = &_hcd_data.ep[ep_num][ep_dir]; + hcd_ep_t *ep = &_hcd_data.ep[ep_num][0]; + uint8_t xact_len; + if (xfer_type & HXFR_SETUP) { + xact_len = 8; + } else if ( xfer_type & HXFR_HS ) { + xact_len = 0; + } else { + xact_len = _hcd_data.sndbc; + } - uint8_t const xact_len = (xfer_type & HXFR_SETUP) ? 8 : _hcd_data.sndbc; ep->xferred_len += xact_len; if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) { @@ -558,10 +596,27 @@ static void handle_xfer_done(uint8_t rhport) { } } else { // IN transfer - ep_dir = 1; - ep = &_hcd_data.ep[ep_num][ep_dir]; - uint8_t const xact_len = reg_read(RCVBC_ADDR); - ep->xferred_len += xact_len; + hcd_ep_t *ep = &_hcd_data.ep[ep_num][1]; + uint8_t xact_len; + + if ( xfer_type & HXFR_HS ) { + xact_len = 0; + } else { + // RCVDAV_IRQ can trigger 2 times (dual buffered) + while ( _hcd_data.hirq & HIRQ_RCVDAV_IRQ ) { + uint8_t rcvbc = reg_read(RCVBC_ADDR); + xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len); + if ( xact_len ) { + fifo_read(ep->buf, xact_len); + ep->buf += xact_len; + ep->xferred_len += xact_len; + } + + // ack RCVDVAV IRQ + reg_write(HIRQ_ADDR, HIRQ_RCVDAV_IRQ); + _hcd_data.hirq = reg_read(HIRQ_ADDR); + } + } // short packet or all bytes transferred if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) { @@ -572,13 +627,35 @@ static void handle_xfer_done(uint8_t rhport) { } } +#if CFG_TUSB_DEBUG >= 3 +void print_hirq(uint8_t hirq) { + TU_LOG3_HEX(hirq); + + if (hirq & HIRQ_HXFRDN_IRQ) TU_LOG3(" HXFRDN"); + if (hirq & HIRQ_FRAME_IRQ) TU_LOG3(" FRAME"); + if (hirq & HIRQ_CONDET_IRQ) TU_LOG3(" CONDET"); + if (hirq & HIRQ_SUSDN_IRQ) TU_LOG3(" SUSDN"); + if (hirq & HIRQ_SNDBAV_IRQ) TU_LOG3(" SNDBAV"); + if (hirq & HIRQ_RCVDAV_IRQ) TU_LOG3(" RCVDAV"); + if (hirq & HIRQ_RWU_IRQ) TU_LOG3(" RWU"); + if (hirq & HIRQ_BUSEVENT_IRQ) TU_LOG3(" BUSEVENT"); + + TU_LOG3("\r\n"); +} + +#else + #define print_hirq(hirq) +#endif + // Interrupt Handler void hcd_int_handler(uint8_t rhport) { // not initialized, do nothing if ( !_hcd_data.inited ) return; - uint8_t hirq = reg_read(HIRQ_ADDR); - TU_LOG3_HEX(hirq); + uint8_t hirq = reg_read(HIRQ_ADDR) & _hcd_data.hien; + if (!hirq) return; + + print_hirq(hirq); if (hirq & HIRQ_FRAME_IRQ) { _hcd_data.frame_count++; @@ -598,13 +675,8 @@ void hcd_int_handler(uint8_t rhport) { handle_xfer_done(rhport); } - if ( hirq & HIRQ_RCVDAV_IRQ ) { - TU_LOG3("RCVDAV\r\n"); - TU_LOG3_INT(reg_read(RCVBC_ADDR)); - } - - // clear all interrupt execept SNDBAV_IRQ - hirq &= ~HIRQ_SNDBAV_IRQ; + // clear all interrupt except SNDBAV_IRQ and RCVDAV_IRQ must be clear after pulling data from FIFO + hirq &= ~ (HIRQ_SNDBAV_IRQ | HIRQ_RCVDAV_IRQ); if ( hirq ) { reg_write(HIRQ_ADDR, hirq); } -- cgit v1.3.1 From 3ed5d6c3724cfa9699d403a76a00f1b04672e2b5 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 24 Aug 2023 16:27:12 +0700 Subject: complete enumeration --- hw/bsp/nrf/family.c | 5 ++- src/portable/analog/max3421/hcd_max3421.c | 68 +++++++++++++++++++------------ 2 files changed, 47 insertions(+), 26 deletions(-) (limited to 'src') diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index 45a5166a7..368763b84 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -105,6 +105,10 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { //--------------------------------------------------------------------+ // API: SPI transfer with MAX3421E, must be implemented by application //--------------------------------------------------------------------+ +void tuh_max3421e_int_api(uint8_t rhport, bool enabled) { + (void) rhport; + nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, enabled); +} void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) { (void) rhport; @@ -241,7 +245,6 @@ void board_init(void) { in_config.pull = NRF_GPIO_PIN_PULLUP; nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max3421e_int_handler); - nrfx_gpiote_in_event_enable(MAX3241E_INTR_PIN, true); #endif } diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 467d7410a..514cf34b7 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -166,6 +166,7 @@ enum { typedef struct { uint8_t xfer_type; uint8_t data_toggle; + uint8_t xfer_complete; uint16_t packet_size; uint16_t total_len; @@ -244,7 +245,6 @@ static void reg_write(uint8_t reg, uint8_t data) { // HIRQ register since we are in full-duplex mode _hcd_data.hirq = rx_buf[0]; - TU_LOG3_HEX(_hcd_data.hirq); } static uint8_t reg_read(uint8_t reg) { @@ -473,6 +473,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf ep->buf = buffer; ep->total_len = buflen; ep->xferred_len = 0; + ep->xfer_complete = 0; peraddr_write(daddr); @@ -595,34 +596,19 @@ static void handle_xfer_done(uint8_t rhport) { // more to transfer } } else { - // IN transfer + // IN transfer: fifo data is already received in RCVDAV IRQ hcd_ep_t *ep = &_hcd_data.ep[ep_num][1]; - uint8_t xact_len; if ( xfer_type & HXFR_HS ) { - xact_len = 0; - } else { - // RCVDAV_IRQ can trigger 2 times (dual buffered) - while ( _hcd_data.hirq & HIRQ_RCVDAV_IRQ ) { - uint8_t rcvbc = reg_read(RCVBC_ADDR); - xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len); - if ( xact_len ) { - fifo_read(ep->buf, xact_len); - ep->buf += xact_len; - ep->xferred_len += xact_len; - } - - // ack RCVDVAV IRQ - reg_write(HIRQ_ADDR, HIRQ_RCVDAV_IRQ); - _hcd_data.hirq = reg_read(HIRQ_ADDR); - } + ep->xfer_complete = 1; } // short packet or all bytes transferred - if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) { + if ( ep->xfer_complete ) { hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true); }else { // more to transfer + hxfr_write(_hcd_data.hxfr); } } } @@ -655,7 +641,7 @@ void hcd_int_handler(uint8_t rhport) { uint8_t hirq = reg_read(HIRQ_ADDR) & _hcd_data.hien; if (!hirq) return; - print_hirq(hirq); +// print_hirq(hirq); if (hirq & HIRQ_FRAME_IRQ) { _hcd_data.frame_count++; @@ -671,12 +657,44 @@ void hcd_int_handler(uint8_t rhport) { } } - if (hirq & HIRQ_HXFRDN_IRQ) { - handle_xfer_done(rhport); + // queue more transfer in handle_xfer_done() can cause hirq to be set again while external IRQ may not catch and/or + // not call this handler again. So we need to loop until all IRQ are cleared + while ( hirq & (HIRQ_RCVDAV_IRQ | HIRQ_HXFRDN_IRQ) ) { + if ( hirq & HIRQ_RCVDAV_IRQ ) { + uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; + hcd_ep_t *ep = &_hcd_data.ep[ep_num][1]; + uint8_t xact_len; + + // RCVDAV_IRQ can trigger 2 times (dual buffered) + while ( hirq & HIRQ_RCVDAV_IRQ ) { + uint8_t rcvbc = reg_read(RCVBC_ADDR); + xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len); + if ( xact_len ) { + fifo_read(ep->buf, xact_len); + ep->buf += xact_len; + ep->xferred_len += xact_len; + } + + // ack RCVDVAV IRQ + reg_write(HIRQ_ADDR, HIRQ_RCVDAV_IRQ); + hirq = reg_read(HIRQ_ADDR); + } + + if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) { + ep->xfer_complete = 1; + } + } + + if ( hirq & HIRQ_HXFRDN_IRQ ) { + reg_write(HIRQ_ADDR, HIRQ_HXFRDN_IRQ); + handle_xfer_done(rhport); + } + + hirq = reg_read(HIRQ_ADDR); } - // clear all interrupt except SNDBAV_IRQ and RCVDAV_IRQ must be clear after pulling data from FIFO - hirq &= ~ (HIRQ_SNDBAV_IRQ | HIRQ_RCVDAV_IRQ); + // clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing + hirq &= ~HIRQ_SNDBAV_IRQ; if ( hirq ) { reg_write(HIRQ_ADDR, hirq); } -- cgit v1.3.1 From 344932d27e1f65932ce922b639370ecc4fff2153 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 24 Aug 2023 16:27:32 +0700 Subject: add tuh_max3421e_int_api(), retry control if received NAK --- src/portable/analog/max3421/hcd_max3421.c | 60 ++++++++++++++++++++----------- 1 file changed, 40 insertions(+), 20 deletions(-) (limited to 'src') diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 514cf34b7..b4f75e392 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -28,6 +28,7 @@ #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 +#include #include "host/hcd.h" //--------------------------------------------------------------------+ @@ -164,11 +165,15 @@ enum { //--------------------------------------------------------------------+ typedef struct { - uint8_t xfer_type; - uint8_t data_toggle; - uint8_t xfer_complete; uint16_t packet_size; + struct TU_ATTR_PACKED { + uint8_t is_iso : 1; + uint8_t data_toggle : 1; + uint8_t xfer_queued : 1; + uint8_t xfer_complete : 1; + }; + uint16_t total_len; uint16_t xferred_len; uint8_t* buf; @@ -176,6 +181,7 @@ typedef struct { typedef struct { bool inited; + atomic_bool busy; // busy transferring // cached register uint8_t sndbc; @@ -198,8 +204,7 @@ static max2341_data_t _hcd_data; void tuh_max3421_spi_cs_api(uint8_t rhport, bool active); bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len); - -//void tuh_max3421e_int_enable(uint8_t rhport, bool enabled); +void tuh_max3421e_int_api(uint8_t rhport, bool enabled); //--------------------------------------------------------------------+ // @@ -348,6 +353,9 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) { bool hcd_init(uint8_t rhport) { (void) rhport; + TU_LOG2_INT(sizeof(hcd_ep_t)); + TU_LOG2_INT(sizeof(max2341_data_t)); + tu_memclr(&_hcd_data, sizeof(_hcd_data)); // full duplex, interrupt negative edge @@ -382,12 +390,12 @@ bool hcd_init(uint8_t rhport) { // Enable USB interrupt void hcd_int_enable (uint8_t rhport) { - (void) rhport; + tuh_max3421e_int_api(rhport, true); } // Disable USB interrupt void hcd_int_disable(uint8_t rhport) { - (void) rhport; + tuh_max3421e_int_api(rhport, false); } // Get frame number (1ms) @@ -447,17 +455,20 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { (void) rhport; (void) dev_addr; - (void) ep_desc; uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress); uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress); - _hcd_data.ep[ep_num][ep_dir].packet_size = tu_edpt_packet_size(ep_desc); + hcd_ep_t * ep = &_hcd_data.ep[ep_num][ep_dir]; + + ep->packet_size = tu_edpt_packet_size(ep_desc); if (ep_desc->bEndpointAddress == 0) { - _hcd_data.ep[ep_num][1].packet_size = tu_edpt_packet_size(ep_desc); + _hcd_data.ep[0][1].packet_size = ep->packet_size; } + ep->is_iso = (TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer) ? 1 : 0; + return true; } @@ -474,11 +485,13 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf ep->total_len = buflen; ep->xferred_len = 0; ep->xfer_complete = 0; + ep->xfer_queued = 1; peraddr_write(daddr); uint8_t hctl = 0; uint8_t hxfr = ep_num; + if ( ep_num == 0 ) { ep->data_toggle = 1; if ( buffer == NULL || buflen == 0 ) { @@ -488,7 +501,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf hxfr_write(hxfr); return true; } - } else if ( ep->xfer_type == TUSB_XFER_ISOCHRONOUS ) { + } else if ( ep->is_iso ) { hxfr |= HXFR_ISO; } @@ -551,11 +564,13 @@ static void handle_xfer_done(uint8_t rhport) { (void) rhport; uint8_t const hrsl = reg_read(HRSL_ADDR); - uint8_t const result = hrsl & HRSL_RESULT_MASK; + uint8_t const hresult = hrsl & HRSL_RESULT_MASK; + uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; + xfer_result_t xfer_result; - TU_LOG3("HRSL: %02X\r\n", hrsl); - switch(result) { + //TU_LOG3("HRSL: %02X\r\n", hrsl); + switch(hresult) { case HRSL_SUCCESS: xfer_result = XFER_RESULT_SUCCESS; break; @@ -568,21 +583,26 @@ static void handle_xfer_done(uint8_t rhport) { // occurred when initialized without any pending transfer. Skip for now return; + case HRSL_NAK: + // NAK on control, retry immediately + if (ep_num == 0) hxfr_write(_hcd_data.hxfr); + return; + default: xfer_result = XFER_RESULT_FAILED; break; } - uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; - uint8_t const xfer_type = _hcd_data.hxfr & 0xf0; + uint8_t const hxfr_type = _hcd_data.hxfr & 0xf0; - if ( (xfer_type & HXFR_SETUP) || (xfer_type & HXFR_OUT_NIN) ) { + if ( (hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN) ) { // SETUP or OUT transfer hcd_ep_t *ep = &_hcd_data.ep[ep_num][0]; uint8_t xact_len; - if (xfer_type & HXFR_SETUP) { + + if ( hxfr_type & HXFR_SETUP) { xact_len = 8; - } else if ( xfer_type & HXFR_HS ) { + } else if ( hxfr_type & HXFR_HS ) { xact_len = 0; } else { xact_len = _hcd_data.sndbc; @@ -599,7 +619,7 @@ static void handle_xfer_done(uint8_t rhport) { // IN transfer: fifo data is already received in RCVDAV IRQ hcd_ep_t *ep = &_hcd_data.ep[ep_num][1]; - if ( xfer_type & HXFR_HS ) { + if ( hxfr_type & HXFR_HS ) { ep->xfer_complete = 1; } -- cgit v1.3.1 From e6cf125e537125fc7303afc7d0703a3de6b8b334 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 24 Aug 2023 16:46:20 +0700 Subject: save data toggle, always retry NAK. work with msc device --- src/portable/analog/max3421/hcd_max3421.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index b4f75e392..9579409c5 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -492,7 +492,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf uint8_t hctl = 0; uint8_t hxfr = ep_num; - if ( ep_num == 0 ) { + if ( ep->is_iso ) { + hxfr |= HXFR_ISO; + } else if ( ep_num == 0 ) { ep->data_toggle = 1; if ( buffer == NULL || buflen == 0 ) { // ZLP for ACK stage, use HS @@ -501,8 +503,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf hxfr_write(hxfr); return true; } - } else if ( ep->is_iso ) { - hxfr |= HXFR_ISO; } if ( 0 == ep_dir ) { @@ -511,7 +511,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size); fifo_write(SNDFIFO_ADDR, buffer, xact_len); - reg_write(SNDBC_ADDR, xact_len); + sndbc_write(xact_len); hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0); hxfr |= HXFR_OUT_NIN; @@ -585,7 +585,10 @@ static void handle_xfer_done(uint8_t rhport) { case HRSL_NAK: // NAK on control, retry immediately - if (ep_num == 0) hxfr_write(_hcd_data.hxfr); + //if (ep_num == 0) + { + hxfr_write(_hcd_data.hxfr); + } return; default: @@ -609,8 +612,14 @@ static void handle_xfer_done(uint8_t rhport) { } ep->xferred_len += xact_len; + ep->buf += xact_len; if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) { + if ( ep_num ) { + // save data toggle for non-control + ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; + } + hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true); }else { // more to transfer @@ -625,6 +634,11 @@ static void handle_xfer_done(uint8_t rhport) { // short packet or all bytes transferred if ( ep->xfer_complete ) { + if ( ep_num ) { + // save data toggle for non-control + ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; + } + hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true); }else { // more to transfer -- cgit v1.3.1 From f5ebc1700f4bde1cc166bf5f3d8eb69d8832722a Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 25 Aug 2023 12:12:44 +0700 Subject: add spi lock with interrupt enable/disable --- src/portable/analog/max3421/hcd_max3421.c | 176 +++++++++++++++--------------- 1 file changed, 91 insertions(+), 85 deletions(-) (limited to 'src') diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 9579409c5..0144deca6 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -180,7 +180,6 @@ typedef struct { } hcd_ep_t; typedef struct { - bool inited; atomic_bool busy; // busy transferring // cached register @@ -194,6 +193,8 @@ typedef struct { volatile uint16_t frame_count; hcd_ep_t ep[8][2]; + + OSAL_MUTEX_DEF(spi_mutex); } max2341_data_t; static max2341_data_t _hcd_data; @@ -210,86 +211,106 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled); // //--------------------------------------------------------------------+ -static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) { - uint8_t const rhport = 0; +static void max3421_spi_lock(uint8_t rhport, bool in_isr) { + // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr + if (!in_isr) { + tuh_max3421e_int_api(rhport, false); + } + + // assert CS + tuh_max3421_spi_cs_api(rhport, true); +} + +static void max3421_spi_unlock(uint8_t rhport, bool in_isr) { + // de-assert CS + tuh_max3421_spi_cs_api(rhport, false); + + // mutex unlock and re-enable interrupt + if (!in_isr) { + tuh_max3421e_int_api(rhport, true); + } +} + +static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint16_t len, bool in_isr) { uint8_t hirq; reg |= CMDBYTE_WRITE; - tuh_max3421_spi_cs_api(rhport, true); + max3421_spi_lock(rhport, in_isr); tuh_max3421_spi_xfer_api(rhport, ®, 1, &hirq, 1); _hcd_data.hirq = hirq; tuh_max3421_spi_xfer_api(rhport, buffer, len, NULL, 0); - tuh_max3421_spi_cs_api(rhport, false); + max3421_spi_unlock(rhport, in_isr); } -static void fifo_read(uint8_t * buffer, uint16_t len) { - uint8_t const rhport = 0; +static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) { uint8_t hirq; uint8_t const reg = RCVVFIFO_ADDR; - tuh_max3421_spi_cs_api(rhport, true); + max3421_spi_lock(rhport, in_isr); tuh_max3421_spi_xfer_api(rhport, ®, 1, &hirq, 0); _hcd_data.hirq = hirq; tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len); - tuh_max3421_spi_cs_api(rhport, false); + max3421_spi_unlock(rhport, in_isr); } -static void reg_write(uint8_t reg, uint8_t data) { - uint8_t const rhport = 0; +static void reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr) { uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data}; uint8_t rx_buf[2] = {0, 0}; - tuh_max3421_spi_cs_api(rhport, true); + max3421_spi_lock(rhport, in_isr); + tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2); - tuh_max3421_spi_cs_api(rhport, false); + + max3421_spi_unlock(rhport, in_isr); // HIRQ register since we are in full-duplex mode _hcd_data.hirq = rx_buf[0]; } -static uint8_t reg_read(uint8_t reg) { - uint8_t const rhport = 0; +static uint8_t reg_read(uint8_t rhport, uint8_t reg, bool in_isr) { uint8_t tx_buf[2] = {reg, 0}; uint8_t rx_buf[2] = {0, 0}; - tuh_max3421_spi_cs_api(rhport, true); + max3421_spi_lock(rhport, in_isr); + bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2); - tuh_max3421_spi_cs_api(rhport, false); + + max3421_spi_unlock(rhport, in_isr); _hcd_data.hirq = rx_buf[0]; return ret ? rx_buf[1] : 0; } -static inline void hien_write(uint8_t data) { +static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) { _hcd_data.hien = data; - reg_write(HIEN_ADDR, data); + reg_write(rhport, HIEN_ADDR, data, in_isr); } -static inline void mode_write(uint8_t data) { +static inline void mode_write(uint8_t rhport, uint8_t data, bool in_isr) { _hcd_data.mode = data; - reg_write(MODE_ADDR, data); + reg_write(rhport, MODE_ADDR, data, in_isr); } -static inline void peraddr_write(uint8_t data) { +static inline void peraddr_write(uint8_t rhport, uint8_t data, bool in_isr) { if ( _hcd_data.peraddr == data ) return; // no need to change address _hcd_data.peraddr = data; - reg_write(PERADDR_ADDR, data); + reg_write(rhport, PERADDR_ADDR, data, in_isr); } -static inline void hxfr_write(uint8_t data) { +static inline void hxfr_write(uint8_t rhport, uint8_t data, bool in_isr) { _hcd_data.hxfr = data; - reg_write(HXFR_ADDR, data); + reg_write(rhport, HXFR_ADDR, data, in_isr); } -static inline void sndbc_write(uint8_t data) { +static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) { _hcd_data.sndbc = data; - reg_write(SNDBC_ADDR, data); + reg_write(rhport, SNDBC_ADDR, data, in_isr); } @@ -307,9 +328,7 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { } tusb_speed_t handle_connect_irq(uint8_t rhport) { - (void) rhport; - - uint8_t const hrsl = reg_read(HRSL_ADDR); + uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true); uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS); tusb_speed_t speed; @@ -328,7 +347,7 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) { default: { // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State) - uint8_t const mode = reg_read(MODE_ADDR); + uint8_t const mode = reg_read(rhport, MODE_ADDR, true); uint8_t const ls_bit = mode & MODE_LOWSPEED; if ( (ls_bit && (jk == HRSL_JSTATUS)) || (!ls_bit && (jk == HRSL_KSTATUS)) ) { @@ -344,7 +363,7 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) { } } - mode_write(new_mode); + mode_write(rhport, new_mode, true); TU_LOG2_INT(speed); return speed; } @@ -358,32 +377,32 @@ bool hcd_init(uint8_t rhport) { tu_memclr(&_hcd_data, sizeof(_hcd_data)); + hcd_int_disable(rhport); + // full duplex, interrupt negative edge - reg_write(PINCTL_ADDR, PINCTL_FDUPSPI); + reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false); // reset - reg_write(USBCTL_ADDR, USBCTL_CHIPRES); - reg_write(USBCTL_ADDR, 0); - while( !(reg_read(USBIRQ_ADDR) & USBIRQ_OSCOK_IRQ) ) { + reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false); + reg_write(rhport, USBCTL_ADDR, 0, false); + while( !(reg_read(rhport, USBIRQ_ADDR, false) & USBIRQ_OSCOK_IRQ) ) { // wait for oscillator to stabilize } // Mode: Host and DP/DM pull down - mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST); + mode_write(rhport, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST, false); // frame reset & bus reset, this will trigger CONDET IRQ if device is already connected - reg_write(HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST); + reg_write(rhport, HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST, false); // clear all previously pending IRQ - reg_write(HIRQ_ADDR, 0xff); - - _hcd_data.inited = true; + reg_write(rhport, HIRQ_ADDR, 0xff, false); // Enable IRQ - hien_write(DEFAULT_HIEN); + hien_write(rhport, DEFAULT_HIEN, false); // Enable Interrupt pin - reg_write(CPUCTL_ADDR, CPUCTL_IE); + reg_write(rhport, CPUCTL_ADDR, CPUCTL_IE, false); return true; } @@ -417,22 +436,20 @@ bool hcd_port_connect_status(uint8_t rhport) { // Reset USB bus on the port. Return immediately, bus reset sequence may not be complete. // Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence. void hcd_port_reset(uint8_t rhport) { - (void) rhport; // Bus reset will also trigger CONDET IRQ, disable it uint8_t const hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ; - hien_write(hien); + hien_write(rhport, hien, false); - reg_write(HCTL_ADDR, HCTL_BUSRST); + reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, false); } // Complete bus reset sequence, may be required by some controllers void hcd_port_reset_end(uint8_t rhport) { - (void) rhport; - reg_write(HCTL_ADDR, 0); + reg_write(rhport, HCTL_ADDR, 0, false); // Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset - reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ); - hien_write(DEFAULT_HIEN); + reg_write(rhport, HIRQ_ADDR, HIRQ_CONDET_IRQ, false); + hien_write(rhport, DEFAULT_HIEN, false); } // Get port link speed @@ -487,7 +504,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf ep->xfer_complete = 0; ep->xfer_queued = 1; - peraddr_write(daddr); + peraddr_write(rhport, daddr, false); uint8_t hctl = 0; uint8_t hxfr = ep_num; @@ -500,7 +517,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf // ZLP for ACK stage, use HS hxfr |= HXFR_HS; hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN); - hxfr_write(hxfr); + hxfr_write(rhport, hxfr, false); return true; } } @@ -510,8 +527,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ); uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size); - fifo_write(SNDFIFO_ADDR, buffer, xact_len); - sndbc_write(xact_len); + fifo_write(rhport, SNDFIFO_ADDR, buffer, xact_len, false); + sndbc_write(rhport, xact_len, false); hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0); hxfr |= HXFR_OUT_NIN; @@ -520,8 +537,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0); } - reg_write(HCTL_ADDR, hctl); - hxfr_write(hxfr); + reg_write(rhport, HCTL_ADDR, hctl, false); + hxfr_write(rhport, hxfr, false); return true; } @@ -544,9 +561,9 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8] ep->total_len = 8; ep->xferred_len = 0; - peraddr_write(daddr); - fifo_write(SUDFIFO_ADDR, setup_packet, 8); - hxfr_write(HXFR_SETUP); + peraddr_write(rhport, daddr, false); + fifo_write(rhport, SUDFIFO_ADDR, setup_packet, 8, false); + hxfr_write(rhport, HXFR_SETUP, false); return true; } @@ -561,9 +578,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { } static void handle_xfer_done(uint8_t rhport) { - (void) rhport; - - uint8_t const hrsl = reg_read(HRSL_ADDR); + uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true); uint8_t const hresult = hrsl & HRSL_RESULT_MASK; uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; @@ -587,7 +602,7 @@ static void handle_xfer_done(uint8_t rhport) { // NAK on control, retry immediately //if (ep_num == 0) { - hxfr_write(_hcd_data.hxfr); + hxfr_write(rhport, _hcd_data.hxfr, true); } return; @@ -615,11 +630,8 @@ static void handle_xfer_done(uint8_t rhport) { ep->buf += xact_len; if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) { - if ( ep_num ) { - // save data toggle for non-control - ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; - } - + // save data toggle + ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true); }else { // more to transfer @@ -634,15 +646,12 @@ static void handle_xfer_done(uint8_t rhport) { // short packet or all bytes transferred if ( ep->xfer_complete ) { - if ( ep_num ) { - // save data toggle for non-control - ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; - } - + // save data toggle + ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true); }else { // more to transfer - hxfr_write(_hcd_data.hxfr); + hxfr_write(rhport, _hcd_data.hxfr, true); } } } @@ -669,10 +678,7 @@ void print_hirq(uint8_t hirq) { // Interrupt Handler void hcd_int_handler(uint8_t rhport) { - // not initialized, do nothing - if ( !_hcd_data.inited ) return; - - uint8_t hirq = reg_read(HIRQ_ADDR) & _hcd_data.hien; + uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true) & _hcd_data.hien; if (!hirq) return; // print_hirq(hirq); @@ -701,17 +707,17 @@ void hcd_int_handler(uint8_t rhport) { // RCVDAV_IRQ can trigger 2 times (dual buffered) while ( hirq & HIRQ_RCVDAV_IRQ ) { - uint8_t rcvbc = reg_read(RCVBC_ADDR); + uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, true); xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len); if ( xact_len ) { - fifo_read(ep->buf, xact_len); + fifo_read(rhport, ep->buf, xact_len, true); ep->buf += xact_len; ep->xferred_len += xact_len; } // ack RCVDVAV IRQ - reg_write(HIRQ_ADDR, HIRQ_RCVDAV_IRQ); - hirq = reg_read(HIRQ_ADDR); + reg_write(rhport, HIRQ_ADDR, HIRQ_RCVDAV_IRQ, true); + hirq = reg_read(rhport, HIRQ_ADDR, true); } if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) { @@ -720,17 +726,17 @@ void hcd_int_handler(uint8_t rhport) { } if ( hirq & HIRQ_HXFRDN_IRQ ) { - reg_write(HIRQ_ADDR, HIRQ_HXFRDN_IRQ); + reg_write(rhport, HIRQ_ADDR, HIRQ_HXFRDN_IRQ, true); handle_xfer_done(rhport); } - hirq = reg_read(HIRQ_ADDR); + hirq = reg_read(rhport, HIRQ_ADDR, true); } // clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing hirq &= ~HIRQ_SNDBAV_IRQ; if ( hirq ) { - reg_write(HIRQ_ADDR, hirq); + reg_write(rhport, HIRQ_ADDR, hirq, true); } } -- cgit v1.3.1 From 09ceaa6cf37d29e605495716fc2497ed5228a37f Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 25 Aug 2023 13:18:47 +0700 Subject: add osal mutex for spi --- src/portable/analog/max3421/hcd_max3421.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 0144deca6..09845ffe4 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -194,7 +194,10 @@ typedef struct { hcd_ep_t ep[8][2]; - OSAL_MUTEX_DEF(spi_mutex); + OSAL_MUTEX_DEF(spi_mutexdef); +#if OSAL_MUTEX_REQUIRED + osal_mutex_t spi_mutex; +#endif } max2341_data_t; static max2341_data_t _hcd_data; @@ -215,6 +218,7 @@ static void max3421_spi_lock(uint8_t rhport, bool in_isr) { // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr if (!in_isr) { tuh_max3421e_int_api(rhport, false); + (void) osal_mutex_lock(_hcd_data.spi_mutex, OSAL_TIMEOUT_WAIT_FOREVER); } // assert CS @@ -228,6 +232,7 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) { // mutex unlock and re-enable interrupt if (!in_isr) { tuh_max3421e_int_api(rhport, true); + (void) osal_mutex_unlock(_hcd_data.spi_mutex); } } @@ -372,12 +377,16 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) { bool hcd_init(uint8_t rhport) { (void) rhport; + hcd_int_disable(rhport); + TU_LOG2_INT(sizeof(hcd_ep_t)); TU_LOG2_INT(sizeof(max2341_data_t)); tu_memclr(&_hcd_data, sizeof(_hcd_data)); - hcd_int_disable(rhport); +#if OSAL_MUTEX_REQUIRED + _hcd_data.spi_mutex = osal_mutex_create(&_hcd_data.spi_mutexdef); +#endif // full duplex, interrupt negative edge reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false); -- cgit v1.3.1 From ecf2f910424b53fecc3ca82ae410f054518cc752 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 25 Aug 2023 16:36:28 +0700 Subject: use endpoint pool for more flexible multiple devices support --- src/portable/analog/max3421/hcd_max3421.c | 178 ++++++++++++++++++++---------- 1 file changed, 121 insertions(+), 57 deletions(-) (limited to 'src') diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 09845ffe4..b0325f240 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -165,22 +165,26 @@ enum { //--------------------------------------------------------------------+ typedef struct { - uint16_t packet_size; - struct TU_ATTR_PACKED { + uint8_t ep_dir : 1; uint8_t is_iso : 1; uint8_t data_toggle : 1; - uint8_t xfer_queued : 1; + uint8_t xfer_pending : 1; uint8_t xfer_complete : 1; }; + struct TU_ATTR_PACKED { + uint8_t daddr : 4; + uint8_t ep_num : 4; + }; + uint16_t packet_size; uint16_t total_len; uint16_t xferred_len; uint8_t* buf; -} hcd_ep_t; +} max3421_ep_t; typedef struct { - atomic_bool busy; // busy transferring + atomic_flag busy; // busy transferring // cached register uint8_t sndbc; @@ -192,15 +196,16 @@ typedef struct { volatile uint16_t frame_count; - hcd_ep_t ep[8][2]; + max3421_ep_t ep0_addr0; // control endpoint for addr0 + max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; OSAL_MUTEX_DEF(spi_mutexdef); #if OSAL_MUTEX_REQUIRED osal_mutex_t spi_mutex; #endif -} max2341_data_t; +} max3421_data_t; -static max2341_data_t _hcd_data; +static max3421_data_t _hcd_data; //--------------------------------------------------------------------+ // API: SPI transfer with MAX3421E, must be implemented by application @@ -211,7 +216,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_ void tuh_max3421e_int_api(uint8_t rhport, bool enabled); //--------------------------------------------------------------------+ -// +// SPI Helper //--------------------------------------------------------------------+ static void max3421_spi_lock(uint8_t rhport, bool in_isr) { @@ -318,6 +323,44 @@ static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) { reg_write(rhport, SNDBC_ADDR, data, in_isr); } +//--------------------------------------------------------------------+ +// Endpoint helper +//--------------------------------------------------------------------+ + +static max3421_ep_t* find_ep_not_addr0(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) { + for(size_t i=0; idaddr && ep_num == ep->ep_num && (ep_dir == ep->ep_dir || ep_num == 0) ) { + return ep; + } + } + + return NULL; +} + +// daddr = 0 and ep_num = 0 means find a free (allocate) endpoint +TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * allocate_ep(void) { + return find_ep_not_addr0(0, 0, 0); +} + +// free all endpoints belong to device address +static void free_ep(uint8_t daddr) { + for (size_t i=0; idaddr == daddr) { + tu_memclr(ep, sizeof(max3421_ep_t)); + } + } +} + +TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) { + if (daddr == 0 && ep_num == 0) { + return &_hcd_data.ep0_addr0; + }else{ + return find_ep_not_addr0(daddr, ep_num, ep_dir); + } +} //--------------------------------------------------------------------+ // Controller API @@ -379,8 +422,8 @@ bool hcd_init(uint8_t rhport) { hcd_int_disable(rhport); - TU_LOG2_INT(sizeof(hcd_ep_t)); - TU_LOG2_INT(sizeof(max2341_data_t)); + TU_LOG2_INT(sizeof(max3421_ep_t)); + TU_LOG2_INT(sizeof(max3421_data_t)); tu_memclr(&_hcd_data, sizeof(_hcd_data)); @@ -478,22 +521,29 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { //--------------------------------------------------------------------+ // Open an endpoint -bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { +bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc) { (void) rhport; - (void) dev_addr; + (void) daddr; uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress); uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress); - hcd_ep_t * ep = &_hcd_data.ep[ep_num][ep_dir]; - - ep->packet_size = tu_edpt_packet_size(ep_desc); + max3421_ep_t * ep; + if (daddr == 0 && ep_num == 0) { + ep = &_hcd_data.ep0_addr0; + }else { + ep = allocate_ep(); + TU_ASSERT(ep); + ep->daddr = daddr; + ep->ep_num = ep_num; + ep->ep_dir = ep_dir; + } - if (ep_desc->bEndpointAddress == 0) { - _hcd_data.ep[0][1].packet_size = ep->packet_size; + if ( TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer ) { + ep->is_iso = 1; } - ep->is_iso = (TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer) ? 1 : 0; + ep->packet_size = tu_edpt_packet_size(ep_desc); return true; } @@ -505,49 +555,54 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf uint8_t const ep_num = tu_edpt_number(ep_addr); uint8_t const ep_dir = tu_edpt_dir(ep_addr); - hcd_ep_t* ep = &_hcd_data.ep[ep_num][ep_dir]; + max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir); + TU_ASSERT(ep); ep->buf = buffer; ep->total_len = buflen; ep->xferred_len = 0; ep->xfer_complete = 0; - ep->xfer_queued = 1; - - peraddr_write(rhport, daddr, false); - - uint8_t hctl = 0; - uint8_t hxfr = ep_num; - - if ( ep->is_iso ) { - hxfr |= HXFR_ISO; - } else if ( ep_num == 0 ) { - ep->data_toggle = 1; - if ( buffer == NULL || buflen == 0 ) { - // ZLP for ACK stage, use HS - hxfr |= HXFR_HS; - hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN); - hxfr_write(rhport, hxfr, false); - return true; + ep->xfer_pending = 1; + + // carry out transfer if not busy +// if ( atomic_flag_test_and_set(&_hcd_data.busy) ) + { + peraddr_write(rhport, daddr, false); + + uint8_t hctl = 0; + uint8_t hxfr = ep_num; + + if ( ep->is_iso ) { + hxfr |= HXFR_ISO; + } else if ( ep_num == 0 ) { + ep->data_toggle = 1; + if ( buffer == NULL || buflen == 0 ) { + // ZLP for ACK stage, use HS + hxfr |= HXFR_HS; + hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN); + hxfr_write(rhport, hxfr, false); + return true; + } } - } - if ( 0 == ep_dir ) { - // Page 12: Programming BULK-OUT Transfers - TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ); + if ( 0 == ep_dir ) { + // Page 12: Programming BULK-OUT Transfers + TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ); - uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size); - fifo_write(rhport, SNDFIFO_ADDR, buffer, xact_len, false); - sndbc_write(rhport, xact_len, false); + uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size); + fifo_write(rhport, SNDFIFO_ADDR, buffer, xact_len, false); + sndbc_write(rhport, xact_len, false); - hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0); - hxfr |= HXFR_OUT_NIN; - } else { - // Page 13: Programming BULK-IN Transfers - hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0); - } + hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0); + hxfr |= HXFR_OUT_NIN; + } else { + // Page 13: Programming BULK-IN Transfers + hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0); + } - reg_write(rhport, HCTL_ADDR, hctl, false); - hxfr_write(rhport, hxfr, false); + reg_write(rhport, HCTL_ADDR, hctl, false); + hxfr_write(rhport, hxfr, false); + } return true; } @@ -566,7 +621,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]) { (void) rhport; - hcd_ep_t* ep = &_hcd_data.ep[0][0]; + max3421_ep_t* ep = find_opened_ep(daddr, 0, 0); ep->total_len = 8; ep->xferred_len = 0; @@ -624,7 +679,7 @@ static void handle_xfer_done(uint8_t rhport) { if ( (hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN) ) { // SETUP or OUT transfer - hcd_ep_t *ep = &_hcd_data.ep[ep_num][0]; + max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 0); uint8_t xact_len; if ( hxfr_type & HXFR_SETUP) { @@ -644,10 +699,15 @@ static void handle_xfer_done(uint8_t rhport) { hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true); }else { // more to transfer + xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); + fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, true); + sndbc_write(rhport, xact_len, true); + + hxfr_write(rhport, _hcd_data.hxfr, true); } } else { // IN transfer: fifo data is already received in RCVDAV IRQ - hcd_ep_t *ep = &_hcd_data.ep[ep_num][1]; + max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1); if ( hxfr_type & HXFR_HS ) { ep->xfer_complete = 1; @@ -702,6 +762,10 @@ void hcd_int_handler(uint8_t rhport) { if (speed == TUSB_SPEED_INVALID) { hcd_event_device_remove(rhport, true); }else { + // FIXME multiple MAX3421 rootdevice address is not 1 + uint8_t const daddr = 1; + free_ep(daddr); + hcd_event_device_attach(rhport, true); } } @@ -710,8 +774,8 @@ void hcd_int_handler(uint8_t rhport) { // not call this handler again. So we need to loop until all IRQ are cleared while ( hirq & (HIRQ_RCVDAV_IRQ | HIRQ_HXFRDN_IRQ) ) { if ( hirq & HIRQ_RCVDAV_IRQ ) { - uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; - hcd_ep_t *ep = &_hcd_data.ep[ep_num][1]; + uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; + max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1); uint8_t xact_len; // RCVDAV_IRQ can trigger 2 times (dual buffered) -- cgit v1.3.1 From ac00b9147298184ca0bd1eadac3a02e7e867085d Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 25 Aug 2023 17:26:57 +0700 Subject: add xact_out(), xact_in() to manage transfer --- src/portable/analog/max3421/hcd_max3421.c | 143 +++++++++++++++++++----------- 1 file changed, 89 insertions(+), 54 deletions(-) (limited to 'src') diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index b0325f240..00b36201c 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -331,7 +331,7 @@ static max3421_ep_t* find_ep_not_addr0(uint8_t daddr, uint8_t ep_num, uint8_t ep for(size_t i=0; idaddr && ep_num == ep->ep_num && (ep_dir == ep->ep_dir || ep_num == 0) ) { + if (daddr == ep->daddr && ep_num == ep->ep_num && (ep_dir == ep->ep_dir || ep_num == 0)) { return ep; } } @@ -362,6 +362,28 @@ TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr, } } +//static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) { +// size_t idx = cur_ep - _hcd_data.ep; +// +// // starting from next endpoint +// for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) { +// max3421_ep_t* ep = &_hcd_data.ep[i]; +// if (ep->xfer_pending) { +// return ep; +// } +// } +// +// // wrap around including current endpoint +// for (size_t i = 0; i <= idx; i++) { +// max3421_ep_t* ep = &_hcd_data.ep[i]; +// if (ep->xfer_pending) { +// return ep; +// } +// } +// +// return NULL; +//} + //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ @@ -548,6 +570,37 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e return true; } +void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { + // Page 12: Programming BULK-OUT Transfers + // TODO double buffered + if (switch_ep) { + peraddr_write(rhport, ep->daddr, in_isr); + + uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0); + reg_write(rhport, HCTL_ADDR, hctl, in_isr); + } + + uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); + fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr); + sndbc_write(rhport, xact_len, in_isr); + + uint8_t const hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0); + hxfr_write(rhport, hxfr, in_isr); +} + +void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { + // Page 13: Programming BULK-IN Transfers + if (switch_ep) { + peraddr_write(rhport, ep->daddr, in_isr); + + uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0); + reg_write(rhport, HCTL_ADDR, hctl, in_isr); + } + + uint8_t const hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0); + hxfr_write(rhport, hxfr, in_isr); +} + // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { (void) rhport; @@ -567,17 +620,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf // carry out transfer if not busy // if ( atomic_flag_test_and_set(&_hcd_data.busy) ) { - peraddr_write(rhport, daddr, false); - - uint8_t hctl = 0; uint8_t hxfr = ep_num; - if ( ep->is_iso ) { - hxfr |= HXFR_ISO; - } else if ( ep_num == 0 ) { + if ( ep_num == 0 ) { ep->data_toggle = 1; if ( buffer == NULL || buflen == 0 ) { // ZLP for ACK stage, use HS + peraddr_write(rhport, daddr, false); + hxfr |= HXFR_HS; hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN); hxfr_write(rhport, hxfr, false); @@ -586,22 +636,11 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf } if ( 0 == ep_dir ) { - // Page 12: Programming BULK-OUT Transfers TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ); - - uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size); - fifo_write(rhport, SNDFIFO_ADDR, buffer, xact_len, false); - sndbc_write(rhport, xact_len, false); - - hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0); - hxfr |= HXFR_OUT_NIN; + xact_out(rhport, ep, true, false); } else { - // Page 13: Programming BULK-IN Transfers - hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0); + xact_in(rhport, ep, true, false); } - - reg_write(rhport, HCTL_ADDR, hctl, false); - hxfr_write(rhport, hxfr, false); } return true; @@ -644,7 +683,12 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { static void handle_xfer_done(uint8_t rhport) { uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true); uint8_t const hresult = hrsl & HRSL_RESULT_MASK; - uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; + + uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; + uint8_t const hxfr_type = _hcd_data.hxfr & 0xf0; + uint8_t const ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1; + + max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, ep_dir); xfer_result_t xfer_result; @@ -663,10 +707,11 @@ static void handle_xfer_done(uint8_t rhport) { return; case HRSL_NAK: - // NAK on control, retry immediately - //if (ep_num == 0) - { + if (ep_num == 0) { + // NAK on control, retry immediately hxfr_write(rhport, _hcd_data.hxfr, true); + }else { + // NAK on non-control, find next pending to switch } return; @@ -675,16 +720,28 @@ static void handle_xfer_done(uint8_t rhport) { break; } - uint8_t const hxfr_type = _hcd_data.hxfr & 0xf0; + if (ep_dir) { + // IN transfer: fifo data is already received in RCVDAV IRQ + if ( hxfr_type & HXFR_HS ) { + ep->xfer_complete = 1; + } - if ( (hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN) ) { + // short packet or all bytes transferred + if ( ep->xfer_complete ) { + // save data toggle + ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; + hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true); + }else { + // more to transfer + hxfr_write(rhport, _hcd_data.hxfr, true); + } + } else { // SETUP or OUT transfer - max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 0); uint8_t xact_len; - if ( hxfr_type & HXFR_SETUP) { + if (hxfr_type & HXFR_SETUP) { xact_len = 8; - } else if ( hxfr_type & HXFR_HS ) { + } else if (hxfr_type & HXFR_HS) { xact_len = 0; } else { xact_len = _hcd_data.sndbc; @@ -693,34 +750,12 @@ static void handle_xfer_done(uint8_t rhport) { ep->xferred_len += xact_len; ep->buf += xact_len; - if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) { + if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) { // save data toggle ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true); - }else { - // more to transfer - xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); - fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, true); - sndbc_write(rhport, xact_len, true); - - hxfr_write(rhport, _hcd_data.hxfr, true); - } - } else { - // IN transfer: fifo data is already received in RCVDAV IRQ - max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1); - - if ( hxfr_type & HXFR_HS ) { - ep->xfer_complete = 1; - } - - // short packet or all bytes transferred - if ( ep->xfer_complete ) { - // save data toggle - ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; - hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true); - }else { - // more to transfer - hxfr_write(rhport, _hcd_data.hxfr, true); + } else { + xact_out(rhport, ep, false, true); } } } -- cgit v1.3.1 From cd7464a8847db5efa14f568bdf8746d898fc7eb4 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 25 Aug 2023 17:37:09 +0700 Subject: try next endpoint when received NAK --- src/portable/analog/max3421/hcd_max3421.c | 58 ++++++++++++++++++++----------- 1 file changed, 37 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 00b36201c..e546f99ce 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -362,27 +362,27 @@ TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr, } } -//static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) { -// size_t idx = cur_ep - _hcd_data.ep; -// -// // starting from next endpoint -// for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) { -// max3421_ep_t* ep = &_hcd_data.ep[i]; -// if (ep->xfer_pending) { -// return ep; -// } -// } -// -// // wrap around including current endpoint -// for (size_t i = 0; i <= idx; i++) { -// max3421_ep_t* ep = &_hcd_data.ep[i]; -// if (ep->xfer_pending) { -// return ep; -// } -// } -// -// return NULL; -//} +static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) { + size_t idx = cur_ep - _hcd_data.ep; + + // starting from next endpoint + for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) { + max3421_ep_t* ep = &_hcd_data.ep[i]; + if (ep->xfer_pending) { + return ep; + } + } + + // wrap around including current endpoint + for (size_t i = 0; i <= idx; i++) { + max3421_ep_t* ep = &_hcd_data.ep[i]; + if (ep->xfer_pending) { + return ep; + } + } + + return NULL; +} //--------------------------------------------------------------------+ // Controller API @@ -443,6 +443,7 @@ bool hcd_init(uint8_t rhport) { (void) rhport; hcd_int_disable(rhport); + tuh_max3421_spi_cs_api(rhport, false); TU_LOG2_INT(sizeof(max3421_ep_t)); TU_LOG2_INT(sizeof(max3421_data_t)); @@ -689,6 +690,7 @@ static void handle_xfer_done(uint8_t rhport) { uint8_t const ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1; max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, ep_dir); + TU_ASSERT(ep, ); xfer_result_t xfer_result; @@ -712,6 +714,20 @@ static void handle_xfer_done(uint8_t rhport) { hxfr_write(rhport, _hcd_data.hxfr, true); }else { // NAK on non-control, find next pending to switch + max3421_ep_t *next_ep = find_next_pending_ep(ep); + TU_ASSERT(next_ep, ); + + if (ep == next_ep) { + // only one pending, retry immediately + hxfr_write(rhport, _hcd_data.hxfr, true); + }else { + // switch to next pending TODO could have issue with double buffered if not clear previously out data + if ( ep_dir ) { + xact_in(rhport, next_ep, true, true); + } else { + xact_out(rhport, next_ep, true, true); + } + } } return; -- cgit v1.3.1 From 502b1bdda62f0f207d9a51daf134574e455f3aa2 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 27 Aug 2023 23:45:34 +0700 Subject: more update to transaction --- examples/host/cdc_msc_hid/src/tusb_config.h | 9 ++-- examples/host/msc_file_explorer/src/tusb_config.h | 10 +++-- src/common/tusb_mcu.h | 12 ++++++ src/host/hcd.h | 4 +- src/host/usbh.c | 1 + src/portable/analog/max3421/hcd_max3421.c | 51 +++++++++++++++-------- 6 files changed, 62 insertions(+), 25 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index abb75f068..7d621d466 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -35,9 +35,12 @@ //--------------------------------------------------------------------+ #if CFG_TUSB_MCU == OPT_MCU_RP2040 -// change to 1 if using pico-pio-usb as host controller for raspberry rp2040 -#define CFG_TUH_RPI_PIO_USB 0 -#define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_USB + // change to 1 if using pico-pio-usb as host controller for raspberry rp2040 + #define CFG_TUH_RPI_PIO_USB 0 + #define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_USB +#elif CFG_TUSB_MCU == OPT_MCU_NRF5X + // Use external USB controller (via SPI) MAX3421E (aka usb host shield) + #define CFG_TUH_MAX3421 1 #endif // RHPort number used for host can be defined by board.mk, default to port 0 diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h index 1e0d067bf..bb2fd4cf5 100644 --- a/examples/host/msc_file_explorer/src/tusb_config.h +++ b/examples/host/msc_file_explorer/src/tusb_config.h @@ -35,11 +35,15 @@ //--------------------------------------------------------------------+ #if CFG_TUSB_MCU == OPT_MCU_RP2040 -// change to 1 if using pico-pio-usb as host controller for raspberry rp2040 -#define CFG_TUH_RPI_PIO_USB 0 -#define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_USB + // change to 1 if using pico-pio-usb as host controller for raspberry rp2040 + #define CFG_TUH_RPI_PIO_USB 0 + #define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_US +#elif CFG_TUSB_MCU == OPT_MCU_NRF5X + // Use external USB controller (via SPI) MAX3421E (aka usb host shield) + #define CFG_TUH_MAX3421 1 #endif + // RHPort number used for host can be defined by board.mk, default to port 0 #ifndef BOARD_TUH_RHPORT #define BOARD_TUH_RHPORT 0 diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 35f94efbc..21939df7c 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -385,6 +385,18 @@ #define TUP_RHPORT_HIGHSPEED 1 #endif + +//--------------------------------------------------------------------+ +// External USB controller +//--------------------------------------------------------------------+ + +#if defined(CFG_TUH_MAX3421) & CFG_TUH_MAX3421 + #ifndef CFG_TUH_MAX3421_ENDPOINT_TOTAL + #define CFG_TUH_MAX3421_ENDPOINT_TOTAL (8 + 4*(CFG_TUH_DEVICE_MAX-1)) + #endif +#endif + + //--------------------------------------------------------------------+ // Default Values //--------------------------------------------------------------------+ diff --git a/src/host/hcd.h b/src/host/hcd.h index 1f01a1a2f..e25b20ea3 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -39,7 +39,7 @@ // Configuration //--------------------------------------------------------------------+ -// Max number of endpoints per device +// Max number of endpoints pair per device // TODO optimize memory usage #ifndef CFG_TUH_ENDPOINT_MAX #define CFG_TUH_ENDPOINT_MAX 16 @@ -167,7 +167,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr); //--------------------------------------------------------------------+ // Open an endpoint -bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc); +bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc); // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen); diff --git a/src/host/usbh.c b/src/host/usbh.c index 7a09f5b6e..12a7f5839 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -919,6 +919,7 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) switch (event->event_id) { // case HCD_EVENT_DEVICE_REMOVE: +// // FIXME device remove from a hub need an HCD API for hcd to free up endpoint // // mark device as removing to prevent further xfer before the event is processed in usbh task // break; diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index e546f99ce..574cca788 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -582,6 +582,7 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { } uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); + TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ, ); fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr); sndbc_write(rhport, xact_len, in_isr); @@ -602,6 +603,28 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { hxfr_write(rhport, hxfr, in_isr); } +TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { + if (ep->ep_dir) { + xact_in(rhport, ep, switch_ep, in_isr); + }else { + xact_out(rhport, ep, switch_ep, in_isr); + } +} + +void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t data_toggle) { + (void) rhport; + (void) result; + ep->xfer_pending = 0; + ep->data_toggle = data_toggle; + //uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir); + //hcd_event_xfer_complete(rhport, ep_addr, ep->xferred_len, result, true); + +// max3421_ep_t *next_ep = find_next_pending_ep(ep); +// if (next_ep) { +// xact_inout(rhport, next_ep, true, true); +// } +} + // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { (void) rhport; @@ -612,6 +635,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir); TU_ASSERT(ep); + // control transfer can switch direction + ep->ep_dir = ep_dir; + ep->buf = buffer; ep->total_len = buflen; ep->xferred_len = 0; @@ -636,12 +662,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf } } - if ( 0 == ep_dir ) { - TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ); - xact_out(rhport, ep, true, false); - } else { - xact_in(rhport, ep, true, false); - } + xact_inout(rhport, ep, true, false); } return true; @@ -662,6 +683,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8] (void) rhport; max3421_ep_t* ep = find_opened_ep(daddr, 0, 0); + ep->ep_dir = 0; ep->total_len = 8; ep->xferred_len = 0; @@ -715,18 +737,13 @@ static void handle_xfer_done(uint8_t rhport) { }else { // NAK on non-control, find next pending to switch max3421_ep_t *next_ep = find_next_pending_ep(ep); - TU_ASSERT(next_ep, ); if (ep == next_ep) { // only one pending, retry immediately hxfr_write(rhport, _hcd_data.hxfr, true); - }else { + }else if (next_ep) { // switch to next pending TODO could have issue with double buffered if not clear previously out data - if ( ep_dir ) { - xact_in(rhport, next_ep, true, true); - } else { - xact_out(rhport, next_ep, true, true); - } + xact_inout(rhport, next_ep, true, true); } } return; @@ -744,8 +761,8 @@ static void handle_xfer_done(uint8_t rhport) { // short packet or all bytes transferred if ( ep->xfer_complete ) { - // save data toggle - ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; + uint8_t const dt = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; // save data toggle + xfer_complete_isr(rhport, ep, xfer_result, dt); hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true); }else { // more to transfer @@ -767,8 +784,8 @@ static void handle_xfer_done(uint8_t rhport) { ep->buf += xact_len; if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) { - // save data toggle - ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; + uint8_t const dt = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; // save data toggle + xfer_complete_isr(rhport, ep, xfer_result, dt); hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true); } else { xact_out(rhport, ep, false, true); -- cgit v1.3.1 From b31924e13edff0f29829056152348a9255e72169 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 28 Aug 2023 12:41:44 +0700 Subject: - add xfer_complete_isr() - merge addr0 ep to pool - add control status to xact in/out - use atomic flag busy to ensure only 1 transfer is active at any time - execute pending transfer after one is complete (or clear busy flag) - change rtt mode to block if full --- hw/bsp/family_support.cmake | 1 + src/portable/analog/max3421/hcd_max3421.c | 118 +++++++++++++++--------------- 2 files changed, 62 insertions(+), 57 deletions(-) (limited to 'src') diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 7c89427c0..1cbcfb2a7 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -216,6 +216,7 @@ function(family_configure_common TARGET RTOS) if (NOT TARGET segger_rtt) add_library(segger_rtt STATIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c) target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT) + target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) endif() target_link_libraries(${TARGET} PUBLIC segger_rtt) endif () diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 574cca788..262dbca0f 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -195,9 +195,7 @@ typedef struct { uint8_t hxfr; volatile uint16_t frame_count; - - max3421_ep_t ep0_addr0; // control endpoint for addr0 - max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; + max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; // [0] is reserved for addr0 OSAL_MUTEX_DEF(spi_mutexdef); #if OSAL_MUTEX_REQUIRED @@ -328,7 +326,7 @@ static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) { //--------------------------------------------------------------------+ static max3421_ep_t* find_ep_not_addr0(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) { - for(size_t i=0; idaddr && ep_num == ep->ep_num && (ep_dir == ep->ep_dir || ep_num == 0)) { @@ -344,9 +342,17 @@ TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * allocate_ep(void) { return find_ep_not_addr0(0, 0, 0); } +TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) { + if (daddr == 0 && ep_num == 0) { + return &_hcd_data.ep[0]; + }else{ + return find_ep_not_addr0(daddr, ep_num, ep_dir); + } +} + // free all endpoints belong to device address static void free_ep(uint8_t daddr) { - for (size_t i=0; idaddr == daddr) { tu_memclr(ep, sizeof(max3421_ep_t)); @@ -354,16 +360,8 @@ static void free_ep(uint8_t daddr) { } } -TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) { - if (daddr == 0 && ep_num == 0) { - return &_hcd_data.ep0_addr0; - }else{ - return find_ep_not_addr0(daddr, ep_num, ep_dir); - } -} - static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) { - size_t idx = cur_ep - _hcd_data.ep; + size_t const idx = cur_ep - _hcd_data.ep; // starting from next endpoint for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) { @@ -553,7 +551,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e max3421_ep_t * ep; if (daddr == 0 && ep_num == 0) { - ep = &_hcd_data.ep0_addr0; + ep = &_hcd_data.ep[0]; }else { ep = allocate_ep(); TU_ASSERT(ep); @@ -581,12 +579,20 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { reg_write(rhport, HCTL_ADDR, hctl, in_isr); } - uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); - TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ, ); - fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr); - sndbc_write(rhport, xact_len, in_isr); + uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0); + + if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) { + // Control ZLP status use HS + hxfr |= HXFR_HS; + } else { + uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); + TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,); + if (xact_len) { + fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr); + } + sndbc_write(rhport, xact_len, in_isr); + } - uint8_t const hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0); hxfr_write(rhport, hxfr, in_isr); } @@ -599,7 +605,12 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { reg_write(rhport, HCTL_ADDR, hctl, in_isr); } - uint8_t const hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0); + uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0); + if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) { + // Control ZLP status use HS + hxfr |= HXFR_HS; + } + hxfr_write(rhport, hxfr, in_isr); } @@ -611,24 +622,8 @@ TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t } } -void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t data_toggle) { - (void) rhport; - (void) result; - ep->xfer_pending = 0; - ep->data_toggle = data_toggle; - //uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir); - //hcd_event_xfer_complete(rhport, ep_addr, ep->xferred_len, result, true); - -// max3421_ep_t *next_ep = find_next_pending_ep(ep); -// if (next_ep) { -// xact_inout(rhport, next_ep, true, true); -// } -} - // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { - (void) rhport; - uint8_t const ep_num = tu_edpt_number(ep_addr); uint8_t const ep_dir = tu_edpt_dir(ep_addr); @@ -644,24 +639,12 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf ep->xfer_complete = 0; ep->xfer_pending = 1; - // carry out transfer if not busy -// if ( atomic_flag_test_and_set(&_hcd_data.busy) ) - { - uint8_t hxfr = ep_num; - - if ( ep_num == 0 ) { - ep->data_toggle = 1; - if ( buffer == NULL || buflen == 0 ) { - // ZLP for ACK stage, use HS - peraddr_write(rhport, daddr, false); - - hxfr |= HXFR_HS; - hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN); - hxfr_write(rhport, hxfr, false); - return true; - } - } + if ( ep_num == 0 ) { + ep->data_toggle = 1; + } + // carry out transfer if not busy + if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) { xact_inout(rhport, ep, true, false); } @@ -683,6 +666,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8] (void) rhport; max3421_ep_t* ep = find_opened_ep(daddr, 0, 0); + TU_ASSERT(ep); + ep->ep_dir = 0; ep->total_len = 8; ep->xferred_len = 0; @@ -703,6 +688,26 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { return false; } +//--------------------------------------------------------------------+ +// Interrupt Handler +//--------------------------------------------------------------------+ + +static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t data_toggle) { + uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir); + ep->data_toggle = data_toggle; + ep->xfer_pending = 0; + hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, true); + + // Find next pending endpoint + max3421_ep_t *next_ep = find_next_pending_ep(ep); + if (next_ep) { + xact_inout(rhport, next_ep, true, true); + }else { + // no more pending + atomic_flag_clear(&_hcd_data.busy); + } +} + static void handle_xfer_done(uint8_t rhport) { uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true); uint8_t const hresult = hrsl & HRSL_RESULT_MASK; @@ -739,7 +744,7 @@ static void handle_xfer_done(uint8_t rhport) { max3421_ep_t *next_ep = find_next_pending_ep(ep); if (ep == next_ep) { - // only one pending, retry immediately + // this endpoint is only one pending, retry immediately hxfr_write(rhport, _hcd_data.hxfr, true); }else if (next_ep) { // switch to next pending TODO could have issue with double buffered if not clear previously out data @@ -763,7 +768,6 @@ static void handle_xfer_done(uint8_t rhport) { if ( ep->xfer_complete ) { uint8_t const dt = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; // save data toggle xfer_complete_isr(rhport, ep, xfer_result, dt); - hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true); }else { // more to transfer hxfr_write(rhport, _hcd_data.hxfr, true); @@ -786,8 +790,8 @@ static void handle_xfer_done(uint8_t rhport) { if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) { uint8_t const dt = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; // save data toggle xfer_complete_isr(rhport, ep, xfer_result, dt); - hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true); } else { + // more to transfer xact_out(rhport, ep, false, true); } } -- cgit v1.3.1 From 588b758717f3c22aa8046d61247b9967de8840b7 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 28 Aug 2023 17:34:22 +0700 Subject: rename OPT_MCU_KINETIS_K64 to OPT_MCU_KINETIS_K --- hw/bsp/board_mcu.h | 2 +- src/common/tusb_mcu.h | 2 +- src/portable/nxp/khci/dcd_khci.c | 6 +++--- src/tusb_option.h | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index 3928435f0..b0f7891b4 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -47,7 +47,7 @@ #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX, OPT_MCU_MCXN9) #include "fsl_device_registers.h" -#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K64) +#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K) #include "fsl_device_registers.h" #elif CFG_TUSB_MCU == OPT_MCU_NRF5X diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 4a0c5acef..d983f8677 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -97,7 +97,7 @@ #define TUP_DCD_ENDPOINT_MAX 8 #define TUP_RHPORT_HIGHSPEED 1 -#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K64) +#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K) #define TUP_USBIP_CHIPIDEA_FS #define TUP_USBIP_CHIPIDEA_FS_KINETIS #define TUP_DCD_ENDPOINT_MAX 16 diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index d957338ad..2293d1b59 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -269,10 +269,10 @@ void dcd_init(uint8_t rhport) { (void) rhport; -#if (CFG_TUSB_MCU == OPT_MCU_KINETIS_K64) +#if (CFG_TUSB_MCU == OPT_MCU_KINETIS_K) uint32_t clk_recover_irc_en; uint32_t clk_recover_ctrl; - + clk_recover_irc_en = KHCI->CLK_RECOVER_IRC_EN; clk_recover_ctrl = KHCI->CLK_RECOVER_CTRL; @@ -284,7 +284,7 @@ void dcd_init(uint8_t rhport) #else KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK; while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK); -#endif +#endif tu_memclr(&_dcd, sizeof(_dcd)); KHCI->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */ diff --git a/src/tusb_option.h b/src/tusb_option.h index bbaa2a53a..bf2667c4c 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -121,7 +121,7 @@ #define OPT_MCU_KINETIS_KL 1200 ///< NXP KL series #define OPT_MCU_KINETIS_K32L 1201 ///< NXP K32L series #define OPT_MCU_KINETIS_K32 1201 ///< Alias to K32L -#define OPT_MCU_KINETIS_K64 1202 ///< NXP K64 series +#define OPT_MCU_KINETIS_K 1202 ///< NXP K series #define OPT_MCU_MKL25ZXX 1200 ///< Alias to KL (obsolete) #define OPT_MCU_K32L2BXX 1201 ///< Alias to K32 (obsolete) -- cgit v1.3.1 From 3740a3287ad5965df34639e90bfa890b36c0fd60 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Aug 2023 18:22:21 +0700 Subject: - correct tuh_max3421e_int_api() for nrf52 - hcd_int_disable/enable is software only to reduce interrupt lag --- hw/bsp/nrf/boards/pca10056/board.h | 9 ++++ hw/bsp/nrf/family.c | 20 ++++++- src/portable/analog/max3421/hcd_max3421.c | 86 +++++++++++++++++++++---------- 3 files changed, 87 insertions(+), 28 deletions(-) (limited to 'src') diff --git a/hw/bsp/nrf/boards/pca10056/board.h b/hw/bsp/nrf/boards/pca10056/board.h index f4368f830..16d31addb 100644 --- a/hw/bsp/nrf/boards/pca10056/board.h +++ b/hw/bsp/nrf/boards/pca10056/board.h @@ -31,6 +31,8 @@ extern "C" { #endif +#define _PINNUM(port, pin) ((port)*32 + (pin)) + // LED #define LED_PIN 13 #define LED_STATE_ON 0 @@ -43,6 +45,13 @@ #define UART_RX_PIN 8 #define UART_TX_PIN 6 +// SPI for USB host shield +#define MAX3421E_SCK_PIN _PINNUM(1, 15) +#define MAX3421E_MOSI_PIN _PINNUM(1, 13) +#define MAX3421E_MISO_PIN _PINNUM(1, 14) +#define MAX3421E_CS_PIN _PINNUM(1, 12) +#define MAX3241E_INTR_PIN _PINNUM(1, 11) + #ifdef __cplusplus } #endif diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index 368763b84..083efc235 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -107,7 +107,12 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { //--------------------------------------------------------------------+ void tuh_max3421e_int_api(uint8_t rhport, bool enabled) { (void) rhport; - nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, enabled); + + if (enabled) { + nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true); + }else { + nrfx_gpiote_trigger_disable(MAX3241E_INTR_PIN); + } } void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) { @@ -217,6 +222,19 @@ void board_init(void) { #endif #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 + // MAX3421 need 3.3v signal + if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) != UICR_REGOUT0_VOUT_3V3) { + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + + NRF_UICR->REGOUT0 = (NRF_UICR->REGOUT0 & ~UICR_REGOUT0_VOUT_Msk) | UICR_REGOUT0_VOUT_3V3; + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + + NVIC_SystemReset(); + } + // manually manage CS nrf_gpio_cfg_output(MAX3421E_CS_PIN); tuh_max3421_spi_cs_api(0, false); diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 262dbca0f..cb7911992 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -184,8 +184,6 @@ typedef struct { } max3421_ep_t; typedef struct { - atomic_flag busy; // busy transferring - // cached register uint8_t sndbc; uint8_t hirq; @@ -194,7 +192,10 @@ typedef struct { uint8_t peraddr; uint8_t hxfr; + atomic_flag busy; // busy transferring + volatile uint8_t intr_disable_count; volatile uint16_t frame_count; + max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; // [0] is reserved for addr0 OSAL_MUTEX_DEF(spi_mutexdef); @@ -220,8 +221,8 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled); static void max3421_spi_lock(uint8_t rhport, bool in_isr) { // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr if (!in_isr) { - tuh_max3421e_int_api(rhport, false); (void) osal_mutex_lock(_hcd_data.spi_mutex, OSAL_TIMEOUT_WAIT_FOREVER); + tuh_max3421e_int_api(rhport, false); } // assert CS @@ -294,6 +295,12 @@ static uint8_t reg_read(uint8_t rhport, uint8_t reg, bool in_isr) { return ret ? rx_buf[1] : 0; } +static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) { + reg_write(rhport, HIRQ_ADDR, data, in_isr); + // HIRQ write 1 is clear + _hcd_data.hirq &= ~data; +} + static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) { _hcd_data.hien = data; reg_write(rhport, HIEN_ADDR, data, in_isr); @@ -440,13 +447,14 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) { bool hcd_init(uint8_t rhport) { (void) rhport; - hcd_int_disable(rhport); + tuh_max3421e_int_api(rhport, false); tuh_max3421_spi_cs_api(rhport, false); TU_LOG2_INT(sizeof(max3421_ep_t)); TU_LOG2_INT(sizeof(max3421_data_t)); tu_memclr(&_hcd_data, sizeof(_hcd_data)); + _hcd_data.peraddr = 0xff; // invalid #if OSAL_MUTEX_REQUIRED _hcd_data.spi_mutex = osal_mutex_create(&_hcd_data.spi_mutexdef); @@ -469,11 +477,13 @@ bool hcd_init(uint8_t rhport) { reg_write(rhport, HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST, false); // clear all previously pending IRQ - reg_write(rhport, HIRQ_ADDR, 0xff, false); + hirq_write(rhport, 0xff, false); // Enable IRQ hien_write(rhport, DEFAULT_HIEN, false); + tuh_max3421e_int_api(rhport, true); + // Enable Interrupt pin reg_write(rhport, CPUCTL_ADDR, CPUCTL_IE, false); @@ -481,13 +491,21 @@ bool hcd_init(uint8_t rhport) { } // Enable USB interrupt +// Not actually enable GPIO interrupt, just set variable to prevent handler to process void hcd_int_enable (uint8_t rhport) { - tuh_max3421e_int_api(rhport, true); + (void) rhport; + // tuh_max3421e_int_api(rhport, true); + if (_hcd_data.intr_disable_count) { + _hcd_data.intr_disable_count--; + } } // Disable USB interrupt +// Not actually disable GPIO interrupt, just set variable to prevent handler to process void hcd_int_disable(uint8_t rhport) { - tuh_max3421e_int_api(rhport, false); + (void) rhport; + //tuh_max3421e_int_api(rhport, false); + _hcd_data.intr_disable_count++; } // Get frame number (1ms) @@ -521,7 +539,7 @@ void hcd_port_reset_end(uint8_t rhport) { reg_write(rhport, HCTL_ADDR, 0, false); // Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset - reg_write(rhport, HIRQ_ADDR, HIRQ_CONDET_IRQ, false); + hirq_write(rhport, HIRQ_CONDET_IRQ, false); hien_write(rhport, DEFAULT_HIEN, false); } @@ -572,19 +590,23 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { // Page 12: Programming BULK-OUT Transfers // TODO double buffered - if (switch_ep) { - peraddr_write(rhport, ep->daddr, in_isr); - - uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0); - reg_write(rhport, HCTL_ADDR, hctl, in_isr); - } uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0); - if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) { // Control ZLP status use HS hxfr |= HXFR_HS; - } else { + } + + if (switch_ep) { + peraddr_write(rhport, ep->daddr, in_isr); + + if ( 0 == (hxfr & HXFR_HS) ) { + uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0); + reg_write(rhport, HCTL_ADDR, hctl, in_isr); + } + } + + if ( 0 == (hxfr & HXFR_HS) ) { uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,); if (xact_len) { @@ -598,12 +620,6 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { // Page 13: Programming BULK-IN Transfers - if (switch_ep) { - peraddr_write(rhport, ep->daddr, in_isr); - - uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0); - reg_write(rhport, HCTL_ADDR, hctl, in_isr); - } uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0); if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) { @@ -611,6 +627,15 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { hxfr |= HXFR_HS; } + if (switch_ep) { + peraddr_write(rhport, ep->daddr, in_isr); + + if ( 0 == (hxfr & HXFR_HS) ) { + uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0); + reg_write(rhport, HCTL_ADDR, hctl, in_isr); + } + } + hxfr_write(rhport, hxfr, in_isr); } @@ -721,7 +746,7 @@ static void handle_xfer_done(uint8_t rhport) { xfer_result_t xfer_result; - //TU_LOG3("HRSL: %02X\r\n", hrsl); +// TU_LOG3("HRSL: %02X\r\n", hrsl); switch(hresult) { case HRSL_SUCCESS: xfer_result = XFER_RESULT_SUCCESS; @@ -821,13 +846,20 @@ void print_hirq(uint8_t hirq) { void hcd_int_handler(uint8_t rhport) { uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true) & _hcd_data.hien; if (!hirq) return; - // print_hirq(hirq); if (hirq & HIRQ_FRAME_IRQ) { _hcd_data.frame_count++; } + // interrupt is disabled, only ack FRAME IRQ and skip the rest + if (_hcd_data.intr_disable_count) { + if (hirq & HIRQ_FRAME_IRQ) { + hirq_write(rhport, HIRQ_FRAME_IRQ, true); + } + return; + } + if (hirq & HIRQ_CONDET_IRQ) { tusb_speed_t speed = handle_connect_irq(rhport); @@ -861,7 +893,7 @@ void hcd_int_handler(uint8_t rhport) { } // ack RCVDVAV IRQ - reg_write(rhport, HIRQ_ADDR, HIRQ_RCVDAV_IRQ, true); + hirq_write(rhport, HIRQ_RCVDAV_IRQ, true); hirq = reg_read(rhport, HIRQ_ADDR, true); } @@ -871,7 +903,7 @@ void hcd_int_handler(uint8_t rhport) { } if ( hirq & HIRQ_HXFRDN_IRQ ) { - reg_write(rhport, HIRQ_ADDR, HIRQ_HXFRDN_IRQ, true); + hirq_write(rhport, HIRQ_HXFRDN_IRQ, true); handle_xfer_done(rhport); } @@ -881,7 +913,7 @@ void hcd_int_handler(uint8_t rhport) { // clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing hirq &= ~HIRQ_SNDBAV_IRQ; if ( hirq ) { - reg_write(rhport, HIRQ_ADDR, hirq, true); + hirq_write(rhport, hirq, true); } } -- cgit v1.3.1 From 2a814a99af32bf084cbb730d97e3c9cb31a3fa85 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Aug 2023 20:27:37 +0700 Subject: - hcd_setup_send() also check for busy flag - xact_inout() to support send setup --- src/portable/analog/max3421/hcd_max3421.c | 71 +++++++++++++++++-------------- 1 file changed, 39 insertions(+), 32 deletions(-) (limited to 'src') diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index cb7911992..461e02593 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -168,6 +168,7 @@ typedef struct { struct TU_ATTR_PACKED { uint8_t ep_dir : 1; uint8_t is_iso : 1; + uint8_t is_setup : 1; uint8_t data_toggle : 1; uint8_t xfer_pending : 1; uint8_t xfer_complete : 1; @@ -590,56 +591,55 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { // Page 12: Programming BULK-OUT Transfers // TODO double buffered - - uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0); - if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) { - // Control ZLP status use HS - hxfr |= HXFR_HS; - } - if (switch_ep) { peraddr_write(rhport, ep->daddr, in_isr); - if ( 0 == (hxfr & HXFR_HS) ) { - uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0); - reg_write(rhport, HCTL_ADDR, hctl, in_isr); - } + uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0); + reg_write(rhport, HCTL_ADDR, hctl, in_isr); } - if ( 0 == (hxfr & HXFR_HS) ) { - uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); - TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,); - if (xact_len) { - fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr); - } - sndbc_write(rhport, xact_len, in_isr); + uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); + TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,); + if (xact_len) { + fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr); } + sndbc_write(rhport, xact_len, in_isr); + uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0); hxfr_write(rhport, hxfr, in_isr); } void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { // Page 13: Programming BULK-IN Transfers - - uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0); - if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) { - // Control ZLP status use HS - hxfr |= HXFR_HS; - } - if (switch_ep) { peraddr_write(rhport, ep->daddr, in_isr); - if ( 0 == (hxfr & HXFR_HS) ) { - uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0); - reg_write(rhport, HCTL_ADDR, hctl, in_isr); - } + uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0); + reg_write(rhport, HCTL_ADDR, hctl, in_isr); } + uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0); hxfr_write(rhport, hxfr, in_isr); } TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { + if (ep->ep_num == 0 ) { + // setup + if (ep->is_setup) { + peraddr_write(rhport, ep->daddr, in_isr); + hxfr_write(rhport, HXFR_SETUP, in_isr); + return; + } + + // status + if (ep->buf == NULL || ep->total_len == 0) { + uint8_t const hxfr = HXFR_HS | (ep->ep_dir ? 0 : HXFR_OUT_NIN); + peraddr_write(rhport, ep->daddr, in_isr); + hxfr_write(rhport, hxfr, in_isr); + return; + } + } + if (ep->ep_dir) { xact_in(rhport, ep, switch_ep, in_isr); }else { @@ -665,12 +665,15 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf ep->xfer_pending = 1; if ( ep_num == 0 ) { + ep->is_setup = 0; ep->data_toggle = 1; } // carry out transfer if not busy if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) { xact_inout(rhport, ep, true, false); + } else { + return true; } return true; @@ -694,12 +697,16 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8] TU_ASSERT(ep); ep->ep_dir = 0; - ep->total_len = 8; + ep->total_len = 8; ep->xferred_len = 0; + ep->is_setup = 1; - peraddr_write(rhport, daddr, false); fifo_write(rhport, SUDFIFO_ADDR, setup_packet, 8, false); - hxfr_write(rhport, HXFR_SETUP, false); + + // carry out transfer if not busy + if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) { + xact_inout(rhport, ep, true, false); + } return true; } -- cgit v1.3.1 From 966584363546023d85f4d8b748b18ace63ea1c57 Mon Sep 17 00:00:00 2001 From: Alexander Mueller Date: Tue, 29 Aug 2023 18:16:50 +0200 Subject: Fix the weak dcd_edpt0_status_complete for Keil Compiler The Keil compiler seems to have different semantics and the defined function was never called. The same is probably true for the other weak functions. I can change those too. --- src/device/dcd.h | 2 +- src/device/usbd_control.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/device/dcd.h b/src/device/dcd.h index 18a708347..b1984fda3 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -155,7 +155,7 @@ void dcd_sof_enable(uint8_t rhport, bool en); // Invoked when a control transfer's status stage is complete. // May help DCD to prepare for next control transfer, this API is optional. -void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) TU_ATTR_WEAK; +void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request); // Configure endpoint's registers according to descriptor bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_ep); diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index 76d062e40..a6081060e 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -135,6 +135,15 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo // USBD API //--------------------------------------------------------------------+ +TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) +{ + (void)rhport; + (void)request; + + // this is the default implementation that is called when no "real" implementation + // of the function exists +} + void usbd_control_reset(void); void usbd_control_set_request(tusb_control_request_t const *request); void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp ); @@ -173,7 +182,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result TU_ASSERT(0 == xferred_bytes); // invoke optional dcd hook if available - if (dcd_edpt0_status_complete) dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request); + dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request); if (_ctrl_xfer.complete_cb) { -- cgit v1.3.1 From 1ab488eb06ef4cb8ad9c0cff91e6b0caf76f73c4 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 30 Aug 2023 16:04:18 +0700 Subject: call xfer_complete_isr() when result is not successful (stalled or failed) --- hw/bsp/nrf/boards/pca10095/board.h | 9 +++++++ hw/bsp/nrf/family.c | 7 +++-- hw/bsp/nrf/nrfx_config.h | 2 +- src/common/tusb_mcu.h | 2 +- src/portable/analog/max3421/hcd_max3421.c | 43 ++++++++++++++++++++++--------- 5 files changed, 47 insertions(+), 16 deletions(-) (limited to 'src') diff --git a/hw/bsp/nrf/boards/pca10095/board.h b/hw/bsp/nrf/boards/pca10095/board.h index fd3c63d6a..b9d3a19dc 100644 --- a/hw/bsp/nrf/boards/pca10095/board.h +++ b/hw/bsp/nrf/boards/pca10095/board.h @@ -31,6 +31,8 @@ extern "C" { #endif +#define _PINNUM(port, pin) ((port)*32 + (pin)) + // LED #define LED_PIN 28 #define LED_STATE_ON 0 @@ -43,6 +45,13 @@ #define UART_RX_PIN 32 #define UART_TX_PIN 33 +// SPI for USB host shield +#define MAX3421E_SCK_PIN _PINNUM(1, 15) +#define MAX3421E_MOSI_PIN _PINNUM(1, 13) +#define MAX3421E_MISO_PIN _PINNUM(1, 14) +#define MAX3421E_CS_PIN _PINNUM(1, 12) +#define MAX3241E_INTR_PIN _PINNUM(1, 11) + #ifdef __cplusplus } #endif diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index 083efc235..2b4260083 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -34,6 +34,7 @@ #pragma GCC diagnostic ignored "-Wcast-align" #pragma GCC diagnostic ignored "-Wunused-parameter" #pragma GCC diagnostic ignored "-Wundef" +#pragma GCC diagnostic ignored "-Wredundant-decls" #endif #include "nrfx.h" @@ -94,7 +95,7 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) { //------------- Host using MAX2341E -------------// #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 -static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0); +static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1); void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { if ( !(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO) ) return; @@ -222,7 +223,8 @@ void board_init(void) { #endif #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 - // MAX3421 need 3.3v signal + // MAX3421 need 3.3v signal (may not be needed) + #if defined(UICR_REGOUT0_VOUT_Msk) && 0 if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) != UICR_REGOUT0_VOUT_3V3) { NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} @@ -234,6 +236,7 @@ void board_init(void) { NVIC_SystemReset(); } + #endif // manually manage CS nrf_gpio_cfg_output(MAX3421E_CS_PIN); diff --git a/hw/bsp/nrf/nrfx_config.h b/hw/bsp/nrf/nrfx_config.h index e3d0ea91b..95ef33ce4 100644 --- a/hw/bsp/nrf/nrfx_config.h +++ b/hw/bsp/nrf/nrfx_config.h @@ -11,7 +11,7 @@ #define NRFX_UARTE0_ENABLED 1 #define NRFX_SPIM_ENABLED 1 -#define NRFX_SPIM0_ENABLED 1 +#define NRFX_SPIM1_ENABLED 1 // use SPI1 since nrf5340 share uart with spi #define NRFX_PRS_ENABLED 0 #define NRFX_USBREG_ENABLED 1 diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 21939df7c..8807ff8aa 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -390,7 +390,7 @@ // External USB controller //--------------------------------------------------------------------+ -#if defined(CFG_TUH_MAX3421) & CFG_TUH_MAX3421 +#if defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 #ifndef CFG_TUH_MAX3421_ENDPOINT_TOTAL #define CFG_TUH_MAX3421_ENDPOINT_TOTAL (8 + 4*(CFG_TUH_DEVICE_MAX-1)) #endif diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 461e02593..705bb5bfd 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -374,7 +374,8 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) { // starting from next endpoint for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) { max3421_ep_t* ep = &_hcd_data.ep[i]; - if (ep->xfer_pending) { + if (ep->xfer_pending && ep->packet_size) { +// TU_LOG3("next pending i = %u\n", i); return ep; } } @@ -382,7 +383,8 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) { // wrap around including current endpoint for (size_t i = 0; i <= idx; i++) { max3421_ep_t* ep = &_hcd_data.ep[i]; - if (ep->xfer_pending) { + if (ep->xfer_pending && ep->packet_size) { +// TU_LOG3("next pending i = %u\n", i); return ep; } } @@ -464,6 +466,10 @@ bool hcd_init(uint8_t rhport) { // full duplex, interrupt negative edge reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false); + // V1 is 0x01, V2 is 0x12, V3 is 0x13 + // uint8_t const revision = reg_read(rhport, REVISION_ADDR, false); + // TU_LOG2_HEX(revision); + // reset reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false); reg_write(rhport, USBCTL_ADDR, 0, false); @@ -699,6 +705,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8] ep->ep_dir = 0; ep->total_len = 8; ep->xferred_len = 0; + ep->xfer_pending = 1; ep->is_setup = 1; fifo_write(rhport, SUDFIFO_ADDR, setup_packet, 8, false); @@ -724,9 +731,16 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { // Interrupt Handler //--------------------------------------------------------------------+ -static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t data_toggle) { +static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl) { uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir); - ep->data_toggle = data_toggle; + + // save data toggle + if (ep->ep_dir) { + ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; + }else { + ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; + } + ep->xfer_pending = 0; hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, true); @@ -763,10 +777,6 @@ static void handle_xfer_done(uint8_t rhport) { xfer_result = XFER_RESULT_STALLED; break; - case HRSL_BAD_REQ: - // occurred when initialized without any pending transfer. Skip for now - return; - case HRSL_NAK: if (ep_num == 0) { // NAK on control, retry immediately @@ -781,15 +791,26 @@ static void handle_xfer_done(uint8_t rhport) { }else if (next_ep) { // switch to next pending TODO could have issue with double buffered if not clear previously out data xact_inout(rhport, next_ep, true, true); + }else { + TU_ASSERT(false,); } } return; + case HRSL_BAD_REQ: + // occurred when initialized without any pending transfer. Skip for now + return; + default: xfer_result = XFER_RESULT_FAILED; break; } + if (xfer_result != XFER_RESULT_SUCCESS) { + xfer_complete_isr(rhport, ep, xfer_result, hrsl); + return; + } + if (ep_dir) { // IN transfer: fifo data is already received in RCVDAV IRQ if ( hxfr_type & HXFR_HS ) { @@ -798,8 +819,7 @@ static void handle_xfer_done(uint8_t rhport) { // short packet or all bytes transferred if ( ep->xfer_complete ) { - uint8_t const dt = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; // save data toggle - xfer_complete_isr(rhport, ep, xfer_result, dt); + xfer_complete_isr(rhport, ep, xfer_result, hrsl); }else { // more to transfer hxfr_write(rhport, _hcd_data.hxfr, true); @@ -820,8 +840,7 @@ static void handle_xfer_done(uint8_t rhport) { ep->buf += xact_len; if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) { - uint8_t const dt = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; // save data toggle - xfer_complete_isr(rhport, ep, xfer_result, dt); + xfer_complete_isr(rhport, ep, xfer_result, hrsl); } else { // more to transfer xact_out(rhport, ep, false, true); -- cgit v1.3.1 From 41493426b38c8ce44b1f7720b907538bc5402f98 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 30 Aug 2023 16:21:43 +0700 Subject: use ep buf to keep setup packet, work well with hid device --- examples/host/msc_file_explorer/src/tusb_config.h | 2 +- src/portable/analog/max3421/hcd_max3421.c | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h index 28e130c0e..e6186ba46 100644 --- a/examples/host/msc_file_explorer/src/tusb_config.h +++ b/examples/host/msc_file_explorer/src/tusb_config.h @@ -37,7 +37,7 @@ #if CFG_TUSB_MCU == OPT_MCU_RP2040 // change to 1 if using pico-pio-usb as host controller for raspberry rp2040 #define CFG_TUH_RPI_PIO_USB 0 - #define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_US + #define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_USB //#elif CFG_TUSB_MCU == OPT_MCU_NRF5X // // Use external USB controller (via SPI) MAX3421E (aka usb host shield) // #define CFG_TUH_MAX3421 1 diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 705bb5bfd..d644390da 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -633,6 +633,7 @@ TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t // setup if (ep->is_setup) { peraddr_write(rhport, ep->daddr, in_isr); + fifo_write(rhport, SUDFIFO_ADDR, ep->buf, 8, in_isr); hxfr_write(rhport, HXFR_SETUP, in_isr); return; } @@ -703,12 +704,12 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8] TU_ASSERT(ep); ep->ep_dir = 0; + ep->is_setup = 1; + ep->buf = (uint8_t*)(uintptr_t) setup_packet; ep->total_len = 8; ep->xferred_len = 0; + ep->xfer_complete = 0; ep->xfer_pending = 1; - ep->is_setup = 1; - - fifo_write(rhport, SUDFIFO_ADDR, setup_packet, 8, false); // carry out transfer if not busy if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) { -- cgit v1.3.1 From 3b7d5aa0421f3d3a7ac199de0138dc40141fbddd Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 31 Aug 2023 16:52:09 +0700 Subject: improve connection & disconnection detection. But there is still issue when CONDETIRQ occurs but we are disabled interrupt (for osal queue access). --- hw/bsp/board.c | 26 ++++------ hw/bsp/nrf/family.c | 49 ++++++++---------- src/host/usbh.c | 2 +- src/portable/analog/max3421/hcd_max3421.c | 85 ++++++++++++++----------------- 4 files changed, 72 insertions(+), 90 deletions(-) (limited to 'src') diff --git a/hw/bsp/board.c b/hw/bsp/board.c index 417630a03..562792625 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -44,17 +44,16 @@ // If using SES IDE, use the Syscalls/SEGGER_RTT_Syscalls_SES.c instead #if !(defined __SES_ARM) && !(defined __SES_RISCV) && !(defined __CROSSWORKS_ARM) + #include "SEGGER_RTT.h" -TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) -{ +TU_ATTR_USED int sys_write(int fhdl, const void *buf, size_t count) { (void) fhdl; - SEGGER_RTT_Write(0, (const char*) buf, (int) count); + SEGGER_RTT_Write(0, (const char *) buf, (int) count); return count; } -TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) -{ +TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) { (void) fhdl; int rd = (int) SEGGER_RTT_Read(0, buf, count); return (rd > 0) ? rd : -1; @@ -67,8 +66,7 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) #include "board_mcu.h" -TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) -{ +TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) { (void) fhdl; uint8_t const* buf8 = (uint8_t const*) buf; @@ -79,8 +77,7 @@ TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) return (int) count; } -TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) -{ +TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { (void) fhdl; (void) buf; (void) count; @@ -90,14 +87,12 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) #else // Default logging with on-board UART -TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) -{ +TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) { (void) fhdl; return board_uart_write(buf, (int) count); } -TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) -{ +TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { (void) fhdl; int rd = board_uart_read((uint8_t*) buf, (int) count); return (rd > 0) ? rd : -1; @@ -105,8 +100,7 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) #endif -int board_getchar(void) -{ +int board_getchar(void) { char c; - return ( sys_read(0, &c, 1) > 0 ) ? (int) c : (-1); + return (sys_read(0, &c, 1) > 0) ? (int) c : (-1); } diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index 2b4260083..7358458ce 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -98,7 +98,7 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) { static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1); void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { - if ( !(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO) ) return; + if (!(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return; tuh_int_handler(1); } @@ -111,7 +111,7 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled) { if (enabled) { nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true); - }else { + } else { nrfx_gpiote_trigger_disable(MAX3241E_INTR_PIN); } } @@ -121,7 +121,7 @@ void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) { nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1); } -bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) { +bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) { (void) rhport; nrfx_spim_xfer_desc_t xfer = { @@ -157,21 +157,21 @@ void board_init(void) { nrf_gpio_cfg_input(BUTTON_PIN, NRF_GPIO_PIN_PULLUP); // 1ms tick timer - SysTick_Config(SystemCoreClock/1000); + SysTick_Config(SystemCoreClock / 1000); // UART nrfx_uarte_config_t uart_cfg = { - .pseltxd = UART_TX_PIN, - .pselrxd = UART_RX_PIN, - .pselcts = NRF_UARTE_PSEL_DISCONNECTED, - .pselrts = NRF_UARTE_PSEL_DISCONNECTED, - .p_context = NULL, - .baudrate = NRF_UARTE_BAUDRATE_115200, // CFG_BOARD_UART_BAUDRATE - .interrupt_priority = 7, - .hal_cfg = { - .hwfc = NRF_UARTE_HWFC_DISABLED, - .parity = NRF_UARTE_PARITY_EXCLUDED, - } + .pseltxd = UART_TX_PIN, + .pselrxd = UART_RX_PIN, + .pselcts = NRF_UARTE_PSEL_DISCONNECTED, + .pselrts = NRF_UARTE_PSEL_DISCONNECTED, + .p_context = NULL, + .baudrate = NRF_UARTE_BAUDRATE_115200, // CFG_BOARD_UART_BAUDRATE + .interrupt_priority = 7, + .hal_cfg = { + .hwfc = NRF_UARTE_HWFC_DISABLED, + .parity = NRF_UARTE_PARITY_EXCLUDED, + } }; nrfx_uarte_init(&_uart_id, &uart_cfg, NULL); //uart_handler); @@ -211,11 +211,11 @@ void board_init(void) { // USB power may already be ready at this time -> no event generated // We need to invoke the handler based on the status initially - #ifdef NRF5340_XXAA +#ifdef NRF5340_XXAA usb_reg = NRF_USBREGULATOR->USBREGSTATUS; - #else +#else usb_reg = NRF_POWER->USBREGSTATUS; - #endif +#endif } if ( usb_reg & VBUSDETECT_Msk ) tusb_hal_nrf_power_event(USB_EVT_DETECTED); @@ -308,8 +308,7 @@ uint32_t board_millis(void) { #ifdef SOFTDEVICE_PRESENT // process SOC event from SD -uint32_t proc_soc(void) -{ +uint32_t proc_soc(void) { uint32_t soc_evt; uint32_t err = sd_evt_get(&soc_evt); @@ -326,18 +325,14 @@ uint32_t proc_soc(void) return err; } -uint32_t proc_ble(void) -{ +uint32_t proc_ble(void) { // do nothing with ble return NRF_ERROR_NOT_FOUND; } -void SD_EVT_IRQHandler(void) -{ +void SD_EVT_IRQHandler(void) { // process BLE and SOC until there is no more events - while( (NRF_ERROR_NOT_FOUND != proc_ble()) || (NRF_ERROR_NOT_FOUND != proc_soc()) ) - { - + while( (NRF_ERROR_NOT_FOUND != proc_ble()) || (NRF_ERROR_NOT_FOUND != proc_soc()) ) { } } diff --git a/src/host/usbh.c b/src/host/usbh.c index 12a7f5839..bacb3a719 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -852,7 +852,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b ep_state->busy = 0; ep_state->claimed = 0; TU_LOG1("Failed\r\n"); - TU_BREAKPOINT(); +// TU_BREAKPOINT(); return false; } } diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index d644390da..56d3aea45 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -405,45 +405,46 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { return false; } -tusb_speed_t handle_connect_irq(uint8_t rhport) { +static void handle_connect_irq(uint8_t rhport) { uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true); uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS); - tusb_speed_t speed; uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST; + TU_LOG2_HEX(jk); switch(jk) { - case 0x00: - // SEO is disconnected - speed = TUSB_SPEED_INVALID; - break; - - case (HRSL_JSTATUS | HRSL_KSTATUS): - // SE1 is illegal - speed = TUSB_SPEED_INVALID; + case 0x00: // SEO is disconnected + case (HRSL_JSTATUS | HRSL_KSTATUS): // SE1 is illegal + mode_write(rhport, new_mode, true); + hcd_event_device_remove(rhport, true); break; default: { - // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State) - uint8_t const mode = reg_read(rhport, MODE_ADDR, true); - uint8_t const ls_bit = mode & MODE_LOWSPEED; + // Bus Reset also cause CONDET IRQ, skip if we are already connected and doing bus reset + if ((_hcd_data.hirq & HIRQ_BUSEVENT_IRQ) && (_hcd_data.mode & MODE_SOFKAENAB)) { + break; + } - if ( (ls_bit && (jk == HRSL_JSTATUS)) || (!ls_bit && (jk == HRSL_KSTATUS)) ) { - speed = TUSB_SPEED_LOW; + // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State) + // However, since we are always in full speed mode, we can just check J-state + if (jk == HRSL_KSTATUS) { new_mode |= MODE_LOWSPEED; - } else { - speed = TUSB_SPEED_FULL; + TU_LOG3("Low speed\n"); + }else { + TU_LOG3("Full speed\n"); } + new_mode |= MODE_SOFKAENAB; + mode_write(rhport, new_mode, true); - new_mode |= MODE_SOFKAENAB; // enable SOF since there is new device + // FIXME multiple MAX3421 rootdevice address is not 1 + uint8_t const daddr = 1; + free_ep(daddr); + + hcd_event_device_attach(rhport, true); break; } } - - mode_write(rhport, new_mode, true); - TU_LOG2_INT(speed); - return speed; } // Initialize controller to host mode @@ -500,8 +501,9 @@ bool hcd_init(uint8_t rhport) { // Enable USB interrupt // Not actually enable GPIO interrupt, just set variable to prevent handler to process void hcd_int_enable (uint8_t rhport) { +// tuh_max3421e_int_api(rhport, true); + (void) rhport; - // tuh_max3421e_int_api(rhport, true); if (_hcd_data.intr_disable_count) { _hcd_data.intr_disable_count--; } @@ -510,8 +512,8 @@ void hcd_int_enable (uint8_t rhport) { // Disable USB interrupt // Not actually disable GPIO interrupt, just set variable to prevent handler to process void hcd_int_disable(uint8_t rhport) { - (void) rhport; //tuh_max3421e_int_api(rhport, false); + (void) rhport; _hcd_data.intr_disable_count++; } @@ -534,20 +536,12 @@ bool hcd_port_connect_status(uint8_t rhport) { // Reset USB bus on the port. Return immediately, bus reset sequence may not be complete. // Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence. void hcd_port_reset(uint8_t rhport) { - // Bus reset will also trigger CONDET IRQ, disable it - uint8_t const hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ; - hien_write(rhport, hien, false); - reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, false); } // Complete bus reset sequence, may be required by some controllers void hcd_port_reset_end(uint8_t rhport) { reg_write(rhport, HCTL_ADDR, 0, false); - - // Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset - hirq_write(rhport, HIRQ_CONDET_IRQ, false); - hien_write(rhport, DEFAULT_HIEN, false); } // Get port link speed @@ -660,7 +654,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf uint8_t const ep_dir = tu_edpt_dir(ep_addr); max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir); - TU_ASSERT(ep); + TU_VERIFY(ep); // control transfer can switch direction ep->ep_dir = ep_dir; @@ -767,8 +761,6 @@ static void handle_xfer_done(uint8_t rhport) { TU_ASSERT(ep, ); xfer_result_t xfer_result; - -// TU_LOG3("HRSL: %02X\r\n", hrsl); switch(hresult) { case HRSL_SUCCESS: xfer_result = XFER_RESULT_SUCCESS; @@ -803,6 +795,7 @@ static void handle_xfer_done(uint8_t rhport) { return; default: + TU_LOG3("HRSL: %02X\r\n", hrsl); xfer_result = XFER_RESULT_FAILED; break; } @@ -875,30 +868,30 @@ void hcd_int_handler(uint8_t rhport) { if (!hirq) return; // print_hirq(hirq); +// uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true); + if (hirq & HIRQ_FRAME_IRQ) { _hcd_data.frame_count++; } + #if 1 // interrupt is disabled, only ack FRAME IRQ and skip the rest if (_hcd_data.intr_disable_count) { if (hirq & HIRQ_FRAME_IRQ) { hirq_write(rhport, HIRQ_FRAME_IRQ, true); } + + if ((hirq & HIRQ_CONDET_IRQ) && !(_hcd_data.mode & MODE_SOFKAENAB)) { + // connection when interrupt is disabled + TU_LOG3_INT(_hcd_data.intr_disable_count); + return; + } return; } + #endif if (hirq & HIRQ_CONDET_IRQ) { - tusb_speed_t speed = handle_connect_irq(rhport); - - if (speed == TUSB_SPEED_INVALID) { - hcd_event_device_remove(rhport, true); - }else { - // FIXME multiple MAX3421 rootdevice address is not 1 - uint8_t const daddr = 1; - free_ep(daddr); - - hcd_event_device_attach(rhport, true); - } + handle_connect_irq(rhport); } // queue more transfer in handle_xfer_done() can cause hirq to be set again while external IRQ may not catch and/or -- cgit v1.3.1 From ed0a233d4830baa8a767fcc20dcbfedbb09b7b41 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 31 Aug 2023 21:28:27 +0700 Subject: vastly improve attach/detach device, still have issue where thing is still hanged occasionally. --- src/portable/analog/max3421/hcd_max3421.c | 126 +++++++++++++++++------------- 1 file changed, 70 insertions(+), 56 deletions(-) (limited to 'src') diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 56d3aea45..c61389cb9 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -215,6 +215,9 @@ void tuh_max3421_spi_cs_api(uint8_t rhport, bool active); bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len); void tuh_max3421e_int_api(uint8_t rhport, bool enabled); +static void handle_connect_irq(uint8_t rhport, bool in_isr); +static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr); + //--------------------------------------------------------------------+ // SPI Helper //--------------------------------------------------------------------+ @@ -238,6 +241,14 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) { if (!in_isr) { tuh_max3421e_int_api(rhport, true); (void) osal_mutex_unlock(_hcd_data.spi_mutex); + + // when re-enable interrupt, we may miss INTR edge (usually via GPIO detection interrupt). + // It would be ok if we are operating since SOF will re-trigger interrupt. + // However, for CONDET_IRQ i.e host not operating therefore we need to manually handle it here. + if (_hcd_data.hirq & HIRQ_CONDET_IRQ) { + handle_connect_irq(rhport, false); + hirq_write(rhport, HIRQ_CONDET_IRQ, false); + } } } @@ -405,48 +416,6 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { return false; } -static void handle_connect_irq(uint8_t rhport) { - uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true); - uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS); - - uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST; - TU_LOG2_HEX(jk); - - switch(jk) { - case 0x00: // SEO is disconnected - case (HRSL_JSTATUS | HRSL_KSTATUS): // SE1 is illegal - mode_write(rhport, new_mode, true); - hcd_event_device_remove(rhport, true); - break; - - default: { - // Bus Reset also cause CONDET IRQ, skip if we are already connected and doing bus reset - if ((_hcd_data.hirq & HIRQ_BUSEVENT_IRQ) && (_hcd_data.mode & MODE_SOFKAENAB)) { - break; - } - - // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State) - // However, since we are always in full speed mode, we can just check J-state - if (jk == HRSL_KSTATUS) { - new_mode |= MODE_LOWSPEED; - TU_LOG3("Low speed\n"); - }else { - TU_LOG3("Full speed\n"); - } - new_mode |= MODE_SOFKAENAB; - mode_write(rhport, new_mode, true); - - // FIXME multiple MAX3421 rootdevice address is not 1 - uint8_t const daddr = 1; - free_ep(daddr); - - hcd_event_device_attach(rhport, true); - - break; - } - } -} - // Initialize controller to host mode bool hcd_init(uint8_t rhport) { (void) rhport; @@ -507,6 +476,14 @@ void hcd_int_enable (uint8_t rhport) { if (_hcd_data.intr_disable_count) { _hcd_data.intr_disable_count--; } + + // when re-enable interrupt, we may miss INTR edge (usually via GPIO detection interrupt). + // It would be ok if we are operating since SOF will re-trigger interrupt. + // However, for CONDET_IRQ i.e host not operating therefore we need to manually handle it here. +// if (_hcd_data.hirq & HIRQ_CONDET_IRQ) { +// handle_connect_irq(rhport, false); +// hirq_write(rhport, HIRQ_CONDET_IRQ, false); +// } } // Disable USB interrupt @@ -726,6 +703,54 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { // Interrupt Handler //--------------------------------------------------------------------+ +static void handle_connect_irq(uint8_t rhport, bool in_isr) { + uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, in_isr); + uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS); + + uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST; + TU_LOG2_HEX(jk); + + switch(jk) { + case 0x00: // SEO is disconnected + case (HRSL_JSTATUS | HRSL_KSTATUS): // SE1 is illegal + mode_write(rhport, new_mode, in_isr); + + // port reset anyway, this will help to stable bus signal for next connection + reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, in_isr); + + hcd_event_device_remove(rhport, in_isr); + + reg_write(rhport, HCTL_ADDR, 0, in_isr); + break; + + default: { + // Bus Reset also cause CONDET IRQ, skip if we are already connected and doing bus reset + if ((_hcd_data.hirq & HIRQ_BUSEVENT_IRQ) && (_hcd_data.mode & MODE_SOFKAENAB)) { + break; + } + + // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State) + // However, since we are always in full speed mode, we can just check J-state + if (jk == HRSL_KSTATUS) { + new_mode |= MODE_LOWSPEED; + TU_LOG3("Low speed\n"); + }else { + TU_LOG3("Full speed\n"); + } + new_mode |= MODE_SOFKAENAB; + mode_write(rhport, new_mode, in_isr); + + // FIXME multiple MAX3421 rootdevice address is not 1 + uint8_t const daddr = 1; + free_ep(daddr); + + hcd_event_device_attach(rhport, in_isr); + + break; + } + } +} + static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl) { uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir); @@ -758,7 +783,7 @@ static void handle_xfer_done(uint8_t rhport) { uint8_t const ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1; max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, ep_dir); - TU_ASSERT(ep, ); + TU_VERIFY(ep, ); xfer_result_t xfer_result; switch(hresult) { @@ -857,7 +882,6 @@ void print_hirq(uint8_t hirq) { TU_LOG3("\r\n"); } - #else #define print_hirq(hirq) #endif @@ -868,30 +892,20 @@ void hcd_int_handler(uint8_t rhport) { if (!hirq) return; // print_hirq(hirq); -// uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true); - if (hirq & HIRQ_FRAME_IRQ) { _hcd_data.frame_count++; } - #if 1 - // interrupt is disabled, only ack FRAME IRQ and skip the rest + // interrupt is disabled by usbh task: only ack FRAME IRQ and skip the rest if (_hcd_data.intr_disable_count) { if (hirq & HIRQ_FRAME_IRQ) { hirq_write(rhport, HIRQ_FRAME_IRQ, true); } - - if ((hirq & HIRQ_CONDET_IRQ) && !(_hcd_data.mode & MODE_SOFKAENAB)) { - // connection when interrupt is disabled - TU_LOG3_INT(_hcd_data.intr_disable_count); - return; - } return; } - #endif if (hirq & HIRQ_CONDET_IRQ) { - handle_connect_irq(rhport); + handle_connect_irq(rhport, true); } // queue more transfer in handle_xfer_done() can cause hirq to be set again while external IRQ may not catch and/or -- cgit v1.3.1 From 1b9108ea0dc237835e801d26cc7eef052acad987 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 6 Sep 2023 17:11:35 +0700 Subject: minor debug clean up --- src/common/tusb_common.h | 6 ++---- src/common/tusb_debug.h | 37 ++++++++++++++----------------------- src/device/usbd.c | 2 +- src/device/usbd_pvt.h | 15 ++++++--------- src/host/usbh.c | 6 ++---- 5 files changed, 25 insertions(+), 41 deletions(-) (limited to 'src') diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index c303c6eaf..6fffed11c 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -122,13 +122,11 @@ TU_ATTR_ALWAYS_INLINE static inline int tu_memcpy_s(void *dest, size_t destsz, c //------------- Bytes -------------// -TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0) -{ +TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0) { return ( ((uint32_t) b3) << 24) | ( ((uint32_t) b2) << 16) | ( ((uint32_t) b1) << 8) | b0; } -TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low) -{ +TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low) { return (uint16_t) ((((uint16_t) high) << 8) | low); } diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h index 36507041f..99176c02a 100644 --- a/src/common/tusb_debug.h +++ b/src/common/tusb_debug.h @@ -58,16 +58,14 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent); #define tu_printf printf #endif -static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize) -{ +static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) { for(uint32_t i=0; i= 2 #define TU_LOG2 TU_LOG1 #define TU_LOG2_MEM TU_LOG1_MEM - #define TU_LOG2_ARR TU_LOG1_ARR - #define TU_LOG2_PTR TU_LOG1_PTR + #define TU_LOG2_BUF TU_LOG1_BUF #define TU_LOG2_INT TU_LOG1_INT #define TU_LOG2_HEX TU_LOG1_HEX #endif @@ -95,30 +91,25 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize) #if CFG_TUSB_DEBUG >= 3 #define TU_LOG3 TU_LOG1 #define TU_LOG3_MEM TU_LOG1_MEM - #define TU_LOG3_ARR TU_LOG1_ARR - #define TU_LOG3_PTR TU_LOG1_PTR + #define TU_LOG3_BUF TU_LOG1_BUF #define TU_LOG3_INT TU_LOG1_INT #define TU_LOG3_HEX TU_LOG1_HEX #endif -typedef struct -{ +typedef struct { uint32_t key; const char* data; } tu_lookup_entry_t; -typedef struct -{ +typedef struct { uint16_t count; tu_lookup_entry_t const* items; } tu_lookup_table_t; -static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key) -{ +static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key) { tu_static char not_found[11]; - for(uint16_t i=0; icount; i++) - { + for(uint16_t i=0; icount; i++) { if (p_table->items[i].key == key) return p_table->items[i].data; } @@ -133,7 +124,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3 #ifndef TU_LOG #define TU_LOG(n, ...) #define TU_LOG_MEM(n, ...) - #define TU_LOG_PTR(n, ...) + #define TU_LOG_BUF(n, ...) #define TU_LOG_INT(n, ...) #define TU_LOG_HEX(n, ...) #define TU_LOG_LOCATION() @@ -144,14 +135,14 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3 #define TU_LOG0(...) #define TU_LOG0_MEM(...) -#define TU_LOG0_PTR(...) +#define TU_LOG0_BUF(...) #define TU_LOG0_INT(...) #define TU_LOG0_HEX(...) #ifndef TU_LOG1 #define TU_LOG1(...) #define TU_LOG1_MEM(...) - #define TU_LOG1_PTR(...) + #define TU_LOG1_BUF(...) #define TU_LOG1_INT(...) #define TU_LOG1_HEX(...) #endif @@ -159,7 +150,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3 #ifndef TU_LOG2 #define TU_LOG2(...) #define TU_LOG2_MEM(...) - #define TU_LOG2_PTR(...) + #define TU_LOG2_BUF(...) #define TU_LOG2_INT(...) #define TU_LOG2_HEX(...) #endif @@ -167,7 +158,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3 #ifndef TU_LOG3 #define TU_LOG3(...) #define TU_LOG3_MEM(...) - #define TU_LOG3_PTR(...) + #define TU_LOG3_BUF(...) #define TU_LOG3_INT(...) #define TU_LOG3_HEX(...) #endif diff --git a/src/device/usbd.c b/src/device/usbd.c index f0d9fba52..50941c46f 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -506,7 +506,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) break; case DCD_EVENT_SETUP_RECEIVED: - TU_LOG_PTR(CFG_TUD_LOG_LEVEL, &event.setup_received); + TU_LOG_BUF(CFG_TUD_LOG_LEVEL, &event.setup_received, 8); TU_LOG_USBD("\r\n"); // Mark as connected after receiving 1st setup packet. diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h index 16585167f..153be7cee 100644 --- a/src/device/usbd_pvt.h +++ b/src/device/usbd_pvt.h @@ -23,8 +23,8 @@ * * This file is part of the TinyUSB stack. */ -#ifndef USBD_PVT_H_ -#define USBD_PVT_H_ +#ifndef _TUSB_USBD_PVT_H_ +#define _TUSB_USBD_PVT_H_ #include "osal/osal.h" #include "common/tusb_fifo.h" @@ -44,8 +44,7 @@ // Class Driver API //--------------------------------------------------------------------+ -typedef struct -{ +typedef struct { #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL char const* name; #endif @@ -111,8 +110,7 @@ bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endp // Check if endpoint is ready (not busy and not stalled) TU_ATTR_ALWAYS_INLINE static inline -bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr) -{ +bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr) { return !usbd_edpt_busy(rhport, ep_addr) && !usbd_edpt_stalled(rhport, ep_addr); } @@ -124,11 +122,10 @@ void usbd_sof_enable(uint8_t rhport, bool en); *------------------------------------------------------------------*/ bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in); -void usbd_defer_func( osal_task_func_t func, void* param, bool in_isr ); - +void usbd_defer_func(osal_task_func_t func, void *param, bool in_isr); #ifdef __cplusplus } #endif -#endif /* USBD_PVT_H_ */ +#endif diff --git a/src/host/usbh.c b/src/host/usbh.c index bacb3a719..e60e680c2 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -583,7 +583,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr, (xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ? tu_str_std_request[xfer->setup->bRequest] : "Class Request"); - TU_LOG_PTR(CFG_TUH_LOG_LEVEL, xfer->setup); + TU_LOG_BUF(CFG_TUH_LOG_LEVEL, xfer->setup, 8); TU_LOG_USBH("\r\n"); if (xfer->complete_cb) { @@ -660,10 +660,8 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result if (XFER_RESULT_SUCCESS != result) { TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes); - #if CFG_TUSB_DEBUG == 1 - TU_LOG1_PTR(request); + TU_LOG1_BUF(request, 8); TU_LOG1("\r\n"); - #endif // terminate transfer if any stage failed _xfer_complete(dev_addr, result); -- cgit v1.3.1 From 21ab40bab2e2fee28fa595f648a17944696c3d65 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 7 Sep 2023 12:38:18 +0700 Subject: - wrap up hcd max3421, work well with nrf52840 - also add usbh_defer_func() --- hw/bsp/nrf/family.c | 7 ++++-- src/host/usbh.c | 26 ++++++++++++---------- src/host/usbh_pvt.h | 10 ++++----- src/portable/analog/max3421/hcd_max3421.c | 36 ++----------------------------- 4 files changed, 27 insertions(+), 52 deletions(-) (limited to 'src') diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index 7358458ce..39ce179e8 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -109,10 +109,12 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { void tuh_max3421e_int_api(uint8_t rhport, bool enabled) { (void) rhport; + // use NVIC_Enable/Disable instead since nrfx_gpiote_trigger_enable/disable clear pending and can miss interrupt + // when disabled if (enabled) { - nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true); + NVIC_EnableIRQ(GPIOTE_IRQn); } else { - nrfx_gpiote_trigger_disable(MAX3241E_INTR_PIN); + NVIC_DisableIRQ(GPIOTE_IRQn); } } @@ -266,6 +268,7 @@ void board_init(void) { in_config.pull = NRF_GPIO_PIN_PULLUP; nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max3421e_int_handler); + nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true); #endif } diff --git a/src/host/usbh.c b/src/host/usbh.c index e60e680c2..e332f35cc 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -753,29 +753,33 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) { // USBH API For Class Driver //--------------------------------------------------------------------+ -uint8_t usbh_get_rhport(uint8_t dev_addr) -{ - usbh_device_t* dev = get_device(dev_addr); +uint8_t usbh_get_rhport(uint8_t dev_addr) { + usbh_device_t *dev = get_device(dev_addr); return dev ? dev->rhport : _dev0.rhport; } -uint8_t* usbh_get_enum_buf(void) -{ +uint8_t *usbh_get_enum_buf(void) { return _usbh_ctrl_buf; } -void usbh_int_set(bool enabled) -{ +void usbh_int_set(bool enabled) { // TODO all host controller if multiple are used since they shared the same event queue - if (enabled) - { + if (enabled) { hcd_int_enable(_usbh_controller); - }else - { + } else { hcd_int_disable(_usbh_controller); } } +void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr) { + hcd_event_t event = { 0 }; + event.event_id = USBH_EVENT_FUNC_CALL; + event.func_call.func = func; + event.func_call.param = param; + + osal_queue_send(_usbh_q, &event, in_isr); +} + //--------------------------------------------------------------------+ // Endpoint API //--------------------------------------------------------------------+ diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h index 0b58a91bc..2b61a77db 100644 --- a/src/host/usbh_pvt.h +++ b/src/host/usbh_pvt.h @@ -24,8 +24,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef _TUSB_USBH_CLASSDRIVER_H_ -#define _TUSB_USBH_CLASSDRIVER_H_ +#ifndef _TUSB_USBH_PVT_H_ +#define _TUSB_USBH_PVT_H_ #include "osal/osal.h" #include "common/tusb_fifo.h" @@ -76,6 +76,8 @@ uint8_t* usbh_get_enum_buf(void); void usbh_int_set(bool enabled); +void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr); + //--------------------------------------------------------------------+ // USBH Endpoint API //--------------------------------------------------------------------+ @@ -85,12 +87,10 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b tuh_xfer_cb_t complete_cb, uintptr_t user_data); TU_ATTR_ALWAYS_INLINE -static inline bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) -{ +static inline bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) { return usbh_edpt_xfer_with_callback(dev_addr, ep_addr, buffer, total_bytes, NULL, 0); } - // Claim an endpoint before submitting a transfer. // If caller does not make any transfer, it must release endpoint for others. bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr); diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index c61389cb9..95cf5516e 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -194,7 +194,6 @@ typedef struct { uint8_t hxfr; atomic_flag busy; // busy transferring - volatile uint8_t intr_disable_count; volatile uint16_t frame_count; max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; // [0] is reserved for addr0 @@ -241,14 +240,6 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) { if (!in_isr) { tuh_max3421e_int_api(rhport, true); (void) osal_mutex_unlock(_hcd_data.spi_mutex); - - // when re-enable interrupt, we may miss INTR edge (usually via GPIO detection interrupt). - // It would be ok if we are operating since SOF will re-trigger interrupt. - // However, for CONDET_IRQ i.e host not operating therefore we need to manually handle it here. - if (_hcd_data.hirq & HIRQ_CONDET_IRQ) { - handle_connect_irq(rhport, false); - hirq_write(rhport, HIRQ_CONDET_IRQ, false); - } } } @@ -470,28 +461,13 @@ bool hcd_init(uint8_t rhport) { // Enable USB interrupt // Not actually enable GPIO interrupt, just set variable to prevent handler to process void hcd_int_enable (uint8_t rhport) { -// tuh_max3421e_int_api(rhport, true); - - (void) rhport; - if (_hcd_data.intr_disable_count) { - _hcd_data.intr_disable_count--; - } - - // when re-enable interrupt, we may miss INTR edge (usually via GPIO detection interrupt). - // It would be ok if we are operating since SOF will re-trigger interrupt. - // However, for CONDET_IRQ i.e host not operating therefore we need to manually handle it here. -// if (_hcd_data.hirq & HIRQ_CONDET_IRQ) { -// handle_connect_irq(rhport, false); -// hirq_write(rhport, HIRQ_CONDET_IRQ, false); -// } + tuh_max3421e_int_api(rhport, true); } // Disable USB interrupt // Not actually disable GPIO interrupt, just set variable to prevent handler to process void hcd_int_disable(uint8_t rhport) { - //tuh_max3421e_int_api(rhport, false); - (void) rhport; - _hcd_data.intr_disable_count++; + tuh_max3421e_int_api(rhport, false); } // Get frame number (1ms) @@ -896,14 +872,6 @@ void hcd_int_handler(uint8_t rhport) { _hcd_data.frame_count++; } - // interrupt is disabled by usbh task: only ack FRAME IRQ and skip the rest - if (_hcd_data.intr_disable_count) { - if (hirq & HIRQ_FRAME_IRQ) { - hirq_write(rhport, HIRQ_FRAME_IRQ, true); - } - return; - } - if (hirq & HIRQ_CONDET_IRQ) { handle_connect_irq(rhport, true); } -- cgit v1.3.1 From 7ce4cfa638a86bfabd7ce8147ea5468d69c1af21 Mon Sep 17 00:00:00 2001 From: maidnl Date: Fri, 8 Sep 2023 10:12:03 +0200 Subject: renesas: added wait function for IN transaction This fixes a problem found on MSD class where data read from from disks were sometimes partially overwritten by the status MSD message ("USBS..."). The function introduced wait for the hw fifo pipe to be empty, that prevent that new writing in the fife overwrite data which are not yet be transmitted by hw. --- src/portable/renesas/rusb2/dcd_rusb2.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src') diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 3ec1b70b5..68ef5890f 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -266,6 +266,13 @@ static void pipe_read_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void tu_fifo_advance_write_pointer(f, count); } + +static void wait_pipe_fifo_empty(rusb2_reg_t* rusb, uint8_t num) { + TU_ASSERT(num); + while( (rusb->PIPE_CTR[num-1] & RUSB2_PIPE_CTR_INBUFM_Msk) > 0 ) {} +} + + //--------------------------------------------------------------------+ // Pipe Transfer //--------------------------------------------------------------------+ @@ -339,6 +346,7 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num) const unsigned rem = pipe->remaining; if (!rem) { + wait_pipe_fifo_empty(rusb, num); pipe->buf = NULL; return true; } -- cgit v1.3.1 From 228acbeac2642534753beffd866db2a7eab45e31 Mon Sep 17 00:00:00 2001 From: maidnl Date: Fri, 8 Sep 2023 15:48:05 +0200 Subject: wait_pipe_fifo_empty() now returns bool (as expected using TU_ASSERT macro) --- src/portable/renesas/rusb2/dcd_rusb2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 68ef5890f..24edc30e7 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -267,9 +267,10 @@ static void pipe_read_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void } -static void wait_pipe_fifo_empty(rusb2_reg_t* rusb, uint8_t num) { +static bool wait_pipe_fifo_empty(rusb2_reg_t* rusb, uint8_t num) { TU_ASSERT(num); while( (rusb->PIPE_CTR[num-1] & RUSB2_PIPE_CTR_INBUFM_Msk) > 0 ) {} + return true; } -- cgit v1.3.1 From c074488f75522c7c29dc7853aa2d8597b4858f89 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 9 Sep 2023 12:20:16 +0700 Subject: minor rename --- hw/bsp/nrf/boards/feather_nrf52840_express/board.h | 10 +- hw/bsp/nrf/boards/pca10056/board.h | 10 +- hw/bsp/nrf/boards/pca10095/board.h | 10 +- hw/bsp/nrf/family.c | 22 +-- hw/bsp/samd51/boards/metro_m4_express/board.h | 12 +- hw/bsp/samd51/family.c | 183 +++++++++++---------- src/portable/analog/max3421/hcd_max3421.c | 14 +- 7 files changed, 131 insertions(+), 130 deletions(-) (limited to 'src') diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h index e6e7590ac..76100a14a 100644 --- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h +++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h @@ -46,11 +46,11 @@ #define UART_TX_PIN 25 // SPI for USB host shield -#define MAX3421E_SCK_PIN 14 -#define MAX3421E_MOSI_PIN 13 -#define MAX3421E_MISO_PIN 15 -#define MAX3421E_CS_PIN 27 -#define MAX3241E_INTR_PIN 26 +#define MAX3421_SCK_PIN 14 +#define MAX3421_MOSI_PIN 13 +#define MAX3421_MISO_PIN 15 +#define MAX3421_CS_PIN 27 +#define MAX3421_INTR_PIN 26 #ifdef __cplusplus } diff --git a/hw/bsp/nrf/boards/pca10056/board.h b/hw/bsp/nrf/boards/pca10056/board.h index 16d31addb..9459e7911 100644 --- a/hw/bsp/nrf/boards/pca10056/board.h +++ b/hw/bsp/nrf/boards/pca10056/board.h @@ -46,11 +46,11 @@ #define UART_TX_PIN 6 // SPI for USB host shield -#define MAX3421E_SCK_PIN _PINNUM(1, 15) -#define MAX3421E_MOSI_PIN _PINNUM(1, 13) -#define MAX3421E_MISO_PIN _PINNUM(1, 14) -#define MAX3421E_CS_PIN _PINNUM(1, 12) -#define MAX3241E_INTR_PIN _PINNUM(1, 11) +#define MAX3421_SCK_PIN _PINNUM(1, 15) +#define MAX3421_MOSI_PIN _PINNUM(1, 13) +#define MAX3421_MISO_PIN _PINNUM(1, 14) +#define MAX3421_CS_PIN _PINNUM(1, 12) +#define MAX3421_INTR_PIN _PINNUM(1, 11) #ifdef __cplusplus } diff --git a/hw/bsp/nrf/boards/pca10095/board.h b/hw/bsp/nrf/boards/pca10095/board.h index b9d3a19dc..ad3379bf6 100644 --- a/hw/bsp/nrf/boards/pca10095/board.h +++ b/hw/bsp/nrf/boards/pca10095/board.h @@ -46,11 +46,11 @@ #define UART_TX_PIN 33 // SPI for USB host shield -#define MAX3421E_SCK_PIN _PINNUM(1, 15) -#define MAX3421E_MOSI_PIN _PINNUM(1, 13) -#define MAX3421E_MISO_PIN _PINNUM(1, 14) -#define MAX3421E_CS_PIN _PINNUM(1, 12) -#define MAX3241E_INTR_PIN _PINNUM(1, 11) +#define MAX3421_SCK_PIN _PINNUM(1, 15) +#define MAX3421_MOSI_PIN _PINNUM(1, 13) +#define MAX3421_MISO_PIN _PINNUM(1, 14) +#define MAX3421_CS_PIN _PINNUM(1, 12) +#define MAX3421_INTR_PIN _PINNUM(1, 11) #ifdef __cplusplus } diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index 47c765a96..6fcfd9476 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -97,8 +97,8 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) { #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1); -void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { - if (!(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return; +void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { + if (!(pin == MAX3421_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return; tuh_int_handler(1); } @@ -207,14 +207,14 @@ void board_init(void) { #endif // manually manage CS - nrf_gpio_cfg_output(MAX3421E_CS_PIN); - nrf_gpio_pin_write(MAX3421E_CS_PIN, 1); + nrf_gpio_cfg_output(MAX3421_CS_PIN); + nrf_gpio_pin_write(MAX3421_CS_PIN, 1); // USB host using max3421e usb controller via SPI nrfx_spim_config_t cfg = { - .sck_pin = MAX3421E_SCK_PIN, - .mosi_pin = MAX3421E_MOSI_PIN, - .miso_pin = MAX3421E_MISO_PIN, + .sck_pin = MAX3421_SCK_PIN, + .mosi_pin = MAX3421_MOSI_PIN, + .miso_pin = MAX3421_MISO_PIN, .ss_pin = NRFX_SPIM_PIN_NOT_USED, .ss_active_high = false, .irq_priority = 3, @@ -233,8 +233,8 @@ void board_init(void) { nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true); in_config.pull = NRF_GPIO_PIN_PULLUP; - nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max3421e_int_handler); - nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true); + nrfx_gpiote_in_init(MAX3421_INTR_PIN, &in_config, max3421_int_handler); + nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true); #endif } @@ -317,7 +317,7 @@ void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) { //--------------------------------------------------------------------+ #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 -void tuh_max3421e_int_api(uint8_t rhport, bool enabled) { +void tuh_max3421_int_api(uint8_t rhport, bool enabled) { (void) rhport; // use NVIC_Enable/Disable instead since nrfx_gpiote_trigger_enable/disable clear pending and can miss interrupt @@ -331,7 +331,7 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled) { void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) { (void) rhport; - nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1); + nrf_gpio_pin_write(MAX3421_CS_PIN, active ? 0 : 1); } bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) { diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.h b/hw/bsp/samd51/boards/metro_m4_express/board.h index 3441d03e9..fe2a867a4 100644 --- a/hw/bsp/samd51/boards/metro_m4_express/board.h +++ b/hw/bsp/samd51/boards/metro_m4_express/board.h @@ -44,12 +44,12 @@ #define UART_RX_PIN 22 // SPI for USB host shield -#define MAX3421E_SERCOM SERCOM2 -#define MAX3421E_SCK_PIN 13 -#define MAX3421E_MOSI_PIN 12 -#define MAX3421E_MISO_PIN 14 -#define MAX3421E_CS_PIN 18 // D10 -#define MAX3241E_INTR_PIN 20 // D9 +#define MAX3421_SERCOM 2 // SERCOM2 +#define MAX3421_SCK_PIN 13 +#define MAX3421_MOSI_PIN 12 +#define MAX3421_MISO_PIN 14 +#define MAX3421_CS_PIN 18 // D10 +#define MAX3421_INTR_PIN 20 // D9 #ifdef __cplusplus diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c index 51cfd19ba..34dd93cef 100644 --- a/hw/bsp/samd51/family.c +++ b/hw/bsp/samd51/family.c @@ -73,58 +73,14 @@ void USB_3_Handler(void) { } //--------------------------------------------------------------------+ -// +// Implementation //--------------------------------------------------------------------+ #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 -void max3421_init(void) -{ - //------------- SPI Init -------------// - - // Enable the APB clock for SERCOM2 - MCLK->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2; - - // Configure GCLK for SERCOM2, initClockNVIC() - GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); - GCLK->PCHCTRL[SERCOM2_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); +static void max3421_init(void); - // Disable the SPI module - SERCOM2->SPI.CTRLA.bit.ENABLE = 0; - - // Reset the SPI module - SERCOM2->SPI.CTRLA.bit.SWRST = 1; - while (SERCOM2->SPI.SYNCBUSY.bit.SWRST); +//#define - // Set up SPI in master mode, MSB first, SPI mode 0 - uint8_t const mosi_pad = 0; - uint8_t const miso_pad = 2; - SERCOM2->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE(3) | SERCOM_SPI_CTRLA_DOPO(mosi_pad) | SERCOM_SPI_CTRLA_DIPO(miso_pad); - - SERCOM2->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN; - while( SERCOM2->SPI.SYNCBUSY.bit.CTRLB == 1 ); - - // Set the baud rate - uint32_t baudrate = 4000000u; - SERCOM2->SPI.BAUD.reg = (uint8_t)(SystemCoreClock / (2 * baudrate) - 1); // Replace 1000000 with your desired baud rate - - // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2) - // 2 function C: PIO_SERCOM - gpio_set_pin_direction(MAX3421E_SCK_PIN, GPIO_DIRECTION_OUT); - gpio_set_pin_pull_mode(MAX3421E_SCK_PIN, GPIO_PULL_OFF); - gpio_set_pin_function(MAX3421E_SCK_PIN, 2); - - gpio_set_pin_direction(MAX3421E_MOSI_PIN, GPIO_DIRECTION_OUT); - gpio_set_pin_pull_mode(MAX3421E_MOSI_PIN, GPIO_PULL_OFF); - gpio_set_pin_function(MAX3421E_MOSI_PIN, 2); - - gpio_set_pin_direction(MAX3421E_MISO_PIN, GPIO_DIRECTION_IN); - gpio_set_pin_pull_mode(MAX3421E_MISO_PIN, GPIO_PULL_OFF); - gpio_set_pin_function(MAX3421E_MISO_PIN, 2); - - // Enable the SPI module - SERCOM2->SPI.CTRLA.bit.ENABLE = 1; - while (SERCOM2->SPI.SYNCBUSY.bit.ENABLE); -} #endif void board_init(void) { @@ -180,46 +136,7 @@ void board_init(void) { gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP); #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 - // CS pin - gpio_set_pin_direction(MAX3421E_CS_PIN, GPIO_DIRECTION_OUT); - gpio_set_pin_level(MAX3421E_CS_PIN, 1); - - // SPI max3421_init(); - - // INT pin with external interrupt - gpio_set_pin_direction(MAX3241E_INTR_PIN, GPIO_DIRECTION_IN); - gpio_set_pin_pull_mode(MAX3241E_INTR_PIN, GPIO_PULL_UP); - - // Enable the APB clock for EIC (External Interrupt Controller) - MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC; - - // Configure GCLK for EIC - GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); - - // Configure PA20 as an input - PORT->Group[0].DIRCLR.reg = PORT_PA20; - PORT->Group[0].PINCFG[20].reg = PORT_PINCFG_INEN | PORT_PINCFG_PULLEN; - PORT->Group[0].OUTSET.reg = PORT_PA20; // Enable pull-up - - // Configure PA20 to use EIC - PORT->Group[0].PMUX[10].bit.PMUXE = MUX_PA20A_EIC_EXTINT4; - PORT->Group[0].PINCFG[20].bit.PMUXEN = 1; - - // Disable EIC - EIC->CTRLA.bit.ENABLE = 0; - while (EIC->SYNCBUSY.bit.ENABLE); - - // Configure EXTINT4 (PA20) to trigger on falling edge - EIC->CONFIG[0].reg |= EIC_CONFIG_SENSE4_FALL; - - // Enable EXTINT4 - EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << 4); - - // Enable EIC - EIC->CTRLA.bit.ENABLE = 1; - while (EIC->SYNCBUSY.bit.ENABLE); - #endif } @@ -264,8 +181,91 @@ uint32_t board_millis(void) { //--------------------------------------------------------------------+ #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 -void EIC_4_Handler(void) -{ +static void max3421_init(void) { + // CS pin + gpio_set_pin_direction(MAX3421_CS_PIN, GPIO_DIRECTION_OUT); + gpio_set_pin_level(MAX3421_CS_PIN, 1); + + //------------- SPI Init -------------// + + // Enable the APB clock for SERCOM2 + MCLK->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2; + + // Configure GCLK for SERCOM2, initClockNVIC() + GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); + GCLK->PCHCTRL[SERCOM2_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); + + // Disable the SPI module + SERCOM2->SPI.CTRLA.bit.ENABLE = 0; + + // Reset the SPI module + SERCOM2->SPI.CTRLA.bit.SWRST = 1; + while (SERCOM2->SPI.SYNCBUSY.bit.SWRST); + + // Set up SPI in master mode, MSB first, SPI mode 0 + uint8_t const mosi_pad = 0; + uint8_t const miso_pad = 2; + SERCOM2->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE(3) | SERCOM_SPI_CTRLA_DOPO(mosi_pad) | SERCOM_SPI_CTRLA_DIPO(miso_pad); + + SERCOM2->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN; + while (SERCOM2->SPI.SYNCBUSY.bit.CTRLB == 1); + + // Set the baud rate + uint32_t baudrate = 4000000u; + SERCOM2->SPI.BAUD.reg = (uint8_t) (SystemCoreClock / (2 * baudrate) - + 1); // Replace 1000000 with your desired baud rate + + // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2) + // 2 function C: PIO_SERCOM + gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT); + gpio_set_pin_pull_mode(MAX3421_SCK_PIN, GPIO_PULL_OFF); + gpio_set_pin_function(MAX3421_SCK_PIN, 2); + + gpio_set_pin_direction(MAX3421_MOSI_PIN, GPIO_DIRECTION_OUT); + gpio_set_pin_pull_mode(MAX3421_MOSI_PIN, GPIO_PULL_OFF); + gpio_set_pin_function(MAX3421_MOSI_PIN, 2); + + gpio_set_pin_direction(MAX3421_MISO_PIN, GPIO_DIRECTION_IN); + gpio_set_pin_pull_mode(MAX3421_MISO_PIN, GPIO_PULL_OFF); + gpio_set_pin_function(MAX3421_MISO_PIN, 2); + + // Enable the SPI module + SERCOM2->SPI.CTRLA.bit.ENABLE = 1; + while (SERCOM2->SPI.SYNCBUSY.bit.ENABLE); + + //------------- External Interrupt -------------// + + // INT pin with external interrupt + gpio_set_pin_direction(MAX3421_INTR_PIN, GPIO_DIRECTION_IN); + gpio_set_pin_pull_mode(MAX3421_INTR_PIN, GPIO_PULL_UP); + + // Enable the APB clock for EIC (External Interrupt Controller) + MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC; + + // Configure GCLK for EIC + GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); + + // Configure PA20 as an input with function A (external interrupt) + gpio_set_pin_direction(MAX3421_INTR_PIN, GPIO_DIRECTION_IN); + gpio_set_pin_pull_mode(MAX3421_INTR_PIN, GPIO_PULL_UP); + gpio_set_pin_function(MAX3421_INTR_PIN, 0); + + // Disable EIC + EIC->CTRLA.bit.ENABLE = 0; + while (EIC->SYNCBUSY.bit.ENABLE); + + // Configure EXTINT4 (PA20) to trigger on falling edge + EIC->CONFIG[0].reg |= EIC_CONFIG_SENSE4_FALL; + + // Enable EXTINT4 + EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << 4); + + // Enable EIC + EIC->CTRLA.bit.ENABLE = 1; + while (EIC->SYNCBUSY.bit.ENABLE); +} + +void EIC_4_Handler(void) { // Clear the interrupt flag EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << 4); @@ -273,7 +273,7 @@ void EIC_4_Handler(void) tuh_int_handler(1); } -void tuh_max3421e_int_api(uint8_t rhport, bool enabled) { +void tuh_max3421_int_api(uint8_t rhport, bool enabled) { (void) rhport; if (enabled) { @@ -285,7 +285,7 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled) { void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) { (void) rhport; - gpio_set_pin_level(MAX3421E_CS_PIN, active ? 0 : 1); + gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1); } bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) { @@ -299,7 +299,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l // Write data to be transmitted uint8_t data = 0x00; if (count < tx_len) { - data = tx_buf[count]; + data = tx_buf[count]; } SERCOM2->SPI.DATA.reg = (uint32_t) data; @@ -322,6 +322,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l return true; } + #endif #endif diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 95cf5516e..238b518a0 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -212,7 +212,7 @@ static max3421_data_t _hcd_data; void tuh_max3421_spi_cs_api(uint8_t rhport, bool active); bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len); -void tuh_max3421e_int_api(uint8_t rhport, bool enabled); +void tuh_max3421_int_api(uint8_t rhport, bool enabled); static void handle_connect_irq(uint8_t rhport, bool in_isr); static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr); @@ -225,7 +225,7 @@ static void max3421_spi_lock(uint8_t rhport, bool in_isr) { // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr if (!in_isr) { (void) osal_mutex_lock(_hcd_data.spi_mutex, OSAL_TIMEOUT_WAIT_FOREVER); - tuh_max3421e_int_api(rhport, false); + tuh_max3421_int_api(rhport, false); } // assert CS @@ -238,7 +238,7 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) { // mutex unlock and re-enable interrupt if (!in_isr) { - tuh_max3421e_int_api(rhport, true); + tuh_max3421_int_api(rhport, true); (void) osal_mutex_unlock(_hcd_data.spi_mutex); } } @@ -411,7 +411,7 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { bool hcd_init(uint8_t rhport) { (void) rhport; - tuh_max3421e_int_api(rhport, false); + tuh_max3421_int_api(rhport, false); tuh_max3421_spi_cs_api(rhport, false); TU_LOG2_INT(sizeof(max3421_ep_t)); @@ -450,7 +450,7 @@ bool hcd_init(uint8_t rhport) { // Enable IRQ hien_write(rhport, DEFAULT_HIEN, false); - tuh_max3421e_int_api(rhport, true); + tuh_max3421_int_api(rhport, true); // Enable Interrupt pin reg_write(rhport, CPUCTL_ADDR, CPUCTL_IE, false); @@ -461,13 +461,13 @@ bool hcd_init(uint8_t rhport) { // Enable USB interrupt // Not actually enable GPIO interrupt, just set variable to prevent handler to process void hcd_int_enable (uint8_t rhport) { - tuh_max3421e_int_api(rhport, true); + tuh_max3421_int_api(rhport, true); } // Disable USB interrupt // Not actually disable GPIO interrupt, just set variable to prevent handler to process void hcd_int_disable(uint8_t rhport) { - tuh_max3421e_int_api(rhport, false); + tuh_max3421_int_api(rhport, false); } // Get frame number (1ms) -- cgit v1.3.1 From 81cd9951080181234f20d81c831ca0595d499577 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 18 Sep 2023 22:15:31 +0700 Subject: add default CFG_TUH_MAX3421 = 0, default spi speed for samd21/samd51 to 12Mhz --- hw/bsp/samd21/family.c | 3 ++- hw/bsp/samd51/family.c | 11 +++++++++-- src/portable/analog/max3421/hcd_max3421.c | 2 +- src/tusb_option.h | 22 +++++++++++++--------- 4 files changed, 25 insertions(+), 13 deletions(-) (limited to 'src') diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c index cfe66b8dc..395155548 100644 --- a/hw/bsp/samd21/family.c +++ b/hw/bsp/samd21/family.c @@ -269,7 +269,8 @@ uint32_t board_millis(void) { static void max3421_init(void) { //------------- SPI Init -------------// - uint32_t const baudrate = 4000000u; + // MAX3421E max SPI clock is 26MHz however SAMD can only work reliably at 12 Mhz + uint32_t const baudrate = 12000000u; // Enable the APB clock for SERCOM PM->APBCMASK.reg |= 1u << (PM_APBCMASK_SERCOM0_Pos + MAX3421_SERCOM_ID); diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c index 2cf00c7af..c1b914a02 100644 --- a/hw/bsp/samd51/family.c +++ b/hw/bsp/samd51/family.c @@ -183,7 +183,9 @@ uint32_t board_millis(void) { static void max3421_init(void) { //------------- SPI Init -------------// - uint32_t const baudrate = 4000000u; + + // MAX3421E max SPI clock is 26MHz however SAMD can only work reliably at 12 Mhz + uint32_t const baudrate = 12000000u; struct { volatile uint32_t *mck_apb; @@ -229,7 +231,12 @@ static void max3421_init(void) { while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1); // Set the baud rate - sercom->SPI.BAUD.reg = (uint8_t) (SystemCoreClock / (2 * baudrate) - 1); + uint8_t baud_reg = (uint8_t) (SystemCoreClock / (2 * baudrate)); + if (baud_reg) { + baud_reg--; + } + + sercom->SPI.BAUD.reg = baud_reg; // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2), function C (sercom) gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT); diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 238b518a0..f3f76fd58 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -263,7 +263,7 @@ static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_is max3421_spi_lock(rhport, in_isr); - tuh_max3421_spi_xfer_api(rhport, ®, 1, &hirq, 0); + tuh_max3421_spi_xfer_api(rhport, ®, 1, &hirq, 1); _hcd_data.hirq = hirq; tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len); diff --git a/src/tusb_option.h b/src/tusb_option.h index c72117850..a41f5a07e 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -424,11 +424,11 @@ //------------- CLASS -------------// #ifndef CFG_TUH_HUB -#define CFG_TUH_HUB 0 + #define CFG_TUH_HUB 0 #endif #ifndef CFG_TUH_CDC -#define CFG_TUH_CDC 0 + #define CFG_TUH_CDC 0 #endif #ifndef CFG_TUH_CDC_FTDI @@ -442,34 +442,38 @@ #endif #ifndef CFG_TUH_HID -#define CFG_TUH_HID 0 + #define CFG_TUH_HID 0 #endif #ifndef CFG_TUH_MIDI -#define CFG_TUH_MIDI 0 + #define CFG_TUH_MIDI 0 #endif #ifndef CFG_TUH_MSC -#define CFG_TUH_MSC 0 + #define CFG_TUH_MSC 0 #endif #ifndef CFG_TUH_VENDOR -#define CFG_TUH_VENDOR 0 + #define CFG_TUH_VENDOR 0 #endif #ifndef CFG_TUH_API_EDPT_XFER -#define CFG_TUH_API_EDPT_XFER 0 + #define CFG_TUH_API_EDPT_XFER 0 #endif // Enable PIO-USB software host controller #ifndef CFG_TUH_RPI_PIO_USB -#define CFG_TUH_RPI_PIO_USB 0 + #define CFG_TUH_RPI_PIO_USB 0 #endif #ifndef CFG_TUD_RPI_PIO_USB -#define CFG_TUD_RPI_PIO_USB 0 + #define CFG_TUD_RPI_PIO_USB 0 #endif +// MAX3421 Host controller option +#ifndef CFG_TUH_MAX3421 + #define CFG_TUH_MAX3421 0 +#endif //--------------------------------------------------------------------+ // TypeC Options (Default) -- cgit v1.3.1 From 9d0251f7a6751a0d998da4fad81a35a043608275 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Tue, 19 Sep 2023 15:42:52 +0200 Subject: Fix UAC interleaved copy. --- src/class/audio/audio_device.c | 113 +++++++++++++++++++---------------------- 1 file changed, 51 insertions(+), 62 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 1a7ce7870..0e4220f4f 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -631,68 +631,59 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t // Decoding according to 2.3.1.5 Audio Streams // Helper function -static inline uint8_t * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, void * dst, uint8_t * dst_end, uint8_t * src, uint8_t const n_ff_used) +static inline uint8_t * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, uint8_t * dst, uint8_t * dst_end, uint8_t * src, uint8_t const n_ff_used) { - // This function is an optimized version of - // while((uint8_t *)dst < dst_end) - // { - // memcpy(dst, src, nBytesToCopy); - // dst = (uint8_t *)dst + nBytesToCopy; - // src += nBytesToCopy * n_ff_used; - // } - - // Optimize for fast half word copies - typedef struct{ - uint16_t val; - } __attribute((__packed__)) unaligned_uint16_t; - - // Optimize for fast word copies - typedef struct{ - uint32_t val; - } __attribute((__packed__)) unaligned_uint32_t; + // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2) switch (nBytesToCopy) { case 1: while((uint8_t *)dst < dst_end) { - *(uint8_t *)dst++ = *src; - src += n_ff_used; + *(uint16_t*)dst = *(uint16_t*)src; + src += 2; + dst += 2; + src += 2 * (n_ff_used - 1); } break; case 2: while((uint8_t *)dst < dst_end) { - *(unaligned_uint16_t*)dst = *(unaligned_uint16_t*)src; - dst += 2; - src += 2 * n_ff_used; + *(uint32_t*)dst = *(uint32_t*)src; + src += 4; + dst += 4; + src += 4 * (n_ff_used - 1); } break; case 3: while((uint8_t *)dst < dst_end) { - // memcpy(dst, src, 3); - // dst = (uint8_t *)dst + 3; - // src += 3 * n_ff_used; - - // TODO: Is there a faster way to copy 3 bytes? - *(uint8_t *)dst++ = *src++; - *(uint8_t *)dst++ = *src++; - *(uint8_t *)dst++ = *src++; - - src += 3 * (n_ff_used - 1); + *(uint16_t*)dst = *(uint16_t*)src; + src += 2; + dst += 2; + *(uint16_t*)dst = *(uint16_t*)src; + src += 2; + dst += 2; + *(uint16_t*)dst = *(uint16_t*)src; + src += 2; + dst += 2; + src += 6 * (n_ff_used - 1); } break; case 4: while((uint8_t *)dst < dst_end) { - *(unaligned_uint32_t*)dst = *(unaligned_uint32_t*)src; + *(uint32_t*)dst++ = *(uint32_t*)src++; + src += 4; + dst += 4; + *(uint32_t*)dst++ = *(uint32_t*)src++; + src += 4; dst += 4; - src += 4 * n_ff_used; + src += 8 * (n_ff_used - 1); } break; } @@ -946,57 +937,55 @@ range [-1, +1) // Helper function static inline uint8_t * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesToCopy, uint8_t * src, uint8_t * src_end, uint8_t * dst, uint8_t const n_ff_used) { - // Optimize for fast half word copies - typedef struct{ - uint16_t val; - } __attribute((__packed__)) unaligned_uint16_t; - - // Optimize for fast word copies - typedef struct{ - uint32_t val; - } __attribute((__packed__)) unaligned_uint32_t; - + // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2) switch (nBytesToCopy) { case 1: while(src < src_end) { - *dst = *src++; - dst += n_ff_used; + *(uint16_t*)dst = *(uint16_t*)src; + src += 2; + dst += 2; + dst += 2 * (n_ff_used - 1); } break; case 2: while(src < src_end) { - *(unaligned_uint16_t*)dst = *(unaligned_uint16_t*)src; - src += 2; - dst += 2 * n_ff_used; + *(uint32_t*)dst = *(uint32_t*)src; + src += 4; + dst += 4; + dst += 4 * (n_ff_used - 1); } break; case 3: while(src < src_end) { - // memcpy(dst, src, 3); - // src = (uint8_t *)src + 3; - // dst += 3 * n_ff_used; - - // TODO: Is there a faster way to copy 3 bytes? - *dst++ = *src++; - *dst++ = *src++; - *dst++ = *src++; - - dst += 3 * (n_ff_used - 1); + *(uint16_t*)dst = *(uint16_t*)src; + src += 2; + dst += 2; + *(uint16_t*)dst = *(uint16_t*)src; + src += 2; + dst += 2; + *(uint16_t*)dst = *(uint16_t*)src; + src += 2; + dst += 2; + dst += 6 * (n_ff_used - 1); } break; case 4: while(src < src_end) { - *(unaligned_uint32_t*)dst = *(unaligned_uint32_t*)src; + *(uint32_t*)dst++ = *(uint32_t*)src++; + src += 4; + dst += 4; + *(uint32_t*)dst++ = *(uint32_t*)src++; src += 4; - dst += 4 * n_ff_used; + dst += 4; + dst += 8 * (n_ff_used - 1); } break; } -- cgit v1.3.1 From 6be7f354c26e09a87d1b856b0e237ff82be5963f Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Tue, 19 Sep 2023 16:32:49 +0200 Subject: Fix cast-align. --- src/class/audio/audio_device.c | 196 +++++++++++++++++++---------------------- 1 file changed, 90 insertions(+), 106 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 0e4220f4f..46fd6dfa9 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -631,64 +631,55 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t // Decoding according to 2.3.1.5 Audio Streams // Helper function -static inline uint8_t * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, uint8_t * dst, uint8_t * dst_end, uint8_t * src, uint8_t const n_ff_used) +static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, void * dst, const void * dst_end, void * src, uint8_t const n_ff_used) { - // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2) - - switch (nBytesToCopy) + uint16_t * dst16 = dst; + uint16_t * src16 = src; + const uint16_t * dst_end16 = dst_end; + uint32_t * dst32 = dst; + uint32_t * src32 = src; + const uint32_t * dst_end32 = dst_end; + + if (nBytesToCopy == 1) { - case 1: - while((uint8_t *)dst < dst_end) - { - *(uint16_t*)dst = *(uint16_t*)src; - src += 2; - dst += 2; - src += 2 * (n_ff_used - 1); - } - break; - - case 2: - while((uint8_t *)dst < dst_end) - { - *(uint32_t*)dst = *(uint32_t*)src; - src += 4; - dst += 4; - src += 4 * (n_ff_used - 1); - } - break; - - case 3: - while((uint8_t *)dst < dst_end) - { - *(uint16_t*)dst = *(uint16_t*)src; - src += 2; - dst += 2; - *(uint16_t*)dst = *(uint16_t*)src; - src += 2; - dst += 2; - *(uint16_t*)dst = *(uint16_t*)src; - src += 2; - dst += 2; - src += 6 * (n_ff_used - 1); - } - break; - - case 4: - while((uint8_t *)dst < dst_end) - { - *(uint32_t*)dst++ = *(uint32_t*)src++; - src += 4; - dst += 4; - *(uint32_t*)dst++ = *(uint32_t*)src++; - src += 4; - dst += 4; - src += 8 * (n_ff_used - 1); - } - break; + while(dst16 < dst_end16) + { + *dst16++ = *src16++; + src16 += n_ff_used - 1; + } + return src16; + } + else if (nBytesToCopy == 2) + { + while(dst32 < dst_end32) + { + *dst32++ = *src32++; + src32 += n_ff_used - 1; + } + return src32; + } + else if (nBytesToCopy == 3) + { + while(dst16 < dst_end16) + { + *dst16++ = *src16++; + *dst16++ = *src16++; + *dst16++ = *src16++; + src16 += 3 * (n_ff_used - 1); + } + return src16; + } + else // nBytesToCopy == 4 + { + while(dst32 < dst_end32) + { + *dst32++ = *src32++; + *dst32++ = *src32++; + src32 += 2 * (n_ff_used - 1); + } + return src32; } - - return src; } static bool audiod_decode_type_I_pcm(uint8_t rhport, audiod_function_t* audio, uint16_t n_bytes_received) @@ -935,62 +926,55 @@ range [-1, +1) * */ // Helper function -static inline uint8_t * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesToCopy, uint8_t * src, uint8_t * src_end, uint8_t * dst, uint8_t const n_ff_used) +static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesToCopy, void * src, const void * src_end, void * dst, uint8_t const n_ff_used) { // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2) - switch (nBytesToCopy) + uint16_t * dst16 = dst; + uint16_t * src16 = src; + const uint16_t * src_end16 = src_end; + uint32_t * dst32 = dst; + uint32_t * src32 = src; + const uint32_t * src_end32 = src_end; + + if (nBytesToCopy == 1) { - case 1: - while(src < src_end) - { - *(uint16_t*)dst = *(uint16_t*)src; - src += 2; - dst += 2; - dst += 2 * (n_ff_used - 1); - } - break; - - case 2: - while(src < src_end) - { - *(uint32_t*)dst = *(uint32_t*)src; - src += 4; - dst += 4; - dst += 4 * (n_ff_used - 1); - } - break; - - case 3: - while(src < src_end) - { - *(uint16_t*)dst = *(uint16_t*)src; - src += 2; - dst += 2; - *(uint16_t*)dst = *(uint16_t*)src; - src += 2; - dst += 2; - *(uint16_t*)dst = *(uint16_t*)src; - src += 2; - dst += 2; - dst += 6 * (n_ff_used - 1); - } - break; - - case 4: - while(src < src_end) - { - *(uint32_t*)dst++ = *(uint32_t*)src++; - src += 4; - dst += 4; - *(uint32_t*)dst++ = *(uint32_t*)src++; - src += 4; - dst += 4; - dst += 8 * (n_ff_used - 1); - } - break; + while(src16 < src_end16) + { + *dst16++ = *src16++; + dst16 += n_ff_used - 1; + } + return dst16; + } + else if (nBytesToCopy == 2) + { + while(src32 < src_end32) + { + *dst32++ = *src32++; + dst32 += n_ff_used - 1; + } + return dst32; + } + else if (nBytesToCopy == 3) + { + while(src16 < src_end16) + { + *dst16++ = *src16++; + *dst16++ = *src16++; + *dst16++ = *src16++; + dst16 += 3 * (n_ff_used - 1); + } + return dst16; + } + else // nBytesToCopy == 4 + { + while(src32 < src_end32) + { + *dst32++ = *src32++; + *dst32++ = *src32++; + dst32 += 2 * (n_ff_used - 1); + } + return dst32; } - - return dst; } static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audio) -- cgit v1.3.1 From a7c136c03f0c4a057f8b49c10ed9cddcecf52879 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 25 Sep 2023 16:53:11 +0700 Subject: adding host/cdc_msc_hid_freertos example --- .idea/cmake.xml | 19 +-- examples/device/cdc_msc_freertos/Makefile | 2 +- examples/device/cdc_msc_freertos/src/main.c | 70 ++++----- examples/host/bare_api/CMakeLists.txt | 5 + examples/host/cdc_msc_hid/CMakeLists.txt | 5 + examples/host/cdc_msc_hid_freertos/CMakeLists.txt | 36 +++++ .../host/cdc_msc_hid_freertos/src/CMakeLists.txt | 4 + examples/host/cdc_msc_hid_freertos/src/main.c | 170 +++++++++++++++++++++ .../host/cdc_msc_hid_freertos/src/tusb_config.h | 133 ++++++++++++++++ examples/host/hid_controller/CMakeLists.txt | 5 + examples/host/msc_file_explorer/CMakeLists.txt | 5 + examples/make.mk | 3 - .../boards/adafruit_metro_esp32s2/board.h | 8 + hw/bsp/espressif/boards/espressif_kaluga_1/board.h | 8 + .../boards/espressif_s2_devkitc/board.cmake | 2 + .../espressif/boards/espressif_s2_devkitc/board.h | 45 ++++++ hw/bsp/espressif/boards/family.c | 130 +++++++++++++--- .../components/tinyusb_src/CMakeLists.txt | 79 ++++++---- src/host/usbh.c | 2 +- src/portable/analog/max3421/hcd_max3421.c | 2 +- 20 files changed, 622 insertions(+), 111 deletions(-) create mode 100644 examples/host/cdc_msc_hid_freertos/CMakeLists.txt create mode 100644 examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt create mode 100644 examples/host/cdc_msc_hid_freertos/src/main.c create mode 100644 examples/host/cdc_msc_hid_freertos/src/tusb_config.h create mode 100644 hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake create mode 100644 hw/bsp/espressif/boards/espressif_s2_devkitc/board.h (limited to 'src') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 89ec1066c..747f0fb58 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -2,23 +2,24 @@ - + - - - - + + + + + + + + - - - @@ -53,7 +54,7 @@ - + diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile index 0bee668b7..3ac62a79c 100644 --- a/examples/device/cdc_msc_freertos/Makefile +++ b/examples/device/cdc_msc_freertos/Makefile @@ -10,7 +10,7 @@ INC += \ src/FreeRTOSConfig \ $(TOP)/hw \ $(TOP)/$(FREERTOS_SRC)/include \ - $(TOP)/$(FREERTOS_PORTABLE_SRC) + $(TOP)/$(FREERTOS_PORTABLE_SRC) \ # Example source EXAMPLE_SOURCE = \ diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index 0b115a595..1dadc4513 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -41,6 +41,7 @@ #define USBD_STACK_SIZE 4096 #else + #include "FreeRTOS.h" #include "semphr.h" #include "queue.h" @@ -54,7 +55,7 @@ #define CDC_STACK_SZIE configMINIMAL_STACK_SIZE //--------------------------------------------------------------------+ -// MACRO CONSTANT TYPEDEF PROTYPES +// MACRO CONSTANT TYPEDEF PROTOTYPES //--------------------------------------------------------------------+ /* Blink pattern @@ -62,7 +63,7 @@ * - 1000 ms : device mounted * - 2500 ms : device is suspended */ -enum { +enum { BLINK_NOT_MOUNTED = 250, BLINK_MOUNTED = 1000, BLINK_SUSPENDED = 2500, @@ -81,16 +82,15 @@ StaticTask_t cdc_taskdef; TimerHandle_t blinky_tm; -void led_blinky_cb(TimerHandle_t xTimer); -void usb_device_task(void* param); -void cdc_task(void* params); +static void led_blinky_cb(TimerHandle_t xTimer); +static void usb_device_task(void *param); +void cdc_task(void *params); //--------------------------------------------------------------------+ // Main //--------------------------------------------------------------------+ -int main(void) -{ +int main(void) { board_init(); #if configSUPPORT_STATIC_ALLOCATION @@ -104,8 +104,8 @@ int main(void) xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef); #else blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb); - xTaskCreate( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL); - xTaskCreate( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL); + xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL); + xTaskCreate(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL); #endif xTimerStart(blinky_tm, 0); @@ -119,16 +119,14 @@ int main(void) } #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) -void app_main(void) -{ +void app_main(void) { main(); } #endif // USB Device Driver task // This top level thread process all usb events and invoke callbacks -void usb_device_task(void* param) -{ +static void usb_device_task(void *param) { (void) param; // init device stack on configured roothub port @@ -141,8 +139,7 @@ void usb_device_task(void* param) } // RTOS forever loop - while (1) - { + while (1) { // put this thread to waiting state until there is new events tud_task(); @@ -156,35 +153,28 @@ void usb_device_task(void* param) //--------------------------------------------------------------------+ // Invoked when device is mounted -void tud_mount_cb(void) -{ +void tud_mount_cb(void) { xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0); } // Invoked when device is unmounted -void tud_umount_cb(void) -{ +void tud_umount_cb(void) { xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0); } // Invoked when usb bus is suspended // remote_wakeup_en : if host allow us to perform remote wakeup // Within 7ms, device must draw an average of current less than 2.5 mA from bus -void tud_suspend_cb(bool remote_wakeup_en) -{ +void tud_suspend_cb(bool remote_wakeup_en) { (void) remote_wakeup_en; xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_SUSPENDED), 0); } // Invoked when usb bus is resumed -void tud_resume_cb(void) -{ - if (tud_mounted()) - { +void tud_resume_cb(void) { + if (tud_mounted()) { xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0); - } - else - { + } else { xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0); } } @@ -192,20 +182,17 @@ void tud_resume_cb(void) //--------------------------------------------------------------------+ // USB CDC //--------------------------------------------------------------------+ -void cdc_task(void* params) -{ +void cdc_task(void *params) { (void) params; // RTOS forever loop - while ( 1 ) - { + while (1) { // connected() check for DTR bit // Most but not all terminal client set this when making connection // if ( tud_cdc_connected() ) { // There are data available - while ( tud_cdc_available() ) - { + while (tud_cdc_available()) { uint8_t buf[64]; // read and echo back @@ -228,32 +215,27 @@ void cdc_task(void* params) } // Invoked when cdc when line state changed e.g connected/disconnected -void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) -{ +void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) { (void) itf; (void) rts; // TODO set some indicator - if ( dtr ) - { + if (dtr) { // Terminal connected - }else - { + } else { // Terminal disconnected } } // Invoked when CDC interface received data from host -void tud_cdc_rx_cb(uint8_t itf) -{ +void tud_cdc_rx_cb(uint8_t itf) { (void) itf; } //--------------------------------------------------------------------+ // BLINKING TASK //--------------------------------------------------------------------+ -void led_blinky_cb(TimerHandle_t xTimer) -{ +static void led_blinky_cb(TimerHandle_t xTimer) { (void) xTimer; static bool led_state = false; diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt index 05398b079..76182d6fa 100644 --- a/examples/host/bare_api/CMakeLists.txt +++ b/examples/host/bare_api/CMakeLists.txt @@ -10,6 +10,11 @@ project(${PROJECT} C CXX ASM) # Checks this example is valid for the family and initializes the project family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) +# Espressif has its own cmake build system +if(FAMILY STREQUAL "espressif") + return() +endif() + add_executable(${PROJECT}) # Example source diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt index ad5751705..a7c372a34 100644 --- a/examples/host/cdc_msc_hid/CMakeLists.txt +++ b/examples/host/cdc_msc_hid/CMakeLists.txt @@ -10,6 +10,11 @@ project(${PROJECT} C CXX ASM) # Checks this example is valid for the family and initializes the project family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) +# Espressif has its own cmake build system +if(FAMILY STREQUAL "espressif") + return() +endif() + add_executable(${PROJECT}) # Example source diff --git a/examples/host/cdc_msc_hid_freertos/CMakeLists.txt b/examples/host/cdc_msc_hid_freertos/CMakeLists.txt new file mode 100644 index 000000000..2e95a18e0 --- /dev/null +++ b/examples/host/cdc_msc_hid_freertos/CMakeLists.txt @@ -0,0 +1,36 @@ +cmake_minimum_required(VERSION 3.17) + +include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) + +# gets PROJECT name for the example (e.g. -) +family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) + +project(${PROJECT} C CXX ASM) + +# Checks this example is valid for the family and initializes the project +family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) + +# Espressif has its own cmake build system +if(FAMILY STREQUAL "espressif") + return() +endif() + +add_executable(${PROJECT}) + +# Example source +target_sources(${PROJECT} PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/freertos_hook.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c + ) + +# Example include +target_include_directories(${PROJECT} PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) + +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_host_example(${PROJECT} freertos) diff --git a/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt new file mode 100644 index 000000000..dd7ec8e58 --- /dev/null +++ b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt @@ -0,0 +1,4 @@ +# This file is for ESP-IDF only +idf_component_register(SRCS "hid_app.c" "main.c" + INCLUDE_DIRS "." + REQUIRES boards tinyusb_src) diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c new file mode 100644 index 000000000..e2ddd52eb --- /dev/null +++ b/examples/host/cdc_msc_hid_freertos/src/main.c @@ -0,0 +1,170 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include +#include +#include + +#include "bsp/board_api.h" +#include "tusb.h" + +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) + // ESP-IDF need "freertos/" prefix in include path. + // CFG_TUSB_OS_INC_PATH should be defined accordingly. + #include "freertos/FreeRTOS.h" + #include "freertos/semphr.h" + #include "freertos/queue.h" + #include "freertos/task.h" + #include "freertos/timers.h" + + #define USBH_STACK_SIZE 4096 +#else + #include "FreeRTOS.h" + #include "semphr.h" + #include "queue.h" + #include "task.h" + #include "timers.h" + + // Increase stack size when debug log is enabled + #define USBH_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1) +#endif + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF PROTOTYPES +//--------------------------------------------------------------------+ +/* Blink pattern + * - 250 ms : device not mounted + * - 1000 ms : device mounted + * - 2500 ms : device is suspended + */ +enum { + BLINK_NOT_MOUNTED = 250, + BLINK_MOUNTED = 1000, + BLINK_SUSPENDED = 2500, +}; + +// static timer & task +#if configSUPPORT_STATIC_ALLOCATION +StaticTimer_t blinky_tmdef; + +StackType_t usb_host_stack[USBH_STACK_SIZE]; +StaticTask_t usb_host_taskdef; + +//StackType_t cdc_stack[CDC_STACK_SZIE]; +//StaticTask_t cdc_taskdef; +#endif + + +TimerHandle_t blinky_tm; + +static void led_blinky_cb(TimerHandle_t xTimer); +static void usb_host_task(void* param); + +extern void cdc_app_task(void); +extern void hid_app_task(void); + +/*------------- MAIN -------------*/ +int main(void) { + board_init(); + + printf("TinyUSB Host CDC MSC HID with FreeRTOS Example\r\n"); + +#if configSUPPORT_STATIC_ALLOCATION + // soft timer for blinky + blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef); + + // Create a task for tinyusb device stack + xTaskCreateStatic(usb_host_task, "usbh", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_host_stack, &usb_host_taskdef); + + // Create CDC task + //xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef); +#else + blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb); + xTaskCreate( usb_device_task, "usbd", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL); + //xTaskCreate( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL); +#endif + + xTimerStart(blinky_tm, 0); + + // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 +#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) + vTaskStartScheduler(); +#endif + + return 0; +} + +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) +void app_main(void) { + main(); +} +#endif + +// USB Host task +// This top level thread process all usb events and invoke callbacks +static void usb_host_task(void *param) { + (void) param; + + // init host stack on configured roothub port + tuh_init(BOARD_TUH_RHPORT); + + if (board_init_after_tusb) { + board_init_after_tusb(); + } + + // RTOS forever loop + while (1) { + // put this thread to waiting state until there is new events + tuh_task(); + + // following code only run if tuh_task() process at least 1 event + } +} + +//--------------------------------------------------------------------+ +// TinyUSB Callbacks +//--------------------------------------------------------------------+ + +void tuh_mount_cb(uint8_t dev_addr) { + // application set-up + printf("A device with address %d is mounted\r\n", dev_addr); +} + +void tuh_umount_cb(uint8_t dev_addr) { + // application tear-down + printf("A device with address %d is unmounted \r\n", dev_addr); +} + + +//--------------------------------------------------------------------+ +// BLINKING TASK +//--------------------------------------------------------------------+ +static void led_blinky_cb(TimerHandle_t xTimer) { + (void) xTimer; + static bool led_state = false; + + board_led_write(led_state); + led_state = 1 - led_state; // toggle +} diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h new file mode 100644 index 000000000..1bed9a9b3 --- /dev/null +++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h @@ -0,0 +1,133 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#ifndef _TUSB_CONFIG_H_ +#define _TUSB_CONFIG_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +//--------------------------------------------------------------------+ +// Board Specific Configuration +//--------------------------------------------------------------------+ + +#if CFG_TUSB_MCU == OPT_MCU_RP2040 + // change to 1 if using pico-pio-usb as host controller for raspberry rp2040 + #define CFG_TUH_RPI_PIO_USB 0 + #define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_USB +#endif + +// RHPort number used for host can be defined by board.mk, default to port 0 +#ifndef BOARD_TUH_RHPORT +#define BOARD_TUH_RHPORT 0 +#endif + +// RHPort max operational speed can defined by board.mk +#ifndef BOARD_TUH_MAX_SPEED +#define BOARD_TUH_MAX_SPEED OPT_MODE_DEFAULT_SPEED +#endif + +//-------------------------------------------------------------------- +// COMMON CONFIGURATION +//-------------------------------------------------------------------- + +// defined by compiler flags for flexibility +#ifndef CFG_TUSB_MCU +#error CFG_TUSB_MCU must be defined +#endif + +#ifndef CFG_TUSB_OS +#define CFG_TUSB_OS OPT_OS_FREERTOS +#endif + +// Espressif IDF requires "freertos/" prefix in include path +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) +#define CFG_TUSB_OS_INC_PATH freertos/ +#endif + +#ifndef CFG_TUSB_DEBUG +#define CFG_TUSB_DEBUG 0 +#endif + +// Enable Host stack +#define CFG_TUH_ENABLED 1 + +// Default is max speed that hardware controller could support with on-chip PHY +#define CFG_TUH_MAX_SPEED BOARD_TUH_MAX_SPEED + +/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. + * Tinyusb use follows macros to declare transferring memory so that they can be put + * into those specific section. + * e.g + * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) + * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) + */ +#ifndef CFG_TUH_MEM_SECTION +#define CFG_TUH_MEM_SECTION +#endif + +#ifndef CFG_TUH_MEM_ALIGN +#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// CONFIGURATION +//-------------------------------------------------------------------- + +// Size of buffer to hold descriptors and other data used for enumeration +#define CFG_TUH_ENUMERATION_BUFSIZE 256 + +#define CFG_TUH_HUB 1 // number of supported hubs +#define CFG_TUH_CDC 1 // CDC ACM +#define CFG_TUH_CDC_FTDI 1 // FTDI Serial. FTDI is not part of CDC class, only to re-use CDC driver API +#define CFG_TUH_CDC_CP210X 1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API +#define CFG_TUH_HID (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces +#define CFG_TUH_MSC 1 +#define CFG_TUH_VENDOR 0 + +// max device support (excluding hub device): 1 hub typically has 4 ports +#define CFG_TUH_DEVICE_MAX (3*CFG_TUH_HUB + 1) + +//------------- HID -------------// +#define CFG_TUH_HID_EPIN_BUFSIZE 64 +#define CFG_TUH_HID_EPOUT_BUFSIZE 64 + +//------------- CDC -------------// + +// Set Line Control state on enumeration/mounted: +// DTR ( bit 0), RTS (bit 1) +#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM 0x03 + +// Set Line Coding on enumeration/mounted, value for cdc_line_coding_t +// bit rate = 115200, 1 stop bit, no parity, 8 bit data width +#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } + + +#ifdef __cplusplus + } +#endif + +#endif /* _TUSB_CONFIG_H_ */ diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt index 3fb630aaa..c1b500dd8 100644 --- a/examples/host/hid_controller/CMakeLists.txt +++ b/examples/host/hid_controller/CMakeLists.txt @@ -10,6 +10,11 @@ project(${PROJECT} C CXX ASM) # Checks this example is valid for the family and initializes the project family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) +# Espressif has its own cmake build system +if(FAMILY STREQUAL "espressif") + return() +endif() + add_executable(${PROJECT}) # Example source diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt index 1868b632e..1a57c7466 100644 --- a/examples/host/msc_file_explorer/CMakeLists.txt +++ b/examples/host/msc_file_explorer/CMakeLists.txt @@ -10,6 +10,11 @@ project(${PROJECT} C CXX ASM) # Checks this example is valid for the family and initializes the project family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) +# Espressif has its own cmake build system +if(FAMILY STREQUAL "espressif") + return() +endif() + add_executable(${PROJECT}) # Example source diff --git a/examples/make.mk b/examples/make.mk index 8fe4a3486..448d7883d 100644 --- a/examples/make.mk +++ b/examples/make.mk @@ -26,9 +26,6 @@ ifeq '$(findstring ;,$(PATH))' ';' CMDEXE := 1 # makefile shell commands should use syntax for DOS CMD, not unix sh -# Unfortunately, SHELL may point to sh or bash, which can't accept DOS syntax. -# We can't just use sh, because while sh and/or bash shell may be available, -# many Windows environments won't have utilities like realpath used below, so... # Force DOS command shell on Windows. SHELL := cmd.exe endif diff --git a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h index 2ec80ef47..44ff11aa0 100644 --- a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h +++ b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h @@ -36,6 +36,14 @@ #define BUTTON_PIN 0 #define BUTTON_STATE_ACTIVE 0 +// SPI for USB host shield +#define MAX3421_SPI_HOST SPI2_HOST +#define MAX3421_SCK_PIN 36 +#define MAX3421_MOSI_PIN 35 +#define MAX3421_MISO_PIN 37 +#define MAX3421_CS_PIN 15 +#define MAX3421_INTR_PIN 14 + #ifdef __cplusplus } #endif diff --git a/hw/bsp/espressif/boards/espressif_kaluga_1/board.h b/hw/bsp/espressif/boards/espressif_kaluga_1/board.h index 0acb9c439..613e6ae0c 100644 --- a/hw/bsp/espressif/boards/espressif_kaluga_1/board.h +++ b/hw/bsp/espressif/boards/espressif_kaluga_1/board.h @@ -37,6 +37,14 @@ #define BUTTON_PIN 0 #define BUTTON_STATE_ACTIVE 0 +// SPI for USB host shield +#define MAX3421_SPI_HOST SPI2_HOST +#define MAX3421_SCK_PIN 36 +#define MAX3421_MOSI_PIN 35 +#define MAX3421_MISO_PIN 37 +#define MAX3421_CS_PIN 15 +#define MAX3421_INTR_PIN 14 + #ifdef __cplusplus } #endif diff --git a/hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake new file mode 100644 index 000000000..abbdf7abc --- /dev/null +++ b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake @@ -0,0 +1,2 @@ +# Apply board specific content here +set(IDF_TARGET "esp32s2") diff --git a/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h new file mode 100644 index 000000000..e068efef9 --- /dev/null +++ b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h @@ -0,0 +1,45 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// Note: On the production version (v1.2) WS2812 is connected to GPIO 18, +// however earlier revision v1.1 WS2812 is connected to GPIO 17 +#define NEOPIXEL_PIN 18 + +#define BUTTON_PIN 0 +#define BUTTON_STATE_ACTIVE 0 + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index 8f857fb71..250b7001e 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -45,16 +45,19 @@ static led_strip_t *strip; #endif -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM DECLARATION -//--------------------------------------------------------------------+ +#if CFG_TUH_ENABLED && CFG_TUH_MAX3421 +#include "driver/spi_master.h" +static void max3421_init(void); +#endif static void configure_pins(usb_hal_context_t *usb); -// Initialize on-board peripherals : led, button, uart and USB -void board_init(void) -{ +//--------------------------------------------------------------------+ +// Implementation +//--------------------------------------------------------------------+ +// Initialize on-board peripherals : led, button, uart and USB +void board_init(void) { #ifdef NEOPIXEL_PIN #ifdef NEOPIXEL_POWER_PIN gpio_reset_pin(NEOPIXEL_POWER_PIN); @@ -79,23 +82,27 @@ void board_init(void) gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT); gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY); +#if CFG_TUD_ENABLED // USB Controller Hal init periph_module_reset(PERIPH_USB_MODULE); periph_module_enable(PERIPH_USB_MODULE); usb_hal_context_t hal = { - .use_external_phy = false // use built-in PHY + .use_external_phy = false // use built-in PHY }; usb_hal_init(&hal); configure_pins(&hal); +#endif + +#if CFG_TUH_ENABLED && CFG_TUH_MAX3421 + max3421_init(); +#endif } -static void configure_pins(usb_hal_context_t *usb) -{ +static void configure_pins(usb_hal_context_t *usb) { /* usb_periph_iopins currently configures USB_OTG as USB Device. * Introduce additional parameters in usb_hal_context_t when adding support - * for USB Host. - */ + * for USB Host. */ for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) { if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) { esp_rom_gpio_pad_select_gpio(iopin->pin); @@ -115,6 +122,7 @@ static void configure_pins(usb_hal_context_t *usb) esp_rom_gpio_pad_unhold(iopin->pin); } } + if (!usb->use_external_phy) { gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3); gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3); @@ -122,8 +130,7 @@ static void configure_pins(usb_hal_context_t *usb) } // Turn LED on or off -void board_led_write(bool state) -{ +void board_led_write(bool state) { #ifdef NEOPIXEL_PIN strip->set_pixel(strip, 0, (state ? 0x88 : 0x00), 0x00, 0x00); strip->refresh(strip, 100); @@ -132,21 +139,102 @@ void board_led_write(bool state) // Get the current state of button // a '1' means active (pressed), a '0' means inactive. -uint32_t board_button_read(void) -{ +uint32_t board_button_read(void) { return gpio_get_level(BUTTON_PIN) == BUTTON_STATE_ACTIVE; } // Get characters from UART -int board_uart_read(uint8_t* buf, int len) -{ - (void) buf; (void) len; +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; return 0; } // Send characters to UART -int board_uart_write(void const * buf, int len) -{ - (void) buf; (void) len; +int board_uart_write(void const *buf, int len) { + (void) buf; + (void) len; return 0; } + +//--------------------------------------------------------------------+ +// API: SPI transfer with MAX3421E, must be implemented by application +//--------------------------------------------------------------------+ +#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 + +static spi_device_handle_t max3421_spi; + +static void IRAM_ATTR max3421_isr_handler(void* arg) +{ + (void) arg; + //uint32_t gpio_num = (uint32_t) arg; + //xQueueSendFromISR(gpio_evt_queue, &gpio_num, NULL); + tuh_int_handler(1); +} + +static void max3421_init(void) { + // CS pin + gpio_set_direction(MAX3421_CS_PIN, GPIO_MODE_OUTPUT); + gpio_set_level(MAX3421_CS_PIN, 1); + + // SPI + spi_bus_config_t buscfg={ + .miso_io_num = MAX3421_MISO_PIN, + .mosi_io_num = MAX3421_MOSI_PIN, + .sclk_io_num = MAX3421_SCK_PIN, + .quadwp_io_num = -1, + .quadhd_io_num = -1, + .data4_io_num = -1, + .data5_io_num = -1, + .data6_io_num = -1, + .data7_io_num = -1, + .max_transfer_sz = 128 + }; + ESP_ERROR_CHECK( spi_bus_initialize(MAX3421_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO) ); + + spi_device_interface_config_t max3421_cfg = { + .command_bits = 8, + .mode = 0, + .clock_speed_hz = 4000000, // 26000000 + .spics_io_num = -1, // manual control CS + .queue_size = 1 + }; + ESP_ERROR_CHECK( spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi) ); + + // Interrupt pin +// gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT); +// gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE); +// +// gpio_install_isr_service(ESP_INTR_FLAG_EDGE); +// gpio_isr_handler_add(MAX3421_INTR_PIN, max3421_isr_handler, NULL); +} + +void tuh_max3421_int_api(uint8_t rhport, bool enabled) { + (void) rhport; + if (enabled) { + gpio_intr_enable(MAX3421_INTR_PIN); + } else { + gpio_intr_disable(MAX3421_INTR_PIN); + } +} + +void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) { + (void) rhport; + gpio_set_level(MAX3421_CS_PIN, active ? 0 : 1); +} + +bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) { + (void) rhport; + + spi_transaction_t xact = { + .length = tx_len, + .rxlength = rx_len, + .tx_buffer = tx_buf, + .rx_buffer = rx_buf + }; + + ESP_ERROR_CHECK(spi_device_transmit(max3421_spi, &xact)); + return true; +} + +#endif diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt index bf8e45be2..2a154a8ff 100644 --- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt +++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt @@ -16,40 +16,57 @@ else() return() endif() -list(APPEND compile_options - "-DCFG_TUSB_MCU=${tusb_mcu}" - "-DCFG_TUSB_OS=OPT_OS_FREERTOS" - #"-DCFG_TUSB_DEBUG=1" - ) +list(APPEND compile_definitions + CFG_TUSB_MCU=${tusb_mcu} + CFG_TUSB_OS=OPT_OS_FREERTOS + ) -idf_component_get_property(freertos_component_dir freertos COMPONENT_DIR) +list(APPEND srcs + # common + ${tusb_src}/tusb.c + ${tusb_src}/common/tusb_fifo.c + # device + ${tusb_src}/device/usbd.c + ${tusb_src}/device/usbd_control.c + ${tusb_src}/class/audio/audio_device.c + ${tusb_src}/class/cdc/cdc_device.c + ${tusb_src}/class/dfu/dfu_device.c + ${tusb_src}/class/dfu/dfu_rt_device.c + ${tusb_src}/class/hid/hid_device.c + ${tusb_src}/class/midi/midi_device.c + ${tusb_src}/class/msc/msc_device.c + ${tusb_src}/class/net/ecm_rndis_device.c + ${tusb_src}/class/net/ncm_device.c + ${tusb_src}/class/usbtmc/usbtmc_device.c + ${tusb_src}/class/vendor/vendor_device.c + ${tusb_src}/class/video/video_device.c + ${tusb_src}/portable/synopsys/dwc2/dcd_dwc2.c + # host + ${tusb_src}/host/usbh.c + ${tusb_src}/host/hub.c + ${tusb_src}/class/cdc/cdc_host.c + ${tusb_src}/class/hid/hid_host.c + ${tusb_src}/class/msc/msc_host.c + ${tusb_src}/class/vendor/vendor_host.c + ) -list(APPEND includes_public - "${tusb_src}" - # The FreeRTOS API include convention in tinyusb is different from esp-idf - #"${freertos_component_dir}/include/freertos" - ) +# use max3421 as host controller +if (MAX3421_HOST STREQUAL "1") + list(APPEND srcs ${tusb_src}/portable/analog/max3421/hcd_max3421.c) + list(APPEND compile_definitions CFG_TUH_MAX3421=1) +endif () -list(APPEND srcs - "${tusb_src}/tusb.c" - "${tusb_src}/common/tusb_fifo.c" - "${tusb_src}/device/usbd.c" - "${tusb_src}/device/usbd_control.c" - "${tusb_src}/class/cdc/cdc_device.c" - "${tusb_src}/class/dfu/dfu_rt_device.c" - "${tusb_src}/class/hid/hid_device.c" - "${tusb_src}/class/midi/midi_device.c" - "${tusb_src}/class/msc/msc_device.c" - "${tusb_src}/class/net/ecm_rndis_device.c" - "${tusb_src}/class/net/ncm_device.c" - "${tusb_src}/class/usbtmc/usbtmc_device.c" - "${tusb_src}/class/vendor/vendor_device.c" - "${tusb_src}/portable/synopsys/dwc2/dcd_dwc2.c" - ) +if (DEFINED LOG) + list(APPEND compile_definitions CFG_TUSB_DEBUG=${LOG}) + if (LOG STREQUAL "4") + # no inline for debug level 4 + list(APPEND compile_definitions TU_ATTR_ALWAYS_INLINE=) + endif () +endif() idf_component_register(SRCS ${srcs} - INCLUDE_DIRS ${includes_public} - REQUIRES src - ) + INCLUDE_DIRS ${tusb_src} + REQUIRES src + ) -target_compile_options(${COMPONENT_LIB} PUBLIC ${compile_options}) +target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions}) diff --git a/src/host/usbh.c b/src/host/usbh.c index e332f35cc..dc2831da3 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -659,7 +659,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result tusb_control_request_t const * request = &_ctrl_xfer.request; if (XFER_RESULT_SUCCESS != result) { - TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes); + TU_LOG1("[%u:%u] Control %s, xferred_bytes = %u\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes); TU_LOG1_BUF(request, 8); TU_LOG1("\r\n"); diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index f3f76fd58..3f6747404 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -882,7 +882,7 @@ void hcd_int_handler(uint8_t rhport) { if ( hirq & HIRQ_RCVDAV_IRQ ) { uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1); - uint8_t xact_len; + uint8_t xact_len = 0; // RCVDAV_IRQ can trigger 2 times (dual buffered) while ( hirq & HIRQ_RCVDAV_IRQ ) { -- cgit v1.3.1 From f6ca86c3ddeaec18f52b15f1065a5c9eea210c00 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Sep 2023 19:09:36 +0700 Subject: tested cdc_msc_hid_freertos with samd51 add -Wno-error=format for espressif wrap up cdc_msc_hid_freertos --- examples/host/cdc_msc_hid_freertos/Makefile | 32 +++ examples/host/cdc_msc_hid_freertos/only.txt | 13 + .../host/cdc_msc_hid_freertos/src/CMakeLists.txt | 4 +- examples/host/cdc_msc_hid_freertos/src/cdc_app.c | 109 +++++++++ .../host/cdc_msc_hid_freertos/src/freertos_hook.c | 111 +++++++++ examples/host/cdc_msc_hid_freertos/src/hid_app.c | 263 +++++++++++++++++++++ examples/host/cdc_msc_hid_freertos/src/main.c | 22 +- examples/host/cdc_msc_hid_freertos/src/msc_app.c | 67 ++++++ hw/bsp/espressif/boards/CMakeLists.txt | 2 + hw/bsp/espressif/boards/family.c | 39 +-- .../components/tinyusb_src/CMakeLists.txt | 1 + hw/bsp/nrf/family.c | 106 +++++---- hw/bsp/samd21/family.c | 9 +- hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/samd51/family.c | 8 +- src/host/usbh.c | 2 +- 16 files changed, 703 insertions(+), 87 deletions(-) create mode 100644 examples/host/cdc_msc_hid_freertos/Makefile create mode 100644 examples/host/cdc_msc_hid_freertos/only.txt create mode 100644 examples/host/cdc_msc_hid_freertos/src/cdc_app.c create mode 100644 examples/host/cdc_msc_hid_freertos/src/freertos_hook.c create mode 100644 examples/host/cdc_msc_hid_freertos/src/hid_app.c create mode 100644 examples/host/cdc_msc_hid_freertos/src/msc_app.c (limited to 'src') diff --git a/examples/host/cdc_msc_hid_freertos/Makefile b/examples/host/cdc_msc_hid_freertos/Makefile new file mode 100644 index 000000000..67bb6da55 --- /dev/null +++ b/examples/host/cdc_msc_hid_freertos/Makefile @@ -0,0 +1,32 @@ +include ../../make.mk + +FREERTOS_SRC = lib/FreeRTOS-Kernel +FREERTOS_PORTABLE_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC) + +INC += \ + src \ + $(TOP)/hw \ + $(TOP)/$(FREERTOS_SRC)/include \ + $(TOP)/$(FREERTOS_PORTABLE_SRC) \ + +# Example source +EXAMPLE_SOURCE = \ + src/cdc_app.c \ + src/freertos_hook.c \ + src/hid_app.c \ + src/main.c \ + src/msc_app.c \ + +SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) + +# TinyUSB Host Stack source +SRC_C += \ + src/class/cdc/cdc_host.c \ + src/class/hid/hid_host.c \ + src/class/msc/msc_host.c \ + src/host/hub.c \ + src/host/usbh.c \ + src/portable/ohci/ohci.c \ + src/portable/nxp/lpc17_40/hcd_lpc17_40.c + +include ../../rules.mk diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt new file mode 100644 index 000000000..3837ac8a2 --- /dev/null +++ b/examples/host/cdc_msc_hid_freertos/only.txt @@ -0,0 +1,13 @@ +mcu:LPC175X_6X +mcu:LPC177X_8X +mcu:LPC18XX +mcu:LPC40XX +mcu:LPC43XX +mcu:MIMXRT1XXX +mcu:MIMXRT10XX +mcu:MIMXRT11XX +mcu:RP2040 +mcu:MSP432E4 +mcu:RX65X +mcu:RAXXX +mcu:MAX3421 diff --git a/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt index dd7ec8e58..6f057c106 100644 --- a/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt +++ b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt @@ -1,4 +1,6 @@ # This file is for ESP-IDF only -idf_component_register(SRCS "hid_app.c" "main.c" +idf_component_register(SRCS "cdc_app.c" "hid_app.c" "main.c" "msc_app.c" INCLUDE_DIRS "." REQUIRES boards tinyusb_src) + +target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format) diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c new file mode 100644 index 000000000..fc2b1228d --- /dev/null +++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c @@ -0,0 +1,109 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2022, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb.h" +#include "bsp/board_api.h" + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ + + +//------------- IMPLEMENTATION -------------// + +size_t get_console_inputs(uint8_t *buf, size_t bufsize) { + size_t count = 0; + while (count < bufsize) { + int ch = board_getchar(); + if (ch <= 0) break; + + buf[count] = (uint8_t) ch; + count++; + } + + return count; +} + +void cdc_app_task(void* param) { + (void) param; + + uint8_t buf[64 + 1]; // +1 for extra null character + uint32_t const bufsize = sizeof(buf) - 1; + + while (1) { + uint32_t count = get_console_inputs(buf, bufsize); + buf[count] = 0; + + if (count) { + // loop over all mounted interfaces + for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) { + if (tuh_cdc_mounted(idx)) { + // console --> cdc interfaces + tuh_cdc_write(idx, buf, count); + tuh_cdc_write_flush(idx); + } + } + } + + taskYIELD(); + } +} + +// Invoked when received new data +void tuh_cdc_rx_cb(uint8_t idx) { + uint8_t buf[64 + 1]; // +1 for extra null character + uint32_t const bufsize = sizeof(buf) - 1; + + // forward cdc interfaces -> console + uint32_t count = tuh_cdc_read(idx, buf, bufsize); + buf[count] = 0; + + printf((char *) buf); +} + +void tuh_cdc_mount_cb(uint8_t idx) { + tuh_itf_info_t itf_info = { 0 }; + tuh_cdc_itf_get_info(idx, &itf_info); + + printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber); + +#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration + // otherwise you need to call tuh_cdc_set_line_coding() first + cdc_line_coding_t line_coding = { 0 }; + if (tuh_cdc_get_local_line_coding(idx, &line_coding)) { + printf(" Baudrate: %lu, Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits); + printf(" Parity : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits); + } +#endif +} + +void tuh_cdc_umount_cb(uint8_t idx) { + tuh_itf_info_t itf_info = { 0 }; + tuh_cdc_itf_get_info(idx, &itf_info); + + printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber); +} diff --git a/examples/host/cdc_msc_hid_freertos/src/freertos_hook.c b/examples/host/cdc_msc_hid_freertos/src/freertos_hook.c new file mode 100644 index 000000000..07d159fd5 --- /dev/null +++ b/examples/host/cdc_msc_hid_freertos/src/freertos_hook.c @@ -0,0 +1,111 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +//--------------------------------------------------------------------+ +// INCLUDE +//--------------------------------------------------------------------+ +#include "FreeRTOS.h" +#include "task.h" +#include "common/tusb_common.h" + +void vApplicationMallocFailedHook(void) { + taskDISABLE_INTERRUPTS(); + TU_ASSERT(false,); +} + +void vApplicationStackOverflowHook(xTaskHandle pxTask, char *pcTaskName) { + (void) pxTask; + (void) pcTaskName; + + taskDISABLE_INTERRUPTS(); + TU_ASSERT(false,); +} + +/* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must provide an + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, + uint32_t *pulIdleTaskStackSize) { + /* If the buffers to be provided to the Idle task are declared inside this + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[configMINIMAL_STACK_SIZE]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + Note that, as the array is necessarily of type StackType_t, + configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} + +/* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory(StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, + uint32_t *pulTimerTaskStackSize) { + /* If the buffers to be provided to the Timer task are declared inside this + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[configTIMER_TASK_STACK_DEPTH]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + Note that, as the array is necessarily of type StackType_t, + configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; +} + +#if CFG_TUSB_MCU == OPT_MCU_RX63X | CFG_TUSB_MCU == OPT_MCU_RX65X +#include "iodefine.h" +void vApplicationSetupTimerInterrupt(void) +{ + /* Enable CMT0 */ + SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1); + MSTP(CMT0) = 0; + SYSTEM.PRCR.WORD = (0xA5u<<8); + + CMT0.CMCNT = 0; + CMT0.CMCOR = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128); + CMT0.CMCR.WORD = TU_BIT(6) | 2; + IR(CMT0, CMI0) = 0; + IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY; + IEN(CMT0, CMI0) = 1; + CMT.CMSTR0.BIT.STR0 = 1; +} +#endif diff --git a/examples/host/cdc_msc_hid_freertos/src/hid_app.c b/examples/host/cdc_msc_hid_freertos/src/hid_app.c new file mode 100644 index 000000000..a2df3b909 --- /dev/null +++ b/examples/host/cdc_msc_hid_freertos/src/hid_app.c @@ -0,0 +1,263 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include "bsp/board_api.h" +#include "tusb.h" + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ + +// If your host terminal support ansi escape code such as TeraTerm +// it can be use to simulate mouse cursor movement within terminal +#define USE_ANSI_ESCAPE 0 + +#define MAX_REPORT 4 + +static uint8_t const keycode2ascii[128][2] = { HID_KEYCODE_TO_ASCII }; + +// Each HID instance can has multiple reports +static struct { + uint8_t report_count; + tuh_hid_report_info_t report_info[MAX_REPORT]; +} hid_info[CFG_TUH_HID]; + +static void process_kbd_report(hid_keyboard_report_t const *report); +static void process_mouse_report(hid_mouse_report_t const *report); +static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len); + +//--------------------------------------------------------------------+ +// TinyUSB Callbacks +//--------------------------------------------------------------------+ + +// Invoked when device with hid interface is mounted +// Report descriptor is also available for use. tuh_hid_parse_report_descriptor() +// can be used to parse common/simple enough descriptor. +// Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped +// therefore report_desc = NULL, desc_len = 0 +void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const *desc_report, uint16_t desc_len) { + printf("HID device address = %d, instance = %d is mounted\r\n", dev_addr, instance); + + // Interface protocol (hid_interface_protocol_enum_t) + const char *protocol_str[] = { "None", "Keyboard", "Mouse" }; + uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance); + + printf("HID Interface Protocol = %s\r\n", protocol_str[itf_protocol]); + + // By default host stack will use activate boot protocol on supported interface. + // Therefore for this simple example, we only need to parse generic report descriptor (with built-in parser) + if (itf_protocol == HID_ITF_PROTOCOL_NONE) { + hid_info[instance].report_count = tuh_hid_parse_report_descriptor(hid_info[instance].report_info, MAX_REPORT, + desc_report, desc_len); + printf("HID has %u reports \r\n", hid_info[instance].report_count); + } + + // request to receive report + // tuh_hid_report_received_cb() will be invoked when report is available + if (!tuh_hid_receive_report(dev_addr, instance)) { + printf("Error: cannot request to receive report\r\n"); + } +} + +// Invoked when device with hid interface is un-mounted +void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance) { + printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance); +} + +// Invoked when received report from device via interrupt endpoint +void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len) { + uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance); + + switch (itf_protocol) { + case HID_ITF_PROTOCOL_KEYBOARD: + TU_LOG2("HID receive boot keyboard report\r\n"); + process_kbd_report((hid_keyboard_report_t const *) report); + break; + + case HID_ITF_PROTOCOL_MOUSE: + TU_LOG2("HID receive boot mouse report\r\n"); + process_mouse_report((hid_mouse_report_t const *) report); + break; + + default: + // Generic report requires matching ReportID and contents with previous parsed report info + process_generic_report(dev_addr, instance, report, len); + break; + } + + // continue to request to receive report + if (!tuh_hid_receive_report(dev_addr, instance)) { + printf("Error: cannot request to receive report\r\n"); + } +} + +//--------------------------------------------------------------------+ +// Keyboard +//--------------------------------------------------------------------+ + +// look up new key in previous keys +static inline bool find_key_in_report(hid_keyboard_report_t const *report, uint8_t keycode) { + for (uint8_t i = 0; i < 6; i++) { + if (report->keycode[i] == keycode) return true; + } + + return false; +} + +static void process_kbd_report(hid_keyboard_report_t const *report) { + static hid_keyboard_report_t prev_report = { 0, 0, { 0 } }; // previous report to check key released + + //------------- example code ignore control (non-printable) key affects -------------// + for (uint8_t i = 0; i < 6; i++) { + if (report->keycode[i]) { + if (find_key_in_report(&prev_report, report->keycode[i])) { + // exist in previous report means the current key is holding + } else { + // not existed in previous report means the current key is pressed + bool const is_shift = report->modifier & (KEYBOARD_MODIFIER_LEFTSHIFT | KEYBOARD_MODIFIER_RIGHTSHIFT); + uint8_t ch = keycode2ascii[report->keycode[i]][is_shift ? 1 : 0]; + putchar(ch); + if (ch == '\r') putchar('\n'); // added new line for enter key + + #ifndef __ICCARM__ // TODO IAR doesn't support stream control ? + fflush(stdout); // flush right away, else nanolib will wait for newline + #endif + } + } + // TODO example skips key released + } + + prev_report = *report; +} + +//--------------------------------------------------------------------+ +// Mouse +//--------------------------------------------------------------------+ + +void cursor_movement(int8_t x, int8_t y, int8_t wheel) { +#if USE_ANSI_ESCAPE + // Move X using ansi escape + if ( x < 0) { + printf(ANSI_CURSOR_BACKWARD(%d), (-x)); // move left + }else if ( x > 0) { + printf(ANSI_CURSOR_FORWARD(%d), x); // move right + } + + // Move Y using ansi escape + if ( y < 0) { + printf(ANSI_CURSOR_UP(%d), (-y)); // move up + }else if ( y > 0) { + printf(ANSI_CURSOR_DOWN(%d), y); // move down + } + + // Scroll using ansi escape + if (wheel < 0) { + printf(ANSI_SCROLL_UP(%d), (-wheel)); // scroll up + }else if (wheel > 0) { + printf(ANSI_SCROLL_DOWN(%d), wheel); // scroll down + } + + printf("\r\n"); +#else + printf("(%d %d %d)\r\n", x, y, wheel); +#endif +} + +static void process_mouse_report(hid_mouse_report_t const *report) { + static hid_mouse_report_t prev_report = { 0 }; + + //------------- button state -------------// + uint8_t button_changed_mask = report->buttons ^ prev_report.buttons; + if (button_changed_mask & report->buttons) { + printf(" %c%c%c ", + report->buttons & MOUSE_BUTTON_LEFT ? 'L' : '-', + report->buttons & MOUSE_BUTTON_MIDDLE ? 'M' : '-', + report->buttons & MOUSE_BUTTON_RIGHT ? 'R' : '-'); + } + + //------------- cursor movement -------------// + cursor_movement(report->x, report->y, report->wheel); +} + +//--------------------------------------------------------------------+ +// Generic Report +//--------------------------------------------------------------------+ +static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len) { + (void) dev_addr; + + uint8_t const rpt_count = hid_info[instance].report_count; + tuh_hid_report_info_t *rpt_info_arr = hid_info[instance].report_info; + tuh_hid_report_info_t *rpt_info = NULL; + + if (rpt_count == 1 && rpt_info_arr[0].report_id == 0) { + // Simple report without report ID as 1st byte + rpt_info = &rpt_info_arr[0]; + } else { + // Composite report, 1st byte is report ID, data starts from 2nd byte + uint8_t const rpt_id = report[0]; + + // Find report id in the array + for (uint8_t i = 0; i < rpt_count; i++) { + if (rpt_id == rpt_info_arr[i].report_id) { + rpt_info = &rpt_info_arr[i]; + break; + } + } + + report++; + len--; + } + + if (!rpt_info) { + printf("Couldn't find report info !\r\n"); + return; + } + + // For complete list of Usage Page & Usage checkout src/class/hid/hid.h. For examples: + // - Keyboard : Desktop, Keyboard + // - Mouse : Desktop, Mouse + // - Gamepad : Desktop, Gamepad + // - Consumer Control (Media Key) : Consumer, Consumer Control + // - System Control (Power key) : Desktop, System Control + // - Generic (vendor) : 0xFFxx, xx + if (rpt_info->usage_page == HID_USAGE_PAGE_DESKTOP) { + switch (rpt_info->usage) { + case HID_USAGE_DESKTOP_KEYBOARD: + TU_LOG1("HID receive keyboard report\r\n"); + // Assume keyboard follow boot report layout + process_kbd_report((hid_keyboard_report_t const *) report); + break; + + case HID_USAGE_DESKTOP_MOUSE: + TU_LOG1("HID receive mouse report\r\n"); + // Assume mouse follow boot report layout + process_mouse_report((hid_mouse_report_t const *) report); + break; + + default: + break; + } + } +} diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c index e2ddd52eb..d5574789f 100644 --- a/examples/host/cdc_msc_hid_freertos/src/main.c +++ b/examples/host/cdc_msc_hid_freertos/src/main.c @@ -51,6 +51,8 @@ #define USBH_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1) #endif +#define CDC_STACK_SZIE (3*configMINIMAL_STACK_SIZE/2) + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTOTYPES //--------------------------------------------------------------------+ @@ -72,18 +74,16 @@ StaticTimer_t blinky_tmdef; StackType_t usb_host_stack[USBH_STACK_SIZE]; StaticTask_t usb_host_taskdef; -//StackType_t cdc_stack[CDC_STACK_SZIE]; -//StaticTask_t cdc_taskdef; +StackType_t cdc_stack[CDC_STACK_SZIE]; +StaticTask_t cdc_taskdef; #endif - TimerHandle_t blinky_tm; static void led_blinky_cb(TimerHandle_t xTimer); static void usb_host_task(void* param); -extern void cdc_app_task(void); -extern void hid_app_task(void); +extern void cdc_app_task(void* param); /*------------- MAIN -------------*/ int main(void) { @@ -91,19 +91,15 @@ int main(void) { printf("TinyUSB Host CDC MSC HID with FreeRTOS Example\r\n"); + // Create soft timer for blinky, task for tinyusb stack and CDC #if configSUPPORT_STATIC_ALLOCATION - // soft timer for blinky blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef); - - // Create a task for tinyusb device stack xTaskCreateStatic(usb_host_task, "usbh", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_host_stack, &usb_host_taskdef); - - // Create CDC task - //xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef); + xTaskCreateStatic(cdc_app_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef); #else blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb); - xTaskCreate( usb_device_task, "usbd", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL); - //xTaskCreate( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL); + xTaskCreate(usb_host_task, "usbd", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL); + xTaskCreate(cdc_app_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL); #endif xTimerStart(blinky_tm, 0); diff --git a/examples/host/cdc_msc_hid_freertos/src/msc_app.c b/examples/host/cdc_msc_hid_freertos/src/msc_app.c new file mode 100644 index 000000000..a8d6fbfaa --- /dev/null +++ b/examples/host/cdc_msc_hid_freertos/src/msc_app.c @@ -0,0 +1,67 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include "tusb.h" + +#if CFG_TUH_MSC + +static scsi_inquiry_resp_t inquiry_resp; + +bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const *cb_data) { + msc_cbw_t const *cbw = cb_data->cbw; + msc_csw_t const *csw = cb_data->csw; + + if (csw->status != 0) { + printf("Inquiry failed\r\n"); + return false; + } + + // Print out Vendor ID, Product ID and Rev + printf("%.8s %.16s rev %.4s\r\n", inquiry_resp.vendor_id, inquiry_resp.product_id, inquiry_resp.product_rev); + + // Get capacity of device + uint32_t const block_count = tuh_msc_get_block_count(dev_addr, cbw->lun); + uint32_t const block_size = tuh_msc_get_block_size(dev_addr, cbw->lun); + + printf("Disk Size: %lu MB\r\n", block_count / ((1024 * 1024) / block_size)); + printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size); + + return true; +} + +//------------- IMPLEMENTATION -------------// +void tuh_msc_mount_cb(uint8_t dev_addr) { + printf("A MassStorage device is mounted\r\n"); + + uint8_t const lun = 0; + tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb, 0); +} + +void tuh_msc_umount_cb(uint8_t dev_addr) { + (void) dev_addr; + printf("A MassStorage device is unmounted\r\n"); +} + +#endif diff --git a/hw/bsp/espressif/boards/CMakeLists.txt b/hw/bsp/espressif/boards/CMakeLists.txt index 325263c1d..8209e8747 100644 --- a/hw/bsp/espressif/boards/CMakeLists.txt +++ b/hw/bsp/espressif/boards/CMakeLists.txt @@ -4,3 +4,5 @@ idf_component_register(SRCS family.c INCLUDE_DIRS "." ${BOARD} ${hw_dir} PRIV_REQUIRES "driver" REQUIRES led_strip src tinyusb_src) + +target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format) diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index 250b7001e..d96d86670 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -33,6 +33,7 @@ #include "soc/usb_periph.h" #include "driver/rmt.h" +#include "driver/uart.h" #if ESP_IDF_VERSION_MAJOR > 4 #include "esp_private/periph_ctrl.h" @@ -145,9 +146,7 @@ uint32_t board_button_read(void) { // Get characters from UART int board_uart_read(uint8_t *buf, int len) { - (void) buf; - (void) len; - return 0; + return uart_read_bytes(UART_NUM_0, buf, len, 0); } // Send characters to UART @@ -157,6 +156,11 @@ int board_uart_write(void const *buf, int len) { return 0; } +int board_getchar(void) { + char c; + return (uart_read_bytes(UART_NUM_0, &c, 1, 0) > 0) ? (int) c : (-1); +} + //--------------------------------------------------------------------+ // API: SPI transfer with MAX3421E, must be implemented by application //--------------------------------------------------------------------+ @@ -164,12 +168,12 @@ int board_uart_write(void const *buf, int len) { static spi_device_handle_t max3421_spi; -static void IRAM_ATTR max3421_isr_handler(void* arg) -{ - (void) arg; - //uint32_t gpio_num = (uint32_t) arg; +static void IRAM_ATTR max3421_isr_handler(void* arg) { + (void) arg; // arg is gpio num //xQueueSendFromISR(gpio_evt_queue, &gpio_num, NULL); + gpio_set_level(13, 1); tuh_int_handler(1); + gpio_set_level(13, 0); } static void max3421_init(void) { @@ -188,12 +192,11 @@ static void max3421_init(void) { .data5_io_num = -1, .data6_io_num = -1, .data7_io_num = -1, - .max_transfer_sz = 128 + .max_transfer_sz = 1024 }; ESP_ERROR_CHECK( spi_bus_initialize(MAX3421_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO) ); spi_device_interface_config_t max3421_cfg = { - .command_bits = 8, .mode = 0, .clock_speed_hz = 4000000, // 26000000 .spics_io_num = -1, // manual control CS @@ -201,12 +204,16 @@ static void max3421_init(void) { }; ESP_ERROR_CHECK( spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi) ); + // debug + gpio_set_direction(13, GPIO_MODE_OUTPUT); + gpio_set_level(13, 0); + // Interrupt pin -// gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT); -// gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE); -// -// gpio_install_isr_service(ESP_INTR_FLAG_EDGE); -// gpio_isr_handler_add(MAX3421_INTR_PIN, max3421_isr_handler, NULL); + gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT); + gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE); + + gpio_install_isr_service(0); + gpio_isr_handler_add(MAX3421_INTR_PIN, max3421_isr_handler, NULL); } void tuh_max3421_int_api(uint8_t rhport, bool enabled) { @@ -227,8 +234,8 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l (void) rhport; spi_transaction_t xact = { - .length = tx_len, - .rxlength = rx_len, + .length = tx_len << 3, // length in bits + .rxlength = rx_len << 3, // length in bits .tx_buffer = tx_buf, .rx_buffer = rx_buf }; diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt index 2a154a8ff..abe276910 100644 --- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt +++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt @@ -70,3 +70,4 @@ idf_component_register(SRCS ${srcs} ) target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions}) +target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format) diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index 6fcfd9476..3620bc8cc 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -95,13 +95,8 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) { //------------- Host using MAX2341E -------------// #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 +static void max3421_init(void); static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1); - -void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { - if (!(pin == MAX3421_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return; - - tuh_int_handler(1); -} #endif @@ -191,50 +186,7 @@ void board_init(void) { #endif #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 - // MAX3421 need 3.3v signal (may not be needed) - #if defined(UICR_REGOUT0_VOUT_Msk) && 0 - if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) != UICR_REGOUT0_VOUT_3V3) { - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - - NRF_UICR->REGOUT0 = (NRF_UICR->REGOUT0 & ~UICR_REGOUT0_VOUT_Msk) | UICR_REGOUT0_VOUT_3V3; - - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - - NVIC_SystemReset(); - } - #endif - - // manually manage CS - nrf_gpio_cfg_output(MAX3421_CS_PIN); - nrf_gpio_pin_write(MAX3421_CS_PIN, 1); - - // USB host using max3421e usb controller via SPI - nrfx_spim_config_t cfg = { - .sck_pin = MAX3421_SCK_PIN, - .mosi_pin = MAX3421_MOSI_PIN, - .miso_pin = MAX3421_MISO_PIN, - .ss_pin = NRFX_SPIM_PIN_NOT_USED, - .ss_active_high = false, - .irq_priority = 3, - .orc = 0xFF, - // default setting 4 Mhz, Mode 0, MSB first - .frequency = NRF_SPIM_FREQ_4M, - .mode = NRF_SPIM_MODE_0, - .bit_order = NRF_SPIM_BIT_ORDER_MSB_FIRST, - }; - - // no handler --> blocking - nrfx_spim_init(&_spi, &cfg, NULL, NULL); - - // max3421e interrupt pin - nrfx_gpiote_init(1); - nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true); - in_config.pull = NRF_GPIO_PIN_PULLUP; - - nrfx_gpiote_in_init(MAX3421_INTR_PIN, &in_config, max3421_int_handler); - nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true); + max3421_init(); #endif } @@ -317,6 +269,60 @@ void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) { //--------------------------------------------------------------------+ #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 +void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { + if (!(pin == MAX3421_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return; + tuh_int_handler(1); +} + +static void max3421_init(void) { + // MAX3421 need 3.3v signal (may not be needed) +// #if defined(UICR_REGOUT0_VOUT_Msk) +// if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) != UICR_REGOUT0_VOUT_3V3) { +// NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; +// while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} +// +// NRF_UICR->REGOUT0 = (NRF_UICR->REGOUT0 & ~UICR_REGOUT0_VOUT_Msk) | UICR_REGOUT0_VOUT_3V3; +// +// NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; +// while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} +// +// NVIC_SystemReset(); +// } +// #endif + + // manually manage CS + nrf_gpio_cfg_output(MAX3421_CS_PIN); + nrf_gpio_pin_write(MAX3421_CS_PIN, 1); + + // USB host using max3421e usb controller via SPI + nrfx_spim_config_t cfg = { + .sck_pin = MAX3421_SCK_PIN, + .mosi_pin = MAX3421_MOSI_PIN, + .miso_pin = MAX3421_MISO_PIN, + .ss_pin = NRFX_SPIM_PIN_NOT_USED, + .ss_active_high = false, + .irq_priority = 3, + .orc = 0xFF, + // default setting 4 Mhz, Mode 0, MSB first + .frequency = NRF_SPIM_FREQ_4M, + .mode = NRF_SPIM_MODE_0, + .bit_order = NRF_SPIM_BIT_ORDER_MSB_FIRST, + }; + + // no handler --> blocking + nrfx_spim_init(&_spi, &cfg, NULL, NULL); + + // max3421e interrupt pin + nrfx_gpiote_init(1); + nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true); + in_config.pull = NRF_GPIO_PIN_PULLUP; + + NVIC_SetPriority(GPIOTE_IRQn, 2); + + nrfx_gpiote_in_init(MAX3421_INTR_PIN, &in_config, max3421_int_handler); + nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true); +} + void tuh_max3421_int_api(uint8_t rhport, bool enabled) { (void) rhport; diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c index 395155548..335039e2f 100644 --- a/hw/bsp/samd21/family.c +++ b/hw/bsp/samd21/family.c @@ -261,6 +261,7 @@ void SysTick_Handler(void) { uint32_t board_millis(void) { return system_ticks; } +#endif //--------------------------------------------------------------------+ // @@ -344,6 +345,11 @@ static void max3421_init(void) { EIC->CONFIG[0].reg &= ~(7 << sense_shift); EIC->CONFIG[0].reg |= 2 << sense_shift; +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(EIC_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + // Enable External Interrupt EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << MAX3421_INTR_EIC_ID); @@ -413,6 +419,3 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l } #endif - - -#endif diff --git a/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h index e3ee529cf..32db4ad95 100644 --- a/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h @@ -59,7 +59,7 @@ #define configTICK_RATE_HZ ( 1000 ) #define configMAX_PRIORITIES ( 5 ) #define configMINIMAL_STACK_SIZE ( 128 ) -#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*6*1024 ) #define configMAX_TASK_NAME_LEN 16 #define configUSE_16_BIT_TICKS 0 #define configIDLE_SHOULD_YIELD 1 diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c index c1b914a02..7b9de35c9 100644 --- a/hw/bsp/samd51/family.c +++ b/hw/bsp/samd51/family.c @@ -175,6 +175,7 @@ void SysTick_Handler(void) { uint32_t board_millis(void) { return system_ticks; } +#endif //--------------------------------------------------------------------+ // API: SPI transfer with MAX3421E, must be implemented by application @@ -290,6 +291,11 @@ static void max3421_init(void) { *eic_config &= ~(7 << sense_shift); *eic_config |= 2 << sense_shift; +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(EIC_0_IRQn + MAX3421_INTR_EIC_ID, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + // Enable External Interrupt EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << MAX3421_INTR_EIC_ID); @@ -360,5 +366,3 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l } #endif - -#endif diff --git a/src/host/usbh.c b/src/host/usbh.c index dc2831da3..e332f35cc 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -659,7 +659,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result tusb_control_request_t const * request = &_ctrl_xfer.request; if (XFER_RESULT_SUCCESS != result) { - TU_LOG1("[%u:%u] Control %s, xferred_bytes = %u\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes); + TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes); TU_LOG1_BUF(request, 8); TU_LOG1("\r\n"); -- cgit v1.3.1 From 1168e4e16343cc0a6d958899460f1b841624974f Mon Sep 17 00:00:00 2001 From: bac Date: Tue, 26 Sep 2023 15:27:17 +0100 Subject: Added support for USB2 HS peripheral (with integrated HS PHY) on STM32U59x chips --- src/portable/synopsys/dwc2/dwc2_stm32.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index cb455bd90..aa77511fa 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -84,7 +84,17 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32U5 #include "stm32u5xx.h" - #define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE + // NOTE: STM595/5A5/599/5A9 only have 1 USB port (with integrated HS PHY) + // USB_OTG_FS_BASE and OTG_FS_IRQn not defined + #if (! defined USB_OTG_FS) + #define USB_OTG_HS_PERIPH_BASE USB_OTG_HS_BASE + #define EP_MAX_HS 9 + #define EP_FIFO_SIZE_HS 4096 + #define USB_OTG_FS_PERIPH_BASE USB_OTG_HS_BASE + #define OTG_FS_IRQn OTG_HS_IRQn + #else + #define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE + #endif #define EP_MAX_FS 6 #define EP_FIFO_SIZE_FS 1280 -- cgit v1.3.1 From 2f6592de7f94851cfcca411242398c5da7b792de Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 27 Sep 2023 11:30:18 +0700 Subject: update max3421 to have hcd_int_handler_ext() --- hw/bsp/espressif/boards/family.c | 22 ++++++++++- src/host/hcd.h | 3 ++ src/portable/analog/max3421/hcd_max3421.c | 62 ++++++++++++++++--------------- 3 files changed, 55 insertions(+), 32 deletions(-) (limited to 'src') diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index d96d86670..a04e1e7c5 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -167,15 +167,30 @@ int board_getchar(void) { #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 static spi_device_handle_t max3421_spi; +SemaphoreHandle_t max3421_intr_sem; static void IRAM_ATTR max3421_isr_handler(void* arg) { (void) arg; // arg is gpio num - //xQueueSendFromISR(gpio_evt_queue, &gpio_num, NULL); gpio_set_level(13, 1); - tuh_int_handler(1); + + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + xSemaphoreGiveFromISR(max3421_intr_sem, &xHigherPriorityTaskWoken); + if (xHigherPriorityTaskWoken) { + portYIELD_FROM_ISR(); + } + gpio_set_level(13, 0); } +static void max3421_intr_task(void* param) { + (void) param; + + while (1) { + xSemaphoreTake(max3421_intr_sem, portMAX_DELAY); + tuh_int_handler(BOARD_TUH_RHPORT); + } +} + static void max3421_init(void) { // CS pin gpio_set_direction(MAX3421_CS_PIN, GPIO_MODE_OUTPUT); @@ -209,6 +224,9 @@ static void max3421_init(void) { gpio_set_level(13, 0); // Interrupt pin + max3421_intr_sem = xSemaphoreCreateBinary(); + xTaskCreate(max3421_intr_task, "max3421 intr", 2048, NULL, configMAX_PRIORITIES-1, NULL); + gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT); gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE); diff --git a/src/host/hcd.h b/src/host/hcd.h index e25b20ea3..a2d4da85d 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -133,6 +133,9 @@ bool hcd_init(uint8_t rhport); // Interrupt Handler void hcd_int_handler(uint8_t rhport); +// Interrupt Hanndler (extended version) +void hcd_int_handler_ext(uint8_t rhport, bool in_isr); + // Enable USB interrupt void hcd_int_enable (uint8_t rhport); diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 3f6747404..652a971ee 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -428,8 +428,8 @@ bool hcd_init(uint8_t rhport) { reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false); // V1 is 0x01, V2 is 0x12, V3 is 0x13 - // uint8_t const revision = reg_read(rhport, REVISION_ADDR, false); - // TU_LOG2_HEX(revision); + uint8_t const revision = reg_read(rhport, REVISION_ADDR, false); + TU_LOG2_HEX(revision); // reset reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false); @@ -693,9 +693,7 @@ static void handle_connect_irq(uint8_t rhport, bool in_isr) { // port reset anyway, this will help to stable bus signal for next connection reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, in_isr); - hcd_event_device_remove(rhport, in_isr); - reg_write(rhport, HCTL_ADDR, 0, in_isr); break; @@ -721,13 +719,12 @@ static void handle_connect_irq(uint8_t rhport, bool in_isr) { free_ep(daddr); hcd_event_device_attach(rhport, in_isr); - break; } } } -static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl) { +static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl, bool in_isr) { uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir); // save data toggle @@ -738,20 +735,20 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re } ep->xfer_pending = 0; - hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, true); + hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, in_isr); // Find next pending endpoint max3421_ep_t *next_ep = find_next_pending_ep(ep); if (next_ep) { - xact_inout(rhport, next_ep, true, true); + xact_inout(rhport, next_ep, true, in_isr); }else { // no more pending atomic_flag_clear(&_hcd_data.busy); } } -static void handle_xfer_done(uint8_t rhport) { - uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true); +static void handle_xfer_done(uint8_t rhport, bool in_isr) { + uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, in_isr); uint8_t const hresult = hrsl & HRSL_RESULT_MASK; uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; @@ -774,17 +771,17 @@ static void handle_xfer_done(uint8_t rhport) { case HRSL_NAK: if (ep_num == 0) { // NAK on control, retry immediately - hxfr_write(rhport, _hcd_data.hxfr, true); + hxfr_write(rhport, _hcd_data.hxfr, in_isr); }else { // NAK on non-control, find next pending to switch max3421_ep_t *next_ep = find_next_pending_ep(ep); if (ep == next_ep) { // this endpoint is only one pending, retry immediately - hxfr_write(rhport, _hcd_data.hxfr, true); + hxfr_write(rhport, _hcd_data.hxfr, in_isr); }else if (next_ep) { // switch to next pending TODO could have issue with double buffered if not clear previously out data - xact_inout(rhport, next_ep, true, true); + xact_inout(rhport, next_ep, true, in_isr); }else { TU_ASSERT(false,); } @@ -802,7 +799,7 @@ static void handle_xfer_done(uint8_t rhport) { } if (xfer_result != XFER_RESULT_SUCCESS) { - xfer_complete_isr(rhport, ep, xfer_result, hrsl); + xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr); return; } @@ -814,10 +811,10 @@ static void handle_xfer_done(uint8_t rhport) { // short packet or all bytes transferred if ( ep->xfer_complete ) { - xfer_complete_isr(rhport, ep, xfer_result, hrsl); + xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr); }else { // more to transfer - hxfr_write(rhport, _hcd_data.hxfr, true); + hxfr_write(rhport, _hcd_data.hxfr, in_isr); } } else { // SETUP or OUT transfer @@ -835,10 +832,10 @@ static void handle_xfer_done(uint8_t rhport) { ep->buf += xact_len; if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) { - xfer_complete_isr(rhport, ep, xfer_result, hrsl); + xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr); } else { // more to transfer - xact_out(rhport, ep, false, true); + xact_out(rhport, ep, false, in_isr); } } } @@ -862,9 +859,9 @@ void print_hirq(uint8_t hirq) { #define print_hirq(hirq) #endif -// Interrupt Handler -void hcd_int_handler(uint8_t rhport) { - uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true) & _hcd_data.hien; +// Interrupt handler (extended) +void hcd_int_handler_ext(uint8_t rhport, bool in_isr) { + uint8_t hirq = reg_read(rhport, HIRQ_ADDR, in_isr) & _hcd_data.hien; if (!hirq) return; // print_hirq(hirq); @@ -873,7 +870,7 @@ void hcd_int_handler(uint8_t rhport) { } if (hirq & HIRQ_CONDET_IRQ) { - handle_connect_irq(rhport, true); + handle_connect_irq(rhport, in_isr); } // queue more transfer in handle_xfer_done() can cause hirq to be set again while external IRQ may not catch and/or @@ -886,17 +883,17 @@ void hcd_int_handler(uint8_t rhport) { // RCVDAV_IRQ can trigger 2 times (dual buffered) while ( hirq & HIRQ_RCVDAV_IRQ ) { - uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, true); + uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, in_isr); xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len); if ( xact_len ) { - fifo_read(rhport, ep->buf, xact_len, true); + fifo_read(rhport, ep->buf, xact_len, in_isr); ep->buf += xact_len; ep->xferred_len += xact_len; } // ack RCVDVAV IRQ - hirq_write(rhport, HIRQ_RCVDAV_IRQ, true); - hirq = reg_read(rhport, HIRQ_ADDR, true); + hirq_write(rhport, HIRQ_RCVDAV_IRQ, in_isr); + hirq = reg_read(rhport, HIRQ_ADDR, in_isr); } if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) { @@ -905,18 +902,23 @@ void hcd_int_handler(uint8_t rhport) { } if ( hirq & HIRQ_HXFRDN_IRQ ) { - hirq_write(rhport, HIRQ_HXFRDN_IRQ, true); - handle_xfer_done(rhport); + hirq_write(rhport, HIRQ_HXFRDN_IRQ, in_isr); + handle_xfer_done(rhport, in_isr); } - hirq = reg_read(rhport, HIRQ_ADDR, true); + hirq = reg_read(rhport, HIRQ_ADDR, in_isr); } // clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing hirq &= ~HIRQ_SNDBAV_IRQ; if ( hirq ) { - hirq_write(rhport, hirq, true); + hirq_write(rhport, hirq, in_isr); } } +// Interrupt Handler +void hcd_int_handler(uint8_t rhport) { + hcd_int_handler_ext(rhport, true); +} + #endif -- cgit v1.3.1 From 3b0ffd0f488671f1bafa4bcd9e22dd51f8bb6dee Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 27 Sep 2023 15:51:03 +0700 Subject: change hcd_int_handler(rhport, in_isr) signature: add in_isr change tuh_int_handler() to take in_isr as optional parameter (default = true) --- examples/host/bare_api/only.txt | 1 + examples/host/cdc_msc_hid/only.txt | 1 + examples/host/hid_controller/only.txt | 1 + examples/host/msc_file_explorer/only.txt | 1 + hw/bsp/imxrt/family.c | 4 +- hw/bsp/kinetis_kl/family.c | 2 +- hw/bsp/kinetis_kl/family.cmake | 75 ++++++++++---------- .../lpc17/boards/lpcxpresso1769/lpcxpresso1769.c | 2 +- hw/bsp/lpc17/boards/mbed1768/mbed1768.c | 2 +- hw/bsp/lpc18/family.c | 55 ++++++--------- hw/bsp/lpc40/family.c | 2 +- hw/bsp/lpc43/family.c | 4 +- hw/bsp/msp432e4/family.c | 2 +- hw/bsp/ngx4330/ngx4330.c | 4 +- hw/bsp/nrf/family.c | 2 +- hw/bsp/ra/family.c | 6 +- hw/bsp/rx/boards/rx65n_target/rx65n_target.c | 2 +- hw/bsp/samd21/family.c | 2 +- hw/bsp/samd51/family.c | 2 +- hw/bsp/stm32g4/family.cmake | 81 +++++++++++----------- hw/bsp/tm4c123/family.c | 2 +- src/common/tusb_common.h | 2 - src/common/tusb_timeout.h | 80 --------------------- src/common/tusb_verify.h | 52 +++++--------- src/host/hcd.h | 2 +- src/host/usbh.h | 11 ++- src/portable/analog/max3421/hcd_max3421.c | 3 +- src/portable/ehci/ehci.c | 4 +- src/portable/mentor/musb/hcd_musb.c | 4 +- src/portable/nxp/khci/hcd_khci.c | 7 +- src/portable/ohci/ohci.c | 5 +- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 4 +- src/portable/renesas/rusb2/hcd_rusb2.c | 5 +- src/portable/template/hcd_template.c | 3 +- src/tusb.h | 4 +- 35 files changed, 172 insertions(+), 267 deletions(-) delete mode 100644 src/common/tusb_timeout.h (limited to 'src') diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt index 3837ac8a2..fee10f9e2 100644 --- a/examples/host/bare_api/only.txt +++ b/examples/host/bare_api/only.txt @@ -1,3 +1,4 @@ +mcu:KINETIS_KL mcu:LPC175X_6X mcu:LPC177X_8X mcu:LPC18XX diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt index 3837ac8a2..fee10f9e2 100644 --- a/examples/host/cdc_msc_hid/only.txt +++ b/examples/host/cdc_msc_hid/only.txt @@ -1,3 +1,4 @@ +mcu:KINETIS_KL mcu:LPC175X_6X mcu:LPC177X_8X mcu:LPC18XX diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt index 3837ac8a2..fee10f9e2 100644 --- a/examples/host/hid_controller/only.txt +++ b/examples/host/hid_controller/only.txt @@ -1,3 +1,4 @@ +mcu:KINETIS_KL mcu:LPC175X_6X mcu:LPC177X_8X mcu:LPC18XX diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt index 3837ac8a2..fee10f9e2 100644 --- a/examples/host/msc_file_explorer/only.txt +++ b/examples/host/msc_file_explorer/only.txt @@ -1,3 +1,4 @@ +mcu:KINETIS_KL mcu:LPC175X_6X mcu:LPC177X_8X mcu:LPC18XX diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index ec95a8b24..32d89f794 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -188,7 +188,7 @@ void USB_OTG1_IRQHandler(void) #endif #if PORT_SUPPORT_HOST(0) - tuh_int_handler(0); + tuh_int_handler(0, true); #endif } @@ -199,7 +199,7 @@ void USB_OTG2_IRQHandler(void) #endif #if PORT_SUPPORT_HOST(1) - tuh_int_handler(1); + tuh_int_handler(1, true); #endif } diff --git a/hw/bsp/kinetis_kl/family.c b/hw/bsp/kinetis_kl/family.c index 3e9aa83a4..c436be3e6 100644 --- a/hw/bsp/kinetis_kl/family.c +++ b/hw/bsp/kinetis_kl/family.c @@ -39,7 +39,7 @@ void USB0_IRQHandler(void) { #if CFG_TUH_ENABLED - tuh_int_handler(0); + tuh_int_handler(0, true); #endif #if CFG_TUD_ENABLED tud_int_handler(0); diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake index 793ef1783..4151979a0 100644 --- a/hw/bsp/kinetis_kl/family.cmake +++ b/hw/bsp/kinetis_kl/family.cmake @@ -22,48 +22,47 @@ set(FAMILY_MCUS KINETIS_KL CACHE INTERNAL "") #------------------------------------ # only need to be built ONCE for all examples function(add_board_target BOARD_TARGET) - if (NOT TARGET ${BOARD_TARGET}) - add_library(${BOARD_TARGET} STATIC - ${SDK_DIR}/drivers/gpio/fsl_gpio.c - ${SDK_DIR}/drivers/lpsci/fsl_lpsci.c - ${SDK_DIR}/drivers/uart/fsl_uart.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c - ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c - ) - target_compile_definitions(${BOARD_TARGET} PUBLIC - ) - target_include_directories(${BOARD_TARGET} PUBLIC - ${CMSIS_DIR}/CMSIS/Core/Include - ${SDK_DIR}/devices/${MCU_VARIANT} - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers - ${SDK_DIR}/drivers/common - ${SDK_DIR}/drivers/gpio - ${SDK_DIR}/drivers/lpsci - ${SDK_DIR}/drivers/port - ${SDK_DIR}/drivers/smc - ${SDK_DIR}/drivers/uart - ) + if (TARGET ${BOARD_TARGET}) + return() + endif () - update_board(${BOARD_TARGET}) + add_library(${BOARD_TARGET} STATIC + ${SDK_DIR}/drivers/gpio/fsl_gpio.c + ${SDK_DIR}/drivers/lpsci/fsl_lpsci.c + ${SDK_DIR}/drivers/uart/fsl_uart.c + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c + ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c + ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMSIS_DIR}/CMSIS/Core/Include + ${SDK_DIR}/devices/${MCU_VARIANT} + ${SDK_DIR}/devices/${MCU_VARIANT}/drivers + ${SDK_DIR}/drivers/common + ${SDK_DIR}/drivers/gpio + ${SDK_DIR}/drivers/lpsci + ${SDK_DIR}/drivers/port + ${SDK_DIR}/drivers/smc + ${SDK_DIR}/drivers/uart + ) + update_board(${BOARD_TARGET}) - # LD_FILE and STARTUP_FILE can be defined in board.cmake + # LD_FILE and STARTUP_FILE can be defined in board.cmake + target_sources(${BOARD_TARGET} PUBLIC + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) - target_sources(${BOARD_TARGET} PUBLIC - ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + # nanolib + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" ) - - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_GNU}" - # nanolib - --specs=nosys.specs - --specs=nano.specs - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--config=${LD_FILE_IAR}" - ) - endif () endif () endfunction() diff --git a/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c b/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c index c7d655368..8c26b906f 100644 --- a/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c +++ b/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c @@ -37,7 +37,7 @@ void USB_IRQHandler(void) #endif #if CFG_TUH_ENABLED - tuh_int_handler(0); + tuh_int_handler(0, true); #endif } diff --git a/hw/bsp/lpc17/boards/mbed1768/mbed1768.c b/hw/bsp/lpc17/boards/mbed1768/mbed1768.c index b2c92d640..613dcb570 100644 --- a/hw/bsp/lpc17/boards/mbed1768/mbed1768.c +++ b/hw/bsp/lpc17/boards/mbed1768/mbed1768.c @@ -151,7 +151,7 @@ void USB_IRQHandler(void) #endif #if CFG_TUH_ENABLED - tuh_int_handler(0); + tuh_int_handler(0, true); #endif } diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c index b11f4fe0e..e6abecb4b 100644 --- a/hw/bsp/lpc18/family.c +++ b/hw/bsp/lpc18/family.c @@ -43,25 +43,23 @@ //--------------------------------------------------------------------+ // USB Interrupt Handler //--------------------------------------------------------------------+ -void USB0_IRQHandler(void) -{ +void USB0_IRQHandler(void) { #if PORT_SUPPORT_DEVICE(0) - tud_int_handler(0); + tud_int_handler(0); #endif #if PORT_SUPPORT_HOST(0) - tuh_int_handler(0); + tuh_int_handler(0, true); #endif } -void USB1_IRQHandler(void) -{ +void USB1_IRQHandler(void) { #if PORT_SUPPORT_DEVICE(1) - tud_int_handler(1); + tud_int_handler(1); #endif #if PORT_SUPPORT_HOST(1) - tuh_int_handler(1); + tuh_int_handler(1, true); #endif } @@ -74,28 +72,26 @@ const uint32_t OscRateIn = 12000000; const uint32_t ExtRateIn = 0; // Invoked by startup code -void SystemInit(void) -{ +void SystemInit(void) { #ifdef __USE_LPCOPEN - extern void (* const g_pfnVectors[])(void); + extern void (*const g_pfnVectors[])(void); unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08; - *pSCB_VTOR = (unsigned int) g_pfnVectors; + *pSCB_VTOR = (unsigned int) g_pfnVectors; #endif board_lpc18_pinmux(); - #ifdef TRACE_ETM +#ifdef TRACE_ETM // Trace clock is limited to 60MHz, limit CPU clock to 120MHz Chip_SetupCoreClock(CLKIN_CRYSTAL, 120000000UL, true); - #else +#else // CPU clock max to 180 Mhz Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true); - #endif +#endif } -void board_init(void) -{ +void board_init(void) { SystemCoreClockUpdate(); #if CFG_TUSB_OS == OPT_OS_NONE @@ -135,27 +131,22 @@ void board_init(void) // Board porting API //--------------------------------------------------------------------+ -void board_led_write(bool state) -{ +void board_led_write(bool state) { Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state); } -uint32_t board_button_read(void) -{ +uint32_t board_button_read(void) { // active low return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1; } -int board_uart_read(uint8_t* buf, int len) -{ +int board_uart_read(uint8_t *buf, int len) { return Chip_UART_Read(UART_DEV, buf, len); } -int board_uart_write(void const * buf, int len) -{ - uint8_t const* buf8 = (uint8_t const*) buf; - for(int i=0; iINTFLAG.reg = EIC_INTFLAG_EXTINT(1 << MAX3421_INTR_EIC_ID); // Call the TinyUSB interrupt handler - tuh_int_handler(1); + tuh_int_handler(1, true); } void tuh_max3421_int_api(uint8_t rhport, bool enabled) { diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c index 2cf00c7af..268d60e48 100644 --- a/hw/bsp/samd51/family.c +++ b/hw/bsp/samd51/family.c @@ -296,7 +296,7 @@ void MAX3421_EIC_Handler(void) { EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << MAX3421_INTR_EIC_ID); // Call the TinyUSB interrupt handler - tuh_int_handler(1); + tuh_int_handler(1, true); } void tuh_max3421_int_api(uint8_t rhport, bool enabled) { diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake index 675a96c74..f8cabcbe5 100644 --- a/hw/bsp/stm32g4/family.cmake +++ b/hw/bsp/stm32g4/family.cmake @@ -26,50 +26,47 @@ set(FAMILY_MCUS STM32G4 CACHE INTERNAL "") #------------------------------------ # only need to be built ONCE for all examples function(add_board_target BOARD_TARGET) - if (NOT TARGET ${BOARD_TARGET}) - # Startup & Linker script - set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) - set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s) - set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) - - add_library(${BOARD_TARGET} STATIC - ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c - ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c - ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} - ) - target_include_directories(${BOARD_TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMSIS_5}/CMSIS/Core/Include - ${ST_CMSIS}/Include - ${ST_HAL_DRIVER}/Inc - ) - target_compile_options(${BOARD_TARGET} PUBLIC + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) + set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s) + set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) + + add_library(${BOARD_TARGET} STATIC + ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${ST_CMSIS}/Include + ${ST_HAL_DRIVER}/Inc + ) + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + # nanolib + --specs=nosys.specs + --specs=nano.specs ) - target_compile_definitions(${BOARD_TARGET} PUBLIC + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" ) - - update_board(${BOARD_TARGET}) - - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_GNU}" - -nostartfiles - # nanolib - --specs=nosys.specs - --specs=nano.specs - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--config=${LD_FILE_IAR}" - ) - endif () endif () endfunction() diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c123/family.c index ad5ae505f..738bc3fa0 100644 --- a/hw/bsp/tm4c123/family.c +++ b/hw/bsp/tm4c123/family.c @@ -8,7 +8,7 @@ void USB0_Handler(void) { #if CFG_TUH_ENABLED - tuh_int_handler(0); + tuh_int_handler(0, true); #endif #if CFG_TUD_ENABLED diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 6fffed11c..caeb5f2ef 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -75,8 +75,6 @@ #include "tusb_types.h" #include "tusb_debug.h" -#include "tusb_timeout.h" // TODO remove - //--------------------------------------------------------------------+ // Optional API implemented by application if needed // TODO move to a more ovious place/file diff --git a/src/common/tusb_timeout.h b/src/common/tusb_timeout.h deleted file mode 100644 index 533e67ab8..000000000 --- a/src/common/tusb_timeout.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/** \ingroup Group_Common Common Files - * \defgroup Group_TimeoutTimer timeout timer - * @{ */ - -#ifndef _TUSB_TIMEOUT_H_ -#define _TUSB_TIMEOUT_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - uint32_t start; - uint32_t interval; -}tu_timeout_t; - -#if 0 - -extern uint32_t tusb_hal_millis(void); - -static inline void tu_timeout_set(tu_timeout_t* tt, uint32_t msec) -{ - tt->interval = msec; - tt->start = tusb_hal_millis(); -} - -static inline bool tu_timeout_expired(tu_timeout_t* tt) -{ - return ( tusb_hal_millis() - tt->start ) >= tt->interval; -} - -// For used with periodic event to prevent drift -static inline void tu_timeout_reset(tu_timeout_t* tt) -{ - tt->start += tt->interval; -} - -static inline void tu_timeout_restart(tu_timeout_t* tt) -{ - tt->start = tusb_hal_millis(); -} - -#endif - -#ifdef __cplusplus - } -#endif - -#endif /* _TUSB_TIMEOUT_H_ */ - -/** @} */ diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h index 12355e8be..1b5f53dfc 100644 --- a/src/common/tusb_verify.h +++ b/src/common/tusb_verify.h @@ -56,12 +56,8 @@ * #define TU_VERIFY(cond) if(cond) return false; * #define TU_VERIFY(cond,ret) if(cond) return ret; * - * #define TU_VERIFY_HDLR(cond,handler) if(cond) {handler; return false;} - * #define TU_VERIFY_HDLR(cond,ret,handler) if(cond) {handler; return ret;} - * * #define TU_ASSERT(cond) if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return false;} * #define TU_ASSERT(cond,ret) if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return ret;} - * *------------------------------------------------------------------*/ #ifdef __cplusplus @@ -97,40 +93,23 @@ #define TU_BREAKPOINT() do {} while (0) #endif -/*------------------------------------------------------------------*/ -/* Macro Generator - *------------------------------------------------------------------*/ - // Helper to implement optional parameter for TU_VERIFY Macro family #define _GET_3RD_ARG(arg1, arg2, arg3, ...) arg3 -#define _GET_4TH_ARG(arg1, arg2, arg3, arg4, ...) arg4 - -/*------------- Generator for TU_VERIFY and TU_VERIFY_HDLR -------------*/ -#define TU_VERIFY_DEFINE(_cond, _handler, _ret) do \ -{ \ - if ( !(_cond) ) { _handler; return _ret; } \ -} while(0) /*------------------------------------------------------------------*/ /* TU_VERIFY * - TU_VERIFY_1ARGS : return false if failed * - TU_VERIFY_2ARGS : return provided value if failed *------------------------------------------------------------------*/ -#define TU_VERIFY_1ARGS(_cond) TU_VERIFY_DEFINE(_cond, , false) -#define TU_VERIFY_2ARGS(_cond, _ret) TU_VERIFY_DEFINE(_cond, , _ret) +#define TU_VERIFY_DEFINE(_cond, _ret) \ + do { \ + if ( !(_cond) ) { return _ret; } \ + } while(0) -#define TU_VERIFY(...) _GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, UNUSED)(__VA_ARGS__) +#define TU_VERIFY_1ARGS(_cond) TU_VERIFY_DEFINE(_cond, false) +#define TU_VERIFY_2ARGS(_cond, _ret) TU_VERIFY_DEFINE(_cond, _ret) - -/*------------------------------------------------------------------*/ -/* TU_VERIFY WITH HANDLER - * - TU_VERIFY_HDLR_2ARGS : execute handler, return false if failed - * - TU_VERIFY_HDLR_3ARGS : execute handler, return provided error if failed - *------------------------------------------------------------------*/ -#define TU_VERIFY_HDLR_2ARGS(_cond, _handler) TU_VERIFY_DEFINE(_cond, _handler, false) -#define TU_VERIFY_HDLR_3ARGS(_cond, _handler, _ret) TU_VERIFY_DEFINE(_cond, _handler, _ret) - -#define TU_VERIFY_HDLR(...) _GET_4TH_ARG(__VA_ARGS__, TU_VERIFY_HDLR_3ARGS, TU_VERIFY_HDLR_2ARGS,UNUSED)(__VA_ARGS__) +#define TU_VERIFY(...) _GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, _dummy)(__VA_ARGS__) /*------------------------------------------------------------------*/ /* ASSERT @@ -138,19 +117,20 @@ * - 1 arg : return false if failed * - 2 arg : return error if failed *------------------------------------------------------------------*/ -#define ASSERT_1ARGS(_cond) TU_VERIFY_DEFINE(_cond, _MESS_FAILED(); TU_BREAKPOINT(), false) -#define ASSERT_2ARGS(_cond, _ret) TU_VERIFY_DEFINE(_cond, _MESS_FAILED(); TU_BREAKPOINT(), _ret) +#define TU_ASSERT_DEFINE(_cond, _ret) \ + do { \ + if ( !(_cond) ) { _MESS_FAILED(); TU_BREAKPOINT(); return _ret; } \ + } while(0) + +#define TU_ASSERT_1ARGS(_cond) TU_ASSERT_DEFINE(_cond, false) +#define TU_ASSERT_2ARGS(_cond, _ret) TU_ASSERT_DEFINE(_cond, _ret) #ifndef TU_ASSERT -#define TU_ASSERT(...) _GET_3RD_ARG(__VA_ARGS__, ASSERT_2ARGS, ASSERT_1ARGS,UNUSED)(__VA_ARGS__) +#define TU_ASSERT(...) _GET_3RD_ARG(__VA_ARGS__, TU_ASSERT_2ARGS, TU_ASSERT_1ARGS, _dummy)(__VA_ARGS__) #endif -/*------------------------------------------------------------------*/ -/* ASSERT HDLR - *------------------------------------------------------------------*/ - #ifdef __cplusplus } #endif -#endif /* TUSB_VERIFY_H_ */ +#endif diff --git a/src/host/hcd.h b/src/host/hcd.h index e25b20ea3..2bde289df 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -131,7 +131,7 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) TU_AT bool hcd_init(uint8_t rhport); // Interrupt Handler -void hcd_int_handler(uint8_t rhport); +void hcd_int_handler(uint8_t rhport, bool in_isr); // Enable USB interrupt void hcd_int_enable (uint8_t rhport); diff --git a/src/host/usbh.h b/src/host/usbh.h index 684e8240e..770d70dfe 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -124,11 +124,16 @@ void tuh_task(void) { bool tuh_task_event_ready(void); #ifndef _TUSB_HCD_H_ -extern void hcd_int_handler(uint8_t rhport); +extern void hcd_int_handler(uint8_t rhport, bool in_isr); #endif -// Interrupt handler, name alias to HCD -#define tuh_int_handler hcd_int_handler +// Interrupt handler alias to HCD with in_isr as optional parameter +// - tuh_int_handler(rhport) --> hcd_int_handler(rhport, true) +// - tuh_int_handler(rhport, in_isr) --> hcd_int_handler(rhport, in_isr) +// Note: this is similar to TU_VERIFY(), _GET_3RD_ARG() is defined in tusb_verify.h +#define _tuh_int_handler_1arg(_rhport) hcd_int_handler(_rhport, true) +#define _tuh_int_hanlder_2arg(_rhport, _in_isr) hcd_int_handler(_rhport, _in_isr) +#define tuh_int_handler(...) _GET_3RD_ARG(__VA_ARGS__, _tuh_int_hanlder_2arg, _tuh_int_handler_1arg, _dummy)(__VA_ARGS__) // Check if roothub port is initialized and active as a host bool tuh_rhport_is_active(uint8_t rhport); diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 238b518a0..d013d6179 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -863,7 +863,8 @@ void print_hirq(uint8_t hirq) { #endif // Interrupt Handler -void hcd_int_handler(uint8_t rhport) { +void hcd_int_handler(uint8_t rhport, bool in_isr) { + (void) in_isr; uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true) & _hcd_data.hien; if (!hirq) return; // print_hirq(hirq); diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index c93c33fc0..572b9826c 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -656,8 +656,8 @@ void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms) } //------------- Host Controller Driver's Interrupt Handler -------------// -void hcd_int_handler(uint8_t rhport) -{ +void hcd_int_handler(uint8_t rhport, bool in_isr) { + (void) in_isr; ehci_registers_t* regs = ehci_data.regs; uint32_t const int_status = regs->status; diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c index 02090df85..5312c2812 100644 --- a/src/portable/mentor/musb/hcd_musb.c +++ b/src/portable/mentor/musb/hcd_musb.c @@ -847,8 +847,10 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { /*------------------------------------------------------------------- * ISR *-------------------------------------------------------------------*/ -void hcd_int_handler(uint8_t rhport) +void hcd_int_handler(uint8_t rhport, bool in_isr) { + (void) in_isr; + uint_fast8_t is, txis, rxis; is = USB0->IS; /* read and clear interrupt status */ diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index 55327e02d..57684b259 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -447,6 +447,10 @@ void hcd_port_reset(uint8_t rhport) _hcd.need_reset = false; } +void hcd_port_reset_end(uint8_t rhport) { + (void) rhport; +} + tusb_speed_t hcd_port_speed_get(uint8_t rhport) { (void)rhport; @@ -583,8 +587,9 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { /*--------------------------------------------------------------------+ * ISR *--------------------------------------------------------------------+*/ -void hcd_int_handler(uint8_t rhport) +void hcd_int_handler(uint8_t rhport, bool in_isr) { + (void) in_isr; uint32_t is = KHCI->ISTAT; uint32_t msk = KHCI->INTEN; diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 413e72037..f978b0965 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -667,8 +667,9 @@ static void done_queue_isr(uint8_t hostid) } } -void hcd_int_handler(uint8_t hostid) -{ +void hcd_int_handler(uint8_t hostid, bool in_isr) { + (void) in_isr; + uint32_t const int_en = OHCI_REG->interrupt_enable; uint32_t const int_status = OHCI_REG->interrupt_status & int_en; diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 21dc3f67d..4ed6d36bb 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -252,9 +252,9 @@ static void __tusb_irq_path_func(hcd_rp2040_irq)(void) } } -void __tusb_irq_path_func(hcd_int_handler)(uint8_t rhport) -{ +void __tusb_irq_path_func(hcd_int_handler)(uint8_t rhport, bool in_isr) { (void) rhport; + (void) in_isr; hcd_rp2040_irq(); } diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 790cd6b32..bf95be707 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -771,8 +771,9 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { //--------------------------------------------------------------------+ // ISR //--------------------------------------------------------------------+ -void hcd_int_handler(uint8_t rhport) -{ +void hcd_int_handler(uint8_t rhport, bool in_isr) { + (void) in_isr; + rusb2_reg_t* rusb = RUSB2_REG(rhport); unsigned is0 = rusb->INTSTS0; unsigned is1 = rusb->INTSTS1; diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c index 3e3b91558..b073d6057 100644 --- a/src/portable/template/hcd_template.c +++ b/src/portable/template/hcd_template.c @@ -51,8 +51,9 @@ bool hcd_init(uint8_t rhport) { } // Interrupt Handler -void hcd_int_handler(uint8_t rhport) { +void hcd_int_handler(uint8_t rhport, bool in_isr) { (void) rhport; + (void) in_isr; } // Enable USB interrupt diff --git a/src/tusb.h b/src/tusb.h index d6534ca28..c9d56d3c3 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -66,7 +66,7 @@ #endif #else #ifndef tuh_int_handler - #define tuh_int_handler(_x) + #define tuh_int_handler(...) #endif #endif @@ -123,7 +123,7 @@ #endif #else #ifndef tud_int_handler - #define tud_int_handler(_x) + #define tud_int_handler(...) #endif #endif -- cgit v1.3.1 From 277852afc1798f2acdb61917984e76b4bafa699e Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 28 Sep 2023 10:56:38 +0700 Subject: fix esp32 msc example --- examples/host/cdc_msc_hid_freertos/src/cdc_app.c | 8 +- examples/host/cdc_msc_hid_freertos/src/hid_app.c | 4 + examples/host/cdc_msc_hid_freertos/src/main.c | 12 +- examples/host/cdc_msc_hid_freertos/src/msc_app.c | 8 +- src/class/msc/msc_host.c | 265 ++++++++++------------- src/class/msc/msc_host.h | 8 +- src/host/usbh.c | 22 +- 7 files changed, 151 insertions(+), 176 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c index 943e534d8..91dcc2e1a 100644 --- a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c +++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c @@ -31,9 +31,7 @@ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ - -//------------- IMPLEMENTATION -------------// - +// helper size_t get_console_inputs(uint8_t *buf, size_t bufsize) { size_t count = 0; while (count < bufsize) { @@ -47,6 +45,10 @@ size_t get_console_inputs(uint8_t *buf, size_t bufsize) { return count; } +void cdc_app_init(void) { + // nothing to do +} + void cdc_app_task(void* param) { (void) param; diff --git a/examples/host/cdc_msc_hid_freertos/src/hid_app.c b/examples/host/cdc_msc_hid_freertos/src/hid_app.c index a2df3b909..9ea5c1be0 100644 --- a/examples/host/cdc_msc_hid_freertos/src/hid_app.c +++ b/examples/host/cdc_msc_hid_freertos/src/hid_app.c @@ -48,6 +48,10 @@ static void process_kbd_report(hid_keyboard_report_t const *report); static void process_mouse_report(hid_mouse_report_t const *report); static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len); +void hid_app_init(void) { + // nothing to do +} + //--------------------------------------------------------------------+ // TinyUSB Callbacks //--------------------------------------------------------------------+ diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c index 88e742ee2..b60be015b 100644 --- a/examples/host/cdc_msc_hid_freertos/src/main.c +++ b/examples/host/cdc_msc_hid_freertos/src/main.c @@ -82,10 +82,15 @@ StaticTask_t cdc_taskdef; TimerHandle_t blinky_tm; static void led_blinky_cb(TimerHandle_t xTimer); -static void usb_host_task(void* param); +extern void cdc_app_init(void); +extern void hid_app_init(void); +extern void msc_app_init(void); +static void usb_host_task(void* param); extern void cdc_app_task(void* param); + + /*------------- MAIN -------------*/ int main(void) { board_init(); @@ -131,6 +136,10 @@ static void usb_host_task(void *param) { board_init_after_tusb(); } + cdc_app_init(); + hid_app_init(); + msc_app_init(); + // RTOS forever loop while (1) { // put this thread to waiting state until there is new events @@ -154,7 +163,6 @@ void tuh_umount_cb(uint8_t dev_addr) { printf("A device with address %d is unmounted \r\n", dev_addr); } - //--------------------------------------------------------------------+ // BLINKING TASK //--------------------------------------------------------------------+ diff --git a/examples/host/cdc_msc_hid_freertos/src/msc_app.c b/examples/host/cdc_msc_hid_freertos/src/msc_app.c index a8d6fbfaa..ee02ba917 100644 --- a/examples/host/cdc_msc_hid_freertos/src/msc_app.c +++ b/examples/host/cdc_msc_hid_freertos/src/msc_app.c @@ -25,10 +25,12 @@ #include "tusb.h" -#if CFG_TUH_MSC - static scsi_inquiry_resp_t inquiry_resp; +void msc_app_init(void) { + // nothing to do +} + bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const *cb_data) { msc_cbw_t const *cbw = cb_data->cbw; msc_csw_t const *csw = cb_data->csw; @@ -63,5 +65,3 @@ void tuh_msc_umount_cb(uint8_t dev_addr) { (void) dev_addr; printf("A MassStorage device is unmounted\r\n"); } - -#endif diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c index da264142c..39f2d9f1c 100644 --- a/src/class/msc/msc_host.c +++ b/src/class/msc/msc_host.c @@ -43,16 +43,14 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -enum -{ +enum { MSC_STAGE_IDLE = 0, MSC_STAGE_CMD, MSC_STAGE_DATA, MSC_STAGE_STATUS, }; -typedef struct -{ +typedef struct { uint8_t itf_num; uint8_t ep_in; uint8_t ep_out; @@ -69,13 +67,13 @@ typedef struct //------------- SCSI -------------// uint8_t stage; - void* buffer; + void* buffer; tuh_msc_complete_cb_t complete_cb; uintptr_t complete_arg; CFG_TUH_MEM_ALIGN msc_cbw_t cbw; CFG_TUH_MEM_ALIGN msc_csw_t csw; -}msch_interface_t; +} msch_interface_t; CFG_TUH_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX]; @@ -86,40 +84,34 @@ static uint8_t _msch_buffer[sizeof(scsi_inquiry_resp_t)]; // FIXME potential nul reference TU_ATTR_ALWAYS_INLINE -static inline msch_interface_t* get_itf(uint8_t dev_addr) -{ - return &_msch_itf[dev_addr-1]; +static inline msch_interface_t* get_itf(uint8_t dev_addr) { + return &_msch_itf[dev_addr - 1]; } //--------------------------------------------------------------------+ // PUBLIC API //--------------------------------------------------------------------+ -uint8_t tuh_msc_get_maxlun(uint8_t dev_addr) -{ +uint8_t tuh_msc_get_maxlun(uint8_t dev_addr) { msch_interface_t* p_msc = get_itf(dev_addr); return p_msc->max_lun; } -uint32_t tuh_msc_get_block_count(uint8_t dev_addr, uint8_t lun) -{ +uint32_t tuh_msc_get_block_count(uint8_t dev_addr, uint8_t lun) { msch_interface_t* p_msc = get_itf(dev_addr); return p_msc->capacity[lun].block_count; } -uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun) -{ +uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun) { msch_interface_t* p_msc = get_itf(dev_addr); return p_msc->capacity[lun].block_size; } -bool tuh_msc_mounted(uint8_t dev_addr) -{ +bool tuh_msc_mounted(uint8_t dev_addr) { msch_interface_t* p_msc = get_itf(dev_addr); return p_msc->mounted; } -bool tuh_msc_ready(uint8_t dev_addr) -{ +bool tuh_msc_ready(uint8_t dev_addr) { msch_interface_t* p_msc = get_itf(dev_addr); return p_msc->mounted && !usbh_edpt_busy(dev_addr, p_msc->ep_in) && !usbh_edpt_busy(dev_addr, p_msc->ep_out); } @@ -127,20 +119,20 @@ bool tuh_msc_ready(uint8_t dev_addr) //--------------------------------------------------------------------+ // PUBLIC API: SCSI COMMAND //--------------------------------------------------------------------+ -static inline void cbw_init(msc_cbw_t *cbw, uint8_t lun) -{ +static inline void cbw_init(msc_cbw_t* cbw, uint8_t lun) { tu_memclr(cbw, sizeof(msc_cbw_t)); cbw->signature = MSC_CBW_SIGNATURE; cbw->tag = 0x54555342; // TUSB cbw->lun = lun; } -bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) -{ - msch_interface_t* p_msc = get_itf(dev_addr); +bool tuh_msc_scsi_command(uint8_t daddr, msc_cbw_t const* cbw, void* data, + tuh_msc_complete_cb_t complete_cb, uintptr_t arg) { + msch_interface_t* p_msc = get_itf(daddr); TU_VERIFY(p_msc->configured); - // TODO claim endpoint + // claim endpoint + TU_VERIFY(usbh_edpt_claim(daddr, p_msc->ep_out)); p_msc->cbw = *cbw; p_msc->stage = MSC_STAGE_CMD; @@ -148,15 +140,18 @@ bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tu p_msc->complete_cb = complete_cb; p_msc->complete_arg = arg; - TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t))); + if (!usbh_edpt_xfer(daddr, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t))) { + usbh_edpt_release(daddr, p_msc->ep_out); + return false; + } return true; } -bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) -{ - msch_interface_t* p_msc = get_itf(dev_addr); - TU_VERIFY(p_msc->configured); +bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, + tuh_msc_complete_cb_t complete_cb, uintptr_t arg) { + msch_interface_t* p_msc = get_itf(dev_addr); + TU_VERIFY(p_msc->configured); msc_cbw_t cbw; cbw_init(&cbw, lun); @@ -169,8 +164,8 @@ bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_r return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg); } -bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) -{ +bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, + tuh_msc_complete_cb_t complete_cb, uintptr_t arg) { msch_interface_t* p_msc = get_itf(dev_addr); TU_VERIFY(p_msc->mounted); @@ -181,18 +176,16 @@ bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* respons cbw.dir = TUSB_DIR_IN_MASK; cbw.cmd_len = sizeof(scsi_inquiry_t); - scsi_inquiry_t const cmd_inquiry = - { - .cmd_code = SCSI_CMD_INQUIRY, - .alloc_length = sizeof(scsi_inquiry_resp_t) + scsi_inquiry_t const cmd_inquiry = { + .cmd_code = SCSI_CMD_INQUIRY, + .alloc_length = sizeof(scsi_inquiry_resp_t) }; memcpy(cbw.command, &cmd_inquiry, cbw.cmd_len); return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg); } -bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) -{ +bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) { msch_interface_t* p_msc = get_itf(dev_addr); TU_VERIFY(p_msc->configured); @@ -200,16 +193,16 @@ bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_ cbw_init(&cbw, lun); cbw.total_bytes = 0; - cbw.dir = TUSB_DIR_OUT; - cbw.cmd_len = sizeof(scsi_test_unit_ready_t); - cbw.command[0] = SCSI_CMD_TEST_UNIT_READY; - cbw.command[1] = lun; // according to wiki TODO need verification + cbw.dir = TUSB_DIR_OUT; + cbw.cmd_len = sizeof(scsi_test_unit_ready_t); + cbw.command[0] = SCSI_CMD_TEST_UNIT_READY; + cbw.command[1] = lun; // according to wiki TODO need verification return tuh_msc_scsi_command(dev_addr, &cbw, NULL, complete_cb, arg); } -bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) -{ +bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void* response, + tuh_msc_complete_cb_t complete_cb, uintptr_t arg) { msc_cbw_t cbw; cbw_init(&cbw, lun); @@ -217,73 +210,64 @@ bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *response, tuh_ms cbw.dir = TUSB_DIR_IN_MASK; cbw.cmd_len = sizeof(scsi_request_sense_t); - scsi_request_sense_t const cmd_request_sense = - { - .cmd_code = SCSI_CMD_REQUEST_SENSE, - .alloc_length = 18 + scsi_request_sense_t const cmd_request_sense = { + .cmd_code = SCSI_CMD_REQUEST_SENSE, + .alloc_length = 18 }; - memcpy(cbw.command, &cmd_request_sense, cbw.cmd_len); return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg); } -bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) -{ +bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void* buffer, uint32_t lba, uint16_t block_count, + tuh_msc_complete_cb_t complete_cb, uintptr_t arg) { msch_interface_t* p_msc = get_itf(dev_addr); TU_VERIFY(p_msc->mounted); msc_cbw_t cbw; cbw_init(&cbw, lun); - cbw.total_bytes = block_count*p_msc->capacity[lun].block_size; - cbw.dir = TUSB_DIR_IN_MASK; - cbw.cmd_len = sizeof(scsi_read10_t); + cbw.total_bytes = block_count * p_msc->capacity[lun].block_size; + cbw.dir = TUSB_DIR_IN_MASK; + cbw.cmd_len = sizeof(scsi_read10_t); - scsi_read10_t const cmd_read10 = - { - .cmd_code = SCSI_CMD_READ_10, - .lba = tu_htonl(lba), - .block_count = tu_htons(block_count) + scsi_read10_t const cmd_read10 = { + .cmd_code = SCSI_CMD_READ_10, + .lba = tu_htonl(lba), + .block_count = tu_htons(block_count) }; - memcpy(cbw.command, &cmd_read10, cbw.cmd_len); return tuh_msc_scsi_command(dev_addr, &cbw, buffer, complete_cb, arg); } -bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) -{ +bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const* buffer, uint32_t lba, uint16_t block_count, + tuh_msc_complete_cb_t complete_cb, uintptr_t arg) { msch_interface_t* p_msc = get_itf(dev_addr); TU_VERIFY(p_msc->mounted); msc_cbw_t cbw; cbw_init(&cbw, lun); - cbw.total_bytes = block_count*p_msc->capacity[lun].block_size; + cbw.total_bytes = block_count * p_msc->capacity[lun].block_size; cbw.dir = TUSB_DIR_OUT; cbw.cmd_len = sizeof(scsi_write10_t); - scsi_write10_t const cmd_write10 = - { - .cmd_code = SCSI_CMD_WRITE_10, - .lba = tu_htonl(lba), - .block_count = tu_htons(block_count) + scsi_write10_t const cmd_write10 = { + .cmd_code = SCSI_CMD_WRITE_10, + .lba = tu_htonl(lba), + .block_count = tu_htons(block_count) }; - memcpy(cbw.command, &cmd_write10, cbw.cmd_len); - return tuh_msc_scsi_command(dev_addr, &cbw, (void*)(uintptr_t) buffer, complete_cb, arg); + return tuh_msc_scsi_command(dev_addr, &cbw, (void*) (uintptr_t) buffer, complete_cb, arg); } #if 0 // MSC interface Reset (not used now) -bool tuh_msc_reset(uint8_t dev_addr) -{ - tusb_control_request_t const new_request = - { - .bmRequestType_bit = - { +bool tuh_msc_reset(uint8_t dev_addr) { + tusb_control_request_t const new_request = { + .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_OUT @@ -300,79 +284,71 @@ bool tuh_msc_reset(uint8_t dev_addr) //--------------------------------------------------------------------+ // CLASS-USBH API //--------------------------------------------------------------------+ -void msch_init(void) -{ +void msch_init(void) { tu_memclr(_msch_itf, sizeof(_msch_itf)); } -void msch_close(uint8_t dev_addr) -{ - TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, ); +void msch_close(uint8_t dev_addr) { + TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX,); msch_interface_t* p_msc = get_itf(dev_addr); - TU_VERIFY(p_msc->configured, ); + TU_VERIFY(p_msc->configured,); TU_LOG_DRV(" MSCh close addr = %d\r\n", dev_addr); // invoke Application Callback if (p_msc->mounted) { - if(tuh_msc_umount_cb) tuh_msc_umount_cb(dev_addr); + if (tuh_msc_umount_cb) tuh_msc_umount_cb(dev_addr); } tu_memclr(p_msc, sizeof(msch_interface_t)); } -bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) -{ +bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) { msch_interface_t* p_msc = get_itf(dev_addr); msc_cbw_t const * cbw = &p_msc->cbw; msc_csw_t * csw = &p_msc->csw; - switch (p_msc->stage) - { + switch (p_msc->stage) { case MSC_STAGE_CMD: // Must be Command Block - TU_ASSERT(ep_addr == p_msc->ep_out && event == XFER_RESULT_SUCCESS && xferred_bytes == sizeof(msc_cbw_t)); + TU_ASSERT(ep_addr == p_msc->ep_out && event == XFER_RESULT_SUCCESS && xferred_bytes == sizeof(msc_cbw_t)); - if ( cbw->total_bytes && p_msc->buffer ) - { + if (cbw->total_bytes && p_msc->buffer) { // Data stage if any p_msc->stage = MSC_STAGE_DATA; - uint8_t const ep_data = (cbw->dir & TUSB_DIR_IN_MASK) ? p_msc->ep_in : p_msc->ep_out; TU_ASSERT(usbh_edpt_xfer(dev_addr, ep_data, p_msc->buffer, (uint16_t) cbw->total_bytes)); - }else - { + } else { // Status stage p_msc->stage = MSC_STAGE_STATUS; TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, (uint16_t) sizeof(msc_csw_t))); } - break; + break; case MSC_STAGE_DATA: // Status stage p_msc->stage = MSC_STAGE_STATUS; TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, (uint16_t) sizeof(msc_csw_t))); - break; + break; case MSC_STAGE_STATUS: // SCSI op is complete p_msc->stage = MSC_STAGE_IDLE; - if (p_msc->complete_cb) - { - tuh_msc_complete_data_t const cb_data = - { - .cbw = cbw, - .csw = csw, - .scsi_data = p_msc->buffer, - .user_arg = p_msc->complete_arg + if (p_msc->complete_cb) { + tuh_msc_complete_data_t const cb_data = { + .cbw = cbw, + .csw = csw, + .scsi_data = p_msc->buffer, + .user_arg = p_msc->complete_arg }; p_msc->complete_cb(dev_addr, &cb_data); } - break; + break; - // unknown state - default: break; + // unknown state + default: + break; } return true; @@ -381,39 +357,35 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32 //--------------------------------------------------------------------+ // MSC Enumeration //--------------------------------------------------------------------+ - -static void config_get_maxlun_complete (tuh_xfer_t* xfer); -static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data); +static void config_get_maxlun_complete(tuh_xfer_t* xfer); +static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data); static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data); static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data); -bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len) -{ +bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const* desc_itf, uint16_t max_len) { (void) rhport; TU_VERIFY (MSC_SUBCLASS_SCSI == desc_itf->bInterfaceSubClass && - MSC_PROTOCOL_BOT == desc_itf->bInterfaceProtocol); + MSC_PROTOCOL_BOT == desc_itf->bInterfaceProtocol); // msc driver length is fixed - uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t)); + uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + + desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t)); TU_ASSERT(drv_len <= max_len); msch_interface_t* p_msc = get_itf(dev_addr); - tusb_desc_endpoint_t const * ep_desc = (tusb_desc_endpoint_t const *) tu_desc_next(desc_itf); + tusb_desc_endpoint_t const* ep_desc = (tusb_desc_endpoint_t const*) tu_desc_next(desc_itf); - for(uint32_t i=0; i<2; i++) - { + for (uint32_t i = 0; i < 2; i++) { TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType && TUSB_XFER_BULK == ep_desc->bmAttributes.xfer); TU_ASSERT(tuh_edpt_open(dev_addr, ep_desc)); - if ( tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN ) - { + if (TUSB_DIR_IN == tu_edpt_dir(ep_desc->bEndpointAddress)) { p_msc->ep_in = ep_desc->bEndpointAddress; - }else - { + } else { p_msc->ep_out = ep_desc->bEndpointAddress; } - ep_desc = (tusb_desc_endpoint_t const *) tu_desc_next(ep_desc); + ep_desc = (tusb_desc_endpoint_t const*) tu_desc_next(ep_desc); } p_msc->itf_num = desc_itf->bInterfaceNumber; @@ -430,32 +402,31 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num) { //------------- Get Max Lun -------------// TU_LOG_DRV("MSC Get Max Lun\r\n"); tusb_control_request_t const request = { - .bmRequestType_bit = { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_CLASS, - .direction = TUSB_DIR_IN - }, - .bRequest = MSC_REQ_GET_MAX_LUN, - .wValue = 0, - .wIndex = itf_num, - .wLength = 1 + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_CLASS, + .direction = TUSB_DIR_IN + }, + .bRequest = MSC_REQ_GET_MAX_LUN, + .wValue = 0, + .wIndex = itf_num, + .wLength = 1 }; tuh_xfer_t xfer = { - .daddr = dev_addr, - .ep_addr = 0, - .setup = &request, - .buffer = _msch_buffer, - .complete_cb = config_get_maxlun_complete, - .user_data = 0 + .daddr = dev_addr, + .ep_addr = 0, + .setup = &request, + .buffer = _msch_buffer, + .complete_cb = config_get_maxlun_complete, + .user_data = 0 }; TU_ASSERT(tuh_control_xfer(&xfer)); return true; } -static void config_get_maxlun_complete (tuh_xfer_t* xfer) -{ +static void config_get_maxlun_complete(tuh_xfer_t* xfer) { uint8_t const daddr = xfer->daddr; msch_interface_t* p_msc = get_itf(daddr); @@ -471,18 +442,16 @@ static void config_get_maxlun_complete (tuh_xfer_t* xfer) tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete, 0); } -static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) -{ +static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) { msc_cbw_t const* cbw = cb_data->cbw; msc_csw_t const* csw = cb_data->csw; - if (csw->status == 0) - { + if (csw->status == 0) { // Unit is ready, read its capacity TU_LOG_DRV("SCSI Read Capacity\r\n"); - tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer), config_read_capacity_complete, 0); - }else - { + tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer), + config_read_capacity_complete, 0); + } else { // Note: During enumeration, some device fails Test Unit Ready and require a few retries // with Request Sense to start working !! // TODO limit number of retries @@ -493,8 +462,7 @@ static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_d return true; } -static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) -{ +static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) { msc_cbw_t const* cbw = cb_data->cbw; msc_csw_t const* csw = cb_data->csw; @@ -503,8 +471,7 @@ static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_dat return true; } -static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) -{ +static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) { msc_cbw_t const* cbw = cb_data->cbw; msc_csw_t const* csw = cb_data->csw; diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h index 6c0e5c9dd..9ca1b4703 100644 --- a/src/class/msc/msc_host.h +++ b/src/class/msc/msc_host.h @@ -24,8 +24,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef _TUSB_MSC_HOST_H_ -#define _TUSB_MSC_HOST_H_ +#ifndef TUSB_MSC_HOST_H_ +#define TUSB_MSC_HOST_H_ #include "msc.h" @@ -73,7 +73,7 @@ uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun); // Perform a full SCSI command (cbw, data, csw) in non-blocking manner. // Complete callback is invoked when SCSI op is complete. // return true if success, false if there is already pending operation. -bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg); +bool tuh_msc_scsi_command(uint8_t daddr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg); // Perform SCSI Inquiry command // Complete callback is invoked when SCSI op is complete. @@ -123,4 +123,4 @@ bool msch_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, ui } #endif -#endif /* _TUSB_MSC_HOST_H_ */ +#endif diff --git a/src/host/usbh.c b/src/host/usbh.c index e332f35cc..8d75c9726 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -817,6 +817,7 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr) } // Submit an transfer +// TODO call usbh_edpt_release if failed bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { @@ -1713,19 +1714,16 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur return true; } -void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) -{ +void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) { usbh_device_t* dev = get_device(dev_addr); - for(itf_num++; itf_num < CFG_TUH_INTERFACE_MAX; itf_num++) - { + for(itf_num++; itf_num < CFG_TUH_INTERFACE_MAX; itf_num++) { // continue with next valid interface // IAD binding interface such as CDCs should return itf_num + 1 when complete // with usbh_driver_set_config_complete() uint8_t const drv_id = dev->itf2drv[itf_num]; usbh_class_driver_t const * driver = get_driver(drv_id); - if (driver) - { + if (driver) { TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num); driver->set_config(dev_addr, itf_num); break; @@ -1733,23 +1731,19 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) } // all interface are configured - if (itf_num == CFG_TUH_INTERFACE_MAX) - { + if (itf_num == CFG_TUH_INTERFACE_MAX) { enum_full_complete(); - if (is_hub_addr(dev_addr)) - { + if (is_hub_addr(dev_addr)) { TU_LOG(CFG_TUH_LOG_LEVEL, "HUB address = %u is mounted\r\n", dev_addr); - }else - { + }else { // Invoke callback if available if (tuh_mount_cb) tuh_mount_cb(dev_addr); } } } -static void enum_full_complete(void) -{ +static void enum_full_complete(void) { // mark enumeration as complete _dev0.enumerating = 0; -- cgit v1.3.1 From 6b8933cfe838b369c58d4fc9ced8aa5c9382a6d6 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 28 Sep 2023 12:55:59 +0700 Subject: fix build with new freertos host example --- examples/device/cdc_msc_freertos/Makefile | 2 - examples/host/bare_api/Makefile | 10 - examples/host/cdc_msc_hid/Makefile | 10 - examples/host/cdc_msc_hid_freertos/Makefile | 18 +- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 215 +++++++++++++++++++++ examples/host/hid_controller/Makefile | 10 - examples/host/msc_file_explorer/Makefile | 10 - hw/bsp/lpc17/family.mk | 4 +- src/portable/analog/max3421/hcd_max3421.c | 4 +- src/tinyusb.mk | 7 + 10 files changed, 237 insertions(+), 53 deletions(-) create mode 100644 examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h (limited to 'src') diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile index 3ac62a79c..84c833fb5 100644 --- a/examples/device/cdc_msc_freertos/Makefile +++ b/examples/device/cdc_msc_freertos/Makefile @@ -1,5 +1,3 @@ -DEPS_SUBMODULES += lib/FreeRTOS-Kernel - include ../../make.mk FREERTOS_SRC = lib/FreeRTOS-Kernel diff --git a/examples/host/bare_api/Makefile b/examples/host/bare_api/Makefile index 058307c40..161f8c774 100644 --- a/examples/host/bare_api/Makefile +++ b/examples/host/bare_api/Makefile @@ -10,14 +10,4 @@ EXAMPLE_SOURCE += \ SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) -# TinyUSB Host Stack source -SRC_C += \ - src/class/cdc/cdc_host.c \ - src/class/hid/hid_host.c \ - src/class/msc/msc_host.c \ - src/host/hub.c \ - src/host/usbh.c \ - src/portable/ohci/ohci.c \ - src/portable/nxp/lpc17_40/hcd_lpc17_40.c - include ../../rules.mk diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile index 7c16b39d3..15b8a5b31 100644 --- a/examples/host/cdc_msc_hid/Makefile +++ b/examples/host/cdc_msc_hid/Makefile @@ -13,14 +13,4 @@ EXAMPLE_SOURCE = \ SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) -# TinyUSB Host Stack source -SRC_C += \ - src/class/cdc/cdc_host.c \ - src/class/hid/hid_host.c \ - src/class/msc/msc_host.c \ - src/host/hub.c \ - src/host/usbh.c \ - src/portable/ohci/ohci.c \ - src/portable/nxp/lpc17_40/hcd_lpc17_40.c - include ../../rules.mk diff --git a/examples/host/cdc_msc_hid_freertos/Makefile b/examples/host/cdc_msc_hid_freertos/Makefile index 67bb6da55..a9670b4f2 100644 --- a/examples/host/cdc_msc_hid_freertos/Makefile +++ b/examples/host/cdc_msc_hid_freertos/Makefile @@ -5,6 +5,7 @@ FREERTOS_PORTABLE_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC) INC += \ src \ + src/FreeRTOSConfig \ $(TOP)/hw \ $(TOP)/$(FREERTOS_SRC)/include \ $(TOP)/$(FREERTOS_PORTABLE_SRC) \ @@ -19,14 +20,15 @@ EXAMPLE_SOURCE = \ SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) -# TinyUSB Host Stack source +# FreeRTOS source, all files in port folder SRC_C += \ - src/class/cdc/cdc_host.c \ - src/class/hid/hid_host.c \ - src/class/msc/msc_host.c \ - src/host/hub.c \ - src/host/usbh.c \ - src/portable/ohci/ohci.c \ - src/portable/nxp/lpc17_40/hcd_lpc17_40.c + $(FREERTOS_SRC)/list.c \ + $(FREERTOS_SRC)/queue.c \ + $(FREERTOS_SRC)/tasks.c \ + $(FREERTOS_SRC)/timers.c \ + $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.c)) + +SRC_S += \ + $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s)) include ../../rules.mk diff --git a/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..a1fc8bb09 --- /dev/null +++ b/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,215 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + +// Include MCU header +#include "bsp/board_mcu.h" + +#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 + #error "ESP32-Sx should use IDF's FreeRTOSConfig.h" +#endif + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wredundant-decls" +#endif + +// TODO fix later +// FIXME cause redundant-decls warnings +#if CFG_TUSB_MCU == OPT_MCU_MM32F327X + extern u32 SystemCoreClock; +#else + extern uint32_t SystemCoreClock; +#endif + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* Define to trap errors during development. */ +// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) + #define configASSERT(_exp) \ + do {\ + if ( !(_exp) ) { \ + volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ + if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \ + taskDISABLE_INTERRUPTS(); \ + __asm("BKPT #0\n"); \ + }\ + }\ + } while(0) +#else + #define configASSERT( x ) +#endif + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< Date: Thu, 28 Sep 2023 16:15:31 +0700 Subject: improve esp32 ci, build esp32 with -DDMAX3421_HOST=1 for max3421 testing revert change in hcd.h --- .github/workflows/build_esp.yml | 21 +------- .../espressif/boards/espressif_s3_devkitm/board.h | 8 +++ src/host/hcd.h | 3 -- tools/build_esp32.py | 63 ++++++++++++---------- 4 files changed, 45 insertions(+), 50 deletions(-) (limited to 'src') diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml index 29585cb36..897616f09 100644 --- a/.github/workflows/build_esp.yml +++ b/.github/workflows/build_esp.yml @@ -29,12 +29,10 @@ jobs: fail-fast: false matrix: board: - # Alphabetical order # ESP32-S2 - - 'espressif_saola_1' + - 'espressif_kaluga_1' # ESP32-S3 - #- 'espressif_s3_devkitm' - # S3 compile error with "dangerous relocation: call8: call target out of range: memcpy" + - 'espressif_s3_devkitm' steps: - name: Setup Python @@ -48,20 +46,5 @@ jobs: - name: Checkout TinyUSB uses: actions/checkout@v3 - - name: Checkout hathach/linkermap - uses: actions/checkout@v3 - with: - repository: hathach/linkermap - path: linkermap - - name: Build run: docker run --rm -v $PWD:/project -w /project espressif/idf:latest python3 tools/build_esp32.py ${{ matrix.board }} - - - name: Linker Map - run: | - pip install linkermap/ - # find -quit to only print linkermap of 1 board per example - for ex in `ls -d examples/device/*/` - do - find ${ex} -maxdepth 3 -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"' - done diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h index fe33b5c43..4b4151e72 100644 --- a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h +++ b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h @@ -36,6 +36,14 @@ #define BUTTON_PIN 0 #define BUTTON_STATE_ACTIVE 0 +// SPI for USB host shield +#define MAX3421_SPI_HOST SPI2_HOST +#define MAX3421_SCK_PIN 36 +#define MAX3421_MOSI_PIN 35 +#define MAX3421_MISO_PIN 37 +#define MAX3421_CS_PIN 15 +#define MAX3421_INTR_PIN 14 + #ifdef __cplusplus } #endif diff --git a/src/host/hcd.h b/src/host/hcd.h index edffb34cb..2bde289df 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -133,9 +133,6 @@ bool hcd_init(uint8_t rhport); // Interrupt Handler void hcd_int_handler(uint8_t rhport, bool in_isr); -// Interrupt Hanndler (extended version) -void hcd_int_handler_ext(uint8_t rhport, bool in_isr); - // Enable USB interrupt void hcd_int_enable (uint8_t rhport); diff --git a/tools/build_esp32.py b/tools/build_esp32.py index 00783bf58..1f73d3b22 100644 --- a/tools/build_esp32.py +++ b/tools/build_esp32.py @@ -17,8 +17,8 @@ exit_status = 0 total_time = time.monotonic() -build_format = '| {:23} | {:30} | {:18} | {:7} | {:6} | {:6} |' -build_separator = '-' * 100 +build_format = '| {:30} | {:30} | {:18} | {:7} | {:6} | {:6} |' +build_separator = '-' * 107 def filter_with_input(mylist): if len(sys.argv) > 1: @@ -26,12 +26,9 @@ def filter_with_input(mylist): if len(input_args) > 0: mylist[:] = input_args + # Build all examples if not specified -all_examples = [] -for entry in os.scandir("examples/device"): - # Only includes example with CMakeLists.txt for esp32s, and skip board_test to speed up ci - if entry.is_dir() and os.path.exists(entry.path + "/sdkconfig.defaults") and entry.name != 'board_test': - all_examples.append(entry.name) +all_examples = [entry.replace('examples/', '') for entry in glob.glob("examples/*/*_freertos")] filter_with_input(all_examples) all_examples.sort() @@ -46,32 +43,41 @@ all_boards.sort() def build_board(example, board): global success_count, fail_count, skip_count, exit_status start_time = time.monotonic() + + # Check if board is skipped + build_dir = f"cmake-build/cmake-build-{board}/{example}" + + # Generate and build + r = subprocess.run(f"cmake examples/{example} -B {build_dir} -G \"Ninja\" -DBOARD={board} -DMAX3421_HOST=1", + shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) + if r.returncode == 0: + r = subprocess.run(f"cmake --build {build_dir}", shell=True, stdout=subprocess.PIPE, + stderr=subprocess.STDOUT) + build_duration = time.monotonic() - start_time flash_size = "-" sram_size = "-" - # Check if board is skipped - if build_utils.skip_example(example, board): - success = SKIPPED - skip_count += 1 - print(build_format.format(example, board, success, '-', flash_size, sram_size)) + if r.returncode == 0: + success = SUCCEEDED + success_count += 1 + #(flash_size, sram_size) = build_size(example, board) else: - subprocess.run("make -C examples/device/{} BOARD={} clean".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) - build_result = subprocess.run("make -j -C examples/device/{} BOARD={} all".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) - - if build_result.returncode == 0: - success = SUCCEEDED - success_count += 1 - (flash_size, sram_size) = build_size(example, board) - else: - exit_status = build_result.returncode - success = FAILED - fail_count += 1 - - build_duration = time.monotonic() - start_time - print(build_format.format(example, board, success, "{:.2f}s".format(build_duration), flash_size, sram_size)) + exit_status = r.returncode + success = FAILED + fail_count += 1 + + title = build_format.format(example, board, success, "{:.2f}s".format(build_duration), flash_size, sram_size) + if os.getenv('CI'): + # always print build output if in CI + print(f"::group::{title}") + print(r.stdout.decode("utf-8")) + print(f"::endgroup::") + else: + # print build output if failed + print(title) + if r.returncode != 0: + print(r.stdout.decode("utf-8")) - if build_result.returncode != 0: - print(build_result.stdout.decode("utf-8")) def build_size(example, board): #elf_file = 'examples/device/{}/_build/{}/{}-firmware.elf'.format(example, board, board) @@ -82,6 +88,7 @@ def build_size(example, board): sram_size = int(size_list[1]) + int(size_list[2]) return (flash_size, sram_size) + print(build_separator) print(build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM')) print(build_separator) -- cgit v1.3.1 From 67e34267a68c81f62ff315ac990f07a60f4dc93c Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 4 Oct 2023 18:00:32 +0700 Subject: change tuh_max3421_spi_xfer_api() signature tested working with sam d21 and d51, not tested with nrf52, seem not working with esp32 --- hw/bsp/espressif/boards/family.c | 39 +++++++++++++++++++------------ hw/bsp/nrf/family.c | 20 ++++++++++------ hw/bsp/samd21/family.c | 27 +++++++++++---------- hw/bsp/samd51/family.c | 35 +++++++++++++++------------ src/portable/analog/max3421/hcd_max3421.c | 27 ++++++++++++--------- 5 files changed, 88 insertions(+), 60 deletions(-) (limited to 'src') diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index c6a592627..912ca5f35 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -38,7 +38,9 @@ #if ESP_IDF_VERSION_MAJOR > 4 #include "esp_private/periph_ctrl.h" #else + #include "driver/periph_ctrl.h" + #endif // Note; current code use UART0 can cause device to reset while monitoring @@ -46,16 +48,21 @@ #define UART_ID UART_NUM_0 #ifdef NEOPIXEL_PIN + #include "led_strip.h" -static led_strip_t *strip; + +static led_strip_t* strip; #endif #if CFG_TUH_ENABLED && CFG_TUH_MAX3421 + #include "driver/spi_master.h" + static void max3421_init(void); + #endif -static void configure_pins(usb_hal_context_t *usb); +static void configure_pins(usb_hal_context_t* usb); //--------------------------------------------------------------------+ // Implementation @@ -115,11 +122,11 @@ void board_init(void) { #endif } -static void configure_pins(usb_hal_context_t *usb) { +static void configure_pins(usb_hal_context_t* usb) { /* usb_periph_iopins currently configures USB_OTG as USB Device. * Introduce additional parameters in usb_hal_context_t when adding support * for USB Host. */ - for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) { + for (const usb_iopin_dsc_t* iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) { if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) { esp_rom_gpio_pad_select_gpio(iopin->pin); if (iopin->is_output) { @@ -160,7 +167,7 @@ uint32_t board_button_read(void) { } // Get characters from UART -int board_uart_read(uint8_t *buf, int len) { +int board_uart_read(uint8_t* buf, int len) { #if USE_UART return uart_read_bytes(UART_ID, buf, len, 0); #else @@ -169,7 +176,7 @@ int board_uart_read(uint8_t *buf, int len) { } // Send characters to UART -int board_uart_write(void const *buf, int len) { +int board_uart_write(void const* buf, int len) { (void) buf; (void) len; return 0; @@ -216,7 +223,7 @@ static void max3421_init(void) { gpio_set_level(MAX3421_CS_PIN, 1); // SPI - spi_bus_config_t buscfg={ + spi_bus_config_t buscfg = { .miso_io_num = MAX3421_MISO_PIN, .mosi_io_num = MAX3421_MOSI_PIN, .sclk_io_num = MAX3421_SCK_PIN, @@ -228,7 +235,7 @@ static void max3421_init(void) { .data7_io_num = -1, .max_transfer_sz = 1024 }; - ESP_ERROR_CHECK( spi_bus_initialize(MAX3421_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO) ); + ESP_ERROR_CHECK(spi_bus_initialize(MAX3421_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO)); spi_device_interface_config_t max3421_cfg = { .mode = 0, @@ -236,7 +243,7 @@ static void max3421_init(void) { .spics_io_num = -1, // manual control CS .queue_size = 1 }; - ESP_ERROR_CHECK( spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi) ); + ESP_ERROR_CHECK(spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi)); // debug gpio_set_direction(13, GPIO_MODE_OUTPUT); @@ -244,7 +251,7 @@ static void max3421_init(void) { // Interrupt pin max3421_intr_sem = xSemaphoreCreateBinary(); - xTaskCreate(max3421_intr_task, "max3421 intr", 2048, NULL, configMAX_PRIORITIES-2, NULL); + xTaskCreate(max3421_intr_task, "max3421 intr", 2048, NULL, configMAX_PRIORITIES - 2, NULL); gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT); gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE); @@ -267,18 +274,20 @@ void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) { gpio_set_level(MAX3421_CS_PIN, active ? 0 : 1); } -bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) { +bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) { (void) rhport; - if (tx_len == 0) { + if (tx_buf == NULL) { // fifo read, transmit rx_buf as dummy tx_buf = rx_buf; - tx_len = rx_len; } + // length in bits + size_t const len_bits = xfer_bytes << 3; + spi_transaction_t xact = { - .length = tx_len << 3, // length in bits - .rxlength = rx_len << 3, // length in bits + .length = len_bits, + .rxlength = rx_buf ? len_bits : 0, .tx_buffer = tx_buf, .rx_buffer = rx_buf }; diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index 631f53fcd..c431389f3 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -95,7 +95,9 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) { //------------- Host using MAX2341E -------------// #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 + static void max3421_init(void); + static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1); #endif @@ -203,15 +205,15 @@ uint32_t board_button_read(void) { return BUTTON_STATE_ACTIVE == nrf_gpio_pin_read(BUTTON_PIN); } -int board_uart_read(uint8_t *buf, int len) { +int board_uart_read(uint8_t* buf, int len) { (void) buf; (void) len; return 0; // return NRFX_SUCCESS == nrfx_uart_rx(&_uart_id, buf, (size_t) len) ? len : 0; } -int board_uart_write(void const *buf, int len) { - return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const *) buf, (size_t) len)) ? len : 0; +int board_uart_write(void const* buf, int len) { + return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len)) ? len : 0; } #if CFG_TUSB_OS == OPT_OS_NONE @@ -323,6 +325,7 @@ static void max3421_init(void) { nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true); } +// API to enable/disable MAX3421 INTR pin interrupt void tuh_max3421_int_api(uint8_t rhport, bool enabled) { (void) rhport; @@ -335,22 +338,25 @@ void tuh_max3421_int_api(uint8_t rhport, bool enabled) { } } +// API to control MAX3421 SPI CS void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) { (void) rhport; nrf_gpio_pin_write(MAX3421_CS_PIN, active ? 0 : 1); } -bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) { +// API to transfer data with MAX3421 SPI +// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only +bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) { (void) rhport; nrfx_spim_xfer_desc_t xfer = { .p_tx_buffer = tx_buf, - .tx_length = tx_len, + .tx_length = tx_buf ? xfer_bytes : 0, .p_rx_buffer = rx_buf, - .rx_length = rx_len, + .rx_length = rx_buf ? xfer_bytes : 0, }; - return (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS); + return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS; } #endif diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c index b9365fc3f..ccb2c99b1 100644 --- a/hw/bsp/samd21/family.c +++ b/hw/bsp/samd21/family.c @@ -72,6 +72,7 @@ static void uart_init(void); #define MAX3421_SERCOM TU_XSTRCAT(SERCOM, MAX3421_SERCOM_ID) static void max3421_init(void); + #endif void board_init(void) { @@ -237,13 +238,13 @@ int board_uart_write(void const * buf, int len) static void uart_init(void) { } -int board_uart_read(uint8_t *buf, int len) { +int board_uart_read(uint8_t* buf, int len) { (void) buf; (void) len; return 0; } -int board_uart_write(void const *buf, int len) { +int board_uart_write(void const* buf, int len) { (void) buf; (void) len; return 0; @@ -261,6 +262,7 @@ void SysTick_Handler(void) { uint32_t board_millis(void) { return system_ticks; } + #endif //--------------------------------------------------------------------+ @@ -278,8 +280,8 @@ static void max3421_init(void) { // Configure GCLK for SERCOM // GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_SERCOM4_CORE | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN; - GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_SERCOM0_CORE_Val+MAX3421_SERCOM_ID) | - GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN; + GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_SERCOM0_CORE_Val + MAX3421_SERCOM_ID) | + GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN; while (GCLK->STATUS.bit.SYNCBUSY); Sercom* sercom = MAX3421_SERCOM; @@ -293,7 +295,7 @@ static void max3421_init(void) { // Set up SPI in master mode, MSB first, SPI mode 0 sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_DOPO(MAX3421_TX_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_RX_PAD) | - SERCOM_SPI_CTRLA_MODE(3); + SERCOM_SPI_CTRLA_MODE(3); sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN; while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1); @@ -366,6 +368,7 @@ void EIC_Handler(void) { tuh_int_handler(1, true); } +// API to enable/disable MAX3421 INTR pin interrupt void tuh_max3421_int_api(uint8_t rhport, bool enabled) { (void) rhport; @@ -376,24 +379,26 @@ void tuh_max3421_int_api(uint8_t rhport, bool enabled) { } } +// API to control MAX3421 SPI CS void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) { (void) rhport; gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1); } -bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) { +// API to transfer data with MAX3421 SPI +// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only +bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) { (void) rhport; Sercom* sercom = MAX3421_SERCOM; - size_t count = 0; - while (count < tx_len || count < rx_len) { + for (size_t count = 0; count < xfer_bytes; count++) { // Wait for the transmit buffer to be empty while (!sercom->SPI.INTFLAG.bit.DRE); // Write data to be transmitted uint8_t data = 0x00; - if (count < tx_len) { + if (tx_buf) { data = tx_buf[count]; } @@ -404,11 +409,9 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l // Read received data data = (uint8_t) sercom->SPI.DATA.reg; - if (count < rx_len) { + if (rx_buf) { rx_buf[count] = data; } - - count++; } // wait for bus idle and clear flags diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c index 4d43c7745..bca18e1a2 100644 --- a/hw/bsp/samd51/family.c +++ b/hw/bsp/samd51/family.c @@ -81,6 +81,7 @@ void USB_3_Handler(void) { #define MAX3421_EIC_Handler TU_XSTRCAT3(EIC_, MAX3421_INTR_EIC_ID, _Handler) static void max3421_init(void); + #endif void board_init(void) { @@ -153,13 +154,13 @@ uint32_t board_button_read(void) { return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1; } -int board_uart_read(uint8_t *buf, int len) { +int board_uart_read(uint8_t* buf, int len) { (void) buf; (void) len; return 0; } -int board_uart_write(void const *buf, int len) { +int board_uart_write(void const* buf, int len) { (void) buf; (void) len; return 0; @@ -175,6 +176,7 @@ void SysTick_Handler(void) { uint32_t board_millis(void) { return system_ticks; } + #endif //--------------------------------------------------------------------+ @@ -189,7 +191,7 @@ static void max3421_init(void) { uint32_t const baudrate = 12000000u; struct { - volatile uint32_t *mck_apb; + volatile uint32_t* mck_apb; uint32_t mask; uint8_t gclk_id_core; uint8_t gclk_id_slow; @@ -214,8 +216,10 @@ static void max3421_init(void) { *sercom_clock[MAX3421_SERCOM_ID].mck_apb |= sercom_clock[MAX3421_SERCOM_ID].mask; // Configure GCLK for SERCOM - GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_core].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); - GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_slow].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); + GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_core].reg = + GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); + GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_slow].reg = + GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); // Disable the SPI module sercom->SPI.CTRLA.bit.ENABLE = 0; @@ -226,7 +230,7 @@ static void max3421_init(void) { // Set up SPI in master mode, MSB first, SPI mode 0 sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_DOPO(MAX3421_TX_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_RX_PAD) | - SERCOM_SPI_CTRLA_MODE(3); + SERCOM_SPI_CTRLA_MODE(3); sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN; while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1); @@ -278,9 +282,9 @@ static void max3421_init(void) { while (EIC->SYNCBUSY.bit.ENABLE); // Configure EIC to trigger on falling edge - volatile uint32_t * eic_config; + volatile uint32_t* eic_config; uint8_t sense_shift; - if ( MAX3421_INTR_EIC_ID < 8 ) { + if (MAX3421_INTR_EIC_ID < 8) { eic_config = &EIC->CONFIG[0].reg; sense_shift = MAX3421_INTR_EIC_ID * 4; } else { @@ -312,6 +316,7 @@ void MAX3421_EIC_Handler(void) { tuh_int_handler(1, true); } +// API to enable/disable MAX3421 INTR pin interrupt void tuh_max3421_int_api(uint8_t rhport, bool enabled) { (void) rhport; @@ -323,24 +328,26 @@ void tuh_max3421_int_api(uint8_t rhport, bool enabled) { } } +// API to control MAX3421 SPI CS void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) { (void) rhport; gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1); } -bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) { +// API to transfer data with MAX3421 SPI +// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only +bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) { (void) rhport; Sercom* sercom = MAX3421_SERCOM; - size_t count = 0; - while (count < tx_len || count < rx_len) { + for (size_t count = 0; count < xfer_bytes; count++) { // Wait for the transmit buffer to be empty while (!sercom->SPI.INTFLAG.bit.DRE); // Write data to be transmitted uint8_t data = 0x00; - if (count < tx_len) { + if (tx_buf) { data = tx_buf[count]; } @@ -351,11 +358,9 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l // Read received data data = (uint8_t) sercom->SPI.DATA.reg; - if (count < rx_len) { + if (rx_buf) { rx_buf[count] = data; } - - count++; } // wait for bus idle and clear flags diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 77912a4c9..787c1e511 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -210,16 +210,21 @@ static max3421_data_t _hcd_data; // API: SPI transfer with MAX3421E, must be implemented by application //--------------------------------------------------------------------+ -void tuh_max3421_spi_cs_api(uint8_t rhport, bool active); -bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len); -void tuh_max3421_int_api(uint8_t rhport, bool enabled); +// API to control MAX3421 SPI CS +extern void tuh_max3421_spi_cs_api(uint8_t rhport, bool active); -static void handle_connect_irq(uint8_t rhport, bool in_isr); -static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr); +// API to transfer data with MAX3421 SPI +// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only +extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes); + +// API to enable/disable MAX3421 INTR pin interrupt +extern void tuh_max3421_int_api(uint8_t rhport, bool enabled); //--------------------------------------------------------------------+ // SPI Helper //--------------------------------------------------------------------+ +static void handle_connect_irq(uint8_t rhport, bool in_isr); +static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr); static void max3421_spi_lock(uint8_t rhport, bool in_isr) { // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr @@ -249,9 +254,9 @@ static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint max3421_spi_lock(rhport, in_isr); - tuh_max3421_spi_xfer_api(rhport, ®, 1, &hirq, 1); + tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); _hcd_data.hirq = hirq; - tuh_max3421_spi_xfer_api(rhport, buffer, len, NULL, 0); + tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len); max3421_spi_unlock(rhport, in_isr); @@ -263,9 +268,9 @@ static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_is max3421_spi_lock(rhport, in_isr); - tuh_max3421_spi_xfer_api(rhport, ®, 1, &hirq, 1); + tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); _hcd_data.hirq = hirq; - tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len); + tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len); max3421_spi_unlock(rhport, in_isr); } @@ -276,7 +281,7 @@ static void reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr) { max3421_spi_lock(rhport, in_isr); - tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2); + tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2); max3421_spi_unlock(rhport, in_isr); @@ -290,7 +295,7 @@ static uint8_t reg_read(uint8_t rhport, uint8_t reg, bool in_isr) { max3421_spi_lock(rhport, in_isr); - bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2); + bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2); max3421_spi_unlock(rhport, in_isr); -- cgit v1.3.1 From ce627f431831e1fbaa3bb7bad35a489b8006b749 Mon Sep 17 00:00:00 2001 From: "denis.krasutski" Date: Fri, 6 Oct 2023 13:04:54 +0300 Subject: feat(ch32f20x): add support of ch32f20x --- .gitignore | 1 + README.rst | 2 +- docs/reference/dependencies.rst | 1 + docs/reference/supported.rst | 5 +- hw/bsp/board_mcu.h | 3 + hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h | 59 ++ hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk | 7 + hw/bsp/ch32f20x/ch32f205.ld | 111 +++ hw/bsp/ch32f20x/ch32f20x_conf.h | 40 + hw/bsp/ch32f20x/ch32f20x_it.c | 35 + hw/bsp/ch32f20x/ch32f20x_it.h | 25 + hw/bsp/ch32f20x/core_cm3.h | 11 + hw/bsp/ch32f20x/debug_uart.c | 105 +++ hw/bsp/ch32f20x/debug_uart.h | 31 + hw/bsp/ch32f20x/family.c | 141 ++++ hw/bsp/ch32f20x/family.mk | 30 + hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s | 493 +++++++++++ hw/bsp/ch32f20x/system_ch32f20x.c | 1122 ++++++++++++++++++++++++++ hw/bsp/ch32f20x/system_ch32f20x.h | 28 + hw/bsp/ch32v307/family.mk | 2 +- src/common/tusb_mcu.h | 4 + src/portable/wch/ch32_usbhs_reg.h | 349 ++++++++ src/portable/wch/ch32v307/ch32_usbhs_reg.h | 345 -------- src/portable/wch/ch32v307/dcd_usbhs.c | 391 --------- src/portable/wch/dcd_ch32_usbhs.c | 391 +++++++++ src/tusb_option.h | 1 + tools/get_deps.py | 3 + tools/iar_template.ipcf | 4 +- 28 files changed, 2999 insertions(+), 741 deletions(-) create mode 100644 hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h create mode 100644 hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk create mode 100644 hw/bsp/ch32f20x/ch32f205.ld create mode 100644 hw/bsp/ch32f20x/ch32f20x_conf.h create mode 100644 hw/bsp/ch32f20x/ch32f20x_it.c create mode 100644 hw/bsp/ch32f20x/ch32f20x_it.h create mode 100644 hw/bsp/ch32f20x/core_cm3.h create mode 100644 hw/bsp/ch32f20x/debug_uart.c create mode 100644 hw/bsp/ch32f20x/debug_uart.h create mode 100644 hw/bsp/ch32f20x/family.c create mode 100644 hw/bsp/ch32f20x/family.mk create mode 100644 hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s create mode 100644 hw/bsp/ch32f20x/system_ch32f20x.c create mode 100644 hw/bsp/ch32f20x/system_ch32f20x.h create mode 100644 src/portable/wch/ch32_usbhs_reg.h delete mode 100644 src/portable/wch/ch32v307/ch32_usbhs_reg.h delete mode 100644 src/portable/wch/ch32v307/dcd_usbhs.c create mode 100644 src/portable/wch/dcd_ch32_usbhs.c (limited to 'src') diff --git a/.gitignore b/.gitignore index c665d6c73..e6ccec736 100644 --- a/.gitignore +++ b/.gitignore @@ -81,6 +81,7 @@ hw/mcu/st/stm32u5xx_hal_driver hw/mcu/st/stm32wbxx_hal_driver hw/mcu/ti hw/mcu/wch/ch32v307 +hw/mcu/wch/ch32f20x lib/CMSIS_5 lib/FreeRTOS-Kernel lib/lwip diff --git a/README.rst b/README.rst index aef310b98..919596e67 100644 --- a/README.rst +++ b/README.rst @@ -60,7 +60,7 @@ The stack supports the following MCUs: - **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, G0, G4, L0, L1, L4, L4+, WB - **TI:** MSP430, MSP432E4, TM4C123 - **ValentyUSB:** eptri -- **WCH:** CH32V307 +- **WCH:** CH32V307, CH32F20x Here is the list of `Supported Devices`_ that can be used with provided examples. diff --git a/docs/reference/dependencies.rst b/docs/reference/dependencies.rst index 130527e2c..d532a3a1e 100644 --- a/docs/reference/dependencies.rst +++ b/docs/reference/dependencies.rst @@ -56,6 +56,7 @@ hw/mcu/st/stm32u5xx_hal_driver https://github.com/STMicroelectronics/ hw/mcu/st/stm32wbxx_hal_driver https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git 2c5f06638be516c1b772f768456ba637f077bac8 hw/mcu/ti https://github.com/hathach/ti_driver.git 143ed6cc20a7615d042b03b21e070197d473e6e5 hw/mcu/wch/ch32v307 https://github.com/openwch/ch32v307.git 17761f5cf9dbbf2dcf665b7c04934188add20082 +hw/mcu/wch/ch32f20x https://github.com/openwch/ch32f20x.git 77c4095087e5ed2c548ec9058e655d0b8757663b lib/CMSIS_5 https://github.com/ARM-software/CMSIS_5.git 20285262657d1b482d132d20d755c8c330d55c1f lib/FreeRTOS-Kernel https://github.com/FreeRTOS/FreeRTOS-Kernel.git def7d2df2b0506d3d249334974f51e427c17a41c lib/lwip https://github.com/lwip-tcpip/lwip.git 159e31b689577dbf69cf0683bbaffbd71fa5ee10 diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index aed64782c..8843dd405 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -109,6 +109,8 @@ Supported MCUs | ValentyUSB | eptri | ✔ | ✖ | ✖ | eptri | | +--------------+-----------------------+--------+------+-----------+-------------------+--------------+ | WCH | CH32V307 | ✔ | | ✔ | ch32v307 | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | CH32F20x | ✔ | | ✔ | ch32f205 | | +--------------+-----------------------+--------+------+-----------+-------------------+--------------+ @@ -415,4 +417,5 @@ Tomu WCH --- -- `CH32V307V-R1-1v0 ` +- `CH32V307V-R1-1v0 `__ +- `CH32F205R-R0-1v0 `__ diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index e5d2bb608..4ce5c4139 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -161,6 +161,9 @@ #elif CFG_TUSB_MCU == OPT_MCU_TM4C123 #include "TM4C123.h" +#elif CFG_TUSB_MCU == OPT_MCU_CH32F20X + #include "ch32f20x.h" + #elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837) // no header needed diff --git a/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h new file mode 100644 index 000000000..d5849bddb --- /dev/null +++ b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h @@ -0,0 +1,59 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023, Denis Krasutski + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// LED: need to wire pin LED1 to PC0 in the P1 header +#define LED_PORT GPIOC +#define LED_PIN GPIO_Pin_1 +#define LED_STATE_ON 0 +#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE) + +// Button: need to wire pin KEY to PC1 in the P1 header +#define BUTTON_PORT GPIOC +#define BUTTON_PIN GPIO_Pin_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE) + +// UART +#define UART_DEV USART2 +#define UART_DEV_IRQn USART2_IRQn +#define UART_DEV_IRQHandler USART2_IRQHandler +#define UART_DEV_GPIO_PORT GPIOA +#define UART_DEV_TX_PIN GPIO_Pin_2 +#define UART_DEV_CLK_EN() do { \ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); \ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); \ + } while(0) + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk new file mode 100644 index 000000000..f0e9bf30f --- /dev/null +++ b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk @@ -0,0 +1,7 @@ +LD_FILE = $(FAMILY_PATH)/ch32f205.ld + +SRC_S += \ + $(FAMILY_PATH)/startup_gcc_ch32f20x_d8c.s + +CFLAGS += \ + -DCH32F20x_D8C diff --git a/hw/bsp/ch32f20x/ch32f205.ld b/hw/bsp/ch32f20x/ch32f205.ld new file mode 100644 index 000000000..7c8d04cc5 --- /dev/null +++ b/hw/bsp/ch32f20x/ch32f205.ld @@ -0,0 +1,111 @@ +ENTRY(Reset_Handler) + +_Min_Heap_Size = 0x200; +_Min_Stack_Size = 0x400; + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K +} +SECTIONS +{ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + _stext = .; + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + _etext = .; + } >FLASH + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + _sidata = LOADADDR(.data); + .data : + { + . = ALIGN(4); + _sdata = .; + *(.data) + *(.data*) + . = ALIGN(4); + _edata = .; + } >RAM AT> FLASH + . = ALIGN(4); + .bss : + { + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + __HeapStart = .; + . = . + _Min_Heap_Size; + __HeapEnd = .; + __StackLimit = .; + . = . + _Min_Stack_Size; + __StackTop = .; + . = ALIGN(4); + } >RAM +_estack = __StackTop; +_sstack = __StackLimit; + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/ch32f20x/ch32f20x_conf.h b/hw/bsp/ch32f20x/ch32f20x_conf.h new file mode 100644 index 000000000..f94da5dec --- /dev/null +++ b/hw/bsp/ch32f20x/ch32f20x_conf.h @@ -0,0 +1,40 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32f20x_conf.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/08/08 + * Description : Library configuration file. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32F20x_CONF_H +#define __CH32F20x_CONF_H + +#include "ch32f20x_adc.h" +#include "ch32f20x_bkp.h" +#include "ch32f20x_can.h" +#include "ch32f20x_crc.h" +#include "ch32f20x_dac.h" +#include "ch32f20x_dbgmcu.h" +#include "ch32f20x_dma.h" +#include "ch32f20x_exti.h" +#include "ch32f20x_flash.h" +#include "ch32f20x_fsmc.h" +#include "ch32f20x_gpio.h" +#include "ch32f20x_i2c.h" +#include "ch32f20x_iwdg.h" +#include "ch32f20x_pwr.h" +#include "ch32f20x_rcc.h" +#include "ch32f20x_rtc.h" +#include "ch32f20x_sdio.h" +#include "ch32f20x_spi.h" +#include "ch32f20x_tim.h" +#include "ch32f20x_usart.h" +#include "ch32f20x_wwdg.h" +#include "ch32f20x_it.h" +#include "ch32f20x_misc.h" + +#endif /* __CH32F20x_CONF_H */ + diff --git a/hw/bsp/ch32f20x/ch32f20x_it.c b/hw/bsp/ch32f20x/ch32f20x_it.c new file mode 100644 index 000000000..94e28e380 --- /dev/null +++ b/hw/bsp/ch32f20x/ch32f20x_it.c @@ -0,0 +1,35 @@ +#include "ch32f20x_it.h" + +#include "ch32f20x.h" + +/* -------------------------------------------------------------------------- */ + +void NMI_Handler(void) { + +} + +/* -------------------------------------------------------------------------- */ + +void MemManage_Handler(void) { + +} + +/* -------------------------------------------------------------------------- */ + +void BusFault_Handler(void) { + +} + +/* -------------------------------------------------------------------------- */ + +void UsageFault_Handler(void) { + +} + +/* -------------------------------------------------------------------------- */ + +void DebugMon_Handler(void) { + +} + +/* -------------------------------------------------------------------------- */ diff --git a/hw/bsp/ch32f20x/ch32f20x_it.h b/hw/bsp/ch32f20x/ch32f20x_it.h new file mode 100644 index 000000000..34f3bbf96 --- /dev/null +++ b/hw/bsp/ch32f20x/ch32f20x_it.h @@ -0,0 +1,25 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32f20x_it.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/08/08 +* Description : This file contains the headers of the interrupt handlers. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32F20xIT_H +#define __CH32F20xIT_H + +#include "ch32f20x.h" + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void DebugMon_Handler(void); + + +#endif /* __CH32F20xIT_H */ diff --git a/hw/bsp/ch32f20x/core_cm3.h b/hw/bsp/ch32f20x/core_cm3.h new file mode 100644 index 000000000..c35a4eec3 --- /dev/null +++ b/hw/bsp/ch32f20x/core_cm3.h @@ -0,0 +1,11 @@ +/* There is core_cm3.h wrapper just to avoid warnings from CMSIS headers */ +/* if you want use original file add to make file: + INC += \ + $(TOP)/$(CH32F20X_SDK_SRC)/CMSIS +*/ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-prototypes" + +#include <../../CMSIS/core_cm3.h> + +#pragma GCC diagnostic pop diff --git a/hw/bsp/ch32f20x/debug_uart.c b/hw/bsp/ch32f20x/debug_uart.c new file mode 100644 index 000000000..a595eb6f7 --- /dev/null +++ b/hw/bsp/ch32f20x/debug_uart.c @@ -0,0 +1,105 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Denis Krasutski + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ +#include + +#include "board.h" +#include "debug_uart.h" + +#define UART_RINGBUFFER_SIZE_TX 64 +#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1) + +static char tx_buf[UART_RINGBUFFER_SIZE_TX]; +static unsigned int tx_produce = 0; +static volatile unsigned int tx_consume = 0; + +void UART_DEV_IRQHandler(void) +{ + if(USART_GetITStatus(UART_DEV, USART_IT_TC) != RESET) { + USART_ClearITPendingBit(UART_DEV, USART_IT_TC); + + if(tx_consume != tx_produce) { + USART_SendData(UART_DEV, tx_buf[tx_consume]); + tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX; + } + } +} + +void uart_write(char c) +{ + unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX; + + NVIC_DisableIRQ(UART_DEV_IRQn); + if((tx_consume != tx_produce) || (USART_GetFlagStatus(UART_DEV, USART_FLAG_TXE) == RESET)) { + tx_buf[tx_produce] = c; + tx_produce = tx_produce_next; + } else { + USART_SendData(UART_DEV, c); + } + NVIC_EnableIRQ(UART_DEV_IRQn); +} + +void uart_sync(void) +{ + while(tx_consume != tx_produce) { + //Waiting for transfer complete + } +} + +void usart_printf_init(uint32_t baudrate) +{ + tx_produce = 0; + tx_consume = 0; + + UART_DEV_CLK_EN(); + + GPIO_InitTypeDef gpio_config = { + .GPIO_Pin = UART_DEV_TX_PIN, + .GPIO_Speed = GPIO_Speed_50MHz, + .GPIO_Mode = GPIO_Mode_AF_PP, + }; + GPIO_Init(UART_DEV_GPIO_PORT, &gpio_config); + + USART_InitTypeDef uart_config = { + .USART_BaudRate = baudrate, + .USART_WordLength = USART_WordLength_8b, + .USART_StopBits = USART_StopBits_1, + .USART_Parity = USART_Parity_No, + .USART_HardwareFlowControl = USART_HardwareFlowControl_None, + .USART_Mode = USART_Mode_Tx, + }; + + USART_Init(UART_DEV, &uart_config); + USART_ITConfig(UART_DEV, USART_IT_TC, ENABLE); + USART_Cmd(UART_DEV, ENABLE); + + NVIC_InitTypeDef nvic_config = { + .NVIC_IRQChannel = UART_DEV_IRQn, + .NVIC_IRQChannelPreemptionPriority = 1, + .NVIC_IRQChannelSubPriority = 3, + .NVIC_IRQChannelCmd = ENABLE, + }; + NVIC_Init(&nvic_config); +} diff --git a/hw/bsp/ch32f20x/debug_uart.h b/hw/bsp/ch32f20x/debug_uart.h new file mode 100644 index 000000000..10284cf6f --- /dev/null +++ b/hw/bsp/ch32f20x/debug_uart.h @@ -0,0 +1,31 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Denis Krasutski + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include + +void uart_write(char c); +void uart_sync(void); +void usart_printf_init(uint32_t baudrate); diff --git a/hw/bsp/ch32f20x/family.c b/hw/bsp/ch32f20x/family.c new file mode 100644 index 000000000..9717832d6 --- /dev/null +++ b/hw/bsp/ch32f20x/family.c @@ -0,0 +1,141 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Denis Krasutski + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "stdio.h" +#include "debug_uart.h" + +#include "ch32f20x.h" + +#include "bsp/board_api.h" +#include "board.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ + +void USBHS_IRQHandler(void) +{ + tud_int_handler(0); +} + +void board_init(void) { + + /* Disable interrupts during init */ + __disable_irq(); + +#if CFG_TUSB_OS == OPT_OS_NONE + SysTick_Config(SystemCoreClock / 1000); +#endif + +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USBHS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + + usart_printf_init(115200); + + // USB HS Clock config + RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY); + RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE); + RCC_USBHSConfig(RCC_USBPLL_Div2); + RCC_USBHSPLLCKREFCLKConfig(RCC_USBHSPLLCKREFCLK_4M); + RCC_USBHSPHYPLLALIVEcmd(ENABLE); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHS, ENABLE); + + // LED + LED_CLOCK_EN(); + GPIO_InitTypeDef led_pin_config = { + .GPIO_Pin = LED_PIN, + .GPIO_Mode = GPIO_Mode_Out_OD, + .GPIO_Speed = GPIO_Speed_50MHz, + }; + GPIO_Init(LED_PORT, &led_pin_config); + + // Button + BUTTON_CLOCK_EN(); + GPIO_InitTypeDef button_pin_config = { + .GPIO_Pin = BUTTON_PIN, + .GPIO_Mode = GPIO_Mode_IPU, + .GPIO_Speed = GPIO_Speed_50MHz, + }; + GPIO_Init(BUTTON_PORT, &button_pin_config); + + /* Enable interrupts globally */ + __enable_irq(); +} + +#if CFG_TUSB_OS == OPT_OS_NONE + +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} + +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + GPIO_WriteBit(LED_PORT, LED_PIN, state); +} + +uint32_t board_button_read(void) +{ + return BUTTON_STATE_ACTIVE == GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN); +} + +int board_uart_read(uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) +{ + int txsize = len; + while ( txsize-- ) + { + uart_write(*(uint8_t const*) buf); + buf++; + } + return len; +} diff --git a/hw/bsp/ch32f20x/family.mk b/hw/bsp/ch32f20x/family.mk new file mode 100644 index 000000000..c08451b9c --- /dev/null +++ b/hw/bsp/ch32f20x/family.mk @@ -0,0 +1,30 @@ +# Submodules +CH32F20X_SDK = hw/mcu/wch/ch32f20x +DEPS_SUBMODULES += $(CH32F20X_SDK) + +# WCH-SDK paths +CH32F20X_SDK_SRC = $(CH32F20X_SDK)/EVT/EXAM/SRC + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m3 + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_CH32F20X \ + -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + +SRC_C += \ + src/portable/wch/dcd_ch32_usbhs.c \ + $(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_gpio.c \ + $(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_misc.c \ + $(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_rcc.c \ + $(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_usart.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(CH32F20X_SDK_SRC)/StdPeriphDriver/inc + +# For freeRTOS port source +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3 + +flash: flash-stlink diff --git a/hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s b/hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s new file mode 100644 index 000000000..2ecac2ac1 --- /dev/null +++ b/hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s @@ -0,0 +1,493 @@ +/** + ****************************************************************************** + * @file startup_gcc_ch32f20x_d8c.s + * @author Denis Krasutski + * @brief CH32F205 Devices vector table + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m3 +.thumb +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.section .text.Reset_Handler +.weak Reset_Handler +.type Reset_Handler, %function +Reset_Handler: + /* set stack pointer */ + ldr sp, =_estack + /* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + + /* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss +FillZerobss: + str r3, [r2] + adds r2, r2, #4 +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + /* Call static constructors */ + bl __libc_init_array + /* Call the application's entry point.*/ + bl main + bx lr + .size Reset_Handler, .-Reset_Handler + +.section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + +/******************************************************************************* + External Interrupts +*******************************************************************************/ +.word WWDG_IRQHandler +.word PVD_IRQHandler +.word TAMPER_IRQHandler +.word RTC_IRQHandler +.word FLASH_IRQHandler +.word RCC_IRQHandler +.word EXTI0_IRQHandler +.word EXTI1_IRQHandler +.word EXTI2_IRQHandler +.word EXTI3_IRQHandler +.word EXTI4_IRQHandler +.word DMA1_Channel1_IRQHandler +.word DMA1_Channel2_IRQHandler +.word DMA1_Channel3_IRQHandler +.word DMA1_Channel4_IRQHandler +.word DMA1_Channel5_IRQHandler +.word DMA1_Channel6_IRQHandler +.word DMA1_Channel7_IRQHandler +.word ADC1_2_IRQHandler +.word USB_HP_CAN1_TX_IRQHandler +.word USB_LP_CAN1_RX0_IRQHandler +.word CAN1_RX1_IRQHandler +.word CAN1_SCE_IRQHandler +.word EXTI9_5_IRQHandler +.word TIM1_BRK_IRQHandler +.word TIM1_UP_IRQHandler +.word TIM1_TRG_COM_IRQHandler +.word TIM1_CC_IRQHandler +.word TIM2_IRQHandler +.word TIM3_IRQHandler +.word TIM4_IRQHandler +.word I2C1_EV_IRQHandler +.word I2C1_ER_IRQHandler +.word I2C2_EV_IRQHandler +.word I2C2_ER_IRQHandler +.word SPI1_IRQHandler +.word SPI2_IRQHandler +.word USART1_IRQHandler +.word USART2_IRQHandler +.word USART3_IRQHandler +.word EXTI15_10_IRQHandler +.word RTCAlarm_IRQHandler +.word 0 +.word TIM8_BRK_IRQHandler +.word TIM8_UP_IRQHandler +.word TIM8_TRG_COM_IRQHandler +.word TIM8_CC_IRQHandler +.word RNG_IRQHandler +.word FSMC_IRQHandler +.word SDIO_IRQHandler +.word TIM5_IRQHandler +.word SPI3_IRQHandler +.word UART4_IRQHandler +.word UART5_IRQHandler +.word TIM6_IRQHandler +.word TIM7_IRQHandler +.word DMA2_Channel1_IRQHandler +.word DMA2_Channel2_IRQHandler +.word DMA2_Channel3_IRQHandler +.word DMA2_Channel4_IRQHandler +.word DMA2_Channel5_IRQHandler +.word ETH_IRQHandler +.word ETH_WKUP_IRQHandler +.word CAN2_TX_IRQHandler +.word CAN2_RX0_IRQHandler +.word CAN2_RX1_IRQHandler +.word CAN2_SCE_IRQHandler +.word OTG_FS_IRQHandler +.word USBHSWakeup_IRQHandler +.word USBHS_IRQHandler +.word DVP_IRQHandler +.word UART6_IRQHandler +.word UART7_IRQHandler +.word UART8_IRQHandler +.word TIM9_BRK_IRQHandler +.word TIM9_UP_IRQHandler +.word TIM9_TRG_COM_IRQHandler +.word TIM9_CC_IRQHandler +.word TIM10_BRK_IRQHandler +.word TIM10_UP_IRQHandler +.word TIM10_TRG_COM_IRQHandler +.word TIM10_CC_IRQHandler +.word DMA2_Channel6_IRQHandler +.word DMA2_Channel7_IRQHandler +.word DMA2_Channel8_IRQHandler +.word DMA2_Channel9_IRQHandler +.word DMA2_Channel10_IRQHandler +.word DMA2_Channel11_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases +* +*******************************************************************************/ +.weak NMI_Handler +.thumb_set NMI_Handler,Default_Handler + +.weak HardFault_Handler +.thumb_set HardFault_Handler,Default_Handler + +.weak MemManage_Handler +.thumb_set MemManage_Handler,Default_Handler + +.weak BusFault_Handler +.thumb_set BusFault_Handler,Default_Handler + +.weak UsageFault_Handler +.thumb_set UsageFault_Handler,Default_Handler + +.weak SVC_Handler +.thumb_set SVC_Handler,Default_Handler + +.weak DebugMon_Handler +.thumb_set DebugMon_Handler,Default_Handler + +.weak PendSV_Handler +.thumb_set PendSV_Handler,Default_Handler + +.weak SysTick_Handler +.thumb_set SysTick_Handler,Default_Handler + +.weak WWDG_IRQHandler +.thumb_set WWDG_IRQHandler,Default_Handler + +.weak PVD_IRQHandler +.thumb_set PVD_IRQHandler,Default_Handler + +.weak TAMPER_IRQHandler +.thumb_set TAMPER_IRQHandler,Default_Handler + +.weak RTC_IRQHandler +.thumb_set RTC_IRQHandler,Default_Handler + +.weak FLASH_IRQHandler +.thumb_set FLASH_IRQHandler,Default_Handler + +.weak RCC_IRQHandler +.thumb_set RCC_IRQHandler,Default_Handler + +.weak EXTI0_IRQHandler +.thumb_set EXTI0_IRQHandler,Default_Handler + +.weak EXTI1_IRQHandler +.thumb_set EXTI1_IRQHandler,Default_Handler + +.weak EXTI2_IRQHandler +.thumb_set EXTI2_IRQHandler,Default_Handler + +.weak EXTI3_IRQHandler +.thumb_set EXTI3_IRQHandler,Default_Handler + +.weak EXTI4_IRQHandler +.thumb_set EXTI4_IRQHandler,Default_Handler + +.weak DMA1_Channel1_IRQHandler +.thumb_set DMA1_Channel1_IRQHandler,Default_Handler + +.weak DMA1_Channel2_IRQHandler +.thumb_set DMA1_Channel2_IRQHandler,Default_Handler + +.weak DMA1_Channel3_IRQHandler +.thumb_set DMA1_Channel3_IRQHandler,Default_Handler + +.weak DMA1_Channel4_IRQHandler +.thumb_set DMA1_Channel4_IRQHandler,Default_Handler + +.weak DMA1_Channel5_IRQHandler +.thumb_set DMA1_Channel5_IRQHandler,Default_Handler + +.weak DMA1_Channel6_IRQHandler +.thumb_set DMA1_Channel6_IRQHandler,Default_Handler + +.weak DMA1_Channel7_IRQHandler +.thumb_set DMA1_Channel7_IRQHandler,Default_Handler + +.weak ADC1_2_IRQHandler +.thumb_set ADC1_2_IRQHandler,Default_Handler + +.weak USB_HP_CAN1_TX_IRQHandler +.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + +.weak USB_LP_CAN1_RX0_IRQHandler +.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + +.weak CAN1_RX1_IRQHandler +.thumb_set CAN1_RX1_IRQHandler,Default_Handler + +.weak CAN1_SCE_IRQHandler +.thumb_set CAN1_SCE_IRQHandler,Default_Handler + +.weak EXTI9_5_IRQHandler +.thumb_set EXTI9_5_IRQHandler,Default_Handler + +.weak TIM1_BRK_IRQHandler +.thumb_set TIM1_BRK_IRQHandler,Default_Handler + +.weak TIM1_UP_IRQHandler +.thumb_set TIM1_UP_IRQHandler,Default_Handler + +.weak TIM1_TRG_COM_IRQHandler +.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + +.weak TIM1_CC_IRQHandler +.thumb_set TIM1_CC_IRQHandler,Default_Handler + +.weak TIM2_IRQHandler +.thumb_set TIM2_IRQHandler,Default_Handler + +.weak TIM3_IRQHandler +.thumb_set TIM3_IRQHandler,Default_Handler + +.weak TIM4_IRQHandler +.thumb_set TIM4_IRQHandler,Default_Handler + +.weak I2C1_EV_IRQHandler +.thumb_set I2C1_EV_IRQHandler,Default_Handler + +.weak I2C1_ER_IRQHandler +.thumb_set I2C1_ER_IRQHandler,Default_Handler + +.weak I2C2_EV_IRQHandler +.thumb_set I2C2_EV_IRQHandler,Default_Handler + +.weak I2C2_ER_IRQHandler +.thumb_set I2C2_ER_IRQHandler,Default_Handler + +.weak SPI1_IRQHandler +.thumb_set SPI1_IRQHandler,Default_Handler + +.weak SPI2_IRQHandler +.thumb_set SPI2_IRQHandler,Default_Handler + +.weak USART1_IRQHandler +.thumb_set USART1_IRQHandler,Default_Handler + +.weak USART2_IRQHandler +.thumb_set USART2_IRQHandler,Default_Handler + +.weak USART3_IRQHandler +.thumb_set USART3_IRQHandler,Default_Handler + +.weak EXTI15_10_IRQHandler +.thumb_set EXTI15_10_IRQHandler,Default_Handler + +.weak RTCAlarm_IRQHandler +.thumb_set RTCAlarm_IRQHandler,Default_Handler + +.weak TIM8_BRK_IRQHandler +.thumb_set TIM8_BRK_IRQHandler,Default_Handler + +.weak TIM8_UP_IRQHandler +.thumb_set TIM8_UP_IRQHandler,Default_Handler + +.weak TIM8_TRG_COM_IRQHandler +.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + +.weak TIM8_CC_IRQHandler +.thumb_set TIM8_CC_IRQHandler,Default_Handler + +.weak RNG_IRQHandler +.thumb_set RNG_IRQHandler,Default_Handler + +.weak FSMC_IRQHandler +.thumb_set FSMC_IRQHandler,Default_Handler + +.weak SDIO_IRQHandler +.thumb_set SDIO_IRQHandler,Default_Handler + +.weak TIM5_IRQHandler +.thumb_set TIM5_IRQHandler,Default_Handler + +.weak SPI3_IRQHandler +.thumb_set SPI3_IRQHandler,Default_Handler + +.weak UART4_IRQHandler +.thumb_set UART4_IRQHandler,Default_Handler + +.weak UART5_IRQHandler +.thumb_set UART5_IRQHandler,Default_Handler + +.weak TIM6_IRQHandler +.thumb_set TIM6_IRQHandler,Default_Handler + +.weak TIM7_IRQHandler +.thumb_set TIM7_IRQHandler,Default_Handler + +.weak DMA2_Channel1_IRQHandler +.thumb_set DMA2_Channel1_IRQHandler,Default_Handler + +.weak DMA2_Channel2_IRQHandler +.thumb_set DMA2_Channel2_IRQHandler,Default_Handler + +.weak DMA2_Channel3_IRQHandler +.thumb_set DMA2_Channel3_IRQHandler,Default_Handler + +.weak DMA2_Channel4_IRQHandler +.thumb_set DMA2_Channel4_IRQHandler,Default_Handler + +.weak DMA2_Channel5_IRQHandler +.thumb_set DMA2_Channel5_IRQHandler,Default_Handler + +.weak ETH_IRQHandler +.thumb_set ETH_IRQHandler,Default_Handler + +.weak ETH_WKUP_IRQHandler +.thumb_set ETH_WKUP_IRQHandler,Default_Handler + +.weak CAN2_TX_IRQHandler +.thumb_set CAN2_TX_IRQHandler,Default_Handler + +.weak CAN2_RX0_IRQHandler +.thumb_set CAN2_RX0_IRQHandler,Default_Handler + +.weak CAN2_RX1_IRQHandler +.thumb_set CAN2_RX1_IRQHandler,Default_Handler + +.weak CAN2_SCE_IRQHandler +.thumb_set CAN2_SCE_IRQHandler,Default_Handler + +.weak OTG_FS_IRQHandler +.thumb_set OTG_FS_IRQHandler,Default_Handler + +.weak USBHSWakeup_IRQHandler +.thumb_set USBHSWakeup_IRQHandler,Default_Handler + +.weak USBHS_IRQHandler +.thumb_set USBHS_IRQHandler,Default_Handler + +.weak DVP_IRQHandler +.thumb_set DVP_IRQHandler,Default_Handler + +.weak UART6_IRQHandler +.thumb_set UART6_IRQHandler,Default_Handler + +.weak UART7_IRQHandler +.thumb_set UART7_IRQHandler,Default_Handler + +.weak UART8_IRQHandler +.thumb_set UART8_IRQHandler,Default_Handler + +.weak TIM9_BRK_IRQHandler +.thumb_set TIM9_BRK_IRQHandler,Default_Handler + +.weak TIM9_UP_IRQHandler +.thumb_set TIM9_UP_IRQHandler,Default_Handler + +.weak TIM9_TRG_COM_IRQHandler +.thumb_set TIM9_TRG_COM_IRQHandler,Default_Handler + +.weak TIM9_CC_IRQHandler +.thumb_set TIM9_CC_IRQHandler,Default_Handler + +.weak TIM10_BRK_IRQHandler +.thumb_set TIM10_BRK_IRQHandler,Default_Handler + +.weak TIM10_UP_IRQHandler +.thumb_set TIM10_UP_IRQHandler,Default_Handler + +.weak TIM10_TRG_COM_IRQHandler +.thumb_set TIM10_TRG_COM_IRQHandler,Default_Handler + +.weak TIM10_CC_IRQHandler +.thumb_set TIM10_CC_IRQHandler,Default_Handler + +.weak DMA2_Channel6_IRQHandler +.thumb_set DMA2_Channel6_IRQHandler,Default_Handler + +.weak DMA2_Channel7_IRQHandler +.thumb_set DMA2_Channel7_IRQHandler,Default_Handler + +.weak DMA2_Channel8_IRQHandler +.thumb_set DMA2_Channel8_IRQHandler,Default_Handler + +.weak DMA2_Channel9_IRQHandler +.thumb_set DMA2_Channel9_IRQHandler,Default_Handler + +.weak DMA2_Channel10_IRQHandler +.thumb_set DMA2_Channel10_IRQHandler,Default_Handler + +.weak DMA2_Channel11_IRQHandler +.thumb_set DMA2_Channel11_IRQHandler,Default_Handler diff --git a/hw/bsp/ch32f20x/system_ch32f20x.c b/hw/bsp/ch32f20x/system_ch32f20x.c new file mode 100644 index 000000000..0a59b9287 --- /dev/null +++ b/hw/bsp/ch32f20x/system_ch32f20x.c @@ -0,0 +1,1122 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : system_ch32f20x.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/08/08 +* Description : CH32F20x Device Peripheral Access Layer System Source File. +* For CH32F208 HSE = 32Mhz +* For others HSE = 8Mhz +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32f20x.h" + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +* If none of the define below is enabled, the HSI is used as System clock source. +*/ + +//#define SYSCLK_FREQ_HSE HSE_VALUE +//#define SYSCLK_FREQ_48MHz_HSE 48000000 +//#define SYSCLK_FREQ_56MHz_HSE 56000000 +//#define SYSCLK_FREQ_72MHz_HSE 72000000 +#define SYSCLK_FREQ_96MHz_HSE 96000000 +//#define SYSCLK_FREQ_120MHz_HSE 120000000 +//#define SYSCLK_FREQ_144MHz_HSE 144000000 +//#define SYSCLK_FREQ_HSI HSI_VALUE +//#define SYSCLK_FREQ_48MHz_HSI 48000000 +//#define SYSCLK_FREQ_56MHz_HSI 56000000 +//#define SYSCLK_FREQ_72MHz_HSI 72000000 +//#define SYSCLK_FREQ_96MHz_HSI 96000000 +//#define SYSCLK_FREQ_120MHz_HSI 120000000 +//#define SYSCLK_FREQ_144MHz_HSI 144000000 + + +/* Uncomment the following line if you need to relocate your vector Table in Internal SRAM */ +/* #define VECT_TAB_SRAM */ + +/* Vector Table base offset field This value must be a multiple of 0x200 */ +#define VECT_TAB_OFFSET 0x0 + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_120MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_144MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_120MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_144MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */ +#else +uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ + +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/* system_private_function_proto_types */ +static void SetSysClock( void ); + +#ifdef SYSCLK_FREQ_HSE +static void SetSysClockToHSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSE +static void SetSysClockTo48_HSE( void ); +#elif defined SYSCLK_FREQ_56MHz_HSE +static void SetSysClockTo56_HSE( void ); +#elif defined SYSCLK_FREQ_72MHz_HSE +static void SetSysClockTo72_HSE( void ); +#elif defined SYSCLK_FREQ_96MHz_HSE +static void SetSysClockTo96_HSE( void ); +#elif defined SYSCLK_FREQ_120MHz_HSE +static void SetSysClockTo120_HSE( void ); +#elif defined SYSCLK_FREQ_144MHz_HSE +static void SetSysClockTo144_HSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSI +static void SetSysClockTo48_HSI( void ); +#elif defined SYSCLK_FREQ_56MHz_HSI +static void SetSysClockTo56_HSI( void ); +#elif defined SYSCLK_FREQ_72MHz_HSI +static void SetSysClockTo72_HSI( void ); +#elif defined SYSCLK_FREQ_96MHz_HSI +static void SetSysClockTo96_HSI( void ); +#elif defined SYSCLK_FREQ_120MHz_HSI +static void SetSysClockTo120_HSI( void ); +#elif defined SYSCLK_FREQ_144MHz_HSI +static void SetSysClockTo144_HSI( void ); + +#endif + + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit( void ) +{ + RCC->CTLR |= ( uint32_t )0x00000001; + +#ifdef CH32F20x_D8C + RCC->CFGR0 &= ( uint32_t )0xF8FF0000; +#else + RCC->CFGR0 &= ( uint32_t )0xF0FF0000; +#endif + + RCC->CTLR &= ( uint32_t )0xFEF6FFFF; + RCC->CTLR &= ( uint32_t )0xFFFBFFFF; + RCC->CFGR0 &= ( uint32_t )0xFF80FFFF; +#ifdef CH32F20x_D8C + RCC->CTLR &= ( uint32_t )0xEBFFFFFF; + RCC->INTR = 0x00FF0000; + RCC->CFGR2 = 0x00000000; +#else + RCC->INTR = 0x009F0000; +#endif + + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate( void ) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + uint8_t Pll_6_5 = 0; + +#if defined (CH32F20x_D8C) + uint8_t Pll2mull = 0; + +#endif + + tmp = RCC->CFGR0 & RCC_SWS; + + switch( tmp ) + { + case 0x00: + SystemCoreClock = HSI_VALUE; + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllmull = RCC->CFGR0 & RCC_PLLMULL; + pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllmull = ( pllmull >> 18 ) + 2; + +#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W) + if( pllmull == 17 ) + { + pllmull = 18; + } +#else + if( pllmull == 2 ) + { + pllmull = 18; + } + if( pllmull == 15 ) + { + pllmull = 13; /* *6.5 */ + Pll_6_5 = 1; + } + if( pllmull == 16 ) + { + pllmull = 15; + } + if( pllmull == 17 ) + { + pllmull = 16; + } +#endif + + if( pllsource == 0x00 ) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE) SystemCoreClock = HSI_VALUE * pllmull; + else SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { +#if defined (CH32F20x_D8C) + if(RCC->CFGR2 & (1<<16)){ /* PLL2 */ + SystemCoreClock = HSE_VALUE/(((RCC->CFGR2 & 0xF0)>>4) + 1); /* PREDIV2 */ + + Pll2mull = (uint8_t)((RCC->CFGR2 & 0xF00)>>8); + + if(Pll2mull == 0) SystemCoreClock = (SystemCoreClock * 5)>>1; + else if(Pll2mull == 1) SystemCoreClock = (SystemCoreClock * 25)>>1; + else if(Pll2mull == 15) SystemCoreClock = SystemCoreClock * 20; + else SystemCoreClock = SystemCoreClock * (Pll2mull + 2); + + SystemCoreClock = SystemCoreClock/((RCC->CFGR2 & 0xF) + 1); /* PREDIV1 */ + } + else{/* HSE */ + SystemCoreClock = HSE_VALUE/((RCC->CFGR2 & 0xF) + 1); /* PREDIV1 */ + } + + SystemCoreClock = SystemCoreClock * pllmull; +#else + +#if defined (CH32F20x_D8W) + if((RCC->CFGR0 & (3<<22)) == (3<<22)) + { + SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; + } + else +#endif + if( ( RCC->CFGR0 & RCC_PLLXTPRE ) != ( uint32_t )RESET ) + { +#ifdef CH32F20x_D8W + SystemCoreClock = ( ( HSE_VALUE >> 2 ) >> 1 ) * pllmull; +#else + SystemCoreClock = ( HSE_VALUE >> 1 ) * pllmull; +#endif + } + else + { +#ifdef CH32F20x_D8W + SystemCoreClock = ( HSE_VALUE >> 2 ) * pllmull; +#else + SystemCoreClock = HSE_VALUE * pllmull; +#endif + + } +#endif + } + + if( Pll_6_5 == 1 ) SystemCoreClock = ( SystemCoreClock / 2 ); + + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = AHBPrescTable[( ( RCC->CFGR0 & RCC_HPRE ) >> 4 )]; + SystemCoreClock >>= tmp; +} + + + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock( void ) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo48_HSE(); +#elif defined SYSCLK_FREQ_56MHz_HSE + SetSysClockTo56_HSE(); +#elif defined SYSCLK_FREQ_72MHz_HSE + SetSysClockTo72_HSE(); +#elif defined SYSCLK_FREQ_96MHz_HSE + SetSysClockTo96_HSE(); +#elif defined SYSCLK_FREQ_120MHz_HSE + SetSysClockTo120_HSE(); +#elif defined SYSCLK_FREQ_144MHz_HSE + SetSysClockTo144_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo48_HSI(); +#elif defined SYSCLK_FREQ_56MHz_HSI + SetSysClockTo56_HSI(); +#elif defined SYSCLK_FREQ_72MHz_HSI + SetSysClockTo72_HSI(); +#elif defined SYSCLK_FREQ_96MHz_HSI + SetSysClockTo96_HSI(); +#elif defined SYSCLK_FREQ_120MHz_HSI + SetSysClockTo120_HSI(); +#elif defined SYSCLK_FREQ_144MHz_HSI + SetSysClockTo144_HSI(); + +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_HSE + +/********************************************************************* + * @fn SetSysClockToHSE + * + * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockToHSE( void ) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ( ( uint32_t )RCC_HSEON ); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } + while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) ); + + if( ( RCC->CTLR & RCC_HSERDY ) != RESET ) + { + HSEStatus = ( uint32_t )0x01; + } + else + { + HSEStatus = ( uint32_t )0x00; + } + + if( HSEStatus == ( uint32_t )0x01 ) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV1; + + /* Select HSE as system clock source + * CH32F20x_D6 (HSE=8Mhz) + * CH32F20x_D8 (HSE=8Mhz) + * CH32F20x_D8W (HSE=32Mhz) + */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) ); + RCC->CFGR0 |= ( uint32_t )RCC_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x04 ) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo48_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSE( void ) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ( ( uint32_t )RCC_HSEON ); + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } + while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) ); + + if( ( RCC->CTLR & RCC_HSERDY ) != RESET ) + { + HSEStatus = ( uint32_t )0x01; + } + else + { + HSEStatus = ( uint32_t )0x00; + } + + if( HSEStatus == ( uint32_t )0x01 ) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2; + + /* CH32F20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8Mhz) + * CH32F20x_D8-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8Mhz) + * CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz(HSE=32Mhz) + */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) ); + +#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W) + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6 ); +#else + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN ); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while( ( RCC->CTLR & RCC_PLLRDY ) == 0 ) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) ); + RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 ) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo56_HSE + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSE( void ) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ( ( uint32_t )RCC_HSEON ); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } + while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) ); + + if( ( RCC->CTLR & RCC_HSERDY ) != RESET ) + { + HSEStatus = ( uint32_t )0x01; + } + else + { + HSEStatus = ( uint32_t )0x00; + } + + if( HSEStatus == ( uint32_t )0x01 ) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2; + + /* CH32F20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8Mhz) + * CH32F20x_D8-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8Mhz) + * CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz(HSE=32Mhz) + */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) ); + +#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W) + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7 ); +#else + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN ); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while( ( RCC->CTLR & RCC_PLLRDY ) == 0 ) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) ); + RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 ) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo72_HSE + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSE( void ) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ( ( uint32_t )RCC_HSEON ); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } + while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) ); + + if( ( RCC->CTLR & RCC_HSERDY ) != RESET ) + { + HSEStatus = ( uint32_t )0x01; + } + else + { + HSEStatus = ( uint32_t )0x00; + } + + if( HSEStatus == ( uint32_t )0x01 ) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2; + + /* CH32F20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8Mhz) + * CH32F20x_D8-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8Mhz) + * CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz(HSE=32Mhz) + */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL ) ); + +#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W) + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9 ); +#else + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN ); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while( ( RCC->CTLR & RCC_PLLRDY ) == 0 ) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) ); + RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 ) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo96_HSE + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSE( void ) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ( ( uint32_t )RCC_HSEON ); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } + while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) ); + + if( ( RCC->CTLR & RCC_HSERDY ) != RESET ) + { + HSEStatus = ( uint32_t )0x01; + } + else + { + HSEStatus = ( uint32_t )0x00; + } + + if( HSEStatus == ( uint32_t )0x01 ) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2; + + /* CH32F20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8Mhz) + * CH32F20x_D8-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8Mhz) + * CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz(HSE=32Mhz) + */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL ) ); + +#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W) + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12 ); +#else + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN ); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while( ( RCC->CTLR & RCC_PLLRDY ) == 0 ) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) ); + RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 ) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo120_HSE + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if defined (CH32F20x_D8W) + RCC->CFGR0 |= (uint32_t)(3<<22); + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2; +#else + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; +#endif + + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32F20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8Mhz) + * CH32F20x_D8-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8Mhz) + * CH32F20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz(HSE=32Mhz) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W) + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + + +#elif defined SYSCLK_FREQ_144MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo144_HSE + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSE( void ) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ( ( uint32_t )RCC_HSEON ); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } + while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) ); + + if( ( RCC->CTLR & RCC_HSERDY ) != RESET ) + { + HSEStatus = ( uint32_t )0x01; + } + else + { + HSEStatus = ( uint32_t )0x00; + } + + if( HSEStatus == ( uint32_t )0x01 ) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2; + + /* CH32F20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8Mhz) + * CH32F20x_D8-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8Mhz) + * CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz(HSE=32Mhz) + */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL ) ); + +#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W) + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18 ); +#else + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN ); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while( ( RCC->CTLR & RCC_PLLRDY ) == 0 ) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) ); + RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 ) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo48_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSI( void ) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) ); + +#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W) + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6 ); +#else + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6_EXTEN ); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while( ( RCC->CTLR & RCC_PLLRDY ) == 0 ) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) ); + RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 ) + { + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo56_HSI + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSI( void ) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) ); + +#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W) + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7 ); +#else + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7_EXTEN ); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while( ( RCC->CTLR & RCC_PLLRDY ) == 0 ) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) ); + RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 ) + { + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo72_HSI + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSI( void ) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) ); + +#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W) + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9 ); +#else + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9_EXTEN ); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while( ( RCC->CTLR & RCC_PLLRDY ) == 0 ) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) ); + RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 ) + { + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo96_HSI + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSI( void ) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) ); + +#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W) + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12 ); +#else + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12_EXTEN ); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while( ( RCC->CTLR & RCC_PLLRDY ) == 0 ) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) ); + RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 ) + { + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo120_HSI + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W) + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15 ); +#else + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15_EXTEN ); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_144MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo144_HSI + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSI( void ) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) ); + +#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W) + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18 ); +#else + RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18_EXTEN ); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while( ( RCC->CTLR & RCC_PLLRDY ) == 0 ) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) ); + RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 ) + { + } +} + + +#endif diff --git a/hw/bsp/ch32f20x/system_ch32f20x.h b/hw/bsp/ch32f20x/system_ch32f20x.h new file mode 100644 index 000000000..734c80a5a --- /dev/null +++ b/hw/bsp/ch32f20x/system_ch32f20x.h @@ -0,0 +1,28 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : system_ch32f20x.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/08/08 +* Description : CH32F20x Device Peripheral Access Layer System Header File. +*******************************************************************************/ +#ifndef __SYSTEM_CH32F20x_H +#define __SYSTEM_CH32F20x_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32F20x_SYSTEM_H */ + + + diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk index 4b06cf429..45f0317ee 100644 --- a/hw/bsp/ch32v307/family.mk +++ b/hw/bsp/ch32v307/family.mk @@ -29,7 +29,7 @@ CFLAGS += \ -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED SRC_C += \ - src/portable/wch/ch32v307/dcd_usbhs.c \ + src/portable/wch/dcd_ch32_usbhs.c \ $(CH32V307_SDK_SRC)/Core/core_riscv.c \ $(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_gpio.c \ $(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_misc.c \ diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 8807ff8aa..a72976ae9 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -383,6 +383,10 @@ #elif TU_CHECK_MCU(OPT_MCU_CH32V307) #define TUP_DCD_ENDPOINT_MAX 16 #define TUP_RHPORT_HIGHSPEED 1 + +#elif TU_CHECK_MCU(OPT_MCU_CH32F20X) + #define TUP_DCD_ENDPOINT_MAX 16 + #define TUP_RHPORT_HIGHSPEED 1 #endif diff --git a/src/portable/wch/ch32_usbhs_reg.h b/src/portable/wch/ch32_usbhs_reg.h new file mode 100644 index 000000000..9b956231f --- /dev/null +++ b/src/portable/wch/ch32_usbhs_reg.h @@ -0,0 +1,349 @@ +#ifndef _USB_CH32_USBHS_REG_H +#define _USB_CH32_USBHS_REG_H + +#if (CFG_TUSB_MCU == OPT_MCU_CH32V307) +#include +#elif (CFG_TUSB_MCU == OPT_MCU_CH32F20X) +#include +#endif + +/******************* GLOBAL ******************/ + +// USB CONTROL +#define USBHS_CONTROL_OFFSET 0x00 +#define USBHS_DMA_EN (1 << 0) +#define USBHS_ALL_CLR (1 << 1) +#define USBHS_FORCE_RST (1 << 2) +#define USBHS_INT_BUSY_EN (1 << 3) +#define USBHS_DEV_PU_EN (1 << 4) +#define USBHS_SPEED_MASK (3 << 5) +#define USBHS_FULL_SPEED (0 << 5) +#define USBHS_HIGH_SPEED (1 << 5) +#define USBHS_LOW_SPEED (2 << 5) +#define USBHS_HOST_MODE (1 << 7) + +// USB_INT_EN +#define USBHS_INT_EN_OFFSET 0x02 +#define USBHS_BUS_RST_EN (1 << 0) +#define USBHS_DETECT_EN (1 << 0) +#define USBHS_TRANSFER_EN (1 << 1) +#define USBHS_SUSPEND_EN (1 << 2) +#define USBHS_SOF_ACT_EN (1 << 3) +#define USBHS_FIFO_OV_EN (1 << 4) +#define USBHS_SETUP_ACT_EN (1 << 5) +#define USBHS_ISO_ACT_EN (1 << 6) +#define USBHS_DEV_NAK_EN (1 << 7) + +// USB DEV AD +#define USBHS_DEV_AD_OFFSET 0x03 +// USB FRAME_NO +#define USBHS_FRAME_NO_OFFSET 0x04 +// USB SUSPEND +#define USBHS_SUSPEND_OFFSET 0x06 +#define USBHS_DEV_REMOTE_WAKEUP (1 << 2) +#define USBHS_LINESTATE_MASK (2 << 4) /* Read Only */ + +// RESERVED0 + +// USB SPEED TYPE +#define USBHS_SPEED_TYPE_OFFSET 0x08 +#define USBSPEED_MASK (0x03) + +// USB_MIS_ST +#define USBHS_MIS_ST_OFFSET 0x09 +#define USBHS_SPLIT_CAN (1 << 0) +#define USBHS_ATTACH (1 << 1) +#define USBHS_SUSPEND (1 << 2) +#define USBHS_BUS_RESET (1 << 3) +#define USBHS_R_FIFO_RDY (1 << 4) +#define USBHS_SIE_FREE (1 << 5) +#define USBHS_SOF_ACT (1 << 6) +#define USBHS_SOF_PRES (1 << 7) + +// INT_FLAG +#define USBHS_INT_FLAG_OFFSET 0x0A +#define USBHS_BUS_RST_FLAG (1 << 0) +#define USBHS_DETECT_FLAG (1 << 0) +#define USBHS_TRANSFER_FLAG (1 << 1) +#define USBHS_SUSPEND_FLAG (1 << 2) +#define USBHS_HST_SOF_FLAG (1 << 3) +#define USBHS_FIFO_OV_FLAG (1 << 4) +#define USBHS_SETUP_FLAG (1 << 5) +#define USBHS_ISO_ACT_FLAG (1 << 6) + +// INT_ST +#define USBHS_INT_ST_OFFSET 0x0B +#define USBHS_DEV_UIS_IS_NAK (1 << 7) +#define USBHS_DEV_UIS_TOG_OK (1 << 6) +#define MASK_UIS_TOKEN (3 << 4) +#define MASK_UIS_ENDP (0x0F) +#define MASK_UIS_H_RES (0x0F) + +#define USBHS_TOGGLE_OK (0x40) +#define USBHS_HOST_RES (0x0f) + +//USB_RX_LEN +#define USBHS_RX_LEN_OFFSET 0x0C +/******************* DEVICE ******************/ + +//UEP_CONFIG +#define USBHS_UEP_CONFIG_OFFSET 0x10 +#define USBHS_EP0_T_EN (1 << 0) +#define USBHS_EP0_R_EN (1 << 16) + +#define USBHS_EP1_T_EN (1 << 1) +#define USBHS_EP1_R_EN (1 << 17) + +#define USBHS_EP2_T_EN (1 << 2) +#define USBHS_EP2_R_EN (1 << 18) + +#define USBHS_EP3_T_EN (1 << 3) +#define USBHS_EP3_R_EN (1 << 19) + +#define USBHS_EP4_T_EN (1 << 4) +#define USBHS_EP4_R_EN (1 << 20) + +#define USBHS_EP5_T_EN (1 << 5) +#define USBHS_EP5_R_EN (1 << 21) + +#define USBHS_EP6_T_EN (1 << 6) +#define USBHS_EP6_R_EN (1 << 22) + +#define USBHS_EP7_T_EN (1 << 7) +#define USBHS_EP7_R_EN (1 << 23) + +#define USBHS_EP8_T_EN (1 << 8) +#define USBHS_EP8_R_EN (1 << 24) + +#define USBHS_EP9_T_EN (1 << 9) +#define USBHS_EP9_R_EN (1 << 25) + +#define USBHS_EP10_T_EN (1 << 10) +#define USBHS_EP10_R_EN (1 << 26) + +#define USBHS_EP11_T_EN (1 << 11) +#define USBHS_EP11_R_EN (1 << 27) + +#define USBHS_EP12_T_EN (1 << 12) +#define USBHS_EP12_R_EN (1 << 28) + +#define USBHS_EP13_T_EN (1 << 13) +#define USBHS_EP13_R_EN (1 << 29) + +#define USBHS_EP14_T_EN (1 << 14) +#define USBHS_EP14_R_EN (1 << 30) + +#define USBHS_EP15_T_EN (1 << 15) +#define USBHS_EP15_R_EN (1 << 31) + +//UEP_TYPE +#define USBHS_UEP_TYPE_OFFSET 0x14 +#define USBHS_EP0_T_TYP (1 << 0) +#define USBHS_EP0_R_TYP (1 << 16) + +#define USBHS_EP1_T_TYP (1 << 1) +#define USBHS_EP1_R_TYP (1 << 17) + +#define USBHS_EP2_T_TYP (1 << 2) +#define USBHS_EP2_R_TYP (1 << 18) + +#define USBHS_EP3_T_TYP (1 << 3) +#define USBHS_EP3_R_TYP (1 << 19) + +#define USBHS_EP4_T_TYP (1 << 4) +#define USBHS_EP4_R_TYP (1 << 20) + +#define USBHS_EP5_T_TYP (1 << 5) +#define USBHS_EP5_R_TYP (1 << 21) + +#define USBHS_EP6_T_TYP (1 << 6) +#define USBHS_EP6_R_TYP (1 << 22) + +#define USBHS_EP7_T_TYP (1 << 7) +#define USBHS_EP7_R_TYP (1 << 23) + +#define USBHS_EP8_T_TYP (1 << 8) +#define USBHS_EP8_R_TYP (1 << 24) + +#define USBHS_EP9_T_TYP (1 << 8) +#define USBHS_EP9_R_TYP (1 << 25) + +#define USBHS_EP10_T_TYP (1 << 10) +#define USBHS_EP10_R_TYP (1 << 26) + +#define USBHS_EP11_T_TYP (1 << 11) +#define USBHS_EP11_R_TYP (1 << 27) + +#define USBHS_EP12_T_TYP (1 << 12) +#define USBHS_EP12_R_TYP (1 << 28) + +#define USBHS_EP13_T_TYP (1 << 13) +#define USBHS_EP13_R_TYP (1 << 29) + +#define USBHS_EP14_T_TYP (1 << 14) +#define USBHS_EP14_R_TYP (1 << 30) + +#define USBHS_EP15_T_TYP (1 << 15) +#define USBHS_EP15_R_TYP (1 << 31) + +/* BUF_MOD UEP1~15 */ +#define USBHS_BUF_MOD_OFFSET 0x18 +#define USBHS_EP0_BUF_MOD (1 << 0) +#define USBHS_EP0_ISO_BUF_MOD (1 << 16) + +#define USBHS_EP1_BUF_MOD (1 << 1) +#define USBHS_EP1_ISO_BUF_MOD (1 << 17) + +#define USBHS_EP2_BUF_MOD (1 << 2) +#define USBHS_EP2_ISO_BUF_MOD (1 << 18) + +#define USBHS_EP3_BUF_MOD (1 << 3) +#define USBHS_EP3_ISO_BUF_MOD (1 << 19) + +#define USBHS_EP4_BUF_MOD (1 << 4) +#define USBHS_EP4_ISO_BUF_MOD (1 << 20) + +#define USBHS_EP5_BUF_MOD (1 << 5) +#define USBHS_EP5_ISO_BUF_MOD (1 << 21) + +#define USBHS_EP6_BUF_MOD (1 << 6) +#define USBHS_EP6_ISO_BUF_MOD (1 << 22) + +#define USBHS_EP7_BUF_MOD (1 << 7) +#define USBHS_EP7_ISO_BUF_MOD (1 << 23) + +#define USBHS_EP8_BUF_MOD (1 << 8) +#define USBHS_EP8_ISO_BUF_MOD (1 << 24) + +#define USBHS_EP9_BUF_MOD (1 << 9) +#define USBHS_EP9_ISO_BUF_MOD (1 << 25) + +#define USBHS_EP10_BUF_MOD (1 << 10) +#define USBHS_EP10_ISO_BUF_MOD (1 << 26) + +#define USBHS_EP11_BUF_MOD (1 << 11) +#define USBHS_EP11_ISO_BUF_MOD (1 << 27) + +#define USBHS_EP12_BUF_MOD (1 << 12) +#define USBHS_EP12_ISO_BUF_MOD (1 << 28) + +#define USBHS_EP13_BUF_MOD (1 << 13) +#define USBHS_EP13_ISO_BUF_MOD (1 << 29) + +#define USBHS_EP14_BUF_MOD (1 << 14) +#define USBHS_EP14_ISO_BUF_MOD (1 << 30) + +#define USBHS_EP15_BUF_MOD (1 << 15) +#define USBHS_EP15_ISO_BUF_MOD (1 << 31) +//USBHS_EPn_T_EN USBHS_EPn_R_EN USBHS_EPn_BUF_MOD Description: Arrange from low to high with UEPn_DMA as the starting address +// 0 0 x The endpoint is disabled and the UEPn_*_DMA buffers are not used. +// 1 0 0 The first address of the receive (OUT) buffer is UEPn_RX_DMA +// 1 0 1 RB_UEPn_RX_TOG[0]=0, use buffer UEPn_RX_DMA RB_UEPn_RX_TOG[0]=1, use buffer UEPn_TX_DMA +// 0 1 0 The first address of the transmit (IN) buffer is UEPn_TX_DMA. +// 0 1 1 RB_UEPn_TX_TOG[0]=0, use buffer UEPn_TX_DMA RB_UEPn_TX_TOG[0]=1, use buffer UEPn_RX_DMA + +/* USB0_DMA */ +#define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address + +/* USBX_RX_DMA */ +#define USBHS_UEPx_RX_DMA_OFFSET(n) (0x1C + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_TX_DMA_OFFSET(n) (0x58 + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_MAX_LEN_OFFSET(n) (0x98 + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_T_LEN_OFFSET(n) (0xD8 + 4 * (n)) // endpoint x DMA buffer address +#define USBHS_UEPx_TX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 2) // endpoint x DMA buffer address +#define USBHS_UEPx_RX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 3) // endpoint x DMA buffer address + +// UEPn_T_LEN +#define USBHS_EP_T_LEN_MASK (0x7FF) + +//UEPn_TX_CTRL +#define USBHS_EP_T_RES_MASK (3 << 0) +#define USBHS_EP_T_RES_ACK (0 << 0) +#define USBHS_EP_T_RES_NYET (1 << 0) +#define USBHS_EP_T_RES_NAK (2 << 0) +#define USBHS_EP_T_RES_STALL (3 << 0) + +#define USBHS_EP_T_TOG_MASK (3 << 3) +#define USBHS_EP_T_TOG_0 (0 << 3) +#define USBHS_EP_T_TOG_1 (1 << 3) +#define USBHS_EP_T_TOG_2 (2 << 3) +#define USBHS_EP_T_TOG_M (3 << 3) + +#define USBHS_EP_T_AUTOTOG (1 << 5) + +//UEPn_RX_CTRL +#define USBHS_EP_R_RES_MASK (3 << 0) +#define USBHS_EP_R_RES_ACK (0 << 0) +#define USBHS_EP_R_RES_NYET (1 << 0) +#define USBHS_EP_R_RES_NAK (2 << 0) +#define USBHS_EP_R_RES_STALL (3 << 0) + +#define USBHS_EP_R_TOG_MASK (3 << 3) +#define USBHS_EP_R_TOG_0 (0 << 3) +#define USBHS_EP_R_TOG_1 (1 << 3) +#define USBHS_EP_R_TOG_2 (2 << 3) +#define USBHS_EP_R_TOG_M (3 << 3) + +#define USBHS_EP_R_AUTOTOG (1 << 5) + +#define USBHS_TOG_MATCH (1 << 6) + +/******************* HOST ******************/ +// USB HOST_CTRL +#define USBHS_SEND_BUS_RESET (1 << 0) +#define USBHS_SEND_BUS_SUSPEND (1 << 1) +#define USBHS_SEND_BUS_RESUME (1 << 2) +#define USBHS_REMOTE_WAKE (1 << 3) +#define USBHS_PHY_SUSPENDM (1 << 4) +#define USBHS_UH_SOFT_FREE (1 << 6) +#define USBHS_SEND_SOF_EN (1 << 7) + +//UH_CONFIG +#define USBHS_HOST_TX_EN (1 << 3) +#define USBHS_HOST_RX_EN (1 << 18) + +// HOST_EP_TYPE +#define USBHS_ENDP_TX_ISO (1 << 3) +#define USBHS_ENDP_RX_ISO (1 << (16 + 2)) + +// R32_UH_EP_PID +#define USBHS_HOST_MASK_TOKEN (0x0f) +#define USBHS_HOST_MASK_ENDP (0x0f << 4) + +//R8_UH_RX_CTRL +#define USBHS_EP_R_RES_MASK (3 << 0) +#define USBHS_EP_R_RES_ACK (0 << 0) +#define USBHS_EP_R_RES_NYET (1 << 0) +#define USBHS_EP_R_RES_NAK (2 << 0) +#define USBHS_EP_R_RES_STALL (3 << 0) + +#define USBHS_UH_R_RES_NO (1 << 2) +#define USBHS_UH_R_TOG_1 (1 << 3) +#define USBHS_UH_R_TOG_2 (2 << 3) +#define USBHS_UH_R_TOG_3 (3 << 3) +#define USBHS_UH_R_TOG_AUTO (1 << 5) +#define USBHS_UH_R_DATA_NO (1 << 6) +//R8_UH_TX_CTRL +#define USBHS_UH_T_RES_MASK (3 << 0) +#define USBHS_UH_T_RES_ACK (0 << 0) +#define USBHS_UH_T_RES_NYET (1 << 0) +#define USBHS_UH_T_RES_NAK (2 << 0) +#define USBHS_UH_T_RES_STALL (3 << 0) + +#define USBHS_UH_T_RES_NO (1 << 2) +#define USBHS_UH_T_TOG_1 (1 << 3) +#define USBHS_UH_T_TOG_2 (2 << 3) +#define USBHS_UH_T_TOG_3 (3 << 3) +#define USBHS_UH_T_TOG_AUTO (1 << 5) +#define USBHS_UH_T_DATA_NO (1 << 6) + +// 00: OUT, 01:SOF, 10:IN, 11:SETUP +#define PID_OUT 0 +#define PID_SOF 1 +#define PID_IN 2 +#define PID_SETUP 3 + +#endif diff --git a/src/portable/wch/ch32v307/ch32_usbhs_reg.h b/src/portable/wch/ch32v307/ch32_usbhs_reg.h deleted file mode 100644 index 5a2c1fbc9..000000000 --- a/src/portable/wch/ch32v307/ch32_usbhs_reg.h +++ /dev/null @@ -1,345 +0,0 @@ -#ifndef _USB_CH32_USBHS_REG_H -#define _USB_CH32_USBHS_REG_H - -#include - -/******************* GLOBAL ******************/ - -// USB CONTROL -#define USBHS_CONTROL_OFFSET 0x00 -#define USBHS_DMA_EN (1 << 0) -#define USBHS_ALL_CLR (1 << 1) -#define USBHS_FORCE_RST (1 << 2) -#define USBHS_INT_BUSY_EN (1 << 3) -#define USBHS_DEV_PU_EN (1 << 4) -#define USBHS_SPEED_MASK (3 << 5) -#define USBHS_FULL_SPEED (0 << 5) -#define USBHS_HIGH_SPEED (1 << 5) -#define USBHS_LOW_SPEED (2 << 5) -#define USBHS_HOST_MODE (1 << 7) - -// USB_INT_EN -#define USBHS_INT_EN_OFFSET 0x02 -#define USBHS_BUS_RST_EN (1 << 0) -#define USBHS_DETECT_EN (1 << 0) -#define USBHS_TRANSFER_EN (1 << 1) -#define USBHS_SUSPEND_EN (1 << 2) -#define USBHS_SOF_ACT_EN (1 << 3) -#define USBHS_FIFO_OV_EN (1 << 4) -#define USBHS_SETUP_ACT_EN (1 << 5) -#define USBHS_ISO_ACT_EN (1 << 6) -#define USBHS_DEV_NAK_EN (1 << 7) - -// USB DEV AD -#define USBHS_DEV_AD_OFFSET 0x03 -// USB FRAME_NO -#define USBHS_FRAME_NO_OFFSET 0x04 -// USB SUSPEND -#define USBHS_SUSPEND_OFFSET 0x06 -#define USBHS_DEV_REMOTE_WAKEUP (1 << 2) -#define USBHS_LINESTATE_MASK (2 << 4) /* Read Only */ - -// RESERVED0 - -// USB SPEED TYPE -#define USBHS_SPEED_TYPE_OFFSET 0x08 -#define USBSPEED_MASK (0x03) - -// USB_MIS_ST -#define USBHS_MIS_ST_OFFSET 0x09 -#define USBHS_SPLIT_CAN (1 << 0) -#define USBHS_ATTACH (1 << 1) -#define USBHS_SUSPEND (1 << 2) -#define USBHS_BUS_RESET (1 << 3) -#define USBHS_R_FIFO_RDY (1 << 4) -#define USBHS_SIE_FREE (1 << 5) -#define USBHS_SOF_ACT (1 << 6) -#define USBHS_SOF_PRES (1 << 7) - -// INT_FLAG -#define USBHS_INT_FLAG_OFFSET 0x0A -#define USBHS_BUS_RST_FLAG (1 << 0) -#define USBHS_DETECT_FLAG (1 << 0) -#define USBHS_TRANSFER_FLAG (1 << 1) -#define USBHS_SUSPEND_FLAG (1 << 2) -#define USBHS_HST_SOF_FLAG (1 << 3) -#define USBHS_FIFO_OV_FLAG (1 << 4) -#define USBHS_SETUP_FLAG (1 << 5) -#define USBHS_ISO_ACT_FLAG (1 << 6) - -// INT_ST -#define USBHS_INT_ST_OFFSET 0x0B -#define USBHS_DEV_UIS_IS_NAK (1 << 7) -#define USBHS_DEV_UIS_TOG_OK (1 << 6) -#define MASK_UIS_TOKEN (3 << 4) -#define MASK_UIS_ENDP (0x0F) -#define MASK_UIS_H_RES (0x0F) - -#define USBHS_TOGGLE_OK (0x40) -#define USBHS_HOST_RES (0x0f) - -//USB_RX_LEN -#define USBHS_RX_LEN_OFFSET 0x0C -/******************* DEVICE ******************/ - -//UEP_CONFIG -#define USBHS_UEP_CONFIG_OFFSET 0x10 -#define USBHS_EP0_T_EN (1 << 0) -#define USBHS_EP0_R_EN (1 << 16) - -#define USBHS_EP1_T_EN (1 << 1) -#define USBHS_EP1_R_EN (1 << 17) - -#define USBHS_EP2_T_EN (1 << 2) -#define USBHS_EP2_R_EN (1 << 18) - -#define USBHS_EP3_T_EN (1 << 3) -#define USBHS_EP3_R_EN (1 << 19) - -#define USBHS_EP4_T_EN (1 << 4) -#define USBHS_EP4_R_EN (1 << 20) - -#define USBHS_EP5_T_EN (1 << 5) -#define USBHS_EP5_R_EN (1 << 21) - -#define USBHS_EP6_T_EN (1 << 6) -#define USBHS_EP6_R_EN (1 << 22) - -#define USBHS_EP7_T_EN (1 << 7) -#define USBHS_EP7_R_EN (1 << 23) - -#define USBHS_EP8_T_EN (1 << 8) -#define USBHS_EP8_R_EN (1 << 24) - -#define USBHS_EP9_T_EN (1 << 9) -#define USBHS_EP9_R_EN (1 << 25) - -#define USBHS_EP10_T_EN (1 << 10) -#define USBHS_EP10_R_EN (1 << 26) - -#define USBHS_EP11_T_EN (1 << 11) -#define USBHS_EP11_R_EN (1 << 27) - -#define USBHS_EP12_T_EN (1 << 12) -#define USBHS_EP12_R_EN (1 << 28) - -#define USBHS_EP13_T_EN (1 << 13) -#define USBHS_EP13_R_EN (1 << 29) - -#define USBHS_EP14_T_EN (1 << 14) -#define USBHS_EP14_R_EN (1 << 30) - -#define USBHS_EP15_T_EN (1 << 15) -#define USBHS_EP15_R_EN (1 << 31) - -//UEP_TYPE -#define USBHS_UEP_TYPE_OFFSET 0x14 -#define USBHS_EP0_T_TYP (1 << 0) -#define USBHS_EP0_R_TYP (1 << 16) - -#define USBHS_EP1_T_TYP (1 << 1) -#define USBHS_EP1_R_TYP (1 << 17) - -#define USBHS_EP2_T_TYP (1 << 2) -#define USBHS_EP2_R_TYP (1 << 18) - -#define USBHS_EP3_T_TYP (1 << 3) -#define USBHS_EP3_R_TYP (1 << 19) - -#define USBHS_EP4_T_TYP (1 << 4) -#define USBHS_EP4_R_TYP (1 << 20) - -#define USBHS_EP5_T_TYP (1 << 5) -#define USBHS_EP5_R_TYP (1 << 21) - -#define USBHS_EP6_T_TYP (1 << 6) -#define USBHS_EP6_R_TYP (1 << 22) - -#define USBHS_EP7_T_TYP (1 << 7) -#define USBHS_EP7_R_TYP (1 << 23) - -#define USBHS_EP8_T_TYP (1 << 8) -#define USBHS_EP8_R_TYP (1 << 24) - -#define USBHS_EP9_T_TYP (1 << 8) -#define USBHS_EP9_R_TYP (1 << 25) - -#define USBHS_EP10_T_TYP (1 << 10) -#define USBHS_EP10_R_TYP (1 << 26) - -#define USBHS_EP11_T_TYP (1 << 11) -#define USBHS_EP11_R_TYP (1 << 27) - -#define USBHS_EP12_T_TYP (1 << 12) -#define USBHS_EP12_R_TYP (1 << 28) - -#define USBHS_EP13_T_TYP (1 << 13) -#define USBHS_EP13_R_TYP (1 << 29) - -#define USBHS_EP14_T_TYP (1 << 14) -#define USBHS_EP14_R_TYP (1 << 30) - -#define USBHS_EP15_T_TYP (1 << 15) -#define USBHS_EP15_R_TYP (1 << 31) - -/* BUF_MOD UEP1~15 */ -#define USBHS_BUF_MOD_OFFSET 0x18 -#define USBHS_EP0_BUF_MOD (1 << 0) -#define USBHS_EP0_ISO_BUF_MOD (1 << 16) - -#define USBHS_EP1_BUF_MOD (1 << 1) -#define USBHS_EP1_ISO_BUF_MOD (1 << 17) - -#define USBHS_EP2_BUF_MOD (1 << 2) -#define USBHS_EP2_ISO_BUF_MOD (1 << 18) - -#define USBHS_EP3_BUF_MOD (1 << 3) -#define USBHS_EP3_ISO_BUF_MOD (1 << 19) - -#define USBHS_EP4_BUF_MOD (1 << 4) -#define USBHS_EP4_ISO_BUF_MOD (1 << 20) - -#define USBHS_EP5_BUF_MOD (1 << 5) -#define USBHS_EP5_ISO_BUF_MOD (1 << 21) - -#define USBHS_EP6_BUF_MOD (1 << 6) -#define USBHS_EP6_ISO_BUF_MOD (1 << 22) - -#define USBHS_EP7_BUF_MOD (1 << 7) -#define USBHS_EP7_ISO_BUF_MOD (1 << 23) - -#define USBHS_EP8_BUF_MOD (1 << 8) -#define USBHS_EP8_ISO_BUF_MOD (1 << 24) - -#define USBHS_EP9_BUF_MOD (1 << 9) -#define USBHS_EP9_ISO_BUF_MOD (1 << 25) - -#define USBHS_EP10_BUF_MOD (1 << 10) -#define USBHS_EP10_ISO_BUF_MOD (1 << 26) - -#define USBHS_EP11_BUF_MOD (1 << 11) -#define USBHS_EP11_ISO_BUF_MOD (1 << 27) - -#define USBHS_EP12_BUF_MOD (1 << 12) -#define USBHS_EP12_ISO_BUF_MOD (1 << 28) - -#define USBHS_EP13_BUF_MOD (1 << 13) -#define USBHS_EP13_ISO_BUF_MOD (1 << 29) - -#define USBHS_EP14_BUF_MOD (1 << 14) -#define USBHS_EP14_ISO_BUF_MOD (1 << 30) - -#define USBHS_EP15_BUF_MOD (1 << 15) -#define USBHS_EP15_ISO_BUF_MOD (1 << 31) -//USBHS_EPn_T_EN USBHS_EPn_R_EN USBHS_EPn_BUF_MOD Description: Arrange from low to high with UEPn_DMA as the starting address -// 0 0 x The endpoint is disabled and the UEPn_*_DMA buffers are not used. -// 1 0 0 The first address of the receive (OUT) buffer is UEPn_RX_DMA -// 1 0 1 RB_UEPn_RX_TOG[0]=0, use buffer UEPn_RX_DMA RB_UEPn_RX_TOG[0]=1, use buffer UEPn_TX_DMA -// 0 1 0 The first address of the transmit (IN) buffer is UEPn_TX_DMA. -// 0 1 1 RB_UEPn_TX_TOG[0]=0, use buffer UEPn_TX_DMA RB_UEPn_TX_TOG[0]=1, use buffer UEPn_RX_DMA - -/* USB0_DMA */ -#define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address - -/* USBX_RX_DMA */ -#define USBHS_UEPx_RX_DMA_OFFSET(n) (0x1C + 4 * (n)) // endpoint x DMA buffer address - -#define USBHS_UEPx_TX_DMA_OFFSET(n) (0x58 + 4 * (n)) // endpoint x DMA buffer address - -#define USBHS_UEPx_MAX_LEN_OFFSET(n) (0x98 + 4 * (n)) // endpoint x DMA buffer address - -#define USBHS_UEPx_T_LEN_OFFSET(n) (0xD8 + 4 * (n)) // endpoint x DMA buffer address -#define USBHS_UEPx_TX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 2) // endpoint x DMA buffer address -#define USBHS_UEPx_RX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 3) // endpoint x DMA buffer address - -// UEPn_T_LEN -#define USBHS_EP_T_LEN_MASK (0x7FF) - -//UEPn_TX_CTRL -#define USBHS_EP_T_RES_MASK (3 << 0) -#define USBHS_EP_T_RES_ACK (0 << 0) -#define USBHS_EP_T_RES_NYET (1 << 0) -#define USBHS_EP_T_RES_NAK (2 << 0) -#define USBHS_EP_T_RES_STALL (3 << 0) - -#define USBHS_EP_T_TOG_MASK (3 << 3) -#define USBHS_EP_T_TOG_0 (0 << 3) -#define USBHS_EP_T_TOG_1 (1 << 3) -#define USBHS_EP_T_TOG_2 (2 << 3) -#define USBHS_EP_T_TOG_M (3 << 3) - -#define USBHS_EP_T_AUTOTOG (1 << 5) - -//UEPn_RX_CTRL -#define USBHS_EP_R_RES_MASK (3 << 0) -#define USBHS_EP_R_RES_ACK (0 << 0) -#define USBHS_EP_R_RES_NYET (1 << 0) -#define USBHS_EP_R_RES_NAK (2 << 0) -#define USBHS_EP_R_RES_STALL (3 << 0) - -#define USBHS_EP_R_TOG_MASK (3 << 3) -#define USBHS_EP_R_TOG_0 (0 << 3) -#define USBHS_EP_R_TOG_1 (1 << 3) -#define USBHS_EP_R_TOG_2 (2 << 3) -#define USBHS_EP_R_TOG_M (3 << 3) - -#define USBHS_EP_R_AUTOTOG (1 << 5) - -#define USBHS_TOG_MATCH (1 << 6) - -/******************* HOST ******************/ -// USB HOST_CTRL -#define USBHS_SEND_BUS_RESET (1 << 0) -#define USBHS_SEND_BUS_SUSPEND (1 << 1) -#define USBHS_SEND_BUS_RESUME (1 << 2) -#define USBHS_REMOTE_WAKE (1 << 3) -#define USBHS_PHY_SUSPENDM (1 << 4) -#define USBHS_UH_SOFT_FREE (1 << 6) -#define USBHS_SEND_SOF_EN (1 << 7) - -//UH_CONFIG -#define USBHS_HOST_TX_EN (1 << 3) -#define USBHS_HOST_RX_EN (1 << 18) - -// HOST_EP_TYPE -#define USBHS_ENDP_TX_ISO (1 << 3) -#define USBHS_ENDP_RX_ISO (1 << (16 + 2)) - -// R32_UH_EP_PID -#define USBHS_HOST_MASK_TOKEN (0x0f) -#define USBHS_HOST_MASK_ENDP (0x0f << 4) - -//R8_UH_RX_CTRL -#define USBHS_EP_R_RES_MASK (3 << 0) -#define USBHS_EP_R_RES_ACK (0 << 0) -#define USBHS_EP_R_RES_NYET (1 << 0) -#define USBHS_EP_R_RES_NAK (2 << 0) -#define USBHS_EP_R_RES_STALL (3 << 0) - -#define USBHS_UH_R_RES_NO (1 << 2) -#define USBHS_UH_R_TOG_1 (1 << 3) -#define USBHS_UH_R_TOG_2 (2 << 3) -#define USBHS_UH_R_TOG_3 (3 << 3) -#define USBHS_UH_R_TOG_AUTO (1 << 5) -#define USBHS_UH_R_DATA_NO (1 << 6) -//R8_UH_TX_CTRL -#define USBHS_UH_T_RES_MASK (3 << 0) -#define USBHS_UH_T_RES_ACK (0 << 0) -#define USBHS_UH_T_RES_NYET (1 << 0) -#define USBHS_UH_T_RES_NAK (2 << 0) -#define USBHS_UH_T_RES_STALL (3 << 0) - -#define USBHS_UH_T_RES_NO (1 << 2) -#define USBHS_UH_T_TOG_1 (1 << 3) -#define USBHS_UH_T_TOG_2 (2 << 3) -#define USBHS_UH_T_TOG_3 (3 << 3) -#define USBHS_UH_T_TOG_AUTO (1 << 5) -#define USBHS_UH_T_DATA_NO (1 << 6) - -// 00: OUT, 01:SOF, 10:IN, 11:SETUP -#define PID_OUT 0 -#define PID_SOF 1 -#define PID_IN 2 -#define PID_SETUP 3 - -#endif diff --git a/src/portable/wch/ch32v307/dcd_usbhs.c b/src/portable/wch/ch32v307/dcd_usbhs.c deleted file mode 100644 index 3ad011cff..000000000 --- a/src/portable/wch/ch32v307/dcd_usbhs.c +++ /dev/null @@ -1,391 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2022 Greg Davill - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_CH32V307) -#include "device/dcd.h" - -#include "ch32_usbhs_reg.h" -#include "core_riscv.h" - -// Max number of bi-directional endpoints including EP0 -#define EP_MAX 16 - -typedef struct { - uint8_t *buffer; - // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API - uint16_t total_len; - uint16_t queued_len; - uint16_t max_size; - bool short_packet; -} xfer_ctl_t; - -#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] -static xfer_ctl_t xfer_status[EP_MAX][2]; - -#define EP_TX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_TX_LEN) + (ep)*2) -#define EP_TX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_TX_CTRL) + (ep)*4) -#define EP_RX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_RX_CTRL) + (ep)*4) -#define EP_RX_MAX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_MAX_LEN) + (ep)*2) - -#define EP_TX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_TX_DMA) + (ep - 1)) -#define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1)) - -/* Endpoint Buffer */ -TU_ATTR_ALIGNED(4) uint8_t EP0_DatabufHD[64]; // ep0(64) - -volatile uint8_t USBHS_Dev_Endp0_Tog = 0x01; - -void dcd_init(uint8_t rhport) { - (void)rhport; - - memset(&xfer_status, 0, sizeof(xfer_status)); - - USBHSD->HOST_CTRL = 0x00; - USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM; - - USBHSD->CONTROL = 0; - -#if TUD_OPT_HIGH_SPEED - USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED; -#else - #error OPT_MODE_FULL_SPEED not currently supported on CH32V307 - USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED; -#endif - - USBHSD->INT_EN = 0; - USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN | USBHS_SUSPEND_EN; - - /* ALL endpoint enable */ - USBHSD->ENDP_CONFIG = 0xffffffff; - - USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN; - USBHSD->ENDP_TYPE = 0x00; - USBHSD->BUF_MODE = 0x00; - - USBHSD->UEP0_MAX_LEN = 64; - - USBHSD->UEP0_DMA = (uint32_t)EP0_DatabufHD; - - USBHSD->UEP0_TX_LEN = 0; - USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_NAK; - USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; - - for (int ep = 1; ep < EP_MAX; ep++) { - EP_TX_LEN(ep) = 0; - EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK; - EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK; - - EP_RX_MAX_LEN(ep) = 512; - } - - USBHSD->DEV_AD = 0; - USBHSD->CONTROL |= USBHS_DEV_PU_EN; -} - -void dcd_int_enable(uint8_t rhport) { - (void)rhport; - - NVIC_EnableIRQ(USBHS_IRQn); -} - -void dcd_int_disable(uint8_t rhport) { - (void)rhport; - - NVIC_DisableIRQ(USBHS_IRQn); -} - -void dcd_edpt_close_all(uint8_t rhport) { - (void)rhport; -} - -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { - (void)dev_addr; - - // Response with zlp status - dcd_edpt_xfer(rhport, 0x80, NULL, 0); -} - -void dcd_remote_wakeup(uint8_t rhport) -{ - (void) rhport; -} - -void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) { - (void)rhport; - - if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && - request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && - request->bRequest == TUSB_REQ_SET_ADDRESS) { - USBHSD->DEV_AD = (uint8_t)request->wValue; - } - - EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK; - EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK; -} - -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) { - (void)rhport; - - uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); - - TU_ASSERT(epnum < EP_MAX); - - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->max_size = tu_edpt_packet_size(desc_edpt); - - if (epnum != 0) { - if (tu_edpt_dir(desc_edpt->bEndpointAddress) == TUSB_DIR_OUT) { - EP_RX_CTRL(epnum) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_ACK; - } else { - EP_TX_LEN(epnum) = 0; - EP_TX_CTRL(epnum) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0; - } - } - - return true; -} - -int usbd_ep_close(const uint8_t ep) { - (void)ep; - - return 0; -} -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - if (epnum == 0) { - if (dir == TUSB_DIR_OUT) { - USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_STALL; - } else { - USBHSD->UEP0_TX_LEN = 0; - USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_STALL; - } - } else { - if (dir == TUSB_DIR_OUT) { - EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_STALL; - - } else { - EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~USBHS_EP_T_RES_MASK) | USBHS_EP_T_RES_STALL; - } - } -} - -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - if (epnum == 0) { - if (dir == TUSB_DIR_OUT) { - USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; - } else { - } - } else { - if (dir == TUSB_DIR_OUT) { - EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~(USBHS_EP_R_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_ACK; - - } else { - EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_NAK; - } - } -} - -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void)rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->buffer = buffer; - // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API - xfer->total_len = total_bytes; - xfer->queued_len = 0; - xfer->short_packet = false; - - // uint16_t num_packets = (total_bytes / xfer->max_size); - uint16_t short_packet_size = total_bytes % (xfer->max_size + 1); - - // Zero-size packet is special case. - if (short_packet_size == 0 || (total_bytes == 0)) { - xfer->short_packet = true; - } - - if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) { - if (!total_bytes) { - xfer->short_packet = true; - if (epnum == 0) { - USBHSD->UEP0_TX_LEN = 0; - USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); - USBHS_Dev_Endp0_Tog ^= 1; - } else { - EP_TX_LEN(epnum) = 0; - EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK; - } - } else { - if (epnum == 0) { - xfer->queued_len += short_packet_size; - memcpy(&EP0_DatabufHD[0], buffer, short_packet_size); - - USBHSD->UEP0_TX_LEN = short_packet_size; - USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); - USBHS_Dev_Endp0_Tog ^= 1; - } else { - xfer->queued_len += short_packet_size; - - EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer; - USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum); - EP_TX_LEN(epnum) = short_packet_size; - EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK; - } - } - } else { /* TUSB_DIR_OUT */ - if (epnum == 0) { - uint32_t read_count = USBHSD->RX_LEN; - read_count = TU_MIN(read_count, total_bytes); - - if ((total_bytes == 8)) { - read_count = 8; - memcpy(buffer, &EP0_DatabufHD[0], 8); - } else { - memcpy(buffer, &EP0_DatabufHD[0], read_count); - } - } else { - EP_RX_DMA_ADDR(epnum) = (uint32_t)xfer->buffer; - USBHSD->ENDP_CONFIG |= (USBHS_EP0_R_EN << epnum); - } - - // usbd_ep_read(ep_addr, buffer, total_bytes, &ret_bytes); - } - return true; -} - - -static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size) { - // xfer->queued_len = xfer->total_len - remaining; - - uint16_t remaining = xfer->total_len - xfer->queued_len; - uint16_t to_recv_size; - - if (remaining <= xfer->max_size) { - // Avoid buffer overflow. - to_recv_size = (xfer_size > remaining) ? remaining : xfer_size; - } else { - // Room for full packet, choose recv_size based on what the microcontroller - // claims. - to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size; - } - - if (to_recv_size) { - } - - xfer->queued_len += xfer_size; - - // Per USB spec, a short OUT packet (including length 0) is always - // indicative of the end of a transfer (at least for ctl, bulk, int). - xfer->short_packet = (xfer_size < xfer->max_size); -} - -void dcd_int_handler(uint8_t rhport) { - (void)rhport; - - uint32_t end_num, rx_token; - uint8_t intflag = 0; - - intflag = USBHSD->INT_FG; - - if (intflag & USBHS_TRANSFER_FLAG) { - - end_num = (USBHSD->INT_ST) & MASK_UIS_ENDP; - rx_token = (((USBHSD->INT_ST) & MASK_UIS_TOKEN) >> 4) & 0x03; - - uint8_t endp = end_num | (rx_token == PID_IN ? TUSB_DIR_IN_MASK : 0); - - xfer_ctl_t *xfer = XFER_CTL_BASE(end_num, tu_edpt_dir(endp)); - - if (rx_token == PID_OUT) { - uint16_t rx_len = USBHSD->RX_LEN; - - receive_packet(xfer, rx_len); - - if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { - xfer->short_packet = false; - - dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true); - } - - if (end_num == 0) { - USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0; - } - - } else if (rx_token == PID_IN) { - if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { - xfer->short_packet = false; - xfer->total_len = 0; - dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true); - - EP_TX_CTRL(end_num) = (EP_TX_CTRL(end_num) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_NAK; - - if (end_num == 0) { - } - } else { - dcd_edpt_xfer(0, endp, xfer->buffer + xfer->queued_len, xfer->total_len - xfer->queued_len); - } - } - - USBHSD->INT_FG = USBHS_TRANSFER_FLAG; /* Clear flag */ - } else if (intflag & USBHS_SETUP_FLAG) { - USBHS_Dev_Endp0_Tog = 1; - dcd_event_setup_received(0, EP0_DatabufHD, true); - - USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */ - } else if (intflag & USBHS_DETECT_FLAG) { - USBHS_Dev_Endp0_Tog = 1; - - xfer_status[0][TUSB_DIR_OUT].max_size = 64; - xfer_status[0][TUSB_DIR_IN].max_size = 64; - - dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true); - - USBHSD->DEV_AD = 0; - USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0; - - USBHSD->INT_FG = USBHS_DETECT_FLAG; /* Clear flag */ - } else if (intflag & USBHS_SUSPEND_FLAG) { - dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SUSPEND }; - dcd_event_handler(&event, true); - - USBHSD->INT_FG = USBHS_SUSPEND_FLAG; /* Clear flag */ - } -} - -#endif diff --git a/src/portable/wch/dcd_ch32_usbhs.c b/src/portable/wch/dcd_ch32_usbhs.c new file mode 100644 index 000000000..1f1c0b876 --- /dev/null +++ b/src/portable/wch/dcd_ch32_usbhs.c @@ -0,0 +1,391 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2022 Greg Davill + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUD_ENABLED && ((CFG_TUSB_MCU == OPT_MCU_CH32V307) || (CFG_TUSB_MCU == OPT_MCU_CH32F20X)) +#include "device/dcd.h" + +#include "ch32_usbhs_reg.h" + + +// Max number of bi-directional endpoints including EP0 +#define EP_MAX 16 + +typedef struct { + uint8_t *buffer; + // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API + uint16_t total_len; + uint16_t queued_len; + uint16_t max_size; + bool short_packet; +} xfer_ctl_t; + +#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] +static xfer_ctl_t xfer_status[EP_MAX][2]; + +#define EP_TX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_TX_LEN) + (ep)*2) +#define EP_TX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_TX_CTRL) + (ep)*4) +#define EP_RX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_RX_CTRL) + (ep)*4) +#define EP_RX_MAX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_MAX_LEN) + (ep)*2) + +#define EP_TX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_TX_DMA) + (ep - 1)) +#define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1)) + +/* Endpoint Buffer */ +TU_ATTR_ALIGNED(4) uint8_t EP0_DatabufHD[64]; // ep0(64) + +volatile uint8_t USBHS_Dev_Endp0_Tog = 0x01; + +void dcd_init(uint8_t rhport) { + (void)rhport; + + memset(&xfer_status, 0, sizeof(xfer_status)); + + USBHSD->HOST_CTRL = 0x00; + USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM; + + USBHSD->CONTROL = 0; + +#if TUD_OPT_HIGH_SPEED + USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED; +#else + #error OPT_MODE_FULL_SPEED not currently supported on CH32 + USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED; +#endif + + USBHSD->INT_EN = 0; + USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN | USBHS_SUSPEND_EN; + + /* ALL endpoint enable */ + USBHSD->ENDP_CONFIG = 0xffffffff; + + USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN; + USBHSD->ENDP_TYPE = 0x00; + USBHSD->BUF_MODE = 0x00; + + USBHSD->UEP0_MAX_LEN = 64; + + USBHSD->UEP0_DMA = (uint32_t)EP0_DatabufHD; + + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_NAK; + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + + for (int ep = 1; ep < EP_MAX; ep++) { + EP_TX_LEN(ep) = 0; + EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK; + EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK; + + EP_RX_MAX_LEN(ep) = 512; + } + + USBHSD->DEV_AD = 0; + USBHSD->CONTROL |= USBHS_DEV_PU_EN; +} + +void dcd_int_enable(uint8_t rhport) { + (void)rhport; + + NVIC_EnableIRQ(USBHS_IRQn); +} + +void dcd_int_disable(uint8_t rhport) { + (void)rhport; + + NVIC_DisableIRQ(USBHS_IRQn); +} + +void dcd_edpt_close_all(uint8_t rhport) { + (void)rhport; +} + +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { + (void)dev_addr; + + // Response with zlp status + dcd_edpt_xfer(rhport, 0x80, NULL, 0); +} + +void dcd_remote_wakeup(uint8_t rhport) +{ + (void) rhport; +} + +void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) { + (void)rhport; + + if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && + request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && + request->bRequest == TUSB_REQ_SET_ADDRESS) { + USBHSD->DEV_AD = (uint8_t)request->wValue; + } + + EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK; + EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK; +} + +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) { + (void)rhport; + + uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); + + TU_ASSERT(epnum < EP_MAX); + + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->max_size = tu_edpt_packet_size(desc_edpt); + + if (epnum != 0) { + if (tu_edpt_dir(desc_edpt->bEndpointAddress) == TUSB_DIR_OUT) { + EP_RX_CTRL(epnum) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_ACK; + } else { + EP_TX_LEN(epnum) = 0; + EP_TX_CTRL(epnum) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0; + } + } + + return true; +} + +int usbd_ep_close(const uint8_t ep) { + (void)ep; + + return 0; +} +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { + (void)rhport; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if (epnum == 0) { + if (dir == TUSB_DIR_OUT) { + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_STALL; + } else { + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_STALL; + } + } else { + if (dir == TUSB_DIR_OUT) { + EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_STALL; + + } else { + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~USBHS_EP_T_RES_MASK) | USBHS_EP_T_RES_STALL; + } + } +} + +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { + (void)rhport; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if (epnum == 0) { + if (dir == TUSB_DIR_OUT) { + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + } else { + } + } else { + if (dir == TUSB_DIR_OUT) { + EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~(USBHS_EP_R_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_ACK; + + } else { + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_NAK; + } + } +} + +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { + (void)rhport; + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = buffer; + // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API + xfer->total_len = total_bytes; + xfer->queued_len = 0; + xfer->short_packet = false; + + // uint16_t num_packets = (total_bytes / xfer->max_size); + uint16_t short_packet_size = total_bytes % (xfer->max_size + 1); + + // Zero-size packet is special case. + if (short_packet_size == 0 || (total_bytes == 0)) { + xfer->short_packet = true; + } + + if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) { + if (!total_bytes) { + xfer->short_packet = true; + if (epnum == 0) { + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); + USBHS_Dev_Endp0_Tog ^= 1; + } else { + EP_TX_LEN(epnum) = 0; + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK; + } + } else { + if (epnum == 0) { + xfer->queued_len += short_packet_size; + memcpy(&EP0_DatabufHD[0], buffer, short_packet_size); + + USBHSD->UEP0_TX_LEN = short_packet_size; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); + USBHS_Dev_Endp0_Tog ^= 1; + } else { + xfer->queued_len += short_packet_size; + + EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer; + USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum); + EP_TX_LEN(epnum) = short_packet_size; + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK; + } + } + } else { /* TUSB_DIR_OUT */ + if (epnum == 0) { + uint32_t read_count = USBHSD->RX_LEN; + read_count = TU_MIN(read_count, total_bytes); + + if ((total_bytes == 8)) { + read_count = 8; + memcpy(buffer, &EP0_DatabufHD[0], 8); + } else { + memcpy(buffer, &EP0_DatabufHD[0], read_count); + } + } else { + EP_RX_DMA_ADDR(epnum) = (uint32_t)xfer->buffer; + USBHSD->ENDP_CONFIG |= (USBHS_EP0_R_EN << epnum); + } + + // usbd_ep_read(ep_addr, buffer, total_bytes, &ret_bytes); + } + return true; +} + + +static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size) { + // xfer->queued_len = xfer->total_len - remaining; + + uint16_t remaining = xfer->total_len - xfer->queued_len; + uint16_t to_recv_size; + + if (remaining <= xfer->max_size) { + // Avoid buffer overflow. + to_recv_size = (xfer_size > remaining) ? remaining : xfer_size; + } else { + // Room for full packet, choose recv_size based on what the microcontroller + // claims. + to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size; + } + + if (to_recv_size) { + } + + xfer->queued_len += xfer_size; + + // Per USB spec, a short OUT packet (including length 0) is always + // indicative of the end of a transfer (at least for ctl, bulk, int). + xfer->short_packet = (xfer_size < xfer->max_size); +} + +void dcd_int_handler(uint8_t rhport) { + (void)rhport; + + uint32_t end_num, rx_token; + uint8_t intflag = 0; + + intflag = USBHSD->INT_FG; + + if (intflag & USBHS_TRANSFER_FLAG) { + + end_num = (USBHSD->INT_ST) & MASK_UIS_ENDP; + rx_token = (((USBHSD->INT_ST) & MASK_UIS_TOKEN) >> 4) & 0x03; + + uint8_t endp = end_num | (rx_token == PID_IN ? TUSB_DIR_IN_MASK : 0); + + xfer_ctl_t *xfer = XFER_CTL_BASE(end_num, tu_edpt_dir(endp)); + + if (rx_token == PID_OUT) { + uint16_t rx_len = USBHSD->RX_LEN; + + receive_packet(xfer, rx_len); + + if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { + xfer->short_packet = false; + + dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true); + } + + if (end_num == 0) { + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0; + } + + } else if (rx_token == PID_IN) { + if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { + xfer->short_packet = false; + xfer->total_len = 0; + dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true); + + EP_TX_CTRL(end_num) = (EP_TX_CTRL(end_num) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_NAK; + + if (end_num == 0) { + } + } else { + dcd_edpt_xfer(0, endp, xfer->buffer + xfer->queued_len, xfer->total_len - xfer->queued_len); + } + } + + USBHSD->INT_FG = USBHS_TRANSFER_FLAG; /* Clear flag */ + } else if (intflag & USBHS_SETUP_FLAG) { + USBHS_Dev_Endp0_Tog = 1; + dcd_event_setup_received(0, EP0_DatabufHD, true); + + USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */ + } else if (intflag & USBHS_DETECT_FLAG) { + USBHS_Dev_Endp0_Tog = 1; + + xfer_status[0][TUSB_DIR_OUT].max_size = 64; + xfer_status[0][TUSB_DIR_IN].max_size = 64; + + dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true); + + USBHSD->DEV_AD = 0; + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0; + + USBHSD->INT_FG = USBHS_DETECT_FLAG; /* Clear flag */ + } else if (intflag & USBHS_SUSPEND_FLAG) { + dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SUSPEND }; + dcd_event_handler(&event, true); + + USBHSD->INT_FG = USBHS_SUSPEND_FLAG; /* Clear flag */ + } +} + +#endif diff --git a/src/tusb_option.h b/src/tusb_option.h index a41f5a07e..f4b1a1dd4 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -169,6 +169,7 @@ // WCH #define OPT_MCU_CH32V307 2200 ///< WCH CH32V307 +#define OPT_MCU_CH32F20X 2210 ///< WCH CH32F20x // NXP LPC MCX diff --git a/tools/get_deps.py b/tools/get_deps.py index 1fac291a3..af3043e4e 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -164,6 +164,9 @@ deps_optional = { 'hw/mcu/wch/ch32v307': ['https://github.com/openwch/ch32v307.git', '17761f5cf9dbbf2dcf665b7c04934188add20082', 'ch32v307'], + 'hw/mcu/wch/ch32f20x': ['https://github.com/openwch/ch32f20x.git', + '77c4095087e5ed2c548ec9058e655d0b8757663b', + 'ch32f20x'], 'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git', '20285262657d1b482d132d20d755c8c330d55c1f', 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x' diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf index 4919fe7b4..c3683c3d7 100644 --- a/tools/iar_template.ipcf +++ b/tools/iar_template.ipcf @@ -164,8 +164,8 @@ $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - $TUSB_DIR$/src/portable/wch/ch32v307/dcd_usbhs.c + + $TUSB_DIR$/src/portable/wch/dcd_ch32_usbhs.c $TUSB_DIR$/src/typec/usbc.c -- cgit v1.3.1 From 8b2cb63da88c0f790fee8d514971153569993b05 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Tue, 10 Oct 2023 18:22:20 +0200 Subject: Fix naming nBytesPerSample. --- src/class/audio/audio_device.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 46fd6dfa9..5d3772a9d 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -631,9 +631,9 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t // Decoding according to 2.3.1.5 Audio Streams // Helper function -static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, void * dst, const void * dst_end, void * src, uint8_t const n_ff_used) +static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesPerSample, void * dst, const void * dst_end, void * src, uint8_t const n_ff_used) { - // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2) + // Due to one FIFO contains 2 channels, data always aligned to (nBytesPerSample * 2) uint16_t * dst16 = dst; uint16_t * src16 = src; const uint16_t * dst_end16 = dst_end; @@ -641,7 +641,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nB uint32_t * src32 = src; const uint32_t * dst_end32 = dst_end; - if (nBytesToCopy == 1) + if (nBytesPerSample == 1) { while(dst16 < dst_end16) { @@ -650,7 +650,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nB } return src16; } - else if (nBytesToCopy == 2) + else if (nBytesPerSample == 2) { while(dst32 < dst_end32) { @@ -659,7 +659,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nB } return src32; } - else if (nBytesToCopy == 3) + else if (nBytesPerSample == 3) { while(dst16 < dst_end16) { @@ -670,7 +670,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nB } return src16; } - else // nBytesToCopy == 4 + else // nBytesPerSample == 4 { while(dst32 < dst_end32) { @@ -926,9 +926,9 @@ range [-1, +1) * */ // Helper function -static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesToCopy, void * src, const void * src_end, void * dst, uint8_t const n_ff_used) +static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesPerSample, void * src, const void * src_end, void * dst, uint8_t const n_ff_used) { - // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2) + // Due to one FIFO contains 2 channels, data always aligned to (nBytesPerSample * 2) uint16_t * dst16 = dst; uint16_t * src16 = src; const uint16_t * src_end16 = src_end; @@ -936,7 +936,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nB uint32_t * src32 = src; const uint32_t * src_end32 = src_end; - if (nBytesToCopy == 1) + if (nBytesPerSample == 1) { while(src16 < src_end16) { @@ -945,7 +945,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nB } return dst16; } - else if (nBytesToCopy == 2) + else if (nBytesPerSample == 2) { while(src32 < src_end32) { @@ -954,7 +954,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nB } return dst32; } - else if (nBytesToCopy == 3) + else if (nBytesPerSample == 3) { while(src16 < src_end16) { @@ -965,7 +965,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nB } return dst16; } - else // nBytesToCopy == 4 + else // nBytesPerSample == 4 { while(src32 < src_end32) { -- cgit v1.3.1 From 656e1e416aa9dbd7ba4c18e777f7294a101f0667 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Tue, 17 Oct 2023 09:46:01 +0200 Subject: Add flow control for IN transfer. --- examples/device/audio_4_channel_mic/src/main.c | 30 ++++- .../audio_4_channel_mic/src/plot_audio_samples.py | 7 +- .../device/audio_4_channel_mic/src/tusb_config.h | 15 ++- src/class/audio/audio_device.c | 140 ++++++++++++++++++--- src/class/audio/audio_device.h | 16 +++ 5 files changed, 187 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c index 4bcbdb692..52e6d71f7 100644 --- a/examples/device/audio_4_channel_mic/src/main.c +++ b/examples/device/audio_4_channel_mic/src/main.c @@ -69,8 +69,13 @@ uint8_t clkValid; audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; // Volume range state audio_control_range_4_n_t(1) sampleFreqRng; // Sample frequency range state +#if CFG_TUD_AUDIO_ENABLE_ENCODING // Audio test data, each buffer contains 2 channels, buffer[0] for CH0-1, buffer[1] for CH1-2 uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ/2]; // Ensure half word aligned +#else +// Audio test data, 4 channels muxed together, buffer[0] for CH0, buffer[1] for CH1, buffer[2] for CH2, buffer[3] for CH3 +uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_EP_SZ_IN]; // Ensure half word aligned +#endif void led_blinking_task(void); void audio_task(void); @@ -97,6 +102,7 @@ int main(void) sampleFreqRng.subrange[0].bRes = 0; // Generate dummy data +#if CFG_TUD_AUDIO_ENABLE_ENCODING uint16_t * p_buff = i2s_dummy_buffer[0]; uint16_t dataVal = 1; for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++) @@ -116,6 +122,23 @@ int main(void) float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000); *p_buff++ = (uint16_t)(sinf(t) * 25) + 200; } +#else + uint16_t * p_buff = i2s_dummy_buffer; + uint16_t dataVal = 1; + for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++) + { + // CH0 saw wave + *p_buff++ = dataVal; + // CH1 inverted saw wave + *p_buff++ = 60 + AUDIO_SAMPLE_RATE/1000 - dataVal; + dataVal++; + // CH3 square wave + *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 120:170; + // CH4 sinus wave + float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000); + *p_buff++ = (uint16_t)(sinf(t) * 25) + 200; + } +#endif while (1) { @@ -384,6 +407,8 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * { case AUDIO_CS_REQ_CUR: TU_LOG2(" Get Sample Freq.\r\n"); + // Set sample rate for flow control + tud_audio_set_tx_flow_control(sampFreq); return tud_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq)); case AUDIO_CS_REQ_RANGE: @@ -429,12 +454,15 @@ bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, u // tud_audio_write_support_ff(channel, data, samples * N_BYTES_PER_SAMPLE * N_CHANNEL_PER_FIFO); // } +#if CFG_TUD_AUDIO_ENABLE_ENCODING // Write I2S buffer into FIFO for (uint8_t cnt=0; cnt < 2; cnt++) { tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX); } - +#else + tud_audio_write(i2s_dummy_buffer, AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX); +#endif return true; } diff --git a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py index a3a2b2fd4..d17a908b6 100644 --- a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py +++ b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py @@ -10,11 +10,11 @@ if __name__ == '__main__': # print(sd.query_devices()) fs = 48000 # Sample rate - duration = 20e-3 # Duration of recording + duration = 1 # Duration of recording if platform.system() == 'Windows': # WDM-KS is needed since there are more than one MicNode device APIs (at least in Windows) - device = 'Microphone (MicNode_4_Ch), Windows WDM-KS' + device = 'Microphone (MicNode_4_Ch), Windows WASAPI' elif platform.system() == 'Darwin': device = 'MicNode_4_Ch' else: @@ -28,8 +28,7 @@ if __name__ == '__main__': time = np.arange(0, duration, 1 / fs) # time vector # strip starting zero - myrecording = myrecording[100:] - time = time[100:] + plt.plot(time, myrecording) plt.xlabel('Time [s]') plt.ylabel('Amplitude') diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h index 291ac4f79..d1e19c5a1 100644 --- a/examples/device/audio_4_channel_mic/src/tusb_config.h +++ b/examples/device/audio_4_channel_mic/src/tusb_config.h @@ -114,14 +114,25 @@ extern "C" { #define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX 2 // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX 4 // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup #define CFG_TUD_AUDIO_EP_SZ_IN TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX) + +#define CFG_TUD_AUDIO_ENABLE_ENCODING 0 + +#if CFG_TUD_AUDIO_ENABLE_ENCODING + #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ CFG_TUD_AUDIO_EP_SZ_IN -#define CFG_TUD_AUDIO_ENABLE_ENCODING 1 #define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING 1 #define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX 2 // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value #define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX) -#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) +#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ 4 * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) + +#else + +#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX 4 * CFG_TUD_AUDIO_EP_SZ_IN +#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ 4 * CFG_TUD_AUDIO_EP_SZ_IN + +#endif #ifdef __cplusplus } diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 5d3772a9d..9299440c9 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -364,14 +364,21 @@ typedef struct #endif #endif +#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL + uint32_t sample_rate_tx; + uint16_t packet_sz_tx[3]; + uint8_t bclock_id_tx; + uint8_t interval_tx; +#endif + // Encoding parameters - parameters are set when alternate AS interface is set by host -#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING +#if CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL) audio_format_type_t format_type_tx; uint8_t n_channels_tx; + uint8_t n_bytes_per_sampe_tx; #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING audio_data_format_type_I_t format_type_I_tx; - uint8_t n_bytes_per_sampe_tx; uint8_t n_channels_per_ff_tx; uint8_t n_ff_used_tx; #endif @@ -444,7 +451,7 @@ static bool audiod_verify_itf_exists(uint8_t itf, uint8_t *func_id); static bool audiod_verify_ep_exists(uint8_t ep, uint8_t *func_id); static uint8_t audiod_get_audio_fct_idx(audiod_function_t * audio); -#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING +#if (CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_ENCODING)) || (CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING) static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const * p_desc, uint8_t const * p_desc_end, uint8_t const as_itf); static inline uint8_t tu_desc_subtype(void const* desc) @@ -453,6 +460,10 @@ static inline uint8_t tu_desc_subtype(void const* desc) } #endif +#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL +static bool audiod_tx_calc_packet_size(const uint16_t* norminal_size, uint16_t data_size, uint16_t fifo_size, uint16_t* packet_size); +#endif + #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP static bool set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, uint32_t mclk_freq); #endif @@ -821,6 +832,57 @@ uint16_t tud_audio_int_ctr_n_write(uint8_t func_id, uint8_t const* buffer, uint1 #endif +#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL + +bool tud_audio_n_set_tx_flow_control(uint8_t func_id, uint32_t sample_rate) +{ + TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL); + audiod_function_t* audio = &_audiod_fct[func_id]; + + TU_VERIFY(audio->format_type_tx == AUDIO_FORMAT_TYPE_I); + TU_VERIFY(audio->n_channels_tx); + TU_VERIFY(audio->n_bytes_per_sampe_tx); + TU_VERIFY(audio->interval_tx); + + if (sample_rate == 0) + { + audio->packet_sz_tx[0] = 0; + audio->packet_sz_tx[1] = 0; + audio->packet_sz_tx[2] = 0; + return false; + } + + const uint8_t interval = (tud_speed_get() == TUSB_SPEED_FULL) ? audio->interval_tx : 1 << (audio->interval_tx - 1); + + const uint32_t sample_normimal = sample_rate * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000); + const uint32_t sample_reminder = sample_rate * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000); + + const uint16_t packet_sz_tx_min = (sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx; + const uint16_t packet_sz_tx_norm = sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx; + const uint16_t packet_sz_tx_max = (sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx; + + TU_ASSERT(packet_sz_tx_max <= audio->ep_in_sz); + + // Frmt20.pdf 2.3.1.1 USB Packets + if (sample_reminder) + { + // All virtual frame packets must either contain INT(nav) audio slots (small VFP) or INT(nav)+1 (large VFP) audio slots + audio->packet_sz_tx[0] = packet_sz_tx_norm; + audio->packet_sz_tx[1] = packet_sz_tx_norm; + audio->packet_sz_tx[2] = packet_sz_tx_max; + } else + { + // In the case where nav = INT(nav), ni may vary between INT(nav)-1 (small VFP), INT(nav) + // (medium VFP) and INT(nav)+1 (large VFP). + audio->packet_sz_tx[0] = packet_sz_tx_min; + audio->packet_sz_tx[1] = packet_sz_tx_norm; + audio->packet_sz_tx[2] = packet_sz_tx_max; + } + + return true; +} + +#endif // This function is called once a transmit of an audio packet was successfully completed. Here, we encode samples and place it in IN EP's buffer for next transmission. // If you prefer your own (more efficient) implementation suiting your purpose set CFG_TUD_AUDIO_ENABLE_ENCODING = 0 and use tud_audio_n_write. @@ -886,9 +948,16 @@ static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t * audio) #else // No support FIFOs, if no linear buffer required schedule transmit, else put data into linear buffer and schedule - +#if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL + uint16_t tgt_packet_sz; + // packet_sz_tx is based on total packet size, here we want size for each support buffer. + if (audiod_tx_calc_packet_size(audio->packet_sz_tx, tu_fifo_count(&audio->ep_in_ff), audio->ep_in_ff.depth, &tgt_packet_sz)) + n_bytes_tx = tgt_packet_sz; + else + n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz); +#else n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz); // Limit up to max packet size, more can not be done for ISO - +#endif #if USE_LINEAR_BUFFER_TX tu_fifo_read_n(&audio->ep_in_ff, audio->lin_buf_in, n_bytes_tx); TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_in, audio->lin_buf_in, n_bytes_tx)); @@ -987,7 +1056,6 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi // Determine amount of samples uint8_t const n_ff_used = audio->n_ff_used_tx; - uint16_t const nBytesToCopy = audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx; uint16_t const capPerFF = audio->ep_in_sz / n_ff_used; // Sample capacity per FIFO in bytes uint16_t nBytesPerFFToSend = tu_fifo_count(&audio->tx_supp_ff[0]); uint8_t cnt_ff; @@ -1001,14 +1069,24 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi } } - // Check if there is enough +#if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL + uint16_t tgt_packet_sz; + // packet_sz_tx is based on total packet size, here we want size for each support buffer. + if (audiod_tx_calc_packet_size(audio->packet_sz_tx, nBytesPerFFToSend * n_ff_used, audio->tx_supp_ff[0].depth * n_ff_used, &tgt_packet_sz)) + nBytesPerFFToSend = tgt_packet_sz / n_ff_used; +#endif + + // Check if there is enough data if (nBytesPerFFToSend == 0) return 0; // Limit to maximum sample number - THIS IS A POSSIBLE ERROR SOURCE IF TOO MANY SAMPLE WOULD NEED TO BE SENT BUT CAN NOT! nBytesPerFFToSend = tu_min16(nBytesPerFFToSend, capPerFF); +#if !CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL // Round to full number of samples (flooring) - nBytesPerFFToSend = (nBytesPerFFToSend / nBytesToCopy) * nBytesToCopy; + uint16_t const nSlotSize = audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx; + nBytesPerFFToSend = (nBytesPerFFToSend / nSlotSize) * nSlotSize; +#endif // Encode uint8_t * dst; @@ -1489,6 +1567,9 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin #if CFG_TUD_AUDIO_ENABLE_EP_IN ep_in = desc_ep->bEndpointAddress; ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size); + #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL + _audiod_fct[i].interval_tx = desc_ep->bInterval; + #endif #endif } else { @@ -1607,6 +1688,11 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * audio->ep_in = 0; // Necessary? + #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL + audio->packet_sz_tx[0] = 0; + audio->packet_sz_tx[1] = 0; + audio->packet_sz_tx[2] = 0; + #endif } #endif // CFG_TUD_AUDIO_ENABLE_EP_IN @@ -1657,7 +1743,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * // Find correct interface if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bInterfaceNumber == itf && ((tusb_desc_interface_t const * )p_desc)->bAlternateSetting == alt) { -#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING +#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL uint8_t const * p_desc_parse_for_params = p_desc; #endif // From this point forward follow the EP descriptors associated to the current alternate setting interface - Open EPs if necessary @@ -1686,12 +1772,13 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * audio->ep_in_sz = tu_edpt_packet_size(desc_ep); // If software encoding is enabled, parse for the corresponding parameters - doing this here means only AS interfaces with EPs get scanned for parameters - #if CFG_TUD_AUDIO_ENABLE_ENCODING + #if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL audiod_parse_for_AS_params(audio, p_desc_parse_for_params, p_desc_end, itf); // Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap - #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING - const uint16_t active_fifo_depth = (uint16_t) ((audio->tx_supp_ff_sz_max / audio->n_bytes_per_sampe_tx) * audio->n_bytes_per_sampe_tx); + #if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING + const uint16_t active_fifo_depth = (uint16_t) ((audio->tx_supp_ff_sz_max / (audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx)) + * (audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx)); for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++) { tu_fifo_config(&audio->tx_supp_ff[cnt], audio->tx_supp_ff[cnt].buffer, active_fifo_depth, 1, true); @@ -2404,7 +2491,7 @@ static bool audiod_verify_ep_exists(uint8_t ep, uint8_t *func_id) return false; } -#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING +#if (CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_ENCODING)) || (CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING) // p_desc points to the AS interface of alternate setting zero // itf is the interface number of the corresponding interface - we check if the interface belongs to EP in or EP out to see if it is a TX or RX parameter // Currently, only AS interfaces with an EP (in or out) are supposed to be parsed for! @@ -2455,7 +2542,7 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const * } // Look for a Type I Format Type Descriptor(2.3.1.6 - Audio Formats) -#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING || CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING +#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AS_INTERFACE_FORMAT_TYPE && ((audio_desc_type_I_format_t const * )p_desc)->bFormatType == AUDIO_FORMAT_TYPE_I) { #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT @@ -2491,6 +2578,31 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const * } #endif +#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL +static bool audiod_tx_calc_packet_size(const uint16_t* norminal_size, uint16_t data_size, uint16_t fifo_size, uint16_t* packet_size) +{ + TU_VERIFY(norminal_size[1]); + + // This flow control method need a FIFO size of 4*Navg + TU_VERIFY(norminal_size[1] <= fifo_size * 4); + + if (data_size < norminal_size[0]) + *packet_size = 0; + else + { + uint16_t slot_size = norminal_size[2] - norminal_size[1]; + if (data_size < fifo_size / 2 - slot_size) + *packet_size = norminal_size[0]; + else if (data_size > fifo_size / 2 + slot_size) + *packet_size = norminal_size[2]; + else + *packet_size = norminal_size[1]; + } + + return true; +} +#endif + #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback) diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h index 7c88b99fc..4cb3ca84c 100644 --- a/src/class/audio/audio_device.h +++ b/src/class/audio/audio_device.h @@ -181,6 +181,11 @@ #endif #endif +// (For TYPE-I format only) Flow control is necessary to allow IN ep send correct amount of data, unless it's a virtual device where data is perfectly synchronized to USB clock. +#ifndef CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL +#define CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL 1 +#endif + // Enable/disable feedback EP (required for asynchronous RX applications) #ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP #define CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP 0 // Feedback - 0 or 1 @@ -392,6 +397,10 @@ tu_fifo_t* tud_audio_n_get_tx_support_ff (uint8_t func_id, uint8_t ff_i uint16_t tud_audio_int_ctr_n_write (uint8_t func_id, uint8_t const* buffer, uint16_t len); #endif +#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL +bool tud_audio_n_set_tx_flow_control (uint8_t func_id, uint32_t sample_rate); +#endif + //--------------------------------------------------------------------+ // Application API (Interface0) //--------------------------------------------------------------------+ @@ -670,6 +679,13 @@ static inline uint16_t tud_audio_int_ctr_write(uint8_t const* buffer, uint16_t l } #endif +#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL +static inline bool tud_audio_set_tx_flow_control(uint32_t sample_rate) +{ + return tud_audio_n_set_tx_flow_control(0, sample_rate); +} +#endif + #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP static inline bool tud_audio_fb_set(uint32_t feedback) -- cgit v1.3.1 From 0a1d6cf4d028bce2248da01b8cc13aa4673e61b5 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Tue, 17 Oct 2023 13:06:55 +0200 Subject: Read sample rate directly from control transfer to eliminate callback. --- examples/device/audio_4_channel_mic/src/main.c | 5 +- src/class/audio/audio_device.c | 301 ++++++++++++++----------- src/class/audio/audio_device.h | 10 - 3 files changed, 173 insertions(+), 143 deletions(-) (limited to 'src') diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c index 52e6d71f7..9c37315c8 100644 --- a/examples/device/audio_4_channel_mic/src/main.c +++ b/examples/device/audio_4_channel_mic/src/main.c @@ -407,9 +407,8 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * { case AUDIO_CS_REQ_CUR: TU_LOG2(" Get Sample Freq.\r\n"); - // Set sample rate for flow control - tud_audio_set_tx_flow_control(sampFreq); - return tud_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq)); + // Buffered control transfer is needed for IN flow control to work + return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq)); case AUDIO_CS_REQ_RANGE: TU_LOG2(" Get Sample Freq. range\r\n"); diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 9299440c9..e246281be 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -461,7 +461,8 @@ static inline uint8_t tu_desc_subtype(void const* desc) #endif #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL -static bool audiod_tx_calc_packet_size(const uint16_t* norminal_size, uint16_t data_size, uint16_t fifo_size, uint16_t* packet_size); +static bool audiod_calc_tx_packet_sz(audiod_function_t* audio); +static uint16_t audiod_tx_packet_size(const uint16_t* norminal_size, uint16_t data_count, uint16_t fifo_depth, uint16_t max_size); #endif #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP @@ -832,58 +833,6 @@ uint16_t tud_audio_int_ctr_n_write(uint8_t func_id, uint8_t const* buffer, uint1 #endif -#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL - -bool tud_audio_n_set_tx_flow_control(uint8_t func_id, uint32_t sample_rate) -{ - TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL); - audiod_function_t* audio = &_audiod_fct[func_id]; - - TU_VERIFY(audio->format_type_tx == AUDIO_FORMAT_TYPE_I); - TU_VERIFY(audio->n_channels_tx); - TU_VERIFY(audio->n_bytes_per_sampe_tx); - TU_VERIFY(audio->interval_tx); - - if (sample_rate == 0) - { - audio->packet_sz_tx[0] = 0; - audio->packet_sz_tx[1] = 0; - audio->packet_sz_tx[2] = 0; - return false; - } - - const uint8_t interval = (tud_speed_get() == TUSB_SPEED_FULL) ? audio->interval_tx : 1 << (audio->interval_tx - 1); - - const uint32_t sample_normimal = sample_rate * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000); - const uint32_t sample_reminder = sample_rate * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000); - - const uint16_t packet_sz_tx_min = (sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx; - const uint16_t packet_sz_tx_norm = sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx; - const uint16_t packet_sz_tx_max = (sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx; - - TU_ASSERT(packet_sz_tx_max <= audio->ep_in_sz); - - // Frmt20.pdf 2.3.1.1 USB Packets - if (sample_reminder) - { - // All virtual frame packets must either contain INT(nav) audio slots (small VFP) or INT(nav)+1 (large VFP) audio slots - audio->packet_sz_tx[0] = packet_sz_tx_norm; - audio->packet_sz_tx[1] = packet_sz_tx_norm; - audio->packet_sz_tx[2] = packet_sz_tx_max; - } else - { - // In the case where nav = INT(nav), ni may vary between INT(nav)-1 (small VFP), INT(nav) - // (medium VFP) and INT(nav)+1 (large VFP). - audio->packet_sz_tx[0] = packet_sz_tx_min; - audio->packet_sz_tx[1] = packet_sz_tx_norm; - audio->packet_sz_tx[2] = packet_sz_tx_max; - } - - return true; -} - -#endif - // This function is called once a transmit of an audio packet was successfully completed. Here, we encode samples and place it in IN EP's buffer for next transmission. // If you prefer your own (more efficient) implementation suiting your purpose set CFG_TUD_AUDIO_ENABLE_ENCODING = 0 and use tud_audio_n_write. @@ -949,12 +898,8 @@ static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t * audio) #else // No support FIFOs, if no linear buffer required schedule transmit, else put data into linear buffer and schedule #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL - uint16_t tgt_packet_sz; // packet_sz_tx is based on total packet size, here we want size for each support buffer. - if (audiod_tx_calc_packet_size(audio->packet_sz_tx, tu_fifo_count(&audio->ep_in_ff), audio->ep_in_ff.depth, &tgt_packet_sz)) - n_bytes_tx = tgt_packet_sz; - else - n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz); + n_bytes_tx = audiod_tx_packet_size(audio->packet_sz_tx, tu_fifo_count(&audio->ep_in_ff), audio->ep_in_ff.depth, audio->ep_in_sz); #else n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz); // Limit up to max packet size, more can not be done for ISO #endif @@ -1056,7 +1001,6 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi // Determine amount of samples uint8_t const n_ff_used = audio->n_ff_used_tx; - uint16_t const capPerFF = audio->ep_in_sz / n_ff_used; // Sample capacity per FIFO in bytes uint16_t nBytesPerFFToSend = tu_fifo_count(&audio->tx_supp_ff[0]); uint8_t cnt_ff; @@ -1070,19 +1014,18 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi } #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL - uint16_t tgt_packet_sz; + const uint16_t norm_packet_sz_tx[3] = {audio->packet_sz_tx[0] / n_ff_used, + audio->packet_sz_tx[1] / n_ff_used, + audio->packet_sz_tx[2] / n_ff_used}; // packet_sz_tx is based on total packet size, here we want size for each support buffer. - if (audiod_tx_calc_packet_size(audio->packet_sz_tx, nBytesPerFFToSend * n_ff_used, audio->tx_supp_ff[0].depth * n_ff_used, &tgt_packet_sz)) - nBytesPerFFToSend = tgt_packet_sz / n_ff_used; -#endif - + nBytesPerFFToSend = audiod_tx_packet_size(norm_packet_sz_tx, nBytesPerFFToSend, audio->tx_supp_ff[0].depth, audio->ep_in_sz / n_ff_used); + // Check if there is enough data + if (nBytesPerFFToSend == 0) return 0; +#else // Check if there is enough data if (nBytesPerFFToSend == 0) return 0; - // Limit to maximum sample number - THIS IS A POSSIBLE ERROR SOURCE IF TOO MANY SAMPLE WOULD NEED TO BE SENT BUT CAN NOT! - nBytesPerFFToSend = tu_min16(nBytesPerFFToSend, capPerFF); - -#if !CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL + nBytesPerFFToSend = tu_min16(nBytesPerFFToSend, audio->ep_in_sz / n_ff_used); // Round to full number of samples (flooring) uint16_t const nSlotSize = audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx; nBytesPerFFToSend = (nBytesPerFFToSend / nSlotSize) * nSlotSize; @@ -1349,7 +1292,7 @@ void audiod_init(void) #endif // CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING // Set encoding parameters for Type_I formats -#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING +#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING switch (i) { #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0 @@ -1529,85 +1472,115 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin } #if USE_ISO_EP_ALLOCATION + { #if CFG_TUD_AUDIO_ENABLE_EP_IN - uint8_t ep_in = 0; - uint16_t ep_in_size = 0; + uint8_t ep_in = 0; + uint16_t ep_in_size = 0; #endif #if CFG_TUD_AUDIO_ENABLE_EP_OUT - uint8_t ep_out = 0; - uint16_t ep_out_size = 0; + uint8_t ep_out = 0; + uint16_t ep_out_size = 0; #endif #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP - uint8_t ep_fb = 0; + uint8_t ep_fb = 0; #endif - - uint8_t const *p_desc = _audiod_fct[i].p_desc; - uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN; - while (p_desc < p_desc_end) - { - if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) + uint8_t const *p_desc = _audiod_fct[i].p_desc; + uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN; + while (p_desc < p_desc_end) { - tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc; - if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) + if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) { - #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP - // Explicit feedback EP - if (desc_ep->bmAttributes.usage == 1) + tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc; + if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) { - ep_fb = desc_ep->bEndpointAddress; - } + #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP + // Explicit feedback EP + if (desc_ep->bmAttributes.usage == 1) + { + ep_fb = desc_ep->bEndpointAddress; + } #endif - // Data EP - if (desc_ep->bmAttributes.usage == 0) - { - if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) + // Data EP + if (desc_ep->bmAttributes.usage == 0) { + if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) + { #if CFG_TUD_AUDIO_ENABLE_EP_IN - ep_in = desc_ep->bEndpointAddress; - ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size); - #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL - _audiod_fct[i].interval_tx = desc_ep->bInterval; - #endif + ep_in = desc_ep->bEndpointAddress; + ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size); #endif - } else - { + } else + { #if CFG_TUD_AUDIO_ENABLE_EP_OUT - ep_out = desc_ep->bEndpointAddress; - ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size); + ep_out = desc_ep->bEndpointAddress; + ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size); #endif + } } - } + } } + + p_desc = tu_desc_next(p_desc); } - p_desc = tu_desc_next(p_desc); - } #if CFG_TUD_AUDIO_ENABLE_EP_IN - if (ep_in) - { - usbd_edpt_iso_alloc(rhport, ep_in, ep_in_size); - } + if (ep_in) + { + usbd_edpt_iso_alloc(rhport, ep_in, ep_in_size); + } #endif #if CFG_TUD_AUDIO_ENABLE_EP_OUT - if (ep_out) - { - usbd_edpt_iso_alloc(rhport, ep_out, ep_out_size); - } + if (ep_out) + { + usbd_edpt_iso_alloc(rhport, ep_out, ep_out_size); + } #endif #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP - if (ep_fb) - { - usbd_edpt_iso_alloc(rhport, ep_fb, 4); - } + if (ep_fb) + { + usbd_edpt_iso_alloc(rhport, ep_fb, 4); + } #endif - + } #endif // USE_ISO_EP_ALLOCATION +#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL + { + uint8_t const *p_desc = _audiod_fct[i].p_desc; + uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN; + while (p_desc < p_desc_end) + { + if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) + { + tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc; + if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) + { + if (desc_ep->bmAttributes.usage == 0) + { + if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) + { + _audiod_fct[i].interval_tx = desc_ep->bInterval; + } + } + } + } else + if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AC_INTERFACE_OUTPUT_TERMINAL) + { + if(tu_unaligned_read16(p_desc + 4) == AUDIO_TERM_TYPE_USB_STREAMING) + { + _audiod_fct[i].bclock_id_tx = p_desc[8]; + } + } + p_desc = tu_desc_next(p_desc); + } + } +#endif // CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL + break; } } @@ -1910,6 +1883,10 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * if (disable) usbd_sof_enable(rhport, false); #endif +#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL + audiod_calc_tx_packet_sz(audio); +#endif + tud_control_status(rhport, p_request); return true; @@ -2352,6 +2329,19 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req // Copy into buffer TU_VERIFY(0 == tu_memcpy_s(_audiod_fct[func_id].ctrl_buf, _audiod_fct[func_id].ctrl_buf_sz, data, (size_t)len)); +#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL + // Find data for sampling_frequency_control + if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS && p_request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE) + { + uint8_t entityID = TU_U16_HIGH(p_request->wIndex); + uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue); + if (_audiod_fct[func_id].bclock_id_tx == entityID && ctrlSel == AUDIO_CS_CTRL_SAM_FREQ && p_request->bRequest == AUDIO_CS_REQ_CUR) + { + _audiod_fct[func_id].sample_rate_tx = tu_unaligned_read32(_audiod_fct[func_id].ctrl_buf); + } + } +#endif + // Schedule transmit return tud_control_xfer(rhport, p_request, (void*)_audiod_fct[func_id].ctrl_buf, len); } @@ -2579,28 +2569,79 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const * #endif #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL -static bool audiod_tx_calc_packet_size(const uint16_t* norminal_size, uint16_t data_size, uint16_t fifo_size, uint16_t* packet_size) + +static bool audiod_calc_tx_packet_sz(audiod_function_t* audio) { - TU_VERIFY(norminal_size[1]); + TU_VERIFY(audio->format_type_tx == AUDIO_FORMAT_TYPE_I); + TU_VERIFY(audio->n_channels_tx); + TU_VERIFY(audio->n_bytes_per_sampe_tx); + TU_VERIFY(audio->interval_tx); + TU_VERIFY(audio->sample_rate_tx); - // This flow control method need a FIFO size of 4*Navg - TU_VERIFY(norminal_size[1] <= fifo_size * 4); + const uint8_t interval = (tud_speed_get() == TUSB_SPEED_FULL) ? audio->interval_tx : 1 << (audio->interval_tx - 1); - if (data_size < norminal_size[0]) - *packet_size = 0; - else + const uint32_t sample_normimal = audio->sample_rate_tx * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000); + const uint32_t sample_reminder = audio->sample_rate_tx * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000); + + const uint16_t packet_sz_tx_min = (sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx; + const uint16_t packet_sz_tx_norm = sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx; + const uint16_t packet_sz_tx_max = (sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx; + + // Endpoint size must larger than packet size + TU_ASSERT(packet_sz_tx_max <= audio->ep_in_sz); + + // Frmt20.pdf 2.3.1.1 USB Packets + if (sample_reminder) { - uint16_t slot_size = norminal_size[2] - norminal_size[1]; - if (data_size < fifo_size / 2 - slot_size) - *packet_size = norminal_size[0]; - else if (data_size > fifo_size / 2 + slot_size) - *packet_size = norminal_size[2]; - else - *packet_size = norminal_size[1]; + // All virtual frame packets must either contain INT(nav) audio slots (small VFP) or INT(nav)+1 (large VFP) audio slots + audio->packet_sz_tx[0] = packet_sz_tx_norm; + audio->packet_sz_tx[1] = packet_sz_tx_norm; + audio->packet_sz_tx[2] = packet_sz_tx_max; + } else + { + // In the case where nav = INT(nav), ni may vary between INT(nav)-1 (small VFP), INT(nav) + // (medium VFP) and INT(nav)+1 (large VFP). + audio->packet_sz_tx[0] = packet_sz_tx_min; + audio->packet_sz_tx[1] = packet_sz_tx_norm; + audio->packet_sz_tx[2] = packet_sz_tx_max; } return true; } + +static uint16_t audiod_tx_packet_size(const uint16_t* norminal_size, uint16_t data_count, uint16_t fifo_depth, uint16_t max_depth) +{ + // Flow control need a FIFO size of at least 4*Navg + if(norminal_size[1] && norminal_size[1] <= fifo_depth * 4) + { + uint16_t packet_size; + uint16_t slot_size = norminal_size[2] - norminal_size[1]; + if (data_count < fifo_depth / 2 - slot_size) + { + if (data_count < norminal_size[0]) + { + // If you get here frequently, then your I2S clock deviation is too big ! + packet_size = 0; + } else + { + packet_size = norminal_size[0]; + } + } + else if (data_count > fifo_depth / 2 + slot_size) + { + packet_size = norminal_size[2]; + } else + { + packet_size = norminal_size[1]; + } + // Normally this cap is not necessary + return tu_min16(packet_size, max_depth); + } else + { + return tu_min16(data_count, max_depth); + } +} + #endif #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h index 4cb3ca84c..ef3e12a06 100644 --- a/src/class/audio/audio_device.h +++ b/src/class/audio/audio_device.h @@ -397,9 +397,6 @@ tu_fifo_t* tud_audio_n_get_tx_support_ff (uint8_t func_id, uint8_t ff_i uint16_t tud_audio_int_ctr_n_write (uint8_t func_id, uint8_t const* buffer, uint16_t len); #endif -#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL -bool tud_audio_n_set_tx_flow_control (uint8_t func_id, uint32_t sample_rate); -#endif //--------------------------------------------------------------------+ // Application API (Interface0) @@ -679,13 +676,6 @@ static inline uint16_t tud_audio_int_ctr_write(uint8_t const* buffer, uint16_t l } #endif -#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL -static inline bool tud_audio_set_tx_flow_control(uint32_t sample_rate) -{ - return tud_audio_n_set_tx_flow_control(0, sample_rate); -} -#endif - #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP static inline bool tud_audio_fb_set(uint32_t feedback) -- cgit v1.3.1 From d83a2107883c8a6224ab99f248a59b216a8d2a82 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Tue, 17 Oct 2023 15:18:05 +0200 Subject: Add blackout time. --- src/class/audio/audio_device.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index e246281be..d32ed56b2 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -2614,25 +2614,39 @@ static uint16_t audiod_tx_packet_size(const uint16_t* norminal_size, uint16_t da // Flow control need a FIFO size of at least 4*Navg if(norminal_size[1] && norminal_size[1] <= fifo_depth * 4) { + // Use blackout to prioritize normal size packet + static int ctrl_blackout = 0; uint16_t packet_size; uint16_t slot_size = norminal_size[2] - norminal_size[1]; - if (data_count < fifo_depth / 2 - slot_size) + if (data_count < norminal_size[0]) { - if (data_count < norminal_size[0]) - { // If you get here frequently, then your I2S clock deviation is too big ! packet_size = 0; + } else + if (data_count < fifo_depth / 2 - slot_size && !ctrl_blackout) + { + packet_size = norminal_size[0]; + ctrl_blackout = 10; + } else + if (data_count > fifo_depth / 2 + slot_size && !ctrl_blackout) + { + packet_size = norminal_size[2]; + if(norminal_size[0] == norminal_size[1]) + { + // nav = INT(nav) + 1 + ctrl_blackout = 2; } else { - packet_size = norminal_size[0]; + // nav = INT(nav) + ctrl_blackout = 10; } - } - else if (data_count > fifo_depth / 2 + slot_size) - { - packet_size = norminal_size[2]; } else { packet_size = norminal_size[1]; + if (ctrl_blackout) + { + ctrl_blackout--; + } } // Normally this cap is not necessary return tu_min16(packet_size, max_depth); -- cgit v1.3.1 From e9d894fe6620d623bc393698a971d08d43516e01 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Tue, 17 Oct 2023 15:23:05 +0200 Subject: Fix compile. --- .../device/audio_4_channel_mic/src/tusb_config.h | 5 +++-- src/class/audio/audio_device.c | 26 +++++++++++----------- 2 files changed, 16 insertions(+), 15 deletions(-) (limited to 'src') diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h index d1e19c5a1..f86b63528 100644 --- a/examples/device/audio_4_channel_mic/src/tusb_config.h +++ b/examples/device/audio_4_channel_mic/src/tusb_config.h @@ -115,7 +115,8 @@ extern "C" { #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX 4 // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup #define CFG_TUD_AUDIO_EP_SZ_IN TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX) -#define CFG_TUD_AUDIO_ENABLE_ENCODING 0 +#define CFG_TUD_AUDIO_ENABLE_ENCODING 1 +#define CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL 1 #if CFG_TUD_AUDIO_ENABLE_ENCODING @@ -129,7 +130,7 @@ extern "C" { #else -#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX 4 * CFG_TUD_AUDIO_EP_SZ_IN +#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ 4 * CFG_TUD_AUDIO_EP_SZ_IN #endif diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index d32ed56b2..220771aec 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -217,7 +217,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT]; // Software encoding/decoding support FIFOs #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0 - CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ]; + CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ]; tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; #if CFG_FIFO_MUTEX osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO @@ -225,7 +225,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT]; #endif #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0 - CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ]; + CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ]; tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; #if CFG_FIFO_MUTEX osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO @@ -233,7 +233,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT]; #endif #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0 - CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ]; + CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ]; tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; #if CFG_FIFO_MUTEX osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO @@ -243,7 +243,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT]; #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING #if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0 - CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ]; + CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ]; tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; #if CFG_FIFO_MUTEX osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO @@ -251,7 +251,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT]; #endif #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0 - CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ]; + CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ]; tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; #if CFG_FIFO_MUTEX osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO @@ -259,7 +259,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT]; #endif #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0 - CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ]; + CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ]; tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; #if CFG_FIFO_MUTEX osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO @@ -2519,7 +2519,7 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const * } #endif -#if CFG_TUD_AUDIO_ENABLE_EP_OUT +#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING if (as_itf == audio->ep_out_as_intf_num) { audio->n_channels_rx = ((audio_desc_cs_as_interface_t const * )p_desc)->bNrChannels; @@ -2552,7 +2552,7 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const * } #endif -#if CFG_TUD_AUDIO_ENABLE_EP_OUT +#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING if (as_itf == audio->ep_out_as_intf_num) { audio->n_bytes_per_sampe_rx = ((audio_desc_type_I_format_t const * )p_desc)->bSubslotSize; @@ -2580,12 +2580,12 @@ static bool audiod_calc_tx_packet_sz(audiod_function_t* audio) const uint8_t interval = (tud_speed_get() == TUSB_SPEED_FULL) ? audio->interval_tx : 1 << (audio->interval_tx - 1); - const uint32_t sample_normimal = audio->sample_rate_tx * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000); - const uint32_t sample_reminder = audio->sample_rate_tx * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000); + const uint16_t sample_normimal = (uint16_t)(audio->sample_rate_tx * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000)); + const uint16_t sample_reminder = (uint16_t)(audio->sample_rate_tx * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000)); - const uint16_t packet_sz_tx_min = (sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx; - const uint16_t packet_sz_tx_norm = sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx; - const uint16_t packet_sz_tx_max = (sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx; + const uint16_t packet_sz_tx_min = (uint16_t)((sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx); + const uint16_t packet_sz_tx_norm = (uint16_t)(sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx); + const uint16_t packet_sz_tx_max = (uint16_t)((sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx); // Endpoint size must larger than packet size TU_ASSERT(packet_sz_tx_max <= audio->ep_in_sz); -- cgit v1.3.1 From ade8a19aefa91e4aba0bbb0ddeafbcd041c6a4c3 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Tue, 17 Oct 2023 21:21:52 +0200 Subject: Put sw_buf in USB section only if necessary. --- src/class/audio/audio_device.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 220771aec..9712afde9 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -110,24 +110,36 @@ #error Maximum number of audio functions restricted to three! #endif +// Put sw_buf in USB section only if necessary +#if USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING +#define IN_SW_BUF_MEM_SECTION +#else +#define IN_SW_BUF_MEM_SECTION CFG_TUD_MEM_SECTION +#endif +#if USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING +#define OUT_SW_BUF_MEM_SECTION +#else +#define OUT_SW_BUF_MEM_SECTION CFG_TUD_MEM_SECTION +#endif + // EP IN software buffers and mutexes #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0 - CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ]; + IN_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ]; #if CFG_FIFO_MUTEX osal_mutex_def_t ep_in_ff_mutex_wr_1; // No need for read mutex as only USB driver reads from FIFO #endif #endif // CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0 - CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ]; + IN_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ]; #if CFG_FIFO_MUTEX osal_mutex_def_t ep_in_ff_mutex_wr_2; // No need for read mutex as only USB driver reads from FIFO #endif #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0 - CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ]; + IN_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ]; #if CFG_FIFO_MUTEX osal_mutex_def_t ep_in_ff_mutex_wr_3; // No need for read mutex as only USB driver reads from FIFO #endif @@ -154,21 +166,21 @@ // EP OUT software buffers and mutexes #if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0 - CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ]; + OUT_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ]; #if CFG_FIFO_MUTEX osal_mutex_def_t ep_out_ff_mutex_rd_1; // No need for write mutex as only USB driver writes into FIFO #endif #endif // CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0 - CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ]; + OUT_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ]; #if CFG_FIFO_MUTEX osal_mutex_def_t ep_out_ff_mutex_rd_2; // No need for write mutex as only USB driver writes into FIFO #endif #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0 - CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ]; + OUT_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ]; #if CFG_FIFO_MUTEX osal_mutex_def_t ep_out_ff_mutex_rd_3; // No need for write mutex as only USB driver writes into FIFO #endif -- cgit v1.3.1 From 27a2c8cba4dc7c56509bb3d9b6415a6fe8f638ac Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 18 Oct 2023 18:43:07 +0700 Subject: adding nulceo stm32u5a5, fix clock configure issue dwc2 core stuck at reset --- hw/bsp/stm32u5/boards/stm32u575eval/board.h | 15 +- hw/bsp/stm32u5/boards/stm32u575nucleo/board.h | 15 +- .../boards/stm32u5a5nucleo/STM32U5A5ZJTXQ_FLASH.ld | 167 ++++++++++ hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake | 2 +- hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h | 57 ++-- hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk | 2 +- .../stm32u5a5nucleo/cubemx/stm32u5a5nucleo.ioc | 352 +++++++++++++++++++++ hw/bsp/stm32u5/family.c | 53 +++- src/common/tusb_mcu.h | 13 +- src/portable/synopsys/dwc2/dwc2_stm32.h | 10 +- src/tusb_option.h | 6 +- tools/get_deps.py | 21 +- 12 files changed, 643 insertions(+), 70 deletions(-) create mode 100644 hw/bsp/stm32u5/boards/stm32u5a5nucleo/STM32U5A5ZJTXQ_FLASH.ld create mode 100644 hw/bsp/stm32u5/boards/stm32u5a5nucleo/cubemx/stm32u5a5nucleo.ioc (limited to 'src') diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.h b/hw/bsp/stm32u5/boards/stm32u575eval/board.h index 5562b95a8..bd91502af 100644 --- a/hw/bsp/stm32u5/boards/stm32u575eval/board.h +++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.h @@ -55,12 +55,10 @@ extern "C" // RCC Clock //--------------------------------------------------------------------+ -static inline void board_clock_init(void) -{ - - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; +static void SystemClock_Config(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; + RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; + RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 }; /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); @@ -94,7 +92,8 @@ static inline void board_clock_init(void) /** Initializes the CPU, AHB and APB buses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.ClockType = + RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; @@ -104,6 +103,8 @@ static inline void board_clock_init(void) HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); } +static void SystemPower_Config(void) { +} #ifdef __cplusplus } diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h index 54a6d4cd7..6d244d418 100644 --- a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h +++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h @@ -54,12 +54,10 @@ extern "C" // RCC Clock //--------------------------------------------------------------------+ -static inline void board_clock_init(void) -{ - - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; +static void SystemClock_Config(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; + RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; + RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 }; /* Enable Power Clock */ __HAL_RCC_PWR_CLK_ENABLE(); @@ -93,7 +91,8 @@ static inline void board_clock_init(void) /** Initializes the CPU, AHB and APB buses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.ClockType = + RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; @@ -103,6 +102,8 @@ static inline void board_clock_init(void) HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); } +static void SystemPower_Config(void) { +} #ifdef __cplusplus } diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/STM32U5A5ZJTXQ_FLASH.ld b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/STM32U5A5ZJTXQ_FLASH.ld new file mode 100644 index 000000000..8aa68a6a6 --- /dev/null +++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/STM32U5A5ZJTXQ_FLASH.ld @@ -0,0 +1,167 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32U5A5xJ Device from STM32U5 series +** 4096Kbytes FLASH +** 2512Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 2496K + SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 4096K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + KEEP(*(.isr_vector)) /* Startup code */ + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake index eea16213b..24d4ef95a 100644 --- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake +++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake @@ -1,7 +1,7 @@ set(MCU_VARIANT stm32u5a5xx) set(JLINK_DEVICE stm32u5a5zj) -set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/STM32U5A9xx_FLASH.ld) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32U5A5ZJTXQ_FLASH.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h index 54a6d4cd7..37b008727 100644 --- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h +++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h @@ -54,46 +54,44 @@ extern "C" // RCC Clock //--------------------------------------------------------------------+ -static inline void board_clock_init(void) -{ - - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; +static void SystemClock_Config(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; + RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; - /* Enable Power Clock */ __HAL_RCC_PWR_CLK_ENABLE(); + HAL_PWREx_EnableVddA(); /** Configure the main internal regulator output voltage - */ - HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { + Error_Handler(); + } /** Initializes the CPU, AHB and APB buses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1; RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 10; - RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLN = 20; + RCC_OscInitStruct.PLL.PLLP = 8; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 1; + RCC_OscInitStruct.PLL.PLLR = 2; RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1; RCC_OscInitStruct.PLL.PLLFRACN = 0; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CLK48; - PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48; - - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; @@ -103,6 +101,19 @@ static inline void board_clock_init(void) HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); } +static void SystemPower_Config(void) { + HAL_PWREx_EnableVddIO2(); + + /* + * Switch to SMPS regulator instead of LDO + */ + if (HAL_PWREx_ConfigSupply(PWR_SMPS_SUPPLY) != HAL_OK) { + Error_Handler(); + } +/* USER CODE BEGIN PWR */ +/* USER CODE END PWR */ +} + #ifdef __cplusplus } diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk index 48a4206a6..13025efa6 100644 --- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk +++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk @@ -2,7 +2,7 @@ CFLAGS += \ -DSTM32U5A5xx \ # All source paths should be relative to the top level. -LD_FILE = ${ST_CMSIS}/Source/Templates/gcc/linker/STM32U5A9xx_FLASH.ld +LD_FILE = ${BOARD_PATH}/STM32U5A5ZJTXQ_FLASH.ld SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u5a5xx.s diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/cubemx/stm32u5a5nucleo.ioc b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/cubemx/stm32u5a5nucleo.ioc new file mode 100644 index 000000000..289734040 --- /dev/null +++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/cubemx/stm32u5a5nucleo.ioc @@ -0,0 +1,352 @@ +#MicroXplorer Configuration settings - do not modify +ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_2 +ADC1.IPParameters=Rank-1\#ChannelRegularConversion,master,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,OffsetNumber-1\#ChannelRegularConversion,MonitoredBy-1\#ChannelRegularConversion,NbrOfConversionFlag +ADC1.MonitoredBy-1\#ChannelRegularConversion=__NULL +ADC1.NbrOfConversionFlag=1 +ADC1.OffsetNumber-1\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC1.Rank-1\#ChannelRegularConversion=1 +ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_5CYCLE +ADC1.master=1 +CAD.formats= +CAD.pinconfig= +CAD.provider= +CORTEX_M33_NS.userName=CORTEX_M33 +File.Version=6 +GPDMA1.DIRECTION_GPDMACH0=DMA_MEMORY_TO_PERIPH +GPDMA1.DIRECTION_GPDMACH3=DMA_MEMORY_TO_PERIPH +GPDMA1.IPHANDLE_GPDMACH0-SIMPLEREQUEST_GPDMACH0=__NULL +GPDMA1.IPHANDLE_GPDMACH3-SIMPLEREQUEST_GPDMACH3=__NULL +GPDMA1.IPHANDLE_GPDMACH5-SIMPLEREQUEST_GPDMACH5=__NULL +GPDMA1.IPParameters=IPHANDLE_GPDMACH5-SIMPLEREQUEST_GPDMACH5,REQUEST_GPDMACH5,IPHANDLE_GPDMACH3-SIMPLEREQUEST_GPDMACH3,REQUEST_GPDMACH3,DIRECTION_GPDMACH3,IPHANDLE_GPDMACH0-SIMPLEREQUEST_GPDMACH0,REQUEST_GPDMACH0,DIRECTION_GPDMACH0,SRCINC_GPDMACH0 +GPDMA1.REQUEST_GPDMACH0=GPDMA1_REQUEST_USART1_TX +GPDMA1.REQUEST_GPDMACH3=GPDMA1_REQUEST_UCPD1_TX +GPDMA1.REQUEST_GPDMACH5=GPDMA1_REQUEST_UCPD1_RX +GPDMA1.SRCINC_GPDMACH0=DMA_SINC_INCREMENTED +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=false +MMTAppReg1.MEMORYMAP.AP=RW_priv_only +MMTAppReg1.MEMORYMAP.AppRegionName=RAM +MMTAppReg1.MEMORYMAP.ContextName=CortexM33 +MMTAppReg1.MEMORYMAP.CoreName=ARM Cortex-M33 +MMTAppReg1.MEMORYMAP.DefaultDataRegion=true +MMTAppReg1.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name,AP +MMTAppReg1.MEMORYMAP.Name=RAM +MMTAppReg1.MEMORYMAP.Size=2555904 +MMTAppReg1.MEMORYMAP.StartAddress=0x20000000 +MMTAppReg2.MEMORYMAP.AppRegionName=RAM Reserved Alias Region +MMTAppReg2.MEMORYMAP.CoreName=ARM Cortex-M33 +MMTAppReg2.MEMORYMAP.DefaultDataRegion=false +MMTAppReg2.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ReservedRegion,Name +MMTAppReg2.MEMORYMAP.Name=RAM Reserved Alias Region +MMTAppReg2.MEMORYMAP.ReservedRegion=true +MMTAppReg2.MEMORYMAP.Size=2555904 +MMTAppReg2.MEMORYMAP.StartAddress=0x0A000000 +MMTAppReg3.MEMORYMAP.AP=RO_priv_only +MMTAppReg3.MEMORYMAP.AppRegionName=FLASH +MMTAppReg3.MEMORYMAP.Cacheability=WTRA +MMTAppReg3.MEMORYMAP.ContextName=CortexM33 +MMTAppReg3.MEMORYMAP.CoreName=ARM Cortex-M33 +MMTAppReg3.MEMORYMAP.DefaultCodeRegion=true +MMTAppReg3.MEMORYMAP.DefaultDataRegion=false +MMTAppReg3.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,MemType,ContextName,Name,AP,Cacheability,DefaultCodeRegion +MMTAppReg3.MEMORYMAP.MemType=ROM +MMTAppReg3.MEMORYMAP.Name=FLASH +MMTAppReg3.MEMORYMAP.Size=4194304 +MMTAppReg3.MEMORYMAP.StartAddress=0x08000000 +MMTAppRegionsCount=3 +MMTConfigApplied=false +Mcu.CPN=STM32U5A5ZJT6Q +Mcu.ContextProject=TrustZoneDisabled +Mcu.Family=STM32U5 +Mcu.IP0=ADC1 +Mcu.IP1=CORTEX_M33_NS +Mcu.IP10=UCPD1 +Mcu.IP11=USART1 +Mcu.IP12=USBPD +Mcu.IP13=USBX +Mcu.IP14=USB_OTG_HS +Mcu.IP2=GPDMA1 +Mcu.IP3=ICACHE +Mcu.IP4=MEMORYMAP +Mcu.IP5=NVIC +Mcu.IP6=PWR +Mcu.IP7=RCC +Mcu.IP8=SYS +Mcu.IP9=THREADX +Mcu.IPNb=15 +Mcu.Name=STM32U5A5ZJTxQ +Mcu.Package=LQFP144 +Mcu.Pin0=PH0-OSC_IN (PH0) +Mcu.Pin1=PH1-OSC_OUT (PH1) +Mcu.Pin10=VP_GPDMA1_VS_GPDMACH0 +Mcu.Pin11=VP_GPDMA1_VS_GPDMACH3 +Mcu.Pin12=VP_GPDMA1_VS_GPDMACH5 +Mcu.Pin13=VP_ICACHE_VS_ICACHE +Mcu.Pin14=VP_PWR_VS_DBSignals +Mcu.Pin15=VP_PWR_VS_SECSignals +Mcu.Pin16=VP_PWR_VS_LPOM +Mcu.Pin17=VP_SYS_VS_tim6 +Mcu.Pin18=VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault +Mcu.Pin19=VP_USBPD_VS_USBPD1 +Mcu.Pin2=PC1 +Mcu.Pin20=VP_USBPD_VS_PD3TYPEC +Mcu.Pin21=VP_USBPD_VS_usbpd_tim2 +Mcu.Pin22=VP_USBPD_VS_usbpd_usb_cohabitation +Mcu.Pin23=VP_USBX_Core_System +Mcu.Pin24=VP_USBX_UX Device CoreStack_HS +Mcu.Pin25=VP_USBX_UX Device Controller_HS +Mcu.Pin26=VP_USBX_UX Device CDC ACM Class_HS +Mcu.Pin27=VP_MEMORYMAP_VS_MEMORYMAP +Mcu.Pin3=PB15 +Mcu.Pin4=PG2 +Mcu.Pin5=PA9 +Mcu.Pin6=PA10 +Mcu.Pin7=PA11 +Mcu.Pin8=PA12 +Mcu.Pin9=PA15 (JTDI) +Mcu.PinsNb=28 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32U5A5ZJTxQ +MxCube.Version=6.9.2 +MxDb.Version=DB.6.0.92 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.GPDMA1_Channel0_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.GPDMA1_Channel3_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.GPDMA1_Channel5_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.OTG_HS_IRQn=true\:7\:0\:true\:false\:true\:false\:true\:true\:true +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false +NVIC.SavedPendsvIrqHandlerGenerated=true +NVIC.SavedSvcallIrqHandlerGenerated=true +NVIC.SavedSystickIrqHandlerGenerated=true +NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:false\:false\:false\:true\:false +NVIC.TIM6_IRQn=true\:15\:0\:false\:false\:true\:false\:false\:true\:true +NVIC.TimeBase=TIM6_IRQn +NVIC.TimeBaseIP=TIM6 +NVIC.UCPD1_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:false\:true +NVIC.USART1_IRQn=true\:6\:0\:true\:false\:true\:false\:true\:true\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +PA10.GPIOParameters=GPIO_Speed,GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP +PA10.GPIO_Speed=GPIO_SPEED_FREQ_HIGH +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA11.GPIOParameters=GPIO_Speed +PA11.GPIO_Speed=GPIO_SPEED_FREQ_LOW +PA11.Mode=Internal_Phy_Device +PA11.Signal=USB_OTG_HS_DM +PA12.GPIOParameters=GPIO_Speed +PA12.GPIO_Speed=GPIO_SPEED_FREQ_LOW +PA12.Mode=Internal_Phy_Device +PA12.Signal=USB_OTG_HS_DP +PA15\ (JTDI).Mode=Sink_AllSignals +PA15\ (JTDI).Signal=UCPD1_CC1 +PA9.GPIOParameters=GPIO_Speed,GPIO_PuPd +PA9.GPIO_PuPd=GPIO_PULLUP +PA9.GPIO_Speed=GPIO_SPEED_FREQ_HIGH +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB15.Mode=Sink_AllSignals +PB15.Signal=UCPD1_CC2 +PC1.Mode=IN2-Single-Ended +PC1.Signal=ADC1_IN2 +PG2.GPIOParameters=GPIO_Label +PG2.GPIO_Label=LED_RED +PG2.Locked=true +PG2.Signal=GPIO_Output +PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator +PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN +PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator +PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT +PWR.IPParameters=PowerMode +PWR.PowerMode=PWR_SMPS_SUPPLY +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32U5A5ZJTxQ +ProjectManager.Example=Ux_Device_CDC_ACM +ProjectManager.ExampleSource=MxCubeFw +ProjectManager.FirmwarePackage=STM32Cube FW_U5 V1.3.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LPBAM.generateCode= +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=stm32u5a5nucleo.ioc +ProjectManager.ProjectName=stm32u5a5nucleo +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=STM32CubeIDE +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_GPDMA1_Init-GPDMA1-false-HAL-true,4-MX_ICACHE_Init-ICACHE-false-HAL-true,5-MX_USART1_UART_Init-USART1-false-HAL-false,6-MX_UCPD1_Init-UCPD1-false-LL-true,7-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-true-HAL-false,8-MX_USBPD_Init-USBPD-false-HAL-false,9-MX_USBX_Init-USBX-false-HAL-false,10-MX_ADC1_Init-ADC1-false-HAL-true,11-MX_MEMORYMAP_Init-MEMORYMAP-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true +RCC.ADCFreq_Value=16000000 +RCC.ADF1Freq_Value=160000000 +RCC.AHBFreq_Value=160000000 +RCC.APB1Freq_Value=160000000 +RCC.APB1TimFreq_Value=160000000 +RCC.APB2Freq_Value=160000000 +RCC.APB2TimFreq_Value=160000000 +RCC.APB3Freq_Value=160000000 +RCC.CK48Freq_Value=48000000 +RCC.CRSFreq_Value=48000000 +RCC.CortexFreq_Value=160000000 +RCC.DACCLockSelectionVirtual=RCC_DAC1CLKSOURCE_LSI +RCC.DACFreq_Value=32000 +RCC.EPOD_VALUE=16000000 +RCC.FCLKCortexFreq_Value=160000000 +RCC.FDCANFreq_Value=160000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=160000000 +RCC.HSE_VALUE=16000000 +RCC.HSI48_VALUE=48000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=160000000 +RCC.I2C2Freq_Value=160000000 +RCC.I2C3Freq_Value=160000000 +RCC.I2C4Freq_Value=160000000 +RCC.I2C5Freq_Value=160000000 +RCC.I2C6Freq_Value=160000000 +RCC.IPParameters=ADCFreq_Value,ADF1Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CK48Freq_Value,CRSFreq_Value,CortexFreq_Value,DACCLockSelectionVirtual,DACFreq_Value,EPOD_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2C5Freq_Value,I2C6Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSIDIV_VALUE,LSI_VALUE,MCO1PinFreq_Value,MDF1Freq_Value,MSIClockRange,MSI_VALUE,OCTOSPIMFreq_Value,PLL1P,PLL2FRACN,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL3FRACN,PLL3PoutputFreq_Value,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLLFRACN,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,RNGFreq_Value,SAESFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBPHYCLockSelection,USBPHYFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value +RCC.LPTIM2Freq_Value=160000000 +RCC.LPUART1Freq_Value=160000000 +RCC.LSCOPinFreq_Value=32000 +RCC.LSE_VALUE=32768 +RCC.LSIDIV_VALUE=32000 +RCC.LSI_VALUE=32000 +RCC.MCO1PinFreq_Value=160000000 +RCC.MDF1Freq_Value=160000000 +RCC.MSIClockRange=RCC_MSIRANGE_0 +RCC.MSI_VALUE=48000000 +RCC.OCTOSPIMFreq_Value=160000000 +RCC.PLL1P=8 +RCC.PLL2FRACN=0 +RCC.PLL2PoutputFreq_Value=3096000000 +RCC.PLL2QoutputFreq_Value=3096000000 +RCC.PLL2RoutputFreq_Value=3096000000 +RCC.PLL3FRACN=0 +RCC.PLL3PoutputFreq_Value=3096000000 +RCC.PLL3QoutputFreq_Value=3096000000 +RCC.PLL3RoutputFreq_Value=3096000000 +RCC.PLLFRACN=0 +RCC.PLLN=20 +RCC.PLLPoutputFreq_Value=40000000 +RCC.PLLQoutputFreq_Value=160000000 +RCC.PLLRCLKFreq_Value=160000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.RNGFreq_Value=48000000 +RCC.SAESFreq_Value=48000000 +RCC.SAI1Freq_Value=3096000000 +RCC.SAI2Freq_Value=3096000000 +RCC.SDMMCFreq_Value=40000000 +RCC.SPI1Freq_Value=160000000 +RCC.SPI2Freq_Value=160000000 +RCC.SPI3Freq_Value=160000000 +RCC.SYSCLKFreq_VALUE=160000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.UART4Freq_Value=160000000 +RCC.UART5Freq_Value=160000000 +RCC.USART1Freq_Value=160000000 +RCC.USART2Freq_Value=160000000 +RCC.USART3Freq_Value=160000000 +RCC.USART6Freq_Value=160000000 +RCC.USBPHYCLockSelection=RCC_USBPHYCLKSOURCE_HSE +RCC.USBPHYFreq_Value=16000000 +RCC.VCOInput2Freq_Value=48000000 +RCC.VCOInput3Freq_Value=48000000 +RCC.VCOInputFreq_Value=16000000 +RCC.VCOOutputFreq_Value=320000000 +RCC.VCOPLL2OutputFreq_Value=6192000000 +RCC.VCOPLL3OutputFreq_Value=6192000000 +USART1.IPParameters=VirtualMode-Asynchronous +USART1.VirtualMode-Asynchronous=VM_ASYNC +USBX.BSP.number=1 +USBX.Core_System=1 +USBX.IPParameters=Core_System,UX_Device_CoreStack,UX_Device_Controller,UX_DEVICE_CDC_ACM,USBD_CDCACM_EPIN_ADDR,USBD_CDCACM_EPOUT_HS_MPS,USBD_CDCACM_EPIN_HS_MPS,UX_DEVICE_APP_MEM_POOL_SIZE,USBD_PRODUCT_STRING,UX_SLAVE_REQUEST_DATA_MAX_LENGTH,USBX_DEVICE_SYS_SIZE,USBD_PID,USBD_SERIAL_NUMBER,UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH,USBD_CDCACM_EPINCMD_ADDR,MAX_POWER_IN_MILLI_AMPER +USBX.MAX_POWER_IN_MILLI_AMPER=0 +USBX.USBD_CDCACM_EPINCMD_ADDR=2 +USBX.USBD_CDCACM_EPIN_ADDR=1 +USBX.USBD_CDCACM_EPIN_HS_MPS=512 +USBX.USBD_CDCACM_EPOUT_HS_MPS=512 +USBX.USBD_PID=22336 +USBX.USBD_PRODUCT_STRING=STM32 Virtual ComPort +USBX.USBD_SERIAL_NUMBER=CDC_ACM001 +USBX.USBX_DEVICE_SYS_SIZE=4*1024 +USBX.UX_DEVICE_APP_MEM_POOL_SIZE=8192 +USBX.UX_DEVICE_CDC_ACM=1 +USBX.UX_Device_Controller=1 +USBX.UX_Device_CoreStack=1 +USBX.UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH=256 +USBX.UX_SLAVE_REQUEST_DATA_MAX_LENGTH=512 +USBX0.BSP.STBoard=false +USBX0.BSP.api=Unknown +USBX0.BSP.component= +USBX0.BSP.condition= +USBX0.BSP.instance=USB_OTG_HS +USBX0.BSP.ip=USB_OTG_HS +USBX0.BSP.mode=Device_Only +USBX0.BSP.name=USBDevice +USBX0.BSP.semaphore= +USBX0.BSP.solution=USB_OTG_HS +USB_OTG_HS.IPParameters=VirtualMode +USB_OTG_HS.VirtualMode=Device_HS +VP_GPDMA1_VS_GPDMACH0.Mode=SIMPLEREQUEST_GPDMACH0 +VP_GPDMA1_VS_GPDMACH0.Signal=GPDMA1_VS_GPDMACH0 +VP_GPDMA1_VS_GPDMACH3.Mode=SIMPLEREQUEST_GPDMACH3 +VP_GPDMA1_VS_GPDMACH3.Signal=GPDMA1_VS_GPDMACH3 +VP_GPDMA1_VS_GPDMACH5.Mode=SIMPLEREQUEST_GPDMACH5 +VP_GPDMA1_VS_GPDMACH5.Signal=GPDMA1_VS_GPDMACH5 +VP_ICACHE_VS_ICACHE.Mode=DirectMappedCache +VP_ICACHE_VS_ICACHE.Signal=ICACHE_VS_ICACHE +VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg +VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP +VP_PWR_VS_DBSignals.Mode=DisableDeadBatterySignals +VP_PWR_VS_DBSignals.Signal=PWR_VS_DBSignals +VP_PWR_VS_LPOM.Mode=PowerOptimisation +VP_PWR_VS_LPOM.Signal=PWR_VS_LPOM +VP_PWR_VS_SECSignals.Mode=Security/Privilege +VP_PWR_VS_SECSignals.Signal=PWR_VS_SECSignals +VP_SYS_VS_tim6.Mode=TIM6 +VP_SYS_VS_tim6.Signal=SYS_VS_tim6 +VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault.Mode=Core_Default +VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault.Signal=THREADX_VS_RTOSJjThreadXJjCoreJjDefault +VP_USBPD_VS_PD3TYPEC.Mode=PD3_TypeC +VP_USBPD_VS_PD3TYPEC.Signal=USBPD_VS_PD3TYPEC +VP_USBPD_VS_USBPD1.Mode=USBPD_P0 +VP_USBPD_VS_USBPD1.Signal=USBPD_VS_USBPD1 +VP_USBPD_VS_usbpd_tim2.Mode=TIM2 +VP_USBPD_VS_usbpd_tim2.Signal=USBPD_VS_usbpd_tim2 +VP_USBPD_VS_usbpd_usb_cohabitation.Mode=Enable USB Support +VP_USBPD_VS_usbpd_usb_cohabitation.Signal=USBPD_VS_usbpd_usb_cohabitation +VP_USBX_Core_System.Mode=Core_System +VP_USBX_Core_System.Signal=USBX_Core_System +VP_USBX_UX\ Device\ CDC\ ACM\ Class_HS.Mode=UX_Device_class_CDC_ACM_HS +VP_USBX_UX\ Device\ CDC\ ACM\ Class_HS.Signal=USBX_UX Device CDC ACM Class_HS +VP_USBX_UX\ Device\ Controller_HS.Mode=UX_Device_Controller_HS +VP_USBX_UX\ Device\ Controller_HS.Signal=USBX_UX Device Controller_HS +VP_USBX_UX\ Device\ CoreStack_HS.Mode=UX_Device_CoreStack_HS +VP_USBX_UX\ Device\ CoreStack_HS.Signal=USBX_UX Device CoreStack_HS +board=NUCLEO-U5A5ZJ-Q +boardIOC=true diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c index ab4194623..16a86cbbb 100644 --- a/hw/bsp/stm32u5/family.c +++ b/hw/bsp/stm32u5/family.c @@ -37,6 +37,9 @@ #pragma GCC diagnostic pop #endif +static void Error_Handler(void) { +} + #include "bsp/board_api.h" #include "board.h" @@ -47,6 +50,10 @@ void OTG_FS_IRQHandler(void) { tud_int_handler(0); } +void OTG_HS_IRQHandler(void) { + tud_int_handler(0); +} + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ @@ -54,8 +61,9 @@ void OTG_FS_IRQHandler(void) { UART_HandleTypeDef UartHandle; void board_init(void) { - - board_clock_init(); + // Init clock, implemented in board.h + SystemClock_Config(); + SystemPower_Config(); // Enable All GPIOs clocks __HAL_RCC_GPIOA_CLK_ENABLE(); @@ -75,9 +83,6 @@ void board_init(void) { #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); #endif GPIO_InitTypeDef GPIO_InitStruct; @@ -135,7 +140,13 @@ void board_init(void) { GPIO_InitStruct.Alternate = GPIO_AF10_USB; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); -#if defined(OTG_FS_VBUS_SENSE) && OTG_FS_VBUS_SENSE +#ifdef USB_OTG_FS + #if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + #endif + + #if defined(OTG_FS_VBUS_SENSE) && OTG_FS_VBUS_SENSE // Configure VBUS Pin OTG_FS_VBUS_SENSE GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; @@ -144,20 +155,44 @@ void board_init(void) { // Enable VBUS sense (B device) via pin PA9 USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; -#else + #else // Disable VBUS sense (B device) via pin PA9 USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; // B-peripheral session valid override enable USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; -#endif // vbus sense + #endif // vbus sense /* Enable USB power on Pwrctrl CR2 register */ HAL_PWREx_EnableVddUSB(); - /* USB_OTG_FS clock enable */ + /* USB clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); +#else + // STM59x/Ax/Fx/Gx only have 1 USB HS port + + #if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + #endif + + + // Disable VBUS sense (B device) + USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + // B-peripheral session valid override enable + USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + + /* Enable USB power on Pwrctrl CR2 register */ + HAL_PWREx_EnableVddUSB(); + + /* USB clock enable */ + __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); +#endif // USB_OTG_FS + + } //--------------------------------------------------------------------+ diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 8807ff8aa..1797f0bc4 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -217,9 +217,7 @@ // TypeC controller #define TUP_USBIP_TYPEC_STM32 - #define TUP_DCD_ENDPOINT_MAX 8 - #define TUP_TYPEC_RHPORTS_NUM 1 #elif TU_CHECK_MCU(OPT_MCU_STM32G0) @@ -261,14 +259,21 @@ #elif TU_CHECK_MCU(OPT_MCU_STM32U5) #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_STM32 - #define TUP_DCD_ENDPOINT_MAX 6 + + // U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY + #if defined(STM32U595xx) || defined(STM32U599xx) || defined(STM32U5A5xx) || defined(STM32U5A9xx) || \ + defined(STM32U5F7xx) || defined(STM32U5F9xx) || defined(STM32U5G7xx) || defined(STM32U5G9xx) + #define TUP_DCD_ENDPOINT_MAX 9 + #define TUP_RHPORT_HIGHSPEED 1 + #else + #define TUP_DCD_ENDPOINT_MAX 6 + #endif #elif TU_CHECK_MCU(OPT_MCU_STM32L5) #define TUP_USBIP_FSDEV #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 - //--------------------------------------------------------------------+ // Sony //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index aa77511fa..a97a10223 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -86,18 +86,16 @@ #include "stm32u5xx.h" // NOTE: STM595/5A5/599/5A9 only have 1 USB port (with integrated HS PHY) // USB_OTG_FS_BASE and OTG_FS_IRQn not defined - #if (! defined USB_OTG_FS) + #if !defined(USB_OTG_FS) #define USB_OTG_HS_PERIPH_BASE USB_OTG_HS_BASE #define EP_MAX_HS 9 #define EP_FIFO_SIZE_HS 4096 - #define USB_OTG_FS_PERIPH_BASE USB_OTG_HS_BASE - #define OTG_FS_IRQn OTG_HS_IRQn + //#define OTG_FS_IRQn OTG_HS_IRQn #else #define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE + #define EP_MAX_FS 6 + #define EP_FIFO_SIZE_FS 1280 #endif - #define EP_MAX_FS 6 - #define EP_FIFO_SIZE_FS 1280 - #else #error "Unsupported MCUs" #endif diff --git a/src/tusb_option.h b/src/tusb_option.h index a41f5a07e..a29eb8a3a 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -174,10 +174,10 @@ // NXP LPC MCX #define OPT_MCU_MCXN9 2300 ///< NXP MCX N9 Series -// Helper to check if configured MCU is one of listed +// Check if configured MCU is one of listed // Apply _TU_CHECK_MCU with || as separator to list of input -#define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m) -#define TU_CHECK_MCU(...) (TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__)) +#define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m) +#define TU_CHECK_MCU(...) (TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__)) //--------------------------------------------------------------------+ // Supported OS diff --git a/tools/get_deps.py b/tools/get_deps.py index 9fdefac9d..8f93ca61f 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -181,6 +181,10 @@ deps_all = {**deps_mandatory, **deps_optional} TOP = Path(__file__).parent.parent.resolve() +def run_cmd(cmd): + return subprocess.run(cmd, shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) + + def get_a_dep(d): if d not in deps_all.keys(): print('{} is not found in dependency list') @@ -189,25 +193,24 @@ def get_a_dep(d): commit = deps_all[d][1] families = deps_all[d][2] - print('cloning {} with {}'.format(d, url)) + print(f'cloning {d} with {url}') p = Path(TOP / d) - git_cmd = "git -C {}".format(p) + git_cmd = f"git -C {p}" # Init git deps if not existed if not p.exists(): p.mkdir(parents=True) - subprocess.run("{} init".format(git_cmd), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) - subprocess.run("{} remote add origin {}".format(git_cmd, url), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) + run_cmd(f"git -C {p} init") + run_cmd(f"git -C {p} remote add origin {url}") # Check if commit is already fetched - result = subprocess.run("{} rev-parse HEAD".format(git_cmd, commit), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) + result = run_cmd(f"git -C {p} rev-parse HEAD") head = result.stdout.decode("utf-8").splitlines()[0] - + run_cmd(f"git -C {p} reset --hard") if commit != head: - subprocess.run("{} reset --hard".format(git_cmd, commit), shell=True) - subprocess.run("{} fetch --depth 1 origin {}".format(git_cmd, commit), shell=True) - subprocess.run("{} checkout FETCH_HEAD".format(git_cmd), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) + run_cmd(f"git -C {p} fetch --depth 1 origin {commit}") + run_cmd(f"git -C {p} checkout FETCH_HEAD") return 0 -- cgit v1.3.1 From d3fa3cdf487be5929240bc23f9d109c5e3e947bc Mon Sep 17 00:00:00 2001 From: Mengsk Date: Wed, 18 Oct 2023 17:05:35 +0200 Subject: Adjsut blackout time. --- examples/device/audio_4_channel_mic/src/tusb_config.h | 4 ++-- src/class/audio/audio_device.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h index f86b63528..cf44918e2 100644 --- a/examples/device/audio_4_channel_mic/src/tusb_config.h +++ b/examples/device/audio_4_channel_mic/src/tusb_config.h @@ -126,12 +126,12 @@ extern "C" { #define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING 1 #define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX 2 // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value #define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX) -#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ 4 * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) +#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ 4 * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) // Minimum 4*EP size is needed for flow control #else #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN -#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ 4 * CFG_TUD_AUDIO_EP_SZ_IN +#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ 4 * CFG_TUD_AUDIO_EP_SZ_IN // Minimum 4*EP size is needed for flow control #endif diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 9712afde9..9af999992 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -2645,11 +2645,11 @@ static uint16_t audiod_tx_packet_size(const uint16_t* norminal_size, uint16_t da packet_size = norminal_size[2]; if(norminal_size[0] == norminal_size[1]) { - // nav = INT(nav) + 1 - ctrl_blackout = 2; + // nav > INT(nav), eg. 44.1k, 88.2k + ctrl_blackout = 0; } else { - // nav = INT(nav) + // nav = INT(nav), eg. 48k, 96k ctrl_blackout = 10; } } else -- cgit v1.3.1 From 2d802e03e9a86ff3306398f1db59b8218f625c7f Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Tue, 24 Oct 2023 22:14:24 +0200 Subject: Update audio_4_channel_mic example for HS device. --- examples/device/audio_4_channel_mic/src/main.c | 30 ++++++++++++---------- .../device/audio_4_channel_mic/src/tusb_config.h | 4 +-- src/device/usbd.h | 6 ++--- 3 files changed, 22 insertions(+), 18 deletions(-) (limited to 'src') diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c index 9c37315c8..1de4f9dac 100644 --- a/examples/device/audio_4_channel_mic/src/main.c +++ b/examples/device/audio_4_channel_mic/src/main.c @@ -71,10 +71,10 @@ audio_control_range_4_n_t(1) sampleFreqRng; // Sample frequency range stat #if CFG_TUD_AUDIO_ENABLE_ENCODING // Audio test data, each buffer contains 2 channels, buffer[0] for CH0-1, buffer[1] for CH1-2 -uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ/2]; // Ensure half word aligned +uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000/CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; #else // Audio test data, 4 channels muxed together, buffer[0] for CH0, buffer[1] for CH1, buffer[2] for CH2, buffer[3] for CH3 -uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_EP_SZ_IN]; // Ensure half word aligned +uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000]; #endif void led_blinking_task(void); @@ -185,8 +185,21 @@ void tud_resume_cb(void) void audio_task(void) { - // Yet to be filled - e.g. put meas data into TX FIFOs etc. - // asm("nop"); + // Yet to be filled - e.g. read audio from I2S buffer. + // Here we simulate a I2S receive callback every 1ms. + static uint32_t start_ms = 0; + uint32_t curr_ms = board_millis(); + if ( start_ms == curr_ms ) return; // not enough time + start_ms = curr_ms; +#if CFG_TUD_AUDIO_ENABLE_ENCODING + // Write I2S buffer into FIFO + for (uint8_t cnt=0; cnt < 2; cnt++) + { + tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX); + } +#else + tud_audio_write(i2s_dummy_buffer, AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX); +#endif } //--------------------------------------------------------------------+ @@ -453,15 +466,6 @@ bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, u // tud_audio_write_support_ff(channel, data, samples * N_BYTES_PER_SAMPLE * N_CHANNEL_PER_FIFO); // } -#if CFG_TUD_AUDIO_ENABLE_ENCODING - // Write I2S buffer into FIFO - for (uint8_t cnt=0; cnt < 2; cnt++) - { - tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX); - } -#else - tud_audio_write(i2s_dummy_buffer, AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX); -#endif return true; } diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h index cf44918e2..46484f847 100644 --- a/examples/device/audio_4_channel_mic/src/tusb_config.h +++ b/examples/device/audio_4_channel_mic/src/tusb_config.h @@ -126,12 +126,12 @@ extern "C" { #define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING 1 #define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX 2 // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value #define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX) -#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ 4 * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) // Minimum 4*EP size is needed for flow control +#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ (TUD_OPT_HIGH_SPEED ? 32 : 4) * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) // Example write FIFO every 1ms, so it should be 8 times larger for HS device #else #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN -#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ 4 * CFG_TUD_AUDIO_EP_SZ_IN // Minimum 4*EP size is needed for flow control +#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ (TUD_OPT_HIGH_SPEED ? 32 : 4) * CFG_TUD_AUDIO_EP_SZ_IN // Example write FIFO every 1ms, so it should be 8 times larger for HS device #endif diff --git a/src/device/usbd.h b/src/device/usbd.h index 782f538fd..93a2033c4 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -465,7 +465,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000) @@ -514,7 +514,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000) @@ -562,7 +562,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ 0x01),\ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\ /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\ -- cgit v1.3.1 From 9cba9a753b2d8a8c06f1dacc5c16d656397f5d79 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Oct 2023 17:40:53 +0700 Subject: update s3 devkitm with max3421 pin following metro s3, check max3421 version to make sure it is valid --- .idea/cmake.xml | 2 +- hw/bsp/espressif/boards/espressif_s3_devkitm/board.h | 6 +++--- src/portable/analog/max3421/hcd_max3421.c | 5 +++-- 3 files changed, 7 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 88e0e27ad..9f17c805c 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -16,7 +16,7 @@ - + diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h index 4b4151e72..a319fbc61 100644 --- a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h +++ b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h @@ -38,9 +38,9 @@ // SPI for USB host shield #define MAX3421_SPI_HOST SPI2_HOST -#define MAX3421_SCK_PIN 36 -#define MAX3421_MOSI_PIN 35 -#define MAX3421_MISO_PIN 37 +#define MAX3421_SCK_PIN 39 +#define MAX3421_MOSI_PIN 42 +#define MAX3421_MISO_PIN 21 #define MAX3421_CS_PIN 15 #define MAX3421_INTR_PIN 14 diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 787c1e511..4665c1b06 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -433,8 +433,9 @@ bool hcd_init(uint8_t rhport) { reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false); // V1 is 0x01, V2 is 0x12, V3 is 0x13 -// uint8_t const revision = reg_read(rhport, REVISION_ADDR, false); -// TU_LOG2_HEX(revision); + uint8_t const revision = reg_read(rhport, REVISION_ADDR, false); + TU_ASSERT(revision == 0x01 || revision == 0x12 || revision == 0x13, false); + TU_LOG2_HEX(revision); // reset reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false); -- cgit v1.3.1 From a4c542a7b4e753997864b129a4d5fd5b9b77f4e3 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 30 Oct 2023 22:21:58 +0700 Subject: addd dwc2_info.py/md update stm32u5a5 board clock & power configure, able to get passed otg clock reset --- hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h | 12 ++ hw/bsp/stm32u5/family.c | 11 +- src/portable/synopsys/dwc2/dwc2_info.md | 54 +++++++++ src/portable/synopsys/dwc2/dwc2_info.py | 158 ++++++++++++++++++++++++++ src/portable/synopsys/dwc2/dwc2_stm32.h | 95 ++++++++-------- src/portable/synopsys/dwc2/dwc2_type.h | 1 + 6 files changed, 278 insertions(+), 53 deletions(-) create mode 100644 src/portable/synopsys/dwc2/dwc2_info.md create mode 100644 src/portable/synopsys/dwc2/dwc2_info.py (limited to 'src') diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h index 37b008727..c4eb94dd8 100644 --- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h +++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h @@ -99,6 +99,18 @@ static void SystemClock_Config(void) { RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); + + // USB Clock + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USBPHY; + PeriphClkInit.UsbPhyClockSelection = RCC_USBPHYCLKSOURCE_HSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } + + /** Set the OTG PHY reference clock selection + */ + HAL_SYSCFG_SetOTGPHYReferenceClockSelection(SYSCFG_OTG_HS_PHY_CLK_SELECT_1); } static void SystemPower_Config(void) { diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c index 16a86cbbb..3fbc50d93 100644 --- a/hw/bsp/stm32u5/family.c +++ b/hw/bsp/stm32u5/family.c @@ -177,7 +177,6 @@ void board_init(void) { NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); #endif - // Disable VBUS sense (B device) USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; @@ -185,11 +184,17 @@ void board_init(void) { USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + /* USB clock enable */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); + __HAL_RCC_USBPHYC_CLK_ENABLE(); + /* Enable USB power on Pwrctrl CR2 register */ HAL_PWREx_EnableVddUSB(); + HAL_PWREx_EnableUSBHSTranceiverSupply(); - /* USB clock enable */ - __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); + /*Configuring the SYSCFG registers OTG_HS PHY*/ + HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE); #endif // USB_OTG_FS diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md new file mode 100644 index 000000000..2d8ab067f --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -0,0 +1,54 @@ +| | BCM2711 (Pi4) | EFM32GG FullSpeed | ESP32-S2 | STM32F407 Fullspeed | STM32F407 Highspeed | STM32F411 Fullspeed | STM32F412 Fullspeed | STM32F723 Fullspeed | STM32F723 HighSpeed | STM32F767 Fullspeed | STM32H743 Highspeed | STM32L476 Fullspeed | STM32U5A5 Highspeed | GD32VF103 Fullspeed | XMC4500 | +|:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------| +| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00001200 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | +| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | +| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229DCD20 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | +| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | +| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | +| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | +| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 3 | 5 | 5 | 8 | 5 | 8 | 5 | 8 | 0 | 6 | +| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 7 | 11 | 11 | 15 | 11 | 15 | 11 | 15 | 0 | 13 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nperiod_tx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - host_period_tx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - dev_token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x020001E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x0200D1E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | +| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | +| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | +| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - total_fifo_size | 4080 | 498 | 200 | 512 | 1012 | 512 | 512 | 512 | 1006 | 512 | 952 | 512 | 952 | 0 | 634 | +| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x0FF08030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x17F08030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - power_optimized | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | +| - service_interval_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_en | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - reserved13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - utmi_phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 2 | +| - dev_ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - vbus_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - a_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - b_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 7 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 | +| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | +| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py new file mode 100644 index 000000000..0af6c4c77 --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -0,0 +1,158 @@ +import click +import ctypes +import pandas as pd + +# hex value for register: guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 +dwc2_reg_list = ['guid', 'gsnpsid', 'ghwcfg1', 'ghwcfg2', 'ghwcfg3', 'ghwcfg4'] +dwc2_reg_value = { + 'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020], + 'EFM32GG FullSpeed': [0, 0x4F54330A, 0, 0x228F5910, 0x1F204E8, 0x1BF08030], + 'ESP32-S2': [0, 0x4F54400A, 0, 0x224DD930, 0xC804B5, 0xD3F0A030], + 'STM32F407 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], + 'STM32F407 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030], + 'STM32F411 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], + 'STM32F412 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], + 'STM32F723 Fullspeed': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], + 'STM32F723 HighSpeed': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030], + 'STM32F767 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], + 'STM32H743 Highspeed': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x3B8D2E8, 0xE3F00030], # both HS cores + 'STM32L476 Fullspeed': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], + 'STM32U5A5 Highspeed': [0x00005000, 0x4F54411A, 0x00000000, 0x228FE052, 0x03B882E8, 0xE2103E30], + 'GD32VF103 Fullspeed': [0x1000, 0, 0, 0, 0, 0], + 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x27A01E5, 0xDBF08030] +} + +# Combine dwc2_info with dwc2_reg_list +# dwc2_info = { +# 'BCM2711 (Pi4)': { +# 'guid': 0x2708A000, +# 'gsnpsid': 0x4F54280A, +# 'ghwcfg1': 0, +# 'ghwcfg2': 0x228DDD50, +# 'ghwcfg3': 0xFF000E8, +# 'ghwcfg4': 0x1FF00020 +# }, +dwc2_info = {key: {field: value for field, value in zip(dwc2_reg_list, values)} for key, values in dwc2_reg_value.items()} + +class GHWCFG2(ctypes.LittleEndianStructure): + _fields_ = [ + ("op_mode", ctypes.c_uint32, 3), + ("arch", ctypes.c_uint32, 2), + ("point2point", ctypes.c_uint32, 1), + ("hs_phy_type", ctypes.c_uint32, 2), + ("fs_phy_type", ctypes.c_uint32, 2), + ("num_dev_ep", ctypes.c_uint32, 4), + ("num_host_ch", ctypes.c_uint32, 4), + ("period_channel_support", ctypes.c_uint32, 1), + ("enable_dynamic_fifo", ctypes.c_uint32, 1), + ("mul_cpu_int", ctypes.c_uint32, 1), + ("reserved21", ctypes.c_uint32, 1), + ("nperiod_tx_q_depth", ctypes.c_uint32, 2), + ("host_period_tx_q_depth", ctypes.c_uint32, 2), + ("dev_token_q_depth", ctypes.c_uint32, 5), + ("otg_enable_ic_usb", ctypes.c_uint32, 1) + ] + + +class GHWCFG3(ctypes.LittleEndianStructure): + _fields_ = [ + ("xfer_size_width", ctypes.c_uint32, 4), + ("packet_size_width", ctypes.c_uint32, 3), + ("otg_enable", ctypes.c_uint32, 1), + ("i2c_enable", ctypes.c_uint32, 1), + ("vendor_ctrl_itf", ctypes.c_uint32, 1), + ("optional_feature_removed", ctypes.c_uint32, 1), + ("synch_reset", ctypes.c_uint32, 1), + ("otg_adp_support", ctypes.c_uint32, 1), + ("otg_enable_hsic", ctypes.c_uint32, 1), + ("battery_charger_support", ctypes.c_uint32, 1), + ("lpm_mode", ctypes.c_uint32, 1), + ("total_fifo_size", ctypes.c_uint32, 16) + ] + + +class GHWCFG4(ctypes.LittleEndianStructure): + _fields_ = [ + ("num_dev_period_in_ep", ctypes.c_uint32, 4), + ("power_optimized", ctypes.c_uint32, 1), + ("ahb_freq_min", ctypes.c_uint32, 1), + ("hibernation", ctypes.c_uint32, 1), + ("reserved7", ctypes.c_uint32, 3), + ("service_interval_mode", ctypes.c_uint32, 1), + ("ipg_isoc_en", ctypes.c_uint32, 1), + ("acg_enable", ctypes.c_uint32, 1), + ("reserved13", ctypes.c_uint32, 1), + ("utmi_phy_data_width", ctypes.c_uint32, 2), + ("dev_ctrl_ep_num", ctypes.c_uint32, 4), + ("iddg_filter_enabled", ctypes.c_uint32, 1), + ("vbus_valid_filter_enabled", ctypes.c_uint32, 1), + ("a_valid_filter_enabled", ctypes.c_uint32, 1), + ("b_valid_filter_enabled", ctypes.c_uint32, 1), + ("dedicated_fifos", ctypes.c_uint32, 1), + ("num_dev_in_eps", ctypes.c_uint32, 4), + ("dma_desc_enable", ctypes.c_uint32, 1), + ("dma_dynamic", ctypes.c_uint32, 1) + ] + + +@click.group() +def cli(): + pass + + +@cli.command() +@click.argument('mcus', nargs=-1) +@click.option('-a', '--all', is_flag=True, help='Print all bit-field values') +def info(mcus, all): + """Print DWC2 register values for given MCU(s)""" + if len(mcus) == 0: + mcus = dwc2_info + + for mcu in mcus: + for entry in dwc2_info: + if mcu.lower() in entry.lower(): + print(f"## {entry}") + for r_name, r_value in dwc2_info[entry].items(): + print(f"{r_name} = 0x{r_value:08X}") + # Print bit-field values + if all and r_name.upper() in globals(): + class_name = globals()[r_name.upper()] + ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little')) + for field_name, field_type, _ in class_name._fields_: + print(f" {field_name} = {getattr(ghwcfg, field_name)}") + + +@cli.command() +def render_md(): + """Render dwc2_info to Markdown table""" + # Create an empty list to hold the dictionaries + dwc2_info_list = [] + + #Iterate over the dwc2_info dictionary and extract fields + for device, reg_values in dwc2_info.items(): + entry_dict = {"Device": device} + for r_name, r_value in reg_values.items(): + entry_dict[r_name] = f"0x{r_value:08X}" + # Print bit-field values + if r_name.upper() in globals(): + class_name = globals()[r_name.upper()] + ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little')) + for field_name, field_type, _ in class_name._fields_: + entry_dict[f' - {field_name}'] = getattr(ghwcfg, field_name) + + dwc2_info_list.append(entry_dict) + + # Create a Pandas DataFrame from the list of dictionaries + df = pd.DataFrame(dwc2_info_list).set_index('Device') + + # Transpose the DataFrame to switch rows and columns + df = df.T + #print(df) + + # Write the Markdown table to a file + with open('dwc2_info.md', 'w') as md_file: + md_file.write(df.to_markdown()) + + +if __name__ == '__main__': + cli() diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index a97a10223..57df4e941 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -28,7 +28,7 @@ #define _DWC2_STM32_H_ #ifdef __cplusplus - extern "C" { +extern "C" { #endif // EP_MAX : Max number of bi-directional endpoints including EP0 @@ -84,17 +84,15 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32U5 #include "stm32u5xx.h" - // NOTE: STM595/5A5/599/5A9 only have 1 USB port (with integrated HS PHY) - // USB_OTG_FS_BASE and OTG_FS_IRQn not defined - #if !defined(USB_OTG_FS) + // U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY + #ifdef USB_OTG_FS + #define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE + #define EP_MAX_FS 6 + #define EP_FIFO_SIZE_FS 1280 + #else #define USB_OTG_HS_PERIPH_BASE USB_OTG_HS_BASE #define EP_MAX_HS 9 #define EP_FIFO_SIZE_HS 4096 - //#define OTG_FS_IRQn OTG_HS_IRQn - #else - #define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE - #define EP_MAX_FS 6 - #define EP_FIFO_SIZE_FS 1280 #endif #else #error "Unsupported MCUs" @@ -109,15 +107,14 @@ // On STM32 for consistency we associate // - Port0 to OTG_FS, and Port1 to OTG_HS -static const dwc2_controller_t _dwc2_controller[] = -{ -#ifdef USB_OTG_FS_PERIPH_BASE - { .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS }, -#endif - -#ifdef USB_OTG_HS_PERIPH_BASE - { .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS }, -#endif +static const dwc2_controller_t _dwc2_controller[] = { + #ifdef USB_OTG_FS_PERIPH_BASE + { .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS }, + #endif + + #ifdef USB_OTG_HS_PERIPH_BASE + { .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS }, + #endif }; //--------------------------------------------------------------------+ @@ -128,40 +125,33 @@ static const dwc2_controller_t _dwc2_controller[] = // extern uint32_t SystemCoreClock; TU_ATTR_ALWAYS_INLINE -static inline void dwc2_dcd_int_enable(uint8_t rhport) -{ - NVIC_EnableIRQ((IRQn_Type)_dwc2_controller[rhport].irqnum); +static inline void dwc2_dcd_int_enable(uint8_t rhport) { + NVIC_EnableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum); } TU_ATTR_ALWAYS_INLINE -static inline void dwc2_dcd_int_disable (uint8_t rhport) -{ - NVIC_DisableIRQ((IRQn_Type)_dwc2_controller[rhport].irqnum); +static inline void dwc2_dcd_int_disable(uint8_t rhport) { + NVIC_DisableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum); } TU_ATTR_ALWAYS_INLINE -static inline void dwc2_remote_wakeup_delay(void) -{ +static inline void dwc2_remote_wakeup_delay(void) { // try to delay for 1 ms uint32_t count = SystemCoreClock / 1000; - while ( count-- ) __NOP(); + while (count--) __NOP(); } // MCU specific PHY init, called BEFORE core reset -static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) -{ - if ( hs_phy_type == HS_PHY_TYPE_NONE ) - { +static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { + if (hs_phy_type == HS_PHY_TYPE_NONE) { // Enable on-chip FS PHY dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN; - }else - { - // Disable FS PHY + } else { + // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable' dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN; // Enable on-chip HS PHY - if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) - { + if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) { #ifdef USB_HS_PHYC // Enable UTMI HS PHY dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN; @@ -200,34 +190,39 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) } // MCU specific PHY update, it is called AFTER init() and core reset -static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) -{ +static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { // used to set turnaround time for fullspeed, nothing to do in highspeed mode - if ( hs_phy_type == HS_PHY_TYPE_NONE ) - { + if (hs_phy_type == HS_PHY_TYPE_NONE) { // Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual uint32_t turnaround; - if ( SystemCoreClock >= 32000000u ) + if (SystemCoreClock >= 32000000u) { turnaround = 0x6u; - else if ( SystemCoreClock >= 27500000u ) + } else if (SystemCoreClock >= 27500000u) { turnaround = 0x7u; - else if ( SystemCoreClock >= 24000000u ) + } else if (SystemCoreClock >= 24000000u) { turnaround = 0x8u; - else if ( SystemCoreClock >= 21800000u ) + } else if (SystemCoreClock >= 21800000u) { turnaround = 0x9u; - else if ( SystemCoreClock >= 20000000u ) + } + else if (SystemCoreClock >= 20000000u) { turnaround = 0xAu; - else if ( SystemCoreClock >= 18500000u ) + } + else if (SystemCoreClock >= 18500000u) { turnaround = 0xBu; - else if ( SystemCoreClock >= 17200000u ) + } + else if (SystemCoreClock >= 17200000u) { turnaround = 0xCu; - else if ( SystemCoreClock >= 16000000u ) + } + else if (SystemCoreClock >= 16000000u) { turnaround = 0xDu; - else if ( SystemCoreClock >= 15000000u ) + } + else if (SystemCoreClock >= 15000000u) { turnaround = 0xEu; - else + } + else { turnaround = 0xFu; + } dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (turnaround << GUSBCFG_TRDT_Pos); } diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 3fc979337..6516882da 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -43,6 +43,7 @@ typedef struct #define DWC2_CORE_REV_3_00a 0x4f54300a #define DWC2_CORE_REV_3_10a 0x4f54310a #define DWC2_CORE_REV_4_00a 0x4f54400a +#define DWC2_CORE_REV_4_11a 0x4f54411a #define DWC2_CORE_REV_4_20a 0x4f54420a #define DWC2_FS_IOT_REV_1_00a 0x5531100a #define DWC2_HS_IOT_REV_1_00a 0x5532100a -- cgit v1.3.1 From 305ef5d48a083f2052351a8a325310168c420c0e Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 30 Oct 2023 22:22:27 +0700 Subject: minor space format dwc2 driver --- src/portable/synopsys/dwc2/dcd_dwc2.c | 648 +++++++++++++--------------------- 1 file changed, 237 insertions(+), 411 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index c6132a1f5..7b50a7d54 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -82,8 +82,8 @@ static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; typedef struct { - uint8_t * buffer; - tu_fifo_t * ff; + uint8_t* buffer; + tu_fifo_t* ff; uint16_t total_len; uint16_t max_size; uint8_t interval; @@ -93,30 +93,27 @@ static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) // EP0 transfers are limited to 1 packet - larger sizes has to be split -static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type +static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type // TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz -static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs) -static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size) +static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs) +static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size) // SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by static bool _sof_en; // Calculate the RX FIFO size according to recommendations from reference manual -static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count) -{ - return 15 + 2*(max_ep_size/4) + 2*ep_count; +static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count) { + return 15 + 2 * (max_ep_size / 4) + 2 * ep_count; } -static void update_grxfsiz(uint8_t rhport) -{ - dwc2_regs_t * dwc2 = DWC2_REG(rhport); +static void update_grxfsiz(uint8_t rhport) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; // Determine largest EP size for RX FIFO uint16_t max_epsize = 0; - for (uint8_t epnum = 0; epnum < ep_count; epnum++) - { + for (uint8_t epnum = 0; epnum < ep_count; epnum++) { max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size); } @@ -125,9 +122,8 @@ static void update_grxfsiz(uint8_t rhport) } // Start of Bus Reset -static void bus_reset(uint8_t rhport) -{ - dwc2_regs_t * dwc2 = DWC2_REG(rhport); +static void bus_reset(uint8_t rhport) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; tu_memclr(xfer_status, sizeof(xfer_status)); @@ -139,15 +135,14 @@ static void bus_reset(uint8_t rhport) dwc2->dcfg &= ~DCFG_DAD_Msk; // 1. NAK for all OUT endpoints - for ( uint8_t n = 0; n < ep_count; n++ ) - { + for (uint8_t n = 0; n < ep_count; n++) { dwc2->epout[n].doepctl |= DOEPCTL_SNAK; } // 2. Set up interrupt mask dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos); - dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; - dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; + dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; + dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; // "USB Data FIFOs" section in reference manual // Peripheral FIFO architecture @@ -206,36 +201,34 @@ static void bus_reset(uint8_t rhport) _allocated_fifo_words_tx = 16; // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) - dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (_dwc2_controller[rhport].ep_fifo_size/4 - _allocated_fifo_words_tx); + dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx); // Fixed control EP0 size to 64 bytes dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); xfer_status[0][TUSB_DIR_OUT].max_size = 64; - xfer_status[0][TUSB_DIR_IN ].max_size = 64; + xfer_status[0][TUSB_DIR_IN].max_size = 64; dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; } -static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes) -{ +static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, + uint16_t total_bytes) { (void) rhport; - dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2_regs_t* dwc2 = DWC2_REG(rhport); // EP0 is limited to one packet each xfer // We use multiple transaction of xfer->max_size length to get a whole transfer done - if ( epnum == 0 ) - { - xfer_ctl_t *const xfer = XFER_CTL_BASE(epnum, dir); + if (epnum == 0) { + xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir); total_bytes = tu_min16(ep0_pending[dir], xfer->max_size); ep0_pending[dir] -= total_bytes; } // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here. - if ( dir == TUSB_DIR_IN ) - { + if (dir == TUSB_DIR_IN) { dwc2_epin_t* epin = dwc2->epin; // A full IN transfer (multiple packets, possibly) triggers XFRC. @@ -245,20 +238,16 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; // For ISO endpoint set correct odd/even bit for next frame. - if ( (epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 ) - { + if ((epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); } // Enable fifo empty interrupt only if there are something to put in the fifo. - if ( total_bytes != 0 ) - { + if (total_bytes != 0) { dwc2->diepempmsk |= (1 << epnum); } - } - else - { + } else { dwc2_epout_t* epout = dwc2->epout; // A full OUT transfer (multiple packets, possibly) triggers XFRC. @@ -267,9 +256,8 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk); epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK; - if ( (epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && - XFER_CTL_BASE(epnum, dir)->interval == 1 ) - { + if ((epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && + XFER_CTL_BASE(epnum, dir)->interval == 1) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); @@ -281,93 +269,35 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c /* Controller API *------------------------------------------------------------------*/ #if CFG_TUSB_DEBUG >= DWC2_DEBUG -void print_dwc2_info(dwc2_regs_t * dwc2) -{ - dwc2_ghwcfg2_t const * hw_cfg2 = &dwc2->ghwcfg2_bm; - dwc2_ghwcfg3_t const * hw_cfg3 = &dwc2->ghwcfg3_bm; - dwc2_ghwcfg4_t const * hw_cfg4 = &dwc2->ghwcfg4_bm; -// TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl); -// TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg); -// TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg); - TU_LOG_HEX(DWC2_DEBUG, dwc2->guid); - TU_LOG_HEX(DWC2_DEBUG, dwc2->gsnpsid); - TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg1); - - // HW configure 2 - TU_LOG(DWC2_DEBUG, "\r\n"); - TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg2); - TU_LOG_INT(DWC2_DEBUG, hw_cfg2->op_mode ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg2->arch ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg2->point2point ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg2->hs_phy_type ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg2->fs_phy_type ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg2->num_dev_ep ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg2->num_host_ch ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg2->period_channel_support ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg2->enable_dynamic_fifo ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg2->mul_cpu_int ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg2->nperiod_tx_q_depth ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg2->host_period_tx_q_depth ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg2->dev_token_q_depth ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg2->otg_enable_ic_usb ); - - // HW configure 3 - TU_LOG(DWC2_DEBUG, "\r\n"); - TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg3); - TU_LOG_INT(DWC2_DEBUG, hw_cfg3->xfer_size_width ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg3->packet_size_width ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_enable ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg3->i2c_enable ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg3->vendor_ctrl_itf ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg3->optional_feature_removed ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg3->synch_reset ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_adp_support ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_enable_hsic ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg3->battery_charger_support ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg3->lpm_mode ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg3->total_fifo_size ); - - // HW configure 4 - TU_LOG(DWC2_DEBUG, "\r\n"); - TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg4); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->num_dev_period_in_ep ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->power_optimized ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->ahb_freq_min ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->hibernation ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->service_interval_mode ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->ipg_isoc_en ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->acg_enable ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->utmi_phy_data_width ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dev_ctrl_ep_num ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->iddg_filter_enabled ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->vbus_valid_filter_enabled ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->a_valid_filter_enabled ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->b_valid_filter_enabled ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dedicated_fifos ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->num_dev_in_eps ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dma_desc_enable ); - TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dma_dynamic ); +void print_dwc2_info(dwc2_regs_t* dwc2) { + // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 + // use dwc2_info.py/md for bit-field value and comparison with other ports + volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid; + TU_LOG(DWC2_DEBUG, "guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n"); + for (size_t i = 0; i < 5; i++) { + TU_LOG(DWC2_DEBUG, "0x%08lX, ", p[i]); + } + TU_LOG(DWC2_DEBUG, "0x%08lX\r\n", p[5]); } + #endif -static void reset_core(dwc2_regs_t * dwc2) -{ +static void reset_core(dwc2_regs_t* dwc2) { // reset core dwc2->grstctl |= GRSTCTL_CSRST; // wait for reset bit is cleared // TODO version 4.20a should wait for RESET DONE mask - while (dwc2->grstctl & GRSTCTL_CSRST) { } + while (dwc2->grstctl & GRSTCTL_CSRST) {} // wait for AHB master IDLE - while ( !(dwc2->grstctl & GRSTCTL_AHBIDL) ) { } + while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {} // wait for device mode ? } -static bool phy_hs_supported(dwc2_regs_t * dwc2) -{ +static bool phy_hs_supported(dwc2_regs_t* dwc2) { // note: esp32 incorrect report its hs_phy_type as utmi #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) return false; @@ -376,8 +306,7 @@ static bool phy_hs_supported(dwc2_regs_t * dwc2) #endif } -static void phy_fs_init(dwc2_regs_t * dwc2) -{ +static void phy_fs_init(dwc2_regs_t* dwc2) { TU_LOG(DWC2_DEBUG, "Fullspeed PHY init\r\n"); // Select FS PHY @@ -401,15 +330,13 @@ static void phy_fs_init(dwc2_regs_t * dwc2) dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos); } -static void phy_hs_init(dwc2_regs_t * dwc2) -{ +static void phy_hs_init(dwc2_regs_t* dwc2) { uint32_t gusbcfg = dwc2->gusbcfg; // De-select FS PHY gusbcfg &= ~GUSBCFG_PHYSEL; - if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) - { + if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) { TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n"); // Select ULPI @@ -423,8 +350,7 @@ static void phy_hs_init(dwc2_regs_t * dwc2) // Disable FS/LS ULPI gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM); - }else - { + } else { TU_LOG(DWC2_DEBUG, "Highspeed UTMI+ PHY init\r\n"); // Select UTMI+ with 8-bit interface @@ -465,8 +391,7 @@ static void phy_hs_init(dwc2_regs_t * dwc2) dwc2->dcfg = dcfg; } -static bool check_dwc2(dwc2_regs_t * dwc2) -{ +static bool check_dwc2(dwc2_regs_t* dwc2) { #if CFG_TUSB_DEBUG >= DWC2_DEBUG print_dwc2_info(dwc2); #endif @@ -481,41 +406,35 @@ static bool check_dwc2(dwc2_regs_t * dwc2) return true; } -void dcd_init (uint8_t rhport) -{ +void dcd_init(uint8_t rhport) { // Programming model begins in the last section of the chapter on the USB // peripheral in each Reference Manual. - dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Check Synopsys ID register, failed if controller clock/power is not enabled - TU_VERIFY(check_dwc2(dwc2), ); - + if (!check_dwc2(dwc2)) return; dcd_disconnect(rhport); // max number of endpoints & total_fifo_size are: // hw_cfg2->num_dev_ep, hw_cfg2->total_fifo_size - if( phy_hs_supported(dwc2) ) - { - // Highspeed - phy_hs_init(dwc2); - }else - { - // core does not support highspeed or hs-phy is not present - phy_fs_init(dwc2); + if (phy_hs_supported(dwc2)) { + phy_hs_init(dwc2); // Highspeed + } else { + phy_fs_init(dwc2); // core does not support highspeed or hs phy is not present } // Restart PHY clock dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE); - /* Set HS/FS Timeout Calibration to 7 (max available value). - * The number of PHY clocks that the application programs in - * this field is added to the high/full speed interpacket timeout - * duration in the core to account for any additional delays - * introduced by the PHY. This can be required, because the delay - * introduced by the PHY in generating the linestate condition - * can vary from one PHY to another. - */ + /* Set HS/FS Timeout Calibration to 7 (max available value). + * The number of PHY clocks that the application programs in + * this field is added to the high/full speed interpacket timeout + * duration in the core to account for any additional delays + * introduced by the PHY. This can be required, because the delay + * introduced by the PHY in generating the linestate condition + * can vary from one PHY to another. + */ dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos); // Force device mode @@ -537,7 +456,7 @@ void dcd_init (uint8_t rhport) // Required as part of core initialization. // TODO: How should mode mismatch be handled? It will cause // the core to stop working/require reset. - dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_MMISM | GINTMSK_RXFLVLM | + dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_MMISM | GINTMSK_RXFLVLM | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; // Enable global interrupt @@ -554,30 +473,26 @@ void dcd_init (uint8_t rhport) dcd_connect(rhport); } -void dcd_int_enable (uint8_t rhport) -{ +void dcd_int_enable(uint8_t rhport) { dwc2_dcd_int_enable(rhport); } -void dcd_int_disable (uint8_t rhport) -{ +void dcd_int_disable(uint8_t rhport) { dwc2_dcd_int_disable(rhport); } -void dcd_set_address (uint8_t rhport, uint8_t dev_addr) -{ - dwc2_regs_t * dwc2 = DWC2_REG(rhport); +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); dwc2->dcfg = (dwc2->dcfg & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos); // Response with status after changing device address dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); } -void dcd_remote_wakeup(uint8_t rhport) -{ +void dcd_remote_wakeup(uint8_t rhport) { (void) rhport; - dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2_regs_t* dwc2 = DWC2_REG(rhport); // set remote wakeup dwc2->dctl |= DCTL_RWUSIG; @@ -592,35 +507,29 @@ void dcd_remote_wakeup(uint8_t rhport) dwc2->dctl &= ~DCTL_RWUSIG; } -void dcd_connect(uint8_t rhport) -{ +void dcd_connect(uint8_t rhport) { (void) rhport; - dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2_regs_t* dwc2 = DWC2_REG(rhport); dwc2->dctl &= ~DCTL_SDIS; } -void dcd_disconnect(uint8_t rhport) -{ +void dcd_disconnect(uint8_t rhport) { (void) rhport; - dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2_regs_t* dwc2 = DWC2_REG(rhport); dwc2->dctl |= DCTL_SDIS; } // Be advised: audio, video and possibly other iso-ep classes use dcd_sof_enable() to enable/disable its corresponding ISR on purpose! -void dcd_sof_enable(uint8_t rhport, bool en) -{ +void dcd_sof_enable(uint8_t rhport, bool en) { (void) rhport; - dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2_regs_t* dwc2 = DWC2_REG(rhport); _sof_en = en; - if (en) - { + if (en) { dwc2->gintsts = GINTSTS_SOF; dwc2->gintmsk |= GINTMSK_SOFM; - } - else - { + } else { dwc2->gintmsk &= ~GINTMSK_SOFM; } } @@ -629,33 +538,30 @@ void dcd_sof_enable(uint8_t rhport, bool en) /* DCD Endpoint port *------------------------------------------------------------------*/ -bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) -{ +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) { (void) rhport; - dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); TU_ASSERT(epnum < ep_count); - xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); xfer->max_size = tu_edpt_packet_size(desc_edpt); xfer->interval = desc_edpt->bInterval; uint16_t const fifo_size = tu_div_ceil(xfer->max_size, 4); - if(dir == TUSB_DIR_OUT) - { + if (dir == TUSB_DIR_OUT) { // Calculate required size of RX FIFO - uint16_t const sz = calc_grxfsiz(4*fifo_size, ep_count); + uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count); // If size_rx needs to be extended check if possible and if so enlarge it - if (dwc2->grxfsiz < sz) - { - TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size/4); + if (dwc2->grxfsiz < sz) { + TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4); // Enlarge RX FIFO dwc2->grxfsiz = sz; @@ -667,9 +573,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) (xfer->max_size << DOEPCTL_MPSIZ_Pos); dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum); - } - else - { + } else { // "USB Data FIFOs" section in reference manual // Peripheral FIFO architecture // @@ -692,15 +596,17 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". // Check if free space is available - TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size/4); + TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4); _allocated_fifo_words_tx += fifo_size; - TU_LOG(DWC2_DEBUG, " Allocated %u bytes at offset %lu", fifo_size*4, _dwc2_controller[rhport].ep_fifo_size-_allocated_fifo_words_tx*4); + TU_LOG(DWC2_DEBUG, " Allocated %u bytes at offset %lu", fifo_size * 4, + _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4); // DIEPTXF starts at FIFO #1. // Both TXFD and TXSA are in unit of 32-bit words. - dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (_dwc2_controller[rhport].ep_fifo_size/4 - _allocated_fifo_words_tx); + dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | + (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx); dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) | (epnum << DIEPCTL_TXFNUM_Pos) | @@ -715,16 +621,14 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) } // Close all non-control endpoints, cancel all pending transfers if any. -void dcd_edpt_close_all (uint8_t rhport) -{ - dwc2_regs_t * dwc2 = DWC2_REG(rhport); +void dcd_edpt_close_all(uint8_t rhport) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; // Disable non-control interrupt dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); - for(uint8_t n = 1; n < ep_count; n++) - { + for (uint8_t n = 1; n < ep_count; n++) { // disable OUT endpoint dwc2->epout[n].doepctl = 0; xfer_status[n][TUSB_DIR_OUT].max_size = 0; @@ -738,31 +642,27 @@ void dcd_edpt_close_all (uint8_t rhport) _allocated_fifo_words_tx = 16; } -bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) -{ +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); - xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); - xfer->buffer = buffer; - xfer->ff = NULL; - xfer->total_len = total_bytes; + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = buffer; + xfer->ff = NULL; + xfer->total_len = total_bytes; // EP0 can only handle one packet - if(epnum == 0) - { + if (epnum == 0) { ep0_pending[dir] = total_bytes; // Schedule the first transaction for EP0 transfer edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]); - } - else - { + } else { uint16_t num_packets = (total_bytes / xfer->max_size); uint16_t const short_packet_size = total_bytes % xfer->max_size; // Zero-size packet is special case. - if ( (short_packet_size > 0) || (total_bytes == 0) ) num_packets++; + if ((short_packet_size > 0) || (total_bytes == 0)) num_packets++; // Schedule packets to be sent within interrupt edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); @@ -775,24 +675,23 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t // bytes should be written and second to keep the return value free to give back a boolean // success message. If total_bytes is too big, the FIFO will copy only what is available // into the USB buffer! -bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) -{ +bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t total_bytes) { // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1 TU_ASSERT(ff->item_size == 1); uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); - xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); - xfer->buffer = NULL; - xfer->ff = ff; - xfer->total_len = total_bytes; + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = NULL; + xfer->ff = ff; + xfer->total_len = total_bytes; uint16_t num_packets = (total_bytes / xfer->max_size); uint16_t const short_packet_size = total_bytes % xfer->max_size; // Zero-size packet is special case. - if ( short_packet_size > 0 || (total_bytes == 0) ) num_packets++; + if (short_packet_size > 0 || (total_bytes == 0)) num_packets++; // Schedule packets to be sent within interrupt edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); @@ -800,62 +699,52 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 return true; } -static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) -{ +static void dcd_edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { (void) rhport; - dwc2_regs_t *dwc2 = DWC2_REG(rhport); + dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); - if ( dir == TUSB_DIR_IN ) - { + if (dir == TUSB_DIR_IN) { dwc2_epin_t* epin = dwc2->epin; // Only disable currently enabled non-control endpoint - if ( (epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA) ) - { + if ((epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA)) { epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); - } - else - { + } else { // Stop transmitting packets and NAK IN xfers. epin[epnum].diepctl |= DIEPCTL_SNAK; - while ( (epin[epnum].diepint & DIEPINT_INEPNE) == 0 ) {} + while ((epin[epnum].diepint & DIEPINT_INEPNE) == 0) {} // Disable the endpoint. epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0); - while ( (epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0 ) {} + while ((epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0) {} epin[epnum].diepint = DIEPINT_EPDISD; } // Flush the FIFO, and wait until we have confirmed it cleared. dwc2->grstctl = ((epnum << GRSTCTL_TXFNUM_Pos) | GRSTCTL_TXFFLSH); - while ( (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0 ) {} - } - else - { + while ((dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0) {} + } else { dwc2_epout_t* epout = dwc2->epout; // Only disable currently enabled non-control endpoint - if ( (epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA) ) - { + if ((epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA)) { epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0; - } - else - { + } else { // Asserting GONAK is required to STALL an OUT endpoint. // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt // anyway, and it can't be cleared by user code. If this while loop never // finishes, we have bigger problems than just the stack. dwc2->dctl |= DCTL_SGONAK; - while ( (dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {} + while ((dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0) {} // Ditto here- disable the endpoint. epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); - while ( (epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0 ) {} + while ((epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0) {} epout[epnum].doepint = DOEPINT_EPDISD; @@ -868,55 +757,46 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) /** * Close an endpoint. */ -void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) -{ - dwc2_regs_t * dwc2 = DWC2_REG(rhport); +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); dcd_edpt_disable(rhport, ep_addr, false); // Update max_size xfer_status[epnum][dir].max_size = 0; // max_size = 0 marks a disabled EP - required for changing FIFO allocation - if (dir == TUSB_DIR_IN) - { + if (dir == TUSB_DIR_IN) { uint16_t const fifo_size = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos; uint16_t const fifo_start = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos; // For now only the last opened endpoint can be closed without fuss. - TU_ASSERT(fifo_start == _dwc2_controller[rhport].ep_fifo_size/4 - _allocated_fifo_words_tx,); + TU_ASSERT(fifo_start == _dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx,); _allocated_fifo_words_tx -= fifo_size; - } - else - { + } else { _out_ep_closed = true; // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty } } -void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) -{ +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { dcd_edpt_disable(rhport, ep_addr, true); } -void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) -{ +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { (void) rhport; - dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); // Clear stall and reset data toggle - if ( dir == TUSB_DIR_IN ) - { + if (dir == TUSB_DIR_IN) { dwc2->epin[epnum].diepctl &= ~DIEPCTL_STALL; dwc2->epin[epnum].diepctl |= DIEPCTL_SD0PID_SEVNFRM; - } - else - { + } else { dwc2->epout[epnum].doepctl &= ~DOEPCTL_STALL; dwc2->epout[epnum].doepctl |= DOEPCTL_SD0PID_SEVNFRM; } @@ -925,70 +805,63 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) /*------------------------------------------------------------------*/ // Read a single data packet from receive FIFO -static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len) -{ +static void read_fifo_packet(uint8_t rhport, uint8_t* dst, uint16_t len) { (void) rhport; - dwc2_regs_t * dwc2 = DWC2_REG(rhport); - volatile const uint32_t * rx_fifo = dwc2->fifo[0]; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + volatile const uint32_t* rx_fifo = dwc2->fifo[0]; // Reading full available 32 bit words from fifo uint16_t full_words = len >> 2; - while(full_words--) - { + while (full_words--) { tu_unaligned_write32(dst, *rx_fifo); dst += 4; } // Read the remaining 1-3 bytes from fifo uint8_t const bytes_rem = len & 0x03; - if ( bytes_rem != 0 ) - { + if (bytes_rem != 0) { uint32_t const tmp = *rx_fifo; dst[0] = tu_u32_byte0(tmp); - if ( bytes_rem > 1 ) dst[1] = tu_u32_byte1(tmp); - if ( bytes_rem > 2 ) dst[2] = tu_u32_byte2(tmp); + if (bytes_rem > 1) dst[1] = tu_u32_byte1(tmp); + if (bytes_rem > 2) dst[2] = tu_u32_byte2(tmp); } } // Write a single data packet to EPIN FIFO -static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const * src, uint16_t len) -{ +static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const* src, uint16_t len) { (void) rhport; - dwc2_regs_t * dwc2 = DWC2_REG(rhport); - volatile uint32_t * tx_fifo = dwc2->fifo[fifo_num]; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num]; // Pushing full available 32 bit words to fifo uint16_t full_words = len >> 2; - while(full_words--) - { + while (full_words--) { *tx_fifo = tu_unaligned_read32(src); src += 4; } // Write the remaining 1-3 bytes into fifo uint8_t const bytes_rem = len & 0x03; - if ( bytes_rem ) - { + if (bytes_rem) { uint32_t tmp_word = src[0]; - if ( bytes_rem > 1 ) tmp_word |= (src[1] << 8); - if ( bytes_rem > 2 ) tmp_word |= (src[2] << 16); + if (bytes_rem > 1) tmp_word |= (src[1] << 8); + if (bytes_rem > 2) tmp_word |= (src[2] << 16); *tx_fifo = tmp_word; } } -static void handle_rxflvl_irq(uint8_t rhport) -{ - dwc2_regs_t * dwc2 = DWC2_REG(rhport); - volatile uint32_t const * rx_fifo = dwc2->fifo[0]; +static void handle_rxflvl_irq(uint8_t rhport) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + volatile uint32_t const* rx_fifo = dwc2->fifo[0]; // Pop control word off FIFO uint32_t const ctl_word = dwc2->grxstsp; - uint8_t const pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk ) >> GRXSTSP_PKTSTS_Pos; - uint8_t const epnum = (ctl_word & GRXSTSP_EPNUM_Msk ) >> GRXSTSP_EPNUM_Pos; - uint16_t const bcnt = (ctl_word & GRXSTSP_BCNT_Msk ) >> GRXSTSP_BCNT_Pos; + uint8_t const pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; + uint8_t const epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; + uint16_t const bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; dwc2_epout_t* epout = &dwc2->epout[epnum]; @@ -1003,10 +876,10 @@ static void handle_rxflvl_irq(uint8_t rhport) // TU_LOG(DWC2_DEBUG, " daint = %08lX, doepint = %04X\r\n", (unsigned long) dwc2->daint, (unsigned int) epout->doepint); //#endif - switch ( pktsts ) - { + switch (pktsts) { // Global OUT NAK: do nothing - case GRXSTS_PKTSTS_GLOBALOUTNAK: break; + case GRXSTS_PKTSTS_GLOBALOUTNAK: + break; case GRXSTS_PKTSTS_SETUPRX: // Setup packet received @@ -1015,26 +888,22 @@ static void handle_rxflvl_irq(uint8_t rhport) // only the last one is valid. _setup_packet[0] = (*rx_fifo); _setup_packet[1] = (*rx_fifo); - break; + break; case GRXSTS_PKTSTS_SETUPDONE: // Setup packet done (Interrupt) epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); - break; + break; - case GRXSTS_PKTSTS_OUTRX: - { + case GRXSTS_PKTSTS_OUTRX: { // Out packet received - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); // Read packet off RxFIFO - if ( xfer->ff ) - { + if (xfer->ff) { // Ring buffer tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt); - } - else - { + } else { // Linear buffer read_fifo_packet(rhport, xfer->buffer, bcnt); @@ -1043,73 +912,64 @@ static void handle_rxflvl_irq(uint8_t rhport) } // Truncate transfer length in case of short packet - if ( bcnt < xfer->max_size ) - { + if (bcnt < xfer->max_size) { xfer->total_len -= (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; - if ( epnum == 0 ) - { + if (epnum == 0) { xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; ep0_pending[TUSB_DIR_OUT] = 0; } } } - break; + break; - // Out packet done (Interrupt) + // Out packet done (Interrupt) case GRXSTS_PKTSTS_OUTDONE: - // Occurred on STM32L47 with dwc2 version 3.10a but not found on other version like 2.80a or 3.30a - // May (or not) be 3.10a specific feature/bug or depending on MCU configuration - // XFRC complete is additionally generated when - // - setup packet is received - // - complete the data stage of control write is complete - if ((epnum == 0) && (bcnt == 0) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) - { - uint32_t doepint = epout->doepint; - - if (doepint & (DOEPINT_STPKTRX | DOEPINT_OTEPSPR)) - { - // skip this "no-data" transfer complete event - // Note: STPKTRX will be clear later by setup received handler - uint32_t clear_flags = DOEPINT_XFRC; - - if (doepint & DOEPINT_OTEPSPR) clear_flags |= DOEPINT_OTEPSPR; - - epout->doepint = clear_flags; - - // TU_LOG(DWC2_DEBUG, " FIX extra transfer complete on setup/data compete\r\n"); - } + // Occurred on STM32L47 with dwc2 version 3.10a but not found on other version like 2.80a or 3.30a + // May (or not) be 3.10a specific feature/bug or depending on MCU configuration + // XFRC complete is additionally generated when + // - setup packet is received + // - complete the data stage of control write is complete + if ((epnum == 0) && (bcnt == 0) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { + uint32_t doepint = epout->doepint; + + if (doepint & (DOEPINT_STPKTRX | DOEPINT_OTEPSPR)) { + // skip this "no-data" transfer complete event + // Note: STPKTRX will be clear later by setup received handler + uint32_t clear_flags = DOEPINT_XFRC; + + if (doepint & DOEPINT_OTEPSPR) clear_flags |= DOEPINT_OTEPSPR; + + epout->doepint = clear_flags; + + // TU_LOG(DWC2_DEBUG, " FIX extra transfer complete on setup/data compete\r\n"); } - break; + } + break; default: // Invalid TU_BREAKPOINT(); - break; + break; } } -static void handle_epout_irq (uint8_t rhport) -{ - dwc2_regs_t * dwc2 = DWC2_REG(rhport); +static void handle_epout_irq(uint8_t rhport) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; // DAINT for a given EP clears when DOEPINTx is cleared. // OEPINT will be cleared when DAINT's out bits are cleared. - for ( uint8_t n = 0; n < ep_count; n++ ) - { - if ( dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + n) ) - { + for (uint8_t n = 0; n < ep_count; n++) { + if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + n)) { dwc2_epout_t* epout = &dwc2->epout[n]; uint32_t const doepint = epout->doepint; // SETUP packet Setup Phase done. - if ( doepint & DOEPINT_STUP ) - { + if (doepint & DOEPINT_STUP) { uint32_t clear_flag = DOEPINT_STUP; // STPKTRX is only available for version from 3_00a - if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) - { + if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { clear_flag |= DOEPINT_STPKTRX; } @@ -1118,20 +978,16 @@ static void handle_epout_irq (uint8_t rhport) } // OUT XFER complete - if ( epout->doepint & DOEPINT_XFRC ) - { + if (epout->doepint & DOEPINT_XFRC) { epout->doepint = DOEPINT_XFRC; - xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); + xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); // EP0 can only handle one packet - if ( (n == 0) && ep0_pending[TUSB_DIR_OUT] ) - { + if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) { // Schedule another packet to be received. edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); - } - else - { + } else { dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); } } @@ -1139,40 +995,32 @@ static void handle_epout_irq (uint8_t rhport) } } -static void handle_epin_irq (uint8_t rhport) -{ - dwc2_regs_t * dwc2 = DWC2_REG(rhport); +static void handle_epin_irq(uint8_t rhport) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; - dwc2_epin_t* epin = dwc2->epin; + dwc2_epin_t* epin = dwc2->epin; // DAINT for a given EP clears when DIEPINTx is cleared. // IEPINT will be cleared when DAINT's out bits are cleared. - for ( uint8_t n = 0; n < ep_count; n++ ) - { - if ( dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n) ) - { + for (uint8_t n = 0; n < ep_count; n++) { + if (dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n)) { // IN XFER complete (entire xfer). - xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); + xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); - if ( epin[n].diepint & DIEPINT_XFRC ) - { + if (epin[n].diepint & DIEPINT_XFRC) { epin[n].diepint = DIEPINT_XFRC; // EP0 can only handle one packet - if ( (n == 0) && ep0_pending[TUSB_DIR_IN] ) - { + if ((n == 0) && ep0_pending[TUSB_DIR_IN]) { // Schedule another packet to be transmitted. edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); - } - else - { + } else { dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); } } // XFER FIFO empty - if ( (epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) ) - { + if ((epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n))) { // diepint's TXFE bit is read-only, software cannot clear it. // It will only be cleared by hardware when written bytes is more than // - 64 bytes or @@ -1181,8 +1029,7 @@ static void handle_epin_irq (uint8_t rhport) uint16_t remaining_packets = (epin[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos; // Process every single packet (only whole packets can be written to fifo) - for ( uint16_t i = 0; i < remaining_packets; i++ ) - { + for (uint16_t i = 0; i < remaining_packets; i++) { uint16_t const remaining_bytes = (epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos; // Packet can not be larger than ep max size @@ -1190,16 +1037,13 @@ static void handle_epin_irq (uint8_t rhport) // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current // EP has to be checked if the buffer can take another WHOLE packet - if ( packet_size > ((epin[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2) ) break; + if (packet_size > ((epin[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) break; // Push packet to Tx-FIFO - if ( xfer->ff ) - { - volatile uint32_t *tx_fifo = dwc2->fifo[n]; + if (xfer->ff) { + volatile uint32_t* tx_fifo = dwc2->fifo[n]; tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, packet_size); - } - else - { + } else { write_fifo_packet(rhport, n, xfer->buffer, packet_size); // Increment pointer to xfer data @@ -1208,8 +1052,7 @@ static void handle_epin_irq (uint8_t rhport) } // Turn off TXFE if all bytes are written. - if ( ((epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0 ) - { + if (((epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0) { dwc2->diepempmsk &= ~(1 << n); } } @@ -1217,55 +1060,49 @@ static void handle_epin_irq (uint8_t rhport) } } -void dcd_int_handler(uint8_t rhport) -{ - dwc2_regs_t *dwc2 = DWC2_REG(rhport); +void dcd_int_handler(uint8_t rhport) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint32_t const int_mask = dwc2->gintmsk; uint32_t const int_status = dwc2->gintsts & int_mask; - if(int_status & GINTSTS_USBRST) - { + if (int_status & GINTSTS_USBRST) { // USBRST is start of reset. dwc2->gintsts = GINTSTS_USBRST; bus_reset(rhport); } - if(int_status & GINTSTS_ENUMDNE) - { + if (int_status & GINTSTS_ENUMDNE) { // ENUMDNE is the end of reset where speed of the link is detected dwc2->gintsts = GINTSTS_ENUMDNE; tusb_speed_t speed; - switch ((dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos) - { + switch ((dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos) { case DSTS_ENUMSPD_HS: speed = TUSB_SPEED_HIGH; - break; + break; case DSTS_ENUMSPD_LS: speed = TUSB_SPEED_LOW; - break; + break; case DSTS_ENUMSPD_FS_HSPHY: case DSTS_ENUMSPD_FS: default: speed = TUSB_SPEED_FULL; - break; + break; } dcd_event_bus_reset(rhport, speed, true); } - if(int_status & GINTSTS_USBSUSP) - { + if (int_status & GINTSTS_USBSUSP) { dwc2->gintsts = GINTSTS_USBSUSP; dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } - if(int_status & GINTSTS_WKUINT) - { + if (int_status & GINTSTS_WKUINT) { dwc2->gintsts = GINTSTS_WKUINT; dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); } @@ -1273,30 +1110,24 @@ void dcd_int_handler(uint8_t rhport) // TODO check GINTSTS_DISCINT for disconnect detection // if(int_status & GINTSTS_DISCINT) - if(int_status & GINTSTS_OTGINT) - { + if (int_status & GINTSTS_OTGINT) { // OTG INT bit is read-only uint32_t const otg_int = dwc2->gotgint; - if (otg_int & GOTGINT_SEDET) - { + if (otg_int & GOTGINT_SEDET) { dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); } dwc2->gotgint = otg_int; } - if(int_status & GINTSTS_SOF) - { + if (int_status & GINTSTS_SOF) { dwc2->gotgint = GINTSTS_SOF; - if (_sof_en) - { + if (_sof_en) { uint32_t frame = (dwc2->dsts & (DSTS_FNSOF)) >> 8; dcd_event_sof(rhport, frame, true); - } - else - { + } else { // Disable SOF interrupt if SOF was not explicitly enabled. SOF was used for remote wakeup detection dwc2->gintmsk &= ~GINTMSK_SOFM; } @@ -1305,22 +1136,19 @@ void dcd_int_handler(uint8_t rhport) } // RxFIFO non-empty interrupt handling. - if(int_status & GINTSTS_RXFLVL) - { + if (int_status & GINTSTS_RXFLVL) { // RXFLVL bit is read-only // Mask out RXFLVL while reading data from FIFO dwc2->gintmsk &= ~GINTMSK_RXFLVLM; // Loop until all available packets were handled - do - { + do { handle_rxflvl_irq(rhport); - } while(dwc2->gotgint & GINTSTS_RXFLVL); + } while (dwc2->gotgint & GINTSTS_RXFLVL); // Manage RX FIFO size - if (_out_ep_closed) - { + if (_out_ep_closed) { update_grxfsiz(rhport); // Disable flag @@ -1331,15 +1159,13 @@ void dcd_int_handler(uint8_t rhport) } // OUT endpoint interrupt handling. - if(int_status & GINTSTS_OEPINT) - { + if (int_status & GINTSTS_OEPINT) { // OEPINT is read-only, clear using DOEPINTn handle_epout_irq(rhport); } // IN endpoint interrupt handling. - if(int_status & GINTSTS_IEPINT) - { + if (int_status & GINTSTS_IEPINT) { // IEPINT bit read-only, clear using DIEPINTn handle_epin_irq(rhport); } -- cgit v1.3.1 From 9f0223dccd9992f936054bae3c6256280af7f26a Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 31 Oct 2023 10:58:15 +0700 Subject: minor clean up --- hw/bsp/stm32f7/family.c | 2 +- src/portable/synopsys/dwc2/dwc2_type.h | 1790 ++++++++++++++++---------------- 2 files changed, 911 insertions(+), 881 deletions(-) (limited to 'src') diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c index b504c435a..18cee073d 100644 --- a/hw/bsp/stm32f7/family.c +++ b/hw/bsp/stm32f7/family.c @@ -199,7 +199,7 @@ void board_init(void) { __HAL_RCC_OTGPHYC_CLK_ENABLE(); #else - // MUC with external ULPI PHY + // MCU with external ULPI PHY /* ULPI CLK */ GPIO_InitStruct.Pin = GPIO_PIN_5; diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 6516882da..c15771237 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -32,7 +32,7 @@ typedef struct uint32_t ep_fifo_size; }dwc2_controller_t; -/* DWC OTG HW Release versions */ +// DWC OTG HW Release versions #define DWC2_CORE_REV_2_71a 0x4f54271a #define DWC2_CORE_REV_2_72a 0x4f54272a #define DWC2_CORE_REV_2_80a 0x4f54280a @@ -49,7 +49,7 @@ typedef struct #define DWC2_HS_IOT_REV_1_00a 0x5532100a #define DWC2_CORE_REV_MASK 0x0000ffff -/* DWC OTG HW Core ID */ +// DWC OTG HW Core ID #define DWC2_OTG_ID 0x4f540000 #define DWC2_FS_IOT_ID 0x55310000 #define DWC2_HS_IOT_ID 0x55320000 @@ -58,13 +58,13 @@ typedef struct // HS PHY typedef struct { - volatile uint32_t HS_PHYC_PLL; // This register is used to control the PLL of the HS PHY. 000h */ - volatile uint32_t Reserved04; // Reserved 004h */ - volatile uint32_t Reserved08; // Reserved 008h */ - volatile uint32_t HS_PHYC_TUNE; // This register is used to control the tuning interface of the High Speed PHY. 00Ch */ - volatile uint32_t Reserved10; // Reserved 010h */ - volatile uint32_t Reserved14; // Reserved 014h */ - volatile uint32_t HS_PHYC_LDO; // This register is used to control the regulator (LDO). 018h */ + volatile uint32_t HS_PHYC_PLL; // 000h This register is used to control the PLL of the HS PHY. + volatile uint32_t Reserved04; // 004h Reserved + volatile uint32_t Reserved08; // 008h Reserved + volatile uint32_t HS_PHYC_TUNE; // 00Ch This register is used to control the tuning interface of the High Speed PHY. + volatile uint32_t Reserved10; // 010h Reserved + volatile uint32_t Reserved14; // 014h Reserved + volatile uint32_t HS_PHYC_LDO; // 018h This register is used to control the regulator (LDO). } HS_PHYC_GlobalTypeDef; #endif @@ -299,103 +299,103 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); /******************** Bit definition for GOTGCTL register ********************/ #define GOTGCTL_SRQSCS_Pos (0U) -#define GOTGCTL_SRQSCS_Msk (0x1UL << GOTGCTL_SRQSCS_Pos) // 0x00000001 */ -#define GOTGCTL_SRQSCS GOTGCTL_SRQSCS_Msk // Session request success */ +#define GOTGCTL_SRQSCS_Msk (0x1UL << GOTGCTL_SRQSCS_Pos) // 0x00000001 +#define GOTGCTL_SRQSCS GOTGCTL_SRQSCS_Msk // Session request success #define GOTGCTL_SRQ_Pos (1U) -#define GOTGCTL_SRQ_Msk (0x1UL << GOTGCTL_SRQ_Pos) // 0x00000002 */ -#define GOTGCTL_SRQ GOTGCTL_SRQ_Msk // Session request */ +#define GOTGCTL_SRQ_Msk (0x1UL << GOTGCTL_SRQ_Pos) // 0x00000002 +#define GOTGCTL_SRQ GOTGCTL_SRQ_Msk // Session request #define GOTGCTL_VBVALOEN_Pos (2U) -#define GOTGCTL_VBVALOEN_Msk (0x1UL << GOTGCTL_VBVALOEN_Pos) // 0x00000004 */ -#define GOTGCTL_VBVALOEN GOTGCTL_VBVALOEN_Msk // VBUS valid override enable */ +#define GOTGCTL_VBVALOEN_Msk (0x1UL << GOTGCTL_VBVALOEN_Pos) // 0x00000004 +#define GOTGCTL_VBVALOEN GOTGCTL_VBVALOEN_Msk // VBUS valid override enable #define GOTGCTL_VBVALOVAL_Pos (3U) -#define GOTGCTL_VBVALOVAL_Msk (0x1UL << GOTGCTL_VBVALOVAL_Pos) // 0x00000008 */ -#define GOTGCTL_VBVALOVAL GOTGCTL_VBVALOVAL_Msk // VBUS valid override value */ +#define GOTGCTL_VBVALOVAL_Msk (0x1UL << GOTGCTL_VBVALOVAL_Pos) // 0x00000008 +#define GOTGCTL_VBVALOVAL GOTGCTL_VBVALOVAL_Msk // VBUS valid override value #define GOTGCTL_AVALOEN_Pos (4U) -#define GOTGCTL_AVALOEN_Msk (0x1UL << GOTGCTL_AVALOEN_Pos) // 0x00000010 */ -#define GOTGCTL_AVALOEN GOTGCTL_AVALOEN_Msk // A-peripheral session valid override enable */ +#define GOTGCTL_AVALOEN_Msk (0x1UL << GOTGCTL_AVALOEN_Pos) // 0x00000010 +#define GOTGCTL_AVALOEN GOTGCTL_AVALOEN_Msk // A-peripheral session valid override enable #define GOTGCTL_AVALOVAL_Pos (5U) -#define GOTGCTL_AVALOVAL_Msk (0x1UL << GOTGCTL_AVALOVAL_Pos) // 0x00000020 */ -#define GOTGCTL_AVALOVAL GOTGCTL_AVALOVAL_Msk // A-peripheral session valid override value */ +#define GOTGCTL_AVALOVAL_Msk (0x1UL << GOTGCTL_AVALOVAL_Pos) // 0x00000020 +#define GOTGCTL_AVALOVAL GOTGCTL_AVALOVAL_Msk // A-peripheral session valid override value #define GOTGCTL_BVALOEN_Pos (6U) -#define GOTGCTL_BVALOEN_Msk (0x1UL << GOTGCTL_BVALOEN_Pos) // 0x00000040 */ -#define GOTGCTL_BVALOEN GOTGCTL_BVALOEN_Msk // B-peripheral session valid override enable */ +#define GOTGCTL_BVALOEN_Msk (0x1UL << GOTGCTL_BVALOEN_Pos) // 0x00000040 +#define GOTGCTL_BVALOEN GOTGCTL_BVALOEN_Msk // B-peripheral session valid override enable #define GOTGCTL_BVALOVAL_Pos (7U) -#define GOTGCTL_BVALOVAL_Msk (0x1UL << GOTGCTL_BVALOVAL_Pos) // 0x00000080 */ -#define GOTGCTL_BVALOVAL GOTGCTL_BVALOVAL_Msk // B-peripheral session valid override value */ +#define GOTGCTL_BVALOVAL_Msk (0x1UL << GOTGCTL_BVALOVAL_Pos) // 0x00000080 +#define GOTGCTL_BVALOVAL GOTGCTL_BVALOVAL_Msk // B-peripheral session valid override value #define GOTGCTL_HNGSCS_Pos (8U) -#define GOTGCTL_HNGSCS_Msk (0x1UL << GOTGCTL_HNGSCS_Pos) // 0x00000100 */ -#define GOTGCTL_HNGSCS GOTGCTL_HNGSCS_Msk // Host set HNP enable */ +#define GOTGCTL_HNGSCS_Msk (0x1UL << GOTGCTL_HNGSCS_Pos) // 0x00000100 +#define GOTGCTL_HNGSCS GOTGCTL_HNGSCS_Msk // Host set HNP enable #define GOTGCTL_HNPRQ_Pos (9U) -#define GOTGCTL_HNPRQ_Msk (0x1UL << GOTGCTL_HNPRQ_Pos) // 0x00000200 */ -#define GOTGCTL_HNPRQ GOTGCTL_HNPRQ_Msk // HNP request */ +#define GOTGCTL_HNPRQ_Msk (0x1UL << GOTGCTL_HNPRQ_Pos) // 0x00000200 +#define GOTGCTL_HNPRQ GOTGCTL_HNPRQ_Msk // HNP request #define GOTGCTL_HSHNPEN_Pos (10U) -#define GOTGCTL_HSHNPEN_Msk (0x1UL << GOTGCTL_HSHNPEN_Pos) // 0x00000400 */ -#define GOTGCTL_HSHNPEN GOTGCTL_HSHNPEN_Msk // Host set HNP enable */ +#define GOTGCTL_HSHNPEN_Msk (0x1UL << GOTGCTL_HSHNPEN_Pos) // 0x00000400 +#define GOTGCTL_HSHNPEN GOTGCTL_HSHNPEN_Msk // Host set HNP enable #define GOTGCTL_DHNPEN_Pos (11U) -#define GOTGCTL_DHNPEN_Msk (0x1UL << GOTGCTL_DHNPEN_Pos) // 0x00000800 */ -#define GOTGCTL_DHNPEN GOTGCTL_DHNPEN_Msk // Device HNP enabled */ +#define GOTGCTL_DHNPEN_Msk (0x1UL << GOTGCTL_DHNPEN_Pos) // 0x00000800 +#define GOTGCTL_DHNPEN GOTGCTL_DHNPEN_Msk // Device HNP enabled #define GOTGCTL_EHEN_Pos (12U) -#define GOTGCTL_EHEN_Msk (0x1UL << GOTGCTL_EHEN_Pos) // 0x00001000 */ -#define GOTGCTL_EHEN GOTGCTL_EHEN_Msk // Embedded host enable */ +#define GOTGCTL_EHEN_Msk (0x1UL << GOTGCTL_EHEN_Pos) // 0x00001000 +#define GOTGCTL_EHEN GOTGCTL_EHEN_Msk // Embedded host enable #define GOTGCTL_CIDSTS_Pos (16U) -#define GOTGCTL_CIDSTS_Msk (0x1UL << GOTGCTL_CIDSTS_Pos) // 0x00010000 */ -#define GOTGCTL_CIDSTS GOTGCTL_CIDSTS_Msk // Connector ID status */ +#define GOTGCTL_CIDSTS_Msk (0x1UL << GOTGCTL_CIDSTS_Pos) // 0x00010000 +#define GOTGCTL_CIDSTS GOTGCTL_CIDSTS_Msk // Connector ID status #define GOTGCTL_DBCT_Pos (17U) -#define GOTGCTL_DBCT_Msk (0x1UL << GOTGCTL_DBCT_Pos) // 0x00020000 */ -#define GOTGCTL_DBCT GOTGCTL_DBCT_Msk // Long/short debounce time */ +#define GOTGCTL_DBCT_Msk (0x1UL << GOTGCTL_DBCT_Pos) // 0x00020000 +#define GOTGCTL_DBCT GOTGCTL_DBCT_Msk // Long/short debounce time #define GOTGCTL_ASVLD_Pos (18U) -#define GOTGCTL_ASVLD_Msk (0x1UL << GOTGCTL_ASVLD_Pos) // 0x00040000 */ -#define GOTGCTL_ASVLD GOTGCTL_ASVLD_Msk // A-session valid */ +#define GOTGCTL_ASVLD_Msk (0x1UL << GOTGCTL_ASVLD_Pos) // 0x00040000 +#define GOTGCTL_ASVLD GOTGCTL_ASVLD_Msk // A-session valid #define GOTGCTL_BSESVLD_Pos (19U) -#define GOTGCTL_BSESVLD_Msk (0x1UL << GOTGCTL_BSESVLD_Pos) // 0x00080000 */ -#define GOTGCTL_BSESVLD GOTGCTL_BSESVLD_Msk // B-session valid */ +#define GOTGCTL_BSESVLD_Msk (0x1UL << GOTGCTL_BSESVLD_Pos) // 0x00080000 +#define GOTGCTL_BSESVLD GOTGCTL_BSESVLD_Msk // B-session valid #define GOTGCTL_OTGVER_Pos (20U) -#define GOTGCTL_OTGVER_Msk (0x1UL << GOTGCTL_OTGVER_Pos) // 0x00100000 */ -#define GOTGCTL_OTGVER GOTGCTL_OTGVER_Msk // OTG version */ +#define GOTGCTL_OTGVER_Msk (0x1UL << GOTGCTL_OTGVER_Pos) // 0x00100000 +#define GOTGCTL_OTGVER GOTGCTL_OTGVER_Msk // OTG version /******************** Bit definition for HCFG register ********************/ #define HCFG_FSLSPCS_Pos (0U) -#define HCFG_FSLSPCS_Msk (0x3UL << HCFG_FSLSPCS_Pos) // 0x00000003 */ -#define HCFG_FSLSPCS HCFG_FSLSPCS_Msk // FS/LS PHY clock select */ -#define HCFG_FSLSPCS_0 (0x1UL << HCFG_FSLSPCS_Pos) // 0x00000001 */ -#define HCFG_FSLSPCS_1 (0x2UL << HCFG_FSLSPCS_Pos) // 0x00000002 */ +#define HCFG_FSLSPCS_Msk (0x3UL << HCFG_FSLSPCS_Pos) // 0x00000003 +#define HCFG_FSLSPCS HCFG_FSLSPCS_Msk // FS/LS PHY clock select +#define HCFG_FSLSPCS_0 (0x1UL << HCFG_FSLSPCS_Pos) // 0x00000001 +#define HCFG_FSLSPCS_1 (0x2UL << HCFG_FSLSPCS_Pos) // 0x00000002 #define HCFG_FSLSS_Pos (2U) -#define HCFG_FSLSS_Msk (0x1UL << HCFG_FSLSS_Pos) // 0x00000004 */ -#define HCFG_FSLSS HCFG_FSLSS_Msk // FS- and LS-only support */ +#define HCFG_FSLSS_Msk (0x1UL << HCFG_FSLSS_Pos) // 0x00000004 +#define HCFG_FSLSS HCFG_FSLSS_Msk // FS- and LS-only support /******************** Bit definition for PCGCR register ********************/ #define PCGCR_STPPCLK_Pos (0U) -#define PCGCR_STPPCLK_Msk (0x1UL << PCGCR_STPPCLK_Pos) // 0x00000001 */ -#define PCGCR_STPPCLK PCGCR_STPPCLK_Msk // Stop PHY clock */ +#define PCGCR_STPPCLK_Msk (0x1UL << PCGCR_STPPCLK_Pos) // 0x00000001 +#define PCGCR_STPPCLK PCGCR_STPPCLK_Msk // Stop PHY clock #define PCGCR_GATEHCLK_Pos (1U) -#define PCGCR_GATEHCLK_Msk (0x1UL << PCGCR_GATEHCLK_Pos) // 0x00000002 */ -#define PCGCR_GATEHCLK PCGCR_GATEHCLK_Msk // Gate HCLK */ +#define PCGCR_GATEHCLK_Msk (0x1UL << PCGCR_GATEHCLK_Pos) // 0x00000002 +#define PCGCR_GATEHCLK PCGCR_GATEHCLK_Msk // Gate HCLK #define PCGCR_PHYSUSP_Pos (4U) -#define PCGCR_PHYSUSP_Msk (0x1UL << PCGCR_PHYSUSP_Pos) // 0x00000010 */ -#define PCGCR_PHYSUSP PCGCR_PHYSUSP_Msk // PHY suspended */ +#define PCGCR_PHYSUSP_Msk (0x1UL << PCGCR_PHYSUSP_Pos) // 0x00000010 +#define PCGCR_PHYSUSP PCGCR_PHYSUSP_Msk // PHY suspended /******************** Bit definition for GOTGINT register ********************/ #define GOTGINT_SEDET_Pos (2U) -#define GOTGINT_SEDET_Msk (0x1UL << GOTGINT_SEDET_Pos) // 0x00000004 */ -#define GOTGINT_SEDET GOTGINT_SEDET_Msk // Session end detected */ +#define GOTGINT_SEDET_Msk (0x1UL << GOTGINT_SEDET_Pos) // 0x00000004 +#define GOTGINT_SEDET GOTGINT_SEDET_Msk // Session end detected #define GOTGINT_SRSSCHG_Pos (8U) -#define GOTGINT_SRSSCHG_Msk (0x1UL << GOTGINT_SRSSCHG_Pos) // 0x00000100 */ -#define GOTGINT_SRSSCHG GOTGINT_SRSSCHG_Msk // Session request success status change */ +#define GOTGINT_SRSSCHG_Msk (0x1UL << GOTGINT_SRSSCHG_Pos) // 0x00000100 +#define GOTGINT_SRSSCHG GOTGINT_SRSSCHG_Msk // Session request success status change #define GOTGINT_HNSSCHG_Pos (9U) -#define GOTGINT_HNSSCHG_Msk (0x1UL << GOTGINT_HNSSCHG_Pos) // 0x00000200 */ -#define GOTGINT_HNSSCHG GOTGINT_HNSSCHG_Msk // Host negotiation success status change */ +#define GOTGINT_HNSSCHG_Msk (0x1UL << GOTGINT_HNSSCHG_Pos) // 0x00000200 +#define GOTGINT_HNSSCHG GOTGINT_HNSSCHG_Msk // Host negotiation success status change #define GOTGINT_HNGDET_Pos (17U) -#define GOTGINT_HNGDET_Msk (0x1UL << GOTGINT_HNGDET_Pos) // 0x00020000 */ -#define GOTGINT_HNGDET GOTGINT_HNGDET_Msk // Host negotiation detected */ +#define GOTGINT_HNGDET_Msk (0x1UL << GOTGINT_HNGDET_Pos) // 0x00020000 +#define GOTGINT_HNGDET GOTGINT_HNGDET_Msk // Host negotiation detected #define GOTGINT_ADTOCHG_Pos (18U) -#define GOTGINT_ADTOCHG_Msk (0x1UL << GOTGINT_ADTOCHG_Pos) // 0x00040000 */ -#define GOTGINT_ADTOCHG GOTGINT_ADTOCHG_Msk // A-device timeout change */ +#define GOTGINT_ADTOCHG_Msk (0x1UL << GOTGINT_ADTOCHG_Pos) // 0x00040000 +#define GOTGINT_ADTOCHG GOTGINT_ADTOCHG_Msk // A-device timeout change #define GOTGINT_DBCDNE_Pos (19U) -#define GOTGINT_DBCDNE_Msk (0x1UL << GOTGINT_DBCDNE_Pos) // 0x00080000 */ -#define GOTGINT_DBCDNE GOTGINT_DBCDNE_Msk // Debounce done */ +#define GOTGINT_DBCDNE_Msk (0x1UL << GOTGINT_DBCDNE_Pos) // 0x00080000 +#define GOTGINT_DBCDNE GOTGINT_DBCDNE_Msk // Debounce done #define GOTGINT_IDCHNG_Pos (20U) -#define GOTGINT_IDCHNG_Msk (0x1UL << GOTGINT_IDCHNG_Pos) // 0x00100000 */ -#define GOTGINT_IDCHNG GOTGINT_IDCHNG_Msk // Change in ID pin input value */ +#define GOTGINT_IDCHNG_Msk (0x1UL << GOTGINT_IDCHNG_Pos) // 0x00100000 +#define GOTGINT_IDCHNG GOTGINT_IDCHNG_Msk // Change in ID pin input value /******************** Bit definition for DCFG register ********************/ #define DCFG_DSPD_Pos (0U) @@ -406,92 +406,92 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DCFG_DSPD_FS 3 // Fullspeed on FS PHY #define DCFG_NZLSOHSK_Pos (2U) -#define DCFG_NZLSOHSK_Msk (0x1UL << DCFG_NZLSOHSK_Pos) // 0x00000004 */ -#define DCFG_NZLSOHSK DCFG_NZLSOHSK_Msk // Nonzero-length status OUT handshake */ +#define DCFG_NZLSOHSK_Msk (0x1UL << DCFG_NZLSOHSK_Pos) // 0x00000004 +#define DCFG_NZLSOHSK DCFG_NZLSOHSK_Msk // Nonzero-length status OUT handshake #define DCFG_DAD_Pos (4U) -#define DCFG_DAD_Msk (0x7FUL << DCFG_DAD_Pos) // 0x000007F0 */ -#define DCFG_DAD DCFG_DAD_Msk // Device address */ -#define DCFG_DAD_0 (0x01UL << DCFG_DAD_Pos) // 0x00000010 */ -#define DCFG_DAD_1 (0x02UL << DCFG_DAD_Pos) // 0x00000020 */ -#define DCFG_DAD_2 (0x04UL << DCFG_DAD_Pos) // 0x00000040 */ -#define DCFG_DAD_3 (0x08UL << DCFG_DAD_Pos) // 0x00000080 */ -#define DCFG_DAD_4 (0x10UL << DCFG_DAD_Pos) // 0x00000100 */ -#define DCFG_DAD_5 (0x20UL << DCFG_DAD_Pos) // 0x00000200 */ -#define DCFG_DAD_6 (0x40UL << DCFG_DAD_Pos) // 0x00000400 */ +#define DCFG_DAD_Msk (0x7FUL << DCFG_DAD_Pos) // 0x000007F0 +#define DCFG_DAD DCFG_DAD_Msk // Device address +#define DCFG_DAD_0 (0x01UL << DCFG_DAD_Pos) // 0x00000010 +#define DCFG_DAD_1 (0x02UL << DCFG_DAD_Pos) // 0x00000020 +#define DCFG_DAD_2 (0x04UL << DCFG_DAD_Pos) // 0x00000040 +#define DCFG_DAD_3 (0x08UL << DCFG_DAD_Pos) // 0x00000080 +#define DCFG_DAD_4 (0x10UL << DCFG_DAD_Pos) // 0x00000100 +#define DCFG_DAD_5 (0x20UL << DCFG_DAD_Pos) // 0x00000200 +#define DCFG_DAD_6 (0x40UL << DCFG_DAD_Pos) // 0x00000400 #define DCFG_PFIVL_Pos (11U) -#define DCFG_PFIVL_Msk (0x3UL << DCFG_PFIVL_Pos) // 0x00001800 */ -#define DCFG_PFIVL DCFG_PFIVL_Msk // Periodic (micro)frame interval */ -#define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) // 0x00000800 */ -#define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) // 0x00001000 */ +#define DCFG_PFIVL_Msk (0x3UL << DCFG_PFIVL_Pos) // 0x00001800 +#define DCFG_PFIVL DCFG_PFIVL_Msk // Periodic (micro)frame interval +#define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) // 0x00000800 +#define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) // 0x00001000 #define DCFG_XCVRDLY_Pos (14U) -#define DCFG_XCVRDLY_Msk (0x1UL << DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define DCFG_XCVRDLY_Msk (0x1UL << DCFG_XCVRDLY_Pos) // 0x00004000 #define DCFG_XCVRDLY DCFG_XCVRDLY_Msk // Enables delay between xcvr_sel and txvalid during device chirp #define DCFG_PERSCHIVL_Pos (24U) -#define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) // 0x03000000 */ -#define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk // Periodic scheduling interval */ -#define DCFG_PERSCHIVL_0 (0x1UL << DCFG_PERSCHIVL_Pos) // 0x01000000 */ -#define DCFG_PERSCHIVL_1 (0x2UL << DCFG_PERSCHIVL_Pos) // 0x02000000 */ +#define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) // 0x03000000 +#define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk // Periodic scheduling interval +#define DCFG_PERSCHIVL_0 (0x1UL << DCFG_PERSCHIVL_Pos) // 0x01000000 +#define DCFG_PERSCHIVL_1 (0x2UL << DCFG_PERSCHIVL_Pos) // 0x02000000 /******************** Bit definition for DCTL register ********************/ #define DCTL_RWUSIG_Pos (0U) -#define DCTL_RWUSIG_Msk (0x1UL << DCTL_RWUSIG_Pos) // 0x00000001 */ -#define DCTL_RWUSIG DCTL_RWUSIG_Msk // Remote wakeup signaling */ +#define DCTL_RWUSIG_Msk (0x1UL << DCTL_RWUSIG_Pos) // 0x00000001 +#define DCTL_RWUSIG DCTL_RWUSIG_Msk // Remote wakeup signaling #define DCTL_SDIS_Pos (1U) -#define DCTL_SDIS_Msk (0x1UL << DCTL_SDIS_Pos) // 0x00000002 */ -#define DCTL_SDIS DCTL_SDIS_Msk // Soft disconnect */ +#define DCTL_SDIS_Msk (0x1UL << DCTL_SDIS_Pos) // 0x00000002 +#define DCTL_SDIS DCTL_SDIS_Msk // Soft disconnect #define DCTL_GINSTS_Pos (2U) -#define DCTL_GINSTS_Msk (0x1UL << DCTL_GINSTS_Pos) // 0x00000004 */ -#define DCTL_GINSTS DCTL_GINSTS_Msk // Global IN NAK status */ +#define DCTL_GINSTS_Msk (0x1UL << DCTL_GINSTS_Pos) // 0x00000004 +#define DCTL_GINSTS DCTL_GINSTS_Msk // Global IN NAK status #define DCTL_GONSTS_Pos (3U) -#define DCTL_GONSTS_Msk (0x1UL << DCTL_GONSTS_Pos) // 0x00000008 */ -#define DCTL_GONSTS DCTL_GONSTS_Msk // Global OUT NAK status */ +#define DCTL_GONSTS_Msk (0x1UL << DCTL_GONSTS_Pos) // 0x00000008 +#define DCTL_GONSTS DCTL_GONSTS_Msk // Global OUT NAK status #define DCTL_TCTL_Pos (4U) -#define DCTL_TCTL_Msk (0x7UL << DCTL_TCTL_Pos) // 0x00000070 */ -#define DCTL_TCTL DCTL_TCTL_Msk // Test control */ -#define DCTL_TCTL_0 (0x1UL << DCTL_TCTL_Pos) // 0x00000010 */ -#define DCTL_TCTL_1 (0x2UL << DCTL_TCTL_Pos) // 0x00000020 */ -#define DCTL_TCTL_2 (0x4UL << DCTL_TCTL_Pos) // 0x00000040 */ +#define DCTL_TCTL_Msk (0x7UL << DCTL_TCTL_Pos) // 0x00000070 +#define DCTL_TCTL DCTL_TCTL_Msk // Test control +#define DCTL_TCTL_0 (0x1UL << DCTL_TCTL_Pos) // 0x00000010 +#define DCTL_TCTL_1 (0x2UL << DCTL_TCTL_Pos) // 0x00000020 +#define DCTL_TCTL_2 (0x4UL << DCTL_TCTL_Pos) // 0x00000040 #define DCTL_SGINAK_Pos (7U) -#define DCTL_SGINAK_Msk (0x1UL << DCTL_SGINAK_Pos) // 0x00000080 */ -#define DCTL_SGINAK DCTL_SGINAK_Msk // Set global IN NAK */ +#define DCTL_SGINAK_Msk (0x1UL << DCTL_SGINAK_Pos) // 0x00000080 +#define DCTL_SGINAK DCTL_SGINAK_Msk // Set global IN NAK #define DCTL_CGINAK_Pos (8U) -#define DCTL_CGINAK_Msk (0x1UL << DCTL_CGINAK_Pos) // 0x00000100 */ -#define DCTL_CGINAK DCTL_CGINAK_Msk // Clear global IN NAK */ +#define DCTL_CGINAK_Msk (0x1UL << DCTL_CGINAK_Pos) // 0x00000100 +#define DCTL_CGINAK DCTL_CGINAK_Msk // Clear global IN NAK #define DCTL_SGONAK_Pos (9U) -#define DCTL_SGONAK_Msk (0x1UL << DCTL_SGONAK_Pos) // 0x00000200 */ -#define DCTL_SGONAK DCTL_SGONAK_Msk // Set global OUT NAK */ +#define DCTL_SGONAK_Msk (0x1UL << DCTL_SGONAK_Pos) // 0x00000200 +#define DCTL_SGONAK DCTL_SGONAK_Msk // Set global OUT NAK #define DCTL_CGONAK_Pos (10U) -#define DCTL_CGONAK_Msk (0x1UL << DCTL_CGONAK_Pos) // 0x00000400 */ -#define DCTL_CGONAK DCTL_CGONAK_Msk // Clear global OUT NAK */ +#define DCTL_CGONAK_Msk (0x1UL << DCTL_CGONAK_Pos) // 0x00000400 +#define DCTL_CGONAK DCTL_CGONAK_Msk // Clear global OUT NAK #define DCTL_POPRGDNE_Pos (11U) -#define DCTL_POPRGDNE_Msk (0x1UL << DCTL_POPRGDNE_Pos) // 0x00000800 */ -#define DCTL_POPRGDNE DCTL_POPRGDNE_Msk // Power-on programming done */ +#define DCTL_POPRGDNE_Msk (0x1UL << DCTL_POPRGDNE_Pos) // 0x00000800 +#define DCTL_POPRGDNE DCTL_POPRGDNE_Msk // Power-on programming done /******************** Bit definition for HFIR register ********************/ #define HFIR_FRIVL_Pos (0U) -#define HFIR_FRIVL_Msk (0xFFFFUL << HFIR_FRIVL_Pos) // 0x0000FFFF */ -#define HFIR_FRIVL HFIR_FRIVL_Msk // Frame interval */ +#define HFIR_FRIVL_Msk (0xFFFFUL << HFIR_FRIVL_Pos) // 0x0000FFFF +#define HFIR_FRIVL HFIR_FRIVL_Msk // Frame interval /******************** Bit definition for HFNUM register ********************/ #define HFNUM_FRNUM_Pos (0U) -#define HFNUM_FRNUM_Msk (0xFFFFUL << HFNUM_FRNUM_Pos) // 0x0000FFFF */ -#define HFNUM_FRNUM HFNUM_FRNUM_Msk // Frame number */ +#define HFNUM_FRNUM_Msk (0xFFFFUL << HFNUM_FRNUM_Pos) // 0x0000FFFF +#define HFNUM_FRNUM HFNUM_FRNUM_Msk // Frame number #define HFNUM_FTREM_Pos (16U) -#define HFNUM_FTREM_Msk (0xFFFFUL << HFNUM_FTREM_Pos) // 0xFFFF0000 */ -#define HFNUM_FTREM HFNUM_FTREM_Msk // Frame time remaining */ +#define HFNUM_FTREM_Msk (0xFFFFUL << HFNUM_FTREM_Pos) // 0xFFFF0000 +#define HFNUM_FTREM HFNUM_FTREM_Msk // Frame time remaining /******************** Bit definition for DSTS register ********************/ #define DSTS_SUSPSTS_Pos (0U) -#define DSTS_SUSPSTS_Msk (0x1UL << DSTS_SUSPSTS_Pos) // 0x00000001 */ -#define DSTS_SUSPSTS DSTS_SUSPSTS_Msk // Suspend status */ +#define DSTS_SUSPSTS_Msk (0x1UL << DSTS_SUSPSTS_Pos) // 0x00000001 +#define DSTS_SUSPSTS DSTS_SUSPSTS_Msk // Suspend status #define DSTS_ENUMSPD_Pos (1U) -#define DSTS_ENUMSPD_Msk (0x3UL << DSTS_ENUMSPD_Pos) // 0x00000006 */ -#define DSTS_ENUMSPD DSTS_ENUMSPD_Msk // Enumerated speed */ +#define DSTS_ENUMSPD_Msk (0x3UL << DSTS_ENUMSPD_Pos) // 0x00000006 +#define DSTS_ENUMSPD DSTS_ENUMSPD_Msk // Enumerated speed #define DSTS_ENUMSPD_HS 0 // Highspeed #define DSTS_ENUMSPD_FS_HSPHY 1 // Fullspeed on HS PHY #define DSTS_ENUMSPD_LS 2 // Lowspeed @@ -499,427 +499,427 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DSTS_EERR_Pos (3U) -#define DSTS_EERR_Msk (0x1UL << DSTS_EERR_Pos) // 0x00000008 */ -#define DSTS_EERR DSTS_EERR_Msk // Erratic error */ +#define DSTS_EERR_Msk (0x1UL << DSTS_EERR_Pos) // 0x00000008 +#define DSTS_EERR DSTS_EERR_Msk // Erratic error #define DSTS_FNSOF_Pos (8U) -#define DSTS_FNSOF_Msk (0x3FFFUL << DSTS_FNSOF_Pos) // 0x003FFF00 */ -#define DSTS_FNSOF DSTS_FNSOF_Msk // Frame number of the received SOF */ +#define DSTS_FNSOF_Msk (0x3FFFUL << DSTS_FNSOF_Pos) // 0x003FFF00 +#define DSTS_FNSOF DSTS_FNSOF_Msk // Frame number of the received SOF /******************** Bit definition for GAHBCFG register ********************/ #define GAHBCFG_GINT_Pos (0U) -#define GAHBCFG_GINT_Msk (0x1UL << GAHBCFG_GINT_Pos) // 0x00000001 */ -#define GAHBCFG_GINT GAHBCFG_GINT_Msk // Global interrupt mask */ +#define GAHBCFG_GINT_Msk (0x1UL << GAHBCFG_GINT_Pos) // 0x00000001 +#define GAHBCFG_GINT GAHBCFG_GINT_Msk // Global interrupt mask #define GAHBCFG_HBSTLEN_Pos (1U) -#define GAHBCFG_HBSTLEN_Msk (0xFUL << GAHBCFG_HBSTLEN_Pos) // 0x0000001E */ -#define GAHBCFG_HBSTLEN GAHBCFG_HBSTLEN_Msk // Burst length/type */ -#define GAHBCFG_HBSTLEN_0 (0x0UL << GAHBCFG_HBSTLEN_Pos) // Single */ -#define GAHBCFG_HBSTLEN_1 (0x1UL << GAHBCFG_HBSTLEN_Pos) // INCR */ -#define GAHBCFG_HBSTLEN_2 (0x3UL << GAHBCFG_HBSTLEN_Pos) // INCR4 */ -#define GAHBCFG_HBSTLEN_3 (0x5UL << GAHBCFG_HBSTLEN_Pos) // INCR8 */ -#define GAHBCFG_HBSTLEN_4 (0x7UL << GAHBCFG_HBSTLEN_Pos) // INCR16 */ +#define GAHBCFG_HBSTLEN_Msk (0xFUL << GAHBCFG_HBSTLEN_Pos) // 0x0000001E +#define GAHBCFG_HBSTLEN GAHBCFG_HBSTLEN_Msk // Burst length/type +#define GAHBCFG_HBSTLEN_0 (0x0UL << GAHBCFG_HBSTLEN_Pos) // Single +#define GAHBCFG_HBSTLEN_1 (0x1UL << GAHBCFG_HBSTLEN_Pos) // INCR +#define GAHBCFG_HBSTLEN_2 (0x3UL << GAHBCFG_HBSTLEN_Pos) // INCR4 +#define GAHBCFG_HBSTLEN_3 (0x5UL << GAHBCFG_HBSTLEN_Pos) // INCR8 +#define GAHBCFG_HBSTLEN_4 (0x7UL << GAHBCFG_HBSTLEN_Pos) // INCR16 #define GAHBCFG_DMAEN_Pos (5U) -#define GAHBCFG_DMAEN_Msk (0x1UL << GAHBCFG_DMAEN_Pos) // 0x00000020 */ -#define GAHBCFG_DMAEN GAHBCFG_DMAEN_Msk // DMA enable */ +#define GAHBCFG_DMAEN_Msk (0x1UL << GAHBCFG_DMAEN_Pos) // 0x00000020 +#define GAHBCFG_DMAEN GAHBCFG_DMAEN_Msk // DMA enable #define GAHBCFG_TXFELVL_Pos (7U) -#define GAHBCFG_TXFELVL_Msk (0x1UL << GAHBCFG_TXFELVL_Pos) // 0x00000080 */ -#define GAHBCFG_TXFELVL GAHBCFG_TXFELVL_Msk // TxFIFO empty level */ +#define GAHBCFG_TXFELVL_Msk (0x1UL << GAHBCFG_TXFELVL_Pos) // 0x00000080 +#define GAHBCFG_TXFELVL GAHBCFG_TXFELVL_Msk // TxFIFO empty level #define GAHBCFG_PTXFELVL_Pos (8U) -#define GAHBCFG_PTXFELVL_Msk (0x1UL << GAHBCFG_PTXFELVL_Pos) // 0x00000100 */ -#define GAHBCFG_PTXFELVL GAHBCFG_PTXFELVL_Msk // Periodic TxFIFO empty level */ +#define GAHBCFG_PTXFELVL_Msk (0x1UL << GAHBCFG_PTXFELVL_Pos) // 0x00000100 +#define GAHBCFG_PTXFELVL GAHBCFG_PTXFELVL_Msk // Periodic TxFIFO empty level #define GSNPSID_ID_MASK TU_GENMASK(31, 16) /******************** Bit definition for GUSBCFG register ********************/ #define GUSBCFG_TOCAL_Pos (0U) -#define GUSBCFG_TOCAL_Msk (0x7UL << GUSBCFG_TOCAL_Pos) // 0x00000007 */ -#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk // FS timeout calibration */ +#define GUSBCFG_TOCAL_Msk (0x7UL << GUSBCFG_TOCAL_Pos) // 0x00000007 +#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk // FS timeout calibration #define GUSBCFG_PHYIF16_Pos (3U) -#define GUSBCFG_PHYIF16_Msk (0x1UL << GUSBCFG_PHYIF16_Pos) // 0x00000008 */ -#define GUSBCFG_PHYIF16 GUSBCFG_PHYIF16_Msk // PHY Interface (PHYIf) */ +#define GUSBCFG_PHYIF16_Msk (0x1UL << GUSBCFG_PHYIF16_Pos) // 0x00000008 +#define GUSBCFG_PHYIF16 GUSBCFG_PHYIF16_Msk // PHY Interface (PHYIf) #define GUSBCFG_ULPI_UTMI_SEL_Pos (4U) -#define GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos) // 0x00000010 */ -#define GUSBCFG_ULPI_UTMI_SEL GUSBCFG_ULPI_UTMI_SEL_Msk // ULPI or UTMI+ Select (ULPI_UTMI_Sel) */ +#define GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos) // 0x00000010 +#define GUSBCFG_ULPI_UTMI_SEL GUSBCFG_ULPI_UTMI_SEL_Msk // ULPI or UTMI+ Select (ULPI_UTMI_Sel) #define GUSBCFG_PHYSEL_Pos (6U) -#define GUSBCFG_PHYSEL_Msk (0x1UL << GUSBCFG_PHYSEL_Pos) // 0x00000040 */ -#define GUSBCFG_PHYSEL GUSBCFG_PHYSEL_Msk // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define GUSBCFG_PHYSEL_Msk (0x1UL << GUSBCFG_PHYSEL_Pos) // 0x00000040 +#define GUSBCFG_PHYSEL GUSBCFG_PHYSEL_Msk // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select #define GUSBCFG_DDRSEL TU_BIT(7) // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface. #define GUSBCFG_SRPCAP_Pos (8U) -#define GUSBCFG_SRPCAP_Msk (0x1UL << GUSBCFG_SRPCAP_Pos) // 0x00000100 */ -#define GUSBCFG_SRPCAP GUSBCFG_SRPCAP_Msk // SRP-capable */ +#define GUSBCFG_SRPCAP_Msk (0x1UL << GUSBCFG_SRPCAP_Pos) // 0x00000100 +#define GUSBCFG_SRPCAP GUSBCFG_SRPCAP_Msk // SRP-capable #define GUSBCFG_HNPCAP_Pos (9U) -#define GUSBCFG_HNPCAP_Msk (0x1UL << GUSBCFG_HNPCAP_Pos) // 0x00000200 */ -#define GUSBCFG_HNPCAP GUSBCFG_HNPCAP_Msk // HNP-capable */ +#define GUSBCFG_HNPCAP_Msk (0x1UL << GUSBCFG_HNPCAP_Pos) // 0x00000200 +#define GUSBCFG_HNPCAP GUSBCFG_HNPCAP_Msk // HNP-capable #define GUSBCFG_TRDT_Pos (10U) -#define GUSBCFG_TRDT_Msk (0xFUL << GUSBCFG_TRDT_Pos) // 0x00003C00 */ -#define GUSBCFG_TRDT GUSBCFG_TRDT_Msk // USB turnaround time */ +#define GUSBCFG_TRDT_Msk (0xFUL << GUSBCFG_TRDT_Pos) // 0x00003C00 +#define GUSBCFG_TRDT GUSBCFG_TRDT_Msk // USB turnaround time #define GUSBCFG_PHYLPCS_Pos (15U) -#define GUSBCFG_PHYLPCS_Msk (0x1UL << GUSBCFG_PHYLPCS_Pos) // 0x00008000 */ -#define GUSBCFG_PHYLPCS GUSBCFG_PHYLPCS_Msk // PHY Low-power clock select */ +#define GUSBCFG_PHYLPCS_Msk (0x1UL << GUSBCFG_PHYLPCS_Pos) // 0x00008000 +#define GUSBCFG_PHYLPCS GUSBCFG_PHYLPCS_Msk // PHY Low-power clock select #define GUSBCFG_ULPIFSLS_Pos (17U) -#define GUSBCFG_ULPIFSLS_Msk (0x1UL << GUSBCFG_ULPIFSLS_Pos) // 0x00020000 */ -#define GUSBCFG_ULPIFSLS GUSBCFG_ULPIFSLS_Msk // ULPI FS/LS select */ +#define GUSBCFG_ULPIFSLS_Msk (0x1UL << GUSBCFG_ULPIFSLS_Pos) // 0x00020000 +#define GUSBCFG_ULPIFSLS GUSBCFG_ULPIFSLS_Msk // ULPI FS/LS select #define GUSBCFG_ULPIAR_Pos (18U) -#define GUSBCFG_ULPIAR_Msk (0x1UL << GUSBCFG_ULPIAR_Pos) // 0x00040000 */ -#define GUSBCFG_ULPIAR GUSBCFG_ULPIAR_Msk // ULPI Auto-resume */ +#define GUSBCFG_ULPIAR_Msk (0x1UL << GUSBCFG_ULPIAR_Pos) // 0x00040000 +#define GUSBCFG_ULPIAR GUSBCFG_ULPIAR_Msk // ULPI Auto-resume #define GUSBCFG_ULPICSM_Pos (19U) -#define GUSBCFG_ULPICSM_Msk (0x1UL << GUSBCFG_ULPICSM_Pos) // 0x00080000 */ -#define GUSBCFG_ULPICSM GUSBCFG_ULPICSM_Msk // ULPI Clock SuspendM */ +#define GUSBCFG_ULPICSM_Msk (0x1UL << GUSBCFG_ULPICSM_Pos) // 0x00080000 +#define GUSBCFG_ULPICSM GUSBCFG_ULPICSM_Msk // ULPI Clock SuspendM #define GUSBCFG_ULPIEVBUSD_Pos (20U) -#define GUSBCFG_ULPIEVBUSD_Msk (0x1UL << GUSBCFG_ULPIEVBUSD_Pos) // 0x00100000 */ -#define GUSBCFG_ULPIEVBUSD GUSBCFG_ULPIEVBUSD_Msk // ULPI External VBUS Drive */ +#define GUSBCFG_ULPIEVBUSD_Msk (0x1UL << GUSBCFG_ULPIEVBUSD_Pos) // 0x00100000 +#define GUSBCFG_ULPIEVBUSD GUSBCFG_ULPIEVBUSD_Msk // ULPI External VBUS Drive #define GUSBCFG_ULPIEVBUSI_Pos (21U) -#define GUSBCFG_ULPIEVBUSI_Msk (0x1UL << GUSBCFG_ULPIEVBUSI_Pos) // 0x00200000 */ -#define GUSBCFG_ULPIEVBUSI GUSBCFG_ULPIEVBUSI_Msk // ULPI external VBUS indicator */ +#define GUSBCFG_ULPIEVBUSI_Msk (0x1UL << GUSBCFG_ULPIEVBUSI_Pos) // 0x00200000 +#define GUSBCFG_ULPIEVBUSI GUSBCFG_ULPIEVBUSI_Msk // ULPI external VBUS indicator #define GUSBCFG_TSDPS_Pos (22U) -#define GUSBCFG_TSDPS_Msk (0x1UL << GUSBCFG_TSDPS_Pos) // 0x00400000 */ -#define GUSBCFG_TSDPS GUSBCFG_TSDPS_Msk // TermSel DLine pulsing selection */ +#define GUSBCFG_TSDPS_Msk (0x1UL << GUSBCFG_TSDPS_Pos) // 0x00400000 +#define GUSBCFG_TSDPS GUSBCFG_TSDPS_Msk // TermSel DLine pulsing selection #define GUSBCFG_PCCI_Pos (23U) -#define GUSBCFG_PCCI_Msk (0x1UL << GUSBCFG_PCCI_Pos) // 0x00800000 */ -#define GUSBCFG_PCCI GUSBCFG_PCCI_Msk // Indicator complement */ +#define GUSBCFG_PCCI_Msk (0x1UL << GUSBCFG_PCCI_Pos) // 0x00800000 +#define GUSBCFG_PCCI GUSBCFG_PCCI_Msk // Indicator complement #define GUSBCFG_PTCI_Pos (24U) -#define GUSBCFG_PTCI_Msk (0x1UL << GUSBCFG_PTCI_Pos) // 0x01000000 */ -#define GUSBCFG_PTCI GUSBCFG_PTCI_Msk // Indicator pass through */ +#define GUSBCFG_PTCI_Msk (0x1UL << GUSBCFG_PTCI_Pos) // 0x01000000 +#define GUSBCFG_PTCI GUSBCFG_PTCI_Msk // Indicator pass through #define GUSBCFG_ULPIIPD_Pos (25U) -#define GUSBCFG_ULPIIPD_Msk (0x1UL << GUSBCFG_ULPIIPD_Pos) // 0x02000000 */ -#define GUSBCFG_ULPIIPD GUSBCFG_ULPIIPD_Msk // ULPI interface protect disable */ +#define GUSBCFG_ULPIIPD_Msk (0x1UL << GUSBCFG_ULPIIPD_Pos) // 0x02000000 +#define GUSBCFG_ULPIIPD GUSBCFG_ULPIIPD_Msk // ULPI interface protect disable #define GUSBCFG_FHMOD_Pos (29U) -#define GUSBCFG_FHMOD_Msk (0x1UL << GUSBCFG_FHMOD_Pos) // 0x20000000 */ -#define GUSBCFG_FHMOD GUSBCFG_FHMOD_Msk // Forced host mode */ +#define GUSBCFG_FHMOD_Msk (0x1UL << GUSBCFG_FHMOD_Pos) // 0x20000000 +#define GUSBCFG_FHMOD GUSBCFG_FHMOD_Msk // Forced host mode #define GUSBCFG_FDMOD_Pos (30U) -#define GUSBCFG_FDMOD_Msk (0x1UL << GUSBCFG_FDMOD_Pos) // 0x40000000 */ -#define GUSBCFG_FDMOD GUSBCFG_FDMOD_Msk // Forced peripheral mode */ +#define GUSBCFG_FDMOD_Msk (0x1UL << GUSBCFG_FDMOD_Pos) // 0x40000000 +#define GUSBCFG_FDMOD GUSBCFG_FDMOD_Msk // Forced peripheral mode #define GUSBCFG_CTXPKT_Pos (31U) -#define GUSBCFG_CTXPKT_Msk (0x1UL << GUSBCFG_CTXPKT_Pos) // 0x80000000 */ -#define GUSBCFG_CTXPKT GUSBCFG_CTXPKT_Msk // Corrupt Tx packet */ +#define GUSBCFG_CTXPKT_Msk (0x1UL << GUSBCFG_CTXPKT_Pos) // 0x80000000 +#define GUSBCFG_CTXPKT GUSBCFG_CTXPKT_Msk // Corrupt Tx packet /******************** Bit definition for GRSTCTL register ********************/ #define GRSTCTL_CSRST_Pos (0U) -#define GRSTCTL_CSRST_Msk (0x1UL << GRSTCTL_CSRST_Pos) // 0x00000001 */ -#define GRSTCTL_CSRST GRSTCTL_CSRST_Msk // Core soft reset */ +#define GRSTCTL_CSRST_Msk (0x1UL << GRSTCTL_CSRST_Pos) // 0x00000001 +#define GRSTCTL_CSRST GRSTCTL_CSRST_Msk // Core soft reset #define GRSTCTL_HSRST_Pos (1U) -#define GRSTCTL_HSRST_Msk (0x1UL << GRSTCTL_HSRST_Pos) // 0x00000002 */ -#define GRSTCTL_HSRST GRSTCTL_HSRST_Msk // HCLK soft reset */ +#define GRSTCTL_HSRST_Msk (0x1UL << GRSTCTL_HSRST_Pos) // 0x00000002 +#define GRSTCTL_HSRST GRSTCTL_HSRST_Msk // HCLK soft reset #define GRSTCTL_FCRST_Pos (2U) -#define GRSTCTL_FCRST_Msk (0x1UL << GRSTCTL_FCRST_Pos) // 0x00000004 */ -#define GRSTCTL_FCRST GRSTCTL_FCRST_Msk // Host frame counter reset */ +#define GRSTCTL_FCRST_Msk (0x1UL << GRSTCTL_FCRST_Pos) // 0x00000004 +#define GRSTCTL_FCRST GRSTCTL_FCRST_Msk // Host frame counter reset #define GRSTCTL_RXFFLSH_Pos (4U) -#define GRSTCTL_RXFFLSH_Msk (0x1UL << GRSTCTL_RXFFLSH_Pos) // 0x00000010 */ -#define GRSTCTL_RXFFLSH GRSTCTL_RXFFLSH_Msk // RxFIFO flush */ +#define GRSTCTL_RXFFLSH_Msk (0x1UL << GRSTCTL_RXFFLSH_Pos) // 0x00000010 +#define GRSTCTL_RXFFLSH GRSTCTL_RXFFLSH_Msk // RxFIFO flush #define GRSTCTL_TXFFLSH_Pos (5U) -#define GRSTCTL_TXFFLSH_Msk (0x1UL << GRSTCTL_TXFFLSH_Pos) // 0x00000020 */ -#define GRSTCTL_TXFFLSH GRSTCTL_TXFFLSH_Msk // TxFIFO flush */ +#define GRSTCTL_TXFFLSH_Msk (0x1UL << GRSTCTL_TXFFLSH_Pos) // 0x00000020 +#define GRSTCTL_TXFFLSH GRSTCTL_TXFFLSH_Msk // TxFIFO flush #define GRSTCTL_TXFNUM_Pos (6U) -#define GRSTCTL_TXFNUM_Msk (0x1FUL << GRSTCTL_TXFNUM_Pos) // 0x000007C0 */ -#define GRSTCTL_TXFNUM GRSTCTL_TXFNUM_Msk // TxFIFO number */ -#define GRSTCTL_TXFNUM_0 (0x01UL << GRSTCTL_TXFNUM_Pos) // 0x00000040 */ -#define GRSTCTL_TXFNUM_1 (0x02UL << GRSTCTL_TXFNUM_Pos) // 0x00000080 */ -#define GRSTCTL_TXFNUM_2 (0x04UL << GRSTCTL_TXFNUM_Pos) // 0x00000100 */ -#define GRSTCTL_TXFNUM_3 (0x08UL << GRSTCTL_TXFNUM_Pos) // 0x00000200 */ -#define GRSTCTL_TXFNUM_4 (0x10UL << GRSTCTL_TXFNUM_Pos) // 0x00000400 */ +#define GRSTCTL_TXFNUM_Msk (0x1FUL << GRSTCTL_TXFNUM_Pos) // 0x000007C0 +#define GRSTCTL_TXFNUM GRSTCTL_TXFNUM_Msk // TxFIFO number +#define GRSTCTL_TXFNUM_0 (0x01UL << GRSTCTL_TXFNUM_Pos) // 0x00000040 +#define GRSTCTL_TXFNUM_1 (0x02UL << GRSTCTL_TXFNUM_Pos) // 0x00000080 +#define GRSTCTL_TXFNUM_2 (0x04UL << GRSTCTL_TXFNUM_Pos) // 0x00000100 +#define GRSTCTL_TXFNUM_3 (0x08UL << GRSTCTL_TXFNUM_Pos) // 0x00000200 +#define GRSTCTL_TXFNUM_4 (0x10UL << GRSTCTL_TXFNUM_Pos) // 0x00000400 #define GRSTCTL_CSFTRST_DONE_Pos (29) #define GRSTCTL_CSFTRST_DONE (1u << GRSTCTL_CSFTRST_DONE_Pos) // Reset Done, only available from v4.20a #define GRSTCTL_DMAREQ_Pos (30U) -#define GRSTCTL_DMAREQ_Msk (0x1UL << GRSTCTL_DMAREQ_Pos) // 0x40000000 */ -#define GRSTCTL_DMAREQ GRSTCTL_DMAREQ_Msk // DMA request signal */ +#define GRSTCTL_DMAREQ_Msk (0x1UL << GRSTCTL_DMAREQ_Pos) // 0x40000000 +#define GRSTCTL_DMAREQ GRSTCTL_DMAREQ_Msk // DMA request signal #define GRSTCTL_AHBIDL_Pos (31U) -#define GRSTCTL_AHBIDL_Msk (0x1UL << GRSTCTL_AHBIDL_Pos) // 0x80000000 */ -#define GRSTCTL_AHBIDL GRSTCTL_AHBIDL_Msk // AHB master idle */ +#define GRSTCTL_AHBIDL_Msk (0x1UL << GRSTCTL_AHBIDL_Pos) // 0x80000000 +#define GRSTCTL_AHBIDL GRSTCTL_AHBIDL_Msk // AHB master idle /******************** Bit definition for DIEPMSK register ********************/ #define DIEPMSK_XFRCM_Pos (0U) -#define DIEPMSK_XFRCM_Msk (0x1UL << DIEPMSK_XFRCM_Pos) // 0x00000001 */ -#define DIEPMSK_XFRCM DIEPMSK_XFRCM_Msk // Transfer completed interrupt mask */ +#define DIEPMSK_XFRCM_Msk (0x1UL << DIEPMSK_XFRCM_Pos) // 0x00000001 +#define DIEPMSK_XFRCM DIEPMSK_XFRCM_Msk // Transfer completed interrupt mask #define DIEPMSK_EPDM_Pos (1U) -#define DIEPMSK_EPDM_Msk (0x1UL << DIEPMSK_EPDM_Pos) // 0x00000002 */ -#define DIEPMSK_EPDM DIEPMSK_EPDM_Msk // Endpoint disabled interrupt mask */ +#define DIEPMSK_EPDM_Msk (0x1UL << DIEPMSK_EPDM_Pos) // 0x00000002 +#define DIEPMSK_EPDM DIEPMSK_EPDM_Msk // Endpoint disabled interrupt mask #define DIEPMSK_TOM_Pos (3U) -#define DIEPMSK_TOM_Msk (0x1UL << DIEPMSK_TOM_Pos) // 0x00000008 */ -#define DIEPMSK_TOM DIEPMSK_TOM_Msk // Timeout condition mask (nonisochronous endpoints) */ +#define DIEPMSK_TOM_Msk (0x1UL << DIEPMSK_TOM_Pos) // 0x00000008 +#define DIEPMSK_TOM DIEPMSK_TOM_Msk // Timeout condition mask (nonisochronous endpoints) #define DIEPMSK_ITTXFEMSK_Pos (4U) -#define DIEPMSK_ITTXFEMSK_Msk (0x1UL << DIEPMSK_ITTXFEMSK_Pos) // 0x00000010 */ -#define DIEPMSK_ITTXFEMSK DIEPMSK_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask */ +#define DIEPMSK_ITTXFEMSK_Msk (0x1UL << DIEPMSK_ITTXFEMSK_Pos) // 0x00000010 +#define DIEPMSK_ITTXFEMSK DIEPMSK_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask #define DIEPMSK_INEPNMM_Pos (5U) -#define DIEPMSK_INEPNMM_Msk (0x1UL << DIEPMSK_INEPNMM_Pos) // 0x00000020 */ -#define DIEPMSK_INEPNMM DIEPMSK_INEPNMM_Msk // IN token received with EP mismatch mask */ +#define DIEPMSK_INEPNMM_Msk (0x1UL << DIEPMSK_INEPNMM_Pos) // 0x00000020 +#define DIEPMSK_INEPNMM DIEPMSK_INEPNMM_Msk // IN token received with EP mismatch mask #define DIEPMSK_INEPNEM_Pos (6U) -#define DIEPMSK_INEPNEM_Msk (0x1UL << DIEPMSK_INEPNEM_Pos) // 0x00000040 */ -#define DIEPMSK_INEPNEM DIEPMSK_INEPNEM_Msk // IN endpoint NAK effective mask */ +#define DIEPMSK_INEPNEM_Msk (0x1UL << DIEPMSK_INEPNEM_Pos) // 0x00000040 +#define DIEPMSK_INEPNEM DIEPMSK_INEPNEM_Msk // IN endpoint NAK effective mask #define DIEPMSK_TXFURM_Pos (8U) -#define DIEPMSK_TXFURM_Msk (0x1UL << DIEPMSK_TXFURM_Pos) // 0x00000100 */ -#define DIEPMSK_TXFURM DIEPMSK_TXFURM_Msk // FIFO underrun mask */ +#define DIEPMSK_TXFURM_Msk (0x1UL << DIEPMSK_TXFURM_Pos) // 0x00000100 +#define DIEPMSK_TXFURM DIEPMSK_TXFURM_Msk // FIFO underrun mask #define DIEPMSK_BIM_Pos (9U) -#define DIEPMSK_BIM_Msk (0x1UL << DIEPMSK_BIM_Pos) // 0x00000200 */ -#define DIEPMSK_BIM DIEPMSK_BIM_Msk // BNA interrupt mask */ +#define DIEPMSK_BIM_Msk (0x1UL << DIEPMSK_BIM_Pos) // 0x00000200 +#define DIEPMSK_BIM DIEPMSK_BIM_Msk // BNA interrupt mask /******************** Bit definition for HPTXSTS register ********************/ #define HPTXSTS_PTXFSAVL_Pos (0U) -#define HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos) // 0x0000FFFF */ -#define HPTXSTS_PTXFSAVL HPTXSTS_PTXFSAVL_Msk // Periodic transmit data FIFO space available */ +#define HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos) // 0x0000FFFF +#define HPTXSTS_PTXFSAVL HPTXSTS_PTXFSAVL_Msk // Periodic transmit data FIFO space available #define HPTXSTS_PTXQSAV_Pos (16U) -#define HPTXSTS_PTXQSAV_Msk (0xFFUL << HPTXSTS_PTXQSAV_Pos) // 0x00FF0000 */ -#define HPTXSTS_PTXQSAV HPTXSTS_PTXQSAV_Msk // Periodic transmit request queue space available */ -#define HPTXSTS_PTXQSAV_0 (0x01UL << HPTXSTS_PTXQSAV_Pos) // 0x00010000 */ -#define HPTXSTS_PTXQSAV_1 (0x02UL << HPTXSTS_PTXQSAV_Pos) // 0x00020000 */ -#define HPTXSTS_PTXQSAV_2 (0x04UL << HPTXSTS_PTXQSAV_Pos) // 0x00040000 */ -#define HPTXSTS_PTXQSAV_3 (0x08UL << HPTXSTS_PTXQSAV_Pos) // 0x00080000 */ -#define HPTXSTS_PTXQSAV_4 (0x10UL << HPTXSTS_PTXQSAV_Pos) // 0x00100000 */ -#define HPTXSTS_PTXQSAV_5 (0x20UL << HPTXSTS_PTXQSAV_Pos) // 0x00200000 */ -#define HPTXSTS_PTXQSAV_6 (0x40UL << HPTXSTS_PTXQSAV_Pos) // 0x00400000 */ -#define HPTXSTS_PTXQSAV_7 (0x80UL << HPTXSTS_PTXQSAV_Pos) // 0x00800000 */ +#define HPTXSTS_PTXQSAV_Msk (0xFFUL << HPTXSTS_PTXQSAV_Pos) // 0x00FF0000 +#define HPTXSTS_PTXQSAV HPTXSTS_PTXQSAV_Msk // Periodic transmit request queue space available +#define HPTXSTS_PTXQSAV_0 (0x01UL << HPTXSTS_PTXQSAV_Pos) // 0x00010000 +#define HPTXSTS_PTXQSAV_1 (0x02UL << HPTXSTS_PTXQSAV_Pos) // 0x00020000 +#define HPTXSTS_PTXQSAV_2 (0x04UL << HPTXSTS_PTXQSAV_Pos) // 0x00040000 +#define HPTXSTS_PTXQSAV_3 (0x08UL << HPTXSTS_PTXQSAV_Pos) // 0x00080000 +#define HPTXSTS_PTXQSAV_4 (0x10UL << HPTXSTS_PTXQSAV_Pos) // 0x00100000 +#define HPTXSTS_PTXQSAV_5 (0x20UL << HPTXSTS_PTXQSAV_Pos) // 0x00200000 +#define HPTXSTS_PTXQSAV_6 (0x40UL << HPTXSTS_PTXQSAV_Pos) // 0x00400000 +#define HPTXSTS_PTXQSAV_7 (0x80UL << HPTXSTS_PTXQSAV_Pos) // 0x00800000 #define HPTXSTS_PTXQTOP_Pos (24U) -#define HPTXSTS_PTXQTOP_Msk (0xFFUL << HPTXSTS_PTXQTOP_Pos) // 0xFF000000 */ -#define HPTXSTS_PTXQTOP HPTXSTS_PTXQTOP_Msk // Top of the periodic transmit request queue */ -#define HPTXSTS_PTXQTOP_0 (0x01UL << HPTXSTS_PTXQTOP_Pos) // 0x01000000 */ -#define HPTXSTS_PTXQTOP_1 (0x02UL << HPTXSTS_PTXQTOP_Pos) // 0x02000000 */ -#define HPTXSTS_PTXQTOP_2 (0x04UL << HPTXSTS_PTXQTOP_Pos) // 0x04000000 */ -#define HPTXSTS_PTXQTOP_3 (0x08UL << HPTXSTS_PTXQTOP_Pos) // 0x08000000 */ -#define HPTXSTS_PTXQTOP_4 (0x10UL << HPTXSTS_PTXQTOP_Pos) // 0x10000000 */ -#define HPTXSTS_PTXQTOP_5 (0x20UL << HPTXSTS_PTXQTOP_Pos) // 0x20000000 */ -#define HPTXSTS_PTXQTOP_6 (0x40UL << HPTXSTS_PTXQTOP_Pos) // 0x40000000 */ -#define HPTXSTS_PTXQTOP_7 (0x80UL << HPTXSTS_PTXQTOP_Pos) // 0x80000000 */ +#define HPTXSTS_PTXQTOP_Msk (0xFFUL << HPTXSTS_PTXQTOP_Pos) // 0xFF000000 +#define HPTXSTS_PTXQTOP HPTXSTS_PTXQTOP_Msk // Top of the periodic transmit request queue +#define HPTXSTS_PTXQTOP_0 (0x01UL << HPTXSTS_PTXQTOP_Pos) // 0x01000000 +#define HPTXSTS_PTXQTOP_1 (0x02UL << HPTXSTS_PTXQTOP_Pos) // 0x02000000 +#define HPTXSTS_PTXQTOP_2 (0x04UL << HPTXSTS_PTXQTOP_Pos) // 0x04000000 +#define HPTXSTS_PTXQTOP_3 (0x08UL << HPTXSTS_PTXQTOP_Pos) // 0x08000000 +#define HPTXSTS_PTXQTOP_4 (0x10UL << HPTXSTS_PTXQTOP_Pos) // 0x10000000 +#define HPTXSTS_PTXQTOP_5 (0x20UL << HPTXSTS_PTXQTOP_Pos) // 0x20000000 +#define HPTXSTS_PTXQTOP_6 (0x40UL << HPTXSTS_PTXQTOP_Pos) // 0x40000000 +#define HPTXSTS_PTXQTOP_7 (0x80UL << HPTXSTS_PTXQTOP_Pos) // 0x80000000 /******************** Bit definition for HAINT register ********************/ #define HAINT_HAINT_Pos (0U) -#define HAINT_HAINT_Msk (0xFFFFUL << HAINT_HAINT_Pos) // 0x0000FFFF */ -#define HAINT_HAINT HAINT_HAINT_Msk // Channel interrupts */ +#define HAINT_HAINT_Msk (0xFFFFUL << HAINT_HAINT_Pos) // 0x0000FFFF +#define HAINT_HAINT HAINT_HAINT_Msk // Channel interrupts /******************** Bit definition for DOEPMSK register ********************/ #define DOEPMSK_XFRCM_Pos (0U) -#define DOEPMSK_XFRCM_Msk (0x1UL << DOEPMSK_XFRCM_Pos) // 0x00000001 */ -#define DOEPMSK_XFRCM DOEPMSK_XFRCM_Msk // Transfer completed interrupt mask */ +#define DOEPMSK_XFRCM_Msk (0x1UL << DOEPMSK_XFRCM_Pos) // 0x00000001 +#define DOEPMSK_XFRCM DOEPMSK_XFRCM_Msk // Transfer completed interrupt mask #define DOEPMSK_EPDM_Pos (1U) -#define DOEPMSK_EPDM_Msk (0x1UL << DOEPMSK_EPDM_Pos) // 0x00000002 */ -#define DOEPMSK_EPDM DOEPMSK_EPDM_Msk // Endpoint disabled interrupt mask */ +#define DOEPMSK_EPDM_Msk (0x1UL << DOEPMSK_EPDM_Pos) // 0x00000002 +#define DOEPMSK_EPDM DOEPMSK_EPDM_Msk // Endpoint disabled interrupt mask #define DOEPMSK_AHBERRM_Pos (2U) -#define DOEPMSK_AHBERRM_Msk (0x1UL << DOEPMSK_AHBERRM_Pos) // 0x00000004 */ -#define DOEPMSK_AHBERRM DOEPMSK_AHBERRM_Msk // OUT transaction AHB Error interrupt mask */ +#define DOEPMSK_AHBERRM_Msk (0x1UL << DOEPMSK_AHBERRM_Pos) // 0x00000004 +#define DOEPMSK_AHBERRM DOEPMSK_AHBERRM_Msk // OUT transaction AHB Error interrupt mask #define DOEPMSK_STUPM_Pos (3U) -#define DOEPMSK_STUPM_Msk (0x1UL << DOEPMSK_STUPM_Pos) // 0x00000008 */ -#define DOEPMSK_STUPM DOEPMSK_STUPM_Msk // SETUP phase done mask */ +#define DOEPMSK_STUPM_Msk (0x1UL << DOEPMSK_STUPM_Pos) // 0x00000008 +#define DOEPMSK_STUPM DOEPMSK_STUPM_Msk // SETUP phase done mask #define DOEPMSK_OTEPDM_Pos (4U) -#define DOEPMSK_OTEPDM_Msk (0x1UL << DOEPMSK_OTEPDM_Pos) // 0x00000010 */ -#define DOEPMSK_OTEPDM DOEPMSK_OTEPDM_Msk // OUT token received when endpoint disabled mask */ +#define DOEPMSK_OTEPDM_Msk (0x1UL << DOEPMSK_OTEPDM_Pos) // 0x00000010 +#define DOEPMSK_OTEPDM DOEPMSK_OTEPDM_Msk // OUT token received when endpoint disabled mask #define DOEPMSK_OTEPSPRM_Pos (5U) -#define DOEPMSK_OTEPSPRM_Msk (0x1UL << DOEPMSK_OTEPSPRM_Pos) // 0x00000020 */ -#define DOEPMSK_OTEPSPRM DOEPMSK_OTEPSPRM_Msk // Status Phase Received mask */ +#define DOEPMSK_OTEPSPRM_Msk (0x1UL << DOEPMSK_OTEPSPRM_Pos) // 0x00000020 +#define DOEPMSK_OTEPSPRM DOEPMSK_OTEPSPRM_Msk // Status Phase Received mask #define DOEPMSK_B2BSTUP_Pos (6U) -#define DOEPMSK_B2BSTUP_Msk (0x1UL << DOEPMSK_B2BSTUP_Pos) // 0x00000040 */ -#define DOEPMSK_B2BSTUP DOEPMSK_B2BSTUP_Msk // Back-to-back SETUP packets received mask */ +#define DOEPMSK_B2BSTUP_Msk (0x1UL << DOEPMSK_B2BSTUP_Pos) // 0x00000040 +#define DOEPMSK_B2BSTUP DOEPMSK_B2BSTUP_Msk // Back-to-back SETUP packets received mask #define DOEPMSK_OPEM_Pos (8U) -#define DOEPMSK_OPEM_Msk (0x1UL << DOEPMSK_OPEM_Pos) // 0x00000100 */ -#define DOEPMSK_OPEM DOEPMSK_OPEM_Msk // OUT packet error mask */ +#define DOEPMSK_OPEM_Msk (0x1UL << DOEPMSK_OPEM_Pos) // 0x00000100 +#define DOEPMSK_OPEM DOEPMSK_OPEM_Msk // OUT packet error mask #define DOEPMSK_BOIM_Pos (9U) -#define DOEPMSK_BOIM_Msk (0x1UL << DOEPMSK_BOIM_Pos) // 0x00000200 */ -#define DOEPMSK_BOIM DOEPMSK_BOIM_Msk // BNA interrupt mask */ +#define DOEPMSK_BOIM_Msk (0x1UL << DOEPMSK_BOIM_Pos) // 0x00000200 +#define DOEPMSK_BOIM DOEPMSK_BOIM_Msk // BNA interrupt mask #define DOEPMSK_BERRM_Pos (12U) -#define DOEPMSK_BERRM_Msk (0x1UL << DOEPMSK_BERRM_Pos) // 0x00001000 */ -#define DOEPMSK_BERRM DOEPMSK_BERRM_Msk // Babble error interrupt mask */ +#define DOEPMSK_BERRM_Msk (0x1UL << DOEPMSK_BERRM_Pos) // 0x00001000 +#define DOEPMSK_BERRM DOEPMSK_BERRM_Msk // Babble error interrupt mask #define DOEPMSK_NAKM_Pos (13U) -#define DOEPMSK_NAKM_Msk (0x1UL << DOEPMSK_NAKM_Pos) // 0x00002000 */ -#define DOEPMSK_NAKM DOEPMSK_NAKM_Msk // OUT Packet NAK interrupt mask */ +#define DOEPMSK_NAKM_Msk (0x1UL << DOEPMSK_NAKM_Pos) // 0x00002000 +#define DOEPMSK_NAKM DOEPMSK_NAKM_Msk // OUT Packet NAK interrupt mask #define DOEPMSK_NYETM_Pos (14U) -#define DOEPMSK_NYETM_Msk (0x1UL << DOEPMSK_NYETM_Pos) // 0x00004000 */ -#define DOEPMSK_NYETM DOEPMSK_NYETM_Msk // NYET interrupt mask */ +#define DOEPMSK_NYETM_Msk (0x1UL << DOEPMSK_NYETM_Pos) // 0x00004000 +#define DOEPMSK_NYETM DOEPMSK_NYETM_Msk // NYET interrupt mask /******************** Bit definition for GINTSTS register ********************/ #define GINTSTS_CMOD_Pos (0U) -#define GINTSTS_CMOD_Msk (0x1UL << GINTSTS_CMOD_Pos) // 0x00000001 */ -#define GINTSTS_CMOD GINTSTS_CMOD_Msk // Current mode of operation */ +#define GINTSTS_CMOD_Msk (0x1UL << GINTSTS_CMOD_Pos) // 0x00000001 +#define GINTSTS_CMOD GINTSTS_CMOD_Msk // Current mode of operation #define GINTSTS_MMIS_Pos (1U) -#define GINTSTS_MMIS_Msk (0x1UL << GINTSTS_MMIS_Pos) // 0x00000002 */ -#define GINTSTS_MMIS GINTSTS_MMIS_Msk // Mode mismatch interrupt */ +#define GINTSTS_MMIS_Msk (0x1UL << GINTSTS_MMIS_Pos) // 0x00000002 +#define GINTSTS_MMIS GINTSTS_MMIS_Msk // Mode mismatch interrupt #define GINTSTS_OTGINT_Pos (2U) -#define GINTSTS_OTGINT_Msk (0x1UL << GINTSTS_OTGINT_Pos) // 0x00000004 */ -#define GINTSTS_OTGINT GINTSTS_OTGINT_Msk // OTG interrupt */ +#define GINTSTS_OTGINT_Msk (0x1UL << GINTSTS_OTGINT_Pos) // 0x00000004 +#define GINTSTS_OTGINT GINTSTS_OTGINT_Msk // OTG interrupt #define GINTSTS_SOF_Pos (3U) -#define GINTSTS_SOF_Msk (0x1UL << GINTSTS_SOF_Pos) // 0x00000008 */ -#define GINTSTS_SOF GINTSTS_SOF_Msk // Start of frame */ +#define GINTSTS_SOF_Msk (0x1UL << GINTSTS_SOF_Pos) // 0x00000008 +#define GINTSTS_SOF GINTSTS_SOF_Msk // Start of frame #define GINTSTS_RXFLVL_Pos (4U) -#define GINTSTS_RXFLVL_Msk (0x1UL << GINTSTS_RXFLVL_Pos) // 0x00000010 */ -#define GINTSTS_RXFLVL GINTSTS_RXFLVL_Msk // RxFIFO nonempty */ +#define GINTSTS_RXFLVL_Msk (0x1UL << GINTSTS_RXFLVL_Pos) // 0x00000010 +#define GINTSTS_RXFLVL GINTSTS_RXFLVL_Msk // RxFIFO nonempty #define GINTSTS_NPTXFE_Pos (5U) -#define GINTSTS_NPTXFE_Msk (0x1UL << GINTSTS_NPTXFE_Pos) // 0x00000020 */ -#define GINTSTS_NPTXFE GINTSTS_NPTXFE_Msk // Nonperiodic TxFIFO empty */ +#define GINTSTS_NPTXFE_Msk (0x1UL << GINTSTS_NPTXFE_Pos) // 0x00000020 +#define GINTSTS_NPTXFE GINTSTS_NPTXFE_Msk // Nonperiodic TxFIFO empty #define GINTSTS_GINAKEFF_Pos (6U) -#define GINTSTS_GINAKEFF_Msk (0x1UL << GINTSTS_GINAKEFF_Pos) // 0x00000040 */ -#define GINTSTS_GINAKEFF GINTSTS_GINAKEFF_Msk // Global IN nonperiodic NAK effective */ +#define GINTSTS_GINAKEFF_Msk (0x1UL << GINTSTS_GINAKEFF_Pos) // 0x00000040 +#define GINTSTS_GINAKEFF GINTSTS_GINAKEFF_Msk // Global IN nonperiodic NAK effective #define GINTSTS_BOUTNAKEFF_Pos (7U) -#define GINTSTS_BOUTNAKEFF_Msk (0x1UL << GINTSTS_BOUTNAKEFF_Pos) // 0x00000080 */ -#define GINTSTS_BOUTNAKEFF GINTSTS_BOUTNAKEFF_Msk // Global OUT NAK effective */ +#define GINTSTS_BOUTNAKEFF_Msk (0x1UL << GINTSTS_BOUTNAKEFF_Pos) // 0x00000080 +#define GINTSTS_BOUTNAKEFF GINTSTS_BOUTNAKEFF_Msk // Global OUT NAK effective #define GINTSTS_ESUSP_Pos (10U) -#define GINTSTS_ESUSP_Msk (0x1UL << GINTSTS_ESUSP_Pos) // 0x00000400 */ -#define GINTSTS_ESUSP GINTSTS_ESUSP_Msk // Early suspend */ +#define GINTSTS_ESUSP_Msk (0x1UL << GINTSTS_ESUSP_Pos) // 0x00000400 +#define GINTSTS_ESUSP GINTSTS_ESUSP_Msk // Early suspend #define GINTSTS_USBSUSP_Pos (11U) -#define GINTSTS_USBSUSP_Msk (0x1UL << GINTSTS_USBSUSP_Pos) // 0x00000800 */ -#define GINTSTS_USBSUSP GINTSTS_USBSUSP_Msk // USB suspend */ +#define GINTSTS_USBSUSP_Msk (0x1UL << GINTSTS_USBSUSP_Pos) // 0x00000800 +#define GINTSTS_USBSUSP GINTSTS_USBSUSP_Msk // USB suspend #define GINTSTS_USBRST_Pos (12U) -#define GINTSTS_USBRST_Msk (0x1UL << GINTSTS_USBRST_Pos) // 0x00001000 */ -#define GINTSTS_USBRST GINTSTS_USBRST_Msk // USB reset */ +#define GINTSTS_USBRST_Msk (0x1UL << GINTSTS_USBRST_Pos) // 0x00001000 +#define GINTSTS_USBRST GINTSTS_USBRST_Msk // USB reset #define GINTSTS_ENUMDNE_Pos (13U) -#define GINTSTS_ENUMDNE_Msk (0x1UL << GINTSTS_ENUMDNE_Pos) // 0x00002000 */ -#define GINTSTS_ENUMDNE GINTSTS_ENUMDNE_Msk // Enumeration done */ +#define GINTSTS_ENUMDNE_Msk (0x1UL << GINTSTS_ENUMDNE_Pos) // 0x00002000 +#define GINTSTS_ENUMDNE GINTSTS_ENUMDNE_Msk // Enumeration done #define GINTSTS_ISOODRP_Pos (14U) -#define GINTSTS_ISOODRP_Msk (0x1UL << GINTSTS_ISOODRP_Pos) // 0x00004000 */ -#define GINTSTS_ISOODRP GINTSTS_ISOODRP_Msk // Isochronous OUT packet dropped interrupt */ +#define GINTSTS_ISOODRP_Msk (0x1UL << GINTSTS_ISOODRP_Pos) // 0x00004000 +#define GINTSTS_ISOODRP GINTSTS_ISOODRP_Msk // Isochronous OUT packet dropped interrupt #define GINTSTS_EOPF_Pos (15U) -#define GINTSTS_EOPF_Msk (0x1UL << GINTSTS_EOPF_Pos) // 0x00008000 */ -#define GINTSTS_EOPF GINTSTS_EOPF_Msk // End of periodic frame interrupt */ +#define GINTSTS_EOPF_Msk (0x1UL << GINTSTS_EOPF_Pos) // 0x00008000 +#define GINTSTS_EOPF GINTSTS_EOPF_Msk // End of periodic frame interrupt #define GINTSTS_IEPINT_Pos (18U) -#define GINTSTS_IEPINT_Msk (0x1UL << GINTSTS_IEPINT_Pos) // 0x00040000 */ -#define GINTSTS_IEPINT GINTSTS_IEPINT_Msk // IN endpoint interrupt */ +#define GINTSTS_IEPINT_Msk (0x1UL << GINTSTS_IEPINT_Pos) // 0x00040000 +#define GINTSTS_IEPINT GINTSTS_IEPINT_Msk // IN endpoint interrupt #define GINTSTS_OEPINT_Pos (19U) -#define GINTSTS_OEPINT_Msk (0x1UL << GINTSTS_OEPINT_Pos) // 0x00080000 */ -#define GINTSTS_OEPINT GINTSTS_OEPINT_Msk // OUT endpoint interrupt */ +#define GINTSTS_OEPINT_Msk (0x1UL << GINTSTS_OEPINT_Pos) // 0x00080000 +#define GINTSTS_OEPINT GINTSTS_OEPINT_Msk // OUT endpoint interrupt #define GINTSTS_IISOIXFR_Pos (20U) -#define GINTSTS_IISOIXFR_Msk (0x1UL << GINTSTS_IISOIXFR_Pos) // 0x00100000 */ -#define GINTSTS_IISOIXFR GINTSTS_IISOIXFR_Msk // Incomplete isochronous IN transfer */ +#define GINTSTS_IISOIXFR_Msk (0x1UL << GINTSTS_IISOIXFR_Pos) // 0x00100000 +#define GINTSTS_IISOIXFR GINTSTS_IISOIXFR_Msk // Incomplete isochronous IN transfer #define GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) -#define GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) // 0x00200000 */ -#define GINTSTS_PXFR_INCOMPISOOUT GINTSTS_PXFR_INCOMPISOOUT_Msk // Incomplete periodic transfer */ +#define GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) // 0x00200000 +#define GINTSTS_PXFR_INCOMPISOOUT GINTSTS_PXFR_INCOMPISOOUT_Msk // Incomplete periodic transfer #define GINTSTS_DATAFSUSP_Pos (22U) -#define GINTSTS_DATAFSUSP_Msk (0x1UL << GINTSTS_DATAFSUSP_Pos) // 0x00400000 */ -#define GINTSTS_DATAFSUSP GINTSTS_DATAFSUSP_Msk // Data fetch suspended */ +#define GINTSTS_DATAFSUSP_Msk (0x1UL << GINTSTS_DATAFSUSP_Pos) // 0x00400000 +#define GINTSTS_DATAFSUSP GINTSTS_DATAFSUSP_Msk // Data fetch suspended #define GINTSTS_RSTDET_Pos (23U) -#define GINTSTS_RSTDET_Msk (0x1UL << GINTSTS_RSTDET_Pos) // 0x00800000 */ -#define GINTSTS_RSTDET GINTSTS_RSTDET_Msk // Reset detected interrupt */ +#define GINTSTS_RSTDET_Msk (0x1UL << GINTSTS_RSTDET_Pos) // 0x00800000 +#define GINTSTS_RSTDET GINTSTS_RSTDET_Msk // Reset detected interrupt #define GINTSTS_HPRTINT_Pos (24U) -#define GINTSTS_HPRTINT_Msk (0x1UL << GINTSTS_HPRTINT_Pos) // 0x01000000 */ -#define GINTSTS_HPRTINT GINTSTS_HPRTINT_Msk // Host port interrupt */ +#define GINTSTS_HPRTINT_Msk (0x1UL << GINTSTS_HPRTINT_Pos) // 0x01000000 +#define GINTSTS_HPRTINT GINTSTS_HPRTINT_Msk // Host port interrupt #define GINTSTS_HCINT_Pos (25U) -#define GINTSTS_HCINT_Msk (0x1UL << GINTSTS_HCINT_Pos) // 0x02000000 */ -#define GINTSTS_HCINT GINTSTS_HCINT_Msk // Host channels interrupt */ +#define GINTSTS_HCINT_Msk (0x1UL << GINTSTS_HCINT_Pos) // 0x02000000 +#define GINTSTS_HCINT GINTSTS_HCINT_Msk // Host channels interrupt #define GINTSTS_PTXFE_Pos (26U) -#define GINTSTS_PTXFE_Msk (0x1UL << GINTSTS_PTXFE_Pos) // 0x04000000 */ -#define GINTSTS_PTXFE GINTSTS_PTXFE_Msk // Periodic TxFIFO empty */ +#define GINTSTS_PTXFE_Msk (0x1UL << GINTSTS_PTXFE_Pos) // 0x04000000 +#define GINTSTS_PTXFE GINTSTS_PTXFE_Msk // Periodic TxFIFO empty #define GINTSTS_LPMINT_Pos (27U) -#define GINTSTS_LPMINT_Msk (0x1UL << GINTSTS_LPMINT_Pos) // 0x08000000 */ -#define GINTSTS_LPMINT GINTSTS_LPMINT_Msk // LPM interrupt */ +#define GINTSTS_LPMINT_Msk (0x1UL << GINTSTS_LPMINT_Pos) // 0x08000000 +#define GINTSTS_LPMINT GINTSTS_LPMINT_Msk // LPM interrupt #define GINTSTS_CIDSCHG_Pos (28U) -#define GINTSTS_CIDSCHG_Msk (0x1UL << GINTSTS_CIDSCHG_Pos) // 0x10000000 */ -#define GINTSTS_CIDSCHG GINTSTS_CIDSCHG_Msk // Connector ID status change */ +#define GINTSTS_CIDSCHG_Msk (0x1UL << GINTSTS_CIDSCHG_Pos) // 0x10000000 +#define GINTSTS_CIDSCHG GINTSTS_CIDSCHG_Msk // Connector ID status change #define GINTSTS_DISCINT_Pos (29U) -#define GINTSTS_DISCINT_Msk (0x1UL << GINTSTS_DISCINT_Pos) // 0x20000000 */ -#define GINTSTS_DISCINT GINTSTS_DISCINT_Msk // Disconnect detected interrupt */ +#define GINTSTS_DISCINT_Msk (0x1UL << GINTSTS_DISCINT_Pos) // 0x20000000 +#define GINTSTS_DISCINT GINTSTS_DISCINT_Msk // Disconnect detected interrupt #define GINTSTS_SRQINT_Pos (30U) -#define GINTSTS_SRQINT_Msk (0x1UL << GINTSTS_SRQINT_Pos) // 0x40000000 */ -#define GINTSTS_SRQINT GINTSTS_SRQINT_Msk // Session request/new session detected interrupt */ +#define GINTSTS_SRQINT_Msk (0x1UL << GINTSTS_SRQINT_Pos) // 0x40000000 +#define GINTSTS_SRQINT GINTSTS_SRQINT_Msk // Session request/new session detected interrupt #define GINTSTS_WKUINT_Pos (31U) -#define GINTSTS_WKUINT_Msk (0x1UL << GINTSTS_WKUINT_Pos) // 0x80000000 */ -#define GINTSTS_WKUINT GINTSTS_WKUINT_Msk // Resume/remote wakeup detected interrupt */ +#define GINTSTS_WKUINT_Msk (0x1UL << GINTSTS_WKUINT_Pos) // 0x80000000 +#define GINTSTS_WKUINT GINTSTS_WKUINT_Msk // Resume/remote wakeup detected interrupt /******************** Bit definition for GINTMSK register ********************/ #define GINTMSK_MMISM_Pos (1U) -#define GINTMSK_MMISM_Msk (0x1UL << GINTMSK_MMISM_Pos) // 0x00000002 */ -#define GINTMSK_MMISM GINTMSK_MMISM_Msk // Mode mismatch interrupt mask */ +#define GINTMSK_MMISM_Msk (0x1UL << GINTMSK_MMISM_Pos) // 0x00000002 +#define GINTMSK_MMISM GINTMSK_MMISM_Msk // Mode mismatch interrupt mask #define GINTMSK_OTGINT_Pos (2U) -#define GINTMSK_OTGINT_Msk (0x1UL << GINTMSK_OTGINT_Pos) // 0x00000004 */ -#define GINTMSK_OTGINT GINTMSK_OTGINT_Msk // OTG interrupt mask */ +#define GINTMSK_OTGINT_Msk (0x1UL << GINTMSK_OTGINT_Pos) // 0x00000004 +#define GINTMSK_OTGINT GINTMSK_OTGINT_Msk // OTG interrupt mask #define GINTMSK_SOFM_Pos (3U) -#define GINTMSK_SOFM_Msk (0x1UL << GINTMSK_SOFM_Pos) // 0x00000008 */ -#define GINTMSK_SOFM GINTMSK_SOFM_Msk // Start of frame mask */ +#define GINTMSK_SOFM_Msk (0x1UL << GINTMSK_SOFM_Pos) // 0x00000008 +#define GINTMSK_SOFM GINTMSK_SOFM_Msk // Start of frame mask #define GINTMSK_RXFLVLM_Pos (4U) -#define GINTMSK_RXFLVLM_Msk (0x1UL << GINTMSK_RXFLVLM_Pos) // 0x00000010 */ -#define GINTMSK_RXFLVLM GINTMSK_RXFLVLM_Msk // Receive FIFO nonempty mask */ +#define GINTMSK_RXFLVLM_Msk (0x1UL << GINTMSK_RXFLVLM_Pos) // 0x00000010 +#define GINTMSK_RXFLVLM GINTMSK_RXFLVLM_Msk // Receive FIFO nonempty mask #define GINTMSK_NPTXFEM_Pos (5U) -#define GINTMSK_NPTXFEM_Msk (0x1UL << GINTMSK_NPTXFEM_Pos) // 0x00000020 */ -#define GINTMSK_NPTXFEM GINTMSK_NPTXFEM_Msk // Nonperiodic TxFIFO empty mask */ +#define GINTMSK_NPTXFEM_Msk (0x1UL << GINTMSK_NPTXFEM_Pos) // 0x00000020 +#define GINTMSK_NPTXFEM GINTMSK_NPTXFEM_Msk // Nonperiodic TxFIFO empty mask #define GINTMSK_GINAKEFFM_Pos (6U) -#define GINTMSK_GINAKEFFM_Msk (0x1UL << GINTMSK_GINAKEFFM_Pos) // 0x00000040 */ -#define GINTMSK_GINAKEFFM GINTMSK_GINAKEFFM_Msk // Global nonperiodic IN NAK effective mask */ +#define GINTMSK_GINAKEFFM_Msk (0x1UL << GINTMSK_GINAKEFFM_Pos) // 0x00000040 +#define GINTMSK_GINAKEFFM GINTMSK_GINAKEFFM_Msk // Global nonperiodic IN NAK effective mask #define GINTMSK_GONAKEFFM_Pos (7U) -#define GINTMSK_GONAKEFFM_Msk (0x1UL << GINTMSK_GONAKEFFM_Pos) // 0x00000080 */ -#define GINTMSK_GONAKEFFM GINTMSK_GONAKEFFM_Msk // Global OUT NAK effective mask */ +#define GINTMSK_GONAKEFFM_Msk (0x1UL << GINTMSK_GONAKEFFM_Pos) // 0x00000080 +#define GINTMSK_GONAKEFFM GINTMSK_GONAKEFFM_Msk // Global OUT NAK effective mask #define GINTMSK_ESUSPM_Pos (10U) -#define GINTMSK_ESUSPM_Msk (0x1UL << GINTMSK_ESUSPM_Pos) // 0x00000400 */ -#define GINTMSK_ESUSPM GINTMSK_ESUSPM_Msk // Early suspend mask */ +#define GINTMSK_ESUSPM_Msk (0x1UL << GINTMSK_ESUSPM_Pos) // 0x00000400 +#define GINTMSK_ESUSPM GINTMSK_ESUSPM_Msk // Early suspend mask #define GINTMSK_USBSUSPM_Pos (11U) -#define GINTMSK_USBSUSPM_Msk (0x1UL << GINTMSK_USBSUSPM_Pos) // 0x00000800 */ -#define GINTMSK_USBSUSPM GINTMSK_USBSUSPM_Msk // USB suspend mask */ +#define GINTMSK_USBSUSPM_Msk (0x1UL << GINTMSK_USBSUSPM_Pos) // 0x00000800 +#define GINTMSK_USBSUSPM GINTMSK_USBSUSPM_Msk // USB suspend mask #define GINTMSK_USBRST_Pos (12U) -#define GINTMSK_USBRST_Msk (0x1UL << GINTMSK_USBRST_Pos) // 0x00001000 */ -#define GINTMSK_USBRST GINTMSK_USBRST_Msk // USB reset mask */ +#define GINTMSK_USBRST_Msk (0x1UL << GINTMSK_USBRST_Pos) // 0x00001000 +#define GINTMSK_USBRST GINTMSK_USBRST_Msk // USB reset mask #define GINTMSK_ENUMDNEM_Pos (13U) -#define GINTMSK_ENUMDNEM_Msk (0x1UL << GINTMSK_ENUMDNEM_Pos) // 0x00002000 */ -#define GINTMSK_ENUMDNEM GINTMSK_ENUMDNEM_Msk // Enumeration done mask */ +#define GINTMSK_ENUMDNEM_Msk (0x1UL << GINTMSK_ENUMDNEM_Pos) // 0x00002000 +#define GINTMSK_ENUMDNEM GINTMSK_ENUMDNEM_Msk // Enumeration done mask #define GINTMSK_ISOODRPM_Pos (14U) -#define GINTMSK_ISOODRPM_Msk (0x1UL << GINTMSK_ISOODRPM_Pos) // 0x00004000 */ -#define GINTMSK_ISOODRPM GINTMSK_ISOODRPM_Msk // Isochronous OUT packet dropped interrupt mask */ +#define GINTMSK_ISOODRPM_Msk (0x1UL << GINTMSK_ISOODRPM_Pos) // 0x00004000 +#define GINTMSK_ISOODRPM GINTMSK_ISOODRPM_Msk // Isochronous OUT packet dropped interrupt mask #define GINTMSK_EOPFM_Pos (15U) -#define GINTMSK_EOPFM_Msk (0x1UL << GINTMSK_EOPFM_Pos) // 0x00008000 */ -#define GINTMSK_EOPFM GINTMSK_EOPFM_Msk // End of periodic frame interrupt mask */ +#define GINTMSK_EOPFM_Msk (0x1UL << GINTMSK_EOPFM_Pos) // 0x00008000 +#define GINTMSK_EOPFM GINTMSK_EOPFM_Msk // End of periodic frame interrupt mask #define GINTMSK_EPMISM_Pos (17U) -#define GINTMSK_EPMISM_Msk (0x1UL << GINTMSK_EPMISM_Pos) // 0x00020000 */ -#define GINTMSK_EPMISM GINTMSK_EPMISM_Msk // Endpoint mismatch interrupt mask */ +#define GINTMSK_EPMISM_Msk (0x1UL << GINTMSK_EPMISM_Pos) // 0x00020000 +#define GINTMSK_EPMISM GINTMSK_EPMISM_Msk // Endpoint mismatch interrupt mask #define GINTMSK_IEPINT_Pos (18U) -#define GINTMSK_IEPINT_Msk (0x1UL << GINTMSK_IEPINT_Pos) // 0x00040000 */ -#define GINTMSK_IEPINT GINTMSK_IEPINT_Msk // IN endpoints interrupt mask */ +#define GINTMSK_IEPINT_Msk (0x1UL << GINTMSK_IEPINT_Pos) // 0x00040000 +#define GINTMSK_IEPINT GINTMSK_IEPINT_Msk // IN endpoints interrupt mask #define GINTMSK_OEPINT_Pos (19U) -#define GINTMSK_OEPINT_Msk (0x1UL << GINTMSK_OEPINT_Pos) // 0x00080000 */ -#define GINTMSK_OEPINT GINTMSK_OEPINT_Msk // OUT endpoints interrupt mask */ +#define GINTMSK_OEPINT_Msk (0x1UL << GINTMSK_OEPINT_Pos) // 0x00080000 +#define GINTMSK_OEPINT GINTMSK_OEPINT_Msk // OUT endpoints interrupt mask #define GINTMSK_IISOIXFRM_Pos (20U) -#define GINTMSK_IISOIXFRM_Msk (0x1UL << GINTMSK_IISOIXFRM_Pos) // 0x00100000 */ -#define GINTMSK_IISOIXFRM GINTMSK_IISOIXFRM_Msk // Incomplete isochronous IN transfer mask */ +#define GINTMSK_IISOIXFRM_Msk (0x1UL << GINTMSK_IISOIXFRM_Pos) // 0x00100000 +#define GINTMSK_IISOIXFRM GINTMSK_IISOIXFRM_Msk // Incomplete isochronous IN transfer mask #define GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos) // 0x00200000 */ -#define GINTMSK_PXFRM_IISOOXFRM GINTMSK_PXFRM_IISOOXFRM_Msk // Incomplete periodic transfer mask */ +#define GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos) // 0x00200000 +#define GINTMSK_PXFRM_IISOOXFRM GINTMSK_PXFRM_IISOOXFRM_Msk // Incomplete periodic transfer mask #define GINTMSK_FSUSPM_Pos (22U) -#define GINTMSK_FSUSPM_Msk (0x1UL << GINTMSK_FSUSPM_Pos) // 0x00400000 */ -#define GINTMSK_FSUSPM GINTMSK_FSUSPM_Msk // Data fetch suspended mask */ +#define GINTMSK_FSUSPM_Msk (0x1UL << GINTMSK_FSUSPM_Pos) // 0x00400000 +#define GINTMSK_FSUSPM GINTMSK_FSUSPM_Msk // Data fetch suspended mask #define GINTMSK_RSTDEM_Pos (23U) -#define GINTMSK_RSTDEM_Msk (0x1UL << GINTMSK_RSTDEM_Pos) // 0x00800000 */ -#define GINTMSK_RSTDEM GINTMSK_RSTDEM_Msk // Reset detected interrupt mask */ +#define GINTMSK_RSTDEM_Msk (0x1UL << GINTMSK_RSTDEM_Pos) // 0x00800000 +#define GINTMSK_RSTDEM GINTMSK_RSTDEM_Msk // Reset detected interrupt mask #define GINTMSK_PRTIM_Pos (24U) -#define GINTMSK_PRTIM_Msk (0x1UL << GINTMSK_PRTIM_Pos) // 0x01000000 */ -#define GINTMSK_PRTIM GINTMSK_PRTIM_Msk // Host port interrupt mask */ +#define GINTMSK_PRTIM_Msk (0x1UL << GINTMSK_PRTIM_Pos) // 0x01000000 +#define GINTMSK_PRTIM GINTMSK_PRTIM_Msk // Host port interrupt mask #define GINTMSK_HCIM_Pos (25U) -#define GINTMSK_HCIM_Msk (0x1UL << GINTMSK_HCIM_Pos) // 0x02000000 */ -#define GINTMSK_HCIM GINTMSK_HCIM_Msk // Host channels interrupt mask */ +#define GINTMSK_HCIM_Msk (0x1UL << GINTMSK_HCIM_Pos) // 0x02000000 +#define GINTMSK_HCIM GINTMSK_HCIM_Msk // Host channels interrupt mask #define GINTMSK_PTXFEM_Pos (26U) -#define GINTMSK_PTXFEM_Msk (0x1UL << GINTMSK_PTXFEM_Pos) // 0x04000000 */ -#define GINTMSK_PTXFEM GINTMSK_PTXFEM_Msk // Periodic TxFIFO empty mask */ +#define GINTMSK_PTXFEM_Msk (0x1UL << GINTMSK_PTXFEM_Pos) // 0x04000000 +#define GINTMSK_PTXFEM GINTMSK_PTXFEM_Msk // Periodic TxFIFO empty mask #define GINTMSK_LPMINTM_Pos (27U) -#define GINTMSK_LPMINTM_Msk (0x1UL << GINTMSK_LPMINTM_Pos) // 0x08000000 */ -#define GINTMSK_LPMINTM GINTMSK_LPMINTM_Msk // LPM interrupt Mask */ +#define GINTMSK_LPMINTM_Msk (0x1UL << GINTMSK_LPMINTM_Pos) // 0x08000000 +#define GINTMSK_LPMINTM GINTMSK_LPMINTM_Msk // LPM interrupt Mask #define GINTMSK_CIDSCHGM_Pos (28U) -#define GINTMSK_CIDSCHGM_Msk (0x1UL << GINTMSK_CIDSCHGM_Pos) // 0x10000000 */ -#define GINTMSK_CIDSCHGM GINTMSK_CIDSCHGM_Msk // Connector ID status change mask */ +#define GINTMSK_CIDSCHGM_Msk (0x1UL << GINTMSK_CIDSCHGM_Pos) // 0x10000000 +#define GINTMSK_CIDSCHGM GINTMSK_CIDSCHGM_Msk // Connector ID status change mask #define GINTMSK_DISCINT_Pos (29U) -#define GINTMSK_DISCINT_Msk (0x1UL << GINTMSK_DISCINT_Pos) // 0x20000000 */ -#define GINTMSK_DISCINT GINTMSK_DISCINT_Msk // Disconnect detected interrupt mask */ +#define GINTMSK_DISCINT_Msk (0x1UL << GINTMSK_DISCINT_Pos) // 0x20000000 +#define GINTMSK_DISCINT GINTMSK_DISCINT_Msk // Disconnect detected interrupt mask #define GINTMSK_SRQIM_Pos (30U) -#define GINTMSK_SRQIM_Msk (0x1UL << GINTMSK_SRQIM_Pos) // 0x40000000 */ -#define GINTMSK_SRQIM GINTMSK_SRQIM_Msk // Session request/new session detected interrupt mask */ +#define GINTMSK_SRQIM_Msk (0x1UL << GINTMSK_SRQIM_Pos) // 0x40000000 +#define GINTMSK_SRQIM GINTMSK_SRQIM_Msk // Session request/new session detected interrupt mask #define GINTMSK_WUIM_Pos (31U) -#define GINTMSK_WUIM_Msk (0x1UL << GINTMSK_WUIM_Pos) // 0x80000000 */ -#define GINTMSK_WUIM GINTMSK_WUIM_Msk // Resume/remote wakeup detected interrupt mask */ +#define GINTMSK_WUIM_Msk (0x1UL << GINTMSK_WUIM_Pos) // 0x80000000 +#define GINTMSK_WUIM GINTMSK_WUIM_Msk // Resume/remote wakeup detected interrupt mask /******************** Bit definition for DAINT register ********************/ #define DAINT_IEPINT_Pos (0U) -#define DAINT_IEPINT_Msk (0xFFFFUL << DAINT_IEPINT_Pos) // 0x0000FFFF */ -#define DAINT_IEPINT DAINT_IEPINT_Msk // IN endpoint interrupt bits */ +#define DAINT_IEPINT_Msk (0xFFFFUL << DAINT_IEPINT_Pos) // 0x0000FFFF +#define DAINT_IEPINT DAINT_IEPINT_Msk // IN endpoint interrupt bits #define DAINT_OEPINT_Pos (16U) -#define DAINT_OEPINT_Msk (0xFFFFUL << DAINT_OEPINT_Pos) // 0xFFFF0000 */ -#define DAINT_OEPINT DAINT_OEPINT_Msk // OUT endpoint interrupt bits */ +#define DAINT_OEPINT_Msk (0xFFFFUL << DAINT_OEPINT_Pos) // 0xFFFF0000 +#define DAINT_OEPINT DAINT_OEPINT_Msk // OUT endpoint interrupt bits /******************** Bit definition for HAINTMSK register ********************/ #define HAINTMSK_HAINTM_Pos (0U) -#define HAINTMSK_HAINTM_Msk (0xFFFFUL << HAINTMSK_HAINTM_Pos) // 0x0000FFFF */ -#define HAINTMSK_HAINTM HAINTMSK_HAINTM_Msk // Channel interrupt mask */ +#define HAINTMSK_HAINTM_Msk (0xFFFFUL << HAINTMSK_HAINTM_Pos) // 0x0000FFFF +#define HAINTMSK_HAINTM HAINTMSK_HAINTM_Msk // Channel interrupt mask /******************** Bit definition for GRXSTSP register ********************/ #define GRXSTSP_EPNUM_Pos (0U) -#define GRXSTSP_EPNUM_Msk (0xFUL << GRXSTSP_EPNUM_Pos) // 0x0000000F */ -#define GRXSTSP_EPNUM GRXSTSP_EPNUM_Msk // IN EP interrupt mask bits */ +#define GRXSTSP_EPNUM_Msk (0xFUL << GRXSTSP_EPNUM_Pos) // 0x0000000F +#define GRXSTSP_EPNUM GRXSTSP_EPNUM_Msk // IN EP interrupt mask bits #define GRXSTSP_BCNT_Pos (4U) -#define GRXSTSP_BCNT_Msk (0x7FFUL << GRXSTSP_BCNT_Pos) // 0x00007FF0 */ -#define GRXSTSP_BCNT GRXSTSP_BCNT_Msk // OUT EP interrupt mask bits */ +#define GRXSTSP_BCNT_Msk (0x7FFUL << GRXSTSP_BCNT_Pos) // 0x00007FF0 +#define GRXSTSP_BCNT GRXSTSP_BCNT_Msk // OUT EP interrupt mask bits #define GRXSTSP_DPID_Pos (15U) -#define GRXSTSP_DPID_Msk (0x3UL << GRXSTSP_DPID_Pos) // 0x00018000 */ -#define GRXSTSP_DPID GRXSTSP_DPID_Msk // OUT EP interrupt mask bits */ +#define GRXSTSP_DPID_Msk (0x3UL << GRXSTSP_DPID_Pos) // 0x00018000 +#define GRXSTSP_DPID GRXSTSP_DPID_Msk // OUT EP interrupt mask bits #define GRXSTSP_PKTSTS_Pos (17U) -#define GRXSTSP_PKTSTS_Msk (0xFUL << GRXSTSP_PKTSTS_Pos) // 0x001E0000 */ -#define GRXSTSP_PKTSTS GRXSTSP_PKTSTS_Msk // OUT EP interrupt mask bits */ +#define GRXSTSP_PKTSTS_Msk (0xFUL << GRXSTSP_PKTSTS_Pos) // 0x001E0000 +#define GRXSTSP_PKTSTS GRXSTSP_PKTSTS_Msk // OUT EP interrupt mask bits #define GRXSTS_PKTSTS_GLOBALOUTNAK 1 #define GRXSTS_PKTSTS_OUTRX 2 @@ -934,773 +934,803 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); /******************** Bit definition for DAINTMSK register ********************/ #define DAINTMSK_IEPM_Pos (0U) -#define DAINTMSK_IEPM_Msk (0xFFFFUL << DAINTMSK_IEPM_Pos) // 0x0000FFFF */ -#define DAINTMSK_IEPM DAINTMSK_IEPM_Msk // IN EP interrupt mask bits */ +#define DAINTMSK_IEPM_Msk (0xFFFFUL << DAINTMSK_IEPM_Pos) // 0x0000FFFF +#define DAINTMSK_IEPM DAINTMSK_IEPM_Msk // IN EP interrupt mask bits #define DAINTMSK_OEPM_Pos (16U) -#define DAINTMSK_OEPM_Msk (0xFFFFUL << DAINTMSK_OEPM_Pos) // 0xFFFF0000 */ -#define DAINTMSK_OEPM DAINTMSK_OEPM_Msk // OUT EP interrupt mask bits */ +#define DAINTMSK_OEPM_Msk (0xFFFFUL << DAINTMSK_OEPM_Pos) // 0xFFFF0000 +#define DAINTMSK_OEPM DAINTMSK_OEPM_Msk // OUT EP interrupt mask bits #if 0 /******************** Bit definition for OTG register ********************/ #define CHNUM_Pos (0U) -#define CHNUM_Msk (0xFUL << CHNUM_Pos) // 0x0000000F */ -#define CHNUM CHNUM_Msk // Channel number */ -#define CHNUM_0 (0x1UL << CHNUM_Pos) // 0x00000001 */ -#define CHNUM_1 (0x2UL << CHNUM_Pos) // 0x00000002 */ -#define CHNUM_2 (0x4UL << CHNUM_Pos) // 0x00000004 */ -#define CHNUM_3 (0x8UL << CHNUM_Pos) // 0x00000008 */ +#define CHNUM_Msk (0xFUL << CHNUM_Pos) // 0x0000000F +#define CHNUM CHNUM_Msk // Channel number +#define CHNUM_0 (0x1UL << CHNUM_Pos) // 0x00000001 +#define CHNUM_1 (0x2UL << CHNUM_Pos) // 0x00000002 +#define CHNUM_2 (0x4UL << CHNUM_Pos) // 0x00000004 +#define CHNUM_3 (0x8UL << CHNUM_Pos) // 0x00000008 #define BCNT_Pos (4U) -#define BCNT_Msk (0x7FFUL << BCNT_Pos) // 0x00007FF0 */ -#define BCNT BCNT_Msk // Byte count */ +#define BCNT_Msk (0x7FFUL << BCNT_Pos) // 0x00007FF0 +#define BCNT BCNT_Msk // Byte count #define DPID_Pos (15U) -#define DPID_Msk (0x3UL << DPID_Pos) // 0x00018000 */ -#define DPID DPID_Msk // Data PID */ -#define DPID_0 (0x1UL << DPID_Pos) // 0x00008000 */ -#define DPID_1 (0x2UL << DPID_Pos) // 0x00010000 */ +#define DPID_Msk (0x3UL << DPID_Pos) // 0x00018000 +#define DPID DPID_Msk // Data PID +#define DPID_0 (0x1UL << DPID_Pos) // 0x00008000 +#define DPID_1 (0x2UL << DPID_Pos) // 0x00010000 #define PKTSTS_Pos (17U) -#define PKTSTS_Msk (0xFUL << PKTSTS_Pos) // 0x001E0000 */ -#define PKTSTS PKTSTS_Msk // Packet status */ -#define PKTSTS_0 (0x1UL << PKTSTS_Pos) // 0x00020000 */ -#define PKTSTS_1 (0x2UL << PKTSTS_Pos) // 0x00040000 */ -#define PKTSTS_2 (0x4UL << PKTSTS_Pos) // 0x00080000 */ -#define PKTSTS_3 (0x8UL << PKTSTS_Pos) // 0x00100000 */ +#define PKTSTS_Msk (0xFUL << PKTSTS_Pos) // 0x001E0000 +#define PKTSTS PKTSTS_Msk // Packet status +#define PKTSTS_0 (0x1UL << PKTSTS_Pos) // 0x00020000 +#define PKTSTS_1 (0x2UL << PKTSTS_Pos) // 0x00040000 +#define PKTSTS_2 (0x4UL << PKTSTS_Pos) // 0x00080000 +#define PKTSTS_3 (0x8UL << PKTSTS_Pos) // 0x00100000 #define EPNUM_Pos (0U) -#define EPNUM_Msk (0xFUL << EPNUM_Pos) // 0x0000000F */ -#define EPNUM EPNUM_Msk // Endpoint number */ -#define EPNUM_0 (0x1UL << EPNUM_Pos) // 0x00000001 */ -#define EPNUM_1 (0x2UL << EPNUM_Pos) // 0x00000002 */ -#define EPNUM_2 (0x4UL << EPNUM_Pos) // 0x00000004 */ -#define EPNUM_3 (0x8UL << EPNUM_Pos) // 0x00000008 */ +#define EPNUM_Msk (0xFUL << EPNUM_Pos) // 0x0000000F +#define EPNUM EPNUM_Msk // Endpoint number +#define EPNUM_0 (0x1UL << EPNUM_Pos) // 0x00000001 +#define EPNUM_1 (0x2UL << EPNUM_Pos) // 0x00000002 +#define EPNUM_2 (0x4UL << EPNUM_Pos) // 0x00000004 +#define EPNUM_3 (0x8UL << EPNUM_Pos) // 0x00000008 #define FRMNUM_Pos (21U) -#define FRMNUM_Msk (0xFUL << FRMNUM_Pos) // 0x01E00000 */ -#define FRMNUM FRMNUM_Msk // Frame number */ -#define FRMNUM_0 (0x1UL << FRMNUM_Pos) // 0x00200000 */ -#define FRMNUM_1 (0x2UL << FRMNUM_Pos) // 0x00400000 */ -#define FRMNUM_2 (0x4UL << FRMNUM_Pos) // 0x00800000 */ -#define FRMNUM_3 (0x8UL << FRMNUM_Pos) // 0x01000000 */ +#define FRMNUM_Msk (0xFUL << FRMNUM_Pos) // 0x01E00000 +#define FRMNUM FRMNUM_Msk // Frame number +#define FRMNUM_0 (0x1UL << FRMNUM_Pos) // 0x00200000 +#define FRMNUM_1 (0x2UL << FRMNUM_Pos) // 0x00400000 +#define FRMNUM_2 (0x4UL << FRMNUM_Pos) // 0x00800000 +#define FRMNUM_3 (0x8UL << FRMNUM_Pos) // 0x01000000 #endif /******************** Bit definition for GRXFSIZ register ********************/ #define GRXFSIZ_RXFD_Pos (0U) -#define GRXFSIZ_RXFD_Msk (0xFFFFUL << GRXFSIZ_RXFD_Pos) // 0x0000FFFF */ -#define GRXFSIZ_RXFD GRXFSIZ_RXFD_Msk // RxFIFO depth */ +#define GRXFSIZ_RXFD_Msk (0xFFFFUL << GRXFSIZ_RXFD_Pos) // 0x0000FFFF +#define GRXFSIZ_RXFD GRXFSIZ_RXFD_Msk // RxFIFO depth /******************** Bit definition for DVBUSDIS register ********************/ #define DVBUSDIS_VBUSDT_Pos (0U) -#define DVBUSDIS_VBUSDT_Msk (0xFFFFUL << DVBUSDIS_VBUSDT_Pos) // 0x0000FFFF */ -#define DVBUSDIS_VBUSDT DVBUSDIS_VBUSDT_Msk // Device VBUS discharge time */ +#define DVBUSDIS_VBUSDT_Msk (0xFFFFUL << DVBUSDIS_VBUSDT_Pos) // 0x0000FFFF +#define DVBUSDIS_VBUSDT DVBUSDIS_VBUSDT_Msk // Device VBUS discharge time /******************** Bit definition for OTG register ********************/ #define GNPTXFSIZ_NPTXFSA_Pos (0U) -#define GNPTXFSIZ_NPTXFSA_Msk (0xFFFFUL << GNPTXFSIZ_NPTXFSA_Pos) // 0x0000FFFF */ -#define GNPTXFSIZ_NPTXFSA GNPTXFSIZ_NPTXFSA_Msk // Nonperiodic transmit RAM start address */ +#define GNPTXFSIZ_NPTXFSA_Msk (0xFFFFUL << GNPTXFSIZ_NPTXFSA_Pos) // 0x0000FFFF +#define GNPTXFSIZ_NPTXFSA GNPTXFSIZ_NPTXFSA_Msk // Nonperiodic transmit RAM start address #define GNPTXFSIZ_NPTXFD_Pos (16U) -#define GNPTXFSIZ_NPTXFD_Msk (0xFFFFUL << GNPTXFSIZ_NPTXFD_Pos) // 0xFFFF0000 */ -#define GNPTXFSIZ_NPTXFD GNPTXFSIZ_NPTXFD_Msk // Nonperiodic TxFIFO depth */ +#define GNPTXFSIZ_NPTXFD_Msk (0xFFFFUL << GNPTXFSIZ_NPTXFD_Pos) // 0xFFFF0000 +#define GNPTXFSIZ_NPTXFD GNPTXFSIZ_NPTXFD_Msk // Nonperiodic TxFIFO depth #define DIEPTXF0_TX0FSA_Pos (0U) -#define DIEPTXF0_TX0FSA_Msk (0xFFFFUL << DIEPTXF0_TX0FSA_Pos) // 0x0000FFFF */ -#define DIEPTXF0_TX0FSA DIEPTXF0_TX0FSA_Msk // Endpoint 0 transmit RAM start address */ +#define DIEPTXF0_TX0FSA_Msk (0xFFFFUL << DIEPTXF0_TX0FSA_Pos) // 0x0000FFFF +#define DIEPTXF0_TX0FSA DIEPTXF0_TX0FSA_Msk // Endpoint 0 transmit RAM start address #define DIEPTXF0_TX0FD_Pos (16U) -#define DIEPTXF0_TX0FD_Msk (0xFFFFUL << DIEPTXF0_TX0FD_Pos) // 0xFFFF0000 */ -#define DIEPTXF0_TX0FD DIEPTXF0_TX0FD_Msk // Endpoint 0 TxFIFO depth */ +#define DIEPTXF0_TX0FD_Msk (0xFFFFUL << DIEPTXF0_TX0FD_Pos) // 0xFFFF0000 +#define DIEPTXF0_TX0FD DIEPTXF0_TX0FD_Msk // Endpoint 0 TxFIFO depth /******************** Bit definition for DVBUSPULSE register ********************/ #define DVBUSPULSE_DVBUSP_Pos (0U) -#define DVBUSPULSE_DVBUSP_Msk (0xFFFUL << DVBUSPULSE_DVBUSP_Pos) // 0x00000FFF */ -#define DVBUSPULSE_DVBUSP DVBUSPULSE_DVBUSP_Msk // Device VBUS pulsing time */ +#define DVBUSPULSE_DVBUSP_Msk (0xFFFUL << DVBUSPULSE_DVBUSP_Pos) // 0x00000FFF +#define DVBUSPULSE_DVBUSP DVBUSPULSE_DVBUSP_Msk // Device VBUS pulsing time /******************** Bit definition for GNPTXSTS register ********************/ #define GNPTXSTS_NPTXFSAV_Pos (0U) -#define GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos) // 0x0000FFFF */ -#define GNPTXSTS_NPTXFSAV GNPTXSTS_NPTXFSAV_Msk // Nonperiodic TxFIFO space available */ +#define GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos) // 0x0000FFFF +#define GNPTXSTS_NPTXFSAV GNPTXSTS_NPTXFSAV_Msk // Nonperiodic TxFIFO space available #define GNPTXSTS_NPTQXSAV_Pos (16U) -#define GNPTXSTS_NPTQXSAV_Msk (0xFFUL << GNPTXSTS_NPTQXSAV_Pos) // 0x00FF0000 */ -#define GNPTXSTS_NPTQXSAV GNPTXSTS_NPTQXSAV_Msk // Nonperiodic transmit request queue space available */ -#define GNPTXSTS_NPTQXSAV_0 (0x01UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00010000 */ -#define GNPTXSTS_NPTQXSAV_1 (0x02UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00020000 */ -#define GNPTXSTS_NPTQXSAV_2 (0x04UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00040000 */ -#define GNPTXSTS_NPTQXSAV_3 (0x08UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00080000 */ -#define GNPTXSTS_NPTQXSAV_4 (0x10UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00100000 */ -#define GNPTXSTS_NPTQXSAV_5 (0x20UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00200000 */ -#define GNPTXSTS_NPTQXSAV_6 (0x40UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00400000 */ -#define GNPTXSTS_NPTQXSAV_7 (0x80UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00800000 */ +#define GNPTXSTS_NPTQXSAV_Msk (0xFFUL << GNPTXSTS_NPTQXSAV_Pos) // 0x00FF0000 +#define GNPTXSTS_NPTQXSAV GNPTXSTS_NPTQXSAV_Msk // Nonperiodic transmit request queue space available +#define GNPTXSTS_NPTQXSAV_0 (0x01UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00010000 +#define GNPTXSTS_NPTQXSAV_1 (0x02UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00020000 +#define GNPTXSTS_NPTQXSAV_2 (0x04UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00040000 +#define GNPTXSTS_NPTQXSAV_3 (0x08UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00080000 +#define GNPTXSTS_NPTQXSAV_4 (0x10UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00100000 +#define GNPTXSTS_NPTQXSAV_5 (0x20UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00200000 +#define GNPTXSTS_NPTQXSAV_6 (0x40UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00400000 +#define GNPTXSTS_NPTQXSAV_7 (0x80UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00800000 #define GNPTXSTS_NPTXQTOP_Pos (24U) -#define GNPTXSTS_NPTXQTOP_Msk (0x7FUL << GNPTXSTS_NPTXQTOP_Pos) // 0x7F000000 */ -#define GNPTXSTS_NPTXQTOP GNPTXSTS_NPTXQTOP_Msk // Top of the nonperiodic transmit request queue */ -#define GNPTXSTS_NPTXQTOP_0 (0x01UL << GNPTXSTS_NPTXQTOP_Pos) // 0x01000000 */ -#define GNPTXSTS_NPTXQTOP_1 (0x02UL << GNPTXSTS_NPTXQTOP_Pos) // 0x02000000 */ -#define GNPTXSTS_NPTXQTOP_2 (0x04UL << GNPTXSTS_NPTXQTOP_Pos) // 0x04000000 */ -#define GNPTXSTS_NPTXQTOP_3 (0x08UL << GNPTXSTS_NPTXQTOP_Pos) // 0x08000000 */ -#define GNPTXSTS_NPTXQTOP_4 (0x10UL << GNPTXSTS_NPTXQTOP_Pos) // 0x10000000 */ -#define GNPTXSTS_NPTXQTOP_5 (0x20UL << GNPTXSTS_NPTXQTOP_Pos) // 0x20000000 */ -#define GNPTXSTS_NPTXQTOP_6 (0x40UL << GNPTXSTS_NPTXQTOP_Pos) // 0x40000000 */ +#define GNPTXSTS_NPTXQTOP_Msk (0x7FUL << GNPTXSTS_NPTXQTOP_Pos) // 0x7F000000 +#define GNPTXSTS_NPTXQTOP GNPTXSTS_NPTXQTOP_Msk // Top of the nonperiodic transmit request queue +#define GNPTXSTS_NPTXQTOP_0 (0x01UL << GNPTXSTS_NPTXQTOP_Pos) // 0x01000000 +#define GNPTXSTS_NPTXQTOP_1 (0x02UL << GNPTXSTS_NPTXQTOP_Pos) // 0x02000000 +#define GNPTXSTS_NPTXQTOP_2 (0x04UL << GNPTXSTS_NPTXQTOP_Pos) // 0x04000000 +#define GNPTXSTS_NPTXQTOP_3 (0x08UL << GNPTXSTS_NPTXQTOP_Pos) // 0x08000000 +#define GNPTXSTS_NPTXQTOP_4 (0x10UL << GNPTXSTS_NPTXQTOP_Pos) // 0x10000000 +#define GNPTXSTS_NPTXQTOP_5 (0x20UL << GNPTXSTS_NPTXQTOP_Pos) // 0x20000000 +#define GNPTXSTS_NPTXQTOP_6 (0x40UL << GNPTXSTS_NPTXQTOP_Pos) // 0x40000000 /******************** Bit definition for DTHRCTL register ********************/ #define DTHRCTL_NONISOTHREN_Pos (0U) -#define DTHRCTL_NONISOTHREN_Msk (0x1UL << DTHRCTL_NONISOTHREN_Pos) // 0x00000001 */ -#define DTHRCTL_NONISOTHREN DTHRCTL_NONISOTHREN_Msk // Nonisochronous IN endpoints threshold enable */ +#define DTHRCTL_NONISOTHREN_Msk (0x1UL << DTHRCTL_NONISOTHREN_Pos) // 0x00000001 +#define DTHRCTL_NONISOTHREN DTHRCTL_NONISOTHREN_Msk // Nonisochronous IN endpoints threshold enable #define DTHRCTL_ISOTHREN_Pos (1U) -#define DTHRCTL_ISOTHREN_Msk (0x1UL << DTHRCTL_ISOTHREN_Pos) // 0x00000002 */ -#define DTHRCTL_ISOTHREN DTHRCTL_ISOTHREN_Msk // ISO IN endpoint threshold enable */ +#define DTHRCTL_ISOTHREN_Msk (0x1UL << DTHRCTL_ISOTHREN_Pos) // 0x00000002 +#define DTHRCTL_ISOTHREN DTHRCTL_ISOTHREN_Msk // ISO IN endpoint threshold enable #define DTHRCTL_TXTHRLEN_Pos (2U) -#define DTHRCTL_TXTHRLEN_Msk (0x1FFUL << DTHRCTL_TXTHRLEN_Pos) // 0x000007FC */ -#define DTHRCTL_TXTHRLEN DTHRCTL_TXTHRLEN_Msk // Transmit threshold length */ -#define DTHRCTL_TXTHRLEN_0 (0x001UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000004 */ -#define DTHRCTL_TXTHRLEN_1 (0x002UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000008 */ -#define DTHRCTL_TXTHRLEN_2 (0x004UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000010 */ -#define DTHRCTL_TXTHRLEN_3 (0x008UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000020 */ -#define DTHRCTL_TXTHRLEN_4 (0x010UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000040 */ -#define DTHRCTL_TXTHRLEN_5 (0x020UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000080 */ -#define DTHRCTL_TXTHRLEN_6 (0x040UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000100 */ -#define DTHRCTL_TXTHRLEN_7 (0x080UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000200 */ -#define DTHRCTL_TXTHRLEN_8 (0x100UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000400 */ +#define DTHRCTL_TXTHRLEN_Msk (0x1FFUL << DTHRCTL_TXTHRLEN_Pos) // 0x000007FC +#define DTHRCTL_TXTHRLEN DTHRCTL_TXTHRLEN_Msk // Transmit threshold length +#define DTHRCTL_TXTHRLEN_0 (0x001UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000004 +#define DTHRCTL_TXTHRLEN_1 (0x002UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000008 +#define DTHRCTL_TXTHRLEN_2 (0x004UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000010 +#define DTHRCTL_TXTHRLEN_3 (0x008UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000020 +#define DTHRCTL_TXTHRLEN_4 (0x010UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000040 +#define DTHRCTL_TXTHRLEN_5 (0x020UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000080 +#define DTHRCTL_TXTHRLEN_6 (0x040UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000100 +#define DTHRCTL_TXTHRLEN_7 (0x080UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000200 +#define DTHRCTL_TXTHRLEN_8 (0x100UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000400 #define DTHRCTL_RXTHREN_Pos (16U) -#define DTHRCTL_RXTHREN_Msk (0x1UL << DTHRCTL_RXTHREN_Pos) // 0x00010000 */ -#define DTHRCTL_RXTHREN DTHRCTL_RXTHREN_Msk // Receive threshold enable */ +#define DTHRCTL_RXTHREN_Msk (0x1UL << DTHRCTL_RXTHREN_Pos) // 0x00010000 +#define DTHRCTL_RXTHREN DTHRCTL_RXTHREN_Msk // Receive threshold enable #define DTHRCTL_RXTHRLEN_Pos (17U) -#define DTHRCTL_RXTHRLEN_Msk (0x1FFUL << DTHRCTL_RXTHRLEN_Pos) // 0x03FE0000 */ -#define DTHRCTL_RXTHRLEN DTHRCTL_RXTHRLEN_Msk // Receive threshold length */ -#define DTHRCTL_RXTHRLEN_0 (0x001UL << DTHRCTL_RXTHRLEN_Pos) // 0x00020000 */ -#define DTHRCTL_RXTHRLEN_1 (0x002UL << DTHRCTL_RXTHRLEN_Pos) // 0x00040000 */ -#define DTHRCTL_RXTHRLEN_2 (0x004UL << DTHRCTL_RXTHRLEN_Pos) // 0x00080000 */ -#define DTHRCTL_RXTHRLEN_3 (0x008UL << DTHRCTL_RXTHRLEN_Pos) // 0x00100000 */ -#define DTHRCTL_RXTHRLEN_4 (0x010UL << DTHRCTL_RXTHRLEN_Pos) // 0x00200000 */ -#define DTHRCTL_RXTHRLEN_5 (0x020UL << DTHRCTL_RXTHRLEN_Pos) // 0x00400000 */ -#define DTHRCTL_RXTHRLEN_6 (0x040UL << DTHRCTL_RXTHRLEN_Pos) // 0x00800000 */ -#define DTHRCTL_RXTHRLEN_7 (0x080UL << DTHRCTL_RXTHRLEN_Pos) // 0x01000000 */ -#define DTHRCTL_RXTHRLEN_8 (0x100UL << DTHRCTL_RXTHRLEN_Pos) // 0x02000000 */ +#define DTHRCTL_RXTHRLEN_Msk (0x1FFUL << DTHRCTL_RXTHRLEN_Pos) // 0x03FE0000 +#define DTHRCTL_RXTHRLEN DTHRCTL_RXTHRLEN_Msk // Receive threshold length +#define DTHRCTL_RXTHRLEN_0 (0x001UL << DTHRCTL_RXTHRLEN_Pos) // 0x00020000 +#define DTHRCTL_RXTHRLEN_1 (0x002UL << DTHRCTL_RXTHRLEN_Pos) // 0x00040000 +#define DTHRCTL_RXTHRLEN_2 (0x004UL << DTHRCTL_RXTHRLEN_Pos) // 0x00080000 +#define DTHRCTL_RXTHRLEN_3 (0x008UL << DTHRCTL_RXTHRLEN_Pos) // 0x00100000 +#define DTHRCTL_RXTHRLEN_4 (0x010UL << DTHRCTL_RXTHRLEN_Pos) // 0x00200000 +#define DTHRCTL_RXTHRLEN_5 (0x020UL << DTHRCTL_RXTHRLEN_Pos) // 0x00400000 +#define DTHRCTL_RXTHRLEN_6 (0x040UL << DTHRCTL_RXTHRLEN_Pos) // 0x00800000 +#define DTHRCTL_RXTHRLEN_7 (0x080UL << DTHRCTL_RXTHRLEN_Pos) // 0x01000000 +#define DTHRCTL_RXTHRLEN_8 (0x100UL << DTHRCTL_RXTHRLEN_Pos) // 0x02000000 #define DTHRCTL_ARPEN_Pos (27U) -#define DTHRCTL_ARPEN_Msk (0x1UL << DTHRCTL_ARPEN_Pos) // 0x08000000 */ -#define DTHRCTL_ARPEN DTHRCTL_ARPEN_Msk // Arbiter parking enable */ +#define DTHRCTL_ARPEN_Msk (0x1UL << DTHRCTL_ARPEN_Pos) // 0x08000000 +#define DTHRCTL_ARPEN DTHRCTL_ARPEN_Msk // Arbiter parking enable /******************** Bit definition for DIEPEMPMSK register ********************/ #define DIEPEMPMSK_INEPTXFEM_Pos (0U) -#define DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos) // 0x0000FFFF */ -#define DIEPEMPMSK_INEPTXFEM DIEPEMPMSK_INEPTXFEM_Msk // IN EP Tx FIFO empty interrupt mask bits */ +#define DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos) // 0x0000FFFF +#define DIEPEMPMSK_INEPTXFEM DIEPEMPMSK_INEPTXFEM_Msk // IN EP Tx FIFO empty interrupt mask bits /******************** Bit definition for DEACHINT register ********************/ #define DEACHINT_IEP1INT_Pos (1U) -#define DEACHINT_IEP1INT_Msk (0x1UL << DEACHINT_IEP1INT_Pos) // 0x00000002 */ -#define DEACHINT_IEP1INT DEACHINT_IEP1INT_Msk // IN endpoint 1interrupt bit */ +#define DEACHINT_IEP1INT_Msk (0x1UL << DEACHINT_IEP1INT_Pos) // 0x00000002 +#define DEACHINT_IEP1INT DEACHINT_IEP1INT_Msk // IN endpoint 1interrupt bit #define DEACHINT_OEP1INT_Pos (17U) -#define DEACHINT_OEP1INT_Msk (0x1UL << DEACHINT_OEP1INT_Pos) // 0x00020000 */ -#define DEACHINT_OEP1INT DEACHINT_OEP1INT_Msk // OUT endpoint 1 interrupt bit */ +#define DEACHINT_OEP1INT_Msk (0x1UL << DEACHINT_OEP1INT_Pos) // 0x00020000 +#define DEACHINT_OEP1INT DEACHINT_OEP1INT_Msk // OUT endpoint 1 interrupt bit /******************** Bit definition for GCCFG register ********************/ #define STM32_GCCFG_DCDET_Pos (0U) -#define STM32_GCCFG_DCDET_Msk (0x1UL << STM32_GCCFG_DCDET_Pos) // 0x00000001 */ -#define STM32_GCCFG_DCDET STM32_GCCFG_DCDET_Msk // Data contact detection (DCD) status */ +#define STM32_GCCFG_DCDET_Msk (0x1UL << STM32_GCCFG_DCDET_Pos) // 0x00000001 +#define STM32_GCCFG_DCDET STM32_GCCFG_DCDET_Msk // Data contact detection (DCD) status + #define STM32_GCCFG_PDET_Pos (1U) -#define STM32_GCCFG_PDET_Msk (0x1UL << STM32_GCCFG_PDET_Pos) // 0x00000002 */ -#define STM32_GCCFG_PDET STM32_GCCFG_PDET_Msk // Primary detection (PD) status */ +#define STM32_GCCFG_PDET_Msk (0x1UL << STM32_GCCFG_PDET_Pos) // 0x00000002 +#define STM32_GCCFG_PDET STM32_GCCFG_PDET_Msk // Primary detection (PD) status + #define STM32_GCCFG_SDET_Pos (2U) -#define STM32_GCCFG_SDET_Msk (0x1UL << STM32_GCCFG_SDET_Pos) // 0x00000004 */ -#define STM32_GCCFG_SDET STM32_GCCFG_SDET_Msk // Secondary detection (SD) status */ +#define STM32_GCCFG_SDET_Msk (0x1UL << STM32_GCCFG_SDET_Pos) // 0x00000004 +#define STM32_GCCFG_SDET STM32_GCCFG_SDET_Msk // Secondary detection (SD) status + #define STM32_GCCFG_PS2DET_Pos (3U) -#define STM32_GCCFG_PS2DET_Msk (0x1UL << STM32_GCCFG_PS2DET_Pos) // 0x00000008 */ -#define STM32_GCCFG_PS2DET STM32_GCCFG_PS2DET_Msk // DM pull-up detection status */ +#define STM32_GCCFG_PS2DET_Msk (0x1UL << STM32_GCCFG_PS2DET_Pos) // 0x00000008 +#define STM32_GCCFG_PS2DET STM32_GCCFG_PS2DET_Msk // DM pull-up detection status + #define STM32_GCCFG_PWRDWN_Pos (16U) -#define STM32_GCCFG_PWRDWN_Msk (0x1UL << STM32_GCCFG_PWRDWN_Pos) // 0x00010000 */ -#define STM32_GCCFG_PWRDWN STM32_GCCFG_PWRDWN_Msk // Power down */ +#define STM32_GCCFG_PWRDWN_Msk (0x1UL << STM32_GCCFG_PWRDWN_Pos) // 0x00010000 +#define STM32_GCCFG_PWRDWN STM32_GCCFG_PWRDWN_Msk // Power down + #define STM32_GCCFG_BCDEN_Pos (17U) -#define STM32_GCCFG_BCDEN_Msk (0x1UL << STM32_GCCFG_BCDEN_Pos) // 0x00020000 */ -#define STM32_GCCFG_BCDEN STM32_GCCFG_BCDEN_Msk // Battery charging detector (BCD) enable */ +#define STM32_GCCFG_BCDEN_Msk (0x1UL << STM32_GCCFG_BCDEN_Pos) // 0x00020000 +#define STM32_GCCFG_BCDEN STM32_GCCFG_BCDEN_Msk // Battery charging detector (BCD) enable + #define STM32_GCCFG_DCDEN_Pos (18U) -#define STM32_GCCFG_DCDEN_Msk (0x1UL << STM32_GCCFG_DCDEN_Pos) // 0x00040000 */ +#define STM32_GCCFG_DCDEN_Msk (0x1UL << STM32_GCCFG_DCDEN_Pos) // 0x00040000 #define STM32_GCCFG_DCDEN STM32_GCCFG_DCDEN_Msk // Data contact detection (DCD) mode enable*/ + #define STM32_GCCFG_PDEN_Pos (19U) -#define STM32_GCCFG_PDEN_Msk (0x1UL << STM32_GCCFG_PDEN_Pos) // 0x00080000 */ +#define STM32_GCCFG_PDEN_Msk (0x1UL << STM32_GCCFG_PDEN_Pos) // 0x00080000 #define STM32_GCCFG_PDEN STM32_GCCFG_PDEN_Msk // Primary detection (PD) mode enable*/ + #define STM32_GCCFG_SDEN_Pos (20U) -#define STM32_GCCFG_SDEN_Msk (0x1UL << STM32_GCCFG_SDEN_Pos) // 0x00100000 */ -#define STM32_GCCFG_SDEN STM32_GCCFG_SDEN_Msk // Secondary detection (SD) mode enable */ +#define STM32_GCCFG_SDEN_Msk (0x1UL << STM32_GCCFG_SDEN_Pos) // 0x00100000 +#define STM32_GCCFG_SDEN STM32_GCCFG_SDEN_Msk // Secondary detection (SD) mode enable + #define STM32_GCCFG_VBDEN_Pos (21U) -#define STM32_GCCFG_VBDEN_Msk (0x1UL << STM32_GCCFG_VBDEN_Pos) // 0x00200000 */ -#define STM32_GCCFG_VBDEN STM32_GCCFG_VBDEN_Msk // VBUS mode enable */ +#define STM32_GCCFG_VBDEN_Msk (0x1UL << STM32_GCCFG_VBDEN_Pos) // 0x00200000 +#define STM32_GCCFG_VBDEN STM32_GCCFG_VBDEN_Msk // VBUS mode enable + #define STM32_GCCFG_OTGIDEN_Pos (22U) -#define STM32_GCCFG_OTGIDEN_Msk (0x1UL << STM32_GCCFG_OTGIDEN_Pos) // 0x00400000 */ -#define STM32_GCCFG_OTGIDEN STM32_GCCFG_OTGIDEN_Msk // OTG Id enable */ +#define STM32_GCCFG_OTGIDEN_Msk (0x1UL << STM32_GCCFG_OTGIDEN_Pos) // 0x00400000 +#define STM32_GCCFG_OTGIDEN STM32_GCCFG_OTGIDEN_Msk // OTG Id enable + #define STM32_GCCFG_PHYHSEN_Pos (23U) -#define STM32_GCCFG_PHYHSEN_Msk (0x1UL << STM32_GCCFG_PHYHSEN_Pos) // 0x00800000 */ -#define STM32_GCCFG_PHYHSEN STM32_GCCFG_PHYHSEN_Msk // HS PHY enable */ +#define STM32_GCCFG_PHYHSEN_Msk (0x1UL << STM32_GCCFG_PHYHSEN_Pos) // 0x00800000 +#define STM32_GCCFG_PHYHSEN STM32_GCCFG_PHYHSEN_Msk // HS PHY enable + +// TODO stm32u5a5 SDEN is 22nd bit, conflict with 20th bit above +//#define STM32_GCCFG_SDEN_Pos (22U) +//#define STM32_GCCFG_SDEN_Msk (0x1U << STM32_GCCFG_SDEN_Pos) // 0x00400000 +//#define STM32_GCCFG_SDEN STM32_GCCFG_SDEN_Msk // Secondary detection (PD) mode enable + +// TODO stm32u5a5 VBVALOVA is 23rd bit, conflict with PHYHSEN bit above +#define STM32_GCCFG_VBVALOVAL_Pos (23U) +#define STM32_GCCFG_VBVALOVAL_Msk (0x1U << STM32_GCCFG_VBVALOVAL_Pos) // 0x00800000 +#define STM32_GCCFG_VBVALOVAL STM32_GCCFG_VBVALOVAL_Msk // Value of VBUSVLDEXT0 femtoPHY input + +#define STM32_GCCFG_VBVALEXTOEN_Pos (24U) +#define STM32_GCCFG_VBVALEXTOEN_Msk (0x1U << STM32_GCCFG_VBVALEXTOEN_Pos) // 0x01000000 +#define STM32_GCCFG_VBVALEXTOEN STM32_GCCFG_VBVALEXTOEN_Msk // Enables of VBUSVLDEXT0 femtoPHY input override + +#define STM32_GCCFG_PULLDOWNEN_Pos (25U) +#define STM32_GCCFG_PULLDOWNEN_Msk (0x1U << STM32_GCCFG_PULLDOWNEN_Pos) // 0x02000000 +#define STM32_GCCFG_PULLDOWNEN STM32_GCCFG_PULLDOWNEN_Msk // Enables of femtoPHY pulldown resistors, used when ID PAD is disabled + /******************** Bit definition for DEACHINTMSK register ********************/ #define DEACHINTMSK_IEP1INTM_Pos (1U) -#define DEACHINTMSK_IEP1INTM_Msk (0x1UL << DEACHINTMSK_IEP1INTM_Pos) // 0x00000002 */ -#define DEACHINTMSK_IEP1INTM DEACHINTMSK_IEP1INTM_Msk // IN Endpoint 1 interrupt mask bit */ +#define DEACHINTMSK_IEP1INTM_Msk (0x1UL << DEACHINTMSK_IEP1INTM_Pos) // 0x00000002 +#define DEACHINTMSK_IEP1INTM DEACHINTMSK_IEP1INTM_Msk // IN Endpoint 1 interrupt mask bit #define DEACHINTMSK_OEP1INTM_Pos (17U) -#define DEACHINTMSK_OEP1INTM_Msk (0x1UL << DEACHINTMSK_OEP1INTM_Pos) // 0x00020000 */ -#define DEACHINTMSK_OEP1INTM DEACHINTMSK_OEP1INTM_Msk // OUT Endpoint 1 interrupt mask bit */ +#define DEACHINTMSK_OEP1INTM_Msk (0x1UL << DEACHINTMSK_OEP1INTM_Pos) // 0x00020000 +#define DEACHINTMSK_OEP1INTM DEACHINTMSK_OEP1INTM_Msk // OUT Endpoint 1 interrupt mask bit /******************** Bit definition for CID register ********************/ #define CID_PRODUCT_ID_Pos (0U) -#define CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos) // 0xFFFFFFFF */ -#define CID_PRODUCT_ID CID_PRODUCT_ID_Msk // Product ID field */ +#define CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos) // 0xFFFFFFFF +#define CID_PRODUCT_ID CID_PRODUCT_ID_Msk // Product ID field /******************** Bit definition for GLPMCFG register ********************/ #define GLPMCFG_LPMEN_Pos (0U) -#define GLPMCFG_LPMEN_Msk (0x1UL << GLPMCFG_LPMEN_Pos) // 0x00000001 */ -#define GLPMCFG_LPMEN GLPMCFG_LPMEN_Msk // LPM support enable */ +#define GLPMCFG_LPMEN_Msk (0x1UL << GLPMCFG_LPMEN_Pos) // 0x00000001 +#define GLPMCFG_LPMEN GLPMCFG_LPMEN_Msk // LPM support enable #define GLPMCFG_LPMACK_Pos (1U) -#define GLPMCFG_LPMACK_Msk (0x1UL << GLPMCFG_LPMACK_Pos) // 0x00000002 */ -#define GLPMCFG_LPMACK GLPMCFG_LPMACK_Msk // LPM Token acknowledge enable */ +#define GLPMCFG_LPMACK_Msk (0x1UL << GLPMCFG_LPMACK_Pos) // 0x00000002 +#define GLPMCFG_LPMACK GLPMCFG_LPMACK_Msk // LPM Token acknowledge enable #define GLPMCFG_BESL_Pos (2U) -#define GLPMCFG_BESL_Msk (0xFUL << GLPMCFG_BESL_Pos) // 0x0000003C */ -#define GLPMCFG_BESL GLPMCFG_BESL_Msk // BESL value received with last ACKed LPM Token */ +#define GLPMCFG_BESL_Msk (0xFUL << GLPMCFG_BESL_Pos) // 0x0000003C +#define GLPMCFG_BESL GLPMCFG_BESL_Msk // BESL value received with last ACKed LPM Token #define GLPMCFG_REMWAKE_Pos (6U) -#define GLPMCFG_REMWAKE_Msk (0x1UL << GLPMCFG_REMWAKE_Pos) // 0x00000040 */ -#define GLPMCFG_REMWAKE GLPMCFG_REMWAKE_Msk // bRemoteWake value received with last ACKed LPM Token */ +#define GLPMCFG_REMWAKE_Msk (0x1UL << GLPMCFG_REMWAKE_Pos) // 0x00000040 +#define GLPMCFG_REMWAKE GLPMCFG_REMWAKE_Msk // bRemoteWake value received with last ACKed LPM Token #define GLPMCFG_L1SSEN_Pos (7U) -#define GLPMCFG_L1SSEN_Msk (0x1UL << GLPMCFG_L1SSEN_Pos) // 0x00000080 */ -#define GLPMCFG_L1SSEN GLPMCFG_L1SSEN_Msk // L1 shallow sleep enable */ +#define GLPMCFG_L1SSEN_Msk (0x1UL << GLPMCFG_L1SSEN_Pos) // 0x00000080 +#define GLPMCFG_L1SSEN GLPMCFG_L1SSEN_Msk // L1 shallow sleep enable #define GLPMCFG_BESLTHRS_Pos (8U) -#define GLPMCFG_BESLTHRS_Msk (0xFUL << GLPMCFG_BESLTHRS_Pos) // 0x00000F00 */ -#define GLPMCFG_BESLTHRS GLPMCFG_BESLTHRS_Msk // BESL threshold */ +#define GLPMCFG_BESLTHRS_Msk (0xFUL << GLPMCFG_BESLTHRS_Pos) // 0x00000F00 +#define GLPMCFG_BESLTHRS GLPMCFG_BESLTHRS_Msk // BESL threshold #define GLPMCFG_L1DSEN_Pos (12U) -#define GLPMCFG_L1DSEN_Msk (0x1UL << GLPMCFG_L1DSEN_Pos) // 0x00001000 */ -#define GLPMCFG_L1DSEN GLPMCFG_L1DSEN_Msk // L1 deep sleep enable */ +#define GLPMCFG_L1DSEN_Msk (0x1UL << GLPMCFG_L1DSEN_Pos) // 0x00001000 +#define GLPMCFG_L1DSEN GLPMCFG_L1DSEN_Msk // L1 deep sleep enable #define GLPMCFG_LPMRSP_Pos (13U) -#define GLPMCFG_LPMRSP_Msk (0x3UL << GLPMCFG_LPMRSP_Pos) // 0x00006000 */ -#define GLPMCFG_LPMRSP GLPMCFG_LPMRSP_Msk // LPM response */ +#define GLPMCFG_LPMRSP_Msk (0x3UL << GLPMCFG_LPMRSP_Pos) // 0x00006000 +#define GLPMCFG_LPMRSP GLPMCFG_LPMRSP_Msk // LPM response #define GLPMCFG_SLPSTS_Pos (15U) -#define GLPMCFG_SLPSTS_Msk (0x1UL << GLPMCFG_SLPSTS_Pos) // 0x00008000 */ -#define GLPMCFG_SLPSTS GLPMCFG_SLPSTS_Msk // Port sleep status */ +#define GLPMCFG_SLPSTS_Msk (0x1UL << GLPMCFG_SLPSTS_Pos) // 0x00008000 +#define GLPMCFG_SLPSTS GLPMCFG_SLPSTS_Msk // Port sleep status #define GLPMCFG_L1RSMOK_Pos (16U) -#define GLPMCFG_L1RSMOK_Msk (0x1UL << GLPMCFG_L1RSMOK_Pos) // 0x00010000 */ -#define GLPMCFG_L1RSMOK GLPMCFG_L1RSMOK_Msk // Sleep State Resume OK */ +#define GLPMCFG_L1RSMOK_Msk (0x1UL << GLPMCFG_L1RSMOK_Pos) // 0x00010000 +#define GLPMCFG_L1RSMOK GLPMCFG_L1RSMOK_Msk // Sleep State Resume OK #define GLPMCFG_LPMCHIDX_Pos (17U) -#define GLPMCFG_LPMCHIDX_Msk (0xFUL << GLPMCFG_LPMCHIDX_Pos) // 0x001E0000 */ -#define GLPMCFG_LPMCHIDX GLPMCFG_LPMCHIDX_Msk // LPM Channel Index */ +#define GLPMCFG_LPMCHIDX_Msk (0xFUL << GLPMCFG_LPMCHIDX_Pos) // 0x001E0000 +#define GLPMCFG_LPMCHIDX GLPMCFG_LPMCHIDX_Msk // LPM Channel Index #define GLPMCFG_LPMRCNT_Pos (21U) -#define GLPMCFG_LPMRCNT_Msk (0x7UL << GLPMCFG_LPMRCNT_Pos) // 0x00E00000 */ -#define GLPMCFG_LPMRCNT GLPMCFG_LPMRCNT_Msk // LPM retry count */ +#define GLPMCFG_LPMRCNT_Msk (0x7UL << GLPMCFG_LPMRCNT_Pos) // 0x00E00000 +#define GLPMCFG_LPMRCNT GLPMCFG_LPMRCNT_Msk // LPM retry count #define GLPMCFG_SNDLPM_Pos (24U) -#define GLPMCFG_SNDLPM_Msk (0x1UL << GLPMCFG_SNDLPM_Pos) // 0x01000000 */ -#define GLPMCFG_SNDLPM GLPMCFG_SNDLPM_Msk // Send LPM transaction */ +#define GLPMCFG_SNDLPM_Msk (0x1UL << GLPMCFG_SNDLPM_Pos) // 0x01000000 +#define GLPMCFG_SNDLPM GLPMCFG_SNDLPM_Msk // Send LPM transaction #define GLPMCFG_LPMRCNTSTS_Pos (25U) -#define GLPMCFG_LPMRCNTSTS_Msk (0x7UL << GLPMCFG_LPMRCNTSTS_Pos) // 0x0E000000 */ -#define GLPMCFG_LPMRCNTSTS GLPMCFG_LPMRCNTSTS_Msk // LPM retry count status */ +#define GLPMCFG_LPMRCNTSTS_Msk (0x7UL << GLPMCFG_LPMRCNTSTS_Pos) // 0x0E000000 +#define GLPMCFG_LPMRCNTSTS GLPMCFG_LPMRCNTSTS_Msk // LPM retry count status #define GLPMCFG_ENBESL_Pos (28U) -#define GLPMCFG_ENBESL_Msk (0x1UL << GLPMCFG_ENBESL_Pos) // 0x10000000 */ -#define GLPMCFG_ENBESL GLPMCFG_ENBESL_Msk // Enable best effort service latency */ +#define GLPMCFG_ENBESL_Msk (0x1UL << GLPMCFG_ENBESL_Pos) // 0x10000000 +#define GLPMCFG_ENBESL GLPMCFG_ENBESL_Msk // Enable best effort service latency /******************** Bit definition for DIEPEACHMSK1 register ********************/ #define DIEPEACHMSK1_XFRCM_Pos (0U) -#define DIEPEACHMSK1_XFRCM_Msk (0x1UL << DIEPEACHMSK1_XFRCM_Pos) // 0x00000001 */ -#define DIEPEACHMSK1_XFRCM DIEPEACHMSK1_XFRCM_Msk // Transfer completed interrupt mask */ +#define DIEPEACHMSK1_XFRCM_Msk (0x1UL << DIEPEACHMSK1_XFRCM_Pos) // 0x00000001 +#define DIEPEACHMSK1_XFRCM DIEPEACHMSK1_XFRCM_Msk // Transfer completed interrupt mask #define DIEPEACHMSK1_EPDM_Pos (1U) -#define DIEPEACHMSK1_EPDM_Msk (0x1UL << DIEPEACHMSK1_EPDM_Pos) // 0x00000002 */ -#define DIEPEACHMSK1_EPDM DIEPEACHMSK1_EPDM_Msk // Endpoint disabled interrupt mask */ +#define DIEPEACHMSK1_EPDM_Msk (0x1UL << DIEPEACHMSK1_EPDM_Pos) // 0x00000002 +#define DIEPEACHMSK1_EPDM DIEPEACHMSK1_EPDM_Msk // Endpoint disabled interrupt mask #define DIEPEACHMSK1_TOM_Pos (3U) -#define DIEPEACHMSK1_TOM_Msk (0x1UL << DIEPEACHMSK1_TOM_Pos) // 0x00000008 */ -#define DIEPEACHMSK1_TOM DIEPEACHMSK1_TOM_Msk // Timeout condition mask (nonisochronous endpoints) */ +#define DIEPEACHMSK1_TOM_Msk (0x1UL << DIEPEACHMSK1_TOM_Pos) // 0x00000008 +#define DIEPEACHMSK1_TOM DIEPEACHMSK1_TOM_Msk // Timeout condition mask (nonisochronous endpoints) #define DIEPEACHMSK1_ITTXFEMSK_Pos (4U) -#define DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos) // 0x00000010 */ -#define DIEPEACHMSK1_ITTXFEMSK DIEPEACHMSK1_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask */ +#define DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos) // 0x00000010 +#define DIEPEACHMSK1_ITTXFEMSK DIEPEACHMSK1_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask #define DIEPEACHMSK1_INEPNMM_Pos (5U) -#define DIEPEACHMSK1_INEPNMM_Msk (0x1UL << DIEPEACHMSK1_INEPNMM_Pos) // 0x00000020 */ -#define DIEPEACHMSK1_INEPNMM DIEPEACHMSK1_INEPNMM_Msk // IN token received with EP mismatch mask */ +#define DIEPEACHMSK1_INEPNMM_Msk (0x1UL << DIEPEACHMSK1_INEPNMM_Pos) // 0x00000020 +#define DIEPEACHMSK1_INEPNMM DIEPEACHMSK1_INEPNMM_Msk // IN token received with EP mismatch mask #define DIEPEACHMSK1_INEPNEM_Pos (6U) -#define DIEPEACHMSK1_INEPNEM_Msk (0x1UL << DIEPEACHMSK1_INEPNEM_Pos) // 0x00000040 */ -#define DIEPEACHMSK1_INEPNEM DIEPEACHMSK1_INEPNEM_Msk // IN endpoint NAK effective mask */ +#define DIEPEACHMSK1_INEPNEM_Msk (0x1UL << DIEPEACHMSK1_INEPNEM_Pos) // 0x00000040 +#define DIEPEACHMSK1_INEPNEM DIEPEACHMSK1_INEPNEM_Msk // IN endpoint NAK effective mask #define DIEPEACHMSK1_TXFURM_Pos (8U) -#define DIEPEACHMSK1_TXFURM_Msk (0x1UL << DIEPEACHMSK1_TXFURM_Pos) // 0x00000100 */ -#define DIEPEACHMSK1_TXFURM DIEPEACHMSK1_TXFURM_Msk // FIFO underrun mask */ +#define DIEPEACHMSK1_TXFURM_Msk (0x1UL << DIEPEACHMSK1_TXFURM_Pos) // 0x00000100 +#define DIEPEACHMSK1_TXFURM DIEPEACHMSK1_TXFURM_Msk // FIFO underrun mask #define DIEPEACHMSK1_BIM_Pos (9U) -#define DIEPEACHMSK1_BIM_Msk (0x1UL << DIEPEACHMSK1_BIM_Pos) // 0x00000200 */ -#define DIEPEACHMSK1_BIM DIEPEACHMSK1_BIM_Msk // BNA interrupt mask */ +#define DIEPEACHMSK1_BIM_Msk (0x1UL << DIEPEACHMSK1_BIM_Pos) // 0x00000200 +#define DIEPEACHMSK1_BIM DIEPEACHMSK1_BIM_Msk // BNA interrupt mask #define DIEPEACHMSK1_NAKM_Pos (13U) -#define DIEPEACHMSK1_NAKM_Msk (0x1UL << DIEPEACHMSK1_NAKM_Pos) // 0x00002000 */ -#define DIEPEACHMSK1_NAKM DIEPEACHMSK1_NAKM_Msk // NAK interrupt mask */ +#define DIEPEACHMSK1_NAKM_Msk (0x1UL << DIEPEACHMSK1_NAKM_Pos) // 0x00002000 +#define DIEPEACHMSK1_NAKM DIEPEACHMSK1_NAKM_Msk // NAK interrupt mask /******************** Bit definition for HPRT register ********************/ #define HPRT_PCSTS_Pos (0U) -#define HPRT_PCSTS_Msk (0x1UL << HPRT_PCSTS_Pos) // 0x00000001 */ -#define HPRT_PCSTS HPRT_PCSTS_Msk // Port connect status */ +#define HPRT_PCSTS_Msk (0x1UL << HPRT_PCSTS_Pos) // 0x00000001 +#define HPRT_PCSTS HPRT_PCSTS_Msk // Port connect status #define HPRT_PCDET_Pos (1U) -#define HPRT_PCDET_Msk (0x1UL << HPRT_PCDET_Pos) // 0x00000002 */ -#define HPRT_PCDET HPRT_PCDET_Msk // Port connect detected */ +#define HPRT_PCDET_Msk (0x1UL << HPRT_PCDET_Pos) // 0x00000002 +#define HPRT_PCDET HPRT_PCDET_Msk // Port connect detected #define HPRT_PENA_Pos (2U) -#define HPRT_PENA_Msk (0x1UL << HPRT_PENA_Pos) // 0x00000004 */ -#define HPRT_PENA HPRT_PENA_Msk // Port enable */ +#define HPRT_PENA_Msk (0x1UL << HPRT_PENA_Pos) // 0x00000004 +#define HPRT_PENA HPRT_PENA_Msk // Port enable #define HPRT_PENCHNG_Pos (3U) -#define HPRT_PENCHNG_Msk (0x1UL << HPRT_PENCHNG_Pos) // 0x00000008 */ -#define HPRT_PENCHNG HPRT_PENCHNG_Msk // Port enable/disable change */ +#define HPRT_PENCHNG_Msk (0x1UL << HPRT_PENCHNG_Pos) // 0x00000008 +#define HPRT_PENCHNG HPRT_PENCHNG_Msk // Port enable/disable change #define HPRT_POCA_Pos (4U) -#define HPRT_POCA_Msk (0x1UL << HPRT_POCA_Pos) // 0x00000010 */ -#define HPRT_POCA HPRT_POCA_Msk // Port overcurrent active */ +#define HPRT_POCA_Msk (0x1UL << HPRT_POCA_Pos) // 0x00000010 +#define HPRT_POCA HPRT_POCA_Msk // Port overcurrent active #define HPRT_POCCHNG_Pos (5U) -#define HPRT_POCCHNG_Msk (0x1UL << HPRT_POCCHNG_Pos) // 0x00000020 */ -#define HPRT_POCCHNG HPRT_POCCHNG_Msk // Port overcurrent change */ +#define HPRT_POCCHNG_Msk (0x1UL << HPRT_POCCHNG_Pos) // 0x00000020 +#define HPRT_POCCHNG HPRT_POCCHNG_Msk // Port overcurrent change #define HPRT_PRES_Pos (6U) -#define HPRT_PRES_Msk (0x1UL << HPRT_PRES_Pos) // 0x00000040 */ -#define HPRT_PRES HPRT_PRES_Msk // Port resume */ +#define HPRT_PRES_Msk (0x1UL << HPRT_PRES_Pos) // 0x00000040 +#define HPRT_PRES HPRT_PRES_Msk // Port resume #define HPRT_PSUSP_Pos (7U) -#define HPRT_PSUSP_Msk (0x1UL << HPRT_PSUSP_Pos) // 0x00000080 */ -#define HPRT_PSUSP HPRT_PSUSP_Msk // Port suspend */ +#define HPRT_PSUSP_Msk (0x1UL << HPRT_PSUSP_Pos) // 0x00000080 +#define HPRT_PSUSP HPRT_PSUSP_Msk // Port suspend #define HPRT_PRST_Pos (8U) -#define HPRT_PRST_Msk (0x1UL << HPRT_PRST_Pos) // 0x00000100 */ -#define HPRT_PRST HPRT_PRST_Msk // Port reset */ +#define HPRT_PRST_Msk (0x1UL << HPRT_PRST_Pos) // 0x00000100 +#define HPRT_PRST HPRT_PRST_Msk // Port reset #define HPRT_PLSTS_Pos (10U) -#define HPRT_PLSTS_Msk (0x3UL << HPRT_PLSTS_Pos) // 0x00000C00 */ -#define HPRT_PLSTS HPRT_PLSTS_Msk // Port line status */ -#define HPRT_PLSTS_0 (0x1UL << HPRT_PLSTS_Pos) // 0x00000400 */ -#define HPRT_PLSTS_1 (0x2UL << HPRT_PLSTS_Pos) // 0x00000800 */ +#define HPRT_PLSTS_Msk (0x3UL << HPRT_PLSTS_Pos) // 0x00000C00 +#define HPRT_PLSTS HPRT_PLSTS_Msk // Port line status +#define HPRT_PLSTS_0 (0x1UL << HPRT_PLSTS_Pos) // 0x00000400 +#define HPRT_PLSTS_1 (0x2UL << HPRT_PLSTS_Pos) // 0x00000800 #define HPRT_PPWR_Pos (12U) -#define HPRT_PPWR_Msk (0x1UL << HPRT_PPWR_Pos) // 0x00001000 */ -#define HPRT_PPWR HPRT_PPWR_Msk // Port power */ +#define HPRT_PPWR_Msk (0x1UL << HPRT_PPWR_Pos) // 0x00001000 +#define HPRT_PPWR HPRT_PPWR_Msk // Port power #define HPRT_PTCTL_Pos (13U) -#define HPRT_PTCTL_Msk (0xFUL << HPRT_PTCTL_Pos) // 0x0001E000 */ -#define HPRT_PTCTL HPRT_PTCTL_Msk // Port test control */ -#define HPRT_PTCTL_0 (0x1UL << HPRT_PTCTL_Pos) // 0x00002000 */ -#define HPRT_PTCTL_1 (0x2UL << HPRT_PTCTL_Pos) // 0x00004000 */ -#define HPRT_PTCTL_2 (0x4UL << HPRT_PTCTL_Pos) // 0x00008000 */ -#define HPRT_PTCTL_3 (0x8UL << HPRT_PTCTL_Pos) // 0x00010000 */ +#define HPRT_PTCTL_Msk (0xFUL << HPRT_PTCTL_Pos) // 0x0001E000 +#define HPRT_PTCTL HPRT_PTCTL_Msk // Port test control +#define HPRT_PTCTL_0 (0x1UL << HPRT_PTCTL_Pos) // 0x00002000 +#define HPRT_PTCTL_1 (0x2UL << HPRT_PTCTL_Pos) // 0x00004000 +#define HPRT_PTCTL_2 (0x4UL << HPRT_PTCTL_Pos) // 0x00008000 +#define HPRT_PTCTL_3 (0x8UL << HPRT_PTCTL_Pos) // 0x00010000 #define HPRT_PSPD_Pos (17U) -#define HPRT_PSPD_Msk (0x3UL << HPRT_PSPD_Pos) // 0x00060000 */ -#define HPRT_PSPD HPRT_PSPD_Msk // Port speed */ -#define HPRT_PSPD_0 (0x1UL << HPRT_PSPD_Pos) // 0x00020000 */ -#define HPRT_PSPD_1 (0x2UL << HPRT_PSPD_Pos) // 0x00040000 */ +#define HPRT_PSPD_Msk (0x3UL << HPRT_PSPD_Pos) // 0x00060000 +#define HPRT_PSPD HPRT_PSPD_Msk // Port speed +#define HPRT_PSPD_0 (0x1UL << HPRT_PSPD_Pos) // 0x00020000 +#define HPRT_PSPD_1 (0x2UL << HPRT_PSPD_Pos) // 0x00040000 /******************** Bit definition for DOEPEACHMSK1 register ********************/ #define DOEPEACHMSK1_XFRCM_Pos (0U) -#define DOEPEACHMSK1_XFRCM_Msk (0x1UL << DOEPEACHMSK1_XFRCM_Pos) // 0x00000001 */ -#define DOEPEACHMSK1_XFRCM DOEPEACHMSK1_XFRCM_Msk // Transfer completed interrupt mask */ +#define DOEPEACHMSK1_XFRCM_Msk (0x1UL << DOEPEACHMSK1_XFRCM_Pos) // 0x00000001 +#define DOEPEACHMSK1_XFRCM DOEPEACHMSK1_XFRCM_Msk // Transfer completed interrupt mask #define DOEPEACHMSK1_EPDM_Pos (1U) -#define DOEPEACHMSK1_EPDM_Msk (0x1UL << DOEPEACHMSK1_EPDM_Pos) // 0x00000002 */ -#define DOEPEACHMSK1_EPDM DOEPEACHMSK1_EPDM_Msk // Endpoint disabled interrupt mask */ +#define DOEPEACHMSK1_EPDM_Msk (0x1UL << DOEPEACHMSK1_EPDM_Pos) // 0x00000002 +#define DOEPEACHMSK1_EPDM DOEPEACHMSK1_EPDM_Msk // Endpoint disabled interrupt mask #define DOEPEACHMSK1_TOM_Pos (3U) -#define DOEPEACHMSK1_TOM_Msk (0x1UL << DOEPEACHMSK1_TOM_Pos) // 0x00000008 */ -#define DOEPEACHMSK1_TOM DOEPEACHMSK1_TOM_Msk // Timeout condition mask */ +#define DOEPEACHMSK1_TOM_Msk (0x1UL << DOEPEACHMSK1_TOM_Pos) // 0x00000008 +#define DOEPEACHMSK1_TOM DOEPEACHMSK1_TOM_Msk // Timeout condition mask #define DOEPEACHMSK1_ITTXFEMSK_Pos (4U) -#define DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos) // 0x00000010 */ -#define DOEPEACHMSK1_ITTXFEMSK DOEPEACHMSK1_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask */ +#define DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos) // 0x00000010 +#define DOEPEACHMSK1_ITTXFEMSK DOEPEACHMSK1_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask #define DOEPEACHMSK1_INEPNMM_Pos (5U) -#define DOEPEACHMSK1_INEPNMM_Msk (0x1UL << DOEPEACHMSK1_INEPNMM_Pos) // 0x00000020 */ -#define DOEPEACHMSK1_INEPNMM DOEPEACHMSK1_INEPNMM_Msk // IN token received with EP mismatch mask */ +#define DOEPEACHMSK1_INEPNMM_Msk (0x1UL << DOEPEACHMSK1_INEPNMM_Pos) // 0x00000020 +#define DOEPEACHMSK1_INEPNMM DOEPEACHMSK1_INEPNMM_Msk // IN token received with EP mismatch mask #define DOEPEACHMSK1_INEPNEM_Pos (6U) -#define DOEPEACHMSK1_INEPNEM_Msk (0x1UL << DOEPEACHMSK1_INEPNEM_Pos) // 0x00000040 */ -#define DOEPEACHMSK1_INEPNEM DOEPEACHMSK1_INEPNEM_Msk // IN endpoint NAK effective mask */ +#define DOEPEACHMSK1_INEPNEM_Msk (0x1UL << DOEPEACHMSK1_INEPNEM_Pos) // 0x00000040 +#define DOEPEACHMSK1_INEPNEM DOEPEACHMSK1_INEPNEM_Msk // IN endpoint NAK effective mask #define DOEPEACHMSK1_TXFURM_Pos (8U) -#define DOEPEACHMSK1_TXFURM_Msk (0x1UL << DOEPEACHMSK1_TXFURM_Pos) // 0x00000100 */ -#define DOEPEACHMSK1_TXFURM DOEPEACHMSK1_TXFURM_Msk // OUT packet error mask */ +#define DOEPEACHMSK1_TXFURM_Msk (0x1UL << DOEPEACHMSK1_TXFURM_Pos) // 0x00000100 +#define DOEPEACHMSK1_TXFURM DOEPEACHMSK1_TXFURM_Msk // OUT packet error mask #define DOEPEACHMSK1_BIM_Pos (9U) -#define DOEPEACHMSK1_BIM_Msk (0x1UL << DOEPEACHMSK1_BIM_Pos) // 0x00000200 */ -#define DOEPEACHMSK1_BIM DOEPEACHMSK1_BIM_Msk // BNA interrupt mask */ +#define DOEPEACHMSK1_BIM_Msk (0x1UL << DOEPEACHMSK1_BIM_Pos) // 0x00000200 +#define DOEPEACHMSK1_BIM DOEPEACHMSK1_BIM_Msk // BNA interrupt mask #define DOEPEACHMSK1_BERRM_Pos (12U) -#define DOEPEACHMSK1_BERRM_Msk (0x1UL << DOEPEACHMSK1_BERRM_Pos) // 0x00001000 */ -#define DOEPEACHMSK1_BERRM DOEPEACHMSK1_BERRM_Msk // Bubble error interrupt mask */ +#define DOEPEACHMSK1_BERRM_Msk (0x1UL << DOEPEACHMSK1_BERRM_Pos) // 0x00001000 +#define DOEPEACHMSK1_BERRM DOEPEACHMSK1_BERRM_Msk // Bubble error interrupt mask #define DOEPEACHMSK1_NAKM_Pos (13U) -#define DOEPEACHMSK1_NAKM_Msk (0x1UL << DOEPEACHMSK1_NAKM_Pos) // 0x00002000 */ -#define DOEPEACHMSK1_NAKM DOEPEACHMSK1_NAKM_Msk // NAK interrupt mask */ +#define DOEPEACHMSK1_NAKM_Msk (0x1UL << DOEPEACHMSK1_NAKM_Pos) // 0x00002000 +#define DOEPEACHMSK1_NAKM DOEPEACHMSK1_NAKM_Msk // NAK interrupt mask #define DOEPEACHMSK1_NYETM_Pos (14U) -#define DOEPEACHMSK1_NYETM_Msk (0x1UL << DOEPEACHMSK1_NYETM_Pos) // 0x00004000 */ -#define DOEPEACHMSK1_NYETM DOEPEACHMSK1_NYETM_Msk // NYET interrupt mask */ +#define DOEPEACHMSK1_NYETM_Msk (0x1UL << DOEPEACHMSK1_NYETM_Pos) // 0x00004000 +#define DOEPEACHMSK1_NYETM DOEPEACHMSK1_NYETM_Msk // NYET interrupt mask /******************** Bit definition for HPTXFSIZ register ********************/ #define HPTXFSIZ_PTXSA_Pos (0U) -#define HPTXFSIZ_PTXSA_Msk (0xFFFFUL << HPTXFSIZ_PTXSA_Pos) // 0x0000FFFF */ -#define HPTXFSIZ_PTXSA HPTXFSIZ_PTXSA_Msk // Host periodic TxFIFO start address */ +#define HPTXFSIZ_PTXSA_Msk (0xFFFFUL << HPTXFSIZ_PTXSA_Pos) // 0x0000FFFF +#define HPTXFSIZ_PTXSA HPTXFSIZ_PTXSA_Msk // Host periodic TxFIFO start address #define HPTXFSIZ_PTXFD_Pos (16U) -#define HPTXFSIZ_PTXFD_Msk (0xFFFFUL << HPTXFSIZ_PTXFD_Pos) // 0xFFFF0000 */ -#define HPTXFSIZ_PTXFD HPTXFSIZ_PTXFD_Msk // Host periodic TxFIFO depth */ +#define HPTXFSIZ_PTXFD_Msk (0xFFFFUL << HPTXFSIZ_PTXFD_Pos) // 0xFFFF0000 +#define HPTXFSIZ_PTXFD HPTXFSIZ_PTXFD_Msk // Host periodic TxFIFO depth /******************** Bit definition for DIEPCTL register ********************/ #define DIEPCTL_MPSIZ_Pos (0U) -#define DIEPCTL_MPSIZ_Msk (0x7FFUL << DIEPCTL_MPSIZ_Pos) // 0x000007FF */ -#define DIEPCTL_MPSIZ DIEPCTL_MPSIZ_Msk // Maximum packet size */ +#define DIEPCTL_MPSIZ_Msk (0x7FFUL << DIEPCTL_MPSIZ_Pos) // 0x000007FF +#define DIEPCTL_MPSIZ DIEPCTL_MPSIZ_Msk // Maximum packet size #define DIEPCTL_USBAEP_Pos (15U) -#define DIEPCTL_USBAEP_Msk (0x1UL << DIEPCTL_USBAEP_Pos) // 0x00008000 */ -#define DIEPCTL_USBAEP DIEPCTL_USBAEP_Msk // USB active endpoint */ +#define DIEPCTL_USBAEP_Msk (0x1UL << DIEPCTL_USBAEP_Pos) // 0x00008000 +#define DIEPCTL_USBAEP DIEPCTL_USBAEP_Msk // USB active endpoint #define DIEPCTL_EONUM_DPID_Pos (16U) -#define DIEPCTL_EONUM_DPID_Msk (0x1UL << DIEPCTL_EONUM_DPID_Pos) // 0x00010000 */ -#define DIEPCTL_EONUM_DPID DIEPCTL_EONUM_DPID_Msk // Even/odd frame */ +#define DIEPCTL_EONUM_DPID_Msk (0x1UL << DIEPCTL_EONUM_DPID_Pos) // 0x00010000 +#define DIEPCTL_EONUM_DPID DIEPCTL_EONUM_DPID_Msk // Even/odd frame #define DIEPCTL_NAKSTS_Pos (17U) -#define DIEPCTL_NAKSTS_Msk (0x1UL << DIEPCTL_NAKSTS_Pos) // 0x00020000 */ -#define DIEPCTL_NAKSTS DIEPCTL_NAKSTS_Msk // NAK status */ +#define DIEPCTL_NAKSTS_Msk (0x1UL << DIEPCTL_NAKSTS_Pos) // 0x00020000 +#define DIEPCTL_NAKSTS DIEPCTL_NAKSTS_Msk // NAK status #define DIEPCTL_EPTYP_Pos (18U) -#define DIEPCTL_EPTYP_Msk (0x3UL << DIEPCTL_EPTYP_Pos) // 0x000C0000 */ -#define DIEPCTL_EPTYP DIEPCTL_EPTYP_Msk // Endpoint type */ -#define DIEPCTL_EPTYP_0 (0x1UL << DIEPCTL_EPTYP_Pos) // 0x00040000 */ -#define DIEPCTL_EPTYP_1 (0x2UL << DIEPCTL_EPTYP_Pos) // 0x00080000 */ +#define DIEPCTL_EPTYP_Msk (0x3UL << DIEPCTL_EPTYP_Pos) // 0x000C0000 +#define DIEPCTL_EPTYP DIEPCTL_EPTYP_Msk // Endpoint type +#define DIEPCTL_EPTYP_0 (0x1UL << DIEPCTL_EPTYP_Pos) // 0x00040000 +#define DIEPCTL_EPTYP_1 (0x2UL << DIEPCTL_EPTYP_Pos) // 0x00080000 #define DIEPCTL_STALL_Pos (21U) -#define DIEPCTL_STALL_Msk (0x1UL << DIEPCTL_STALL_Pos) // 0x00200000 */ -#define DIEPCTL_STALL DIEPCTL_STALL_Msk // STALL handshake */ +#define DIEPCTL_STALL_Msk (0x1UL << DIEPCTL_STALL_Pos) // 0x00200000 +#define DIEPCTL_STALL DIEPCTL_STALL_Msk // STALL handshake #define DIEPCTL_TXFNUM_Pos (22U) -#define DIEPCTL_TXFNUM_Msk (0xFUL << DIEPCTL_TXFNUM_Pos) // 0x03C00000 */ -#define DIEPCTL_TXFNUM DIEPCTL_TXFNUM_Msk // TxFIFO number */ -#define DIEPCTL_TXFNUM_0 (0x1UL << DIEPCTL_TXFNUM_Pos) // 0x00400000 */ -#define DIEPCTL_TXFNUM_1 (0x2UL << DIEPCTL_TXFNUM_Pos) // 0x00800000 */ -#define DIEPCTL_TXFNUM_2 (0x4UL << DIEPCTL_TXFNUM_Pos) // 0x01000000 */ -#define DIEPCTL_TXFNUM_3 (0x8UL << DIEPCTL_TXFNUM_Pos) // 0x02000000 */ +#define DIEPCTL_TXFNUM_Msk (0xFUL << DIEPCTL_TXFNUM_Pos) // 0x03C00000 +#define DIEPCTL_TXFNUM DIEPCTL_TXFNUM_Msk // TxFIFO number +#define DIEPCTL_TXFNUM_0 (0x1UL << DIEPCTL_TXFNUM_Pos) // 0x00400000 +#define DIEPCTL_TXFNUM_1 (0x2UL << DIEPCTL_TXFNUM_Pos) // 0x00800000 +#define DIEPCTL_TXFNUM_2 (0x4UL << DIEPCTL_TXFNUM_Pos) // 0x01000000 +#define DIEPCTL_TXFNUM_3 (0x8UL << DIEPCTL_TXFNUM_Pos) // 0x02000000 #define DIEPCTL_CNAK_Pos (26U) -#define DIEPCTL_CNAK_Msk (0x1UL << DIEPCTL_CNAK_Pos) // 0x04000000 */ -#define DIEPCTL_CNAK DIEPCTL_CNAK_Msk // Clear NAK */ +#define DIEPCTL_CNAK_Msk (0x1UL << DIEPCTL_CNAK_Pos) // 0x04000000 +#define DIEPCTL_CNAK DIEPCTL_CNAK_Msk // Clear NAK #define DIEPCTL_SNAK_Pos (27U) -#define DIEPCTL_SNAK_Msk (0x1UL << DIEPCTL_SNAK_Pos) // 0x08000000 */ -#define DIEPCTL_SNAK DIEPCTL_SNAK_Msk // Set NAK */ +#define DIEPCTL_SNAK_Msk (0x1UL << DIEPCTL_SNAK_Pos) // 0x08000000 +#define DIEPCTL_SNAK DIEPCTL_SNAK_Msk // Set NAK #define DIEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos) // 0x10000000 */ -#define DIEPCTL_SD0PID_SEVNFRM DIEPCTL_SD0PID_SEVNFRM_Msk // Set DATA0 PID */ +#define DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos) // 0x10000000 +#define DIEPCTL_SD0PID_SEVNFRM DIEPCTL_SD0PID_SEVNFRM_Msk // Set DATA0 PID #define DIEPCTL_SODDFRM_Pos (29U) -#define DIEPCTL_SODDFRM_Msk (0x1UL << DIEPCTL_SODDFRM_Pos) // 0x20000000 */ -#define DIEPCTL_SODDFRM DIEPCTL_SODDFRM_Msk // Set odd frame */ +#define DIEPCTL_SODDFRM_Msk (0x1UL << DIEPCTL_SODDFRM_Pos) // 0x20000000 +#define DIEPCTL_SODDFRM DIEPCTL_SODDFRM_Msk // Set odd frame #define DIEPCTL_EPDIS_Pos (30U) -#define DIEPCTL_EPDIS_Msk (0x1UL << DIEPCTL_EPDIS_Pos) // 0x40000000 */ -#define DIEPCTL_EPDIS DIEPCTL_EPDIS_Msk // Endpoint disable */ +#define DIEPCTL_EPDIS_Msk (0x1UL << DIEPCTL_EPDIS_Pos) // 0x40000000 +#define DIEPCTL_EPDIS DIEPCTL_EPDIS_Msk // Endpoint disable #define DIEPCTL_EPENA_Pos (31U) -#define DIEPCTL_EPENA_Msk (0x1UL << DIEPCTL_EPENA_Pos) // 0x80000000 */ -#define DIEPCTL_EPENA DIEPCTL_EPENA_Msk // Endpoint enable */ +#define DIEPCTL_EPENA_Msk (0x1UL << DIEPCTL_EPENA_Pos) // 0x80000000 +#define DIEPCTL_EPENA DIEPCTL_EPENA_Msk // Endpoint enable /******************** Bit definition for HCCHAR register ********************/ #define HCCHAR_MPSIZ_Pos (0U) -#define HCCHAR_MPSIZ_Msk (0x7FFUL << HCCHAR_MPSIZ_Pos) // 0x000007FF */ -#define HCCHAR_MPSIZ HCCHAR_MPSIZ_Msk // Maximum packet size */ +#define HCCHAR_MPSIZ_Msk (0x7FFUL << HCCHAR_MPSIZ_Pos) // 0x000007FF +#define HCCHAR_MPSIZ HCCHAR_MPSIZ_Msk // Maximum packet size #define HCCHAR_EPNUM_Pos (11U) -#define HCCHAR_EPNUM_Msk (0xFUL << HCCHAR_EPNUM_Pos) // 0x00007800 */ -#define HCCHAR_EPNUM HCCHAR_EPNUM_Msk // Endpoint number */ -#define HCCHAR_EPNUM_0 (0x1UL << HCCHAR_EPNUM_Pos) // 0x00000800 */ -#define HCCHAR_EPNUM_1 (0x2UL << HCCHAR_EPNUM_Pos) // 0x00001000 */ -#define HCCHAR_EPNUM_2 (0x4UL << HCCHAR_EPNUM_Pos) // 0x00002000 */ -#define HCCHAR_EPNUM_3 (0x8UL << HCCHAR_EPNUM_Pos) // 0x00004000 */ +#define HCCHAR_EPNUM_Msk (0xFUL << HCCHAR_EPNUM_Pos) // 0x00007800 +#define HCCHAR_EPNUM HCCHAR_EPNUM_Msk // Endpoint number +#define HCCHAR_EPNUM_0 (0x1UL << HCCHAR_EPNUM_Pos) // 0x00000800 +#define HCCHAR_EPNUM_1 (0x2UL << HCCHAR_EPNUM_Pos) // 0x00001000 +#define HCCHAR_EPNUM_2 (0x4UL << HCCHAR_EPNUM_Pos) // 0x00002000 +#define HCCHAR_EPNUM_3 (0x8UL << HCCHAR_EPNUM_Pos) // 0x00004000 #define HCCHAR_EPDIR_Pos (15U) -#define HCCHAR_EPDIR_Msk (0x1UL << HCCHAR_EPDIR_Pos) // 0x00008000 */ -#define HCCHAR_EPDIR HCCHAR_EPDIR_Msk // Endpoint direction */ +#define HCCHAR_EPDIR_Msk (0x1UL << HCCHAR_EPDIR_Pos) // 0x00008000 +#define HCCHAR_EPDIR HCCHAR_EPDIR_Msk // Endpoint direction #define HCCHAR_LSDEV_Pos (17U) -#define HCCHAR_LSDEV_Msk (0x1UL << HCCHAR_LSDEV_Pos) // 0x00020000 */ -#define HCCHAR_LSDEV HCCHAR_LSDEV_Msk // Low-speed device */ +#define HCCHAR_LSDEV_Msk (0x1UL << HCCHAR_LSDEV_Pos) // 0x00020000 +#define HCCHAR_LSDEV HCCHAR_LSDEV_Msk // Low-speed device #define HCCHAR_EPTYP_Pos (18U) -#define HCCHAR_EPTYP_Msk (0x3UL << HCCHAR_EPTYP_Pos) // 0x000C0000 */ -#define HCCHAR_EPTYP HCCHAR_EPTYP_Msk // Endpoint type */ -#define HCCHAR_EPTYP_0 (0x1UL << HCCHAR_EPTYP_Pos) // 0x00040000 */ -#define HCCHAR_EPTYP_1 (0x2UL << HCCHAR_EPTYP_Pos) // 0x00080000 */ +#define HCCHAR_EPTYP_Msk (0x3UL << HCCHAR_EPTYP_Pos) // 0x000C0000 +#define HCCHAR_EPTYP HCCHAR_EPTYP_Msk // Endpoint type +#define HCCHAR_EPTYP_0 (0x1UL << HCCHAR_EPTYP_Pos) // 0x00040000 +#define HCCHAR_EPTYP_1 (0x2UL << HCCHAR_EPTYP_Pos) // 0x00080000 #define HCCHAR_MC_Pos (20U) -#define HCCHAR_MC_Msk (0x3UL << HCCHAR_MC_Pos) // 0x00300000 */ -#define HCCHAR_MC HCCHAR_MC_Msk // Multi Count (MC) / Error Count (EC) */ -#define HCCHAR_MC_0 (0x1UL << HCCHAR_MC_Pos) // 0x00100000 */ -#define HCCHAR_MC_1 (0x2UL << HCCHAR_MC_Pos) // 0x00200000 */ +#define HCCHAR_MC_Msk (0x3UL << HCCHAR_MC_Pos) // 0x00300000 +#define HCCHAR_MC HCCHAR_MC_Msk // Multi Count (MC) / Error Count (EC) +#define HCCHAR_MC_0 (0x1UL << HCCHAR_MC_Pos) // 0x00100000 +#define HCCHAR_MC_1 (0x2UL << HCCHAR_MC_Pos) // 0x00200000 #define HCCHAR_DAD_Pos (22U) -#define HCCHAR_DAD_Msk (0x7FUL << HCCHAR_DAD_Pos) // 0x1FC00000 */ -#define HCCHAR_DAD HCCHAR_DAD_Msk // Device address */ -#define HCCHAR_DAD_0 (0x01UL << HCCHAR_DAD_Pos) // 0x00400000 */ -#define HCCHAR_DAD_1 (0x02UL << HCCHAR_DAD_Pos) // 0x00800000 */ -#define HCCHAR_DAD_2 (0x04UL << HCCHAR_DAD_Pos) // 0x01000000 */ -#define HCCHAR_DAD_3 (0x08UL << HCCHAR_DAD_Pos) // 0x02000000 */ -#define HCCHAR_DAD_4 (0x10UL << HCCHAR_DAD_Pos) // 0x04000000 */ -#define HCCHAR_DAD_5 (0x20UL << HCCHAR_DAD_Pos) // 0x08000000 */ -#define HCCHAR_DAD_6 (0x40UL << HCCHAR_DAD_Pos) // 0x10000000 */ +#define HCCHAR_DAD_Msk (0x7FUL << HCCHAR_DAD_Pos) // 0x1FC00000 +#define HCCHAR_DAD HCCHAR_DAD_Msk // Device address +#define HCCHAR_DAD_0 (0x01UL << HCCHAR_DAD_Pos) // 0x00400000 +#define HCCHAR_DAD_1 (0x02UL << HCCHAR_DAD_Pos) // 0x00800000 +#define HCCHAR_DAD_2 (0x04UL << HCCHAR_DAD_Pos) // 0x01000000 +#define HCCHAR_DAD_3 (0x08UL << HCCHAR_DAD_Pos) // 0x02000000 +#define HCCHAR_DAD_4 (0x10UL << HCCHAR_DAD_Pos) // 0x04000000 +#define HCCHAR_DAD_5 (0x20UL << HCCHAR_DAD_Pos) // 0x08000000 +#define HCCHAR_DAD_6 (0x40UL << HCCHAR_DAD_Pos) // 0x10000000 #define HCCHAR_ODDFRM_Pos (29U) -#define HCCHAR_ODDFRM_Msk (0x1UL << HCCHAR_ODDFRM_Pos) // 0x20000000 */ -#define HCCHAR_ODDFRM HCCHAR_ODDFRM_Msk // Odd frame */ +#define HCCHAR_ODDFRM_Msk (0x1UL << HCCHAR_ODDFRM_Pos) // 0x20000000 +#define HCCHAR_ODDFRM HCCHAR_ODDFRM_Msk // Odd frame #define HCCHAR_CHDIS_Pos (30U) -#define HCCHAR_CHDIS_Msk (0x1UL << HCCHAR_CHDIS_Pos) // 0x40000000 */ -#define HCCHAR_CHDIS HCCHAR_CHDIS_Msk // Channel disable */ +#define HCCHAR_CHDIS_Msk (0x1UL << HCCHAR_CHDIS_Pos) // 0x40000000 +#define HCCHAR_CHDIS HCCHAR_CHDIS_Msk // Channel disable #define HCCHAR_CHENA_Pos (31U) -#define HCCHAR_CHENA_Msk (0x1UL << HCCHAR_CHENA_Pos) // 0x80000000 */ -#define HCCHAR_CHENA HCCHAR_CHENA_Msk // Channel enable */ +#define HCCHAR_CHENA_Msk (0x1UL << HCCHAR_CHENA_Pos) // 0x80000000 +#define HCCHAR_CHENA HCCHAR_CHENA_Msk // Channel enable /******************** Bit definition for HCSPLT register ********************/ #define HCSPLT_PRTADDR_Pos (0U) -#define HCSPLT_PRTADDR_Msk (0x7FUL << HCSPLT_PRTADDR_Pos) // 0x0000007F */ -#define HCSPLT_PRTADDR HCSPLT_PRTADDR_Msk // Port address */ -#define HCSPLT_PRTADDR_0 (0x01UL << HCSPLT_PRTADDR_Pos) // 0x00000001 */ -#define HCSPLT_PRTADDR_1 (0x02UL << HCSPLT_PRTADDR_Pos) // 0x00000002 */ -#define HCSPLT_PRTADDR_2 (0x04UL << HCSPLT_PRTADDR_Pos) // 0x00000004 */ -#define HCSPLT_PRTADDR_3 (0x08UL << HCSPLT_PRTADDR_Pos) // 0x00000008 */ -#define HCSPLT_PRTADDR_4 (0x10UL << HCSPLT_PRTADDR_Pos) // 0x00000010 */ -#define HCSPLT_PRTADDR_5 (0x20UL << HCSPLT_PRTADDR_Pos) // 0x00000020 */ -#define HCSPLT_PRTADDR_6 (0x40UL << HCSPLT_PRTADDR_Pos) // 0x00000040 */ +#define HCSPLT_PRTADDR_Msk (0x7FUL << HCSPLT_PRTADDR_Pos) // 0x0000007F +#define HCSPLT_PRTADDR HCSPLT_PRTADDR_Msk // Port address +#define HCSPLT_PRTADDR_0 (0x01UL << HCSPLT_PRTADDR_Pos) // 0x00000001 +#define HCSPLT_PRTADDR_1 (0x02UL << HCSPLT_PRTADDR_Pos) // 0x00000002 +#define HCSPLT_PRTADDR_2 (0x04UL << HCSPLT_PRTADDR_Pos) // 0x00000004 +#define HCSPLT_PRTADDR_3 (0x08UL << HCSPLT_PRTADDR_Pos) // 0x00000008 +#define HCSPLT_PRTADDR_4 (0x10UL << HCSPLT_PRTADDR_Pos) // 0x00000010 +#define HCSPLT_PRTADDR_5 (0x20UL << HCSPLT_PRTADDR_Pos) // 0x00000020 +#define HCSPLT_PRTADDR_6 (0x40UL << HCSPLT_PRTADDR_Pos) // 0x00000040 #define HCSPLT_HUBADDR_Pos (7U) -#define HCSPLT_HUBADDR_Msk (0x7FUL << HCSPLT_HUBADDR_Pos) // 0x00003F80 */ -#define HCSPLT_HUBADDR HCSPLT_HUBADDR_Msk // Hub address */ -#define HCSPLT_HUBADDR_0 (0x01UL << HCSPLT_HUBADDR_Pos) // 0x00000080 */ -#define HCSPLT_HUBADDR_1 (0x02UL << HCSPLT_HUBADDR_Pos) // 0x00000100 */ -#define HCSPLT_HUBADDR_2 (0x04UL << HCSPLT_HUBADDR_Pos) // 0x00000200 */ -#define HCSPLT_HUBADDR_3 (0x08UL << HCSPLT_HUBADDR_Pos) // 0x00000400 */ -#define HCSPLT_HUBADDR_4 (0x10UL << HCSPLT_HUBADDR_Pos) // 0x00000800 */ -#define HCSPLT_HUBADDR_5 (0x20UL << HCSPLT_HUBADDR_Pos) // 0x00001000 */ -#define HCSPLT_HUBADDR_6 (0x40UL << HCSPLT_HUBADDR_Pos) // 0x00002000 */ +#define HCSPLT_HUBADDR_Msk (0x7FUL << HCSPLT_HUBADDR_Pos) // 0x00003F80 +#define HCSPLT_HUBADDR HCSPLT_HUBADDR_Msk // Hub address +#define HCSPLT_HUBADDR_0 (0x01UL << HCSPLT_HUBADDR_Pos) // 0x00000080 +#define HCSPLT_HUBADDR_1 (0x02UL << HCSPLT_HUBADDR_Pos) // 0x00000100 +#define HCSPLT_HUBADDR_2 (0x04UL << HCSPLT_HUBADDR_Pos) // 0x00000200 +#define HCSPLT_HUBADDR_3 (0x08UL << HCSPLT_HUBADDR_Pos) // 0x00000400 +#define HCSPLT_HUBADDR_4 (0x10UL << HCSPLT_HUBADDR_Pos) // 0x00000800 +#define HCSPLT_HUBADDR_5 (0x20UL << HCSPLT_HUBADDR_Pos) // 0x00001000 +#define HCSPLT_HUBADDR_6 (0x40UL << HCSPLT_HUBADDR_Pos) // 0x00002000 #define HCSPLT_XACTPOS_Pos (14U) -#define HCSPLT_XACTPOS_Msk (0x3UL << HCSPLT_XACTPOS_Pos) // 0x0000C000 */ -#define HCSPLT_XACTPOS HCSPLT_XACTPOS_Msk // XACTPOS */ -#define HCSPLT_XACTPOS_0 (0x1UL << HCSPLT_XACTPOS_Pos) // 0x00004000 */ -#define HCSPLT_XACTPOS_1 (0x2UL << HCSPLT_XACTPOS_Pos) // 0x00008000 */ +#define HCSPLT_XACTPOS_Msk (0x3UL << HCSPLT_XACTPOS_Pos) // 0x0000C000 +#define HCSPLT_XACTPOS HCSPLT_XACTPOS_Msk // XACTPOS +#define HCSPLT_XACTPOS_0 (0x1UL << HCSPLT_XACTPOS_Pos) // 0x00004000 +#define HCSPLT_XACTPOS_1 (0x2UL << HCSPLT_XACTPOS_Pos) // 0x00008000 #define HCSPLT_COMPLSPLT_Pos (16U) -#define HCSPLT_COMPLSPLT_Msk (0x1UL << HCSPLT_COMPLSPLT_Pos) // 0x00010000 */ -#define HCSPLT_COMPLSPLT HCSPLT_COMPLSPLT_Msk // Do complete split */ +#define HCSPLT_COMPLSPLT_Msk (0x1UL << HCSPLT_COMPLSPLT_Pos) // 0x00010000 +#define HCSPLT_COMPLSPLT HCSPLT_COMPLSPLT_Msk // Do complete split #define HCSPLT_SPLITEN_Pos (31U) -#define HCSPLT_SPLITEN_Msk (0x1UL << HCSPLT_SPLITEN_Pos) // 0x80000000 */ -#define HCSPLT_SPLITEN HCSPLT_SPLITEN_Msk // Split enable */ +#define HCSPLT_SPLITEN_Msk (0x1UL << HCSPLT_SPLITEN_Pos) // 0x80000000 +#define HCSPLT_SPLITEN HCSPLT_SPLITEN_Msk // Split enable /******************** Bit definition for HCINT register ********************/ #define HCINT_XFRC_Pos (0U) -#define HCINT_XFRC_Msk (0x1UL << HCINT_XFRC_Pos) // 0x00000001 */ -#define HCINT_XFRC HCINT_XFRC_Msk // Transfer completed */ +#define HCINT_XFRC_Msk (0x1UL << HCINT_XFRC_Pos) // 0x00000001 +#define HCINT_XFRC HCINT_XFRC_Msk // Transfer completed #define HCINT_CHH_Pos (1U) -#define HCINT_CHH_Msk (0x1UL << HCINT_CHH_Pos) // 0x00000002 */ -#define HCINT_CHH HCINT_CHH_Msk // Channel halted */ +#define HCINT_CHH_Msk (0x1UL << HCINT_CHH_Pos) // 0x00000002 +#define HCINT_CHH HCINT_CHH_Msk // Channel halted #define HCINT_AHBERR_Pos (2U) -#define HCINT_AHBERR_Msk (0x1UL << HCINT_AHBERR_Pos) // 0x00000004 */ -#define HCINT_AHBERR HCINT_AHBERR_Msk // AHB error */ +#define HCINT_AHBERR_Msk (0x1UL << HCINT_AHBERR_Pos) // 0x00000004 +#define HCINT_AHBERR HCINT_AHBERR_Msk // AHB error #define HCINT_STALL_Pos (3U) -#define HCINT_STALL_Msk (0x1UL << HCINT_STALL_Pos) // 0x00000008 */ -#define HCINT_STALL HCINT_STALL_Msk // STALL response received interrupt */ +#define HCINT_STALL_Msk (0x1UL << HCINT_STALL_Pos) // 0x00000008 +#define HCINT_STALL HCINT_STALL_Msk // STALL response received interrupt #define HCINT_NAK_Pos (4U) -#define HCINT_NAK_Msk (0x1UL << HCINT_NAK_Pos) // 0x00000010 */ -#define HCINT_NAK HCINT_NAK_Msk // NAK response received interrupt */ +#define HCINT_NAK_Msk (0x1UL << HCINT_NAK_Pos) // 0x00000010 +#define HCINT_NAK HCINT_NAK_Msk // NAK response received interrupt #define HCINT_ACK_Pos (5U) -#define HCINT_ACK_Msk (0x1UL << HCINT_ACK_Pos) // 0x00000020 */ -#define HCINT_ACK HCINT_ACK_Msk // ACK response received/transmitted interrupt */ +#define HCINT_ACK_Msk (0x1UL << HCINT_ACK_Pos) // 0x00000020 +#define HCINT_ACK HCINT_ACK_Msk // ACK response received/transmitted interrupt #define HCINT_NYET_Pos (6U) -#define HCINT_NYET_Msk (0x1UL << HCINT_NYET_Pos) // 0x00000040 */ -#define HCINT_NYET HCINT_NYET_Msk // Response received interrupt */ +#define HCINT_NYET_Msk (0x1UL << HCINT_NYET_Pos) // 0x00000040 +#define HCINT_NYET HCINT_NYET_Msk // Response received interrupt #define HCINT_TXERR_Pos (7U) -#define HCINT_TXERR_Msk (0x1UL << HCINT_TXERR_Pos) // 0x00000080 */ -#define HCINT_TXERR HCINT_TXERR_Msk // Transaction error */ +#define HCINT_TXERR_Msk (0x1UL << HCINT_TXERR_Pos) // 0x00000080 +#define HCINT_TXERR HCINT_TXERR_Msk // Transaction error #define HCINT_BBERR_Pos (8U) -#define HCINT_BBERR_Msk (0x1UL << HCINT_BBERR_Pos) // 0x00000100 */ -#define HCINT_BBERR HCINT_BBERR_Msk // Babble error */ +#define HCINT_BBERR_Msk (0x1UL << HCINT_BBERR_Pos) // 0x00000100 +#define HCINT_BBERR HCINT_BBERR_Msk // Babble error #define HCINT_FRMOR_Pos (9U) -#define HCINT_FRMOR_Msk (0x1UL << HCINT_FRMOR_Pos) // 0x00000200 */ -#define HCINT_FRMOR HCINT_FRMOR_Msk // Frame overrun */ +#define HCINT_FRMOR_Msk (0x1UL << HCINT_FRMOR_Pos) // 0x00000200 +#define HCINT_FRMOR HCINT_FRMOR_Msk // Frame overrun #define HCINT_DTERR_Pos (10U) -#define HCINT_DTERR_Msk (0x1UL << HCINT_DTERR_Pos) // 0x00000400 */ -#define HCINT_DTERR HCINT_DTERR_Msk // Data toggle error */ +#define HCINT_DTERR_Msk (0x1UL << HCINT_DTERR_Pos) // 0x00000400 +#define HCINT_DTERR HCINT_DTERR_Msk // Data toggle error /******************** Bit definition for DIEPINT register ********************/ #define DIEPINT_XFRC_Pos (0U) -#define DIEPINT_XFRC_Msk (0x1UL << DIEPINT_XFRC_Pos) // 0x00000001 */ -#define DIEPINT_XFRC DIEPINT_XFRC_Msk // Transfer completed interrupt */ +#define DIEPINT_XFRC_Msk (0x1UL << DIEPINT_XFRC_Pos) // 0x00000001 +#define DIEPINT_XFRC DIEPINT_XFRC_Msk // Transfer completed interrupt #define DIEPINT_EPDISD_Pos (1U) -#define DIEPINT_EPDISD_Msk (0x1UL << DIEPINT_EPDISD_Pos) // 0x00000002 */ -#define DIEPINT_EPDISD DIEPINT_EPDISD_Msk // Endpoint disabled interrupt */ +#define DIEPINT_EPDISD_Msk (0x1UL << DIEPINT_EPDISD_Pos) // 0x00000002 +#define DIEPINT_EPDISD DIEPINT_EPDISD_Msk // Endpoint disabled interrupt #define DIEPINT_AHBERR_Pos (2U) -#define DIEPINT_AHBERR_Msk (0x1UL << DIEPINT_AHBERR_Pos) // 0x00000004 */ -#define DIEPINT_AHBERR DIEPINT_AHBERR_Msk // AHB Error (AHBErr) during an IN transaction */ +#define DIEPINT_AHBERR_Msk (0x1UL << DIEPINT_AHBERR_Pos) // 0x00000004 +#define DIEPINT_AHBERR DIEPINT_AHBERR_Msk // AHB Error (AHBErr) during an IN transaction #define DIEPINT_TOC_Pos (3U) -#define DIEPINT_TOC_Msk (0x1UL << DIEPINT_TOC_Pos) // 0x00000008 */ -#define DIEPINT_TOC DIEPINT_TOC_Msk // Timeout condition */ +#define DIEPINT_TOC_Msk (0x1UL << DIEPINT_TOC_Pos) // 0x00000008 +#define DIEPINT_TOC DIEPINT_TOC_Msk // Timeout condition #define DIEPINT_ITTXFE_Pos (4U) -#define DIEPINT_ITTXFE_Msk (0x1UL << DIEPINT_ITTXFE_Pos) // 0x00000010 */ -#define DIEPINT_ITTXFE DIEPINT_ITTXFE_Msk // IN token received when TxFIFO is empty */ +#define DIEPINT_ITTXFE_Msk (0x1UL << DIEPINT_ITTXFE_Pos) // 0x00000010 +#define DIEPINT_ITTXFE DIEPINT_ITTXFE_Msk // IN token received when TxFIFO is empty #define DIEPINT_INEPNM_Pos (5U) -#define DIEPINT_INEPNM_Msk (0x1UL << DIEPINT_INEPNM_Pos) // 0x00000020 */ -#define DIEPINT_INEPNM DIEPINT_INEPNM_Msk // IN token received with EP mismatch */ +#define DIEPINT_INEPNM_Msk (0x1UL << DIEPINT_INEPNM_Pos) // 0x00000020 +#define DIEPINT_INEPNM DIEPINT_INEPNM_Msk // IN token received with EP mismatch #define DIEPINT_INEPNE_Pos (6U) -#define DIEPINT_INEPNE_Msk (0x1UL << DIEPINT_INEPNE_Pos) // 0x00000040 */ -#define DIEPINT_INEPNE DIEPINT_INEPNE_Msk // IN endpoint NAK effective */ +#define DIEPINT_INEPNE_Msk (0x1UL << DIEPINT_INEPNE_Pos) // 0x00000040 +#define DIEPINT_INEPNE DIEPINT_INEPNE_Msk // IN endpoint NAK effective #define DIEPINT_TXFE_Pos (7U) -#define DIEPINT_TXFE_Msk (0x1UL << DIEPINT_TXFE_Pos) // 0x00000080 */ -#define DIEPINT_TXFE DIEPINT_TXFE_Msk // Transmit FIFO empty */ +#define DIEPINT_TXFE_Msk (0x1UL << DIEPINT_TXFE_Pos) // 0x00000080 +#define DIEPINT_TXFE DIEPINT_TXFE_Msk // Transmit FIFO empty #define DIEPINT_TXFIFOUDRN_Pos (8U) -#define DIEPINT_TXFIFOUDRN_Msk (0x1UL << DIEPINT_TXFIFOUDRN_Pos) // 0x00000100 */ -#define DIEPINT_TXFIFOUDRN DIEPINT_TXFIFOUDRN_Msk // Transmit Fifo Underrun */ +#define DIEPINT_TXFIFOUDRN_Msk (0x1UL << DIEPINT_TXFIFOUDRN_Pos) // 0x00000100 +#define DIEPINT_TXFIFOUDRN DIEPINT_TXFIFOUDRN_Msk // Transmit Fifo Underrun #define DIEPINT_BNA_Pos (9U) -#define DIEPINT_BNA_Msk (0x1UL << DIEPINT_BNA_Pos) // 0x00000200 */ -#define DIEPINT_BNA DIEPINT_BNA_Msk // Buffer not available interrupt */ +#define DIEPINT_BNA_Msk (0x1UL << DIEPINT_BNA_Pos) // 0x00000200 +#define DIEPINT_BNA DIEPINT_BNA_Msk // Buffer not available interrupt #define DIEPINT_PKTDRPSTS_Pos (11U) -#define DIEPINT_PKTDRPSTS_Msk (0x1UL << DIEPINT_PKTDRPSTS_Pos) // 0x00000800 */ -#define DIEPINT_PKTDRPSTS DIEPINT_PKTDRPSTS_Msk // Packet dropped status */ +#define DIEPINT_PKTDRPSTS_Msk (0x1UL << DIEPINT_PKTDRPSTS_Pos) // 0x00000800 +#define DIEPINT_PKTDRPSTS DIEPINT_PKTDRPSTS_Msk // Packet dropped status #define DIEPINT_BERR_Pos (12U) -#define DIEPINT_BERR_Msk (0x1UL << DIEPINT_BERR_Pos) // 0x00001000 */ -#define DIEPINT_BERR DIEPINT_BERR_Msk // Babble error interrupt */ +#define DIEPINT_BERR_Msk (0x1UL << DIEPINT_BERR_Pos) // 0x00001000 +#define DIEPINT_BERR DIEPINT_BERR_Msk // Babble error interrupt #define DIEPINT_NAK_Pos (13U) -#define DIEPINT_NAK_Msk (0x1UL << DIEPINT_NAK_Pos) // 0x00002000 */ -#define DIEPINT_NAK DIEPINT_NAK_Msk // NAK interrupt */ +#define DIEPINT_NAK_Msk (0x1UL << DIEPINT_NAK_Pos) // 0x00002000 +#define DIEPINT_NAK DIEPINT_NAK_Msk // NAK interrupt /******************** Bit definition for HCINTMSK register ********************/ #define HCINTMSK_XFRCM_Pos (0U) -#define HCINTMSK_XFRCM_Msk (0x1UL << HCINTMSK_XFRCM_Pos) // 0x00000001 */ -#define HCINTMSK_XFRCM HCINTMSK_XFRCM_Msk // Transfer completed mask */ +#define HCINTMSK_XFRCM_Msk (0x1UL << HCINTMSK_XFRCM_Pos) // 0x00000001 +#define HCINTMSK_XFRCM HCINTMSK_XFRCM_Msk // Transfer completed mask #define HCINTMSK_CHHM_Pos (1U) -#define HCINTMSK_CHHM_Msk (0x1UL << HCINTMSK_CHHM_Pos) // 0x00000002 */ -#define HCINTMSK_CHHM HCINTMSK_CHHM_Msk // Channel halted mask */ +#define HCINTMSK_CHHM_Msk (0x1UL << HCINTMSK_CHHM_Pos) // 0x00000002 +#define HCINTMSK_CHHM HCINTMSK_CHHM_Msk // Channel halted mask #define HCINTMSK_AHBERR_Pos (2U) -#define HCINTMSK_AHBERR_Msk (0x1UL << HCINTMSK_AHBERR_Pos) // 0x00000004 */ -#define HCINTMSK_AHBERR HCINTMSK_AHBERR_Msk // AHB error */ +#define HCINTMSK_AHBERR_Msk (0x1UL << HCINTMSK_AHBERR_Pos) // 0x00000004 +#define HCINTMSK_AHBERR HCINTMSK_AHBERR_Msk // AHB error #define HCINTMSK_STALLM_Pos (3U) -#define HCINTMSK_STALLM_Msk (0x1UL << HCINTMSK_STALLM_Pos) // 0x00000008 */ -#define HCINTMSK_STALLM HCINTMSK_STALLM_Msk // STALL response received interrupt mask */ +#define HCINTMSK_STALLM_Msk (0x1UL << HCINTMSK_STALLM_Pos) // 0x00000008 +#define HCINTMSK_STALLM HCINTMSK_STALLM_Msk // STALL response received interrupt mask #define HCINTMSK_NAKM_Pos (4U) -#define HCINTMSK_NAKM_Msk (0x1UL << HCINTMSK_NAKM_Pos) // 0x00000010 */ -#define HCINTMSK_NAKM HCINTMSK_NAKM_Msk // NAK response received interrupt mask */ +#define HCINTMSK_NAKM_Msk (0x1UL << HCINTMSK_NAKM_Pos) // 0x00000010 +#define HCINTMSK_NAKM HCINTMSK_NAKM_Msk // NAK response received interrupt mask #define HCINTMSK_ACKM_Pos (5U) -#define HCINTMSK_ACKM_Msk (0x1UL << HCINTMSK_ACKM_Pos) // 0x00000020 */ -#define HCINTMSK_ACKM HCINTMSK_ACKM_Msk // ACK response received/transmitted interrupt mask */ +#define HCINTMSK_ACKM_Msk (0x1UL << HCINTMSK_ACKM_Pos) // 0x00000020 +#define HCINTMSK_ACKM HCINTMSK_ACKM_Msk // ACK response received/transmitted interrupt mask #define HCINTMSK_NYET_Pos (6U) -#define HCINTMSK_NYET_Msk (0x1UL << HCINTMSK_NYET_Pos) // 0x00000040 */ -#define HCINTMSK_NYET HCINTMSK_NYET_Msk // response received interrupt mask */ +#define HCINTMSK_NYET_Msk (0x1UL << HCINTMSK_NYET_Pos) // 0x00000040 +#define HCINTMSK_NYET HCINTMSK_NYET_Msk // response received interrupt mask #define HCINTMSK_TXERRM_Pos (7U) -#define HCINTMSK_TXERRM_Msk (0x1UL << HCINTMSK_TXERRM_Pos) // 0x00000080 */ -#define HCINTMSK_TXERRM HCINTMSK_TXERRM_Msk // Transaction error mask */ +#define HCINTMSK_TXERRM_Msk (0x1UL << HCINTMSK_TXERRM_Pos) // 0x00000080 +#define HCINTMSK_TXERRM HCINTMSK_TXERRM_Msk // Transaction error mask #define HCINTMSK_BBERRM_Pos (8U) -#define HCINTMSK_BBERRM_Msk (0x1UL << HCINTMSK_BBERRM_Pos) // 0x00000100 */ -#define HCINTMSK_BBERRM HCINTMSK_BBERRM_Msk // Babble error mask */ +#define HCINTMSK_BBERRM_Msk (0x1UL << HCINTMSK_BBERRM_Pos) // 0x00000100 +#define HCINTMSK_BBERRM HCINTMSK_BBERRM_Msk // Babble error mask #define HCINTMSK_FRMORM_Pos (9U) -#define HCINTMSK_FRMORM_Msk (0x1UL << HCINTMSK_FRMORM_Pos) // 0x00000200 */ -#define HCINTMSK_FRMORM HCINTMSK_FRMORM_Msk // Frame overrun mask */ +#define HCINTMSK_FRMORM_Msk (0x1UL << HCINTMSK_FRMORM_Pos) // 0x00000200 +#define HCINTMSK_FRMORM HCINTMSK_FRMORM_Msk // Frame overrun mask #define HCINTMSK_DTERRM_Pos (10U) -#define HCINTMSK_DTERRM_Msk (0x1UL << HCINTMSK_DTERRM_Pos) // 0x00000400 */ -#define HCINTMSK_DTERRM HCINTMSK_DTERRM_Msk // Data toggle error mask */ +#define HCINTMSK_DTERRM_Msk (0x1UL << HCINTMSK_DTERRM_Pos) // 0x00000400 +#define HCINTMSK_DTERRM HCINTMSK_DTERRM_Msk // Data toggle error mask /******************** Bit definition for DIEPTSIZ register ********************/ #define DIEPTSIZ_XFRSIZ_Pos (0U) -#define DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos) // 0x0007FFFF */ -#define DIEPTSIZ_XFRSIZ DIEPTSIZ_XFRSIZ_Msk // Transfer size */ +#define DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos) // 0x0007FFFF +#define DIEPTSIZ_XFRSIZ DIEPTSIZ_XFRSIZ_Msk // Transfer size #define DIEPTSIZ_PKTCNT_Pos (19U) -#define DIEPTSIZ_PKTCNT_Msk (0x3FFUL << DIEPTSIZ_PKTCNT_Pos) // 0x1FF80000 */ -#define DIEPTSIZ_PKTCNT DIEPTSIZ_PKTCNT_Msk // Packet count */ +#define DIEPTSIZ_PKTCNT_Msk (0x3FFUL << DIEPTSIZ_PKTCNT_Pos) // 0x1FF80000 +#define DIEPTSIZ_PKTCNT DIEPTSIZ_PKTCNT_Msk // Packet count #define DIEPTSIZ_MULCNT_Pos (29U) -#define DIEPTSIZ_MULCNT_Msk (0x3UL << DIEPTSIZ_MULCNT_Pos) // 0x60000000 */ -#define DIEPTSIZ_MULCNT DIEPTSIZ_MULCNT_Msk // Packet count */ +#define DIEPTSIZ_MULCNT_Msk (0x3UL << DIEPTSIZ_MULCNT_Pos) // 0x60000000 +#define DIEPTSIZ_MULCNT DIEPTSIZ_MULCNT_Msk // Packet count /******************** Bit definition for HCTSIZ register ********************/ #define HCTSIZ_XFRSIZ_Pos (0U) -#define HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos) // 0x0007FFFF */ -#define HCTSIZ_XFRSIZ HCTSIZ_XFRSIZ_Msk // Transfer size */ +#define HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos) // 0x0007FFFF +#define HCTSIZ_XFRSIZ HCTSIZ_XFRSIZ_Msk // Transfer size #define HCTSIZ_PKTCNT_Pos (19U) -#define HCTSIZ_PKTCNT_Msk (0x3FFUL << HCTSIZ_PKTCNT_Pos) // 0x1FF80000 */ -#define HCTSIZ_PKTCNT HCTSIZ_PKTCNT_Msk // Packet count */ +#define HCTSIZ_PKTCNT_Msk (0x3FFUL << HCTSIZ_PKTCNT_Pos) // 0x1FF80000 +#define HCTSIZ_PKTCNT HCTSIZ_PKTCNT_Msk // Packet count #define HCTSIZ_DOPING_Pos (31U) -#define HCTSIZ_DOPING_Msk (0x1UL << HCTSIZ_DOPING_Pos) // 0x80000000 */ -#define HCTSIZ_DOPING HCTSIZ_DOPING_Msk // Do PING */ +#define HCTSIZ_DOPING_Msk (0x1UL << HCTSIZ_DOPING_Pos) // 0x80000000 +#define HCTSIZ_DOPING HCTSIZ_DOPING_Msk // Do PING #define HCTSIZ_DPID_Pos (29U) -#define HCTSIZ_DPID_Msk (0x3UL << HCTSIZ_DPID_Pos) // 0x60000000 */ -#define HCTSIZ_DPID HCTSIZ_DPID_Msk // Data PID */ -#define HCTSIZ_DPID_0 (0x1UL << HCTSIZ_DPID_Pos) // 0x20000000 */ -#define HCTSIZ_DPID_1 (0x2UL << HCTSIZ_DPID_Pos) // 0x40000000 */ +#define HCTSIZ_DPID_Msk (0x3UL << HCTSIZ_DPID_Pos) // 0x60000000 +#define HCTSIZ_DPID HCTSIZ_DPID_Msk // Data PID +#define HCTSIZ_DPID_0 (0x1UL << HCTSIZ_DPID_Pos) // 0x20000000 +#define HCTSIZ_DPID_1 (0x2UL << HCTSIZ_DPID_Pos) // 0x40000000 /******************** Bit definition for DIEPDMA register ********************/ #define DIEPDMA_DMAADDR_Pos (0U) -#define DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos) // 0xFFFFFFFF */ -#define DIEPDMA_DMAADDR DIEPDMA_DMAADDR_Msk // DMA address */ +#define DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos) // 0xFFFFFFFF +#define DIEPDMA_DMAADDR DIEPDMA_DMAADDR_Msk // DMA address /******************** Bit definition for HCDMA register ********************/ #define HCDMA_DMAADDR_Pos (0U) -#define HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos) // 0xFFFFFFFF */ -#define HCDMA_DMAADDR HCDMA_DMAADDR_Msk // DMA address */ +#define HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos) // 0xFFFFFFFF +#define HCDMA_DMAADDR HCDMA_DMAADDR_Msk // DMA address /******************** Bit definition for DTXFSTS register ********************/ #define DTXFSTS_INEPTFSAV_Pos (0U) -#define DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos) // 0x0000FFFF */ -#define DTXFSTS_INEPTFSAV DTXFSTS_INEPTFSAV_Msk // IN endpoint TxFIFO space available */ +#define DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos) // 0x0000FFFF +#define DTXFSTS_INEPTFSAV DTXFSTS_INEPTFSAV_Msk // IN endpoint TxFIFO space available /******************** Bit definition for DIEPTXF register ********************/ #define DIEPTXF_INEPTXSA_Pos (0U) -#define DIEPTXF_INEPTXSA_Msk (0xFFFFUL << DIEPTXF_INEPTXSA_Pos) // 0x0000FFFF */ -#define DIEPTXF_INEPTXSA DIEPTXF_INEPTXSA_Msk // IN endpoint FIFOx transmit RAM start address */ +#define DIEPTXF_INEPTXSA_Msk (0xFFFFUL << DIEPTXF_INEPTXSA_Pos) // 0x0000FFFF +#define DIEPTXF_INEPTXSA DIEPTXF_INEPTXSA_Msk // IN endpoint FIFOx transmit RAM start address #define DIEPTXF_INEPTXFD_Pos (16U) -#define DIEPTXF_INEPTXFD_Msk (0xFFFFUL << DIEPTXF_INEPTXFD_Pos) // 0xFFFF0000 */ -#define DIEPTXF_INEPTXFD DIEPTXF_INEPTXFD_Msk // IN endpoint TxFIFO depth */ +#define DIEPTXF_INEPTXFD_Msk (0xFFFFUL << DIEPTXF_INEPTXFD_Pos) // 0xFFFF0000 +#define DIEPTXF_INEPTXFD DIEPTXF_INEPTXFD_Msk // IN endpoint TxFIFO depth /******************** Bit definition for DOEPCTL register ********************/ #define DOEPCTL_MPSIZ_Pos (0U) -#define DOEPCTL_MPSIZ_Msk (0x7FFUL << DOEPCTL_MPSIZ_Pos) // 0x000007FF */ -#define DOEPCTL_MPSIZ DOEPCTL_MPSIZ_Msk // Maximum packet size */ //Bit 1 */ +#define DOEPCTL_MPSIZ_Msk (0x7FFUL << DOEPCTL_MPSIZ_Pos) // 0x000007FF +#define DOEPCTL_MPSIZ DOEPCTL_MPSIZ_Msk // Maximum packet size //Bit 1 #define DOEPCTL_USBAEP_Pos (15U) -#define DOEPCTL_USBAEP_Msk (0x1UL << DOEPCTL_USBAEP_Pos) // 0x00008000 */ -#define DOEPCTL_USBAEP DOEPCTL_USBAEP_Msk // USB active endpoint */ +#define DOEPCTL_USBAEP_Msk (0x1UL << DOEPCTL_USBAEP_Pos) // 0x00008000 +#define DOEPCTL_USBAEP DOEPCTL_USBAEP_Msk // USB active endpoint #define DOEPCTL_NAKSTS_Pos (17U) -#define DOEPCTL_NAKSTS_Msk (0x1UL << DOEPCTL_NAKSTS_Pos) // 0x00020000 */ -#define DOEPCTL_NAKSTS DOEPCTL_NAKSTS_Msk // NAK status */ +#define DOEPCTL_NAKSTS_Msk (0x1UL << DOEPCTL_NAKSTS_Pos) // 0x00020000 +#define DOEPCTL_NAKSTS DOEPCTL_NAKSTS_Msk // NAK status #define DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << DOEPCTL_SD0PID_SEVNFRM_Pos) // 0x10000000 */ -#define DOEPCTL_SD0PID_SEVNFRM DOEPCTL_SD0PID_SEVNFRM_Msk // Set DATA0 PID */ +#define DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << DOEPCTL_SD0PID_SEVNFRM_Pos) // 0x10000000 +#define DOEPCTL_SD0PID_SEVNFRM DOEPCTL_SD0PID_SEVNFRM_Msk // Set DATA0 PID #define DOEPCTL_SODDFRM_Pos (29U) -#define DOEPCTL_SODDFRM_Msk (0x1UL << DOEPCTL_SODDFRM_Pos) // 0x20000000 */ -#define DOEPCTL_SODDFRM DOEPCTL_SODDFRM_Msk // Set odd frame */ +#define DOEPCTL_SODDFRM_Msk (0x1UL << DOEPCTL_SODDFRM_Pos) // 0x20000000 +#define DOEPCTL_SODDFRM DOEPCTL_SODDFRM_Msk // Set odd frame #define DOEPCTL_EPTYP_Pos (18U) -#define DOEPCTL_EPTYP_Msk (0x3UL << DOEPCTL_EPTYP_Pos) // 0x000C0000 */ -#define DOEPCTL_EPTYP DOEPCTL_EPTYP_Msk // Endpoint type */ -#define DOEPCTL_EPTYP_0 (0x1UL << DOEPCTL_EPTYP_Pos) // 0x00040000 */ -#define DOEPCTL_EPTYP_1 (0x2UL << DOEPCTL_EPTYP_Pos) // 0x00080000 */ +#define DOEPCTL_EPTYP_Msk (0x3UL << DOEPCTL_EPTYP_Pos) // 0x000C0000 +#define DOEPCTL_EPTYP DOEPCTL_EPTYP_Msk // Endpoint type +#define DOEPCTL_EPTYP_0 (0x1UL << DOEPCTL_EPTYP_Pos) // 0x00040000 +#define DOEPCTL_EPTYP_1 (0x2UL << DOEPCTL_EPTYP_Pos) // 0x00080000 #define DOEPCTL_SNPM_Pos (20U) -#define DOEPCTL_SNPM_Msk (0x1UL << DOEPCTL_SNPM_Pos) // 0x00100000 */ -#define DOEPCTL_SNPM DOEPCTL_SNPM_Msk // Snoop mode */ +#define DOEPCTL_SNPM_Msk (0x1UL << DOEPCTL_SNPM_Pos) // 0x00100000 +#define DOEPCTL_SNPM DOEPCTL_SNPM_Msk // Snoop mode #define DOEPCTL_STALL_Pos (21U) -#define DOEPCTL_STALL_Msk (0x1UL << DOEPCTL_STALL_Pos) // 0x00200000 */ -#define DOEPCTL_STALL DOEPCTL_STALL_Msk // STALL handshake */ +#define DOEPCTL_STALL_Msk (0x1UL << DOEPCTL_STALL_Pos) // 0x00200000 +#define DOEPCTL_STALL DOEPCTL_STALL_Msk // STALL handshake #define DOEPCTL_CNAK_Pos (26U) -#define DOEPCTL_CNAK_Msk (0x1UL << DOEPCTL_CNAK_Pos) // 0x04000000 */ -#define DOEPCTL_CNAK DOEPCTL_CNAK_Msk // Clear NAK */ +#define DOEPCTL_CNAK_Msk (0x1UL << DOEPCTL_CNAK_Pos) // 0x04000000 +#define DOEPCTL_CNAK DOEPCTL_CNAK_Msk // Clear NAK #define DOEPCTL_SNAK_Pos (27U) -#define DOEPCTL_SNAK_Msk (0x1UL << DOEPCTL_SNAK_Pos) // 0x08000000 */ -#define DOEPCTL_SNAK DOEPCTL_SNAK_Msk // Set NAK */ +#define DOEPCTL_SNAK_Msk (0x1UL << DOEPCTL_SNAK_Pos) // 0x08000000 +#define DOEPCTL_SNAK DOEPCTL_SNAK_Msk // Set NAK #define DOEPCTL_EPDIS_Pos (30U) -#define DOEPCTL_EPDIS_Msk (0x1UL << DOEPCTL_EPDIS_Pos) // 0x40000000 */ -#define DOEPCTL_EPDIS DOEPCTL_EPDIS_Msk // Endpoint disable */ +#define DOEPCTL_EPDIS_Msk (0x1UL << DOEPCTL_EPDIS_Pos) // 0x40000000 +#define DOEPCTL_EPDIS DOEPCTL_EPDIS_Msk // Endpoint disable #define DOEPCTL_EPENA_Pos (31U) -#define DOEPCTL_EPENA_Msk (0x1UL << DOEPCTL_EPENA_Pos) // 0x80000000 */ -#define DOEPCTL_EPENA DOEPCTL_EPENA_Msk // Endpoint enable */ +#define DOEPCTL_EPENA_Msk (0x1UL << DOEPCTL_EPENA_Pos) // 0x80000000 +#define DOEPCTL_EPENA DOEPCTL_EPENA_Msk // Endpoint enable /******************** Bit definition for DOEPINT register ********************/ #define DOEPINT_XFRC_Pos (0U) -#define DOEPINT_XFRC_Msk (0x1UL << DOEPINT_XFRC_Pos) // 0x00000001 */ -#define DOEPINT_XFRC DOEPINT_XFRC_Msk // Transfer completed interrupt */ +#define DOEPINT_XFRC_Msk (0x1UL << DOEPINT_XFRC_Pos) // 0x00000001 +#define DOEPINT_XFRC DOEPINT_XFRC_Msk // Transfer completed interrupt #define DOEPINT_EPDISD_Pos (1U) -#define DOEPINT_EPDISD_Msk (0x1UL << DOEPINT_EPDISD_Pos) // 0x00000002 */ -#define DOEPINT_EPDISD DOEPINT_EPDISD_Msk // Endpoint disabled interrupt */ +#define DOEPINT_EPDISD_Msk (0x1UL << DOEPINT_EPDISD_Pos) // 0x00000002 +#define DOEPINT_EPDISD DOEPINT_EPDISD_Msk // Endpoint disabled interrupt #define DOEPINT_AHBERR_Pos (2U) -#define DOEPINT_AHBERR_Msk (0x1UL << DOEPINT_AHBERR_Pos) // 0x00000004 */ -#define DOEPINT_AHBERR DOEPINT_AHBERR_Msk // AHB Error (AHBErr) during an OUT transaction */ +#define DOEPINT_AHBERR_Msk (0x1UL << DOEPINT_AHBERR_Pos) // 0x00000004 +#define DOEPINT_AHBERR DOEPINT_AHBERR_Msk // AHB Error (AHBErr) during an OUT transaction #define DOEPINT_STUP_Pos (3U) -#define DOEPINT_STUP_Msk (0x1UL << DOEPINT_STUP_Pos) // 0x00000008 */ -#define DOEPINT_STUP DOEPINT_STUP_Msk // SETUP phase done */ +#define DOEPINT_STUP_Msk (0x1UL << DOEPINT_STUP_Pos) // 0x00000008 +#define DOEPINT_STUP DOEPINT_STUP_Msk // SETUP phase done #define DOEPINT_OTEPDIS_Pos (4U) -#define DOEPINT_OTEPDIS_Msk (0x1UL << DOEPINT_OTEPDIS_Pos) // 0x00000010 */ -#define DOEPINT_OTEPDIS DOEPINT_OTEPDIS_Msk // OUT token received when endpoint disabled */ +#define DOEPINT_OTEPDIS_Msk (0x1UL << DOEPINT_OTEPDIS_Pos) // 0x00000010 +#define DOEPINT_OTEPDIS DOEPINT_OTEPDIS_Msk // OUT token received when endpoint disabled #define DOEPINT_OTEPSPR_Pos (5U) -#define DOEPINT_OTEPSPR_Msk (0x1UL << DOEPINT_OTEPSPR_Pos) // 0x00000020 */ -#define DOEPINT_OTEPSPR DOEPINT_OTEPSPR_Msk // Status Phase Received For Control Write */ +#define DOEPINT_OTEPSPR_Msk (0x1UL << DOEPINT_OTEPSPR_Pos) // 0x00000020 +#define DOEPINT_OTEPSPR DOEPINT_OTEPSPR_Msk // Status Phase Received For Control Write #define DOEPINT_B2BSTUP_Pos (6U) -#define DOEPINT_B2BSTUP_Msk (0x1UL << DOEPINT_B2BSTUP_Pos) // 0x00000040 */ -#define DOEPINT_B2BSTUP DOEPINT_B2BSTUP_Msk // Back-to-back SETUP packets received */ +#define DOEPINT_B2BSTUP_Msk (0x1UL << DOEPINT_B2BSTUP_Pos) // 0x00000040 +#define DOEPINT_B2BSTUP DOEPINT_B2BSTUP_Msk // Back-to-back SETUP packets received #define DOEPINT_OUTPKTERR_Pos (8U) -#define DOEPINT_OUTPKTERR_Msk (0x1UL << DOEPINT_OUTPKTERR_Pos) // 0x00000100 */ -#define DOEPINT_OUTPKTERR DOEPINT_OUTPKTERR_Msk // OUT packet error */ +#define DOEPINT_OUTPKTERR_Msk (0x1UL << DOEPINT_OUTPKTERR_Pos) // 0x00000100 +#define DOEPINT_OUTPKTERR DOEPINT_OUTPKTERR_Msk // OUT packet error #define DOEPINT_NAK_Pos (13U) -#define DOEPINT_NAK_Msk (0x1UL << DOEPINT_NAK_Pos) // 0x00002000 */ -#define DOEPINT_NAK DOEPINT_NAK_Msk // NAK Packet is transmitted by the device */ +#define DOEPINT_NAK_Msk (0x1UL << DOEPINT_NAK_Pos) // 0x00002000 +#define DOEPINT_NAK DOEPINT_NAK_Msk // NAK Packet is transmitted by the device #define DOEPINT_NYET_Pos (14U) -#define DOEPINT_NYET_Msk (0x1UL << DOEPINT_NYET_Pos) // 0x00004000 */ -#define DOEPINT_NYET DOEPINT_NYET_Msk // NYET interrupt */ +#define DOEPINT_NYET_Msk (0x1UL << DOEPINT_NYET_Pos) // 0x00004000 +#define DOEPINT_NYET DOEPINT_NYET_Msk // NYET interrupt #define DOEPINT_STPKTRX_Pos (15U) -#define DOEPINT_STPKTRX_Msk (0x1UL << DOEPINT_STPKTRX_Pos) // 0x00008000 */ -#define DOEPINT_STPKTRX DOEPINT_STPKTRX_Msk // Setup Packet Received */ +#define DOEPINT_STPKTRX_Msk (0x1UL << DOEPINT_STPKTRX_Pos) // 0x00008000 +#define DOEPINT_STPKTRX DOEPINT_STPKTRX_Msk // Setup Packet Received /******************** Bit definition for DOEPTSIZ register ********************/ #define DOEPTSIZ_XFRSIZ_Pos (0U) -#define DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << DOEPTSIZ_XFRSIZ_Pos) // 0x0007FFFF */ -#define DOEPTSIZ_XFRSIZ DOEPTSIZ_XFRSIZ_Msk // Transfer size */ +#define DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << DOEPTSIZ_XFRSIZ_Pos) // 0x0007FFFF +#define DOEPTSIZ_XFRSIZ DOEPTSIZ_XFRSIZ_Msk // Transfer size #define DOEPTSIZ_PKTCNT_Pos (19U) -#define DOEPTSIZ_PKTCNT_Msk (0x3FFUL << DOEPTSIZ_PKTCNT_Pos) // 0x1FF80000 */ -#define DOEPTSIZ_PKTCNT DOEPTSIZ_PKTCNT_Msk // Packet count */ +#define DOEPTSIZ_PKTCNT_Msk (0x3FFUL << DOEPTSIZ_PKTCNT_Pos) // 0x1FF80000 +#define DOEPTSIZ_PKTCNT DOEPTSIZ_PKTCNT_Msk // Packet count #define DOEPTSIZ_STUPCNT_Pos (29U) -#define DOEPTSIZ_STUPCNT_Msk (0x3UL << DOEPTSIZ_STUPCNT_Pos) // 0x60000000 */ -#define DOEPTSIZ_STUPCNT DOEPTSIZ_STUPCNT_Msk // SETUP packet count */ -#define DOEPTSIZ_STUPCNT_0 (0x1UL << DOEPTSIZ_STUPCNT_Pos) // 0x20000000 */ -#define DOEPTSIZ_STUPCNT_1 (0x2UL << DOEPTSIZ_STUPCNT_Pos) // 0x40000000 */ +#define DOEPTSIZ_STUPCNT_Msk (0x3UL << DOEPTSIZ_STUPCNT_Pos) // 0x60000000 +#define DOEPTSIZ_STUPCNT DOEPTSIZ_STUPCNT_Msk // SETUP packet count +#define DOEPTSIZ_STUPCNT_0 (0x1UL << DOEPTSIZ_STUPCNT_Pos) // 0x20000000 +#define DOEPTSIZ_STUPCNT_1 (0x2UL << DOEPTSIZ_STUPCNT_Pos) // 0x40000000 /******************** Bit definition for PCGCTL register ********************/ #define PCGCTL_IF_DEV_MODE TU_BIT(31) -- cgit v1.3.1 From db3ff4b3527b9b81d381ecc21a74e76e81b2a8e9 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 31 Oct 2023 11:26:31 +0700 Subject: usb on u5a5 hs work well with correct VBVALEXTOEN/VBVALOVAL set --- hw/bsp/family_support.cmake | 2 +- hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake | 1 + hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h | 6 +++-- hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk | 1 + hw/bsp/stm32u5/family.c | 28 +++++++++++------------ src/portable/synopsys/dwc2/dcd_dwc2.c | 3 ++- src/portable/synopsys/dwc2/dwc2_stm32.h | 25 +++++++++++--------- 7 files changed, 37 insertions(+), 29 deletions(-) (limited to 'src') diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 9c625b58e..eec42160e 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -217,7 +217,7 @@ function(family_configure_common TARGET RTOS) if (NOT TARGET segger_rtt) add_library(segger_rtt STATIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c) target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT) - target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) + #target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) endif() target_link_libraries(${TARGET} PUBLIC segger_rtt) endif () diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake index 24d4ef95a..230c3b722 100644 --- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake +++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake @@ -6,5 +6,6 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32U5A5ZJTXQ_FLASH.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32U5A5xx + HSE_VALUE=16000000UL ) endfunction() diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h index c4eb94dd8..1cc61d6bb 100644 --- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h +++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h @@ -38,8 +38,8 @@ extern "C" #define LED_STATE_ON 1 // BUTTON -#define BUTTON_PORT GPIOA -#define BUTTON_PIN GPIO_PIN_0 +#define BUTTON_PORT GPIOC +#define BUTTON_PIN GPIO_PIN_13 #define BUTTON_STATE_ACTIVE 1 // UART Enable for STLink VCOM @@ -101,6 +101,8 @@ static void SystemClock_Config(void) { HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); // USB Clock + __HAL_RCC_SYSCFG_CLK_ENABLE(); + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USBPHY; PeriphClkInit.UsbPhyClockSelection = RCC_USBPHYCLKSOURCE_HSE; diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk index 13025efa6..e759cec24 100644 --- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk +++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk @@ -1,5 +1,6 @@ CFLAGS += \ -DSTM32U5A5xx \ + -DHSE_VALUE=16000000UL \ # All source paths should be relative to the top level. LD_FILE = ${BOARD_PATH}/STM32U5A5ZJTXQ_FLASH.ld diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c index 3fbc50d93..94294b25d 100644 --- a/hw/bsp/stm32u5/family.c +++ b/hw/bsp/stm32u5/family.c @@ -124,7 +124,7 @@ void board_init(void) { HAL_UART_Init(&UartHandle); - /* Configure USB FS GPIOs */ + /* Configure USB GPIOs */ /* Configure DM DP Pins */ GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12); GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -153,6 +153,12 @@ void board_init(void) { GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + /* Enable USB power on Pwrctrl CR2 register */ + HAL_PWREx_EnableVddUSB(); + + /* USB clock enable */ + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + // Enable VBUS sense (B device) via pin PA9 USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; #else @@ -164,11 +170,6 @@ void board_init(void) { USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; #endif // vbus sense - /* Enable USB power on Pwrctrl CR2 register */ - HAL_PWREx_EnableVddUSB(); - - /* USB clock enable */ - __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); #else // STM59x/Ax/Fx/Gx only have 1 USB HS port @@ -177,15 +178,7 @@ void board_init(void) { NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); #endif - // Disable VBUS sense (B device) - USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; - - // B-peripheral session valid override enable - USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; - USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; - /* USB clock enable */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); __HAL_RCC_USBPHYC_CLK_ENABLE(); @@ -195,6 +188,13 @@ void board_init(void) { /*Configuring the SYSCFG registers OTG_HS PHY*/ HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE); + + // Disable VBUS sense (B device) + USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + // B-peripheral session valid override enable + USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN; + USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL; #endif // USB_OTG_FS diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 7b50a7d54..5c5450ac2 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -1074,7 +1074,6 @@ void dcd_int_handler(uint8_t rhport) { if (int_status & GINTSTS_ENUMDNE) { // ENUMDNE is the end of reset where speed of the link is detected - dwc2->gintsts = GINTSTS_ENUMDNE; tusb_speed_t speed; @@ -1094,6 +1093,8 @@ void dcd_int_handler(uint8_t rhport) { break; } + // TODO must update GUSBCFG_TRDT according to link speed + dcd_event_bus_reset(rhport, speed, true); } diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 57df4e941..2070c3943 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -24,8 +24,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef _DWC2_STM32_H_ -#define _DWC2_STM32_H_ +#ifndef DWC2_STM32_H_ +#define DWC2_STM32_H_ #ifdef __cplusplus extern "C" { @@ -124,35 +124,36 @@ static const dwc2_controller_t _dwc2_controller[] = { // SystemCoreClock is already included by family header // extern uint32_t SystemCoreClock; -TU_ATTR_ALWAYS_INLINE -static inline void dwc2_dcd_int_enable(uint8_t rhport) { +TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { NVIC_EnableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum); } -TU_ATTR_ALWAYS_INLINE -static inline void dwc2_dcd_int_disable(uint8_t rhport) { +TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) { NVIC_DisableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum); } -TU_ATTR_ALWAYS_INLINE -static inline void dwc2_remote_wakeup_delay(void) { +TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { // try to delay for 1 ms uint32_t count = SystemCoreClock / 1000; while (count--) __NOP(); } // MCU specific PHY init, called BEFORE core reset +// - dwc2 3.30a (H5) use USB_HS_PHYC +// - dwc2 4.11a (U5) use femtoPHY static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { if (hs_phy_type == HS_PHY_TYPE_NONE) { // Enable on-chip FS PHY dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN; } else { +#if CFG_TUSB_MCU != OPT_MCU_STM32U5 // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable' dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN; +#endif // Enable on-chip HS PHY if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) { -#ifdef USB_HS_PHYC + #ifdef USB_HS_PHYC // Enable UTMI HS PHY dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN; @@ -184,7 +185,9 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { // Enable PLL internal PHY USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; -#endif + #else + + #endif } } } @@ -232,4 +235,4 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { } #endif -#endif /* _DWC2_STM32_H_ */ +#endif -- cgit v1.3.1 From 214a4afa6aafe9daac6c1c304eb305b44e8cf86d Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 31 Oct 2023 11:53:40 +0700 Subject: dwc2 flush tx,rx fifo in dcd_init() --- src/portable/synopsys/dwc2/dcd_dwc2.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 5c5450ac2..ac93632be 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -447,6 +447,14 @@ void dcd_init(uint8_t rhport) { // (non zero-length packet), send STALL back and discard. dwc2->dcfg |= DCFG_NZLSOHSK; + // flush all TX fifo and wait for it cleared + dwc2->grstctl = GRSTCTL_TXFFLSH | (0x10u << GRSTCTL_TXFNUM_Pos); + while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {} + + // flush RX fifo and wait for it cleared + dwc2->grstctl = GRSTCTL_RXFFLSH; + while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {} + // Clear all interrupts uint32_t int_mask = dwc2->gintsts; dwc2->gintsts |= int_mask; -- cgit v1.3.1 From 06c9d9a79a4426ece73052edca885f890b997fc4 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Nov 2023 16:36:28 +0700 Subject: remove legacy driver st/synopsys --- src/portable/st/synopsys/dcd_synopsys.c | 1240 ----------------------- src/portable/st/synopsys/synopsys_common.h | 1465 ---------------------------- 2 files changed, 2705 deletions(-) delete mode 100644 src/portable/st/synopsys/dcd_synopsys.c delete mode 100644 src/portable/st/synopsys/synopsys_common.h (limited to 'src') diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c deleted file mode 100644 index 2fc3adb4f..000000000 --- a/src/portable/st/synopsys/dcd_synopsys.c +++ /dev/null @@ -1,1240 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2018 Scott Shawcroft, 2019 William D. Jones for Adafruit Industries - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * Copyright (c) 2020 Jan Duempelmann - * Copyright (c) 2020 Reinhard Panhuber - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) -// We disable SOF for now until needed later on -#define USE_SOF 0 - -#if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \ - defined (STM32F107xB) || defined (STM32F107xC) -#define STM32F1_SYNOPSYS -#endif - -#if defined (STM32L475xx) || defined (STM32L476xx) || \ - defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \ - defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define STM32L4_SYNOPSYS -#endif - -#if CFG_TUD_ENABLED && \ - ( (CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_SYNOPSYS)) || \ - CFG_TUSB_MCU == OPT_MCU_STM32F2 || \ - CFG_TUSB_MCU == OPT_MCU_STM32F4 || \ - CFG_TUSB_MCU == OPT_MCU_STM32F7 || \ - CFG_TUSB_MCU == OPT_MCU_STM32H7 || \ - (CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS) || \ - CFG_TUSB_MCU == OPT_MCU_GD32VF103 ) \ - ) - -// EP_MAX : Max number of bi-directional endpoints including EP0 -// EP_FIFO_SIZE : Size of dedicated USB SRAM -#if CFG_TUSB_MCU == OPT_MCU_STM32F1 -#include "stm32f1xx.h" -#define EP_MAX_FS 4 -#define EP_FIFO_SIZE_FS 1280 - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F2 -#include "stm32f2xx.h" -#define EP_MAX_FS USB_OTG_FS_MAX_IN_ENDPOINTS -#define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F4 -#include "stm32f4xx.h" -#define EP_MAX_FS USB_OTG_FS_MAX_IN_ENDPOINTS -#define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE -#define EP_MAX_HS USB_OTG_HS_MAX_IN_ENDPOINTS -#define EP_FIFO_SIZE_HS USB_OTG_HS_TOTAL_FIFO_SIZE - -#elif CFG_TUSB_MCU == OPT_MCU_STM32H7 -#include "stm32h7xx.h" -#define EP_MAX_FS 9 -#define EP_FIFO_SIZE_FS 4096 -#define EP_MAX_HS 9 -#define EP_FIFO_SIZE_HS 4096 - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F7 -#include "stm32f7xx.h" -#define EP_MAX_FS 6 -#define EP_FIFO_SIZE_FS 1280 -#define EP_MAX_HS 9 -#define EP_FIFO_SIZE_HS 4096 - -#elif CFG_TUSB_MCU == OPT_MCU_STM32L4 -#include "stm32l4xx.h" -#define EP_MAX_FS 6 -#define EP_FIFO_SIZE_FS 1280 - -#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103 -#include "synopsys_common.h" - -// for remote wakeup delay -#define __NOP() __asm volatile ("nop") - -// These numbers are the same for the whole GD32VF103 family. -#define OTG_FS_IRQn 86 -#define EP_MAX_FS 4 -#define EP_FIFO_SIZE_FS 1280 - -// The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local -// Interrupt Controller by Nuclei. It is nearly API compatible to the -// NVIC used by ARM MCUs. -#define ECLIC_INTERRUPT_ENABLE_BASE 0xD2001001UL - -#define NVIC_EnableIRQ __eclic_enable_interrupt -#define NVIC_DisableIRQ __eclic_disable_interrupt - -static inline void __eclic_enable_interrupt (uint32_t irq) { - *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 1; -} - -static inline void __eclic_disable_interrupt (uint32_t irq){ - *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0; -} - -#else -#error "Unsupported MCUs" -#endif - -#include "device/dcd.h" - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ - -// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS -#if TUD_OPT_RHPORT == 0 -#define EP_MAX EP_MAX_FS -#define EP_FIFO_SIZE EP_FIFO_SIZE_FS -#define RHPORT_REGS_BASE USB_OTG_FS_PERIPH_BASE -#define RHPORT_IRQn OTG_FS_IRQn - -#else -#define EP_MAX EP_MAX_HS -#define EP_FIFO_SIZE EP_FIFO_SIZE_HS -#define RHPORT_REGS_BASE USB_OTG_HS_PERIPH_BASE -#define RHPORT_IRQn OTG_HS_IRQn - -#endif - -#define GLOBAL_BASE(_port) ((USB_OTG_GlobalTypeDef*) RHPORT_REGS_BASE) -#define DEVICE_BASE(_port) (USB_OTG_DeviceTypeDef *) (RHPORT_REGS_BASE + USB_OTG_DEVICE_BASE) -#define OUT_EP_BASE(_port) (USB_OTG_OUTEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_OUT_ENDPOINT_BASE) -#define IN_EP_BASE(_port) (USB_OTG_INEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_IN_ENDPOINT_BASE) -#define FIFO_BASE(_port, _x) ((volatile uint32_t *) (RHPORT_REGS_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE)) - -enum -{ - DCD_HIGH_SPEED = 0, // Highspeed mode - DCD_FULL_SPEED_USE_HS = 1, // Full speed in Highspeed port (probably with internal PHY) - DCD_FULL_SPEED = 3, // Full speed with internal PHY -}; - -static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; - -typedef struct { - uint8_t * buffer; - tu_fifo_t * ff; - uint16_t total_len; - uint16_t max_size; - uint8_t interval; -} xfer_ctl_t; - -typedef volatile uint32_t * usb_fifo_t; - -xfer_ctl_t xfer_status[EP_MAX][2]; -#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] - -// EP0 transfers are limited to 1 packet - larger sizes has to be split -static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type - -// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from usb_otg->GRXFSIZ -static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs) -static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size) - -// Calculate the RX FIFO size according to recommendations from reference manual -static inline uint16_t calc_rx_ff_size(uint16_t ep_size) -{ - return 15 + 2*(ep_size/4) + 2*EP_MAX; -} - -static void update_grxfsiz(uint8_t rhport) -{ - (void) rhport; - - USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); - - // Determine largest EP size for RX FIFO - uint16_t max_epsize = 0; - for (uint8_t epnum = 0; epnum < EP_MAX; epnum++) - { - max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size); - } - - // Update size of RX FIFO - usb_otg->GRXFSIZ = calc_rx_ff_size(max_epsize); -} - -// Setup the control endpoint 0. -static void bus_reset(uint8_t rhport) -{ - (void) rhport; - - USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); - USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); - USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); - USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); - - tu_memclr(xfer_status, sizeof(xfer_status)); - _out_ep_closed = false; - - // clear device address - dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk; - - // 1. NAK for all OUT endpoints - for(uint8_t n = 0; n < EP_MAX; n++) { - out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK; - } - - // 2. Un-mask interrupt bits - dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos); - dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM; - dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM; - - // "USB Data FIFOs" section in reference manual - // Peripheral FIFO architecture - // - // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start. - // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located - // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard - // configuration done below. - // - // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed. - // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a - // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually - // opened when the host sends an additional command: setInterface. At this point in time - // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size - // an additional memory - // - // --------------- 320 or 1024 ( 1280 or 4096 bytes ) - // | IN FIFO 0 | - // --------------- (320 or 1024) - 16 - // | IN FIFO 1 | - // --------------- (320 or 1024) - 16 - x - // | . . . . | - // --------------- (320 or 1024) - 16 - x - y - ... - z - // | IN FIFO MAX | - // --------------- - // | FREE | - // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | - // --------------- 0 - // - // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits): - // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN - // - // - All EP OUT shared a unique OUT FIFO which uses - // - 13 for setup packets + control words (up to 3 setup packets). - // - 1 for global NAK (not required/used here). - // - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1" - // - 2 for each used OUT endpoint - // - // Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum - // - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x 16 + 2 x EP_MAX = 47 + 2 x EP_MAX - // - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x EP_MAX = 271 + 2 x EP_MAX - // - // NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge - // of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX - // - // For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO - // are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to - // overwrite this. - - usb_otg->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64); - - _allocated_fifo_words_tx = 16; - - // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) - usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); - - // Fixed control EP0 size to 64 bytes - in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos); - xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64; - - out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos); - - usb_otg->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT; -} - -// Set turn-around timeout according to link speed -extern uint32_t SystemCoreClock; -static void set_turnaround(USB_OTG_GlobalTypeDef * usb_otg, tusb_speed_t speed) -{ - usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; - - if ( speed == TUSB_SPEED_HIGH ) - { - // Use fixed 0x09 for Highspeed - usb_otg->GUSBCFG |= (0x09 << USB_OTG_GUSBCFG_TRDT_Pos); - } - else - { - // Turnaround timeout depends on the MCU clock - uint32_t turnaround; - - if ( SystemCoreClock >= 32000000U ) - turnaround = 0x6U; - else if ( SystemCoreClock >= 27500000U ) - turnaround = 0x7U; - else if ( SystemCoreClock >= 24000000U ) - turnaround = 0x8U; - else if ( SystemCoreClock >= 21800000U ) - turnaround = 0x9U; - else if ( SystemCoreClock >= 20000000U ) - turnaround = 0xAU; - else if ( SystemCoreClock >= 18500000U ) - turnaround = 0xBU; - else if ( SystemCoreClock >= 17200000U ) - turnaround = 0xCU; - else if ( SystemCoreClock >= 16000000U ) - turnaround = 0xDU; - else if ( SystemCoreClock >= 15000000U ) - turnaround = 0xEU; - else - turnaround = 0xFU; - - // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz - usb_otg->GUSBCFG |= (turnaround << USB_OTG_GUSBCFG_TRDT_Pos); - } -} - -static tusb_speed_t get_speed(uint8_t rhport) -{ - (void) rhport; - USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); - uint32_t const enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos; - return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL; -} - -static void set_speed(uint8_t rhport, tusb_speed_t speed) -{ - uint32_t bitvalue; - - if ( rhport == 1 ) - { - bitvalue = ((TUSB_SPEED_HIGH == speed) ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS); - } - else - { - bitvalue = DCD_FULL_SPEED; - } - - USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); - - // Clear and set speed bits - dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos); - dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos); -} - -#if defined(USB_HS_PHYC) -static bool USB_HS_PHYCInit(void) -{ - USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE; - - // Enable LDO: Note STM32F72/3xx Reference Manual rev 3 June 2018 incorrectly defined this bit as Disabled !! - usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; - - // Wait until LDO ready - while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {} - - uint32_t phyc_pll = 0; - - // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS - switch ( HSE_VALUE ) - { - case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ ; break; - case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break; - case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ ; break; - case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ ; break; - case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ ; break; - case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk ; break; // Value not defined in header - default: - TU_ASSERT(0); - } - usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll; - - // Control the tuning interface of the High Speed PHY - // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver - usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U; - - // Enable PLL internal PHY - usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; - - // Original ST code has 2 ms delay for PLL stabilization. - // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration - - return true; -} -#endif - -static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes) -{ - (void) rhport; - - USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); - USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); - USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); - - // EP0 is limited to one packet each xfer - // We use multiple transaction of xfer->max_size length to get a whole transfer done - if(epnum == 0) { - xfer_ctl_t * const xfer = XFER_CTL_BASE(epnum, dir); - total_bytes = tu_min16(ep0_pending[dir], xfer->max_size); - ep0_pending[dir] -= total_bytes; - } - - // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here. - if(dir == TUSB_DIR_IN) { - // A full IN transfer (multiple packets, possibly) triggers XFRC. - in_ep[epnum].DIEPTSIZ = (num_packets << USB_OTG_DIEPTSIZ_PKTCNT_Pos) | - ((total_bytes << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) & USB_OTG_DIEPTSIZ_XFRSIZ_Msk); - - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK; - // For ISO endpoint set correct odd/even bit for next frame. - if ((in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP) == USB_OTG_DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) - { - // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos)); - in_ep[epnum].DIEPCTL |= (odd_frame_now ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DIEPCTL_SODDFRM_Msk); - } - // Enable fifo empty interrupt only if there are something to put in the fifo. - if(total_bytes != 0) { - dev->DIEPEMPMSK |= (1 << epnum); - } - } else { - // A full OUT transfer (multiple packets, possibly) triggers XFRC. - out_ep[epnum].DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT_Msk | USB_OTG_DOEPTSIZ_XFRSIZ); - out_ep[epnum].DOEPTSIZ |= (num_packets << USB_OTG_DOEPTSIZ_PKTCNT_Pos) | - ((total_bytes << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) & USB_OTG_DOEPTSIZ_XFRSIZ_Msk); - - out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK; - if ((out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP) == USB_OTG_DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) - { - // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos)); - out_ep[epnum].DOEPCTL |= (odd_frame_now ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DOEPCTL_SODDFRM_Msk); - } - } -} - -/*------------------------------------------------------------------*/ -/* Controller API - *------------------------------------------------------------------*/ -void dcd_init (uint8_t rhport) -{ - // Programming model begins in the last section of the chapter on the USB - // peripheral in each Reference Manual. - - USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); - - // No HNP/SRP (no OTG support), program timeout later. - if ( rhport == 1 ) - { - // On selected MCUs HS port1 can be used with external PHY via ULPI interface -#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED - // deactivate internal PHY - usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN; - - // Init The UTMI Interface - usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); - - // Select default internal VBUS Indicator and Drive for ULPI - usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); -#else - usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; -#endif - -#if defined(USB_HS_PHYC) - // Highspeed with embedded UTMI PHYC - - // Select UTMI Interface - usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL; - usb_otg->GCCFG |= USB_OTG_GCCFG_PHYHSEN; - - // Enables control of a High Speed USB PHY - USB_HS_PHYCInit(); -#endif - } else - { - // Enable internal PHY - usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; - } - - // Reset core after selecting PHY - // Wait AHB IDLE, reset then wait until it is cleared - while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {} - usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; - while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {} - - // Restart PHY clock - *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0; - - // Clear all interrupts - usb_otg->GINTSTS |= usb_otg->GINTSTS; - - // Required as part of core initialization. - // TODO: How should mode mismatch be handled? It will cause - // the core to stop working/require reset. - usb_otg->GINTMSK |= USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_MMISM; - - USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); - - // If USB host misbehaves during status portion of control xfer - // (non zero-length packet), send STALL back and discard. - dev->DCFG |= USB_OTG_DCFG_NZLSOHSK; - - set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL); - - // Enable internal USB transceiver, unless using HS core (port 1) with external PHY. - if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN; - - usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | - USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM | - USB_OTG_GINTMSK_RXFLVLM | (USE_SOF ? USB_OTG_GINTMSK_SOFM : 0); - - // Enable global interrupt - usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_GINT; - - dcd_connect(rhport); -} - -void dcd_int_enable (uint8_t rhport) -{ - (void) rhport; - NVIC_EnableIRQ(RHPORT_IRQn); -} - -void dcd_int_disable (uint8_t rhport) -{ - (void) rhport; - NVIC_DisableIRQ(RHPORT_IRQn); -} - -void dcd_set_address (uint8_t rhport, uint8_t dev_addr) -{ - USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); - dev->DCFG = (dev->DCFG & ~USB_OTG_DCFG_DAD_Msk) | (dev_addr << USB_OTG_DCFG_DAD_Pos); - - // Response with status after changing device address - dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); -} - -static void remote_wakeup_delay(void) -{ - // try to delay for 1 ms - uint32_t count = SystemCoreClock / 1000; - while ( count-- ) - { - __NOP(); - } -} - -void dcd_remote_wakeup(uint8_t rhport) -{ - (void) rhport; - - USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); - USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); - - // set remote wakeup - dev->DCTL |= USB_OTG_DCTL_RWUSIG; - - // enable SOF to detect bus resume - usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF; - usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM; - - // Per specs: remote wakeup signal bit must be clear within 1-15ms - remote_wakeup_delay(); - - dev->DCTL &= ~USB_OTG_DCTL_RWUSIG; -} - -void dcd_connect(uint8_t rhport) -{ - (void) rhport; - USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); - dev->DCTL &= ~USB_OTG_DCTL_SDIS; -} - -void dcd_disconnect(uint8_t rhport) -{ - (void) rhport; - USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); - dev->DCTL |= USB_OTG_DCTL_SDIS; -} - -void dcd_sof_enable(uint8_t rhport, bool en) -{ - (void) rhport; - (void) en; - - // TODO implement later -} - -/*------------------------------------------------------------------*/ -/* DCD Endpoint port - *------------------------------------------------------------------*/ - -bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) -{ - (void) rhport; - - USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); - USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); - USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); - USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); - - uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); - - TU_ASSERT(epnum < EP_MAX); - - xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); - xfer->max_size = tu_edpt_packet_size(desc_edpt); - xfer->interval = desc_edpt->bInterval; - - uint16_t const fifo_size = (xfer->max_size + 3) / 4; // Round up to next full word - - if(dir == TUSB_DIR_OUT) - { - // Calculate required size of RX FIFO - uint16_t const sz = calc_rx_ff_size(4*fifo_size); - - // If size_rx needs to be extended check if possible and if so enlarge it - if (usb_otg->GRXFSIZ < sz) - { - TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4); - - // Enlarge RX FIFO - usb_otg->GRXFSIZ = sz; - } - - out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) | - (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) | - (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << USB_OTG_DOEPCTL_MPSIZ_Pos); - - dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum)); - } - else - { - // "USB Data FIFOs" section in reference manual - // Peripheral FIFO architecture - // - // --------------- 320 or 1024 ( 1280 or 4096 bytes ) - // | IN FIFO 0 | - // --------------- (320 or 1024) - 16 - // | IN FIFO 1 | - // --------------- (320 or 1024) - 16 - x - // | . . . . | - // --------------- (320 or 1024) - 16 - x - y - ... - z - // | IN FIFO MAX | - // --------------- - // | FREE | - // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | - // --------------- 0 - // - // In FIFO is allocated by following rules: - // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". - - // Check if free space is available - TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE/4); - - _allocated_fifo_words_tx += fifo_size; - - TU_LOG(2, " Allocated %u bytes at offset %u", fifo_size*4, EP_FIFO_SIZE-_allocated_fifo_words_tx*4); - - // DIEPTXF starts at FIFO #1. - // Both TXFD and TXSA are in unit of 32-bit words. - usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); - - in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) | - (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) | - (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) | - (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << USB_OTG_DIEPCTL_MPSIZ_Pos); - - dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum)); - } - - return true; -} - -// Close all non-control endpoints, cancel all pending transfers if any. -void dcd_edpt_close_all (uint8_t rhport) -{ - (void) rhport; - -// USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); - USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); - USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); - USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); - - // Disable non-control interrupt - dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos); - - for(uint8_t n = 1; n < EP_MAX; n++) - { - // disable OUT endpoint - out_ep[n].DOEPCTL = 0; - xfer_status[n][TUSB_DIR_OUT].max_size = 0; - - // disable IN endpoint - in_ep[n].DIEPCTL = 0; - xfer_status[n][TUSB_DIR_IN].max_size = 0; - } - - // reset allocated fifo IN - _allocated_fifo_words_tx = 16; -} - -bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) -{ - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); - xfer->buffer = buffer; - xfer->ff = NULL; - xfer->total_len = total_bytes; - - // EP0 can only handle one packet - if(epnum == 0) { - ep0_pending[dir] = total_bytes; - // Schedule the first transaction for EP0 transfer - edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]); - return true; - } - - uint16_t num_packets = (total_bytes / xfer->max_size); - uint16_t const short_packet_size = total_bytes % xfer->max_size; - - // Zero-size packet is special case. - if(short_packet_size > 0 || (total_bytes == 0)) { - num_packets++; - } - - // Schedule packets to be sent within interrupt - edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); - - return true; -} - -// The number of bytes has to be given explicitly to allow more flexible control of how many -// bytes should be written and second to keep the return value free to give back a boolean -// success message. If total_bytes is too big, the FIFO will copy only what is available -// into the USB buffer! -bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) -{ - // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1 - TU_ASSERT(ff->item_size == 1); - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); - xfer->buffer = NULL; - xfer->ff = ff; - xfer->total_len = total_bytes; - - uint16_t num_packets = (total_bytes / xfer->max_size); - uint16_t const short_packet_size = total_bytes % xfer->max_size; - - // Zero-size packet is special case. - if(short_packet_size > 0 || (total_bytes == 0)) num_packets++; - - // Schedule packets to be sent within interrupt - edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); - - return true; -} - -static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) -{ - (void) rhport; - - USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); - USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); - USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); - USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - if(dir == TUSB_DIR_IN) { - // Only disable currently enabled non-control endpoint - if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPENA) ){ - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK | (stall ? USB_OTG_DIEPCTL_STALL : 0); - } else { - // Stop transmitting packets and NAK IN xfers. - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK; - while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_INEPNE) == 0); - - // Disable the endpoint. - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPDIS | (stall ? USB_OTG_DIEPCTL_STALL : 0); - while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_EPDISD_Msk) == 0); - in_ep[epnum].DIEPINT = USB_OTG_DIEPINT_EPDISD; - } - - // Flush the FIFO, and wait until we have confirmed it cleared. - usb_otg->GRSTCTL |= (epnum << USB_OTG_GRSTCTL_TXFNUM_Pos); - usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH; - while((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0); - } else { - // Only disable currently enabled non-control endpoint - if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA) ){ - out_ep[epnum].DOEPCTL |= stall ? USB_OTG_DOEPCTL_STALL : 0; - } else { - // Asserting GONAK is required to STALL an OUT endpoint. - // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt - // anyway, and it can't be cleared by user code. If this while loop never - // finishes, we have bigger problems than just the stack. - dev->DCTL |= USB_OTG_DCTL_SGONAK; - while((usb_otg->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0); - - // Ditto here- disable the endpoint. - out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPDIS | (stall ? USB_OTG_DOEPCTL_STALL : 0); - while((out_ep[epnum].DOEPINT & USB_OTG_DOEPINT_EPDISD_Msk) == 0); - out_ep[epnum].DOEPINT = USB_OTG_DOEPINT_EPDISD; - - // Allow other OUT endpoints to keep receiving. - dev->DCTL |= USB_OTG_DCTL_CGONAK; - } - } -} - -/** - * Close an endpoint. - */ -void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) -{ - USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - dcd_edpt_disable(rhport, ep_addr, false); - - // Update max_size - xfer_status[epnum][dir].max_size = 0; // max_size = 0 marks a disabled EP - required for changing FIFO allocation - - if (dir == TUSB_DIR_IN) - { - uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos; - uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos; - // For now only the last opened endpoint can be closed without fuss. - TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,); - _allocated_fifo_words_tx -= fifo_size; - } - else - { - _out_ep_closed = true; // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty - } -} - -void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) -{ - dcd_edpt_disable(rhport, ep_addr, true); -} - -void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) -{ - (void) rhport; - - USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); - USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - // Clear stall and reset data toggle - if(dir == TUSB_DIR_IN) { - in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; - } else { - out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; - } -} - -/*------------------------------------------------------------------*/ - -// Read a single data packet from receive FIFO -static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len) -{ - (void) rhport; - - usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0); - - // Reading full available 32 bit words from fifo - uint16_t full_words = len >> 2; - for(uint16_t i = 0; i < full_words; i++) { - uint32_t tmp = *rx_fifo; - dst[0] = tmp & 0x000000FF; - dst[1] = (tmp & 0x0000FF00) >> 8; - dst[2] = (tmp & 0x00FF0000) >> 16; - dst[3] = (tmp & 0xFF000000) >> 24; - dst += 4; - } - - // Read the remaining 1-3 bytes from fifo - uint8_t bytes_rem = len & 0x03; - if(bytes_rem != 0) { - uint32_t tmp = *rx_fifo; - dst[0] = tmp & 0x000000FF; - if(bytes_rem > 1) { - dst[1] = (tmp & 0x0000FF00) >> 8; - } - if(bytes_rem > 2) { - dst[2] = (tmp & 0x00FF0000) >> 16; - } - } -} - -// Write a single data packet to EPIN FIFO -static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, uint16_t len) -{ - (void) rhport; - - usb_fifo_t tx_fifo = FIFO_BASE(rhport, fifo_num); - - // Pushing full available 32 bit words to fifo - uint16_t full_words = len >> 2; - for(uint16_t i = 0; i < full_words; i++){ - *tx_fifo = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0]; - src += 4; - } - - // Write the remaining 1-3 bytes into fifo - uint8_t bytes_rem = len & 0x03; - if(bytes_rem){ - uint32_t tmp_word = 0; - tmp_word |= src[0]; - if(bytes_rem > 1){ - tmp_word |= src[1] << 8; - } - if(bytes_rem > 2){ - tmp_word |= src[2] << 16; - } - *tx_fifo = tmp_word; - } -} - -static void handle_rxflvl_ints(uint8_t rhport, USB_OTG_OUTEndpointTypeDef * out_ep) { - USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); - usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0); - - // Pop control word off FIFO - uint32_t ctl_word = usb_otg->GRXSTSP; - uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos; - uint8_t epnum = (ctl_word & USB_OTG_GRXSTSP_EPNUM_Msk) >> USB_OTG_GRXSTSP_EPNUM_Pos; - uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos; - - switch(pktsts) { - case 0x01: // Global OUT NAK (Interrupt) - break; - - case 0x02: // Out packet recvd - { - xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - - // Read packet off RxFIFO - if (xfer->ff) - { - // Ring buffer - tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *)(uintptr_t) rx_fifo, bcnt); - } - else - { - // Linear buffer - read_fifo_packet(rhport, xfer->buffer, bcnt); - - // Increment pointer to xfer data - xfer->buffer += bcnt; - } - - // Truncate transfer length in case of short packet - if(bcnt < xfer->max_size) { - xfer->total_len -= (out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DOEPTSIZ_XFRSIZ_Pos; - if(epnum == 0) { - xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; - ep0_pending[TUSB_DIR_OUT] = 0; - } - } - } - break; - - case 0x03: // Out packet done (Interrupt) - break; - - case 0x04: // Setup packet done (Interrupt) - out_ep[epnum].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos); - break; - - case 0x06: // Setup packet recvd - // We can receive up to three setup packets in succession, but - // only the last one is valid. - _setup_packet[0] = (* rx_fifo); - _setup_packet[1] = (* rx_fifo); - break; - - default: // Invalid - TU_BREAKPOINT(); - break; - } -} - -static void handle_epout_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTypeDef * out_ep) { - // DAINT for a given EP clears when DOEPINTx is cleared. - // OEPINT will be cleared when DAINT's out bits are cleared. - for(uint8_t n = 0; n < EP_MAX; n++) { - xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); - - if(dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) { - // SETUP packet Setup Phase done. - if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) { - out_ep[n].DOEPINT = USB_OTG_DOEPINT_STUP; - dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true); - } - - // OUT XFER complete - if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_XFRC) { - out_ep[n].DOEPINT = USB_OTG_DOEPINT_XFRC; - - // EP0 can only handle one packet - if((n == 0) && ep0_pending[TUSB_DIR_OUT]) { - // Schedule another packet to be received. - edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); - } else { - dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); - } - } - } - } -} - -static void handle_epin_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointTypeDef * in_ep) { - // DAINT for a given EP clears when DIEPINTx is cleared. - // IEPINT will be cleared when DAINT's out bits are cleared. - for ( uint8_t n = 0; n < EP_MAX; n++ ) - { - xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); - - if ( dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n)) ) - { - // IN XFER complete (entire xfer). - if ( in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC ) - { - in_ep[n].DIEPINT = USB_OTG_DIEPINT_XFRC; - - // EP0 can only handle one packet - if((n == 0) && ep0_pending[TUSB_DIR_IN]) { - // Schedule another packet to be transmitted. - edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); - } else { - dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); - } - } - - // XFER FIFO empty - if ( (in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) ) - { - // DIEPINT's TXFE bit is read-only, software cannot clear it. - // It will only be cleared by hardware when written bytes is more than - // - 64 bytes or - // - Half of TX FIFO size (configured by DIEPTXF) - - uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_PKTCNT_Msk) >> USB_OTG_DIEPTSIZ_PKTCNT_Pos; - - // Process every single packet (only whole packets can be written to fifo) - for(uint16_t i = 0; i < remaining_packets; i++) - { - uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos; - - // Packet can not be larger than ep max size - uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size); - - // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current - // EP has to be checked if the buffer can take another WHOLE packet - if(packet_size > ((in_ep[n].DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV_Msk) << 2)) break; - - // Push packet to Tx-FIFO - if (xfer->ff) - { - usb_fifo_t tx_fifo = FIFO_BASE(rhport, n); - tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size); - } - else - { - write_fifo_packet(rhport, n, xfer->buffer, packet_size); - - // Increment pointer to xfer data - xfer->buffer += packet_size; - } - } - - // Turn off TXFE if all bytes are written. - if (((in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos) == 0) - { - dev->DIEPEMPMSK &= ~(1 << n); - } - } - } - } -} - -void dcd_int_handler(uint8_t rhport) -{ - USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); - USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); - USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); - USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); - - uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK; - - if(int_status & USB_OTG_GINTSTS_USBRST) - { - // USBRST is start of reset. - usb_otg->GINTSTS = USB_OTG_GINTSTS_USBRST; - bus_reset(rhport); - } - - if(int_status & USB_OTG_GINTSTS_ENUMDNE) - { - // ENUMDNE is the end of reset where speed of the link is detected - - usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE; - - tusb_speed_t const speed = get_speed(rhport); - - set_turnaround(usb_otg, speed); - dcd_event_bus_reset(rhport, speed, true); - } - - if(int_status & USB_OTG_GINTSTS_USBSUSP) - { - usb_otg->GINTSTS = USB_OTG_GINTSTS_USBSUSP; - dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); - } - - if(int_status & USB_OTG_GINTSTS_WKUINT) - { - usb_otg->GINTSTS = USB_OTG_GINTSTS_WKUINT; - dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); - } - - // TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection - // if(int_status & USB_OTG_GINTSTS_DISCINT) - - if(int_status & USB_OTG_GINTSTS_OTGINT) - { - // OTG INT bit is read-only - uint32_t const otg_int = usb_otg->GOTGINT; - - if (otg_int & USB_OTG_GOTGINT_SEDET) - { - dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); - } - - usb_otg->GOTGINT = otg_int; - } - - if(int_status & USB_OTG_GINTSTS_SOF) - { - usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF; - - // Disable SOF interrupt since currently only used for remote wakeup detection - usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM; - - dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); - } - - // RxFIFO non-empty interrupt handling. - if(int_status & USB_OTG_GINTSTS_RXFLVL) - { - // RXFLVL bit is read-only - - // Mask out RXFLVL while reading data from FIFO - usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM; - - // Loop until all available packets were handled - do - { - handle_rxflvl_ints(rhport, out_ep); - } while(usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL); - - // Manage RX FIFO size - if (_out_ep_closed) - { - update_grxfsiz(rhport); - - // Disable flag - _out_ep_closed = false; - } - - usb_otg->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - } - - // OUT endpoint interrupt handling. - if(int_status & USB_OTG_GINTSTS_OEPINT) - { - // OEPINT is read-only - handle_epout_ints(rhport, dev, out_ep); - } - - // IN endpoint interrupt handling. - if(int_status & USB_OTG_GINTSTS_IEPINT) - { - // IEPINT bit read-only - handle_epin_ints(rhport, dev, in_ep); - } - - // // Check for Incomplete isochronous IN transfer - // if(int_status & USB_OTG_GINTSTS_IISOIXFR) { - // printf(" IISOIXFR!\r\n"); - //// TU_LOG2(" IISOIXFR!\r\n"); - // } -} - -#endif diff --git a/src/portable/st/synopsys/synopsys_common.h b/src/portable/st/synopsys/synopsys_common.h deleted file mode 100644 index ce3195b23..000000000 --- a/src/portable/st/synopsys/synopsys_common.h +++ /dev/null @@ -1,1465 +0,0 @@ -/** - ****************************************************************************** - * @file synopsys_common.h - * @author MCD Application Team - * @brief CMSIS Cortex-M3 Device USB OTG peripheral Header File. - * This file contains the USB OTG peripheral register's definitions, bits - * definitions and memory mapping for STM32F1xx devices. - * - * This file contains: - * - Data structures and the address mapping for the USB OTG peripheral - * - The Peripheral's registers declarations and bits definition - * - Macros to access the peripheral's registers hardware - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -#include "stdint.h" - -#pragma once - -#ifdef __cplusplus - #define __I volatile -#else - #define __I volatile const -#endif -#define __O volatile -#define __IO volatile -#define __IM volatile const -#define __OM volatile -#define __IOM volatile - -/** - * @brief __USB_OTG_Core_register - */ - -typedef struct -{ - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset: 000h */ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset: 004h */ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset: 008h */ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset: 00Ch */ - __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset: 010h */ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset: 014h */ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset: 018h */ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset: 01Ch */ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset: 020h */ - __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register Address offset: 024h */ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset: 028h */ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */ - uint32_t Reserved30[2]; /*!< Reserved 030h*/ - __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset: 038h */ - __IO uint32_t CID; /*!< User ID Register Address offset: 03Ch */ - uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ - __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */ - __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */ -} USB_OTG_GlobalTypeDef; - -/** - * @brief __device_Registers - */ - -typedef struct -{ - __IO uint32_t DCFG; /*!< dev Configuration Register Address offset: 800h*/ - __IO uint32_t DCTL; /*!< dev Control Register Address offset: 804h*/ - __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset: 808h*/ - uint32_t Reserved0C; /*!< Reserved 80Ch*/ - __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask Address offset: 810h*/ - __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset: 814h*/ - __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset: 818h*/ - __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset: 81Ch*/ - uint32_t Reserved20; /*!< Reserved 820h*/ - uint32_t Reserved9; /*!< Reserved 824h*/ - __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset: 828h*/ - __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset: 82Ch*/ - __IO uint32_t DTHRCTL; /*!< dev thr Address offset: 830h*/ - __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset: 834h*/ - __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset: 838h*/ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset: 83Ch*/ - uint32_t Reserved40; /*!< dedicated EP mask Address offset: 840h*/ - __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset: 844h*/ - uint32_t Reserved44[15]; /*!< Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset: 884h*/ -} USB_OTG_DeviceTypeDef; - -/** - * @brief __IN_Endpoint-Specific_Register - */ - -typedef struct -{ - __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h*/ - __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ - __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ - __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ - uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ -} USB_OTG_INEndpointTypeDef; - -/** - * @brief __OUT_Endpoint-Specific_Registers - */ - -typedef struct -{ - __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h*/ - __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ - __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ - uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ -} USB_OTG_OUTEndpointTypeDef; - -/** - * @brief __Host_Mode_Register_Structures - */ - -typedef struct -{ - __IO uint32_t HCFG; /*!< Host Configuration Register 400h*/ - __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h*/ - __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h*/ - uint32_t Reserved40C; /*!< Reserved 40Ch*/ - __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h*/ - __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h*/ - __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h*/ -} USB_OTG_HostTypeDef; - -/** - * @brief __Host_Channel_Specific_Registers - */ - -typedef struct -{ - __IO uint32_t HCCHAR; - __IO uint32_t HCSPLT; - __IO uint32_t HCINT; - __IO uint32_t HCINTMSK; - __IO uint32_t HCTSIZ; - __IO uint32_t HCDMA; - uint32_t Reserved[2]; -} USB_OTG_HostChannelTypeDef; - -/*!< USB registers base address */ -#define USB_OTG_FS_PERIPH_BASE 0x50000000UL - -#define USB_OTG_GLOBAL_BASE 0x00000000UL -#define USB_OTG_DEVICE_BASE 0x00000800UL -#define USB_OTG_IN_ENDPOINT_BASE 0x00000900UL -#define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00UL -#define USB_OTG_EP_REG_SIZE 0x00000020UL -#define USB_OTG_HOST_BASE 0x00000400UL -#define USB_OTG_HOST_PORT_BASE 0x00000440UL -#define USB_OTG_HOST_CHANNEL_BASE 0x00000500UL -#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020UL -#define USB_OTG_PCGCCTL_BASE 0x00000E00UL -#define USB_OTG_FIFO_BASE 0x00001000UL -#define USB_OTG_FIFO_SIZE 0x00001000UL - -/******************************************************************************/ -/* */ -/* USB_OTG */ -/* */ -/******************************************************************************/ -/******************** Bit definition for USB_OTG_GOTGCTL register ***********/ -#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) -#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ -#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ -#define USB_OTG_GOTGCTL_SRQ_Pos (1U) -#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ -#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ -#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) -#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ -#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ -#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) -#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ -#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ -#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) -#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ -#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ -#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) -#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ -#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ -#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) -#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ -#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ -#define USB_OTG_GOTGCTL_DBCT_Pos (17U) -#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ -#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ -#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) -#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ -#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ -#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ - -/******************** Bit definition for USB_OTG_HCFG register ********************/ - -#define USB_OTG_HCFG_FSLSPCS_Pos (0U) -#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ -#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ -#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ -#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ -#define USB_OTG_HCFG_FSLSS_Pos (2U) -#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ - -/******************** Bit definition for USB_OTG_DCFG register ********************/ - -#define USB_OTG_DCFG_DSPD_Pos (0U) -#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ -#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ -#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ -#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ -#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) -#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ -#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ - -#define USB_OTG_DCFG_DAD_Pos (4U) -#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ -#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ -#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ -#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ -#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ -#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ -#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ -#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ - -#define USB_OTG_DCFG_PFIVL_Pos (11U) -#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ -#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ -#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ - -#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) -#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ -#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ -#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ - -/******************** Bit definition for USB_OTG_PCGCR register ********************/ -#define USB_OTG_PCGCR_STPPCLK_Pos (0U) -#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ -#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) -#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ -#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) -#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ -#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ - -/******************** Bit definition for USB_OTG_GOTGINT register ********************/ -#define USB_OTG_GOTGINT_SEDET_Pos (2U) -#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ -#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ -#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) -#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ -#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ -#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) -#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ -#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ -#define USB_OTG_GOTGINT_HNGDET_Pos (17U) -#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ -#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ -#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) -#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ -#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ -#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) -#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ - -/******************** Bit definition for USB_OTG_DCTL register ********************/ -#define USB_OTG_DCTL_RWUSIG_Pos (0U) -#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ -#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ -#define USB_OTG_DCTL_SDIS_Pos (1U) -#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ -#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ -#define USB_OTG_DCTL_GINSTS_Pos (2U) -#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ -#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ -#define USB_OTG_DCTL_GONSTS_Pos (3U) -#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ -#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ - -#define USB_OTG_DCTL_TCTL_Pos (4U) -#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ -#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ -#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ -#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ -#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ -#define USB_OTG_DCTL_SGINAK_Pos (7U) -#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ -#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ -#define USB_OTG_DCTL_CGINAK_Pos (8U) -#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ -#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ -#define USB_OTG_DCTL_SGONAK_Pos (9U) -#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ -#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ -#define USB_OTG_DCTL_CGONAK_Pos (10U) -#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ -#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ -#define USB_OTG_DCTL_POPRGDNE_Pos (11U) -#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ -#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ - -/******************** Bit definition for USB_OTG_HFIR register ********************/ -#define USB_OTG_HFIR_FRIVL_Pos (0U) -#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ - -/******************** Bit definition for USB_OTG_HFNUM register ********************/ -#define USB_OTG_HFNUM_FRNUM_Pos (0U) -#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ -#define USB_OTG_HFNUM_FTREM_Pos (16U) -#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ - -/******************** Bit definition for USB_OTG_DSTS register ********************/ -#define USB_OTG_DSTS_SUSPSTS_Pos (0U) -#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ -#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ - -#define USB_OTG_DSTS_ENUMSPD_Pos (1U) -#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ -#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ -#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ -#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ -#define USB_OTG_DSTS_EERR_Pos (3U) -#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ -#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ -#define USB_OTG_DSTS_FNSOF_Pos (8U) -#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ -#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ - -/******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ -#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) -#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ -#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ -#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ -#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ -#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ -#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ -#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ -#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) -#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ -#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ -#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) -#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ -#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ -#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) -#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ -#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ - -/******************** Bit definition for USB_OTG_GUSBCFG register ********************/ - -#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) -#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ -#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ -#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ -#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ -#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ -#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) -#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ -#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ -#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) -#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ -#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ -#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) -#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ -#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ -#define USB_OTG_GUSBCFG_TRDT_Pos (10U) -#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ -#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ -#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ -#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ -#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ -#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ -#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) -#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ -#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ -#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) -#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ -#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ -#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) -#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ -#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ -#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) -#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ -#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ -#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) -#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ -#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ -#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) -#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ -#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ -#define USB_OTG_GUSBCFG_PCCI_Pos (23U) -#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ -#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ -#define USB_OTG_GUSBCFG_PTCI_Pos (24U) -#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ -#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ -#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) -#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ -#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ -#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) -#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ -#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ -#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) -#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ -#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ -#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) -#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ - -/******************** Bit definition for USB_OTG_GRSTCTL register ********************/ -#define USB_OTG_GRSTCTL_CSRST_Pos (0U) -#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ -#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ -#define USB_OTG_GRSTCTL_FCRST_Pos (2U) -#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ -#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ -#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) -#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ -#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ -#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) -#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ -#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ - - -#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) -#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ -#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ -#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ -#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ -#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ -#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ -#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ -#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) -#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ -#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ -#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) -#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ -#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ - -/******************** Bit definition for USB_OTG_DIEPMSK register ********************/ -#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) -#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ -#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DIEPMSK_EPDM_Pos (1U) -#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ -#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DIEPMSK_TOM_Pos (3U) -#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ -#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ -#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) -#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ -#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ -#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) -#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ -#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ -#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) -#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ -#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ -#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) -#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ -#define USB_OTG_DIEPMSK_BIM_Pos (9U) -#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ -#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ - -/******************** Bit definition for USB_OTG_HPTXSTS register ********************/ -#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) -#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ -#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) -#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ -#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ -#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ - -#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) -#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ -#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for USB_OTG_HAINT register ********************/ -#define USB_OTG_HAINT_HAINT_Pos (0U) -#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ - -/******************** Bit definition for USB_OTG_DOEPMSK register ********************/ -#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) -#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ -#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DOEPMSK_EPDM_Pos (1U) -#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ -#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) -#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ -#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ -#define USB_OTG_DOEPMSK_STUPM_Pos (3U) -#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ -#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ -#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) -#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ -#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ -#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) -#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ -#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ -#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) -#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ -#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ -#define USB_OTG_DOEPMSK_BOIM_Pos (9U) -#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ -#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ -#define USB_OTG_DOEPMSK_BERRM_Pos (12U) -#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ -#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ -#define USB_OTG_DOEPMSK_NAKM_Pos (13U) -#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ -#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ -#define USB_OTG_DOEPMSK_NYETM_Pos (14U) -#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ -#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ -/******************** Bit definition for USB_OTG_GINTSTS register ********************/ -#define USB_OTG_GINTSTS_CMOD_Pos (0U) -#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ -#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ -#define USB_OTG_GINTSTS_MMIS_Pos (1U) -#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ -#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ -#define USB_OTG_GINTSTS_OTGINT_Pos (2U) -#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ -#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ -#define USB_OTG_GINTSTS_SOF_Pos (3U) -#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ -#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ -#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) -#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ -#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ -#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) -#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ -#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ -#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) -#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ -#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ -#define USB_OTG_GINTSTS_ESUSP_Pos (10U) -#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ -#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ -#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) -#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ -#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ -#define USB_OTG_GINTSTS_USBRST_Pos (12U) -#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ -#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ -#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) -#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ -#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ -#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) -#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ -#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ -#define USB_OTG_GINTSTS_EOPF_Pos (15U) -#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ -#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ -#define USB_OTG_GINTSTS_IEPINT_Pos (18U) -#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ -#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ -#define USB_OTG_GINTSTS_OEPINT_Pos (19U) -#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ -#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ -#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) -#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ -#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ -#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) -#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ -#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) -#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ -#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ -#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) -#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ -#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ -#define USB_OTG_GINTSTS_HCINT_Pos (25U) -#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ -#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ -#define USB_OTG_GINTSTS_PTXFE_Pos (26U) -#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ -#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ -#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) -#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ -#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ -#define USB_OTG_GINTSTS_DISCINT_Pos (29U) -#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ -#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ -#define USB_OTG_GINTSTS_SRQINT_Pos (30U) -#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ -#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ - -/******************** Bit definition for USB_OTG_GINTMSK register ********************/ -#define USB_OTG_GINTMSK_MMISM_Pos (1U) -#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ -#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ -#define USB_OTG_GINTMSK_OTGINT_Pos (2U) -#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ -#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ -#define USB_OTG_GINTMSK_SOFM_Pos (3U) -#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ -#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ -#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) -#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ -#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ -#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) -#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ -#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ -#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) -#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ -#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ -#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) -#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ -#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) -#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ -#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ -#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) -#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ -#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ -#define USB_OTG_GINTMSK_USBRST_Pos (12U) -#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ -#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ -#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) -#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ -#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ -#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) -#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ -#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ -#define USB_OTG_GINTMSK_EOPFM_Pos (15U) -#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ -#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ -#define USB_OTG_GINTMSK_EPMISM_Pos (17U) -#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ -#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ -#define USB_OTG_GINTMSK_IEPINT_Pos (18U) -#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ -#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ -#define USB_OTG_GINTMSK_OEPINT_Pos (19U) -#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ -#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ -#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) -#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ -#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ -#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) -#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ -#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ -#define USB_OTG_GINTMSK_PRTIM_Pos (24U) -#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ -#define USB_OTG_GINTMSK_HCIM_Pos (25U) -#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ -#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ -#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) -#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ -#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ -#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) -#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ -#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ -#define USB_OTG_GINTMSK_DISCINT_Pos (29U) -#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ -#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ -#define USB_OTG_GINTMSK_SRQIM_Pos (30U) -#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ -#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ -#define USB_OTG_GINTMSK_WUIM_Pos (31U) -#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ - -/******************** Bit definition for USB_OTG_DAINT register ********************/ -#define USB_OTG_DAINT_IEPINT_Pos (0U) -#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ -#define USB_OTG_DAINT_OEPINT_Pos (16U) -#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ - -/******************** Bit definition for USB_OTG_HAINTMSK register ********************/ -#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) -#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ - -/******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_BCNT_Pos (4U) -#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_DPID_Pos (15U) -#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) -#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ - -/******************** Bit definition for USB_OTG_DAINTMSK register ********************/ -#define USB_OTG_DAINTMSK_IEPM_Pos (0U) -#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ -#define USB_OTG_DAINTMSK_OEPM_Pos (16U) -#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ - -/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ -#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) -#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ - -/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ -#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) -#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ - -/******************** Bit definition for OTG register ********************/ -#define USB_OTG_NPTXFSA_Pos (0U) -#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ -#define USB_OTG_NPTXFD_Pos (16U) -#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ -#define USB_OTG_TX0FSA_Pos (0U) -#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ -#define USB_OTG_TX0FD_Pos (16U) -#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ - -/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/ -#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) -#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ -#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ - -/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ -#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) -#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ - -#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) -#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ - -#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) -#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for USB_OTG_DTHRCTL register ********************/ -#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) -#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ -#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ -#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) -#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ -#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ - -#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) -#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ -#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ -#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ -#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) -#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ -#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ - -#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) -#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ -#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) -#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ -#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ - -/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ -#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) -#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ - -/******************** Bit definition for USB_OTG_DEACHINT register ********************/ -#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) -#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ -#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ -#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) -#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ -#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ - -/******************** Bit definition for USB_OTG_GCCFG register ********************/ -#define USB_OTG_GCCFG_PWRDWN_Pos (16U) -#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ -#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ -#define USB_OTG_GCCFG_VBUSASEN_Pos (18U) -#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */ -#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */ -#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) -#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */ -#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */ -#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) -#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */ -#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */ - -/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/ -#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) -#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ -#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ -#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) -#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ -#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ - -/******************** Bit definition for USB_OTG_CID register ********************/ -#define USB_OTG_CID_PRODUCT_ID_Pos (0U) -#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ -#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ - -/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ -#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) -#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ -#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) -#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ -#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) -#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ -#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ -#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) -#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ -#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ -#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) -#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ -#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ -#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) -#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ -#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ -#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) -#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ -#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) -#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ -#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ -#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) -#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ -#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ - -/******************** Bit definition for USB_OTG_HPRT register ********************/ -#define USB_OTG_HPRT_PCSTS_Pos (0U) -#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ -#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ -#define USB_OTG_HPRT_PCDET_Pos (1U) -#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ -#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ -#define USB_OTG_HPRT_PENA_Pos (2U) -#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ -#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ -#define USB_OTG_HPRT_PENCHNG_Pos (3U) -#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ -#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ -#define USB_OTG_HPRT_POCA_Pos (4U) -#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ -#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ -#define USB_OTG_HPRT_POCCHNG_Pos (5U) -#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ -#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ -#define USB_OTG_HPRT_PRES_Pos (6U) -#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ -#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ -#define USB_OTG_HPRT_PSUSP_Pos (7U) -#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ -#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ -#define USB_OTG_HPRT_PRST_Pos (8U) -#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ -#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - -#define USB_OTG_HPRT_PLSTS_Pos (10U) -#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ -#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ -#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ -#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ -#define USB_OTG_HPRT_PPWR_Pos (12U) -#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ -#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - -#define USB_OTG_HPRT_PTCTL_Pos (13U) -#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ -#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ -#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ -#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ -#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ -#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - -#define USB_OTG_HPRT_PSPD_Pos (17U) -#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ -#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ -#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ -#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ -#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) -#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ -#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) -#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ -#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) -#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ -#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ -#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) -#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ -#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ -#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) -#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ -#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ -#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) -#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ -#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ -#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) -#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ -#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) -#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ -#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) -#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ -#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) -#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ -#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) -#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ -#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ - -/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ -#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) -#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ - -/******************** Bit definition for USB_OTG_DIEPCTL register ********************/ -#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) -#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ -#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ -#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) -#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ -#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ -#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) -#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ -#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ -#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) -#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ - -#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) -#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ -#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ -#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ -#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ -#define USB_OTG_DIEPCTL_STALL_Pos (21U) -#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ -#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ - -#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) -#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ -#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ -#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ -#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ -#define USB_OTG_DIEPCTL_CNAK_Pos (26U) -#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ -#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ -#define USB_OTG_DIEPCTL_SNAK_Pos (27U) -#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ -#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ -#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) -#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ -#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ -#define USB_OTG_DIEPCTL_EPENA_Pos (31U) -#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ -#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ - -/******************** Bit definition for USB_OTG_HCCHAR register ********************/ -#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) -#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ -#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - -#define USB_OTG_HCCHAR_EPNUM_Pos (11U) -#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ -#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ -#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ -#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ -#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ -#define USB_OTG_HCCHAR_EPDIR_Pos (15U) -#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ -#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ -#define USB_OTG_HCCHAR_LSDEV_Pos (17U) -#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ -#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - -#define USB_OTG_HCCHAR_EPTYP_Pos (18U) -#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ -#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ -#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ -#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - -#define USB_OTG_HCCHAR_DAD_Pos (22U) -#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ -#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ -#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ -#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ -#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ -#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ -#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ -#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ -#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ -#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) -#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ -#define USB_OTG_HCCHAR_CHDIS_Pos (30U) -#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ -#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ -#define USB_OTG_HCCHAR_CHENA_Pos (31U) -#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ - -/******************** Bit definition for USB_OTG_HCSPLT register ********************/ - -#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) -#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ -#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ -#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ -#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ -#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ -#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ -#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ -#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ - -#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) -#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ -#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ -#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ -#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ -#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ -#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ -#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ -#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ -#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ - -#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) -#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ -#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ -#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ -#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ -#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) -#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ -#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ -#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) -#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ - -/******************** Bit definition for USB_OTG_HCINT register ********************/ -#define USB_OTG_HCINT_XFRC_Pos (0U) -#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ -#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ -#define USB_OTG_HCINT_CHH_Pos (1U) -#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ -#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ -#define USB_OTG_HCINT_AHBERR_Pos (2U) -#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ -#define USB_OTG_HCINT_STALL_Pos (3U) -#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ -#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ -#define USB_OTG_HCINT_NAK_Pos (4U) -#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ -#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ -#define USB_OTG_HCINT_ACK_Pos (5U) -#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ -#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ -#define USB_OTG_HCINT_NYET_Pos (6U) -#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ -#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ -#define USB_OTG_HCINT_TXERR_Pos (7U) -#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ -#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ -#define USB_OTG_HCINT_BBERR_Pos (8U) -#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ -#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ -#define USB_OTG_HCINT_FRMOR_Pos (9U) -#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ -#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ -#define USB_OTG_HCINT_DTERR_Pos (10U) -#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ -#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ - -/******************** Bit definition for USB_OTG_DIEPINT register ********************/ -#define USB_OTG_DIEPINT_XFRC_Pos (0U) -#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ -#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ -#define USB_OTG_DIEPINT_EPDISD_Pos (1U) -#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ -#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ -#define USB_OTG_DIEPINT_AHBERR_Pos (2U) -#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ -#define USB_OTG_DIEPINT_TOC_Pos (3U) -#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ -#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ -#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) -#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ -#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ -#define USB_OTG_DIEPINT_INEPNM_Pos (5U) -#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */ -#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ -#define USB_OTG_DIEPINT_INEPNE_Pos (6U) -#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ -#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ -#define USB_OTG_DIEPINT_TXFE_Pos (7U) -#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ -#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ -#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) -#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ -#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ -#define USB_OTG_DIEPINT_BNA_Pos (9U) -#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ -#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ -#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) -#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ -#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ -#define USB_OTG_DIEPINT_BERR_Pos (12U) -#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ -#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ -#define USB_OTG_DIEPINT_NAK_Pos (13U) -#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ -#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ - -/******************** Bit definition for USB_OTG_HCINTMSK register ********************/ -#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) -#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ -#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ -#define USB_OTG_HCINTMSK_CHHM_Pos (1U) -#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ -#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ -#define USB_OTG_HCINTMSK_STALLM_Pos (3U) -#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ -#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ -#define USB_OTG_HCINTMSK_NAKM_Pos (4U) -#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ -#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ -#define USB_OTG_HCINTMSK_ACKM_Pos (5U) -#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ -#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ -#define USB_OTG_HCINTMSK_NYET_Pos (6U) -#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ -#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ -#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) -#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ -#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ -#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) -#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ -#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ -#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) -#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ -#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ -#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) -#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ -#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ - -/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ - -#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) -#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ -#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ -#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) -#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ -#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ -/******************** Bit definition for USB_OTG_HCTSIZ register ********************/ -#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) -#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ -#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ -#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) -#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ -#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ -#define USB_OTG_HCTSIZ_DPID_Pos (29U) -#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ -#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ -#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ -#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for USB_OTG_DIEPDMA register ********************/ -#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) -#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ -#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ - -/******************** Bit definition for USB_OTG_HCDMA register ********************/ -#define USB_OTG_HCDMA_DMAADDR_Pos (0U) -#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ -#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ - -/******************** Bit definition for USB_OTG_DTXFSTS register ********************/ -#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) -#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ - -/******************** Bit definition for USB_OTG_DIEPTXF register ********************/ -#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) -#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ -#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) -#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ - -/******************** Bit definition for USB_OTG_DOEPCTL register ********************/ - -#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) -#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ -#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*! Date: Thu, 2 Nov 2023 15:22:02 +0700 Subject: skip tuh_max3421_spi_cs_api() in hcd_init() only call tuh_max3421_spi_cs_api() in SPI start/end transfer since Arduino port use this to call begin/endTransaction() --- src/portable/analog/max3421/hcd_max3421.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 4665c1b06..65f87f7c6 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -417,7 +417,6 @@ bool hcd_init(uint8_t rhport) { (void) rhport; tuh_max3421_int_api(rhport, false); - tuh_max3421_spi_cs_api(rhport, false); TU_LOG2_INT(sizeof(max3421_ep_t)); TU_LOG2_INT(sizeof(max3421_data_t)); -- cgit v1.3.1 From 4b9320e40ea65ca023925d0a644b116b7066e06f Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 3 Nov 2023 22:22:13 +0700 Subject: fix race condition when dev0 is removed while enumerating --- src/host/usbh.c | 70 +++++++++++++------------- src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 16 +++--- 2 files changed, 44 insertions(+), 42 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 8d75c9726..fb4fbe3cb 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -55,16 +55,12 @@ typedef struct uint8_t rhport; uint8_t hub_addr; uint8_t hub_port; - uint8_t speed; - - // enumeration is in progress, done when all interfaces are configured - volatile uint8_t enumerating; -// struct TU_ATTR_PACKED { -// uint8_t speed : 4; // packed speed to save footprint -// volatile uint8_t enumerating : 1; -// uint8_t TU_RESERVED : 3; -// }; + struct TU_ATTR_PACKED { + uint8_t speed : 4; // packed speed to save footprint + volatile uint8_t enumerating : 1; // enumeration is in progress, false if not connected or all interfaces are configured + uint8_t TU_RESERVED : 3; + }; } usbh_dev0_t; typedef struct { @@ -431,8 +427,8 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { switch (event.event_id) { case HCD_EVENT_DEVICE_ATTACH: - // due to the shared _usbh_ctrl_buf, we must complete enumerating - // one device before enumerating another one. + // due to the shared _usbh_ctrl_buf, we must complete enumerating one device before enumerating another one. + // TODO better to have an separated queue for newly attached devices if ( _dev0.enumerating ) { TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport); @@ -556,11 +552,13 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { // EP0 with setup packet TU_VERIFY(xfer->ep_addr == 0 && xfer->setup); - // pre-check to help reducing mutex lock - TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE); - + // Check if device is still connected (enumerating for dev0) uint8_t const daddr = xfer->daddr; + if ( daddr == 0 && !_dev0.enumerating) return false; + if ( daddr != 0 && get_device(daddr)->connected == 0) return false; + // pre-check to help reducing mutex lock + TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE); (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); bool const is_idle = (_ctrl_xfer.stage == CONTROL_STAGE_IDLE); @@ -917,19 +915,23 @@ void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info) } } -TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) -{ - switch (event->event_id) - { -// case HCD_EVENT_DEVICE_REMOVE: -// // FIXME device remove from a hub need an HCD API for hcd to free up endpoint -// // mark device as removing to prevent further xfer before the event is processed in usbh task -// break; +TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) { + switch (event->event_id) { + case HCD_EVENT_DEVICE_REMOVE: + // FIXME device remove from a hub need an HCD API for hcd to free up endpoint + // mark device as removing to prevent further xfer before the event is processed in usbh task - default: - osal_queue_send(_usbh_q, event, in_isr); - break; + // Check if dev0 is removed + if ((event->rhport == _dev0.rhport) && (event->connection.hub_addr == _dev0.hub_addr) && + (event->connection.hub_port == _dev0.hub_port)) { + _dev0.enumerating = 0; + } + break; + + default: break; } + + osal_queue_send(_usbh_q, event, in_isr); } //--------------------------------------------------------------------+ @@ -1294,8 +1296,7 @@ static bool _parse_configuration_descriptor (uint8_t dev_addr, tusb_desc_configu static void enum_full_complete(void); // process device enumeration -static void process_enumeration(tuh_xfer_t* xfer) -{ +static void process_enumeration(tuh_xfer_t* xfer) { // Retry a few times with transfers in enumeration since device can be unstable when starting up enum { ATTEMPT_COUNT_MAX = 3, @@ -1303,19 +1304,20 @@ static void process_enumeration(tuh_xfer_t* xfer) }; static uint8_t failed_count = 0; - if (XFER_RESULT_SUCCESS != xfer->result) - { + if (XFER_RESULT_SUCCESS != xfer->result) { // retry if not reaching max attempt - if ( failed_count < ATTEMPT_COUNT_MAX ) - { + bool retry = _dev0.enumerating && (failed_count < ATTEMPT_COUNT_MAX); + if ( retry ) { failed_count++; osal_task_delay(ATTEMPT_DELAY_MS); // delay a bit TU_LOG1("Enumeration attempt %u\r\n", failed_count); - TU_ASSERT(tuh_control_xfer(xfer), ); - }else - { + retry = tuh_control_xfer(xfer); + } + + if (!retry) { enum_full_complete(); } + return; } failed_count = 0; diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c index 93bc1bf43..f4de3c51d 100644 --- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c @@ -182,14 +182,6 @@ void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id) { root_port_t *rport = PIO_USB_ROOT_PORT(root_id); uint32_t const ints = rport->ints; - if ( ints & PIO_USB_INTS_CONNECT_BITS ) { - hcd_event_device_attach(tu_rhport, true); - } - - if ( ints & PIO_USB_INTS_DISCONNECT_BITS ) { - hcd_event_device_remove(tu_rhport, true); - } - if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS ) { handle_endpoint_irq(rport, XFER_RESULT_SUCCESS, &rport->ep_complete); } @@ -202,6 +194,14 @@ void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id) { handle_endpoint_irq(rport, XFER_RESULT_FAILED, &rport->ep_error); } + if ( ints & PIO_USB_INTS_CONNECT_BITS ) { + hcd_event_device_attach(tu_rhport, true); + } + + if ( ints & PIO_USB_INTS_DISCONNECT_BITS ) { + hcd_event_device_remove(tu_rhport, true); + } + // clear all rport->ints &= ~ints; } -- cgit v1.3.1 From 9377fd6901dd9c7b5361a9ce5c01a99cc6761750 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 3 Nov 2023 22:34:49 +0700 Subject: fix -Werror=null-dereference warning --- src/host/usbh.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index fb4fbe3cb..d8fff9905 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -554,8 +554,12 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { // Check if device is still connected (enumerating for dev0) uint8_t const daddr = xfer->daddr; - if ( daddr == 0 && !_dev0.enumerating) return false; - if ( daddr != 0 && get_device(daddr)->connected == 0) return false; + if ( daddr == 0 ) { + if (!_dev0.enumerating) return false; + } else { + usbh_device_t const* dev = get_device(daddr); + if (dev && dev->connected == 0) return false; + } // pre-check to help reducing mutex lock TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE); -- cgit v1.3.1 From 8bac68db84ccbf4f9fbd0d6075b6a1b0253c081a Mon Sep 17 00:00:00 2001 From: Antonio Vázquez Blanco Date: Wed, 11 Oct 2023 10:15:52 +0200 Subject: Add historical EP compatibility to bth class --- src/class/bth/bth_device.c | 2 +- src/class/bth/bth_device.h | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c index c5c74d26a..be36e8c11 100755 --- a/src/class/bth/bth_device.c +++ b/src/class/bth/bth_device.c @@ -204,7 +204,7 @@ bool btd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t c request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE) { // HCI command packet addressing for single function Primary Controllers - TU_VERIFY(request->bRequest == 0 && request->wValue == 0 && request->wIndex == 0); + TU_VERIFY((CFG_TUD_BTH_HISTORICAL_COMPAT && request->bRequest == 0xe0) || (request->bRequest == 0 && request->wValue == 0 && request->wIndex == 0)); } else if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE) { diff --git a/src/class/bth/bth_device.h b/src/class/bth/bth_device.h index 921bd7a1a..c23e74bfb 100755 --- a/src/class/bth/bth_device.h +++ b/src/class/bth/bth_device.h @@ -39,6 +39,13 @@ #ifndef CFG_TUD_BTH_DATA_EPSIZE #define CFG_TUD_BTH_DATA_EPSIZE 64 #endif +#ifndef CFG_TUD_BTH_HISTORICAL_COMPAT +#define CFG_TUD_BTH_HISTORICAL_COMPAT 0 +#endif +#ifndef CFG_TUD_BTH_ISO_ALT_COUNT +// See Bluetooth Core v5.3, Vol. 4, Part B, Section 2.1 +#error You must tell the driver the number of ISO endpoints to use +#endif typedef struct TU_ATTR_PACKED { -- cgit v1.3.1 From b5b34e73d6cbce1a1d85999ef92712fb98a73a84 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sun, 19 Nov 2023 16:10:16 +0100 Subject: Add dwc2 info of F429. --- src/portable/synopsys/dwc2/dwc2_info.md | 108 ++++++++++++++++---------------- src/portable/synopsys/dwc2/dwc2_info.py | 2 + 2 files changed, 56 insertions(+), 54 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index 2d8ab067f..f298f6656 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,54 +1,54 @@ -| | BCM2711 (Pi4) | EFM32GG FullSpeed | ESP32-S2 | STM32F407 Fullspeed | STM32F407 Highspeed | STM32F411 Fullspeed | STM32F412 Fullspeed | STM32F723 Fullspeed | STM32F723 HighSpeed | STM32F767 Fullspeed | STM32H743 Highspeed | STM32L476 Fullspeed | STM32U5A5 Highspeed | GD32VF103 Fullspeed | XMC4500 | -|:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------| -| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00001200 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | -| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | -| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229DCD20 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | -| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | -| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | -| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | -| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | -| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 3 | 5 | 5 | 8 | 5 | 8 | 5 | 8 | 0 | 6 | -| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 7 | 11 | 11 | 15 | 11 | 15 | 11 | 15 | 0 | 13 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nperiod_tx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - host_period_tx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - dev_token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x020001E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x0200D1E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | -| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | -| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | -| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - total_fifo_size | 4080 | 498 | 200 | 512 | 1012 | 512 | 512 | 512 | 1006 | 512 | 952 | 512 | 952 | 0 | 634 | -| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x0FF08030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x17F08030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - power_optimized | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | -| - service_interval_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_en | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - reserved13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - utmi_phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 2 | -| - dev_ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - vbus_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - a_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - b_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 7 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 | -| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | -| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| | BCM2711 (Pi4) | EFM32GG FullSpeed | ESP32-S2 | STM32F407 Fullspeed | STM32F407 Highspeed | STM32F411 Fullspeed | STM32F412 Fullspeed | STM32F429 Fullspeed | STM32F429 Highspeed | STM32F723 Fullspeed | STM32F723 HighSpeed | STM32F767 Fullspeed | STM32H743 Highspeed | STM32L476 Fullspeed | STM32U5A5 Highspeed | GD32VF103 Fullspeed | XMC4500 | +|:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------| +| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00001200 | 0x00002000 | 0x00001200 | 0x00001100 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | +| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54281A | 0x4F54281A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | +| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229DCD20 | 0x229ED520 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | +| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | +| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | +| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | +| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 3 | 5 | 3 | 5 | 5 | 8 | 5 | 8 | 5 | 8 | 0 | 6 | +| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 7 | 11 | 7 | 11 | 11 | 15 | 11 | 15 | 11 | 15 | 0 | 13 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nperiod_tx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - host_period_tx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - dev_token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x020001E8 | 0x0200D1E8 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x03EED2E8 | 0x0200D1E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | +| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | +| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | +| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - total_fifo_size | 4080 | 498 | 200 | 512 | 1012 | 512 | 512 | 512 | 1012 | 512 | 1006 | 512 | 952 | 512 | 952 | 0 | 634 | +| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x0FF08030 | 0x17F08030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x23F00030 | 0x17F08030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - power_optimized | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | +| - service_interval_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_en | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - reserved13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - utmi_phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 2 | +| - dev_ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - vbus_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - a_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - b_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 7 | 11 | 7 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 | +| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | +| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | \ No newline at end of file diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 0af6c4c77..4bcdb4fe5 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -12,6 +12,8 @@ dwc2_reg_value = { 'STM32F407 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030], 'STM32F411 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], 'STM32F412 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], + 'STM32F429 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], + 'STM32F429 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030], 'STM32F723 Fullspeed': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], 'STM32F723 HighSpeed': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030], 'STM32F767 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], -- cgit v1.3.1 From 8af470e06d032d1b9731d817741318883c0b8fa0 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sun, 19 Nov 2023 16:19:11 +0100 Subject: Fix CI --- src/portable/synopsys/dwc2/dwc2_info.md | 2 +- src/portable/synopsys/dwc2/dwc2_info.py | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index f298f6656..d093502b0 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -51,4 +51,4 @@ | - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | | - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 7 | 11 | 7 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 | | - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | -| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | \ No newline at end of file +| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 4bcdb4fe5..03c095655 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -154,6 +154,7 @@ def render_md(): # Write the Markdown table to a file with open('dwc2_info.md', 'w') as md_file: md_file.write(df.to_markdown()) + md_file.write('\n') if __name__ == '__main__': -- cgit v1.3.1 From 1f71625a32a77d5fe243f71f9e8be03c9bbc41d1 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 20 Nov 2023 21:31:06 +0700 Subject: add tuh_max3421_reg_read(), tuh_max3421_reg_read() for application usage added max3241 for feather m4 and tested --- hw/bsp/samd51/boards/feather_m4_express/board.h | 17 ++++++ hw/bsp/samd51/family.c | 28 +++++++-- src/portable/analog/max3421/hcd_max3421.c | 78 +++++++++++++++---------- 3 files changed, 86 insertions(+), 37 deletions(-) (limited to 'src') diff --git a/hw/bsp/samd51/boards/feather_m4_express/board.h b/hw/bsp/samd51/boards/feather_m4_express/board.h index 4629643fd..474163c06 100644 --- a/hw/bsp/samd51/boards/feather_m4_express/board.h +++ b/hw/bsp/samd51/boards/feather_m4_express/board.h @@ -31,6 +31,8 @@ extern "C" { #endif +#define _PINNUM(port, pin) ((port)*32 + (pin)) + // LED #define LED_PIN 23 #define LED_STATE_ON 1 @@ -43,6 +45,21 @@ #define UART_TX_PIN (32 + 17) #define UART_RX_PIN (32 + 16) +// SPI for USB host shield +#define MAX3421_SERCOM_ID 1 // SERCOM2 +#define MAX3421_SERCOM_FUNCTION 2 // function C + +#define MAX3421_SCK_PIN _PINNUM(0, 17) +#define MAX3421_MOSI_PIN _PINNUM(1, 23) +#define MAX3421_MISO_PIN _PINNUM(1, 22) +#define MAX3421_TX_PAD 2 // MOSI = PAD_3, SCK = PAD_1 +#define MAX3421_RX_PAD 2 // MISO = PAD_2 + +#define MAX3421_CS_PIN 21 // D11 + +#define MAX3421_INTR_PIN 20 // D10 +#define MAX3421_INTR_EIC_ID 4 // EIC4 + #ifdef __cplusplus } #endif diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c index bca18e1a2..2a2aee982 100644 --- a/hw/bsp/samd51/family.c +++ b/hw/bsp/samd51/family.c @@ -76,12 +76,18 @@ void USB_3_Handler(void) { // Implementation //--------------------------------------------------------------------+ -#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 +#if CFG_TUH_ENABLED && CFG_TUH_MAX3421 + +// API to read MAX3421's register. Implemented by TinyUSB +extern uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr); + +// API to write MAX3421's register. Implemented by TinyUSB +extern bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr); + #define MAX3421_SERCOM TU_XSTRCAT(SERCOM, MAX3421_SERCOM_ID) #define MAX3421_EIC_Handler TU_XSTRCAT3(EIC_, MAX3421_INTR_EIC_ID, _Handler) static void max3421_init(void); - #endif void board_init(void) { @@ -136,11 +142,23 @@ void board_init(void) { gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM); gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP); -#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 +#if CFG_TUH_ENABLED && CFG_TUH_MAX3421 max3421_init(); #endif } +void board_init_after_tusb(void) { +#if CFG_TUH_ENABLED && CFG_TUH_MAX3421 + // FeatherWing MAX3421E use MAX3421E's GPIO0 for VBUS enable + enum { + IOPINS1_ADDR = 20u << 3, // 0xA0 + }; + + uint8_t rhport = 1; + tuh_max3421_reg_write(rhport, IOPINS1_ADDR, 0x01, false); +#endif +} + //--------------------------------------------------------------------+ // Board porting API //--------------------------------------------------------------------+ @@ -182,7 +200,7 @@ uint32_t board_millis(void) { //--------------------------------------------------------------------+ // API: SPI transfer with MAX3421E, must be implemented by application //--------------------------------------------------------------------+ -#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 +#if CFG_TUH_ENABLED && CFG_TUH_MAX3421 static void max3421_init(void) { //------------- SPI Init -------------// @@ -262,7 +280,7 @@ static void max3421_init(void) { // Enable the SPI module sercom->SPI.CTRLA.bit.ENABLE = 1; - while (sercom->SPI.SYNCBUSY.bit.ENABLE); + while (sercom->SPI.SYNCBUSY.bit.ENABLE) {} //------------- External Interrupt -------------// diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 65f87f7c6..2abd74d51 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -54,6 +54,12 @@ enum { CPUCTL_ADDR = 16u << 3, // 0x80 PINCTL_ADDR = 17u << 3, // 0x88 REVISION_ADDR = 18u << 3, // 0x90 + // 19 is not used + IOPINS1_ADDR = 20u << 3, // 0xA0 + IOPINS2_ADDR = 21u << 3, // 0xA8 + GPINIRQ_ADDR = 22u << 3, // 0xB0 + GPINIEN_ADDR = 23u << 3, // 0xB8 + GPINPOL_ADDR = 24u << 3, // 0xC0 HIRQ_ADDR = 25u << 3, // 0xC8 HIEN_ADDR = 26u << 3, // 0xD0 MODE_ADDR = 27u << 3, // 0xD8 @@ -207,7 +213,9 @@ typedef struct { static max3421_data_t _hcd_data; //--------------------------------------------------------------------+ -// API: SPI transfer with MAX3421E, must be implemented by application +// API: SPI transfer with MAX3421E +// - spi_cs_api(), spi_xfer_api(), int_api(): must be implemented by application +// - reg_read(), reg_write(): is implemented by this driver, can be used by application //--------------------------------------------------------------------+ // API to control MAX3421 SPI CS @@ -220,11 +228,18 @@ extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint // API to enable/disable MAX3421 INTR pin interrupt extern void tuh_max3421_int_api(uint8_t rhport, bool enabled); +// API to read MAX3421's register. Implemented by TinyUSB +uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr); + +// API to write MAX3421's register. Implemented by TinyUSB +bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr); + //--------------------------------------------------------------------+ -// SPI Helper +// SPI Commands and Helper //--------------------------------------------------------------------+ -static void handle_connect_irq(uint8_t rhport, bool in_isr); -static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr); + +#define reg_read tuh_max3421_reg_read +#define reg_write tuh_max3421_reg_write static void max3421_spi_lock(uint8_t rhport, bool in_isr) { // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr @@ -248,61 +263,60 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) { } } -static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint16_t len, bool in_isr) { - uint8_t hirq; - reg |= CMDBYTE_WRITE; +uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr) { + uint8_t tx_buf[2] = {reg, 0}; + uint8_t rx_buf[2] = {0, 0}; max3421_spi_lock(rhport, in_isr); - - tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); - _hcd_data.hirq = hirq; - tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len); - + bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2); max3421_spi_unlock(rhport, in_isr); + _hcd_data.hirq = rx_buf[0]; + return ret ? rx_buf[1] : 0; } -static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) { - uint8_t hirq; - uint8_t const reg = RCVVFIFO_ADDR; +bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr) { + uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data}; + uint8_t rx_buf[2] = {0, 0}; max3421_spi_lock(rhport, in_isr); + bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2); + max3421_spi_unlock(rhport, in_isr); - tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); - _hcd_data.hirq = hirq; - tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len); + // HIRQ register since we are in full-duplex mode + _hcd_data.hirq = rx_buf[0]; - max3421_spi_unlock(rhport, in_isr); + return ret; } -static void reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr) { - uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data}; - uint8_t rx_buf[2] = {0, 0}; +static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint16_t len, bool in_isr) { + uint8_t hirq; + reg |= CMDBYTE_WRITE; max3421_spi_lock(rhport, in_isr); - tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2); + tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); + _hcd_data.hirq = hirq; + tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len); max3421_spi_unlock(rhport, in_isr); - // HIRQ register since we are in full-duplex mode - _hcd_data.hirq = rx_buf[0]; } -static uint8_t reg_read(uint8_t rhport, uint8_t reg, bool in_isr) { - uint8_t tx_buf[2] = {reg, 0}; - uint8_t rx_buf[2] = {0, 0}; +static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) { + uint8_t hirq; + uint8_t const reg = RCVVFIFO_ADDR; max3421_spi_lock(rhport, in_isr); - bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2); + tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); + _hcd_data.hirq = hirq; + tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len); max3421_spi_unlock(rhport, in_isr); - - _hcd_data.hirq = rx_buf[0]; - return ret ? rx_buf[1] : 0; } +//------------- register write helper -------------// static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) { reg_write(rhport, HIRQ_ADDR, data, in_isr); // HIRQ write 1 is clear -- cgit v1.3.1 From aedc92f2d31af6209b00e8a5d7abbfec02ed979b Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Nov 2023 11:25:55 +0700 Subject: fix typo in cdc line coding enum --- examples/host/cdc_msc_hid/src/tusb_config.h | 2 +- examples/host/cdc_msc_hid_freertos/src/tusb_config.h | 2 +- src/class/cdc/cdc.h | 20 +++++++++++--------- src/class/cdc/cdc_host.h | 2 +- 4 files changed, 14 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index c8e9138e3..a53000a11 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -118,7 +118,7 @@ // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t // bit rate = 115200, 1 stop bit, no parity, 8 bit data width -#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } +#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } #ifdef __cplusplus diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h index 1bed9a9b3..ba23301ed 100644 --- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h @@ -123,7 +123,7 @@ // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t // bit rate = 115200, 1 stop bit, no parity, 8 bit data width -#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } +#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } #ifdef __cplusplus diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index 4658e43af..deec32ae4 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -182,21 +182,23 @@ typedef enum CDC_REQUEST_MDLM_SEMANTIC_MODEL = 0x60, }cdc_management_request_t; -enum -{ +enum { CDC_CONTROL_LINE_STATE_DTR = 0x01, CDC_CONTROL_LINE_STATE_RTS = 0x02, }; -enum -{ - CDC_LINE_CONDING_STOP_BITS_1 = 0, // 1 bit - CDC_LINE_CONDING_STOP_BITS_1_5 = 1, // 1.5 bits - CDC_LINE_CONDING_STOP_BITS_2 = 2, // 2 bits +enum { + CDC_LINE_CODING_STOP_BITS_1 = 0, // 1 bit + CDC_LINE_CODING_STOP_BITS_1_5 = 1, // 1.5 bits + CDC_LINE_CODING_STOP_BITS_2 = 2, // 2 bits }; -enum -{ +// TODO Backward compatible for typos. Maybe removed in the future release +#define CDC_LINE_CONDING_STOP_BITS_1 CDC_LINE_CODING_STOP_BITS_1 +#define CDC_LINE_CONDING_STOP_BITS_1_5 CDC_LINE_CODING_STOP_BITS_1_5 +#define CDC_LINE_CONDING_STOP_BITS_2 CDC_LINE_CODING_STOP_BITS_2 + +enum { CDC_LINE_CODING_PARITY_NONE = 0, CDC_LINE_CODING_PARITY_ODD = 1, CDC_LINE_CODING_PARITY_EVEN = 2, diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 19552f1ee..9e5edd94e 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -44,7 +44,7 @@ // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t //#ifndef CFG_TUH_CDC_LINE_CODING_ON_ENUM -//#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } +//#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } //#endif // RX FIFO size -- cgit v1.3.1 From 025ffa200c5508c23e76316045792af4f7728da5 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Nov 2023 17:36:52 +0700 Subject: add spec version to dwc2 info --- src/portable/synopsys/dwc2/dwc2_info.md | 1 + src/portable/synopsys/dwc2/dwc2_info.py | 14 +- src/portable/synopsys/dwc2/hwcfg_list.md | 777 ------------------------------- 3 files changed, 12 insertions(+), 780 deletions(-) delete mode 100644 src/portable/synopsys/dwc2/hwcfg_list.md (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index d093502b0..8690a0755 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -2,6 +2,7 @@ |:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------| | guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00001200 | 0x00002000 | 0x00001200 | 0x00001100 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | | gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54281A | 0x4F54281A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | +| - specs version | 2.80a | 3.30a | 4.00a | 2.81a | 2.81a | 2.81a | 3.20a | 2.81a | 2.81a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | | ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | | ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229DCD20 | 0x229ED520 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | | - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 03c095655..55bec3d23 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -36,6 +36,7 @@ dwc2_reg_value = { # }, dwc2_info = {key: {field: value for field, value in zip(dwc2_reg_list, values)} for key, values in dwc2_reg_value.items()} + class GHWCFG2(ctypes.LittleEndianStructure): _fields_ = [ ("op_mode", ctypes.c_uint32, 3), @@ -130,13 +131,20 @@ def render_md(): # Create an empty list to hold the dictionaries dwc2_info_list = [] - #Iterate over the dwc2_info dictionary and extract fields + # Iterate over the dwc2_info dictionary and extract fields for device, reg_values in dwc2_info.items(): entry_dict = {"Device": device} for r_name, r_value in reg_values.items(): entry_dict[r_name] = f"0x{r_value:08X}" - # Print bit-field values - if r_name.upper() in globals(): + + if r_name == 'gsnpsid': + # Get dwc2 specs version + major = ((r_value >> 8) >> 4) & 0x0F + minor = (r_value >> 4) & 0xFF + patch = chr((r_value & 0x0F) + ord('a') - 0xA) + entry_dict[f' - specs version'] = f"{major:X}.{minor:02X}{patch}" + elif r_name.upper() in globals(): + # Get bit-field values which exist as ctypes structures class_name = globals()[r_name.upper()] ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little')) for field_name, field_type, _ in class_name._fields_: diff --git a/src/portable/synopsys/dwc2/hwcfg_list.md b/src/portable/synopsys/dwc2/hwcfg_list.md deleted file mode 100644 index b5590da00..000000000 --- a/src/portable/synopsys/dwc2/hwcfg_list.md +++ /dev/null @@ -1,777 +0,0 @@ -# DWC2 Hardware Configuration Registers - -## Broadcom BCM2711 (Pi4) - -dwc2->guid = 2708A000 -dwc2->gsnpsid = 4F54280A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 228DDD50 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 2 -hw_cfg2->point2point = 0 -hw_cfg2->hs_phy_type = 1 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 7 -hw_cfg2->num_host_ch = 7 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 0 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = FF000E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 0 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 0 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 0 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 4080 - -dwc2->ghwcfg4 = 1FF00020 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 0 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 0 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 15 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## EFM32GG FS - -dwc2->guid = 0 -dwc2->gsnpsid = 4F54330A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 228F5910 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 2 -hw_cfg2->point2point = 0 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 6 -hw_cfg2->num_host_ch = 13 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 0 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 1F204E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 0 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 1 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 0 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 0 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 498 - -dwc2->ghwcfg4 = 1BF08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 13 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## ESP32-S2 Fullspeed - -dwc2->guid = 0 -dwc2->gsnpsid = 4F54400A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 224DD930 -hw_cfg2->op_mode = 2 -hw_cfg2->arch = 3 -hw_cfg2->point2point = 0 -hw_cfg2->hs_phy_type = 1 -hw_cfg2->fs_phy_type = 2 -hw_cfg2->num_dev_ep = 6 -hw_cfg2->num_host_ch = 9 -hw_cfg2->period_channel_support = 0 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 1 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 22 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = C804B5 -hw_cfg3->xfer_size_width = 10 -hw_cfg3->packet_size_width = 5 -hw_cfg3->otg_enable = 0 -hw_cfg3->i2c_enable = 0 -hw_cfg3->vendor_ctrl_itf = 1 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 1 -hw_cfg3->otg_adp_support = 1 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 1 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 23130 - -dwc2->ghwcfg4 = D3F0A030 -hw_cfg4->num_dev_period_in_ep = 10 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 0 -hw_cfg4->hibernation = 1 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 1 -hw_cfg4->acg_enable = 1 -hw_cfg4->utmi_phy_data_width = 1 -hw_cfg4->dev_ctrl_ep_num = 10 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 0 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 0 -hw_cfg4->dedicated_fifos = 0 -hw_cfg4->num_dev_in_eps = 13 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 1 - -## STM32F407 and STM32F207 - -STM32F407 and STM32F207 are exactly the same - -### STM32F407 Fullspeed - -dwc2->guid = 1200 -dwc2->gsnpsid = 4F54281A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229DCD20 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 0 -hw_cfg2->point2point = 1 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 3 -hw_cfg2->num_host_ch = 7 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 20001E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 0 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 0 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 512 - -dwc2->ghwcfg4 = FF08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 7 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -### STM32F407 Highspeed - -dwc2->guid = 1100 -dwc2->gsnpsid = 4F54281A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229ED590 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 2 -hw_cfg2->point2point = 0 -hw_cfg2->hs_phy_type = 2 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 5 -hw_cfg2->num_host_ch = 11 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 3F403E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 1 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 0 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 0 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 1012 - -dwc2->ghwcfg4 = 17F00030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 0 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 11 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## STM32F411 Fullspeed - -dwc2->guid = 1200 -dwc2->gsnpsid = 4F54281A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229DCD20 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 0 -hw_cfg2->point2point = 1 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 3 -hw_cfg2->num_host_ch = 7 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 20001E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 0 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 0 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 512 - -dwc2->ghwcfg4 = FF08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 7 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## STM32F412 FS - -dwc2->guid = 2000 -dwc2->gsnpsid = 4F54320A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229ED520 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 0 -hw_cfg2->point2point = 1 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 5 -hw_cfg2->num_host_ch = 11 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 200D1E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 1 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 1 -hw_cfg3->lpm_mode = 1 -hw_cfg3->total_fifo_size = 512 - -dwc2->ghwcfg4 = 17F08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 11 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## STM32F723 - -### STM32F723 HighSpeed - -dwc2->guid = 3100 -dwc2->gsnpsid = 4F54330A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229FE1D0 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 2 -hw_cfg2->point2point = 0 -hw_cfg2->hs_phy_type = 3 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 8 -hw_cfg2->num_host_ch = 15 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 3EED2E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 0 -hw_cfg3->vendor_ctrl_itf = 1 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 1 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 1 -hw_cfg3->lpm_mode = 1 -hw_cfg3->total_fifo_size = 1006 - -dwc2->ghwcfg4 = 23F00030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 0 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 1 -hw_cfg4->dma_desc_enable = 1 -hw_cfg4->dma_dynamic = 0 - -### STM32F723 Fullspeed - -dwc2->guid = 3000 -dwc2->gsnpsid = 4F54330A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229ED520 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 0 -hw_cfg2->point2point = 1 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 5 -hw_cfg2->num_host_ch = 11 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 200D1E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 1 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 1 -hw_cfg3->lpm_mode = 1 -hw_cfg3->total_fifo_size = 512 - -dwc2->ghwcfg4 = 17F08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 11 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## STM32F767 FS - -dwc2->guid = 2000 -dwc2->gsnpsid = 4F54320A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229ED520 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 0 -hw_cfg2->point2point = 1 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 5 -hw_cfg2->num_host_ch = 11 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 200D1E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 1 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 1 -hw_cfg3->lpm_mode = 1 -hw_cfg3->total_fifo_size = 512 - -dwc2->ghwcfg4 = 17F08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 11 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## STM32H743 (both cores HS) - -dwc2->guid = 2300 -dwc2->gsnpsid = 4F54330A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229FE190 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 2 -hw_cfg2->point2point = 0 -hw_cfg2->hs_phy_type = 2 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 8 -hw_cfg2->num_host_ch = 15 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 3B8D2E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 0 -hw_cfg3->vendor_ctrl_itf = 1 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 1 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 1 -hw_cfg3->lpm_mode = 1 -hw_cfg3->total_fifo_size = 952 - -dwc2->ghwcfg4 = E3F00030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 0 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 1 -hw_cfg4->dma_desc_enable = 1 -hw_cfg4->dma_dynamic = 1 - -## STM32L476 FS - -dwc2->guid = 2000 -dwc2->gsnpsid = 4F54310A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229ED520 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 0 -hw_cfg2->point2point = 1 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 5 -hw_cfg2->num_host_ch = 11 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 200D1E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 1 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 1 -hw_cfg3->lpm_mode = 1 -hw_cfg3->total_fifo_size = 512 - -dwc2->ghwcfg4 = 17F08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 11 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## GD32VF103 Fullspeed - -dwc2->guid = 1000 -dwc2->gsnpsid = 0 -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 0 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 0 -hw_cfg2->point2point = 0 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 0 -hw_cfg2->num_dev_ep = 0 -hw_cfg2->num_host_ch = 0 -hw_cfg2->period_channel_support = 0 -hw_cfg2->enable_dynamic_fifo = 0 -hw_cfg2->mul_cpu_int = 0 -hw_cfg2->nperiod_tx_q_depth = 0 -hw_cfg2->host_period_tx_q_depth = 0 -hw_cfg2->dev_token_q_depth = 0 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 0 -hw_cfg3->xfer_size_width = 0 -hw_cfg3->packet_size_width = 0 -hw_cfg3->otg_enable = 0 -hw_cfg3->i2c_enable = 0 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 0 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 0 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 0 - -dwc2->ghwcfg4 = 0 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 0 -hw_cfg4->ahb_freq_min = 0 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 0 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 0 -hw_cfg4->vbus_valid_filter_enabled = 0 -hw_cfg4->a_valid_filter_enabled = 0 -hw_cfg4->b_valid_filter_enabled = 0 -hw_cfg4->dedicated_fifos = 0 -hw_cfg4->num_dev_in_eps = 0 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## XMC4500 - -dwc2->guid = AEC000 -dwc2->gsnpsid = 4F54292A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 228F5930 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 2 -hw_cfg2->point2point = 1 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 6 -hw_cfg2->num_host_ch = 13 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 0 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 27A01E5 -hw_cfg3->xfer_size_width = 5 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 0 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 0 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 634 - -dwc2->ghwcfg4 = DBF08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 13 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 1 -- cgit v1.3.1 From 01f22a9e25c9581c1a38559737a7ca7d1fc22c15 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Nov 2023 22:50:10 +0700 Subject: fix h7 running on fullspeed phy has issue with WFI if not disable ULPI clock --- src/portable/synopsys/dwc2/dwc2_stm32.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 2070c3943..dd78ccd06 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -145,6 +145,22 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { if (hs_phy_type == HS_PHY_TYPE_NONE) { // Enable on-chip FS PHY dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN; + + // https://community.st.com/t5/stm32cubemx-mcus/why-stm32h743-usb-fs-doesn-t-work-if-freertos-tickless-idle/m-p/349480#M18867 + // H7 running on full-speed phy need to disable ULPI clock in sleep mode. + // Otherwise, USB won't work when mcu executing WFI/WFE instruction i.e tick-less RTOS. + // Note: there may be other family that is affected by this, but only H7 is tested so far + #if defined(USB_OTG_FS_PERIPH_BASE) && defined(RCC_AHB1LPENR_USB2OTGFSULPILPEN) + if ( USB_OTG_FS_PERIPH_BASE == (uint32_t) dwc2 ) { + RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB2OTGFSULPILPEN; + } + #endif + + #if defined(USB_OTG_HS_PERIPH_BASE) && defined(RCC_AHB1LPENR_USB1OTGHSULPILPEN) + if ( USB_OTG_HS_PERIPH_BASE == (uint32_t) dwc2 ) { + RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB1OTGHSULPILPEN; + } + #endif } else { #if CFG_TUSB_MCU != OPT_MCU_STM32U5 // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable' -- cgit v1.3.1 From 68894398af9e8a096c700b7a4e8c127e53a2d6bc Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 1 Nov 2023 15:45:44 +1100 Subject: Add optional hooks for DCD and HCD events These are intended to allow bare metal platforms with one-shot scheduling capabilities to schedule the TinyUSB task handlers whenever they know there is work for them to do. Signed-off-by: Angus Gratton --- src/device/usbd.c | 15 +++++++++++---- src/host/usbh.c | 2 ++ src/tusb_option.h | 12 ++++++++++++ 3 files changed, 25 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index 50941c46f..2b6d07a96 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1079,6 +1079,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const //--------------------------------------------------------------------+ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr) { + bool send = false; switch (event->event_id) { case DCD_EVENT_UNPLUGGED: @@ -1086,7 +1087,7 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr) _usbd_dev.addressed = 0; _usbd_dev.cfg_num = 0; _usbd_dev.suspended = 0; - osal_queue_send(_usbd_q, event, in_isr); + send = true; break; case DCD_EVENT_SUSPEND: @@ -1097,7 +1098,7 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr) if ( _usbd_dev.connected ) { _usbd_dev.suspended = 1; - osal_queue_send(_usbd_q, event, in_isr); + send = true; } break; @@ -1106,7 +1107,7 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr) if ( _usbd_dev.connected ) { _usbd_dev.suspended = 0; - osal_queue_send(_usbd_q, event, in_isr); + send = true; } break; @@ -1129,15 +1130,21 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr) dcd_event_t const event_resume = { .rhport = event->rhport, .event_id = DCD_EVENT_RESUME }; osal_queue_send(_usbd_q, &event_resume, in_isr); + CFG_TUD_EVENT_HOOK(&event_resume, in_isr); } // skip osal queue for SOF in usbd task break; default: - osal_queue_send(_usbd_q, event, in_isr); + send = true; break; } + + if (send) { + osal_queue_send(_usbd_q, event, in_isr); + CFG_TUD_EVENT_HOOK(event, in_isr); + } } //--------------------------------------------------------------------+ diff --git a/src/host/usbh.c b/src/host/usbh.c index d8fff9905..2fdc8216d 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -780,6 +780,7 @@ void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr) { event.func_call.param = param; osal_queue_send(_usbh_q, &event, in_isr); + CFG_TUH_EVENT_HOOK(event, in_isr); } //--------------------------------------------------------------------+ @@ -936,6 +937,7 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) } osal_queue_send(_usbh_q, event, in_isr); + CFG_TUH_EVENT_HOOK(event, in_isr); } //--------------------------------------------------------------------+ diff --git a/src/tusb_option.h b/src/tusb_option.h index a29eb8a3a..aedc02dbc 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -485,6 +485,18 @@ #define tuc_int_handler(_p) #endif +//--------------------------------------------------------------------+ +// Optional event hook functions for platform integration (defaults) +//--------------------------------------------------------------------+ + +#ifndef CFG_TUD_EVENT_HOOK +#define CFG_TUD_EVENT_HOOK(EVENT, IN_ISR) +#endif + +#ifndef CFG_TUH_EVENT_HOOK +#define CFG_TUH_EVENT_HOOK(EVENT, IN_ISR) +#endif + //------------------------------------------------------------------ // Configuration Validation //------------------------------------------------------------------ -- cgit v1.3.1 From 54356a719e3968702d86346ec6305679ebd9dd0f Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 23 Nov 2023 17:53:17 +0700 Subject: minor-update --- hw/bsp/board.c | 20 ++++++++---- hw/bsp/family_support.cmake | 5 +-- hw/bsp/nrf/family.cmake | 4 +-- hw/bsp/nrf/family.mk | 3 ++ hw/bsp/stm32h7/family.cmake | 4 +-- src/osal/osal_none.h | 64 ++++++++++++++----------------------- tools/cmake/toolchain/arm_gcc.cmake | 2 +- 7 files changed, 47 insertions(+), 55 deletions(-) (limited to 'src') diff --git a/hw/bsp/board.c b/hw/bsp/board.c index 562792625..23b4b6628 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -44,13 +44,12 @@ // If using SES IDE, use the Syscalls/SEGGER_RTT_Syscalls_SES.c instead #if !(defined __SES_ARM) && !(defined __SES_RISCV) && !(defined __CROSSWORKS_ARM) - #include "SEGGER_RTT.h" -TU_ATTR_USED int sys_write(int fhdl, const void *buf, size_t count) { +TU_ATTR_USED int sys_write(int fhdl, const char *buf, size_t count) { (void) fhdl; SEGGER_RTT_Write(0, (const char *) buf, (int) count); - return count; + return (int) count; } TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) { @@ -63,10 +62,9 @@ TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) { #elif defined(LOGGER_SWO) // Logging with SWO for ARM Cortex - #include "board_mcu.h" -TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) { +TU_ATTR_USED int sys_write (int fhdl, const char *buf, size_t count) { (void) fhdl; uint8_t const* buf8 = (uint8_t const*) buf; @@ -87,7 +85,7 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { #else // Default logging with on-board UART -TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) { +TU_ATTR_USED int sys_write (int fhdl, const char *buf, size_t count) { (void) fhdl; return board_uart_write(buf, (int) count); } @@ -100,6 +98,16 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { #endif +//TU_ATTR_USED int _close(int fhdl) { +// (void) fhdl; +// return 0; +//} + +//TU_ATTR_USED int _fstat(int file, struct stat *st) { +// memset(st, 0, sizeof(*st)); +// st->st_mode = S_IFCHR; +//} + int board_getchar(void) { char c; return (sys_read(0, &c, 1) > 0) ? (int) c : (-1); diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index eec42160e..930237fea 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -201,6 +201,9 @@ function(family_configure_common TARGET RTOS) # Generate linker map file if (CMAKE_C_COMPILER_ID STREQUAL "GNU") target_link_options(${TARGET} PUBLIC "LINKER:-Map=$.map") + if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0) + target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") + endif () endif() # ETM Trace option @@ -289,13 +292,11 @@ function(family_configure_device_example TARGET RTOS) family_configure_example(${TARGET} ${RTOS}) endfunction() - # Configure host example with RTOS function(family_configure_host_example TARGET RTOS) family_configure_example(${TARGET} ${RTOS}) endfunction() - # Configure host + device example with RTOS function(family_configure_dual_usb_example TARGET RTOS) family_configure_example(${TARGET} ${RTOS}) diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 99d9ac6dd..8cee2b433 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -84,9 +84,7 @@ function(add_board_target BOARD_TARGET) # linker file "LINKER:--script=${LD_FILE_GNU}" -L${NRFX_DIR}/mdk - # nanolib - --specs=nosys.specs - --specs=nano.specs + --specs=nosys.specs --specs=nano.specs ) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${BOARD_TARGET} PUBLIC diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk index df22477df..29802dc37 100644 --- a/hw/bsp/nrf/family.mk +++ b/hw/bsp/nrf/family.mk @@ -12,6 +12,9 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_NRF5X \ -DCONFIG_GPIO_AS_PINRESET +#CFLAGS += -nostdlib +#CFLAGS += -D__START=main + # suppress warning caused by vendor mcu driver CFLAGS += \ -Wno-error=undef \ diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake index c08857a50..2d6ec76c8 100644 --- a/hw/bsp/stm32h7/family.cmake +++ b/hw/bsp/stm32h7/family.cmake @@ -66,9 +66,7 @@ function(add_board_target BOARD_TARGET) target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" -nostartfiles - # nanolib - --specs=nosys.specs - --specs=nano.specs + --specs=nosys.specs --specs=nano.specs ) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${BOARD_TARGET} PUBLIC diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h index 76e77c25d..a07d39828 100644 --- a/src/osal/osal_none.h +++ b/src/osal/osal_none.h @@ -24,11 +24,11 @@ * This file is part of the TinyUSB stack. */ -#ifndef _TUSB_OSAL_NONE_H_ -#define _TUSB_OSAL_NONE_H_ +#ifndef TUSB_OSAL_NONE_H_ +#define TUSB_OSAL_NONE_H_ #ifdef __cplusplus - extern "C" { +extern "C" { #endif //--------------------------------------------------------------------+ @@ -43,39 +43,34 @@ TU_ATTR_WEAK void osal_task_delay(uint32_t msec); //--------------------------------------------------------------------+ // Binary Semaphore API //--------------------------------------------------------------------+ -typedef struct -{ +typedef struct { volatile uint16_t count; -}osal_semaphore_def_t; +} osal_semaphore_def_t; typedef osal_semaphore_def_t* osal_semaphore_t; -TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) { semdef->count = 0; return semdef; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) { (void) in_isr; sem_hdl->count++; return true; } // TODO blocking for now -TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) { (void) msec; - while (sem_hdl->count == 0) { } + while (sem_hdl->count == 0) {} sem_hdl->count--; return true; } -TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) -{ +TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) { sem_hdl->count = 0; } @@ -90,19 +85,16 @@ typedef osal_semaphore_t osal_mutex_t; // Note: multiple cores MCUs usually do provide IPC API for mutex // or we can use std atomic function -TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) { mdef->count = 1; return mdef; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) { return osal_semaphore_wait(mutex_hdl, msec); } -TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) { return osal_semaphore_post(mutex_hdl, false); } @@ -119,11 +111,10 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd //--------------------------------------------------------------------+ #include "common/tusb_fifo.h" -typedef struct -{ - void (*interrupt_set)(bool); +typedef struct { + void (* interrupt_set)(bool); tu_fifo_t ff; -}osal_queue_def_t; +} osal_queue_def_t; typedef osal_queue_def_t* osal_queue_t; @@ -136,27 +127,23 @@ typedef osal_queue_def_t* osal_queue_t; } // lock queue by disable USB interrupt -TU_ATTR_ALWAYS_INLINE static inline void _osal_q_lock(osal_queue_t qhdl) -{ +TU_ATTR_ALWAYS_INLINE static inline void _osal_q_lock(osal_queue_t qhdl) { // disable dcd/hcd interrupt qhdl->interrupt_set(false); } // unlock queue -TU_ATTR_ALWAYS_INLINE static inline void _osal_q_unlock(osal_queue_t qhdl) -{ +TU_ATTR_ALWAYS_INLINE static inline void _osal_q_unlock(osal_queue_t qhdl) { // enable dcd/hcd interrupt qhdl->interrupt_set(true); } -TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) { tu_fifo_clear(&qdef->ff); return (osal_queue_t) qdef; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) { (void) msec; // not used, always behave as msec = 0 _osal_q_lock(qhdl); @@ -166,8 +153,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v return success; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const* data, bool in_isr) { if (!in_isr) { _osal_q_lock(qhdl); } @@ -179,19 +165,17 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void } TU_ASSERT(success); - return success; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) { // Skip queue lock/unlock since this function is primarily called // with interrupt disabled before going into low power mode return tu_fifo_empty(&qhdl->ff); } #ifdef __cplusplus - } +} #endif -#endif /* _TUSB_OSAL_NONE_H_ */ +#endif diff --git a/tools/cmake/toolchain/arm_gcc.cmake b/tools/cmake/toolchain/arm_gcc.cmake index cefa9d2ce..7680d75ab 100644 --- a/tools/cmake/toolchain/arm_gcc.cmake +++ b/tools/cmake/toolchain/arm_gcc.cmake @@ -29,7 +29,7 @@ list(APPEND TOOLCHAIN_COMMON_FLAGS -fno-strict-aliasing ) -set(TOOLCHAIN_EXE_LINKER_FLAGS +list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS -Wl,--print-memory-usage -Wl,--gc-sections -Wl,--cref -- cgit v1.3.1 From 6e5c7f43906bac8ab47642e56c153297b83f3679 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 24 Nov 2023 16:08:06 +0700 Subject: rename to CFG_TUD_BTH_HISTORICAL_COMPATIBLE, move CFG_TUD_BTH_ISO_ALT_COUNT to tusb_option.h and mandatory for BTH driver --- src/class/bth/bth_device.c | 4 +++- src/class/bth/bth_device.h | 12 ++++++------ src/device/usbd.h | 4 ---- src/tusb_option.h | 13 +++++++++---- 4 files changed, 18 insertions(+), 15 deletions(-) (limited to 'src') diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c index be36e8c11..f145e2ead 100755 --- a/src/class/bth/bth_device.c +++ b/src/class/bth/bth_device.c @@ -204,7 +204,9 @@ bool btd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t c request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE) { // HCI command packet addressing for single function Primary Controllers - TU_VERIFY((CFG_TUD_BTH_HISTORICAL_COMPAT && request->bRequest == 0xe0) || (request->bRequest == 0 && request->wValue == 0 && request->wIndex == 0)); + // also compatible with historical mode if enabled + TU_VERIFY((request->bRequest == 0 && request->wValue == 0 && request->wIndex == 0) || + (CFG_TUD_BTH_HISTORICAL_COMPATIBLE && request->bRequest == 0xe0)); } else if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE) { diff --git a/src/class/bth/bth_device.h b/src/class/bth/bth_device.h index c23e74bfb..e782c532b 100755 --- a/src/class/bth/bth_device.h +++ b/src/class/bth/bth_device.h @@ -36,15 +36,15 @@ #ifndef CFG_TUD_BTH_EVENT_EPSIZE #define CFG_TUD_BTH_EVENT_EPSIZE 16 #endif + #ifndef CFG_TUD_BTH_DATA_EPSIZE #define CFG_TUD_BTH_DATA_EPSIZE 64 #endif -#ifndef CFG_TUD_BTH_HISTORICAL_COMPAT -#define CFG_TUD_BTH_HISTORICAL_COMPAT 0 -#endif -#ifndef CFG_TUD_BTH_ISO_ALT_COUNT -// See Bluetooth Core v5.3, Vol. 4, Part B, Section 2.1 -#error You must tell the driver the number of ISO endpoints to use + +// Allow BTH class to work in historically compatibility mode where the bRequest is always 0xe0. +// See Bluetooth Core v5.3, Vol. 4, Part B, Section 2.2 +#ifndef CFG_TUD_BTH_HISTORICAL_COMPATIBLE +#define CFG_TUD_BTH_HISTORICAL_COMPATIBLE 0 #endif typedef struct TU_ATTR_PACKED diff --git a/src/device/usbd.h b/src/device/usbd.h index 93a2033c4..e14e3d6de 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -771,10 +771,6 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb #define TUD_BT_PROTOCOL_PRIMARY_CONTROLLER 0x01 #define TUD_BT_PROTOCOL_AMP_CONTROLLER 0x02 -#ifndef CFG_TUD_BTH_ISO_ALT_COUNT -#define CFG_TUD_BTH_ISO_ALT_COUNT 0 -#endif - // Length of template descriptor: 38 bytes + number of ISO alternatives * 23 #define TUD_BTH_DESC_LEN (8 + 9 + 7 + 7 + 7 + (CFG_TUD_BTH_ISO_ALT_COUNT) * (9 + 7 + 7)) diff --git a/src/tusb_option.h b/src/tusb_option.h index b8509a069..7920fbf35 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -342,6 +342,15 @@ #define CFG_TUD_INTERFACE_MAX 16 #endif +//------------- Device Class Driver -------------// +#ifndef CFG_TUD_BTH + #define CFG_TUD_BTH 0 +#endif + +#if CFG_TUD_BTH && !defined(CFG_TUD_BTH_ISO_ALT_COUNT) +#error CFG_TUD_BTH_ISO_ALT_COUNT must be defined to tell Bluetooth driver the number of ISO endpoints to use +#endif + #ifndef CFG_TUD_CDC #define CFG_TUD_CDC 0 #endif @@ -382,10 +391,6 @@ #define CFG_TUD_DFU 0 #endif -#ifndef CFG_TUD_BTH - #define CFG_TUD_BTH 0 -#endif - #ifndef CFG_TUD_ECM_RNDIS #ifdef CFG_TUD_NET #warning "CFG_TUD_NET is renamed to CFG_TUD_ECM_RNDIS" -- cgit v1.3.1 From 188fbd8ed9b5e0f5cc3ddb5e89f7afd421fc7c06 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 24 Nov 2023 18:21:24 +0700 Subject: add optional event hook callback tud_event_hook_cb() and tuh_event_hook_cb() --- src/device/usbd.c | 83 +++++++++++++++++++++++-------------------------------- src/device/usbd.h | 3 ++ src/host/usbh.c | 18 ++++++------ src/host/usbh.h | 5 +++- src/tusb_option.h | 12 -------- 5 files changed, 52 insertions(+), 69 deletions(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index 2b6d07a96..59466b42e 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -242,22 +242,17 @@ tu_static uint8_t _app_driver_count = 0; // virtually joins built-in and application drivers together. // Application is positioned first to allow overwriting built-in ones. -static inline usbd_class_driver_t const * get_driver(uint8_t drvid) -{ +TU_ATTR_ALWAYS_INLINE static inline usbd_class_driver_t const * get_driver(uint8_t drvid) { usbd_class_driver_t const * driver = NULL; - if ( drvid < _app_driver_count ) { // Application drivers driver = &_app_driver[drvid]; } else if ( drvid < TOTAL_DRIVER_COUNT && BUILTIN_DRIVER_COUNT > 0 ){ driver = &_usbd_driver[drvid - _app_driver_count]; } - return driver; } - - //--------------------------------------------------------------------+ // DCD Event //--------------------------------------------------------------------+ @@ -278,6 +273,11 @@ tu_static osal_queue_t _usbd_q; #define _usbd_mutex NULL #endif +TU_ATTR_ALWAYS_INLINE static inline bool queue_event(dcd_event_t const * event, bool in_isr) { + bool ret = osal_queue_send(_usbd_q, event, in_isr); + if (tud_event_hook_cb) tud_event_hook_cb(event->rhport, event->event_id, in_isr); + return ret; +} //--------------------------------------------------------------------+ // Prototypes @@ -374,8 +374,7 @@ bool tud_connect(void) //--------------------------------------------------------------------+ // USBD Task //--------------------------------------------------------------------+ -bool tud_inited(void) -{ +bool tud_inited(void) { return _usbd_rhport != RHPORT_INVALID; } @@ -1077,73 +1076,64 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const //--------------------------------------------------------------------+ // DCD Event Handler //--------------------------------------------------------------------+ -TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr) -{ +TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const* event, bool in_isr) { bool send = false; - switch (event->event_id) - { + switch (event->event_id) { case DCD_EVENT_UNPLUGGED: - _usbd_dev.connected = 0; - _usbd_dev.addressed = 0; - _usbd_dev.cfg_num = 0; - _usbd_dev.suspended = 0; + _usbd_dev.connected = 0; + _usbd_dev.addressed = 0; + _usbd_dev.cfg_num = 0; + _usbd_dev.suspended = 0; send = true; - break; + break; case DCD_EVENT_SUSPEND: // NOTE: When plugging/unplugging device, the D+/D- state are unstable and // can accidentally meet the SUSPEND condition ( Bus Idle for 3ms ). // In addition, some MCUs such as SAMD or boards that haven no VBUS detection cannot distinguish // suspended vs disconnected. We will skip handling SUSPEND/RESUME event if not currently connected - if ( _usbd_dev.connected ) - { + if (_usbd_dev.connected) { _usbd_dev.suspended = 1; send = true; } - break; + break; case DCD_EVENT_RESUME: // skip event if not connected (especially required for SAMD) - if ( _usbd_dev.connected ) - { + if (_usbd_dev.connected) { _usbd_dev.suspended = 0; send = true; } - break; + break; case DCD_EVENT_SOF: - // SOF driver handler in ISR context - for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) - { - usbd_class_driver_t const * driver = get_driver(i); - if (driver && driver->sof) - { - driver->sof(event->rhport, event->sof.frame_count); - } - } - // Some MCUs after running dcd_remote_wakeup() does not have way to detect the end of remote wakeup // which last 1-15 ms. DCD can use SOF as a clear indicator that bus is back to operational - if ( _usbd_dev.suspended ) - { + if (_usbd_dev.suspended) { _usbd_dev.suspended = 0; - dcd_event_t const event_resume = { .rhport = event->rhport, .event_id = DCD_EVENT_RESUME }; - osal_queue_send(_usbd_q, &event_resume, in_isr); - CFG_TUD_EVENT_HOOK(&event_resume, in_isr); + dcd_event_t const event_resume = {.rhport = event->rhport, .event_id = DCD_EVENT_RESUME}; + queue_event(&event_resume, in_isr); + } + + // SOF driver handler in ISR context + for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) { + usbd_class_driver_t const* driver = get_driver(i); + if (driver && driver->sof) { + driver->sof(event->rhport, event->sof.frame_count); + } } // skip osal queue for SOF in usbd task - break; + break; default: send = true; - break; + break; } if (send) { - osal_queue_send(_usbd_q, event, in_isr); - CFG_TUD_EVENT_HOOK(event, in_isr); + queue_event(event, in_isr); } } @@ -1187,18 +1177,15 @@ bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count } // Helper to defer an isr function -void usbd_defer_func(osal_task_func_t func, void* param, bool in_isr) -{ - dcd_event_t event = - { +void usbd_defer_func(osal_task_func_t func, void* param, bool in_isr) { + dcd_event_t event = { .rhport = 0, .event_id = USBD_EVENT_FUNC_CALL, }; - event.func_call.func = func; event.func_call.param = param; - dcd_event_handler(&event, in_isr); + queue_event(&event, in_isr); } //--------------------------------------------------------------------+ diff --git a/src/device/usbd.h b/src/device/usbd.h index 93a2033c4..1e2f31b06 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -146,6 +146,9 @@ TU_ATTR_WEAK void tud_suspend_cb(bool remote_wakeup_en); // Invoked when usb bus is resumed TU_ATTR_WEAK void tud_resume_cb(void); +// Invoked when there is a new usb event, which need to be processed by tud_task()/tud_task_ext() +TU_ATTR_WEAK void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr); + // Invoked when received control request with VENDOR TYPE TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request); diff --git a/src/host/usbh.c b/src/host/usbh.c index 2fdc8216d..bbda99ea2 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -247,9 +247,7 @@ CFG_TUH_MEM_SECTION struct //------------- Helper Function -------------// -TU_ATTR_ALWAYS_INLINE -static inline usbh_device_t* get_device(uint8_t dev_addr) -{ +TU_ATTR_ALWAYS_INLINE static inline usbh_device_t* get_device(uint8_t dev_addr) { TU_VERIFY(dev_addr > 0 && dev_addr <= TOTAL_DEVICES, NULL); return &_usbh_devices[dev_addr-1]; } @@ -268,6 +266,12 @@ TU_ATTR_WEAK void osal_task_delay(uint32_t msec) { } #endif +TU_ATTR_ALWAYS_INLINE static inline bool queue_event(hcd_event_t const * event, bool in_isr) { + bool ret = osal_queue_send(_usbh_q, event, in_isr); + if (tuh_event_hook_cb) tuh_event_hook_cb(event->rhport, event->event_id, in_isr); + return ret; +} + //--------------------------------------------------------------------+ // Device API //--------------------------------------------------------------------+ @@ -433,7 +437,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport); bool is_empty = osal_queue_empty(_usbh_q); - osal_queue_send(_usbh_q, &event, in_isr); + queue_event(&event, in_isr); if (is_empty) { // Exit if this is the only event in the queue, otherwise we may loop forever @@ -779,8 +783,7 @@ void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr) { event.func_call.func = func; event.func_call.param = param; - osal_queue_send(_usbh_q, &event, in_isr); - CFG_TUH_EVENT_HOOK(event, in_isr); + queue_event(&event, in_isr); } //--------------------------------------------------------------------+ @@ -936,8 +939,7 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) default: break; } - osal_queue_send(_usbh_q, event, in_isr); - CFG_TUH_EVENT_HOOK(event, in_isr); + queue_event(event, in_isr); } //--------------------------------------------------------------------+ diff --git a/src/host/usbh.h b/src/host/usbh.h index 770d70dfe..7591c7672 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -90,9 +90,12 @@ TU_ATTR_WEAK void tuh_mount_cb (uint8_t daddr); // Invoked when a device failed to mount during enumeration process // TU_ATTR_WEAK void tuh_mount_failed_cb (uint8_t daddr); -/// Invoked when a device is unmounted (detached) +// Invoked when a device is unmounted (detached) TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr); +// Invoked when there is a new usb event, which need to be processed by tuh_task()/tuh_task_ext() +TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr); + //--------------------------------------------------------------------+ // APPLICATION API //--------------------------------------------------------------------+ diff --git a/src/tusb_option.h b/src/tusb_option.h index cf774a41c..b8509a069 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -486,18 +486,6 @@ #define tuc_int_handler(_p) #endif -//--------------------------------------------------------------------+ -// Optional event hook functions for platform integration (defaults) -//--------------------------------------------------------------------+ - -#ifndef CFG_TUD_EVENT_HOOK -#define CFG_TUD_EVENT_HOOK(EVENT, IN_ISR) -#endif - -#ifndef CFG_TUH_EVENT_HOOK -#define CFG_TUH_EVENT_HOOK(EVENT, IN_ISR) -#endif - //------------------------------------------------------------------ // Configuration Validation //------------------------------------------------------------------ -- cgit v1.3.1 From 2fed722b0004e64667df526043f3bfcb131d3ee3 Mon Sep 17 00:00:00 2001 From: Xudong Zheng <7pkvm5aw@slicealias.com> Date: Sun, 27 Aug 2023 15:21:15 -0400 Subject: add tuh_hid_set_default_protocol() to set default USB host HID protocol --- src/class/hid/hid_host.c | 11 +++++++++-- src/class/hid/hid_host.h | 5 +++++ 2 files changed, 14 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index a3551c85a..80312676a 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -211,6 +211,13 @@ static void set_protocol_complete(tuh_xfer_t* xfer) } } +CFG_TUH_MEM_SECTION +tu_static uint8_t _hidh_default_protocol = HID_PROTOCOL_BOOT; + +void tuh_hid_set_default_protocol(uint8_t protocol) { + _hidh_default_protocol = protocol; +} + static bool _hidh_set_protocol(uint8_t daddr, uint8_t itf_num, uint8_t protocol, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_DRV("HID Set Protocol = %d\r\n", protocol); @@ -521,7 +528,7 @@ bool hidh_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *desc_ p_hid->report_desc_len = tu_unaligned_read16(&desc_hid->wReportLength); // Per HID Specs: default is Report protocol, though we will force Boot protocol when set_config - p_hid->protocol_mode = HID_PROTOCOL_BOOT; + p_hid->protocol_mode = _hidh_default_protocol; if ( HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass ) { p_hid->itf_protocol = desc_itf->bInterfaceProtocol; @@ -591,7 +598,7 @@ static void process_set_config(tuh_xfer_t* xfer) break; case CONFIG_SET_PROTOCOL: - _hidh_set_protocol(daddr, p_hid->itf_num, HID_PROTOCOL_BOOT, process_set_config, CONFIG_GET_REPORT_DESC); + _hidh_set_protocol(daddr, p_hid->itf_num, _hidh_default_protocol, process_set_config, CONFIG_GET_REPORT_DESC); break; case CONFIG_GET_REPORT_DESC: diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h index 08ad421d2..3c59e301d 100644 --- a/src/class/hid/hid_host.h +++ b/src/class/hid/hid_host.h @@ -97,6 +97,11 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr, // Application can use set_protocol() to switch back to Report protocol. uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t idx); +// Device by default is initialized in Boot protocol for simplicity. Application +// can use this to modify the default protocol before calling tuh_init(), or use +// set_protocol() to change the protocol after initialization. +void tuh_hid_set_default_protocol(uint8_t protocol); + // Set protocol to HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1) // This function is only supported by Boot interface (tuh_n_hid_interface_protocol() != NONE) bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t idx, uint8_t protocol); -- cgit v1.3.1 From f469250fa34929b1890500b1d7abfb2a7bb7dcc5 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 24 Nov 2023 18:35:00 +0700 Subject: minor update --- src/class/hid/hid_host.c | 5 ++--- src/class/hid/hid_host.h | 5 ++--- 2 files changed, 4 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 80312676a..db52b503f 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -67,6 +67,8 @@ typedef struct CFG_TUH_MEM_SECTION tu_static hidh_interface_t _hidh_itf[CFG_TUH_HID]; +tu_static uint8_t _hidh_default_protocol = HID_PROTOCOL_BOOT; + //--------------------------------------------------------------------+ // Helper //--------------------------------------------------------------------+ @@ -211,9 +213,6 @@ static void set_protocol_complete(tuh_xfer_t* xfer) } } -CFG_TUH_MEM_SECTION -tu_static uint8_t _hidh_default_protocol = HID_PROTOCOL_BOOT; - void tuh_hid_set_default_protocol(uint8_t protocol) { _hidh_default_protocol = protocol; } diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h index 3c59e301d..238b7c627 100644 --- a/src/class/hid/hid_host.h +++ b/src/class/hid/hid_host.h @@ -97,9 +97,8 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr, // Application can use set_protocol() to switch back to Report protocol. uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t idx); -// Device by default is initialized in Boot protocol for simplicity. Application -// can use this to modify the default protocol before calling tuh_init(), or use -// set_protocol() to change the protocol after initialization. +// Device by default is enumerated in Boot protocol for simplicity. Application +// can use this to modify the default protocol for next enumeration. void tuh_hid_set_default_protocol(uint8_t protocol); // Set protocol to HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1) -- cgit v1.3.1 From 426f791e7af6c8d53c828ecab37848ac833965ea Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 24 Nov 2023 11:38:20 +0700 Subject: minor doc --- docs/reference/supported.rst | 2 +- src/device/dcd.h | 30 +++++++++++------------------- 2 files changed, 12 insertions(+), 20 deletions(-) (limited to 'src') diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index 983640dd3..c9fc4a882 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -41,7 +41,7 @@ Supported MCUs | | | dsPIC33 | ✔ | | | pic | ci_fs variant| | | +-----------------+--------+------+-----------+-------------------+--------------+ | | | 32mz | ✔ | | | pic32mz | musb variant | -+--------------+-----------------------+--------+------+-----------+-------------------+--------------+ ++--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+ | Mind Montion | mm32 | ✔ | | ✖ | mm32f327x_otg | ci_fs variant| +--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+ | NordicSemi | nRF52833, nRF52840 | ✔ | ✖ | ✖ | nrf5x | | diff --git a/src/device/dcd.h b/src/device/dcd.h index 18a708347..8c6813cf7 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -47,8 +47,7 @@ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ -typedef enum -{ +typedef enum { DCD_EVENT_INVALID = 0, DCD_EVENT_BUS_RESET, DCD_EVENT_UNPLUGGED, @@ -65,13 +64,11 @@ typedef enum DCD_EVENT_COUNT } dcd_eventid_t; -typedef struct TU_ATTR_ALIGNED(4) -{ +typedef struct TU_ATTR_ALIGNED(4) { uint8_t rhport; uint8_t event_id; - union - { + union { // BUS RESET struct { tusb_speed_t speed; @@ -123,7 +120,7 @@ void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_W //--------------------------------------------------------------------+ // Initialize controller to device mode -void dcd_init (uint8_t rhport); +void dcd_init(uint8_t rhport); // Interrupt Handler void dcd_int_handler(uint8_t rhport); @@ -184,11 +181,11 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr); void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr); // Allocate packet buffer used by ISO endpoints -// Some MCU need manual packet buffer allocation, we allocation largest size to avoid clustering +// Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering TU_ATTR_WEAK bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size); // Configure and enable an ISO endpoint according to descriptor -TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc); +TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc); //--------------------------------------------------------------------+ // Event API (implemented by stack) @@ -198,23 +195,20 @@ TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t co extern void dcd_event_handler(dcd_event_t const * event, bool in_isr); // helper to send bus signal event -TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr) -{ +TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr) { dcd_event_t event = { .rhport = rhport, .event_id = eid }; dcd_event_handler(&event, in_isr); } // helper to send bus reset event -TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr) -{ +TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr) { dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_BUS_RESET }; event.bus_reset.speed = speed; dcd_event_handler(&event, in_isr); } // helper to send setup received -TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr) -{ +TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr) { dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SETUP_RECEIVED }; memcpy(&event.setup_received, setup, sizeof(tusb_control_request_t)); @@ -222,8 +216,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport } // helper to send transfer complete event -TU_ATTR_ALWAYS_INLINE static inline void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr) -{ +TU_ATTR_ALWAYS_INLINE static inline void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr) { dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_XFER_COMPLETE }; event.xfer_complete.ep_addr = ep_addr; @@ -233,8 +226,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dcd_event_xfer_complete (uint8_t rhport dcd_event_handler(&event, in_isr); } -static inline void dcd_event_sof(uint8_t rhport, uint32_t frame_count, bool in_isr) -{ +TU_ATTR_ALWAYS_INLINE static inline void dcd_event_sof(uint8_t rhport, uint32_t frame_count, bool in_isr) { dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SOF }; event.sof.frame_count = frame_count; dcd_event_handler(&event, in_isr); -- cgit v1.3.1 From 031be18e26933850d63c91659832b9987efecf24 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 24 Nov 2023 16:36:12 +0700 Subject: update release version --- library.json | 2 +- repository.yml | 3 ++- src/tusb_option.h | 2 +- tools/make_release.py | 21 +++++++++++++++------ 4 files changed, 19 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/library.json b/library.json index d637b528d..3cdd5990f 100644 --- a/library.json +++ b/library.json @@ -1,6 +1,6 @@ { "name": "TinyUSB", - "version": "0.15.0", + "version": "0.16.0", "description": "TinyUSB is an open-source cross-platform USB Host/Device stack for embedded system, designed to be memory-safe with no dynamic allocation and thread-safe with all interrupt events are deferred then handled in the non-ISR task function.", "keywords": "usb, host, device", "repository": diff --git a/repository.yml b/repository.yml index 702753a90..28666d2d4 100644 --- a/repository.yml +++ b/repository.yml @@ -13,5 +13,6 @@ repo.versions: "0.13.0": "0.13.0" "0.14.0": "0.14.0" "0.15.0": "0.15.0" - "0-latest": "0.15.0" + "0.16.0": "0.16.0" + "0-latest": "0.16.0" "0-dev": "0.0.0" diff --git a/src/tusb_option.h b/src/tusb_option.h index 7920fbf35..6758933d8 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -30,7 +30,7 @@ #include "common/tusb_compiler.h" #define TUSB_VERSION_MAJOR 0 -#define TUSB_VERSION_MINOR 15 +#define TUSB_VERSION_MINOR 16 #define TUSB_VERSION_REVISION 0 #define TUSB_VERSION_STRING TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION) diff --git a/tools/make_release.py b/tools/make_release.py index 7481e8864..256ca8f21 100644 --- a/tools/make_release.py +++ b/tools/make_release.py @@ -1,6 +1,6 @@ import re -version = '0.15.0' +version = '0.16.0' print('version {}'.format(version)) ver_id = version.split('.') @@ -9,13 +9,11 @@ ver_id = version.split('.') # src/tusb_option.h ################### f_option_h = 'src/tusb_option.h' - with open(f_option_h) as f: fdata = f.read() - -fdata = re.sub(r'(#define TUSB_VERSION_MAJOR *) \d+', r"\1 {}".format(ver_id[0]), fdata) -fdata = re.sub(r'(#define TUSB_VERSION_MINOR *) \d+', r"\1 {}".format(ver_id[1]), fdata) -fdata = re.sub(r'(#define TUSB_VERSION_REVISION *) \d+', r"\1 {}".format(ver_id[2]), fdata) + fdata = re.sub(r'(#define TUSB_VERSION_MAJOR *) \d+', r"\1 {}".format(ver_id[0]), fdata) + fdata = re.sub(r'(#define TUSB_VERSION_MINOR *) \d+', r"\1 {}".format(ver_id[1]), fdata) + fdata = re.sub(r'(#define TUSB_VERSION_REVISION *) \d+', r"\1 {}".format(ver_id[2]), fdata) # Write the file out again with open(f_option_h, 'w') as f: @@ -33,6 +31,17 @@ if fdata.find(version) < 0: with open(f_repository_yml, 'w') as f: f.write(fdata) +################### +# library.json +################### +f_library_json = 'library.json' +with open(f_library_json) as f: + fdata = f.read() + fdata = re.sub(r'( {4}"version":) "\d+\.\d+\.\d+"', rf'\1 "{version}"', fdata) + +with open(f_library_json, 'w') as f: + f.write(fdata) + ################### # docs/info/changelog.rst ################### -- cgit v1.3.1 From 7e1fe2ff83e1089a1e75e4fdc03af4b0aa6048ea Mon Sep 17 00:00:00 2001 From: IngHK Date: Fri, 24 Nov 2023 22:02:58 +0100 Subject: made log line end consistent \r\n --- examples/device/cdc_uac2/src/main.c | 2 +- src/portable/analog/max3421/hcd_max3421.c | 8 ++++---- src/portable/ehci/ehci.c | 4 ++-- src/portable/mentor/musb/dcd_musb.c | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/examples/device/cdc_uac2/src/main.c b/examples/device/cdc_uac2/src/main.c index 7afa96c1a..25b2cd9a5 100644 --- a/examples/device/cdc_uac2/src/main.c +++ b/examples/device/cdc_uac2/src/main.c @@ -60,7 +60,7 @@ int main(void) led_blinking_task(); #if (CFG_TUSB_MCU == OPT_MCU_RP2040) - // printf("Hello, world!\n"); + // printf("Hello, world!\r\n"); #endif } diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 65f87f7c6..d7ce5a92f 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -382,7 +382,7 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) { for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) { max3421_ep_t* ep = &_hcd_data.ep[i]; if (ep->xfer_pending && ep->packet_size) { -// TU_LOG3("next pending i = %u\n", i); +// TU_LOG3("next pending i = %u\r\n", i); return ep; } } @@ -391,7 +391,7 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) { for (size_t i = 0; i <= idx; i++) { max3421_ep_t* ep = &_hcd_data.ep[i]; if (ep->xfer_pending && ep->packet_size) { -// TU_LOG3("next pending i = %u\n", i); +// TU_LOG3("next pending i = %u\r\n", i); return ep; } } @@ -712,9 +712,9 @@ static void handle_connect_irq(uint8_t rhport, bool in_isr) { // However, since we are always in full speed mode, we can just check J-state if (jk == HRSL_KSTATUS) { new_mode |= MODE_LOWSPEED; - TU_LOG3("Low speed\n"); + TU_LOG3("Low speed\r\n"); }else { - TU_LOG3("Full speed\n"); + TU_LOG3("Full speed\r\n"); } new_mode |= MODE_SOFKAENAB; mode_write(rhport, new_mode, in_isr); diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 572b9826c..e145cbb1b 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -581,7 +581,7 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) { // clear halted bit if not caused by STALL to allow more transfer xfer_result = XFER_RESULT_FAILED; qtd_overlay->halted = false; - TU_LOG3(" QHD xfer err count: %d\n", qtd_overlay->err_count); + TU_LOG3(" QHD xfer err count: %d\r\n", qtd_overlay->err_count); // TU_BREAKPOINT(); // TODO skip unplugged device }else { // no error bits are set, endpoint is halted due to STALL @@ -664,7 +664,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { if (int_status & EHCI_INT_MASK_HC_HALTED) { // something seriously wrong, maybe forget to flush/invalidate cache TU_BREAKPOINT(); - TU_LOG1(" HC halted\n"); + TU_LOG1(" HC halted\r\n"); return; } diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 3c0114e41..a817c5d6e 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -158,9 +158,9 @@ static inline unsigned free_block_size(free_block_t const *blk) #if 0 static inline void print_block_list(free_block_t const *blk, unsigned num) { - TU_LOG1("*************\n"); + TU_LOG1("*************\r\n"); for (unsigned i = 0; i < num; ++i) { - TU_LOG1(" Blk%u %u %u\n", i, blk->beg, blk->end); + TU_LOG1(" Blk%u %u %u\r\n", i, blk->beg, blk->end); ++blk; } } -- cgit v1.3.1 From b8881a3a141530a1d383d8869881e773b8a07d80 Mon Sep 17 00:00:00 2001 From: IngHK Date: Fri, 24 Nov 2023 22:34:28 +0100 Subject: fixed compile errors due to untreated CFG_TUH_LOG_LEVEL --- src/common/tusb_debug.h | 2 +- src/host/usbh.c | 8 ++++---- src/host/usbh_pvt.h | 2 +- src/tusb.c | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h index 99176c02a..bd388d910 100644 --- a/src/common/tusb_debug.h +++ b/src/common/tusb_debug.h @@ -43,7 +43,7 @@ #if CFG_TUSB_DEBUG // Enum to String for debugging purposes -#if CFG_TUSB_DEBUG >= 2 +#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL extern char const* const tu_str_speed[]; extern char const* const tu_str_std_request[]; extern char const* const tu_str_xfer_result[]; diff --git a/src/host/usbh.c b/src/host/usbh.c index d8fff9905..78c8abfbd 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -113,7 +113,7 @@ typedef struct { // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -#if CFG_TUSB_DEBUG >= 2 +#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL #define DRIVER_NAME(_name) .name = _name, #else #define DRIVER_NAME(_name) @@ -1233,7 +1233,7 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu TU_LOG_USBH("Device unplugged address = %u\r\n", daddr); if (is_hub_addr(daddr)) { - TU_LOG(CFG_TUH_LOG_LEVEL, " is a HUB device %u\r\n", daddr); + TU_LOG_USBH(" is a HUB device %u\r\n", daddr); // Submit removed event If the device itself is a hub (un-rolled recursive) // TODO a better to unroll recursrive is using array of removing_hubs and mark it here @@ -1708,7 +1708,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur if ( drv_id == TOTAL_DRIVER_COUNT - 1 ) { - TU_LOG(CFG_TUH_LOG_LEVEL, "[%u:%u] Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n", + TU_LOG_USBH("[%u:%u] Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n", dev->rhport, dev_addr, desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol); } } @@ -1741,7 +1741,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) { enum_full_complete(); if (is_hub_addr(dev_addr)) { - TU_LOG(CFG_TUH_LOG_LEVEL, "HUB address = %u is mounted\r\n", dev_addr); + TU_LOG_USBH("HUB address = %u is mounted\r\n", dev_addr); }else { // Invoke callback if available if (tuh_mount_cb) tuh_mount_cb(dev_addr); diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h index 2b61a77db..3363ab9eb 100644 --- a/src/host/usbh_pvt.h +++ b/src/host/usbh_pvt.h @@ -51,7 +51,7 @@ enum { //--------------------------------------------------------------------+ typedef struct { - #if CFG_TUSB_DEBUG >= 2 + #if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL char const* name; #endif diff --git a/src/tusb.c b/src/tusb.c index 7b0a669a0..e0c1066d4 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -419,7 +419,7 @@ uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize #if CFG_TUSB_DEBUG #include -#if CFG_TUSB_DEBUG >= 2 +#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL char const* const tu_str_speed[] = { "Full", "Low", "High" }; char const* const tu_str_std_request[] = -- cgit v1.3.1 From c4e04d3db4f8f33e906afbae4739d64e53fa9987 Mon Sep 17 00:00:00 2001 From: Oliver Larsson Date: Sun, 29 Oct 2023 16:53:10 +0100 Subject: Add configuration option CFG_TUH_CDC_CP210X_PID_LIST to tusb_option.h --- src/class/cdc/cdc_host.c | 2 +- src/class/cdc/serial/cp210x.h | 2 -- src/tusb_option.h | 6 ++++++ 3 files changed, 7 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 53e15710e..a6af9b84d 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -109,7 +109,7 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu #if CFG_TUH_CDC_CP210X #include "serial/cp210x.h" -static uint16_t const cp210x_pids[] = { TU_CP210X_PID_LIST }; +static uint16_t const cp210x_pids[] = { CFG_TUH_CDC_CP210X_PID_LIST }; enum { CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0]) }; diff --git a/src/class/cdc/serial/cp210x.h b/src/class/cdc/serial/cp210x.h index b01417092..2c749f522 100644 --- a/src/class/cdc/serial/cp210x.h +++ b/src/class/cdc/serial/cp210x.h @@ -29,8 +29,6 @@ // https://www.silabs.com/documents/public/application-notes/AN571.pdf #define TU_CP210X_VID 0x10C4 -#define TU_CP210X_PID_LIST \ - 0xEA60, 0xEA70 /* Config request codes */ #define CP210X_IFC_ENABLE 0x00 diff --git a/src/tusb_option.h b/src/tusb_option.h index a41f5a07e..3d290ae66 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -441,6 +441,12 @@ #define CFG_TUH_CDC_CP210X 0 #endif +#ifndef CFG_TUH_CDC_CP210X_PID_LIST + // List of product IDs that can use the CP210X CDC driver + #define CFG_TUH_CDC_CP210X_PID_LIST \ + 0xEA60, 0xEA70 +#endif + #ifndef CFG_TUH_HID #define CFG_TUH_HID 0 #endif -- cgit v1.3.1 From efde252ed0a577536f409db980f46db844a23b2b Mon Sep 17 00:00:00 2001 From: IngHK Date: Fri, 8 Dec 2023 16:59:52 +0100 Subject: improved CFG_TUSB_DEBUG handling due to compile errors --- src/common/tusb_debug.h | 2 +- src/tusb.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h index bd388d910..0f4dc93f3 100644 --- a/src/common/tusb_debug.h +++ b/src/common/tusb_debug.h @@ -43,7 +43,7 @@ #if CFG_TUSB_DEBUG // Enum to String for debugging purposes -#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL +#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL || CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL extern char const* const tu_str_speed[]; extern char const* const tu_str_std_request[]; extern char const* const tu_str_xfer_result[]; diff --git a/src/tusb.c b/src/tusb.c index e0c1066d4..7943ea5ef 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -419,7 +419,7 @@ uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize #if CFG_TUSB_DEBUG #include -#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL +#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL || CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL char const* const tu_str_speed[] = { "Full", "Low", "High" }; char const* const tu_str_std_request[] = -- cgit v1.3.1 From ac418f4d25400c12864b242f94215664dc5d9229 Mon Sep 17 00:00:00 2001 From: Angel Molina Date: Sat, 9 Dec 2023 23:13:53 +0100 Subject: Fix strict-overflow warning when compiling with gcc >= 12 --- src/class/audio/audio_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 9af999992..731c39b54 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -1565,7 +1565,7 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin { uint8_t const *p_desc = _audiod_fct[i].p_desc; uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN; - while (p_desc < p_desc_end) + while (p_desc_end - p_desc > 0) { if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) { -- cgit v1.3.1 From 506617d4b39ba9118a24477a4be6db9733e2e2f1 Mon Sep 17 00:00:00 2001 From: Ángel Molina Núñez Date: Sun, 10 Dec 2023 17:04:46 +0100 Subject: Add comment to explain why the condition changes --- src/class/audio/audio_device.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 731c39b54..d438d0715 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -1565,6 +1565,7 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin { uint8_t const *p_desc = _audiod_fct[i].p_desc; uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN; + // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning while (p_desc_end - p_desc > 0) { if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) -- cgit v1.3.1 From 9a7e23379ccd4fe572af824c09d6113401412522 Mon Sep 17 00:00:00 2001 From: Oliver Larsson Date: Mon, 11 Dec 2023 09:36:10 +0100 Subject: Add configuration option CFG_TUH_CDC_FTDI_PID_LIST to tusb_option.h --- src/class/cdc/cdc_host.c | 2 +- src/class/cdc/serial/ftdi_sio.h | 5 +---- src/tusb_option.h | 6 ++++++ 3 files changed, 8 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index a6af9b84d..a6dfb45ae 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -90,7 +90,7 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfe #if CFG_TUH_CDC_FTDI #include "serial/ftdi_sio.h" -static uint16_t const ftdi_pids[] = { TU_FTDI_PID_LIST }; +static uint16_t const ftdi_pids[] = { CFG_TUH_CDC_FTDI_PID_LIST }; enum { FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0]) }; diff --git a/src/class/cdc/serial/ftdi_sio.h b/src/class/cdc/serial/ftdi_sio.h index 6916e4031..0825f0719 100644 --- a/src/class/cdc/serial/ftdi_sio.h +++ b/src/class/cdc/serial/ftdi_sio.h @@ -25,11 +25,8 @@ #ifndef TUSB_FTDI_SIO_H #define TUSB_FTDI_SIO_H -// VID/PID for matching FTDI devices +// VID for matching FTDI devices #define TU_FTDI_VID 0x0403 -#define TU_FTDI_PID_LIST \ - 0x6001, 0x6006, 0x6010, 0x6011, 0x6014, 0x6015, 0x8372, 0xFBFA, \ - 0xcd18 // Commands #define FTDI_SIO_RESET 0 /* Reset the port */ diff --git a/src/tusb_option.h b/src/tusb_option.h index 900784388..7597392d6 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -442,6 +442,12 @@ #define CFG_TUH_CDC_FTDI 0 #endif +#ifndef CFG_TUH_CDC_FTDI_PID_LIST + // List of product IDs that can use the FTDI CDC driver + #define CFG_TUH_CDC_FTDI_PID_LIST \ + 0x6001, 0x6006, 0x6010, 0x6011, 0x6014, 0x6015, 0x8372, 0xFBFA, 0xCD18 +#endif + #ifndef CFG_TUH_CDC_CP210X // CP210X is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_CDC_CP210X 0 -- cgit v1.3.1 From 93c40b6966db53ce70f4bea6b8a72bf2986ac180 Mon Sep 17 00:00:00 2001 From: henneboi Date: Fri, 8 Dec 2023 13:34:42 +0100 Subject: Add Support stm32h5 for stm32h573i based on stm32_fsdev G0 implementation Tested on Windows with IAR and gcc toolchain ( via cubeide) Tested only with audio examples, but sould be ok for other examples Cmake pacthed : but not tested Linux build : not tested Added a temporary workaround in make file to support H5 HAL repo ( ARMCC_VERSION=0) --- hw/bsp/board_mcu.h | 11 +- hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h | 165 ++++++++++ .../boards/stm32h573i-dk/STM32H573I-DK_FLASH.ld | 187 +++++++++++ hw/bsp/stm32h5/boards/stm32h573i-dk/board.cmake | 10 + hw/bsp/stm32h5/boards/stm32h573i-dk/board.h | 125 ++++++++ hw/bsp/stm32h5/boards/stm32h573i-dk/board.mk | 13 + hw/bsp/stm32h5/family.c | 206 ++++++++++++ hw/bsp/stm32h5/family.cmake | 116 +++++++ hw/bsp/stm32h5/family.mk | 57 ++++ hw/bsp/stm32h5/stm32h5xx_hal_conf.h | 355 +++++++++++++++++++++ src/common/tusb_mcu.h | 6 + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 11 +- .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 29 ++ src/tusb_option.h | 1 + tools/get_deps.py | 9 +- 15 files changed, 1295 insertions(+), 6 deletions(-) create mode 100644 hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/stm32h5/boards/stm32h573i-dk/STM32H573I-DK_FLASH.ld create mode 100644 hw/bsp/stm32h5/boards/stm32h573i-dk/board.cmake create mode 100644 hw/bsp/stm32h5/boards/stm32h573i-dk/board.h create mode 100644 hw/bsp/stm32h5/boards/stm32h573i-dk/board.mk create mode 100644 hw/bsp/stm32h5/family.c create mode 100644 hw/bsp/stm32h5/family.cmake create mode 100644 hw/bsp/stm32h5/family.mk create mode 100644 hw/bsp/stm32h5/stm32h5xx_hal_conf.h (limited to 'src') diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index 4ce5c4139..d40f33bbe 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -40,8 +40,8 @@ // Include order follows OPT_MCU_ number #if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX) || \ - TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC18XX) || \ - TU_CHECK_MCU(OPT_MCU_LPC40XX, OPT_MCU_LPC43XX) + TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC18XX) || \ + TU_CHECK_MCU(OPT_MCU_LPC40XX, OPT_MCU_LPC43XX) #include "chip.h" #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX, OPT_MCU_MCXN9) @@ -54,8 +54,8 @@ #include "nrf.h" #elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \ - CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \ - CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21 + CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \ + CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21 #include "sam.h" #elif CFG_TUSB_MCU == OPT_MCU_SAMG @@ -83,6 +83,9 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32G4 #include "stm32g4xx.h" +#elif CFG_TUSB_MCU == OPT_MCU_STM32H5 + #include "stm32h5xx.h" + #elif CFG_TUSB_MCU == OPT_MCU_STM32H7 #include "stm32h7xx.h" diff --git a/hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..52dfa095f --- /dev/null +++ b/hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,165 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "stm32g0xx.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* Define to trap errors during development. */ +// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) +#define configASSERT(_exp) \ + do {\ + if ( !(_exp) ) { \ + volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ + if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \ + taskDISABLE_INTERRUPTS(); \ + __asm("BKPT #0\n"); \ + }\ + }\ + } while(0) +#else +#define configASSERT( x ) +#endif + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS 2 + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<
© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32h5/boards/stm32h573i-dk/board.cmake b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.cmake new file mode 100644 index 000000000..82d4474af --- /dev/null +++ b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.cmake @@ -0,0 +1,10 @@ +set(MCU_VARIANT stm32h573i-dk) +set(JLINK_DEVICE stm32h573i-dk) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32H573I-DK_FLASH.ld) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + STM32H573xx + ) +endfunction() diff --git a/hw/bsp/stm32h5/boards/stm32h573i-dk/board.h b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.h new file mode 100644 index 000000000..01834f151 --- /dev/null +++ b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.h @@ -0,0 +1,125 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * Copyright (c) 2034, HiFiPhile + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_PORT GPIOI +#define LED_PIN GPIO_PIN_9 +#define LED_STATE_ON 0 + +// Button +#define BUTTON_PORT GPIOC +#define BUTTON_PIN GPIO_PIN_13 +#define BUTTON_STATE_ACTIVE 0 + +// UART Enable for STLink VCOM +#define UART_DEV USART1 +#define UART_CLK_EN __USART1_CLK_ENABLE +#define UART_GPIO_PORT GPIOA +#define UART_GPIO_AF GPIO_AF7_USART1 + +#define UART_TX_PIN GPIO_PIN_9 +#define UART_RX_PIN GPIO_PIN_10 + + + + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ +// Clock configure for STM32stm32h573i-dk +static inline void board_clock_init(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + Freq 250MHZ */ + + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 5; + RCC_OscInitStruct.PLL.PLLN = 100; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /** Initializes the CPU, AHB and APB buses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); + + // Configure CRS clock source + __HAL_RCC_CRS_CLK_ENABLE(); + RCC_CRSInitTypeDef RCC_CRSInitStruct = {0}; + RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1; + RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB; + RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING; + RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000); + RCC_CRSInitStruct.ErrorLimitValue = 34; + RCC_CRSInitStruct.HSI48CalibrationValue = 32; + HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct); + + + /* Select HSI48 as USB clock source */ + RCC_PeriphCLKInitTypeDef usb_clk = {0 }; + usb_clk.PeriphClockSelection = RCC_PERIPHCLK_USB; + usb_clk.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + HAL_RCCEx_PeriphCLKConfig(&usb_clk); + + /* Peripheral clock enable */ + __HAL_RCC_USB_CLK_ENABLE(); + + SystemCoreClockUpdate(); + + +} + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32h5/boards/stm32h573i-dk/board.mk b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.mk new file mode 100644 index 000000000..66b299886 --- /dev/null +++ b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.mk @@ -0,0 +1,13 @@ +CFLAGS += \ + -DSTM32H573xx + +# GCC +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h573xx.s +LD_FILE_GCC = $(BOARD_PATH)/STM32H573I-DK_FLASH.ld + +# IAR +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h573xx.s +LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h573xx_flash.icf + +# For flash-jlink target +JLINK_DEVICE = stm32h573i-dk diff --git a/hw/bsp/stm32h5/family.c b/hw/bsp/stm32h5/family.c new file mode 100644 index 000000000..d035b791c --- /dev/null +++ b/hw/bsp/stm32h5/family.c @@ -0,0 +1,206 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * Copyright (c) 2023 HiFiPhile + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "stm32h5xx_hal.h" +#include "bsp/board_api.h" +#include "board.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB_DRD_FS_IRQHandler(void) +{ + tud_int_handler(0); +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ +UART_HandleTypeDef UartHandle; + +void board_init(void) +{ + HAL_Init(); // required for HAL_RCC_Osc TODO check with freeRTOS + board_clock_init(); + + // Enable All GPIOs clocks + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + + //__HAL_RCC_SYSCFG_CLK_ENABLE(); + //__HAL_RCC_PWR_CLK_ENABLE(); + + UART_CLK_EN(); + + #if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); + #elif CFG_TUSB_OS == OPT_OS_FREERTOS + // Explicitly disable systick to prevent its ISR runs before scheduler start + SysTick->CTRL &= ~1U; + + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB_DRD_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + #endif + + GPIO_InitTypeDef GPIO_InitStruct; + + // LED + GPIO_InitStruct.Pin = LED_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct); + + board_led_write(false); + + // Button + GPIO_InitStruct.Pin = BUTTON_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); + + #ifdef UART_DEV + // UART + GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = UART_GPIO_AF; + HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct); + + UartHandle = (UART_HandleTypeDef) + { + .Instance = UART_DEV, + .Init.BaudRate = CFG_BOARD_UART_BAUDRATE, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.OverSampling = UART_OVERSAMPLING_16, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT + }; + HAL_UART_Init(&UartHandle); + #endif + + // USB Pins TODO double check USB clock and pin setup + // Configure USB DM and DP pins. This is optional, and maintained only for user guidance. + GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12); + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_USB_CLK_ENABLE(); + + /* Enable VDDUSB */ + HAL_PWREx_EnableVddUSB(); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON)); + HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state); +} + +uint32_t board_button_read(void) +{ + return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t *stm32_uuid = (volatile uint32_t *) UID_BASE; + uint32_t *id32 = (uint32_t *)(uintptr_t) id; + uint8_t const len = 12; + + id32[0] = stm32_uuid[0]; + id32[1] = stm32_uuid[1]; + id32[2] = stm32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) +{ + #ifdef UART_DEV + HAL_UART_Transmit(&UartHandle, (uint8_t *)(uintptr_t) buf, len, 0xffff); + return len; + #else + (void) buf; + (void) len; + (void) UartHandle; + return 0; + #endif +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) +{ + system_ticks++; + HAL_IncTick(); +} + +uint32_t board_millis(void) +{ + return system_ticks; +} + +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) +{ + +} diff --git a/hw/bsp/stm32h5/family.cmake b/hw/bsp/stm32h5/family.cmake new file mode 100644 index 000000000..8edee1887 --- /dev/null +++ b/hw/bsp/stm32h5/family.cmake @@ -0,0 +1,116 @@ +include_guard() + +if (NOT BOARD) + message(FATAL_ERROR "BOARD not specified") +endif () + +set(ST_FAMILY h5) +set(ST_PREFIX stm32${ST_FAMILY}xx) + +set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver) +set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY}) +set(CMSIS_5 ${TOP}/lib/CMSIS_5) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS STM32H5 CACHE INTERNAL "") + + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (NOT TARGET ${BOARD_TARGET}) + # Startup & Linker script + set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) + set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s) + set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) + + add_library(${BOARD_TARGET} STATIC + ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${ST_CMSIS}/Include + ${ST_HAL_DRIVER}/Inc + ) + target_compile_options(${BOARD_TARGET} PUBLIC + ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + # nanolib + --specs=nosys.specs + --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_STM32H5 ${RTOS}) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + ${TOP}/src/portable/st/typec/typec_stm32.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + + # Link dependencies + target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + + # Flashing + family_flash_stlink(${TARGET}) + #family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/stm32h5/family.mk b/hw/bsp/stm32h5/family.mk new file mode 100644 index 000000000..e04e08d80 --- /dev/null +++ b/hw/bsp/stm32h5/family.mk @@ -0,0 +1,57 @@ +ST_FAMILY = h5 +DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver + +ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) +ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver + +include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= cortex-m33 + +# -------------- +# Compiler Flags +# -------------- +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_STM32H5 + +# workaround to fix a build issue due to a wrong define check in hal, this define must be removed as soon as the repo is fixed +CFLAGS += \ + -D__ARMCC_VERSION=0 + +# GCC Flags +CFLAGS_GCC += \ + -flto \ + -nostdlib -nostartfiles \ + -Wno-unused-parameter \ + -Wno-cast-align + +# suppress warning caused by vendor mcu driver +CFLAGS_GCC += -Wno-error=cast-align + +#LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs + +# ----------------- +# Sources & Include +# ----------------- + +SRC_C += \ + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ + $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(ST_CMSIS)/Include \ + $(TOP)/$(ST_HAL_DRIVER)/Inc + +# flash target using on-board stlink +flash: flash-stlink diff --git a/hw/bsp/stm32h5/stm32h5xx_hal_conf.h b/hw/bsp/stm32h5/stm32h5xx_hal_conf.h new file mode 100644 index 000000000..d017bb06b --- /dev/null +++ b/hw/bsp/stm32h5/stm32h5xx_hal_conf.h @@ -0,0 +1,355 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h5xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32h5xx_HAL_CONF_H +#define STM32h5xx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_COMP_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +/* #define HAL_FDCAN_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED + +/* ########################## Register Callbacks selection ############################## */ +/** + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0u +#define USE_HAL_CEC_REGISTER_CALLBACKS 0u +#define USE_HAL_COMP_REGISTER_CALLBACKS 0u +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0u +#define USE_HAL_DAC_REGISTER_CALLBACKS 0u +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0u +#define USE_HAL_HCD_REGISTER_CALLBACKS 0u +#define USE_HAL_I2C_REGISTER_CALLBACKS 0u +#define USE_HAL_I2S_REGISTER_CALLBACKS 0u +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0u +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u +#define USE_HAL_PCD_REGISTER_CALLBACKS 0u +#define USE_HAL_RNG_REGISTER_CALLBACKS 0u +#define USE_HAL_RTC_REGISTER_CALLBACKS 0u +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u +#define USE_HAL_SPI_REGISTER_CALLBACKS 0u +#define USE_HAL_TIM_REGISTER_CALLBACKS 0u +#define USE_HAL_UART_REGISTER_CALLBACKS 0u +#define USE_HAL_USART_REGISTER_CALLBACKS 0u +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u + + +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Core Speed oscillator (CSI) default value. + * This value is the default CSI range value after Reset. + */ +#if !defined (CSI_VALUE) +#define CSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz +The real value may vary depending on the variations +in voltage and temperature.*/ + +#if !defined (LSI_STARTUP_TIME) +#define LSI_STARTUP_TIME 130UL /*!< Time out for LSI start up, in ms */ +#endif /* LSI_STARTUP_TIME */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for SPI/SAI peripheral + * This value is used by the SPI/SAI HAL module to compute the SPI/SAI clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ############################################ System Configuration ################################################ */ + +/** + * @brief This is the HAL system configuration section + */ + +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U /*!< Enable prefetch */ + + + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* ################## CRYP peripheral configuration ########################## */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include modules header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32h5xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32h5xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32h5xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32h5xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32h5xx_hal_adc.h" +#include "stm32h5xx_hal_adc_ex.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED +#include "stm32h5xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32h5xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32h5xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32h5xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED +#include "stm32h5xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32h5xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32h5xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32h5xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32h5xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32h5xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED +#include "stm32h5xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32h5xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32h5xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32h5xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32h5xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32h5xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32h5xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32h5xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32h5xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32h5xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32h5xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32h5xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32h5xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32h5xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32h5xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for functions parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32h5xx_HAL_CONF_H */ diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 6fab190ea..9c4083031 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -210,6 +210,12 @@ #define TUP_DCD_ENDPOINT_MAX 9 +#elif TU_CHECK_MCU(OPT_MCU_STM32H5) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_STM32 + #define TUP_DCD_ENDPOINT_MAX 8 + + #elif TU_CHECK_MCU(OPT_MCU_STM32G4) // Device controller #define TUP_USBIP_FSDEV diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 14cabaf8d..b0a00b7ee 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -242,7 +242,7 @@ void dcd_init (uint8_t rhport) } USB->CNTR = 0; // Enable USB -#ifndef STM32G0 // BTABLE register does not exist any more on STM32G0, it is fixed to USB SRAM base address +#if !defined(STM32G0) && !defined(STM32H5) // BTABLE register does not exist any more on STM32G0, it is fixed to USB SRAM base address USB->BTABLE = DCD_STM32_BTABLE_BASE; #endif USB->ISTR = 0; // Clear pending interrupts @@ -357,6 +357,11 @@ void dcd_int_enable (uint8_t rhport) #else NVIC_EnableIRQ(USB_UCPD1_2_IRQn); #endif + + +#elif CFG_TUSB_MCU == OPT_MCU_STM32H5 + NVIC_EnableIRQ(USB_DRD_FS_IRQn); + #elif CFG_TUSB_MCU == OPT_MCU_STM32WB NVIC_EnableIRQ(USB_HP_IRQn); @@ -414,6 +419,10 @@ void dcd_int_disable(uint8_t rhport) #else NVIC_DisableIRQ(USB_UCPD1_2_IRQn); #endif + +#elif CFG_TUSB_MCU == OPT_MCU_STM32H5 + NVIC_DisableIRQ(USB_DRD_FS_IRQn); + #elif CFG_TUSB_MCU == OPT_MCU_STM32WB NVIC_DisableIRQ(USB_HP_IRQn); diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index e6649de5a..0db426e50 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -110,6 +110,35 @@ #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY #define USB_CNTR_FSUSP USB_CNTR_SUSPEN +#elif CFG_TUSB_MCU == OPT_MCU_STM32H5 + #include "stm32h5xx.h" + #define PMA_32BIT_ACCESS + #define PMA_LENGTH (2048u) + #undef USB_PMAADDR + #define USB_PMAADDR USB_DRD_PMAADDR + #define USB_TypeDef USB_DRD_TypeDef + #define EP0R CHEP0R + #define USB_EP_CTR_RX USB_EP_VTRX + #define USB_EP_CTR_TX USB_EP_VTTX + #define USB_EP_T_FIELD USB_CHEP_UTYPE + #define USB_EPREG_MASK USB_CHEP_REG_MASK + #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK + #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK + #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1 + #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2 + #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1 + #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2 + #define USB_EPRX_STAT USB_CH_RX_VALID + #define USB_EPKIND_MASK USB_EP_KIND_MASK + #define USB USB_DRD_FS + #define USB_CNTR_FRES USB_CNTR_USBRST + #define USB_CNTR_RESUME USB_CNTR_L2RES + #define USB_ISTR_EP_ID USB_ISTR_IDN + #define USB_EPADDR_FIELD USB_CHEP_ADDR + #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY + #define USB_CNTR_FSUSP USB_CNTR_SUSPEN + + #elif CFG_TUSB_MCU == OPT_MCU_STM32WB #include "stm32wbxx.h" #define PMA_LENGTH (1024u) diff --git a/src/tusb_option.h b/src/tusb_option.h index 7597392d6..699691b53 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -86,6 +86,7 @@ #define OPT_MCU_STM32WB 312 ///< ST WB #define OPT_MCU_STM32U5 313 ///< ST U5 #define OPT_MCU_STM32L5 314 ///< ST L5 +#define OPT_MCU_STM32H5 315 ///< ST H5 // Sony #define OPT_MCU_CXD56 400 ///< SONY CXD56 diff --git a/tools/get_deps.py b/tools/get_deps.py index 79c272c07..cda4fc8da 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -95,6 +95,10 @@ deps_optional = { 'hw/mcu/st/cmsis_device_h7': ['https://github.com/STMicroelectronics/cmsis_device_h7.git', '60dc2c913203dc8629dc233d4384dcc41c91e77f', 'stm32h7'], + 'hw/mcu/st/cmsis_device_h5': ['https://github.com/STMicroelectronics/cmsis_device_h5.git', + '62b2cb0fbfe10c5791ee469bbde7b397c2fea8f5', + 'stm32h5'], + 'hw/mcu/st/cmsis_device_l0': ['https://github.com/STMicroelectronics/cmsis_device_l0.git', '06748ca1f93827befdb8b794402320d94d02004f', 'stm32l0'], @@ -140,6 +144,9 @@ deps_optional = { 'hw/mcu/st/stm32h7xx_hal_driver': ['https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git', 'd8461b980b59b1625207d8c4f2ce0a9c2a7a3b04', 'stm32h7'], + 'hw/mcu/st/stm32h5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32h5xx_hal_driver.git', + '2cf77de584196d619cec1b4586c3b9e2820a254e', + 'stm32h5'], 'hw/mcu/st/stm32l0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git', 'fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b', 'stm32l0'], @@ -170,7 +177,7 @@ deps_optional = { 'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git', '20285262657d1b482d132d20d755c8c330d55c1f', 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x' - 'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 ' + 'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5' 'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb'], 'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git', 'e73e04ca63495672d955f9268e003cffe168fcd8', -- cgit v1.3.1 From 19d7d62e804dbf26f9d193d72710574abcd6fa95 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 13 Dec 2023 18:54:00 +0700 Subject: try to add samd51 to hil pool using doublereset (rpi gpio) and bossac --- .github/workflows/cmake_arm.yml | 10 +++++++++- hw/bsp/samd21/family.cmake | 3 ++- hw/bsp/samd51/family.c | 14 ++++++++++++++ hw/bsp/samd51/family.cmake | 4 +++- src/device/usbd_pvt.h | 5 ----- src/host/usbh_pvt.h | 5 ----- src/tusb_option.h | 10 ++++++++++ test/hil/hil_pi4.json | 9 +++++++++ test/hil/hil_test.py | 39 +++++++++++++++++++++++++++++++++++++-- 9 files changed, 84 insertions(+), 15 deletions(-) (limited to 'src') diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml index f760ca3ca..46dc7a93b 100644 --- a/.github/workflows/cmake_arm.yml +++ b/.github/workflows/cmake_arm.yml @@ -102,6 +102,13 @@ jobs: path: | cmake-build/cmake-build-feather_nrf52840_express/*/*/*.elf + - name: Upload Artifacts for Hardware Testing (samd51) + if: matrix.family == 'samd51' && github.repository_owner == 'hathach' + uses: actions/upload-artifact@v3 + with: + name: itsybitsy_m4 + path: | + cmake-build/cmake-build-itsybitsy_m4/*/*/*.bin # --------------------------------------- # Hardware in the loop (HIL) @@ -116,8 +123,9 @@ jobs: fail-fast: false matrix: board: - - 'raspberry_pi_pico' - 'feather_nrf52840_express' + - 'itsybitsy_m4' + - 'raspberry_pi_pico' steps: - name: Clean workspace run: | diff --git a/hw/bsp/samd21/family.cmake b/hw/bsp/samd21/family.cmake index 44aad6ecb..a79a25b54 100644 --- a/hw/bsp/samd21/family.cmake +++ b/hw/bsp/samd21/family.cmake @@ -10,7 +10,7 @@ set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS SAMD21 CACHE INTERNAL "") - +set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -c \"transport select swd\" -f target/at91samdXX.cfg") #------------------------------------ # BOARD_TARGET @@ -102,4 +102,5 @@ function(family_configure_example TARGET RTOS) # Flashing family_flash_jlink(${TARGET}) + #family_flash_openocd(${TARGET} ${OPENOCD_OPTION}) endfunction() diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c index 009a0d290..170c88191 100644 --- a/hw/bsp/samd51/family.c +++ b/hw/bsp/samd51/family.c @@ -157,6 +157,20 @@ uint32_t board_button_read(void) { return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1; } +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + + uint32_t did_addr[4] = {0x008061FC, 0x00806010, 0x00806014, 0x00806018}; + + for (int i = 0; i < 4; i++) { + uint32_t did = *((uint32_t const*) did_addr[i]); + did = TU_BSWAP32(did); // swap endian to match samd51 uf2 bootloader + memcpy(id + i * 4, &did, 4); + } + + return 16; +} + int board_uart_read(uint8_t* buf, int len) { (void) buf; (void) len; diff --git a/hw/bsp/samd51/family.cmake b/hw/bsp/samd51/family.cmake index 7591f3b1b..4d91bf1a6 100644 --- a/hw/bsp/samd51/family.cmake +++ b/hw/bsp/samd51/family.cmake @@ -10,7 +10,7 @@ set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS SAMD51 CACHE INTERNAL "") - +set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -c \"transport select swd\" -c \"set CHIPNAME samd51\" -f target/atsame5x.cfg") #------------------------------------ # BOARD_TARGET @@ -100,5 +100,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) + #family_flash_openocd(${TARGET} ${OPENOCD_OPTION}) endfunction() diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h index 153be7cee..9039bc9d6 100644 --- a/src/device/usbd_pvt.h +++ b/src/device/usbd_pvt.h @@ -33,11 +33,6 @@ extern "C" { #endif -// Level where CFG_TUSB_DEBUG must be at least for USBD is logged -#ifndef CFG_TUD_LOG_LEVEL -#define CFG_TUD_LOG_LEVEL 2 -#endif - #define TU_LOG_USBD(...) TU_LOG(CFG_TUD_LOG_LEVEL, __VA_ARGS__) //--------------------------------------------------------------------+ diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h index 3363ab9eb..4a97a1c18 100644 --- a/src/host/usbh_pvt.h +++ b/src/host/usbh_pvt.h @@ -35,11 +35,6 @@ extern "C" { #endif -// Level where CFG_TUSB_DEBUG must be at least for USBH is logged -#ifndef CFG_TUH_LOG_LEVEL - #define CFG_TUH_LOG_LEVEL 2 -#endif - #define TU_LOG_USBH(...) TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__) enum { diff --git a/src/tusb_option.h b/src/tusb_option.h index 7597392d6..4d2aa137c 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -299,6 +299,16 @@ #define CFG_TUSB_DEBUG 0 #endif +// Level where CFG_TUSB_DEBUG must be at least for USBH is logged +#ifndef CFG_TUH_LOG_LEVEL + #define CFG_TUH_LOG_LEVEL 2 +#endif + +// Level where CFG_TUSB_DEBUG must be at least for USBD is logged +#ifndef CFG_TUD_LOG_LEVEL + #define CFG_TUD_LOG_LEVEL 2 +#endif + // Memory section for placing buffer used for usb transferring. If MEM_SECTION is different for // host and device use: CFG_TUD_MEM_SECTION, CFG_TUH_MEM_SECTION instead #ifndef CFG_TUSB_MEM_SECTION diff --git a/test/hil/hil_pi4.json b/test/hil/hil_pi4.json index 560c3964e..17d9ff1fa 100644 --- a/test/hil/hil_pi4.json +++ b/test/hil/hil_pi4.json @@ -23,6 +23,15 @@ "flasher": "jlink", "flasher_sn": "000682804350", "flasher_args": "-device nrf52840_xxaa" + }, + { + "name": "itsybitsy_m4", + "uid": "D784B28C5338533335202020FF044726", + "flasher": "bossac", + "flashser_vendor": "Adafruit Industries", + "flasher_product": "ItsyBitsy M4 Express", + "flasher_reset_pin": "2", + "flasher_args": "--offset 0x4000" } ] } diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py index 8f8a3aa65..f9611b96e 100644 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -34,6 +34,10 @@ import subprocess import json import glob +# for RPI double reset: install sudo apt install python3-gpiozero or sudo pip install gpiozero +from gpiozero import LED + + ENUM_TIMEOUT = 10 @@ -41,6 +45,8 @@ ENUM_TIMEOUT = 10 def get_serial_dev(id, vendor_str, product_str, ifnum): if vendor_str and product_str: # known vendor and product + vendor_str = vendor_str.replace(' ', '_') + product_str = product_str.replace(' ', '_') return f'/dev/serial/by-id/usb-{vendor_str}_{product_str}_{id}-if{ifnum:02d}' else: # just use id: mostly for cp210x/ftdi flasher @@ -115,7 +121,7 @@ def flash_jlink(board, firmware): def flash_openocd(board, firmware): ret = subprocess.run( - f'openocd -c "adapter serial {board["flasher_sn"]}" {board["flasher_args"]} -c "program {firmware}" -c "reset init" -c "resume" -c "exit"', + f'openocd -c "adapter serial {board["flasher_sn"]}" {board["flasher_args"]} -c "program {firmware} reset exit"', shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) return ret @@ -133,6 +139,35 @@ def flash_esptool(board, firmware): return ret +def doublereset_with_rpi_gpio(board): + # Off = 0 = Reset + led = LED(board["flasher_reset_pin"]) + + led.off() + time.sleep(0.1) + led.on() + time.sleep(0.1) + led.off() + time.sleep(0.1) + led.on() + +def flash_bossac(board, firmware): + # double reset to enter bootloader + doublereset_with_rpi_gpio(board) + + port = get_serial_dev(board["uid"], board["flashser_vendor"], board["flasher_product"], 0) + timeout = ENUM_TIMEOUT + while timeout: + if os.path.exists(port): + time.sleep(0.5) + break + else: + time.sleep(0.5) + timeout = timeout - 0.5 + ret = subprocess.run(f'bossac --port {port} {board["flasher_args"]} -U -i -R -e -w {firmware}', shell=True, stdout=subprocess.PIPE, + stderr=subprocess.STDOUT) + return ret + # ------------------------------------------------------------- # Tests # ------------------------------------------------------------- @@ -305,7 +340,7 @@ def main(config_file, board): for test in test_list: fw_list = [ - # cmake: esp32 use .bin file + # cmake: esp32 & samd51 use .bin file f'cmake-build/cmake-build-{item["name"]}/device/{test}/{test}.elf', f'cmake-build/cmake-build-{item["name"]}/device/{test}/{test}.bin', # make -- cgit v1.3.1 From f3d713ac7336913a68326eae5a7e146ec2cd22c3 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Tue, 12 Dec 2023 22:35:05 +0100 Subject: Fix CI & typo. --- hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h | 2 +- hw/bsp/stm32h5/boards/stm32h573i-dk/board.h | 2 +- hw/bsp/stm32h5/family.mk | 4 ++-- src/common/tusb_mcu.h | 1 - src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 7 ++----- src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 4 ++-- tools/get_deps.py | 1 - 7 files changed, 8 insertions(+), 13 deletions(-) (limited to 'src') diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h index ae0820529..9ebaf73f0 100644 --- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h +++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h @@ -2,7 +2,7 @@ * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) - * Copyright (c) 2034, HiFiPhile + * Copyright (c) 2023, HiFiPhile * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/hw/bsp/stm32h5/boards/stm32h573i-dk/board.h b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.h index 01834f151..a8808e32b 100644 --- a/hw/bsp/stm32h5/boards/stm32h573i-dk/board.h +++ b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.h @@ -2,7 +2,7 @@ * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) - * Copyright (c) 2034, HiFiPhile + * Copyright (c) 2023, HiFiPhile * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/hw/bsp/stm32h5/family.mk b/hw/bsp/stm32h5/family.mk index e04e08d80..2fd95ecec 100644 --- a/hw/bsp/stm32h5/family.mk +++ b/hw/bsp/stm32h5/family.mk @@ -11,9 +11,9 @@ CPU_CORE ?= cortex-m33 # Compiler Flags # -------------- CFLAGS += \ - -DCFG_TUSB_MCU=OPT_MCU_STM32H5 + -DCFG_TUSB_MCU=OPT_MCU_STM32H5 -# workaround to fix a build issue due to a wrong define check in hal, this define must be removed as soon as the repo is fixed +# workaround to fix a build issue due to a wrong define check in hal, this define must be removed as soon as the repo is fixed CFLAGS += \ -D__ARMCC_VERSION=0 diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 9c4083031..e589c4c86 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -214,7 +214,6 @@ #define TUP_USBIP_FSDEV #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 - #elif TU_CHECK_MCU(OPT_MCU_STM32G4) // Device controller diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index b0a00b7ee..21cd3da26 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -357,11 +357,9 @@ void dcd_int_enable (uint8_t rhport) #else NVIC_EnableIRQ(USB_UCPD1_2_IRQn); #endif - - + #elif CFG_TUSB_MCU == OPT_MCU_STM32H5 NVIC_EnableIRQ(USB_DRD_FS_IRQn); - #elif CFG_TUSB_MCU == OPT_MCU_STM32WB NVIC_EnableIRQ(USB_HP_IRQn); @@ -419,10 +417,9 @@ void dcd_int_disable(uint8_t rhport) #else NVIC_DisableIRQ(USB_UCPD1_2_IRQn); #endif - + #elif CFG_TUSB_MCU == OPT_MCU_STM32H5 NVIC_DisableIRQ(USB_DRD_FS_IRQn); - #elif CFG_TUSB_MCU == OPT_MCU_STM32WB NVIC_DisableIRQ(USB_HP_IRQn); diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 0db426e50..b71e4f498 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -137,8 +137,8 @@ #define USB_EPADDR_FIELD USB_CHEP_ADDR #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY #define USB_CNTR_FSUSP USB_CNTR_SUSPEN - - + + #elif CFG_TUSB_MCU == OPT_MCU_STM32WB #include "stm32wbxx.h" #define PMA_LENGTH (1024u) diff --git a/tools/get_deps.py b/tools/get_deps.py index cda4fc8da..38ff81412 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -98,7 +98,6 @@ deps_optional = { 'hw/mcu/st/cmsis_device_h5': ['https://github.com/STMicroelectronics/cmsis_device_h5.git', '62b2cb0fbfe10c5791ee469bbde7b397c2fea8f5', 'stm32h5'], - 'hw/mcu/st/cmsis_device_l0': ['https://github.com/STMicroelectronics/cmsis_device_l0.git', '06748ca1f93827befdb8b794402320d94d02004f', 'stm32l0'], -- cgit v1.3.1 From 7f84fe9bdad2b3d7e2fc48b7dedb8bbdf305bf57 Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Thu, 21 Dec 2023 08:48:59 +0100 Subject: dcd_nrf5x: Fix dcd_edpt_open for iso endpoint When ISO endpoint handling was introduced two lines that clear stall and data toggle bit were left unchanged and they were effective for ISO enadpoint as well. This is incorrect behavior since EPSTALL and DTOGGLE registers have only 3 bits for address. Leaving code that clears toggle bit results in endpoint 0 toggle bit being reset when iso endpoint (8) is opened. Now code that clears stall and toggle bit is applied to non-iso endpoint only as it was done before iso handling was introduced. --- src/portable/nordic/nrf5x/dcd_nrf5x.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index acc967bb3..4e702aed4 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -340,6 +340,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) NRF_USBD->INTENSET = TU_BIT(USBD_INTEN_ENDEPIN0_Pos + epnum); NRF_USBD->EPINEN |= TU_BIT(epnum); } + // clear stall and reset DataToggle + NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr; + NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr; } else { @@ -375,10 +378,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) } } - // clear stall and reset DataToggle - NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr; - NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr; - __ISB(); __DSB(); return true; -- cgit v1.3.1 From a39be99a58847318e67d06db17c24e481d318f08 Mon Sep 17 00:00:00 2001 From: IngHK Date: Tue, 26 Dec 2023 12:24:54 +0100 Subject: improved hex debug print, improved USBH debug prints, added pid/vid debug print --- src/common/tusb_debug.h | 2 +- src/host/usbh.c | 29 ++++++++++++++++------------- src/host/usbh_pvt.h | 6 +++++- 3 files changed, 22 insertions(+), 15 deletions(-) (limited to 'src') diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h index 0f4dc93f3..8db1606ae 100644 --- a/src/common/tusb_debug.h +++ b/src/common/tusb_debug.h @@ -76,7 +76,7 @@ static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) { #define TU_LOG1_MEM tu_print_mem #define TU_LOG1_BUF(_x, _n) tu_print_buf((uint8_t const*)(_x), _n) #define TU_LOG1_INT(_x) tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) ) -#define TU_LOG1_HEX(_x) tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) ) +#define TU_LOG1_HEX(_x) tu_printf(#_x " = 0x%lX\r\n", (unsigned long) (_x) ) // Log Level 2: Warn #if CFG_TUSB_DEBUG >= 2 diff --git a/src/host/usbh.c b/src/host/usbh.c index 4d30d9f81..ee7424ed9 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -291,6 +291,9 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t *vid, uint16_t *pid) { *vid = dev->vid; *pid = dev->pid; + TU_LOG_HEX_USBH(*vid); + TU_LOG_HEX_USBH(*pid); + return true; } @@ -340,12 +343,12 @@ bool tuh_init(uint8_t controller_id) { if ( tuh_inited() ) return true; TU_LOG_USBH("USBH init on controller %u\r\n", controller_id); - TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(usbh_device_t)); - TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(hcd_event_t)); - TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(_ctrl_xfer)); - TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tuh_xfer_t)); - TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tu_fifo_t)); - TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tu_edpt_stream_t)); + TU_LOG_INT_USBH(sizeof(usbh_device_t)); + TU_LOG_INT_USBH(sizeof(hcd_event_t)); + TU_LOG_INT_USBH(sizeof(_ctrl_xfer)); + TU_LOG_INT_USBH(sizeof(tuh_xfer_t)); + TU_LOG_INT_USBH(sizeof(tu_fifo_t)); + TU_LOG_INT_USBH(sizeof(tu_edpt_stream_t)); // Event queue _usbh_q = osal_queue_create( &_usbh_qdef ); @@ -589,7 +592,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr, (xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ? tu_str_std_request[xfer->setup->bRequest] : "Class Request"); - TU_LOG_BUF(CFG_TUH_LOG_LEVEL, xfer->setup, 8); + TU_LOG_BUF_USBH(xfer->setup, 8); TU_LOG_USBH("\r\n"); if (xfer->complete_cb) { @@ -665,9 +668,9 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result tusb_control_request_t const * request = &_ctrl_xfer.request; if (XFER_RESULT_SUCCESS != result) { - TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes); - TU_LOG1_BUF(request, 8); - TU_LOG1("\r\n"); + TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes); + TU_LOG_BUF_USBH(request, 8); + TU_LOG_USBH("\r\n"); // terminate transfer if any stage failed _xfer_complete(dev_addr, result); @@ -685,7 +688,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result case CONTROL_STAGE_DATA: if (request->wLength) { TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, dev_addr); - TU_LOG_MEM(CFG_TUH_LOG_LEVEL, _ctrl_xfer.buffer, xferred_bytes, 2); + TU_LOG_MEM_USBH(_ctrl_xfer.buffer, xferred_bytes, 2); } _ctrl_xfer.actual_len = (uint16_t) xferred_bytes; @@ -860,7 +863,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b // HCD error, mark endpoint as ready to allow next transfer ep_state->busy = 0; ep_state->claimed = 0; - TU_LOG1("Failed\r\n"); + TU_LOG_USBH("Failed\r\n"); // TU_BREAKPOINT(); return false; } @@ -1318,7 +1321,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { if ( retry ) { failed_count++; osal_task_delay(ATTEMPT_DELAY_MS); // delay a bit - TU_LOG1("Enumeration attempt %u\r\n", failed_count); + TU_LOG_USBH("Enumeration attempt %u\r\n", failed_count); retry = tuh_control_xfer(xfer); } diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h index 4a97a1c18..4ed2a72b5 100644 --- a/src/host/usbh_pvt.h +++ b/src/host/usbh_pvt.h @@ -35,7 +35,11 @@ extern "C" { #endif -#define TU_LOG_USBH(...) TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__) +#define TU_LOG_USBH(...) TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__) +#define TU_LOG_MEM_USBH(...) TU_LOG_MEM(CFG_TUH_LOG_LEVEL, __VA_ARGS__) +#define TU_LOG_BUF_USBH(...) TU_LOG_BUF(CFG_TUH_LOG_LEVEL, __VA_ARGS__) +#define TU_LOG_INT_USBH(...) TU_LOG_INT(CFG_TUH_LOG_LEVEL, __VA_ARGS__) +#define TU_LOG_HEX_USBH(...) TU_LOG_HEX(CFG_TUH_LOG_LEVEL, __VA_ARGS__) enum { USBH_EPSIZE_BULK_MAX = (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS) -- cgit v1.3.1 From 551e47a464f55e1e36e2812e79902f4ef2955a17 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Dec 2023 22:50:01 +0700 Subject: allow rp2040 to use max3421e as host controller - fix warnings build hcd max3421 with rp2040 - add tinyusb_host_max3421 target for rp2040 cmake, -DMAX3421_HOST=1 will enable this - add max3421 driver implementation for rp2040 family - update tusb_config for host to allow easy enable host selection for rp2040 (default/pio-usb/max3421) --- .idea/cmake.xml | 15 +-- examples/host/bare_api/src/tusb_config.h | 64 +++++----- examples/host/cdc_msc_hid/src/tusb_config.h | 64 +++++----- .../host/cdc_msc_hid_freertos/src/tusb_config.h | 64 +++++----- examples/host/hid_controller/src/tusb_config.h | 64 +++++----- examples/host/msc_file_explorer/src/tusb_config.h | 65 +++++----- hw/bsp/rp2040/board.h | 11 ++ hw/bsp/rp2040/family.c | 140 +++++++++++++++------ hw/bsp/rp2040/family.cmake | 22 +++- src/portable/analog/max3421/hcd_max3421.c | 36 +++--- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 2 +- 11 files changed, 341 insertions(+), 206 deletions(-) (limited to 'src') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index d12e44789..d3917c1f7 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -2,16 +2,17 @@ - - - + + + + - + @@ -25,7 +26,7 @@ - + @@ -39,10 +40,10 @@ - - + + diff --git a/examples/host/bare_api/src/tusb_config.h b/examples/host/bare_api/src/tusb_config.h index ede9618d3..05ffbdf75 100644 --- a/examples/host/bare_api/src/tusb_config.h +++ b/examples/host/bare_api/src/tusb_config.h @@ -30,28 +30,8 @@ extern "C" { #endif -//--------------------------------------------------------------------+ -// Board Specific Configuration -//--------------------------------------------------------------------+ - -#if CFG_TUSB_MCU == OPT_MCU_RP2040 -// change to 1 if using pico-pio-usb as host controller for raspberry rp2040 -#define CFG_TUH_RPI_PIO_USB 0 -#define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_USB -#endif - -// RHPort number used for host can be defined by board.mk, default to port 0 -#ifndef BOARD_TUH_RHPORT -#define BOARD_TUH_RHPORT 0 -#endif - -// RHPort max operational speed can defined by board.mk -#ifndef BOARD_TUH_MAX_SPEED -#define BOARD_TUH_MAX_SPEED OPT_MODE_DEFAULT_SPEED -#endif - //-------------------------------------------------------------------- -// COMMON CONFIGURATION +// Common Configuration //-------------------------------------------------------------------- // defined by compiler flags for flexibility @@ -67,12 +47,6 @@ #define CFG_TUSB_DEBUG 0 #endif -// Enable Host stack -#define CFG_TUH_ENABLED 1 - -// Default is max speed that hardware controller could support with on-chip PHY -#define CFG_TUH_MAX_SPEED BOARD_TUH_MAX_SPEED - /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. * Tinyusb use follows macros to declare transferring memory so that they can be put * into those specific section. @@ -85,11 +59,43 @@ #endif #ifndef CFG_TUH_MEM_ALIGN -#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4))) +#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// Host Configuration +//-------------------------------------------------------------------- + +// Enable Host stack +#define CFG_TUH_ENABLED 1 + +#if CFG_TUSB_MCU == OPT_MCU_RP2040 + // #define CFG_TUH_RPI_PIO_USB 1 // use pio-usb as host controller + // #define CFG_TUH_RPI_PIO_USB 1 // use max3421 as host controller + + // host roothub port is 1 if using either pio-usb or max3421 + #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) + #define BOARD_TUH_RHPORT 1 + #endif +#endif + +// Default is max speed that hardware controller could support with on-chip PHY +#define CFG_TUH_MAX_SPEED BOARD_TUH_MAX_SPEED + +//------------------------- Board Specific -------------------------- + +// RHPort number used for host can be defined by board.mk, default to port 0 +#ifndef BOARD_TUH_RHPORT +#define BOARD_TUH_RHPORT 0 +#endif + +// RHPort max operational speed can defined by board.mk +#ifndef BOARD_TUH_MAX_SPEED +#define BOARD_TUH_MAX_SPEED OPT_MODE_DEFAULT_SPEED #endif //-------------------------------------------------------------------- -// CONFIGURATION +// Driver Configuration //-------------------------------------------------------------------- // Size of buffer to hold descriptors and other data used for enumeration diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index a53000a11..61abb85eb 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -30,28 +30,8 @@ extern "C" { #endif -//--------------------------------------------------------------------+ -// Board Specific Configuration -//--------------------------------------------------------------------+ - -#if CFG_TUSB_MCU == OPT_MCU_RP2040 - // change to 1 if using pico-pio-usb as host controller for raspberry rp2040 - #define CFG_TUH_RPI_PIO_USB 0 - #define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_USB -#endif - -// RHPort number used for host can be defined by board.mk, default to port 0 -#ifndef BOARD_TUH_RHPORT -#define BOARD_TUH_RHPORT 0 -#endif - -// RHPort max operational speed can defined by board.mk -#ifndef BOARD_TUH_MAX_SPEED -#define BOARD_TUH_MAX_SPEED OPT_MODE_DEFAULT_SPEED -#endif - //-------------------------------------------------------------------- -// COMMON CONFIGURATION +// Common Configuration //-------------------------------------------------------------------- // defined by compiler flags for flexibility @@ -67,12 +47,6 @@ #define CFG_TUSB_DEBUG 0 #endif -// Enable Host stack -#define CFG_TUH_ENABLED 1 - -// Default is max speed that hardware controller could support with on-chip PHY -#define CFG_TUH_MAX_SPEED BOARD_TUH_MAX_SPEED - /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. * Tinyusb use follows macros to declare transferring memory so that they can be put * into those specific section. @@ -85,11 +59,43 @@ #endif #ifndef CFG_TUH_MEM_ALIGN -#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4))) +#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// Host Configuration +//-------------------------------------------------------------------- + +// Enable Host stack +#define CFG_TUH_ENABLED 1 + +#if CFG_TUSB_MCU == OPT_MCU_RP2040 + // #define CFG_TUH_RPI_PIO_USB 1 // use pio-usb as host controller + // #define CFG_TUH_RPI_PIO_USB 1 // use max3421 as host controller + + // host roothub port is 1 if using either pio-usb or max3421 + #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) + #define BOARD_TUH_RHPORT 1 + #endif +#endif + +// Default is max speed that hardware controller could support with on-chip PHY +#define CFG_TUH_MAX_SPEED BOARD_TUH_MAX_SPEED + +//------------------------- Board Specific -------------------------- + +// RHPort number used for host can be defined by board.mk, default to port 0 +#ifndef BOARD_TUH_RHPORT +#define BOARD_TUH_RHPORT 0 +#endif + +// RHPort max operational speed can defined by board.mk +#ifndef BOARD_TUH_MAX_SPEED +#define BOARD_TUH_MAX_SPEED OPT_MODE_DEFAULT_SPEED #endif //-------------------------------------------------------------------- -// CONFIGURATION +// Driver Configuration //-------------------------------------------------------------------- // Size of buffer to hold descriptors and other data used for enumeration diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h index ba23301ed..c661f47be 100644 --- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h @@ -30,28 +30,8 @@ extern "C" { #endif -//--------------------------------------------------------------------+ -// Board Specific Configuration -//--------------------------------------------------------------------+ - -#if CFG_TUSB_MCU == OPT_MCU_RP2040 - // change to 1 if using pico-pio-usb as host controller for raspberry rp2040 - #define CFG_TUH_RPI_PIO_USB 0 - #define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_USB -#endif - -// RHPort number used for host can be defined by board.mk, default to port 0 -#ifndef BOARD_TUH_RHPORT -#define BOARD_TUH_RHPORT 0 -#endif - -// RHPort max operational speed can defined by board.mk -#ifndef BOARD_TUH_MAX_SPEED -#define BOARD_TUH_MAX_SPEED OPT_MODE_DEFAULT_SPEED -#endif - //-------------------------------------------------------------------- -// COMMON CONFIGURATION +// Common Configuration //-------------------------------------------------------------------- // defined by compiler flags for flexibility @@ -72,12 +52,6 @@ #define CFG_TUSB_DEBUG 0 #endif -// Enable Host stack -#define CFG_TUH_ENABLED 1 - -// Default is max speed that hardware controller could support with on-chip PHY -#define CFG_TUH_MAX_SPEED BOARD_TUH_MAX_SPEED - /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. * Tinyusb use follows macros to declare transferring memory so that they can be put * into those specific section. @@ -90,11 +64,43 @@ #endif #ifndef CFG_TUH_MEM_ALIGN -#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4))) +#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// Host Configuration +//-------------------------------------------------------------------- + +// Enable Host stack +#define CFG_TUH_ENABLED 1 + +#if CFG_TUSB_MCU == OPT_MCU_RP2040 + // #define CFG_TUH_RPI_PIO_USB 1 // use pio-usb as host controller + // #define CFG_TUH_RPI_PIO_USB 1 // use max3421 as host controller + + // host roothub port is 1 if using either pio-usb or max3421 + #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) + #define BOARD_TUH_RHPORT 1 + #endif +#endif + +// Default is max speed that hardware controller could support with on-chip PHY +#define CFG_TUH_MAX_SPEED BOARD_TUH_MAX_SPEED + +//------------------------- Board Specific -------------------------- + +// RHPort number used for host can be defined by board.mk, default to port 0 +#ifndef BOARD_TUH_RHPORT +#define BOARD_TUH_RHPORT 0 +#endif + +// RHPort max operational speed can defined by board.mk +#ifndef BOARD_TUH_MAX_SPEED +#define BOARD_TUH_MAX_SPEED OPT_MODE_DEFAULT_SPEED #endif //-------------------------------------------------------------------- -// CONFIGURATION +// Driver Configuration //-------------------------------------------------------------------- // Size of buffer to hold descriptors and other data used for enumeration diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h index d37fc02d2..8ddaddda7 100644 --- a/examples/host/hid_controller/src/tusb_config.h +++ b/examples/host/hid_controller/src/tusb_config.h @@ -30,28 +30,8 @@ extern "C" { #endif -//--------------------------------------------------------------------+ -// Board Specific Configuration -//--------------------------------------------------------------------+ - - #if CFG_TUSB_MCU == OPT_MCU_RP2040 -// change to 1 if using pico-pio-usb as host controller for raspberry rp2040 -#define CFG_TUH_RPI_PIO_USB 0 -#define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_USB -#endif - -// RHPort number used for host can be defined by board.mk, default to port 0 -#ifndef BOARD_TUH_RHPORT -#define BOARD_TUH_RHPORT 0 -#endif - -// RHPort max operational speed can defined by board.mk -#ifndef BOARD_TUH_MAX_SPEED -#define BOARD_TUH_MAX_SPEED OPT_MODE_DEFAULT_SPEED -#endif - //-------------------------------------------------------------------- -// COMMON CONFIGURATION +// Common Configuration //-------------------------------------------------------------------- // defined by compiler flags for flexibility @@ -67,12 +47,6 @@ #define CFG_TUSB_DEBUG 0 #endif -// Enable Host stack -#define CFG_TUH_ENABLED 1 - -// Default is max speed that hardware controller could support with on-chip PHY -#define CFG_TUH_MAX_SPEED BOARD_TUH_MAX_SPEED - /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. * Tinyusb use follows macros to declare transferring memory so that they can be put * into those specific section. @@ -85,11 +59,43 @@ #endif #ifndef CFG_TUH_MEM_ALIGN -#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4))) +#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// Host Configuration +//-------------------------------------------------------------------- + +// Enable Host stack +#define CFG_TUH_ENABLED 1 + +#if CFG_TUSB_MCU == OPT_MCU_RP2040 + // #define CFG_TUH_RPI_PIO_USB 1 // use pio-usb as host controller + // #define CFG_TUH_RPI_PIO_USB 1 // use max3421 as host controller + + // host roothub port is 1 if using either pio-usb or max3421 + #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) + #define BOARD_TUH_RHPORT 1 + #endif +#endif + +// Default is max speed that hardware controller could support with on-chip PHY +#define CFG_TUH_MAX_SPEED BOARD_TUH_MAX_SPEED + +//------------------------- Board Specific -------------------------- + +// RHPort number used for host can be defined by board.mk, default to port 0 +#ifndef BOARD_TUH_RHPORT +#define BOARD_TUH_RHPORT 0 +#endif + +// RHPort max operational speed can defined by board.mk +#ifndef BOARD_TUH_MAX_SPEED +#define BOARD_TUH_MAX_SPEED OPT_MODE_DEFAULT_SPEED #endif //-------------------------------------------------------------------- -// CONFIGURATION +// Driver Configuration //-------------------------------------------------------------------- // Size of buffer to hold descriptors and other data used for enumeration diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h index b4ccd8223..1703761a4 100644 --- a/examples/host/msc_file_explorer/src/tusb_config.h +++ b/examples/host/msc_file_explorer/src/tusb_config.h @@ -30,29 +30,8 @@ extern "C" { #endif -//--------------------------------------------------------------------+ -// Board Specific Configuration -//--------------------------------------------------------------------+ - -#if CFG_TUSB_MCU == OPT_MCU_RP2040 - // change to 1 if using pico-pio-usb as host controller for raspberry rp2040 - #define CFG_TUH_RPI_PIO_USB 0 - #define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_USB -#endif - - -// RHPort number used for host can be defined by board.mk, default to port 0 -#ifndef BOARD_TUH_RHPORT -#define BOARD_TUH_RHPORT 0 -#endif - -// RHPort max operational speed can defined by board.mk -#ifndef BOARD_TUH_MAX_SPEED -#define BOARD_TUH_MAX_SPEED OPT_MODE_DEFAULT_SPEED -#endif - //-------------------------------------------------------------------- -// COMMON CONFIGURATION +// Common Configuration //-------------------------------------------------------------------- // defined by compiler flags for flexibility @@ -68,12 +47,6 @@ #define CFG_TUSB_DEBUG 0 #endif -// Enable Host stack -#define CFG_TUH_ENABLED 1 - -// Default is max speed that hardware controller could support with on-chip PHY -#define CFG_TUH_MAX_SPEED BOARD_TUH_MAX_SPEED - /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. * Tinyusb use follows macros to declare transferring memory so that they can be put * into those specific section. @@ -86,11 +59,43 @@ #endif #ifndef CFG_TUH_MEM_ALIGN -#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4))) +#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// Host Configuration +//-------------------------------------------------------------------- + +// Enable Host stack +#define CFG_TUH_ENABLED 1 + +#if CFG_TUSB_MCU == OPT_MCU_RP2040 + // #define CFG_TUH_RPI_PIO_USB 1 // use pio-usb as host controller + // #define CFG_TUH_RPI_PIO_USB 1 // use max3421 as host controller + + // host roothub port is 1 if using either pio-usb or max3421 + #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) + #define BOARD_TUH_RHPORT 1 + #endif +#endif + +// Default is max speed that hardware controller could support with on-chip PHY +#define CFG_TUH_MAX_SPEED BOARD_TUH_MAX_SPEED + +//------------------------- Board Specific -------------------------- + +// RHPort number used for host can be defined by board.mk, default to port 0 +#ifndef BOARD_TUH_RHPORT +#define BOARD_TUH_RHPORT 0 +#endif + +// RHPort max operational speed can defined by board.mk +#ifndef BOARD_TUH_MAX_SPEED +#define BOARD_TUH_MAX_SPEED OPT_MODE_DEFAULT_SPEED #endif //-------------------------------------------------------------------- -// CONFIGURATION +// Driver Configuration //-------------------------------------------------------------------- // Size of buffer to hold descriptors and other data used for enumeration diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h index 063c9580e..3849894ce 100644 --- a/hw/bsp/rp2040/board.h +++ b/hw/bsp/rp2040/board.h @@ -74,6 +74,17 @@ #define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 #endif +//-------------------------------------------------------------------- +// USB Host MAX3421E +//-------------------------------------------------------------------- + +#define MAX3421_SPI PICO_DEFAULT_SPI_INSTANCE +#define MAX3421_SCK_PIN PICO_DEFAULT_SPI_SCK_PIN +#define MAX3421_MOSI_PIN PICO_DEFAULT_SPI_TX_PIN +#define MAX3421_MISO_PIN PICO_DEFAULT_SPI_RX_PIN +#define MAX3421_CS_PIN 10 +#define MAX3421_INTR_PIN 9 + #ifdef __cplusplus } #endif diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index 5ac104688..cffb632f3 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -37,10 +37,19 @@ #include "bsp/board_api.h" #include "board.h" +#ifdef UART_DEV +static uart_inst_t *uart_inst; +#endif + #if CFG_TUH_RPI_PIO_USB || CFG_TUD_RPI_PIO_USB #include "pio_usb.h" #endif +#if CFG_TUH_ENABLED && CFG_TUH_MAX3421 +#include "hardware/spi.h" +static void max3421_init(void); +#endif + #ifdef BUTTON_BOOTSEL // This example blinks the Picoboard LED when the BOOTSEL button is pressed. // @@ -53,73 +62,66 @@ // This doesn't work if others are trying to access flash at the same time, // e.g. XIP streamer, or the other core. bool __no_inline_not_in_flash_func(get_bootsel_button)(void) { - const uint CS_PIN_INDEX = 1; + const uint CS_PIN_INDEX = 1; - // Must disable interrupts, as interrupt handlers may be in flash, and we - // are about to temporarily disable flash access! - uint32_t flags = save_and_disable_interrupts(); + // Must disable interrupts, as interrupt handlers may be in flash, and we + // are about to temporarily disable flash access! + uint32_t flags = save_and_disable_interrupts(); - // Set chip select to Hi-Z - hw_write_masked(&ioqspi_hw->io[CS_PIN_INDEX].ctrl, - GPIO_OVERRIDE_LOW << IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB, - IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS); + // Set chip select to Hi-Z + hw_write_masked(&ioqspi_hw->io[CS_PIN_INDEX].ctrl, + GPIO_OVERRIDE_LOW << IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB, + IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS); - // Note we can't call into any sleep functions in flash right now - for (volatile int i = 0; i < 1000; ++i); + // Note we can't call into any sleep functions in flash right now + for (volatile int i = 0; i < 1000; ++i); - // The HI GPIO registers in SIO can observe and control the 6 QSPI pins. - // Note the button pulls the pin *low* when pressed. - bool button_state = (sio_hw->gpio_hi_in & (1u << CS_PIN_INDEX)); + // The HI GPIO registers in SIO can observe and control the 6 QSPI pins. + // Note the button pulls the pin *low* when pressed. + bool button_state = (sio_hw->gpio_hi_in & (1u << CS_PIN_INDEX)); - // Need to restore the state of chip select, else we are going to have a - // bad time when we return to code in flash! - hw_write_masked(&ioqspi_hw->io[CS_PIN_INDEX].ctrl, - GPIO_OVERRIDE_NORMAL << IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB, - IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS); + // Need to restore the state of chip select, else we are going to have a + // bad time when we return to code in flash! + hw_write_masked(&ioqspi_hw->io[CS_PIN_INDEX].ctrl, + GPIO_OVERRIDE_NORMAL << IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB, + IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS); - restore_interrupts(flags); + restore_interrupts(flags); - return button_state; + return button_state; } #endif //------------- Segger RTT retarget -------------// #if defined(LOGGER_RTT) - // Logging with RTT // - If RTT Control Block is not found by 'Auto Detection` try to use 'Search Range` with '0x20000000 0x10000' // - SWD speed is rather slow around 1000Khz - #include "pico/stdio/driver.h" #include "SEGGER_RTT.h" -static void stdio_rtt_write (const char *buf, int length) -{ +static void stdio_rtt_write (const char *buf, int length) { SEGGER_RTT_Write(0, buf, (unsigned) length); } -static int stdio_rtt_read (char *buf, int len) -{ +static int stdio_rtt_read (char *buf, int len) { return (int) SEGGER_RTT_Read(0, buf, (unsigned) len); } -static stdio_driver_t stdio_rtt = -{ +static stdio_driver_t stdio_rtt = { .out_chars = stdio_rtt_write, .out_flush = NULL, .in_chars = stdio_rtt_read }; -void stdio_rtt_init(void) -{ +void stdio_rtt_init(void) { stdio_set_driver_enabled(&stdio_rtt, true); } - #endif -#ifdef UART_DEV -static uart_inst_t *uart_inst; -#endif +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ void board_init(void) { @@ -165,7 +167,9 @@ void board_init(void) #endif #if CFG_TUH_ENABLED - // set portfunc to host !!! + #if CFG_TUH_MAX3421 + max3421_init(); + #endif #endif #if !CFG_TUD_ENABLED && !CFG_TUH_ENABLED @@ -242,3 +246,69 @@ int board_getchar(void) { // rp2040 implementation will install appropriate handler when initializing // tinyusb. There is no need to forward IRQ from application //--------------------------------------------------------------------+ + +//--------------------------------------------------------------------+ +// API: SPI transfer with MAX3421E, must be implemented by application +//--------------------------------------------------------------------+ +#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 + +void max3421_int_handler(uint gpio, uint32_t event_mask) { + if (!(gpio == MAX3421_INTR_PIN && event_mask & GPIO_IRQ_EDGE_FALL)) return; + tuh_int_handler(BOARD_TUH_RHPORT, true); +} + +static void max3421_init(void) { + // CS pin + gpio_init(MAX3421_CS_PIN); + gpio_set_dir(MAX3421_CS_PIN, GPIO_OUT); + gpio_put(MAX3421_CS_PIN, true); + + // Interrupt pin + gpio_init(MAX3421_INTR_PIN); + gpio_set_dir(MAX3421_INTR_PIN, GPIO_IN); + gpio_pull_up(MAX3421_INTR_PIN); + gpio_set_irq_enabled_with_callback(MAX3421_INTR_PIN, GPIO_IRQ_EDGE_FALL, true, max3421_int_handler); + + // SPI init + spi_init(MAX3421_SPI, 4*1000000ul); + gpio_set_function(MAX3421_SCK_PIN, GPIO_FUNC_SPI); + gpio_set_function(MAX3421_MOSI_PIN, GPIO_FUNC_SPI); + gpio_set_function(MAX3421_MISO_PIN, GPIO_FUNC_SPI); + spi_set_format(MAX3421_SPI, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST); +} + +//// API to enable/disable MAX3421 INTR pin interrupt +void tuh_max3421_int_api(uint8_t rhport, bool enabled) { + (void) rhport; + irq_set_enabled(IO_IRQ_BANK0, enabled); +} + +// API to control MAX3421 SPI CS +void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) { + (void) rhport; + gpio_put(MAX3421_CS_PIN, !active); +} + +// API to transfer data with MAX3421 SPI +// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only +bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) { + (void) rhport; + + if (tx_buf == NULL && rx_buf == NULL) { + return false; + } + + int ret; + + if (tx_buf == NULL) { + ret = spi_read_blocking(MAX3421_SPI, 0, rx_buf, xfer_bytes); + }else if (rx_buf == NULL) { + ret = spi_write_blocking(MAX3421_SPI, tx_buf, xfer_bytes); + }else { + ret = spi_write_read_blocking(spi0, tx_buf, rx_buf, xfer_bytes); + } + + return ret == (int) xfer_bytes; +} + +#endif diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index 77d8029d9..ec40806fd 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -103,6 +103,20 @@ target_compile_definitions(tinyusb_host_base INTERFACE RP2040_USB_HOST_MODE=1 ) +#------------------------------------ +# Host MAX3421 +#------------------------------------ +add_library(tinyusb_host_max3421 INTERFACE) +target_sources(tinyusb_host_max3421 INTERFACE + ${TOP}/src/portable/analog/max3421/hcd_max3421.c + ) +target_compile_definitions(tinyusb_host_max3421 INTERFACE + CFG_TUH_MAX3421=1 + ) +target_link_libraries(tinyusb_host_max3421 INTERFACE + hardware_spi + ) + #------------------------------------ # BSP & Additions #------------------------------------ @@ -126,7 +140,7 @@ target_compile_definitions(tinyusb_additions INTERFACE if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt") target_compile_definitions(tinyusb_additions INTERFACE LOGGER_RTT - SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL + #SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL ) target_sources(tinyusb_additions INTERFACE @@ -186,6 +200,7 @@ function(family_add_pico_pio_usb TARGET) target_link_libraries(${TARGET} PUBLIC tinyusb_pico_pio_usb) endfunction() + # since Pico-PIO_USB compiler support may lag, and change from version to version, add a function that pico-sdk/pico-examples # can check (if present) in case the user has updated their TinyUSB function(is_compiler_supported_by_pico_pio_usb OUTVAR) @@ -209,6 +224,11 @@ function(family_configure_host_example TARGET RTOS) family_add_pico_pio_usb(${PROJECT}) endif() endif() + + # for max3421 host + if (MAX3421_HOST STREQUAL "1") + target_link_libraries(${TARGET} PUBLIC tinyusb_host_max3421) + endif() endfunction() diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 051b7eaa8..cc4799dd6 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -171,6 +171,8 @@ enum { //--------------------------------------------------------------------+ typedef struct { + uint8_t daddr; + struct TU_ATTR_PACKED { uint8_t ep_dir : 1; uint8_t is_iso : 1; @@ -179,17 +181,19 @@ typedef struct { uint8_t xfer_pending : 1; uint8_t xfer_complete : 1; }; + struct TU_ATTR_PACKED { - uint8_t daddr : 4; uint8_t ep_num : 4; + uint16_t packet_size : 12; }; - uint16_t packet_size; uint16_t total_len; uint16_t xferred_len; uint8_t* buf; } max3421_ep_t; +TU_VERIFY_STATIC(sizeof(max3421_ep_t) == 12, "size is not correct"); + typedef struct { // cached register uint8_t sndbc; @@ -320,7 +324,7 @@ static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_is static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) { reg_write(rhport, HIRQ_ADDR, data, in_isr); // HIRQ write 1 is clear - _hcd_data.hirq &= ~data; + _hcd_data.hirq &= (uint8_t) ~data; } static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) { @@ -390,7 +394,7 @@ static void free_ep(uint8_t daddr) { } static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) { - size_t const idx = cur_ep - _hcd_data.ep; + size_t const idx = (size_t) (cur_ep - _hcd_data.ep); // starting from next endpoint for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) { @@ -537,8 +541,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e (void) rhport; (void) daddr; - uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress); - uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress); + uint8_t const ep_num = tu_edpt_number(ep_desc->bEndpointAddress); + tusb_dir_t const ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress); max3421_ep_t * ep; if (daddr == 0 && ep_num == 0) { @@ -547,15 +551,15 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e ep = allocate_ep(); TU_ASSERT(ep); ep->daddr = daddr; - ep->ep_num = ep_num; - ep->ep_dir = ep_dir; + ep->ep_num = (uint8_t) (ep_num & 0x0f); + ep->ep_dir = (ep_dir == TUSB_DIR_IN) ? 1 : 0; } if ( TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer ) { ep->is_iso = 1; } - ep->packet_size = tu_edpt_packet_size(ep_desc); + ep->packet_size = (uint16_t) (tu_edpt_packet_size(ep_desc) & 0x7ff); return true; } @@ -577,7 +581,7 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { } sndbc_write(rhport, xact_len, in_isr); - uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0); + uint8_t const hxfr = (uint8_t ) (ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0)); hxfr_write(rhport, hxfr, in_isr); } @@ -590,7 +594,7 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { reg_write(rhport, HCTL_ADDR, hctl, in_isr); } - uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0); + uint8_t const hxfr = (uint8_t) (ep->ep_num | (ep->is_iso ? HXFR_ISO : 0)); hxfr_write(rhport, hxfr, in_isr); } @@ -623,13 +627,13 @@ TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { uint8_t const ep_num = tu_edpt_number(ep_addr); - uint8_t const ep_dir = tu_edpt_dir(ep_addr); + uint8_t const ep_dir = (uint8_t) tu_edpt_dir(ep_addr); max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir); TU_VERIFY(ep); // control transfer can switch direction - ep->ep_dir = ep_dir; + ep->ep_dir = ep_dir ? 1u : 0u; ep->buf = buffer; ep->total_len = buflen; @@ -748,9 +752,9 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re // save data toggle if (ep->ep_dir) { - ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; + ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1u : 0u; }else { - ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; + ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1u : 0u; } ep->xfer_pending = 0; @@ -929,7 +933,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { } // clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing - hirq &= ~HIRQ_SNDBAV_IRQ; + hirq &= (uint8_t) ~HIRQ_SNDBAV_IRQ; if ( hirq ) { hirq_write(rhport, hirq, in_isr); } diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 4ed6d36bb..08aef9314 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -27,7 +27,7 @@ #include "tusb_option.h" -#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUH_RPI_PIO_USB +#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUH_RPI_PIO_USB && !CFG_TUH_MAX3421 #include "pico.h" #include "rp2040_usb.h" -- cgit v1.3.1 From c2bbcc9f60a2b7293fad4e24468d3f045fde28ee Mon Sep 17 00:00:00 2001 From: IngHK Date: Tue, 26 Dec 2023 20:14:03 +0100 Subject: initial support of CH34x CDC device --- examples/host/cdc_msc_hid/src/tusb_config.h | 1 + .../host/cdc_msc_hid_freertos/src/tusb_config.h | 1 + src/class/cdc/cdc_host.c | 466 ++++++++++++++++++++- src/class/cdc/serial/ch34x.h | 113 +++++ src/tusb_option.h | 17 + 5 files changed, 595 insertions(+), 3 deletions(-) create mode 100644 src/class/cdc/serial/ch34x.h (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index 61abb85eb..76d59c316 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -105,6 +105,7 @@ #define CFG_TUH_CDC 1 // CDC ACM #define CFG_TUH_CDC_FTDI 1 // FTDI Serial. FTDI is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_CDC_CP210X 1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API +#define CFG_TUH_CDC_CH34X 1 // CH340 or CH341 Serial. CH34X is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_HID (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces #define CFG_TUH_MSC 1 #define CFG_TUH_VENDOR 0 diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h index c661f47be..bb7c3388d 100644 --- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h @@ -110,6 +110,7 @@ #define CFG_TUH_CDC 1 // CDC ACM #define CFG_TUH_CDC_FTDI 1 // FTDI Serial. FTDI is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_CDC_CP210X 1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API +#define CFG_TUH_CDC_CH34X 1 // CH340 or CH341 Serial. CH34X is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_HID (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces #define CFG_TUH_MSC 1 #define CFG_TUH_VENDOR 0 diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index a6dfb45ae..9b5186e0c 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -2,6 +2,7 @@ * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) + * Copyright (c) 2023 Heiko Kuester (CH34x support) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -69,7 +70,16 @@ typedef struct { uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE]; } stream; - + #if CFG_TUH_CDC_CH34X + struct { + uint32_t baud_rate; + uint8_t mcr; + uint8_t msr; + uint8_t lcr; + uint32_t quirks; + uint8_t version; + } ch34x; + #endif } cdch_interface_t; CFG_TUH_MEM_SECTION @@ -121,6 +131,23 @@ static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif +//------------- CH34x prototypes -------------// +#if CFG_TUH_CDC_CH34X +#include "serial/ch34x.h" + +static uint16_t const ch34x_vids_pids[][2] = { CFG_TUH_CDC_CH34X_VID_PID_LIST }; +enum { + CH34X_VID_PID_COUNT = sizeof ( ch34x_vids_pids ) / sizeof ( ch34x_vids_pids[0] ) +}; + +static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len ); +static void ch34x_process_config ( tuh_xfer_t* xfer ); + +static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data ); +static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ); +#endif + + enum { SERIAL_DRIVER_ACM = 0, @@ -131,6 +158,10 @@ enum { #if CFG_TUH_CDC_CP210X SERIAL_DRIVER_CP210X, #endif + +#if CFG_TUH_CDC_CH34X + SERIAL_DRIVER_CH34X, +#endif }; typedef struct { @@ -159,6 +190,13 @@ static const cdch_serial_driver_t serial_drivers[] = { .set_baudrate = cp210x_set_baudrate }, #endif + + #if CFG_TUH_CDC_CH34X + { .process_set_config = ch34x_process_config, + .set_control_line_state = ch34x_set_modem_ctrl, + .set_baudrate = ch34x_set_baudrate + }, +#endif }; enum { @@ -426,6 +464,12 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) break; #endif + #if CFG_TUH_CDC_CH34X + case SERIAL_DRIVER_CH34X: + TU_ASSERT(false, ); // see special ch34x_control_complete function + break; + #endif + default: break; } } @@ -641,7 +685,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d { return acm_open(daddr, itf_desc, max_len); } - #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X + #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X else if ( 0xff == itf_desc->bInterfaceClass ) { uint16_t vid, pid; @@ -666,8 +710,16 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d } } #endif + + #if CFG_TUH_CDC_CH34X + for (size_t i = 0; i < CH34X_VID_PID_COUNT; i++) { + if ( ch34x_vids_pids[i][0] == vid && ch34x_vids_pids[i][1] == pid ) { + return ch34x_open(daddr, itf_desc, max_len); + } + } + #endif } - #endif + #endif // CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X return false; } @@ -1176,4 +1228,412 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { #endif +//--------------------------------------------------------------------+ +// CH34x +//--------------------------------------------------------------------+ + +#if CFG_TUH_CDC_CH34X + +enum { + CONFIG_CH34X_STEP1 = 0, + CONFIG_CH34X_STEP2, + CONFIG_CH34X_STEP3, + CONFIG_CH34X_STEP4, + CONFIG_CH34X_STEP5, + CONFIG_CH34X_STEP6, + CONFIG_CH34X_STEP7, + CONFIG_CH34X_STEP8, + CONFIG_CH34X_COMPLETE +}; + +static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len ) +{ + // CH34x Interface includes 1 vendor interface + 3 bulk endpoints + TU_VERIFY ( itf_desc->bNumEndpoints == 3 ); + TU_VERIFY ( sizeof ( tusb_desc_interface_t ) + 2 * sizeof ( tusb_desc_endpoint_t ) <= max_len ); + + cdch_interface_t *p_cdc = make_new_itf ( daddr, itf_desc ); + TU_VERIFY ( p_cdc ); + + TU_LOG_DRV ( "CH34x opened\r\n" ); + p_cdc->serial_drid = SERIAL_DRIVER_CH34X; + + // endpoint pair + tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next ( itf_desc ); + + // data endpoints expected to be in pairs + return open_ep_stream_pair ( p_cdc, desc_ep ); +} + +static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +{ + tusb_control_request_t const request_setup = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_DEVICE, + .type = TUSB_REQ_TYPE_VENDOR, + .direction = direction + }, + .bRequest = request, + .wValue = tu_htole16 ( value ), + .wIndex = tu_htole16 ( index ), + .wLength = tu_htole16 ( length ) + }; + + // use usbh enum buf since application variable does not live long enough + uint8_t* enum_buf = NULL; + + if ( buffer && length > 0 ) { + enum_buf = usbh_get_enum_buf(); + tu_memcpy_s ( enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length ); + } + + tuh_xfer_t xfer = { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request_setup, + .buffer = enum_buf, + .complete_cb = complete_cb, + // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber + .user_data = (uintptr_t)( ( p_cdc->bInterfaceNumber & 0xff ) << 8 ) | ( user_data & 0xff ) + }; + + return tuh_control_xfer ( &xfer ); + return false; +} + +static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +{ + return ch34x_set_request ( p_cdc, TUSB_DIR_OUT, request, value, index, /* buffer */ NULL, /* length */ 0, complete_cb, user_data ); +} + +static bool ch341_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +{ + return ch34x_set_request ( p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize, complete_cb, user_data ); +} + +static int32_t ch341_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +{ + return ch341_control_out ( p_cdc, CH341_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data ); +} + +static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +{ + return ch341_control_in ( p_cdc, CH341_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data ); +} + +/* + * The device line speed is given by the following equation: + * + * baudrate = 48000000 / (2^(12 - 3 * ps - fact) * div), where + * + * 0 <= ps <= 3, + * 0 <= fact <= 1, + * 2 <= div <= 256 if fact = 0, or + * 9 <= div <= 256 if fact = 1 + */ +// calculate baudrate devisors +// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c +static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) +{ + uint32_t fact, div, clk_div; + bool force_fact0 = false; + int32_t ps; + static const uint32_t ch341_min_rates[] = { + CH341_MIN_RATE(0), + CH341_MIN_RATE(1), + CH341_MIN_RATE(2), + CH341_MIN_RATE(3), + }; + + /* + * Clamp to supported range, this makes the (ps < 0) and (div < 2) + * sanity checks below redundant. + */ + inline uint32_t max ( uint32_t val, uint32_t maxval ) { return val > maxval ? val : maxval; } + inline uint32_t min ( uint32_t val, uint32_t minval ) { return val < minval ? val : minval; } + inline uint32_t clamp_val ( uint32_t val, uint32_t minval, uint32_t maxval ) { return min ( max ( val, minval ), maxval ); } + speed = clamp_val(speed, CH341_MIN_BPS, CH341_MAX_BPS); + + /* + * Start with highest possible base clock (fact = 1) that will give a + * divisor strictly less than 512. + */ + fact = 1; + for (ps = 3; ps >= 0; ps--) { + if (speed > ch341_min_rates[ps]) + break; + } + + if (ps < 0) + return -EINVAL; + + /* Determine corresponding divisor, rounding down. */ + clk_div = CH341_CLK_DIV(ps, fact); + div = CH341_CLKRATE / (clk_div * speed); + + /* Some devices require a lower base clock if ps < 3. */ + if (ps < 3 && (p_cdc->ch34x.quirks & CH341_QUIRK_LIMITED_PRESCALER)) + force_fact0 = true; + + /* Halve base clock (fact = 0) if required. */ + if (div < 9 || div > 255 || force_fact0) { + div /= 2; + clk_div *= 2; + fact = 0; + } + + if (div < 2) + return -EINVAL; + + /* + * Pick next divisor if resulting rate is closer to the requested one, + * scale up to avoid rounding errors on low rates. + */ + if (16 * CH341_CLKRATE / (clk_div * div) - 16 * speed >= + 16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1))) + div++; + + /* + * Prefer lower base clock (fact = 0) if even divisor. + * + * Note that this makes the receiver more tolerant to errors. + */ + if (fact == 1 && div % 2 == 0) { + div /= 2; + fact = 0; + } + + return (0x100 - div) << 8 | fact << 2 | ps; +} + +// set baudrate (low level) +// do not confuse with ch34x_set_baudrate +// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c +static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +{ + int val; + + if (!baud_rate) + return -EINVAL; + + val = ch341_get_divisor(p_cdc, baud_rate); + if (val < 0) + return -EINVAL; + + /* + * CH341A buffers data until a full endpoint-size packet (32 bytes) + * has been received unless bit 7 is set. + * + * At least one device with version 0x27 appears to have this bit + * inverted. + */ + if ( p_cdc->ch34x.version > 0x27 ) + val |= BIT(7); + + return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data ); +} + +// set lcr register +// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c +static int32_t ch341_set_lcr ( cdch_interface_t* p_cdc, uint8_t lcr, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +{ + /* + * Chip versions before version 0x30 as read using + * CH341_REQ_READ_VERSION used separate registers for line control + * (stop bits, parity and word length). Version 0x30 and above use + * CH341_REG_LCR only and CH341_REG_LCR2 is always set to zero. + */ + if ( p_cdc->ch34x.version < 0x30 ) + return 0; + + return ch341_write_reg ( p_cdc, CH341_REG_LCR2 << 8 | CH341_REG_LCR, lcr, complete_cb, user_data ); +} + +// set handshake (modem controls) +// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c +static int32_t ch341_set_handshake ( cdch_interface_t* p_cdc, uint8_t control, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +{ + return ch341_control_out ( p_cdc, CH341_REQ_MODEM_CTRL, /* value */ ~control, /* index */ 0, complete_cb, user_data ); +} + +// detect quirks (special versions of CH34x) +// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c +static int32_t ch341_detect_quirks ( tuh_xfer_t* xfer, cdch_interface_t* p_cdc, uint8_t step, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +{ + /* + * A subset of CH34x devices does not support all features. The + * prescaler is limited and there is no support for sending a RS232 + * break condition. A read failure when trying to set up the latter is + * used to detect these devices. + */ + switch ( step ) + { + case 1: + p_cdc->ch34x.quirks = 0; + return ch341_read_reg_request ( p_cdc, CH341_REG_BREAK, buffer, buffersize, complete_cb, user_data ); + break; + case 2: + if ( xfer->result != XFER_RESULT_SUCCESS ) + p_cdc->ch34x.quirks |= CH341_QUIRK_LIMITED_PRESCALER | CH341_QUIRK_SIMULATE_BREAK; + return true; + break; + default: + TU_ASSERT ( false ); // suspicious step + break; + } +} + +// internal control complete to update state such as line state, encoding +// CH34x needs a special interface recovery due to abnormal wIndex usage +static void ch34x_control_complete(tuh_xfer_t* xfer) +{ + uint8_t const itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 ); + uint8_t const idx = tuh_cdc_itf_get_index ( xfer->daddr, itf_num ); + cdch_interface_t *p_cdc = get_itf ( idx ); + TU_ASSERT ( p_cdc, ); + TU_ASSERT ( p_cdc->serial_drid == SERIAL_DRIVER_CH34X, ); // ch34x_control_complete is only used for CH34x + + if (xfer->result == XFER_RESULT_SUCCESS) { + switch (xfer->setup->bRequest) { + case CH341_REQ_WRITE_REG: { // register write request + switch ( tu_le16toh ( xfer->setup->wValue ) ) { + case ( CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER ): { // baudrate write + p_cdc->line_coding.bit_rate = p_cdc->ch34x.baud_rate; + break; + } + default: { + TU_ASSERT(false, ); // unexpected register write + break; + } + } + break; + } + default: { + TU_ASSERT(false, ); // unexpected request + break; + } + } + xfer->complete_cb = p_cdc->user_control_cb; + if (xfer->complete_cb) + xfer->complete_cb(xfer); + } +} + +static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) // do not confuse with ch341_set_baudrate +{ + TU_LOG_DRV("CDC CH34x Set BaudRate = %lu\r\n", baudrate); + uint32_t baud_le = tu_htole32(baudrate); + p_cdc->ch34x.baud_rate = baudrate; + p_cdc->user_control_cb = complete_cb; + return ch341_set_baudrate ( p_cdc, baud_le, complete_cb ? ch34x_control_complete : NULL, user_data ); +} + +static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +{ + TU_LOG_DRV("CDC CH34x Set Control Line State\r\n"); + // todo later + return false; +} + +static void ch34x_process_config ( tuh_xfer_t* xfer ) +{ + uintptr_t const state = xfer->user_data & 0xff; + // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber + uint8_t const itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 ); + uint8_t const idx = tuh_cdc_itf_get_index ( xfer->daddr, itf_num ); + cdch_interface_t *p_cdc = get_itf ( idx ); + uint8_t buffer [ CH34X_BUFFER_SIZE ]; + cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT ( p_cdc, ); + + if ( state == 0 ) { + // defaults + p_cdc->ch34x.baud_rate = DEFAULT_BAUD_RATE; + p_cdc->ch34x.mcr = 0; + p_cdc->ch34x.msr = 0; + p_cdc->ch34x.quirks = 0; + p_cdc->ch34x.version = 0; + /* + * Some CH340 devices appear unable to change the initial LCR + * settings, so set a sane 8N1 default. + */ + p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX | CH341_LCR_CS8; + } + // This process flow has been taken over from Linux driver /drivers/usb/serial/ch341.c + switch ( state ) { + case CONFIG_CH34X_STEP1: // request version read + TU_ASSERT ( ch341_control_in ( p_cdc, /* request */ CH341_REQ_READ_VERSION, /* value */ 0, /* index */ 0, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP2 ), ); + break; + case CONFIG_CH34X_STEP2: // handle version read data, request to init CH34x + p_cdc->ch34x.version = xfer->buffer[0]; + TU_LOG_DRV ( "Chip version=%02x\r\n", p_cdc->ch34x.version ); + TU_ASSERT ( ch341_control_out ( p_cdc, /* request */ CH341_REQ_SERIAL_INIT, /* value */ 0, /* index */ 0, ch34x_process_config, CONFIG_CH34X_STEP3 ), ); + break; + case CONFIG_CH34X_STEP3: // set baudrate with default values (see above) + TU_ASSERT ( ch341_set_baudrate ( p_cdc, p_cdc->ch34x.baud_rate, ch34x_process_config, CONFIG_CH34X_STEP4 ) > 0, ); + break; + case CONFIG_CH34X_STEP4: // set line controls with default values (see above) + TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_STEP5 ) > 0, ); + break; + case CONFIG_CH34X_STEP5: // set handshake RTS/DTR + TU_ASSERT ( ch341_set_handshake ( p_cdc, p_cdc->ch34x.mcr, ch34x_process_config, CONFIG_CH34X_STEP6 ) > 0, ); + break; + case CONFIG_CH34X_STEP6: // detect quirks step 1 + TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 1, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP7 ) > 0, ); + break; + case CONFIG_CH34X_STEP7: // detect quirks step 2 and set baudrate with configured values + TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 2, NULL, 0, NULL, 0 ) > 0, ); +#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + TU_ASSERT ( ch34x_set_baudrate ( p_cdc, line_coding.bit_rate, ch34x_process_config, CONFIG_CH34X_STEP8 ), ); +#else + TU_ATTR_FALLTHROUGH; #endif + break; + case CONFIG_CH34X_STEP8: // set data/stop bit quantities, parity +#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX; + switch ( line_coding.data_bits ) { + case 5: + p_cdc->ch34x.lcr |= CH341_LCR_CS5; + break; + case 6: + p_cdc->ch34x.lcr |= CH341_LCR_CS6; + break; + case 7: + p_cdc->ch34x.lcr |= CH341_LCR_CS7; + break; + case 8: + p_cdc->ch34x.lcr |= CH341_LCR_CS8; + break; + default: + TU_ASSERT ( false, ); // not supported data_bits + p_cdc->ch34x.lcr |= CH341_LCR_CS8; + break; + } + if ( line_coding.parity != CDC_LINE_CODING_PARITY_NONE ) { + p_cdc->ch34x.lcr |= CH341_LCR_ENABLE_PAR; + if ( line_coding.parity == CDC_LINE_CODING_PARITY_EVEN || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE ) + p_cdc->ch34x.lcr |= CH341_LCR_PAR_EVEN; + if ( line_coding.parity == CDC_LINE_CODING_PARITY_MARK || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE ) + p_cdc->ch34x.lcr |= CH341_LCR_MARK_SPACE; + } + TU_ASSERT ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2, ); // not supported 1.5 stop bits + if ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2 ) + p_cdc->ch34x.lcr |= CH341_LCR_STOP_BITS_2; + TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_COMPLETE ) > 0, ); +#else + TU_ATTR_FALLTHROUGH; +#endif + break; + case CONFIG_CH34X_COMPLETE: + set_config_complete ( p_cdc, idx, itf_num ); + break; + default: + TU_ASSERT ( false, ); + break; + } +} + +#endif // CFG_TUH_CDC_CH34X + +#endif // (CFG_TUH_ENABLED && CFG_TUH_CDC) diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h new file mode 100644 index 000000000..94e18b252 --- /dev/null +++ b/src/class/cdc/serial/ch34x.h @@ -0,0 +1,113 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Heiko Kuester (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _CH34X_H_ +#define _CH34X_H_ + +#include + +#define BIT(nr) ( (uint32_t)1 << (nr) ) + +#define CH34X_BUFFER_SIZE 2 + +// The following defines have been taken over from Linux driver /drivers/usb/serial/ch341.c + +#define DEFAULT_BAUD_RATE 9600 + +/* flags for IO-Bits */ +#define CH341_BIT_RTS (1 << 6) +#define CH341_BIT_DTR (1 << 5) + +/******************************/ +/* interrupt pipe definitions */ +/******************************/ +/* always 4 interrupt bytes */ +/* first irq byte normally 0x08 */ +/* second irq byte base 0x7d + below */ +/* third irq byte base 0x94 + below */ +/* fourth irq byte normally 0xee */ + +/* second interrupt byte */ +#define CH341_MULT_STAT 0x04 /* multiple status since last interrupt event */ + +/* status returned in third interrupt answer byte, inverted in data + from irq */ +#define CH341_BIT_CTS 0x01 +#define CH341_BIT_DSR 0x02 +#define CH341_BIT_RI 0x04 +#define CH341_BIT_DCD 0x08 +#define CH341_BITS_MODEM_STAT 0x0f /* all bits */ + +/* Break support - the information used to implement this was gleaned from + * the Net/FreeBSD uchcom.c driver by Takanori Watanabe. Domo arigato. + */ + +// USB requests +#define CH341_REQ_READ_VERSION 0x5F // dec 95 +#define CH341_REQ_WRITE_REG 0x9A +#define CH341_REQ_READ_REG 0x95 +#define CH341_REQ_SERIAL_INIT 0xA1 +#define CH341_REQ_MODEM_CTRL 0xA4 + +// CH34x registers +#define CH341_REG_BREAK 0x05 +#define CH341_REG_PRESCALER 0x12 +#define CH341_REG_DIVISOR 0x13 +#define CH341_REG_LCR 0x18 +#define CH341_REG_LCR2 0x25 + +#define CH341_NBREAK_BITS 0x01 + +// line control bits +#define CH341_LCR_ENABLE_RX 0x80 +#define CH341_LCR_ENABLE_TX 0x40 +#define CH341_LCR_MARK_SPACE 0x20 +#define CH341_LCR_PAR_EVEN 0x10 +#define CH341_LCR_ENABLE_PAR 0x08 +#define CH341_LCR_STOP_BITS_2 0x04 +#define CH341_LCR_CS8 0x03 +#define CH341_LCR_CS7 0x02 +#define CH341_LCR_CS6 0x01 +#define CH341_LCR_CS5 0x00 + +#define CH341_QUIRK_LIMITED_PRESCALER BIT(0) +#define CH341_QUIRK_SIMULATE_BREAK BIT(1) + +#define CH341_CLKRATE 48000000 +#define CH341_CLK_DIV(ps, fact) (1 << (12 - 3 * (ps) - (fact))) +#define CH341_MIN_RATE(ps) (CH341_CLKRATE / (CH341_CLK_DIV((ps), 1) * 512)) + +/* Supported range is 46 to 3000000 bps. */ +#define CH341_MIN_BPS DIV_ROUND_UP(CH341_CLKRATE, CH341_CLK_DIV(0, 0) * 256) +#define CH341_MAX_BPS (CH341_CLKRATE / (CH341_CLK_DIV(3, 0) * 2)) + +#define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP +#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) + +// error codes +#define EINVAL 22 /* Invalid argument */ + +#endif /* _CH34X_H_ */ diff --git a/src/tusb_option.h b/src/tusb_option.h index a76281c0c..13151a07b 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -470,6 +470,23 @@ 0xEA60, 0xEA70 #endif +#ifndef CFG_TUH_CDC_CH34X + // CH34X is not part of CDC class, only to re-use CDC driver API + #define CFG_TUH_CDC_CH34X 0 +#endif + +#ifndef CFG_TUH_CDC_CH34X_VID_PID_LIST + // List of product IDs that can use the CH34X CDC driver + #define CFG_TUH_CDC_CH34X_VID_PID_LIST \ + { 0x1a86, 0x7523 }, /* ch340 chip */ \ + { 0x1a86, 0x7522 }, /* ch340k chip */ \ + { 0x1a86, 0x5523 }, /* ch341 chip */ \ + { 0x1a86, 0xe523 }, /* ch330 chip */ \ + { 0x4348, 0x5523 }, /* ch340 custom chip */ \ + { 0x2184, 0x0057 }, /* overtaken from Linux driver /drivers/usb/serial/ch341.c */ \ + { 0x9986, 0x7523 } /* overtaken from Linux driver /drivers/usb/serial/ch341.c */ +#endif + #ifndef CFG_TUH_HID #define CFG_TUH_HID 0 #endif -- cgit v1.3.1 From 9a1559a35653e34c2fc8b4dccdc9f40ad476913c Mon Sep 17 00:00:00 2001 From: YixingShen Date: Thu, 28 Dec 2023 00:28:24 +0800 Subject: add __ARM_ARCH_8_1M_MAIN__ for M55 --- src/common/tusb_verify.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h index 1b5f53dfc..8aa66b4df 100644 --- a/src/common/tusb_verify.h +++ b/src/common/tusb_verify.h @@ -75,8 +75,8 @@ #define _MESS_FAILED() do {} while (0) #endif -// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33 -#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) +// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55 +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) #define TU_BREAKPOINT() do \ { \ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ -- cgit v1.3.1 From a4aa454a7a21c022569eccfea493b8a96d182d9c Mon Sep 17 00:00:00 2001 From: Ryzee119 Date: Sun, 7 Jan 2024 08:25:31 +1030 Subject: [HUB] Fix double status xfer --- src/host/hub.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/host/hub.c b/src/host/hub.c index 32f5e0ac7..3bac18698 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -435,9 +435,12 @@ static void hub_port_get_status_complete (tuh_xfer_t* xfer) // Other changes are: L1 state // TODO clear change - // prepare for next hub status - // TODO continue with status_change, or maybe we can do it again with status - hub_edpt_status_xfer(daddr); + else + { + // prepare for next hub status + // TODO continue with status_change, or maybe we can do it again with status + hub_edpt_status_xfer(daddr); + } } } -- cgit v1.3.1 From d39d06e6d920aadc9e479d4dfb8620dd3871cb98 Mon Sep 17 00:00:00 2001 From: Ryzee119 Date: Tue, 9 Jan 2024 16:22:54 +1030 Subject: [HUB] Prevent status request to invalid ep_num --- src/host/usbh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 4d30d9f81..53e8a654b 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -456,7 +456,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { #if CFG_TUH_HUB // TODO remove - if ( event.connection.hub_addr != 0) { + if ( event.connection.hub_addr != 0 && event.connection.hub_port != 0) { // done with hub, waiting for next data on status pipe (void) hub_edpt_status_xfer( event.connection.hub_addr ); } -- cgit v1.3.1 From 91f65a36bfb1d4516c39306e77fb15d4e1c2fc0b Mon Sep 17 00:00:00 2001 From: IngHK Date: Tue, 9 Jan 2024 09:53:54 +0100 Subject: [CDC] host: moved acm_open to other acm prototypes --- src/class/cdc/cdc_host.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index a6dfb45ae..b20da3723 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -80,6 +80,7 @@ static cdch_interface_t cdch_data[CFG_TUH_CDC]; //--------------------------------------------------------------------+ //------------- ACM prototypes -------------// +static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); static void acm_process_config(tuh_xfer_t* xfer); static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -605,8 +606,6 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t // Enumeration //--------------------------------------------------------------------+ -static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); - static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const *desc_ep) { for(size_t i=0; i<2; i++) -- cgit v1.3.1 From 0d4b24e56cf11e79b46f88f0d8b8656c0444a149 Mon Sep 17 00:00:00 2001 From: Okarss <104319900+Okarss@users.noreply.github.com> Date: Sun, 7 Jan 2024 20:18:33 +0200 Subject: [STM32 FSDEV] Fix ISR race conditions --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 21cd3da26..5f7944d1f 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -673,13 +673,13 @@ void dcd_int_handler(uint8_t rhport) { /* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */ if(int_status & USB_ISTR_SOF) { - USB->ISTR &=~USB_ISTR_SOF; + USB->ISTR = ~USB_ISTR_SOF; dcd_event_sof(0, USB->FNR & USB_FNR_FN, true); } if(int_status & USB_ISTR_RESET) { // USBRST is start of reset. - USB->ISTR &=~USB_ISTR_RESET; + USB->ISTR = ~USB_ISTR_RESET; dcd_handle_bus_reset(); dcd_event_bus_reset(0, TUSB_SPEED_FULL, true); return; // Don't do the rest of the things here; perhaps they've been cleared? @@ -697,7 +697,7 @@ void dcd_int_handler(uint8_t rhport) { USB->CNTR &= ~USB_CNTR_LPMODE; USB->CNTR &= ~USB_CNTR_FSUSP; - USB->ISTR &=~USB_ISTR_WKUP; + USB->ISTR = ~USB_ISTR_WKUP; dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); } @@ -711,7 +711,7 @@ void dcd_int_handler(uint8_t rhport) { USB->CNTR |= USB_CNTR_LPMODE; /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - USB->ISTR &=~USB_ISTR_SUSP; + USB->ISTR = ~USB_ISTR_SUSP; dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); } @@ -724,7 +724,7 @@ void dcd_int_handler(uint8_t rhport) { { remoteWakeCountdown--; } - USB->ISTR &=~USB_ISTR_ESOF; + USB->ISTR = ~USB_ISTR_ESOF; } } -- cgit v1.3.1 From e7e19f562765999ed76b25b93649e80d9652b088 Mon Sep 17 00:00:00 2001 From: Ryzee119 Date: Sun, 7 Jan 2024 08:30:33 +1030 Subject: [OHCI] Allow more than 16 devices --- src/portable/ohci/ohci.c | 16 +++++++++++++--- src/portable/ohci/ohci.h | 16 +++++++++++++--- 2 files changed, 26 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index f978b0965..c7f4c04ad 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -157,6 +157,7 @@ static ohci_ed_t * const p_ed_head[] = static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed); static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr); +static gtd_extra_data_t *gtd_get_extra_data(ohci_gtd_t const * const gtd); //--------------------------------------------------------------------+ // USBH-HCD API @@ -345,7 +346,7 @@ static void gtd_init(ohci_gtd_t *p_td, uint8_t *data_ptr, uint16_t total_bytes) tu_memclr(p_td, sizeof(ohci_gtd_t)); p_td->used = 1; - p_td->expected_bytes = total_bytes; + gtd_get_extra_data(p_td)->expected_bytes = total_bytes; p_td->buffer_rounding = 1; // less than queued length is not a error p_td->delay_interrupt = OHCI_INT_ON_COMPLETE_NO; @@ -610,6 +611,16 @@ static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd) } } +static gtd_extra_data_t *gtd_get_extra_data(ohci_gtd_t const * const gtd) { + if ( gtd_is_control(gtd) ) + { + return &ohci_data.control[((intptr_t)gtd - (intptr_t)&ohci_data.control->gtd) / sizeof(ohci_data.control[0])].gtd_data; + }else + { + return &ohci_data.gtd_data[gtd - ohci_data.gtd_pool]; + } +} + static inline uint32_t gtd_xfer_byte_left(uint32_t buffer_end, uint32_t current_buffer) { // 5.2.9 OHCI sample code @@ -641,8 +652,7 @@ static void done_queue_isr(uint8_t hostid) if ( (qtd->delay_interrupt == OHCI_INT_ON_COMPLETE_YES) || (event != XFER_RESULT_SUCCESS) ) { ohci_ed_t * const ed = gtd_get_ed(qtd); - - uint32_t const xferred_bytes = qtd->expected_bytes - gtd_xfer_byte_left((uint32_t) qtd->buffer_end, (uint32_t) qtd->current_buffer_pointer); + uint32_t const xferred_bytes = gtd_get_extra_data(qtd)->expected_bytes - gtd_xfer_byte_left((uint32_t) qtd->buffer_end, (uint32_t) qtd->current_buffer_pointer); // NOTE Assuming the current list is BULK and there is no other EDs in the list has queued TDs. // When there is a error resulting this ED is halted, and this EP still has other queued TD diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h index 2081ffabb..cb23396bc 100644 --- a/src/portable/ohci/ohci.h +++ b/src/portable/ohci/ohci.h @@ -45,6 +45,9 @@ enum { #define ED_MAX (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX) #define GTD_MAX ED_MAX +// tinyUSB's OHCI implementation caps number of EDs to 8 bits +TU_VERIFY_STATIC (ED_MAX <= 256, "Reduce CFG_TUH_DEVICE_MAX or CFG_TUH_ENDPOINT_MAX"); + //--------------------------------------------------------------------+ // OHCI Data Structure //--------------------------------------------------------------------+ @@ -70,9 +73,8 @@ typedef struct TU_ATTR_ALIGNED(16) { // Word 0 uint32_t used : 1; - uint32_t index : 4; // endpoint index the td belongs to, or device address in case of control xfer - uint32_t expected_bytes : 13; // TODO available for hcd - + uint32_t index : 8; // endpoint index the gtd belongs to, or device address in case of control xfer + uint32_t : 9; // can be used uint32_t buffer_rounding : 1; uint32_t pid : 2; uint32_t delay_interrupt : 3; @@ -152,6 +154,12 @@ typedef struct TU_ATTR_ALIGNED(32) TU_VERIFY_STATIC( sizeof(ochi_itd_t) == 32, "size is not correct" ); +typedef struct +{ + uint16_t expected_bytes : 13; // can be up to 8192 bytes long so use 13 bits + uint16_t : 3; // can be used +} gtd_extra_data_t; + // structure with member alignment required from large to small typedef struct TU_ATTR_ALIGNED(256) { @@ -164,11 +172,13 @@ typedef struct TU_ATTR_ALIGNED(256) struct { ohci_ed_t ed; ohci_gtd_t gtd; + gtd_extra_data_t gtd_data; }control[CFG_TUH_DEVICE_MAX+CFG_TUH_HUB+1]; // ochi_itd_t itd[OHCI_MAX_ITD]; // itd requires alignment of 32 ohci_ed_t ed_pool[ED_MAX]; ohci_gtd_t gtd_pool[GTD_MAX]; + gtd_extra_data_t gtd_data[GTD_MAX]; // extra data needed by TDs that can't fit in the TD struct volatile uint16_t frame_number_hi; -- cgit v1.3.1 From 3bf6826451536f1afc6eb4e7f088ac65d9b8c707 Mon Sep 17 00:00:00 2001 From: Alex Voinea Date: Wed, 10 Jan 2024 10:27:21 +0100 Subject: Disable ULPI clock during sleep on stm32f7 when using internal phy --- src/portable/synopsys/dwc2/dwc2_stm32.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index dd78ccd06..3237a50f6 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -149,7 +149,7 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { // https://community.st.com/t5/stm32cubemx-mcus/why-stm32h743-usb-fs-doesn-t-work-if-freertos-tickless-idle/m-p/349480#M18867 // H7 running on full-speed phy need to disable ULPI clock in sleep mode. // Otherwise, USB won't work when mcu executing WFI/WFE instruction i.e tick-less RTOS. - // Note: there may be other family that is affected by this, but only H7 is tested so far + // Note: there may be other family that is affected by this, but only H7 and F7 is tested so far #if defined(USB_OTG_FS_PERIPH_BASE) && defined(RCC_AHB1LPENR_USB2OTGFSULPILPEN) if ( USB_OTG_FS_PERIPH_BASE == (uint32_t) dwc2 ) { RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB2OTGFSULPILPEN; @@ -161,6 +161,13 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB1OTGHSULPILPEN; } #endif + + #if defined(USB_OTG_HS_PERIPH_BASE) && defined(RCC_AHB1LPENR_OTGHSULPILPEN) + if ( USB_OTG_HS_PERIPH_BASE == (uint32_t) dwc2 ) { + RCC->AHB1LPENR &= ~RCC_AHB1LPENR_OTGHSULPILPEN; + } + #endif + } else { #if CFG_TUSB_MCU != OPT_MCU_STM32U5 // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable' -- cgit v1.3.1 From 545821399b10243f84509a543ae8c6457e9da803 Mon Sep 17 00:00:00 2001 From: Okarss <104319900+Okarss@users.noreply.github.com> Date: Thu, 11 Jan 2024 00:59:39 +0200 Subject: [STM32 FSDEV] Introduce a typedef for bus access width --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 10 +++++----- src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 3 +++ 2 files changed, 8 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 5f7944d1f..91f90352e 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -673,13 +673,13 @@ void dcd_int_handler(uint8_t rhport) { /* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */ if(int_status & USB_ISTR_SOF) { - USB->ISTR = ~USB_ISTR_SOF; + USB->ISTR = (fsdev_bus_t)~USB_ISTR_SOF; dcd_event_sof(0, USB->FNR & USB_FNR_FN, true); } if(int_status & USB_ISTR_RESET) { // USBRST is start of reset. - USB->ISTR = ~USB_ISTR_RESET; + USB->ISTR = (fsdev_bus_t)~USB_ISTR_RESET; dcd_handle_bus_reset(); dcd_event_bus_reset(0, TUSB_SPEED_FULL, true); return; // Don't do the rest of the things here; perhaps they've been cleared? @@ -697,7 +697,7 @@ void dcd_int_handler(uint8_t rhport) { USB->CNTR &= ~USB_CNTR_LPMODE; USB->CNTR &= ~USB_CNTR_FSUSP; - USB->ISTR = ~USB_ISTR_WKUP; + USB->ISTR = (fsdev_bus_t)~USB_ISTR_WKUP; dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); } @@ -711,7 +711,7 @@ void dcd_int_handler(uint8_t rhport) { USB->CNTR |= USB_CNTR_LPMODE; /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - USB->ISTR = ~USB_ISTR_SUSP; + USB->ISTR = (fsdev_bus_t)~USB_ISTR_SUSP; dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); } @@ -724,7 +724,7 @@ void dcd_int_handler(uint8_t rhport) { { remoteWakeCountdown--; } - USB->ISTR = ~USB_ISTR_ESOF; + USB->ISTR = (fsdev_bus_t)~USB_ISTR_ESOF; } } diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index b71e4f498..d28eb0d9a 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -173,8 +173,11 @@ // For type-safety create a new macro for the volatile address of PMAADDR // The compiler should warn us if we cast it to a non-volatile type? #ifdef PMA_32BIT_ACCESS +typedef uint32_t fsdev_bus_t; static __IO uint32_t * const pma32 = (__IO uint32_t*)USB_PMAADDR; + #else +typedef uint16_t fsdev_bus_t; // Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden) static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR; -- cgit v1.3.1 From c619a861414d2edeb34c5f59b74ed0fe28b39172 Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 11 Jan 2024 08:53:47 +0100 Subject: bInterfaceClass number replaced by define --- src/class/cdc/cdc_host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index b20da3723..79477ef53 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -641,7 +641,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d return acm_open(daddr, itf_desc, max_len); } #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X - else if ( 0xff == itf_desc->bInterfaceClass ) + else if ( TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass ) { uint16_t vid, pid; TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid)); -- cgit v1.3.1 From e68c6658c954d0c5daed2952d500c230b7dfb30d Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 11 Jan 2024 17:35:05 +0700 Subject: move gtd extra out of control struct to save sram also rename gtd_data to gtd_extra --- src/portable/ohci/ohci.c | 13 ++++++------- src/portable/ohci/ohci.h | 18 ++++++++---------- 2 files changed, 14 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index c7f4c04ad..c59d4755e 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -612,12 +612,11 @@ static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd) } static gtd_extra_data_t *gtd_get_extra_data(ohci_gtd_t const * const gtd) { - if ( gtd_is_control(gtd) ) - { - return &ohci_data.control[((intptr_t)gtd - (intptr_t)&ohci_data.control->gtd) / sizeof(ohci_data.control[0])].gtd_data; - }else - { - return &ohci_data.gtd_data[gtd - ohci_data.gtd_pool]; + if ( gtd_is_control(gtd) ) { + uint8_t idx = ((uintptr_t)gtd - (uintptr_t)&ohci_data.control->gtd) / sizeof(ohci_data.control[0]); + return &ohci_data.gtd_extra_control[idx]; + }else { + return &ohci_data.gtd_extra[gtd - ohci_data.gtd_pool]; } } @@ -661,7 +660,7 @@ static void done_queue_isr(uint8_t hostid) // --> HC will not process Control list (due to service ratio when Bulk list not empty) // To walk-around this, the halted ED will have TailP = HeadP (empty list condition), when clearing halt // the TailP must be set back to NULL for processing remaining TDs - if ((event != XFER_RESULT_SUCCESS)) + if (event != XFER_RESULT_SUCCESS) { ed->td_tail &= 0x0Ful; ed->td_tail |= tu_align16(ed->td_head.address); // mark halted EP as empty queue diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h index cb23396bc..4feefd771 100644 --- a/src/portable/ohci/ohci.h +++ b/src/portable/ohci/ohci.h @@ -154,15 +154,12 @@ typedef struct TU_ATTR_ALIGNED(32) TU_VERIFY_STATIC( sizeof(ochi_itd_t) == 32, "size is not correct" ); -typedef struct -{ - uint16_t expected_bytes : 13; // can be up to 8192 bytes long so use 13 bits - uint16_t : 3; // can be used +typedef struct { + uint16_t expected_bytes; // up to 8192 bytes so max is 13 bits } gtd_extra_data_t; // structure with member alignment required from large to small -typedef struct TU_ATTR_ALIGNED(256) -{ +typedef struct TU_ATTR_ALIGNED(256) { ohci_hcca_t hcca; ohci_ed_t bulk_head_ed; // static bulk head (dummy) @@ -172,16 +169,17 @@ typedef struct TU_ATTR_ALIGNED(256) struct { ohci_ed_t ed; ohci_gtd_t gtd; - gtd_extra_data_t gtd_data; - }control[CFG_TUH_DEVICE_MAX+CFG_TUH_HUB+1]; + } control[CFG_TUH_DEVICE_MAX + CFG_TUH_HUB + 1]; // ochi_itd_t itd[OHCI_MAX_ITD]; // itd requires alignment of 32 ohci_ed_t ed_pool[ED_MAX]; ohci_gtd_t gtd_pool[GTD_MAX]; - gtd_extra_data_t gtd_data[GTD_MAX]; // extra data needed by TDs that can't fit in the TD struct - volatile uint16_t frame_number_hi; + // extra data needed by TDs that can't fit in the TD struct + gtd_extra_data_t gtd_extra_control[CFG_TUH_DEVICE_MAX + CFG_TUH_HUB + 1]; + gtd_extra_data_t gtd_extra[GTD_MAX]; + volatile uint16_t frame_number_hi; } ohci_data_t; //--------------------------------------------------------------------+ -- cgit v1.3.1 From 2d3d14891251baedfc965810c650615bdee128cf Mon Sep 17 00:00:00 2001 From: Okarss <104319900+Okarss@users.noreply.github.com> Date: Thu, 11 Jan 2024 21:02:14 +0200 Subject: [STM32 FSDEV] Align names for consistency --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 30 +++++----- .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 65 +++++++++++----------- 2 files changed, 48 insertions(+), 47 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 91f90352e..9c37f1f98 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -128,8 +128,8 @@ # define DCD_STM32_BTABLE_BASE 0U #endif -#ifndef DCD_STM32_BTABLE_LENGTH -# define DCD_STM32_BTABLE_LENGTH (PMA_LENGTH - DCD_STM32_BTABLE_BASE) +#ifndef DCD_STM32_BTABLE_SIZE +# define DCD_STM32_BTABLE_SIZE (FSDEV_PMA_SIZE - DCD_STM32_BTABLE_BASE) #endif /*************************************************** @@ -137,7 +137,7 @@ */ TU_VERIFY_STATIC((MAX_EP_COUNT) <= STFSDEV_EP_COUNT, "Only 8 endpoints supported on the hardware"); -TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))<=(PMA_LENGTH), "BTABLE does not fit in PMA RAM"); +TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_SIZE)) <= (FSDEV_PMA_SIZE), "BTABLE does not fit in PMA RAM"); TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligned to 8 bytes"); //--------------------------------------------------------------------+ @@ -559,7 +559,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) // Must reset EP to NAK (in case it had been stalling) (though, maybe too late here) pcd_set_ep_rx_status(USB,0u,USB_EP_RX_NAK); pcd_set_ep_tx_status(USB,0u,USB_EP_TX_NAK); -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT dcd_event_setup_received(0, (uint8_t*)(USB_PMAADDR + pcd_get_ep_rx_address(USB, EPindex)), true); #else // The setup_received function uses memcpy, so this must first copy the setup data into @@ -786,7 +786,7 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length) } // Ensure allocated buffer is aligned -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT length = (length + 3) & ~0x03; #else length = (length + 1) & ~0x01; @@ -798,7 +798,7 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length) ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer // Verify no overflow - TU_ASSERT(ep_buf_ptr <= PMA_LENGTH, 0xFFFF); + TU_ASSERT(ep_buf_ptr <= FSDEV_PMA_SIZE, 0xFFFF); epXferCtl->pma_ptr = addr; epXferCtl->pma_alloc_size = length; @@ -1227,7 +1227,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) } } -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes) { const uint8_t* srcVal = src; @@ -1283,7 +1283,7 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, ui __IO uint16_t *pdwVal; srcVal = src; - pdwVal = &pma[PMA_STRIDE*(dst>>1)]; + pdwVal = &pma[FSDEV_PMA_STRIDE * (dst >> 1)]; while (n--) { @@ -1291,7 +1291,7 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, ui srcVal++; temp2 = temp1 | ((uint16_t)(((uint16_t)(*srcVal)) << 8U)) ; *pdwVal = temp2; - pdwVal += PMA_STRIDE; + pdwVal += FSDEV_PMA_STRIDE; srcVal++; } @@ -1323,7 +1323,7 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN // We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part, // last lin byte will be combined with wrapped part // To ensure PMA is always access aligned (dst aligned to 16 or 32 bit) -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT if((cnt_lin & 0x03) && cnt_wrap) { // Copy first linear part @@ -1386,7 +1386,7 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN return true; } -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes) { uint8_t* dstVal = dst; @@ -1434,13 +1434,13 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t __IO const uint16_t *pdwVal; uint32_t temp; - pdwVal = &pma[PMA_STRIDE*(src>>1)]; + pdwVal = &pma[FSDEV_PMA_STRIDE * (src >> 1)]; uint8_t *dstVal = (uint8_t*)dst; while (n--) { temp = *pdwVal; - pdwVal += PMA_STRIDE; + pdwVal += FSDEV_PMA_STRIDE; *dstVal++ = ((temp >> 0) & 0xFF); *dstVal++ = ((temp >> 8) & 0xFF); } @@ -1448,7 +1448,7 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t if (wNBytes & 0x01) { temp = *pdwVal; - pdwVal += PMA_STRIDE; + pdwVal += FSDEV_PMA_STRIDE; *dstVal++ = ((temp >> 0) & 0xFF); } return true; @@ -1475,7 +1475,7 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB // We want to read from PMA and write it into the FIFO, if LIN part is ODD and has WRAPPED part, // last lin byte will be combined with wrapped part // To ensure PMA is always access aligned (src aligned to 16 or 32 bit) -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT if((cnt_lin & 0x03) && cnt_wrap) { // Copy first linear part diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index d28eb0d9a..3f4db985d 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -28,7 +28,7 @@ // This file contains source copied from ST's HAL, and thus should have their copyright statement. -// PMA_LENGTH is PMA buffer size in bytes. +// FSDEV_PMA_SIZE is PMA buffer size in bytes. // On 512-byte devices, access with a stride of two words (use every other 16-bit address) // On 1024-byte devices, access with a stride of one word (use every 16-bit address) @@ -37,7 +37,7 @@ #if CFG_TUSB_MCU == OPT_MCU_STM32F0 #include "stm32f0xx.h" - #define PMA_LENGTH (1024u) + #define FSDEV_PMA_SIZE (1024u) // F0x2 models are crystal-less // All have internal D+ pull-up // 070RB: 2 x 16 bits/word memory LPM Support, BCD Support @@ -45,7 +45,7 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32F1 #include "stm32f1xx.h" - #define PMA_LENGTH (512u) + #define FSDEV_PMA_SIZE (512u) // NO internal Pull-ups // *B, and *C: 2 x 16 bits/word @@ -56,7 +56,7 @@ defined(STM32F303xB) || defined(STM32F303xC) || \ defined(STM32F373xC) #include "stm32f3xx.h" - #define PMA_LENGTH (512u) + #define FSDEV_PMA_SIZE (512u) // NO internal Pull-ups // *B, and *C: 1 x 16 bits/word // PMA dedicated to USB (no sharing with CAN) @@ -65,27 +65,27 @@ defined(STM32F302xD) || defined(STM32F302xE) || \ defined(STM32F303xD) || defined(STM32F303xE) #include "stm32f3xx.h" - #define PMA_LENGTH (1024u) + #define FSDEV_PMA_SIZE (1024u) // NO internal Pull-ups // *6, *8, *D, and *E: 2 x 16 bits/word LPM Support // When CAN clock is enabled, USB can use first 768 bytes ONLY. #elif CFG_TUSB_MCU == OPT_MCU_STM32L0 #include "stm32l0xx.h" - #define PMA_LENGTH (1024u) + #define FSDEV_PMA_SIZE (1024u) #elif CFG_TUSB_MCU == OPT_MCU_STM32L1 #include "stm32l1xx.h" - #define PMA_LENGTH (512u) + #define FSDEV_PMA_SIZE (512u) #elif CFG_TUSB_MCU == OPT_MCU_STM32G4 #include "stm32g4xx.h" - #define PMA_LENGTH (1024u) + #define FSDEV_PMA_SIZE (1024u) #elif CFG_TUSB_MCU == OPT_MCU_STM32G0 #include "stm32g0xx.h" - #define PMA_32BIT_ACCESS - #define PMA_LENGTH (2048u) + #define FSDEV_BUS_32BIT + #define FSDEV_PMA_SIZE (2048u) #undef USB_PMAADDR #define USB_PMAADDR USB_DRD_PMAADDR #define USB_TypeDef USB_DRD_TypeDef @@ -112,8 +112,8 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32H5 #include "stm32h5xx.h" - #define PMA_32BIT_ACCESS - #define PMA_LENGTH (2048u) + #define FSDEV_BUS_32BIT + #define FSDEV_PMA_SIZE (2048u) #undef USB_PMAADDR #define USB_PMAADDR USB_DRD_PMAADDR #define USB_TypeDef USB_DRD_TypeDef @@ -141,18 +141,18 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32WB #include "stm32wbxx.h" - #define PMA_LENGTH (1024u) + #define FSDEV_PMA_SIZE (1024u) /* ST provided header has incorrect value */ #undef USB_PMAADDR #define USB_PMAADDR USB1_PMAADDR #elif CFG_TUSB_MCU == OPT_MCU_STM32L4 #include "stm32l4xx.h" - #define PMA_LENGTH (1024u) + #define FSDEV_PMA_SIZE (1024u) #elif CFG_TUSB_MCU == OPT_MCU_STM32L5 #include "stm32l5xx.h" - #define PMA_LENGTH (1024u) + #define FSDEV_PMA_SIZE (1024u) #ifndef USB_PMAADDR #define USB_PMAADDR (USB_BASE + (USB_PMAADDR_NS - USB_BASE_NS)) @@ -164,15 +164,16 @@ #endif // For purposes of accessing the packet -#if ((PMA_LENGTH) == 512u) - #define PMA_STRIDE (2u) -#elif ((PMA_LENGTH) == 1024u) - #define PMA_STRIDE (1u) +#if ((FSDEV_PMA_SIZE) == 512u) + #define FSDEV_PMA_STRIDE (2u) +#elif ((FSDEV_PMA_SIZE) == 1024u) + #define FSDEV_PMA_STRIDE (1u) #endif +// The fsdev_bus_t type can be used for both register and PMA access necessities // For type-safety create a new macro for the volatile address of PMAADDR // The compiler should warn us if we cast it to a non-volatile type? -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT typedef uint32_t fsdev_bus_t; static __IO uint32_t * const pma32 = (__IO uint32_t*)USB_PMAADDR; @@ -184,7 +185,7 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR; TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) { size_t total_word_offset = (((USBx)->BTABLE)>>1) + x; - total_word_offset *= PMA_STRIDE; + total_word_offset *= FSDEV_PMA_STRIDE; return &(pma[total_word_offset]); } @@ -215,7 +216,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t si /* SetENDPOINT */ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue) { -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT (void) USBx; __O uint32_t *reg = (__O uint32_t *)(USB_DRD_BASE + bEpIdx*4); *reg = wRegValue; @@ -227,7 +228,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, ui /* GetENDPOINT */ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) { -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT (void) USBx; __I uint32_t *reg = (__I uint32_t *)(USB_DRD_BASE + bEpIdx*4); #else @@ -282,7 +283,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, */ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) { -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT (void) USBx; return (pma32[2*bEpIdx] & 0x03FF0000) >> 16; #else @@ -293,7 +294,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USB TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) { -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT (void) USBx; return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16; #else @@ -320,7 +321,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx, TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx) { -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT (void) USBx; return pma32[2*bEpIdx] & 0x0000FFFFu ; #else @@ -330,7 +331,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx) { -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT (void) USBx; return pma32[2*bEpIdx + 1] & 0x0000FFFFu; #else @@ -340,7 +341,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) { -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT (void) USBx; pma32[2*bEpIdx] = (pma32[2*bEpIdx] & 0xFFFF0000u) | (addr & 0x0000FFFCu); #else @@ -350,7 +351,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USB TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) { -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT (void) USBx; pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & 0xFFFF0000u) | (addr & 0x0000FFFCu); #else @@ -360,7 +361,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USB TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT (void) USBx; pma32[2*bEpIdx] = (pma32[2*bEpIdx] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16); #else @@ -371,7 +372,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, u TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT (void) USBx; pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16); #else @@ -383,7 +384,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, u TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t blocksize, uint32_t numblocks) { /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */ -#ifdef PMA_32BIT_ACCESS +#ifdef FSDEV_BUS_32BIT (void) USBx; pma32[rxtx_idx] = (pma32[rxtx_idx] & 0x0000FFFFu) | (blocksize << 31) | ((numblocks - blocksize) << 26); #else -- cgit v1.3.1 From 290f4bea91e739979217eb91d589a75f9ac0f6a7 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 12 Jan 2024 15:47:08 +0700 Subject: - change tuh_event_hook_cb, tud_event_hook_cb to weak default implementation - change code style --- src/device/usbd.c | 362 +++++++++++++++++++++++----------------------- src/device/usbd.h | 2 +- src/device/usbd_control.c | 33 ++--- src/host/usbh.c | 126 ++++++++-------- src/host/usbh.h | 2 +- 5 files changed, 255 insertions(+), 270 deletions(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index 59466b42e..5c94ebcc5 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -38,11 +38,19 @@ //--------------------------------------------------------------------+ // USBD Configuration //--------------------------------------------------------------------+ - #ifndef CFG_TUD_TASK_QUEUE_SZ #define CFG_TUD_TASK_QUEUE_SZ 16 #endif +//--------------------------------------------------------------------+ +// Callback weak stubs (called if application does not provide) +//--------------------------------------------------------------------+ +TU_ATTR_WEAK void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) { + (void)rhport; + (void)eventid; + (void)in_isr; +} + //--------------------------------------------------------------------+ // Device Data //--------------------------------------------------------------------+ @@ -50,10 +58,8 @@ // Invalid driver ID in itf2drv[] ep2drv[][] mapping enum { DRVID_INVALID = 0xFFu }; -typedef struct -{ - struct TU_ATTR_PACKED - { +typedef struct { + struct TU_ATTR_PACKED { volatile uint8_t connected : 1; volatile uint8_t addressed : 1; volatile uint8_t suspended : 1; @@ -85,151 +91,150 @@ tu_static usbd_device_t _usbd_dev; #endif // Built-in class drivers -tu_static usbd_class_driver_t const _usbd_driver[] = -{ - #if CFG_TUD_CDC - { - DRIVER_NAME("CDC") - .init = cdcd_init, - .reset = cdcd_reset, - .open = cdcd_open, - .control_xfer_cb = cdcd_control_xfer_cb, - .xfer_cb = cdcd_xfer_cb, - .sof = NULL - }, - #endif - - #if CFG_TUD_MSC - { - DRIVER_NAME("MSC") - .init = mscd_init, - .reset = mscd_reset, - .open = mscd_open, - .control_xfer_cb = mscd_control_xfer_cb, - .xfer_cb = mscd_xfer_cb, - .sof = NULL - }, - #endif - - #if CFG_TUD_HID - { - DRIVER_NAME("HID") - .init = hidd_init, - .reset = hidd_reset, - .open = hidd_open, - .control_xfer_cb = hidd_control_xfer_cb, - .xfer_cb = hidd_xfer_cb, - .sof = NULL - }, - #endif - - #if CFG_TUD_AUDIO - { - DRIVER_NAME("AUDIO") - .init = audiod_init, - .reset = audiod_reset, - .open = audiod_open, - .control_xfer_cb = audiod_control_xfer_cb, - .xfer_cb = audiod_xfer_cb, - .sof = audiod_sof_isr - }, - #endif - - #if CFG_TUD_VIDEO - { - DRIVER_NAME("VIDEO") - .init = videod_init, - .reset = videod_reset, - .open = videod_open, - .control_xfer_cb = videod_control_xfer_cb, - .xfer_cb = videod_xfer_cb, - .sof = NULL - }, - #endif - - #if CFG_TUD_MIDI - { - DRIVER_NAME("MIDI") - .init = midid_init, - .open = midid_open, - .reset = midid_reset, - .control_xfer_cb = midid_control_xfer_cb, - .xfer_cb = midid_xfer_cb, - .sof = NULL - }, - #endif - - #if CFG_TUD_VENDOR - { - DRIVER_NAME("VENDOR") - .init = vendord_init, - .reset = vendord_reset, - .open = vendord_open, - .control_xfer_cb = tud_vendor_control_xfer_cb, - .xfer_cb = vendord_xfer_cb, - .sof = NULL - }, - #endif - - #if CFG_TUD_USBTMC - { - DRIVER_NAME("TMC") - .init = usbtmcd_init_cb, - .reset = usbtmcd_reset_cb, - .open = usbtmcd_open_cb, - .control_xfer_cb = usbtmcd_control_xfer_cb, - .xfer_cb = usbtmcd_xfer_cb, - .sof = NULL - }, - #endif - - #if CFG_TUD_DFU_RUNTIME - { - DRIVER_NAME("DFU-RUNTIME") - .init = dfu_rtd_init, - .reset = dfu_rtd_reset, - .open = dfu_rtd_open, - .control_xfer_cb = dfu_rtd_control_xfer_cb, - .xfer_cb = NULL, - .sof = NULL - }, - #endif - - #if CFG_TUD_DFU - { - DRIVER_NAME("DFU") - .init = dfu_moded_init, - .reset = dfu_moded_reset, - .open = dfu_moded_open, - .control_xfer_cb = dfu_moded_control_xfer_cb, - .xfer_cb = NULL, - .sof = NULL - }, - #endif - - #if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM - { - DRIVER_NAME("NET") - .init = netd_init, - .reset = netd_reset, - .open = netd_open, - .control_xfer_cb = netd_control_xfer_cb, - .xfer_cb = netd_xfer_cb, - .sof = NULL, - }, - #endif - - #if CFG_TUD_BTH - { - DRIVER_NAME("BTH") - .init = btd_init, - .reset = btd_reset, - .open = btd_open, - .control_xfer_cb = btd_control_xfer_cb, - .xfer_cb = btd_xfer_cb, - .sof = NULL - }, - #endif +tu_static usbd_class_driver_t const _usbd_driver[] = { + #if CFG_TUD_CDC + { + DRIVER_NAME("CDC") + .init = cdcd_init, + .reset = cdcd_reset, + .open = cdcd_open, + .control_xfer_cb = cdcd_control_xfer_cb, + .xfer_cb = cdcd_xfer_cb, + .sof = NULL + }, + #endif + + #if CFG_TUD_MSC + { + DRIVER_NAME("MSC") + .init = mscd_init, + .reset = mscd_reset, + .open = mscd_open, + .control_xfer_cb = mscd_control_xfer_cb, + .xfer_cb = mscd_xfer_cb, + .sof = NULL + }, + #endif + + #if CFG_TUD_HID + { + DRIVER_NAME("HID") + .init = hidd_init, + .reset = hidd_reset, + .open = hidd_open, + .control_xfer_cb = hidd_control_xfer_cb, + .xfer_cb = hidd_xfer_cb, + .sof = NULL + }, + #endif + + #if CFG_TUD_AUDIO + { + DRIVER_NAME("AUDIO") + .init = audiod_init, + .reset = audiod_reset, + .open = audiod_open, + .control_xfer_cb = audiod_control_xfer_cb, + .xfer_cb = audiod_xfer_cb, + .sof = audiod_sof_isr + }, + #endif + + #if CFG_TUD_VIDEO + { + DRIVER_NAME("VIDEO") + .init = videod_init, + .reset = videod_reset, + .open = videod_open, + .control_xfer_cb = videod_control_xfer_cb, + .xfer_cb = videod_xfer_cb, + .sof = NULL + }, + #endif + + #if CFG_TUD_MIDI + { + DRIVER_NAME("MIDI") + .init = midid_init, + .open = midid_open, + .reset = midid_reset, + .control_xfer_cb = midid_control_xfer_cb, + .xfer_cb = midid_xfer_cb, + .sof = NULL + }, + #endif + + #if CFG_TUD_VENDOR + { + DRIVER_NAME("VENDOR") + .init = vendord_init, + .reset = vendord_reset, + .open = vendord_open, + .control_xfer_cb = tud_vendor_control_xfer_cb, + .xfer_cb = vendord_xfer_cb, + .sof = NULL + }, + #endif + + #if CFG_TUD_USBTMC + { + DRIVER_NAME("TMC") + .init = usbtmcd_init_cb, + .reset = usbtmcd_reset_cb, + .open = usbtmcd_open_cb, + .control_xfer_cb = usbtmcd_control_xfer_cb, + .xfer_cb = usbtmcd_xfer_cb, + .sof = NULL + }, + #endif + + #if CFG_TUD_DFU_RUNTIME + { + DRIVER_NAME("DFU-RUNTIME") + .init = dfu_rtd_init, + .reset = dfu_rtd_reset, + .open = dfu_rtd_open, + .control_xfer_cb = dfu_rtd_control_xfer_cb, + .xfer_cb = NULL, + .sof = NULL + }, + #endif + + #if CFG_TUD_DFU + { + DRIVER_NAME("DFU") + .init = dfu_moded_init, + .reset = dfu_moded_reset, + .open = dfu_moded_open, + .control_xfer_cb = dfu_moded_control_xfer_cb, + .xfer_cb = NULL, + .sof = NULL + }, + #endif + + #if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM + { + DRIVER_NAME("NET") + .init = netd_init, + .reset = netd_reset, + .open = netd_open, + .control_xfer_cb = netd_control_xfer_cb, + .xfer_cb = netd_xfer_cb, + .sof = NULL, + }, + #endif + + #if CFG_TUD_BTH + { + DRIVER_NAME("BTH") + .init = btd_init, + .reset = btd_reset, + .open = btd_open, + .control_xfer_cb = btd_control_xfer_cb, + .xfer_cb = btd_xfer_cb, + .sof = NULL + }, + #endif }; enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) }; @@ -275,7 +280,7 @@ tu_static osal_queue_t _usbd_q; TU_ATTR_ALWAYS_INLINE static inline bool queue_event(dcd_event_t const * event, bool in_isr) { bool ret = osal_queue_send(_usbd_q, event, in_isr); - if (tud_event_hook_cb) tud_event_hook_cb(event->rhport, event->event_id, in_isr); + tud_event_hook_cb(event->rhport, event->event_id, in_isr); return ret; } @@ -297,27 +302,23 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, // Debug //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL -tu_static char const* const _usbd_event_str[DCD_EVENT_COUNT] = -{ - "Invalid" , - "Bus Reset" , - "Unplugged" , - "SOF" , - "Suspend" , - "Resume" , - "Setup Received" , - "Xfer Complete" , - "Func Call" +tu_static char const* const _usbd_event_str[DCD_EVENT_COUNT] = { + "Invalid", + "Bus Reset", + "Unplugged", + "SOF", + "Suspend", + "Resume", + "Setup Received", + "Xfer Complete", + "Func Call" }; // for usbd_control to print the name of control complete driver -void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback) -{ - for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) - { - usbd_class_driver_t const * driver = get_driver(i); - if ( driver && driver->control_xfer_cb == callback ) - { +void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback) { + for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) { + usbd_class_driver_t const* driver = get_driver(i); + if (driver && driver->control_xfer_cb == callback) { TU_LOG_USBD(" %s control complete\r\n", driver->name); return; } @@ -329,43 +330,36 @@ void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback) //--------------------------------------------------------------------+ // Application API //--------------------------------------------------------------------+ -tusb_speed_t tud_speed_get(void) -{ +tusb_speed_t tud_speed_get(void) { return (tusb_speed_t) _usbd_dev.speed; } -bool tud_connected(void) -{ +bool tud_connected(void) { return _usbd_dev.connected; } -bool tud_mounted(void) -{ +bool tud_mounted(void) { return _usbd_dev.cfg_num ? true : false; } -bool tud_suspended(void) -{ +bool tud_suspended(void) { return _usbd_dev.suspended; } -bool tud_remote_wakeup(void) -{ +bool tud_remote_wakeup(void) { // only wake up host if this feature is supported and enabled and we are suspended - TU_VERIFY (_usbd_dev.suspended && _usbd_dev.remote_wakeup_support && _usbd_dev.remote_wakeup_en ); + TU_VERIFY (_usbd_dev.suspended && _usbd_dev.remote_wakeup_support && _usbd_dev.remote_wakeup_en); dcd_remote_wakeup(_usbd_rhport); return true; } -bool tud_disconnect(void) -{ +bool tud_disconnect(void) { TU_VERIFY(dcd_disconnect); dcd_disconnect(_usbd_rhport); return true; } -bool tud_connect(void) -{ +bool tud_connect(void) { TU_VERIFY(dcd_connect); dcd_connect(_usbd_rhport); return true; diff --git a/src/device/usbd.h b/src/device/usbd.h index 5456148bf..3ab6c813f 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -147,7 +147,7 @@ TU_ATTR_WEAK void tud_suspend_cb(bool remote_wakeup_en); TU_ATTR_WEAK void tud_resume_cb(void); // Invoked when there is a new usb event, which need to be processed by tud_task()/tud_task_ext() -TU_ATTR_WEAK void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr); +void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr); // Invoked when received control request with VENDOR TYPE TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request); diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index a6081060e..ea18b28da 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -32,24 +32,32 @@ #include "tusb.h" #include "device/usbd_pvt.h" +//--------------------------------------------------------------------+ +// Callback weak stubs (called if application does not provide) +//--------------------------------------------------------------------+ +TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) { + (void)rhport; + (void)request; +} + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF +//--------------------------------------------------------------------+ + #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback); #endif -enum -{ +enum { EDPT_CTRL_OUT = 0x00, EDPT_CTRL_IN = 0x80 }; -typedef struct -{ +typedef struct { tusb_control_request_t request; - uint8_t* buffer; uint16_t data_len; uint16_t total_xferred; - usbd_control_xfer_cb_t complete_cb; } usbd_control_xfer_t; @@ -134,23 +142,12 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo //--------------------------------------------------------------------+ // USBD API //--------------------------------------------------------------------+ - -TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) -{ - (void)rhport; - (void)request; - - // this is the default implementation that is called when no "real" implementation - // of the function exists -} - void usbd_control_reset(void); void usbd_control_set_request(tusb_control_request_t const *request); void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp ); bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes); -void usbd_control_reset(void) -{ +void usbd_control_reset(void) { tu_varclr(&_ctrl_xfer); } diff --git a/src/host/usbh.c b/src/host/usbh.c index 53e8a654b..dfe6ddb42 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -36,7 +36,6 @@ //--------------------------------------------------------------------+ // USBH Configuration //--------------------------------------------------------------------+ - #ifndef CFG_TUH_TASK_QUEUE_SZ #define CFG_TUH_TASK_QUEUE_SZ 16 #endif @@ -46,11 +45,18 @@ #endif //--------------------------------------------------------------------+ -// USBH-HCD common data structure +// Callback weak stubs (called if application does not provide) //--------------------------------------------------------------------+ +TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) { + (void) rhport; + (void) eventid; + (void) in_isr; +} -typedef struct -{ +//--------------------------------------------------------------------+ +// USBH-HCD common data structure +//--------------------------------------------------------------------+ +typedef struct { // port uint8_t rhport; uint8_t hub_addr; @@ -112,60 +118,58 @@ typedef struct { //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ - #if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL #define DRIVER_NAME(_name) .name = _name, #else #define DRIVER_NAME(_name) #endif -static usbh_class_driver_t const usbh_class_drivers[] = -{ - #if CFG_TUH_CDC +static usbh_class_driver_t const usbh_class_drivers[] = { + #if CFG_TUH_CDC { - DRIVER_NAME("CDC") - .init = cdch_init, - .open = cdch_open, - .set_config = cdch_set_config, - .xfer_cb = cdch_xfer_cb, - .close = cdch_close + DRIVER_NAME("CDC") + .init = cdch_init, + .open = cdch_open, + .set_config = cdch_set_config, + .xfer_cb = cdch_xfer_cb, + .close = cdch_close }, - #endif + #endif - #if CFG_TUH_MSC + #if CFG_TUH_MSC { - DRIVER_NAME("MSC") - .init = msch_init, - .open = msch_open, - .set_config = msch_set_config, - .xfer_cb = msch_xfer_cb, - .close = msch_close + DRIVER_NAME("MSC") + .init = msch_init, + .open = msch_open, + .set_config = msch_set_config, + .xfer_cb = msch_xfer_cb, + .close = msch_close }, - #endif + #endif - #if CFG_TUH_HID + #if CFG_TUH_HID { - DRIVER_NAME("HID") - .init = hidh_init, - .open = hidh_open, - .set_config = hidh_set_config, - .xfer_cb = hidh_xfer_cb, - .close = hidh_close + DRIVER_NAME("HID") + .init = hidh_init, + .open = hidh_open, + .set_config = hidh_set_config, + .xfer_cb = hidh_xfer_cb, + .close = hidh_close }, - #endif + #endif - #if CFG_TUH_HUB + #if CFG_TUH_HUB { - DRIVER_NAME("HUB") - .init = hub_init, - .open = hub_open, - .set_config = hub_set_config, - .xfer_cb = hub_xfer_cb, - .close = hub_close + DRIVER_NAME("HUB") + .init = hub_init, + .open = hub_open, + .set_config = hub_set_config, + .xfer_cb = hub_xfer_cb, + .close = hub_close }, - #endif + #endif - #if CFG_TUH_VENDOR + #if CFG_TUH_VENDOR { DRIVER_NAME("VENDOR") .init = cush_init, @@ -173,7 +177,7 @@ static usbh_class_driver_t const usbh_class_drivers[] = .xfer_cb = cush_isr, .close = cush_close } - #endif + #endif }; enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) }; @@ -233,8 +237,7 @@ static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE]; // Control transfers: since most controllers do not support multiple control transfers // on multiple devices concurrently and control transfers are not used much except for // enumeration, we will only execute control transfers one at a time. -CFG_TUH_MEM_SECTION struct -{ +CFG_TUH_MEM_SECTION struct { CFG_TUH_MEM_ALIGN tusb_control_request_t request; uint8_t* buffer; tuh_xfer_cb_t complete_cb; @@ -268,7 +271,7 @@ TU_ATTR_WEAK void osal_task_delay(uint32_t msec) { TU_ATTR_ALWAYS_INLINE static inline bool queue_event(hcd_event_t const * event, bool in_isr) { bool ret = osal_queue_send(_usbh_q, event, in_isr); - if (tuh_event_hook_cb) tuh_event_hook_cb(event->rhport, event->event_id, in_isr); + tuh_event_hook_cb(event->rhport, event->event_id, in_isr); return ret; } @@ -367,17 +370,14 @@ bool tuh_init(uint8_t controller_id) { tu_memclr(_usbh_devices, sizeof(_usbh_devices)); tu_memclr(&_ctrl_xfer, sizeof(_ctrl_xfer)); - for(uint8_t i=0; iname); driver->init(); } @@ -545,8 +545,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { // Control transfer //--------------------------------------------------------------------+ -static void _control_blocking_complete_cb(tuh_xfer_t* xfer) -{ +static void _control_blocking_complete_cb(tuh_xfer_t* xfer) { // update result *((xfer_result_t*) xfer->user_data) = xfer->result; } @@ -625,21 +624,18 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { return true; } -TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage) -{ +TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage) { (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); _ctrl_xfer.stage = stage; (void) osal_mutex_unlock(_usbh_mutex); } -static void _xfer_complete(uint8_t daddr, xfer_result_t result) -{ +static void _xfer_complete(uint8_t daddr, xfer_result_t result) { TU_LOG_USBH("\r\n"); // duplicate xfer since user can execute control transfer within callback tusb_control_request_t const request = _ctrl_xfer.request; - tuh_xfer_t xfer_temp = - { + tuh_xfer_t xfer_temp = { .daddr = daddr, .ep_addr = 0, .result = result, @@ -652,8 +648,7 @@ static void _xfer_complete(uint8_t daddr, xfer_result_t result) _set_control_xfer_stage(CONTROL_STAGE_IDLE); - if (xfer_temp.complete_cb) - { + if (xfer_temp.complete_cb) { xfer_temp.complete_cb(&xfer_temp); } } @@ -710,17 +705,16 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result // //--------------------------------------------------------------------+ -bool tuh_edpt_xfer(tuh_xfer_t* xfer) -{ - uint8_t const daddr = xfer->daddr; +bool tuh_edpt_xfer(tuh_xfer_t* xfer) { + uint8_t const daddr = xfer->daddr; uint8_t const ep_addr = xfer->ep_addr; TU_VERIFY(daddr && ep_addr); TU_VERIFY(usbh_edpt_claim(daddr, ep_addr)); - if ( !usbh_edpt_xfer_with_callback(daddr, ep_addr, xfer->buffer, (uint16_t) xfer->buflen, xfer->complete_cb, xfer->user_data) ) - { + if (!usbh_edpt_xfer_with_callback(daddr, ep_addr, xfer->buffer, (uint16_t) xfer->buflen, + xfer->complete_cb, xfer->user_data)) { usbh_edpt_release(daddr, ep_addr); return false; } diff --git a/src/host/usbh.h b/src/host/usbh.h index 7591c7672..9ff118543 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -94,7 +94,7 @@ TU_ATTR_WEAK void tuh_mount_cb (uint8_t daddr); TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr); // Invoked when there is a new usb event, which need to be processed by tuh_task()/tuh_task_ext() -TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr); +void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr); //--------------------------------------------------------------------+ // APPLICATION API -- cgit v1.3.1 From 8eca596fa649a4e32da53f65ac1a41f963b89eb6 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 12 Jan 2024 16:05:35 +0700 Subject: style changes --- src/device/usbd_control.c | 105 +++++++++++++++++++--------------------------- 1 file changed, 43 insertions(+), 62 deletions(-) (limited to 'src') diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index ea18b28da..35cce1f7e 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -35,9 +35,9 @@ //--------------------------------------------------------------------+ // Callback weak stubs (called if application does not provide) //--------------------------------------------------------------------+ -TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) { - (void)rhport; - (void)request; +TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* request) { + (void) rhport; + (void) request; } //--------------------------------------------------------------------+ @@ -50,7 +50,7 @@ extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callb enum { EDPT_CTRL_OUT = 0x00, - EDPT_CTRL_IN = 0x80 + EDPT_CTRL_IN = 0x80 }; typedef struct { @@ -71,20 +71,18 @@ tu_static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE]; //--------------------------------------------------------------------+ // Queue ZLP status transaction -static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const * request) -{ +static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const* request) { // Opposite to endpoint in Data Phase uint8_t const ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN; return usbd_edpt_xfer(rhport, ep_addr, NULL, 0); } // Status phase -bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request) -{ - _ctrl_xfer.request = (*request); - _ctrl_xfer.buffer = NULL; +bool tud_control_status(uint8_t rhport, tusb_control_request_t const* request) { + _ctrl_xfer.request = (*request); + _ctrl_xfer.buffer = NULL; _ctrl_xfer.total_xferred = 0; - _ctrl_xfer.data_len = 0; + _ctrl_xfer.data_len = 0; return _status_stage_xact(rhport, request); } @@ -92,16 +90,15 @@ bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request) // Queue a transaction in Data Stage // Each transaction has up to Endpoint0's max packet size. // This function can also transfer an zero-length packet -static bool _data_stage_xact(uint8_t rhport) -{ - uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, CFG_TUD_ENDPOINT0_SIZE); +static bool _data_stage_xact(uint8_t rhport) { + uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, + CFG_TUD_ENDPOINT0_SIZE); uint8_t ep_addr = EDPT_CTRL_OUT; - if ( _ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN ) - { + if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN) { ep_addr = EDPT_CTRL_IN; - if ( xact_len ) { + if (xact_len) { TU_VERIFY(0 == tu_memcpy_s(_usbd_ctrl_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)); } } @@ -111,29 +108,24 @@ static bool _data_stage_xact(uint8_t rhport) // Transmit data to/from the control endpoint. // If the request's wLength is zero, a status packet is sent instead. -bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, void* buffer, uint16_t len) -{ - _ctrl_xfer.request = (*request); - _ctrl_xfer.buffer = (uint8_t*) buffer; +bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const* request, void* buffer, uint16_t len) { + _ctrl_xfer.request = (*request); + _ctrl_xfer.buffer = (uint8_t*) buffer; _ctrl_xfer.total_xferred = 0U; - _ctrl_xfer.data_len = tu_min16(len, request->wLength); + _ctrl_xfer.data_len = tu_min16(len, request->wLength); - if (request->wLength > 0U) - { - if(_ctrl_xfer.data_len > 0U) - { + if (request->wLength > 0U) { + if (_ctrl_xfer.data_len > 0U) { TU_ASSERT(buffer); } // TU_LOG2(" Control total data length is %u bytes\r\n", _ctrl_xfer.data_len); // Data stage - TU_ASSERT( _data_stage_xact(rhport) ); - } - else - { + TU_ASSERT(_data_stage_xact(rhport)); + } else { // Status stage - TU_ASSERT( _status_stage_xact(rhport, request) ); + TU_ASSERT(_status_stage_xact(rhport, request)); } return true; @@ -143,46 +135,41 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo // USBD API //--------------------------------------------------------------------+ void usbd_control_reset(void); -void usbd_control_set_request(tusb_control_request_t const *request); -void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp ); -bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes); +void usbd_control_set_request(tusb_control_request_t const* request); +void usbd_control_set_complete_callback(usbd_control_xfer_cb_t fp); +bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes); void usbd_control_reset(void) { tu_varclr(&_ctrl_xfer); } // Set complete callback -void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp ) -{ +void usbd_control_set_complete_callback(usbd_control_xfer_cb_t fp) { _ctrl_xfer.complete_cb = fp; } // for dcd_set_address where DCD is responsible for status response -void usbd_control_set_request(tusb_control_request_t const *request) -{ - _ctrl_xfer.request = (*request); - _ctrl_xfer.buffer = NULL; +void usbd_control_set_request(tusb_control_request_t const* request) { + _ctrl_xfer.request = (*request); + _ctrl_xfer.buffer = NULL; _ctrl_xfer.total_xferred = 0; - _ctrl_xfer.data_len = 0; + _ctrl_xfer.data_len = 0; } // callback when a transaction complete on // - DATA stage of control endpoint or // - Status stage -bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) -{ +bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { (void) result; // Endpoint Address is opposite to direction bit, this is Status Stage complete event - if ( tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction ) - { + if (tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction) { TU_ASSERT(0 == xferred_bytes); // invoke optional dcd hook if available dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request); - if (_ctrl_xfer.complete_cb) - { + if (_ctrl_xfer.complete_cb) { // TODO refactor with usbd_driver_print_control_complete_name _ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_ACK, &_ctrl_xfer.request); } @@ -190,8 +177,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result return true; } - if ( _ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT ) - { + if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT) { TU_VERIFY(_ctrl_xfer.buffer); memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes); TU_LOG_MEM(CFG_TUD_LOG_LEVEL, _usbd_ctrl_buf, xferred_bytes, 2); @@ -202,15 +188,14 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result // Data Stage is complete when all request's length are transferred or // a short packet is sent including zero-length packet. - if ( (_ctrl_xfer.request.wLength == _ctrl_xfer.total_xferred) || (xferred_bytes < CFG_TUD_ENDPOINT0_SIZE) ) - { + if ((_ctrl_xfer.request.wLength == _ctrl_xfer.total_xferred) || + (xferred_bytes < CFG_TUD_ENDPOINT0_SIZE)) { // DATA stage is complete bool is_ok = true; // invoke complete callback if set // callback can still stall control in status phase e.g out data does not make sense - if ( _ctrl_xfer.complete_cb ) - { + if (_ctrl_xfer.complete_cb) { #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL usbd_driver_print_control_complete_name(_ctrl_xfer.complete_cb); #endif @@ -218,21 +203,17 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result is_ok = _ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_DATA, &_ctrl_xfer.request); } - if ( is_ok ) - { + if (is_ok) { // Send status - TU_ASSERT( _status_stage_xact(rhport, &_ctrl_xfer.request) ); - }else - { + TU_ASSERT(_status_stage_xact(rhport, &_ctrl_xfer.request)); + } else { // Stall both IN and OUT control endpoint dcd_edpt_stall(rhport, EDPT_CTRL_OUT); dcd_edpt_stall(rhport, EDPT_CTRL_IN); } - } - else - { + } else { // More data to transfer - TU_ASSERT( _data_stage_xact(rhport) ); + TU_ASSERT(_data_stage_xact(rhport)); } return true; -- cgit v1.3.1 From d92eb38c211899ed963250272d882fcac8dbaf9c Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 15 Jan 2024 16:56:18 +0700 Subject: change code style --- src/class/cdc/cdc_host.c | 526 +++++++++++++++++++++-------------------------- 1 file changed, 235 insertions(+), 291 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 4f36f7517..05a061487 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -106,7 +106,7 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfe static uint16_t const ftdi_pids[] = { CFG_TUH_CDC_FTDI_PID_LIST }; enum { - FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0]) + FTDI_PID_COUNT = TU_ARRAY_SIZE(ftdi_pids) }; // Store last request baudrate since divisor to baudrate is not easy @@ -114,7 +114,6 @@ static uint32_t _ftdi_requested_baud; static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len); static void ftdi_process_config(tuh_xfer_t* xfer); - static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif @@ -125,12 +124,11 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu static uint16_t const cp210x_pids[] = { CFG_TUH_CDC_CP210X_PID_LIST }; enum { - CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0]) + CP210X_PID_COUNT = TU_ARRAY_SIZE(cp210x_pids) }; static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); static void cp210x_process_config(tuh_xfer_t* xfer); - static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif @@ -141,16 +139,16 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_ static uint16_t const ch34x_vids_pids[][2] = { CFG_TUH_CDC_CH34X_VID_PID_LIST }; enum { - CH34X_VID_PID_COUNT = sizeof ( ch34x_vids_pids ) / sizeof ( ch34x_vids_pids[0] ) + CH34X_VID_PID_COUNT = TU_ARRAY_SIZE(ch34x_vids_pids) }; static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len ); static void ch34x_process_config ( tuh_xfer_t* xfer ); - static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data ); static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ); #endif +//------------- Common -------------// enum { SERIAL_DRIVER_ACM = 0, @@ -204,29 +202,25 @@ static const cdch_serial_driver_t serial_drivers[] = { }; enum { - SERIAL_DRIVER_COUNT = sizeof(serial_drivers) / sizeof(serial_drivers[0]) + SERIAL_DRIVER_COUNT = TU_ARRAY_SIZE(serial_drivers) }; //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -static inline cdch_interface_t* get_itf(uint8_t idx) -{ +static inline cdch_interface_t* get_itf(uint8_t idx) { TU_ASSERT(idx < CFG_TUH_CDC, NULL); cdch_interface_t* p_cdc = &cdch_data[idx]; return (p_cdc->daddr != 0) ? p_cdc : NULL; } -static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr) -{ - for(uint8_t i=0; idaddr == daddr) && - (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr)) - { + (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr)) { return i; } } @@ -234,14 +228,10 @@ static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr) return TUSB_INDEX_INVALID_8; } - -static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const *itf_desc) -{ - for(uint8_t i=0; idaddr = daddr; p_cdc->bInterfaceNumber = itf_desc->bInterfaceNumber; p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass; @@ -262,20 +252,16 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer); // APPLICATION API //--------------------------------------------------------------------+ -uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num) -{ - for(uint8_t i=0; idaddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i; } return TUSB_INDEX_INVALID_8; } -bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) -{ +bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && info); @@ -297,30 +283,26 @@ bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) return true; } -bool tuh_cdc_mounted(uint8_t idx) -{ +bool tuh_cdc_mounted(uint8_t idx) { cdch_interface_t* p_cdc = get_itf(idx); return p_cdc != NULL; } -bool tuh_cdc_get_dtr(uint8_t idx) -{ +bool tuh_cdc_get_dtr(uint8_t idx) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR) ? true : false; } -bool tuh_cdc_get_rts(uint8_t idx) -{ +bool tuh_cdc_get_rts(uint8_t idx) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false; } -bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding) -{ +bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); @@ -333,32 +315,28 @@ bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding) // Write //--------------------------------------------------------------------+ -uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize) -{ +uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return tu_edpt_stream_write(&p_cdc->stream.tx, buffer, bufsize); } -uint32_t tuh_cdc_write_flush(uint8_t idx) -{ +uint32_t tuh_cdc_write_flush(uint8_t idx) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return tu_edpt_stream_write_xfer(&p_cdc->stream.tx); } -bool tuh_cdc_write_clear(uint8_t idx) -{ +bool tuh_cdc_write_clear(uint8_t idx) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return tu_edpt_stream_clear(&p_cdc->stream.tx); } -uint32_t tuh_cdc_write_available(uint8_t idx) -{ +uint32_t tuh_cdc_write_available(uint8_t idx) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); @@ -369,32 +347,28 @@ uint32_t tuh_cdc_write_available(uint8_t idx) // Read //--------------------------------------------------------------------+ -uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) -{ +uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return tu_edpt_stream_read(&p_cdc->stream.rx, buffer, bufsize); } -uint32_t tuh_cdc_read_available(uint8_t idx) -{ +uint32_t tuh_cdc_read_available(uint8_t idx) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return tu_edpt_stream_read_available(&p_cdc->stream.rx); } -bool tuh_cdc_peek(uint8_t idx, uint8_t* ch) -{ +bool tuh_cdc_peek(uint8_t idx, uint8_t* ch) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return tu_edpt_stream_peek(&p_cdc->stream.rx, ch); } -bool tuh_cdc_read_clear (uint8_t idx) -{ +bool tuh_cdc_read_clear (uint8_t idx) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); @@ -408,15 +382,13 @@ bool tuh_cdc_read_clear (uint8_t idx) //--------------------------------------------------------------------+ // internal control complete to update state such as line state, encoding -static void cdch_internal_control_complete(tuh_xfer_t* xfer) -{ +static void cdch_internal_control_complete(tuh_xfer_t* xfer) { uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t* p_cdc = get_itf(idx); TU_ASSERT(p_cdc, ); - if (xfer->result == XFER_RESULT_SUCCESS) - { + if (xfer->result == XFER_RESULT_SUCCESS) { switch (p_cdc->serial_drid) { case SERIAL_DRIVER_ACM: switch (xfer->setup->bRequest) { @@ -502,7 +474,6 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c } TU_VERIFY(ret && result == XFER_RESULT_SUCCESS); - p_cdc->line_state = (uint8_t) line_state; return true; } @@ -526,7 +497,6 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete } TU_VERIFY(ret && result == XFER_RESULT_SUCCESS); - p_cdc->line_coding.bit_rate = baudrate; return true; } @@ -552,7 +522,6 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, } TU_VERIFY(ret && result == XFER_RESULT_SUCCESS); - p_cdc->line_coding = *line_coding; return true; } @@ -562,31 +531,26 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, // CLASS-USBH API //--------------------------------------------------------------------+ -void cdch_init(void) -{ +void cdch_init(void) { tu_memclr(cdch_data, sizeof(cdch_data)); - for(size_t i=0; istream.tx, true, true, false, - p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE, - p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE); + p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE, + p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE); tu_edpt_stream_init(&p_cdc->stream.rx, true, false, false, - p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE, - p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE); + p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE, + p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE); } } -void cdch_close(uint8_t daddr) -{ - for(uint8_t idx=0; idxdaddr == daddr) - { + if (p_cdc->daddr == daddr) { TU_LOG_DRV(" CDCh close addr = %u index = %u\r\n", daddr, idx); // Invoke application callback @@ -618,16 +582,11 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t // - xferred_bytes is multiple of EP Packet size and not zero tu_edpt_stream_write_zlp_if_needed(&p_cdc->stream.tx, xferred_bytes); } - } - else if ( ep_addr == p_cdc->stream.rx.ep_addr ) { + } else if ( ep_addr == p_cdc->stream.rx.ep_addr ) { #if CFG_TUH_CDC_FTDI if (p_cdc->serial_drid == SERIAL_DRIVER_FTDI) { // FTDI reserve 2 bytes for status - // FTDI status -// uint8_t status[2] = { -// p_cdc->stream.rx.ep_buf[0], -// p_cdc->stream.rx.ep_buf[1] -// }; + // uint8_t status[2] = {p_cdc->stream.rx.ep_buf[0], p_cdc->stream.rx.ep_buf[1]}; tu_edpt_stream_read_xfer_complete_offset(&p_cdc->stream.rx, xferred_bytes, 2); }else #endif @@ -653,20 +612,15 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t // Enumeration //--------------------------------------------------------------------+ -static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const *desc_ep) -{ - for(size_t i=0; i<2; i++) - { +static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const* desc_ep) { + for (size_t i = 0; i < 2; i++) { TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && - TUSB_XFER_BULK == desc_ep->bmAttributes.xfer); - + TUSB_XFER_BULK == desc_ep->bmAttributes.xfer); TU_ASSERT(tuh_edpt_open(p_cdc->daddr, desc_ep)); - if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN ) - { + if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { tu_edpt_stream_open(&p_cdc->stream.rx, p_cdc->daddr, desc_ep); - }else - { + } else { tu_edpt_stream_open(&p_cdc->stream.tx, p_cdc->daddr, desc_ep); } @@ -676,20 +630,17 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t co return true; } -bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) -{ +bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { (void) rhport; - // Only support ACM subclass + // For CDC: only support ACM subclass // Note: Protocol 0xFF can be RNDIS device - if ( TUSB_CLASS_CDC == itf_desc->bInterfaceClass && - CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) - { + if (TUSB_CLASS_CDC == itf_desc->bInterfaceClass && + CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) { return acm_open(daddr, itf_desc, max_len); } #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X - else if ( TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass ) - { + else if (TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) { uint16_t vid, pid; TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid)); @@ -721,7 +672,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d } #endif } - #endif // CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X + #endif return false; } @@ -767,94 +718,85 @@ enum { CONFIG_ACM_COMPLETE, }; -static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) -{ - uint8_t const * p_desc_end = ((uint8_t const*) itf_desc) + max_len; +static bool acm_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) { + uint8_t const* p_desc_end = ((uint8_t const*) itf_desc) + max_len; - cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); + cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY(p_cdc); p_cdc->serial_drid = SERIAL_DRIVER_ACM; //------------- Control Interface -------------// - uint8_t const * p_desc = tu_desc_next(itf_desc); + uint8_t const* p_desc = tu_desc_next(itf_desc); // Communication Functional Descriptors - while( (p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc)) ) - { - if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) ) - { + while ((p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc))) { + if (CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc)) { // save ACM bmCapabilities - p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities; + p_cdc->acm_capability = ((cdc_desc_func_acm_t const*) p_desc)->bmCapabilities; } p_desc = tu_desc_next(p_desc); } // Open notification endpoint of control interface if any - if (itf_desc->bNumEndpoints == 1) - { + if (itf_desc->bNumEndpoints == 1) { TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)); - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc; + tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) p_desc; - TU_ASSERT( tuh_edpt_open(daddr, desc_ep) ); + TU_ASSERT(tuh_edpt_open(daddr, desc_ep)); p_cdc->ep_notif = desc_ep->bEndpointAddress; p_desc = tu_desc_next(p_desc); } //------------- Data Interface (if any) -------------// - if ( (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && - (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) ) - { + if ((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && + (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const*) p_desc)->bInterfaceClass)) { // next to endpoint descriptor p_desc = tu_desc_next(p_desc); // data endpoints expected to be in pairs - TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const *) p_desc)); + TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const*) p_desc)); } return true; } -static void acm_process_config(tuh_xfer_t* xfer) -{ +static void acm_process_config(tuh_xfer_t* xfer) { uintptr_t const state = xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT(p_cdc, ); + cdch_interface_t* p_cdc = get_itf(idx); + TU_ASSERT(p_cdc,); - switch(state) - { + switch (state) { case CONFIG_ACM_SET_CONTROL_LINE_STATE: #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - if (p_cdc->acm_capability.support_line_request) - { - TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config, - CONFIG_ACM_SET_LINE_CODING), ); + if (p_cdc->acm_capability.support_line_request) { + TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config, CONFIG_ACM_SET_LINE_CODING),); break; } - #endif + #endif TU_ATTR_FALLTHROUGH; case CONFIG_ACM_SET_LINE_CODING: - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - if (p_cdc->acm_capability.support_line_request) - { + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + if (p_cdc->acm_capability.support_line_request) { cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE), ); + TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE),); break; } - #endif + #endif TU_ATTR_FALLTHROUGH; case CONFIG_ACM_COMPLETE: // itf_num+1 to account for data interface as well - set_config_complete(p_cdc, idx, itf_num+1); + set_config_complete(p_cdc, idx, itf_num + 1); break; - default: break; + default: + break; } } @@ -987,13 +929,12 @@ static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint1 return tuh_control_xfer(&xfer); } -static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data); } -static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +static bool +ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_DRV("CDC FTDI Set Control Line State\r\n"); p_cdc->user_control_cb = complete_cb; TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, @@ -1001,8 +942,7 @@ static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state return true; } -static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base) -{ +static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base) { const uint8_t divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 }; uint32_t divisor; @@ -1022,13 +962,11 @@ static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base) return divisor; } -static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) -{ +static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) { return ftdi_232bm_baud_base_to_divisor(baud, 48000000u); } -static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate); TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor); @@ -1055,8 +993,7 @@ static void ftdi_process_config(tuh_xfer_t* xfer) { case CONFIG_FTDI_MODEM_CTRL: #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - TU_ASSERT( - ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),); + TU_ASSERT(ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),); break; #else TU_ATTR_FALLTHROUGH; @@ -1172,8 +1109,7 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_ complete_cb ? cdch_internal_control_complete : NULL, user_data); } -static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_DRV("CDC CP210x Set Control Line State\r\n"); p_cdc->user_control_cb = complete_cb; return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, @@ -1213,8 +1149,7 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { case CONFIG_CP210X_SET_DTR_RTS: #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - TU_ASSERT( - cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, cp210x_process_config, CONFIG_CP210X_COMPLETE),); + TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, cp210x_process_config, CONFIG_CP210X_COMPLETE),); break; #else TU_ATTR_FALLTHROUGH; @@ -1248,8 +1183,7 @@ enum { CONFIG_CH34X_COMPLETE }; -static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len ) -{ +static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len ) { // CH34x Interface includes 1 vendor interface + 3 bulk endpoints TU_VERIFY ( itf_desc->bNumEndpoints == 3 ); TU_VERIFY ( sizeof ( tusb_desc_interface_t ) + 2 * sizeof ( tusb_desc_endpoint_t ) <= max_len ); @@ -1303,23 +1237,19 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint return false; } -static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ +static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { return ch34x_set_request ( p_cdc, TUSB_DIR_OUT, request, value, index, /* buffer */ NULL, /* length */ 0, complete_cb, user_data ); } -static bool ch341_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ +static bool ch341_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { return ch34x_set_request ( p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize, complete_cb, user_data ); } -static int32_t ch341_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ +static int32_t ch341_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { return ch341_control_out ( p_cdc, CH341_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data ); } -static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ +static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { return ch341_control_in ( p_cdc, CH341_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data ); } @@ -1335,8 +1265,7 @@ static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, u */ // calculate baudrate devisors // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c -static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) -{ +static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) { uint32_t fact, div, clk_div; bool force_fact0 = false; int32_t ps; @@ -1362,20 +1291,19 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) */ fact = 1; for (ps = 3; ps >= 0; ps--) { - if (speed > ch341_min_rates[ps]) - break; + if (speed > ch341_min_rates[ps]) break; } - if (ps < 0) - return -EINVAL; + if (ps < 0) return -EINVAL; /* Determine corresponding divisor, rounding down. */ clk_div = CH341_CLK_DIV(ps, fact); div = CH341_CLKRATE / (clk_div * speed); /* Some devices require a lower base clock if ps < 3. */ - if (ps < 3 && (p_cdc->ch34x.quirks & CH341_QUIRK_LIMITED_PRESCALER)) + if (ps < 3 && (p_cdc->ch34x.quirks & CH341_QUIRK_LIMITED_PRESCALER)) { force_fact0 = true; + } /* Halve base clock (fact = 0) if required. */ if (div < 9 || div > 255 || force_fact0) { @@ -1384,16 +1312,16 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) fact = 0; } - if (div < 2) - return -EINVAL; + if (div < 2) return -EINVAL; /* * Pick next divisor if resulting rate is closer to the requested one, * scale up to avoid rounding errors on low rates. */ if (16 * CH341_CLKRATE / (clk_div * div) - 16 * speed >= - 16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1))) + 16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1))) { div++; + } /* * Prefer lower base clock (fact = 0) if even divisor. @@ -1411,16 +1339,13 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) // set baudrate (low level) // do not confuse with ch34x_set_baudrate // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c -static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ +static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { int val; - if (!baud_rate) - return -EINVAL; + if (!baud_rate) return -EINVAL; val = ch341_get_divisor(p_cdc, baud_rate); - if (val < 0) - return -EINVAL; + if (val < 0) return -EINVAL; /* * CH341A buffers data until a full endpoint-size packet (32 bytes) @@ -1429,100 +1354,94 @@ static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, * At least one device with version 0x27 appears to have this bit * inverted. */ - if ( p_cdc->ch34x.version > 0x27 ) + if ( p_cdc->ch34x.version > 0x27 ) { val |= BIT(7); + } return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data ); } // set lcr register // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c -static int32_t ch341_set_lcr ( cdch_interface_t* p_cdc, uint8_t lcr, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ +static int32_t ch341_set_lcr ( cdch_interface_t* p_cdc, uint8_t lcr, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { /* * Chip versions before version 0x30 as read using * CH341_REQ_READ_VERSION used separate registers for line control * (stop bits, parity and word length). Version 0x30 and above use * CH341_REG_LCR only and CH341_REG_LCR2 is always set to zero. */ - if ( p_cdc->ch34x.version < 0x30 ) - return 0; + if ( p_cdc->ch34x.version < 0x30 ) return 0; return ch341_write_reg ( p_cdc, CH341_REG_LCR2 << 8 | CH341_REG_LCR, lcr, complete_cb, user_data ); } // set handshake (modem controls) // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c -static int32_t ch341_set_handshake ( cdch_interface_t* p_cdc, uint8_t control, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ +static int32_t ch341_set_handshake ( cdch_interface_t* p_cdc, uint8_t control, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { return ch341_control_out ( p_cdc, CH341_REQ_MODEM_CTRL, /* value */ ~control, /* index */ 0, complete_cb, user_data ); } // detect quirks (special versions of CH34x) // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c -static int32_t ch341_detect_quirks ( tuh_xfer_t* xfer, cdch_interface_t* p_cdc, uint8_t step, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ +static int32_t ch341_detect_quirks ( tuh_xfer_t* xfer, cdch_interface_t* p_cdc, uint8_t step, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { /* * A subset of CH34x devices does not support all features. The * prescaler is limited and there is no support for sending a RS232 * break condition. A read failure when trying to set up the latter is * used to detect these devices. */ - switch ( step ) - { - case 1: - p_cdc->ch34x.quirks = 0; - return ch341_read_reg_request ( p_cdc, CH341_REG_BREAK, buffer, buffersize, complete_cb, user_data ); - break; - case 2: - if ( xfer->result != XFER_RESULT_SUCCESS ) - p_cdc->ch34x.quirks |= CH341_QUIRK_LIMITED_PRESCALER | CH341_QUIRK_SIMULATE_BREAK; - return true; - break; - default: - TU_ASSERT ( false ); // suspicious step - break; + switch (step) { + case 1: + p_cdc->ch34x.quirks = 0; + return ch341_read_reg_request(p_cdc, CH341_REG_BREAK, buffer, buffersize, complete_cb, user_data); + break; + + case 2: + if (xfer->result != XFER_RESULT_SUCCESS) { + p_cdc->ch34x.quirks |= CH341_QUIRK_LIMITED_PRESCALER | CH341_QUIRK_SIMULATE_BREAK; + } + return true; + break; + + default: + TU_ASSERT (false); // suspicious step + break; } } // internal control complete to update state such as line state, encoding // CH34x needs a special interface recovery due to abnormal wIndex usage -static void ch34x_control_complete(tuh_xfer_t* xfer) -{ - uint8_t const itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 ); - uint8_t const idx = tuh_cdc_itf_get_index ( xfer->daddr, itf_num ); - cdch_interface_t *p_cdc = get_itf ( idx ); - TU_ASSERT ( p_cdc, ); - TU_ASSERT ( p_cdc->serial_drid == SERIAL_DRIVER_CH34X, ); // ch34x_control_complete is only used for CH34x +static void ch34x_control_complete(tuh_xfer_t* xfer) { + uint8_t const itf_num = (uint8_t) ((xfer->user_data & 0xff00) >> 8); + uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t* p_cdc = get_itf(idx); + TU_ASSERT (p_cdc,); + TU_ASSERT (p_cdc->serial_drid == SERIAL_DRIVER_CH34X,); // ch34x_control_complete is only used for CH34x if (xfer->result == XFER_RESULT_SUCCESS) { switch (xfer->setup->bRequest) { - case CH341_REQ_WRITE_REG: { // register write request - switch ( tu_le16toh ( xfer->setup->wValue ) ) { - case ( CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER ): { // baudrate write - p_cdc->line_coding.bit_rate = p_cdc->ch34x.baud_rate; + case CH341_REQ_WRITE_REG: // register write request + switch (tu_le16toh (xfer->setup->wValue)) { + case (CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER): // baudrate write + p_cdc->line_coding.bit_rate = p_cdc->ch34x.baud_rate; + break; + + default: + TU_ASSERT(false,); // unexpected register write + break; + } break; - } - default: { - TU_ASSERT(false, ); // unexpected register write + + default: + TU_ASSERT(false,); // unexpected request break; - } - } - break; - } - default: { - TU_ASSERT(false, ); // unexpected request - break; - } } xfer->complete_cb = p_cdc->user_control_cb; - if (xfer->complete_cb) - xfer->complete_cb(xfer); + if (xfer->complete_cb) xfer->complete_cb(xfer); } } -static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) // do not confuse with ch341_set_baudrate -{ +static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) /* do not confuse with ch341_set_baudrate */ { TU_LOG_DRV("CDC CH34x Set BaudRate = %lu\r\n", baudrate); uint32_t baud_le = tu_htole32(baudrate); p_cdc->ch34x.baud_rate = baudrate; @@ -1530,15 +1449,13 @@ static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh return ch341_set_baudrate ( p_cdc, baud_le, complete_cb ? ch34x_control_complete : NULL, user_data ); } -static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ +static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { TU_LOG_DRV("CDC CH34x Set Control Line State\r\n"); // todo later return false; } -static void ch34x_process_config ( tuh_xfer_t* xfer ) -{ +static void ch34x_process_config ( tuh_xfer_t* xfer ) { uintptr_t const state = xfer->user_data & 0xff; // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber uint8_t const itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 ); @@ -1561,81 +1478,108 @@ static void ch34x_process_config ( tuh_xfer_t* xfer ) */ p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX | CH341_LCR_CS8; } + // This process flow has been taken over from Linux driver /drivers/usb/serial/ch341.c - switch ( state ) { - case CONFIG_CH34X_STEP1: // request version read - TU_ASSERT ( ch341_control_in ( p_cdc, /* request */ CH341_REQ_READ_VERSION, /* value */ 0, /* index */ 0, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP2 ), ); - break; - case CONFIG_CH34X_STEP2: // handle version read data, request to init CH34x - p_cdc->ch34x.version = xfer->buffer[0]; - TU_LOG_DRV ( "Chip version=%02x\r\n", p_cdc->ch34x.version ); - TU_ASSERT ( ch341_control_out ( p_cdc, /* request */ CH341_REQ_SERIAL_INIT, /* value */ 0, /* index */ 0, ch34x_process_config, CONFIG_CH34X_STEP3 ), ); - break; - case CONFIG_CH34X_STEP3: // set baudrate with default values (see above) - TU_ASSERT ( ch341_set_baudrate ( p_cdc, p_cdc->ch34x.baud_rate, ch34x_process_config, CONFIG_CH34X_STEP4 ) > 0, ); - break; - case CONFIG_CH34X_STEP4: // set line controls with default values (see above) - TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_STEP5 ) > 0, ); - break; - case CONFIG_CH34X_STEP5: // set handshake RTS/DTR - TU_ASSERT ( ch341_set_handshake ( p_cdc, p_cdc->ch34x.mcr, ch34x_process_config, CONFIG_CH34X_STEP6 ) > 0, ); - break; - case CONFIG_CH34X_STEP6: // detect quirks step 1 - TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 1, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP7 ) > 0, ); - break; - case CONFIG_CH34X_STEP7: // detect quirks step 2 and set baudrate with configured values - TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 2, NULL, 0, NULL, 0 ) > 0, ); -#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - TU_ASSERT ( ch34x_set_baudrate ( p_cdc, line_coding.bit_rate, ch34x_process_config, CONFIG_CH34X_STEP8 ), ); -#else - TU_ATTR_FALLTHROUGH; -#endif - break; - case CONFIG_CH34X_STEP8: // set data/stop bit quantities, parity -#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX; - switch ( line_coding.data_bits ) { - case 5: - p_cdc->ch34x.lcr |= CH341_LCR_CS5; + switch (state) { + case CONFIG_CH34X_STEP1: // request version read + TU_ASSERT (ch341_control_in(p_cdc, /* request */ CH341_REQ_READ_VERSION, /* value */ 0, /* index */0, + buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP2),); break; - case 6: - p_cdc->ch34x.lcr |= CH341_LCR_CS6; + + case CONFIG_CH34X_STEP2: // handle version read data, request to init CH34x + p_cdc->ch34x.version = xfer->buffer[0]; + TU_LOG_DRV ("Chip version=%02x\r\n", p_cdc->ch34x.version); + TU_ASSERT (ch341_control_out(p_cdc, /* request */ CH341_REQ_SERIAL_INIT, /* value */ 0, /* index */0, + ch34x_process_config, CONFIG_CH34X_STEP3),); break; - case 7: - p_cdc->ch34x.lcr |= CH341_LCR_CS7; + + case CONFIG_CH34X_STEP3: // set baudrate with default values (see above) + TU_ASSERT (ch341_set_baudrate(p_cdc, p_cdc->ch34x.baud_rate, ch34x_process_config, + CONFIG_CH34X_STEP4) > 0,); break; - case 8: - p_cdc->ch34x.lcr |= CH341_LCR_CS8; + + case CONFIG_CH34X_STEP4: // set line controls with default values (see above) + TU_ASSERT (ch341_set_lcr(p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_STEP5) > 0,); break; - default: - TU_ASSERT ( false, ); // not supported data_bits - p_cdc->ch34x.lcr |= CH341_LCR_CS8; + + case CONFIG_CH34X_STEP5: // set handshake RTS/DTR + TU_ASSERT (ch341_set_handshake(p_cdc, p_cdc->ch34x.mcr, ch34x_process_config, CONFIG_CH34X_STEP6) > 0,); break; - } - if ( line_coding.parity != CDC_LINE_CODING_PARITY_NONE ) { - p_cdc->ch34x.lcr |= CH341_LCR_ENABLE_PAR; - if ( line_coding.parity == CDC_LINE_CODING_PARITY_EVEN || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE ) - p_cdc->ch34x.lcr |= CH341_LCR_PAR_EVEN; - if ( line_coding.parity == CDC_LINE_CODING_PARITY_MARK || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE ) - p_cdc->ch34x.lcr |= CH341_LCR_MARK_SPACE; - } - TU_ASSERT ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2, ); // not supported 1.5 stop bits - if ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2 ) - p_cdc->ch34x.lcr |= CH341_LCR_STOP_BITS_2; - TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_COMPLETE ) > 0, ); + + case CONFIG_CH34X_STEP6: // detect quirks step 1 + TU_ASSERT (ch341_detect_quirks(xfer, p_cdc, /* step */ 1, buffer, CH34X_BUFFER_SIZE, + ch34x_process_config, CONFIG_CH34X_STEP7) > 0,); + break; + + case CONFIG_CH34X_STEP7: // detect quirks step 2 and set baudrate with configured values + TU_ASSERT (ch341_detect_quirks(xfer, p_cdc, /* step */ 2, NULL, 0, NULL, 0) > 0,); +#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + TU_ASSERT (ch34x_set_baudrate(p_cdc, line_coding.bit_rate, ch34x_process_config, CONFIG_CH34X_STEP8),); #else - TU_ATTR_FALLTHROUGH; + TU_ATTR_FALLTHROUGH; #endif - break; + break; + + case CONFIG_CH34X_STEP8: // set data/stop bit quantities, parity +#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX; + switch (line_coding.data_bits) { + case 5: + p_cdc->ch34x.lcr |= CH341_LCR_CS5; + break; + + case 6: + p_cdc->ch34x.lcr |= CH341_LCR_CS6; + break; + + case 7: + p_cdc->ch34x.lcr |= CH341_LCR_CS7; + break; + + case 8: + p_cdc->ch34x.lcr |= CH341_LCR_CS8; + break; + + default: + TU_ASSERT (false,); // not supported data_bits + p_cdc->ch34x.lcr |= CH341_LCR_CS8; + break; + } + + if (line_coding.parity != CDC_LINE_CODING_PARITY_NONE) { + p_cdc->ch34x.lcr |= CH341_LCR_ENABLE_PAR; + + if (line_coding.parity == CDC_LINE_CODING_PARITY_EVEN || + line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) { + p_cdc->ch34x.lcr |= CH341_LCR_PAR_EVEN; + } + + if (line_coding.parity == CDC_LINE_CODING_PARITY_MARK || + line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) { + p_cdc->ch34x.lcr |= CH341_LCR_MARK_SPACE; + } + } + TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits == + CDC_LINE_CODING_STOP_BITS_2,); // not supported 1.5 stop bits + if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2) { + p_cdc->ch34x.lcr |= CH341_LCR_STOP_BITS_2; + } + TU_ASSERT (ch341_set_lcr(p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_COMPLETE) > 0,); +#else + TU_ATTR_FALLTHROUGH; +#endif + break; + case CONFIG_CH34X_COMPLETE: - set_config_complete ( p_cdc, idx, itf_num ); + set_config_complete(p_cdc, idx, itf_num); break; + default: - TU_ASSERT ( false, ); + TU_ASSERT (false,); break; } } #endif // CFG_TUH_CDC_CH34X -#endif // (CFG_TUH_ENABLED && CFG_TUH_CDC) +#endif -- cgit v1.3.1 From d192868d62b56ef2eab9300bf0698a77e4e01cd3 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 15 Jan 2024 18:25:15 +0700 Subject: fix sign-conversion warning --- src/class/cdc/cdc_host.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 05a061487..0cc35da52 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1207,7 +1207,7 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_DEVICE, .type = TUSB_REQ_TYPE_VENDOR, - .direction = direction + .direction = direction & 0x01u }, .bRequest = request, .wValue = tu_htole16 ( value ), @@ -1265,6 +1265,11 @@ static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, u */ // calculate baudrate devisors // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c + +static inline uint32_t clamp_val(uint32_t val, uint32_t minval, uint32_t maxval) { + return tu_min32(tu_max32(val, minval), maxval); +} + static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) { uint32_t fact, div, clk_div; bool force_fact0 = false; @@ -1280,9 +1285,6 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) { * Clamp to supported range, this makes the (ps < 0) and (div < 2) * sanity checks below redundant. */ - inline uint32_t max ( uint32_t val, uint32_t maxval ) { return val > maxval ? val : maxval; } - inline uint32_t min ( uint32_t val, uint32_t minval ) { return val < minval ? val : minval; } - inline uint32_t clamp_val ( uint32_t val, uint32_t minval, uint32_t maxval ) { return min ( max ( val, minval ), maxval ); } speed = clamp_val(speed, CH341_MIN_BPS, CH341_MAX_BPS); /* @@ -1297,7 +1299,7 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) { if (ps < 0) return -EINVAL; /* Determine corresponding divisor, rounding down. */ - clk_div = CH341_CLK_DIV(ps, fact); + clk_div = CH341_CLK_DIV((uint32_t) ps, fact); div = CH341_CLKRATE / (clk_div * speed); /* Some devices require a lower base clock if ps < 3. */ @@ -1333,19 +1335,20 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) { fact = 0; } - return (0x100 - div) << 8 | fact << 2 | ps; + return (int32_t) ((0x100 - div) << 8 | fact << 2 | (uint32_t) ps); } // set baudrate (low level) // do not confuse with ch34x_set_baudrate // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c -static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { - int val; - +static int32_t ch341_set_baudrate (cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { if (!baud_rate) return -EINVAL; - val = ch341_get_divisor(p_cdc, baud_rate); - if (val < 0) return -EINVAL; + int ret; + ret = ch341_get_divisor(p_cdc, baud_rate); + if (ret < 0) return -EINVAL; + + uint16_t val = (uint16_t) ret; /* * CH341A buffers data until a full endpoint-size packet (32 bytes) @@ -1355,7 +1358,7 @@ static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, * inverted. */ if ( p_cdc->ch34x.version > 0x27 ) { - val |= BIT(7); + val = (val | BIT(7)); } return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data ); @@ -1449,8 +1452,13 @@ static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh return ch341_set_baudrate ( p_cdc, baud_le, complete_cb ? ch34x_control_complete : NULL, user_data ); } -static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { +static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_DRV("CDC CH34x Set Control Line State\r\n"); + (void) p_cdc; + (void) line_state; + (void) complete_cb; + (void) user_data; + // todo later return false; } -- cgit v1.3.1 From 1f2901e8b12258c953e3c338897f188c98b5eaed Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 15 Jan 2024 18:42:39 +0700 Subject: fix conflict of BIT() macro --- src/class/cdc/cdc_host.c | 2 +- src/class/cdc/serial/ch34x.h | 11 ++++------- src/common/tusb_common.h | 1 + 3 files changed, 6 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 0cc35da52..ca5bfff04 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1358,7 +1358,7 @@ static int32_t ch341_set_baudrate (cdch_interface_t* p_cdc, uint32_t baud_rate, * inverted. */ if ( p_cdc->ch34x.version > 0x27 ) { - val = (val | BIT(7)); + val = (val | TU_BIT(7)); } return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data ); diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h index 94e18b252..4a5e61bbd 100644 --- a/src/class/cdc/serial/ch34x.h +++ b/src/class/cdc/serial/ch34x.h @@ -29,7 +29,7 @@ #include -#define BIT(nr) ( (uint32_t)1 << (nr) ) +//#define BIT(nr) ( (uint32_t)1 << (nr) ) #define CH34X_BUFFER_SIZE 2 @@ -93,20 +93,17 @@ #define CH341_LCR_CS6 0x01 #define CH341_LCR_CS5 0x00 -#define CH341_QUIRK_LIMITED_PRESCALER BIT(0) -#define CH341_QUIRK_SIMULATE_BREAK BIT(1) +#define CH341_QUIRK_LIMITED_PRESCALER TU_BIT(0) +#define CH341_QUIRK_SIMULATE_BREAK TU_BIT(1) #define CH341_CLKRATE 48000000 #define CH341_CLK_DIV(ps, fact) (1 << (12 - 3 * (ps) - (fact))) #define CH341_MIN_RATE(ps) (CH341_CLKRATE / (CH341_CLK_DIV((ps), 1) * 512)) /* Supported range is 46 to 3000000 bps. */ -#define CH341_MIN_BPS DIV_ROUND_UP(CH341_CLKRATE, CH341_CLK_DIV(0, 0) * 256) +#define CH341_MIN_BPS TU_DIV_CEIL(CH341_CLKRATE, CH341_CLK_DIV(0, 0) * 256) #define CH341_MAX_BPS (CH341_CLKRATE / (CH341_CLK_DIV(3, 0) * 2)) -#define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP -#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) - // error codes #define EINVAL 22 /* Invalid argument */ diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index caeb5f2ef..1f08ce4ed 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -37,6 +37,7 @@ #define TU_ARRAY_SIZE(_arr) ( sizeof(_arr) / sizeof(_arr[0]) ) #define TU_MIN(_x, _y) ( ( (_x) < (_y) ) ? (_x) : (_y) ) #define TU_MAX(_x, _y) ( ( (_x) > (_y) ) ? (_x) : (_y) ) +#define TU_DIV_CEIL(n, d) (((n) + (d) - 1) / (d)) #define TU_U16(_high, _low) ((uint16_t) (((_high) << 8) | (_low))) #define TU_U16_HIGH(_u16) ((uint8_t) (((_u16) >> 8) & 0x00ff)) -- cgit v1.3.1 From aa58cdcfa6a35cf5d903eaffd304db4834ce56ec Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 16 Jan 2024 01:28:29 +0700 Subject: change CFG_TUH_CDC_FTDI/CP210X_PID_LIST to CFG_TUH_CDC_FTDI/CP210X_VID_PID_LIST which contains both vid and pid. --- .idea/cmake.xml | 2 +- src/class/cdc/cdc_host.c | 24 ++++++++++-------------- src/tusb_option.h | 18 ++++++++++-------- 3 files changed, 21 insertions(+), 23 deletions(-) (limited to 'src') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 432e44172..3cb883e62 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -80,7 +80,7 @@ - + \ No newline at end of file diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 79477ef53..2463671c6 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -91,9 +91,9 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfe #if CFG_TUH_CDC_FTDI #include "serial/ftdi_sio.h" -static uint16_t const ftdi_pids[] = { CFG_TUH_CDC_FTDI_PID_LIST }; +static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST }; enum { - FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0]) + FTDI_PID_COUNT = sizeof(ftdi_vid_pid_list) / sizeof(ftdi_vid_pid_list[0]) }; // Store last request baudrate since divisor to baudrate is not easy @@ -110,9 +110,9 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu #if CFG_TUH_CDC_CP210X #include "serial/cp210x.h" -static uint16_t const cp210x_pids[] = { CFG_TUH_CDC_CP210X_PID_LIST }; +static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIST }; enum { - CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0]) + CP210X_PID_COUNT = sizeof(cp210x_vid_pid_list) / sizeof(cp210x_vid_pid_list[0]) }; static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); @@ -647,21 +647,17 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid)); #if CFG_TUH_CDC_FTDI - if (TU_FTDI_VID == vid) { - for (size_t i = 0; i < FTDI_PID_COUNT; i++) { - if (ftdi_pids[i] == pid) { - return ftdi_open(daddr, itf_desc, max_len); - } + for (size_t i = 0; i < FTDI_PID_COUNT; i++) { + if (ftdi_vid_pid_list[i][0] == vid && ftdi_vid_pid_list[i][1] == pid) { + return ftdi_open(daddr, itf_desc, max_len); } } #endif #if CFG_TUH_CDC_CP210X - if (TU_CP210X_VID == vid) { - for (size_t i = 0; i < CP210X_PID_COUNT; i++) { - if (cp210x_pids[i] == pid) { - return cp210x_open(daddr, itf_desc, max_len); - } + for (size_t i = 0; i < CP210X_PID_COUNT; i++) { + if (cp210x_vid_pid_list[i][0] == vid && cp210x_vid_pid_list[i][1] == pid) { + return cp210x_open(daddr, itf_desc, max_len); } } #endif diff --git a/src/tusb_option.h b/src/tusb_option.h index a76281c0c..57f026312 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -453,10 +453,12 @@ #define CFG_TUH_CDC_FTDI 0 #endif -#ifndef CFG_TUH_CDC_FTDI_PID_LIST - // List of product IDs that can use the FTDI CDC driver - #define CFG_TUH_CDC_FTDI_PID_LIST \ - 0x6001, 0x6006, 0x6010, 0x6011, 0x6014, 0x6015, 0x8372, 0xFBFA, 0xCD18 +#ifndef CFG_TUH_CDC_FTDI_VID_PID_LIST + // List of product IDs that can use the FTDI CDC driver. 0x0403 is FTDI's VID + #define CFG_TUH_CDC_FTDI_VID_PID_LIST \ + {0x0403, 0x6001}, {0x0403, 0x6006}, {0x0403, 0x6010}, {0x0403, 0x6011}, \ + {0x0403, 0x6014}, {0x0403, 0x6015}, {0x0403, 0x8372}, {0x0403, 0xFBFA}, \ + {0x0403, 0xCD18} #endif #ifndef CFG_TUH_CDC_CP210X @@ -464,10 +466,10 @@ #define CFG_TUH_CDC_CP210X 0 #endif -#ifndef CFG_TUH_CDC_CP210X_PID_LIST - // List of product IDs that can use the CP210X CDC driver - #define CFG_TUH_CDC_CP210X_PID_LIST \ - 0xEA60, 0xEA70 +#ifndef CFG_TUH_CDC_CP210X_VID_PID_LIST + // List of product IDs that can use the CP210X CDC driver. 0x10C4 is Silicon Labs' VID + #define CFG_TUH_CDC_CP210X_VID_PID_LIST \ + {0x10C4, 0xEA60}, {0x10C4, 0xEA70} #endif #ifndef CFG_TUH_HID -- cgit v1.3.1 From e2aa671346103d3ed80c2849350488d5ddf2e0dc Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 16 Jan 2024 12:54:39 +0700 Subject: move open() ad vid_pid_list into serial driver struct --- src/class/cdc/cdc_host.c | 102 ++++++++++++++++++++++------------------------- 1 file changed, 47 insertions(+), 55 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index c018cf057..91e35ec8c 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -104,10 +104,7 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfe #if CFG_TUH_CDC_FTDI #include "serial/ftdi_sio.h" -static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST }; -enum { - FTDI_PID_COUNT = TU_ARRAY_SIZE(ftdi_vid_pid_list) -}; +static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST}; // Store last request baudrate since divisor to baudrate is not easy static uint32_t _ftdi_requested_baud; @@ -122,10 +119,7 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu #if CFG_TUH_CDC_CP210X #include "serial/cp210x.h" -static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIST }; -enum { - CP210X_PID_COUNT = TU_ARRAY_SIZE(cp210x_vid_pid_list) -}; +static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIST}; static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); static void cp210x_process_config(tuh_xfer_t* xfer); @@ -137,10 +131,7 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_ #if CFG_TUH_CDC_CH34X #include "serial/ch34x.h" -static uint16_t const ch34x_vids_pids[][2] = { CFG_TUH_CDC_CH34X_VID_PID_LIST }; -enum { - CH34X_VID_PID_COUNT = TU_ARRAY_SIZE(ch34x_vids_pids) -}; +static uint16_t const ch34x_vid_pid_list[][2] = {CFG_TUH_CDC_CH34X_VID_PID_LIST}; static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len ); static void ch34x_process_config ( tuh_xfer_t* xfer ); @@ -164,9 +155,14 @@ enum { #if CFG_TUH_CDC_CH34X SERIAL_DRIVER_CH34X, #endif + + SERIAL_DRIVER_COUNT }; typedef struct { + uint16_t const (*vid_pid_list)[2]; + uint16_t const vid_pid_count; + bool (*const open)(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len); void (*const process_set_config)(tuh_xfer_t* xfer); bool (*const set_control_line_state)(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); bool (*const set_baudrate)(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -174,36 +170,50 @@ typedef struct { // Note driver list must be in the same order as SERIAL_DRIVER enum static const cdch_serial_driver_t serial_drivers[] = { - { .process_set_config = acm_process_config, - .set_control_line_state = acm_set_control_line_state, - .set_baudrate = acm_set_baudrate + { + .vid_pid_list = NULL, + .vid_pid_count = 0, + .open = acm_open, + .process_set_config = acm_process_config, + .set_control_line_state = acm_set_control_line_state, + .set_baudrate = acm_set_baudrate }, #if CFG_TUH_CDC_FTDI - { .process_set_config = ftdi_process_config, - .set_control_line_state = ftdi_sio_set_modem_ctrl, - .set_baudrate = ftdi_sio_set_baudrate + { + .vid_pid_list = ftdi_vid_pid_list, + .vid_pid_count = TU_ARRAY_SIZE(ftdi_vid_pid_list), + .open = ftdi_open, + .process_set_config = ftdi_process_config, + .set_control_line_state = ftdi_sio_set_modem_ctrl, + .set_baudrate = ftdi_sio_set_baudrate }, #endif #if CFG_TUH_CDC_CP210X - { .process_set_config = cp210x_process_config, - .set_control_line_state = cp210x_set_modem_ctrl, - .set_baudrate = cp210x_set_baudrate + { + .vid_pid_list = cp210x_vid_pid_list, + .vid_pid_count = TU_ARRAY_SIZE(cp210x_vid_pid_list), + .open = cp210x_open, + .process_set_config = cp210x_process_config, + .set_control_line_state = cp210x_set_modem_ctrl, + .set_baudrate = cp210x_set_baudrate }, #endif #if CFG_TUH_CDC_CH34X - { .process_set_config = ch34x_process_config, - .set_control_line_state = ch34x_set_modem_ctrl, - .set_baudrate = ch34x_set_baudrate + { + .vid_pid_list = ch34x_vid_pid_list, + .vid_pid_count = TU_ARRAY_SIZE(ch34x_vid_pid_list), + .open = ch34x_open, + .process_set_config = ch34x_process_config, + .set_control_line_state = ch34x_set_modem_ctrl, + .set_baudrate = ch34x_set_baudrate }, -#endif + #endif }; -enum { - SERIAL_DRIVER_COUNT = TU_ARRAY_SIZE(serial_drivers) -}; +TU_VERIFY_STATIC(TU_ARRAY_SIZE(serial_drivers) == SERIAL_DRIVER_COUNT, "Serial driver count mismatch"); //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION @@ -639,36 +649,20 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) { return acm_open(daddr, itf_desc, max_len); } - #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X - else if (TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) { + else if (SERIAL_DRIVER_COUNT > 1 && + TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) { uint16_t vid, pid; TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid)); - #if CFG_TUH_CDC_FTDI - for (size_t i = 0; i < FTDI_PID_COUNT; i++) { - if (ftdi_vid_pid_list[i][0] == vid && ftdi_vid_pid_list[i][1] == pid) { - return ftdi_open(daddr, itf_desc, max_len); - } - } - #endif - - #if CFG_TUH_CDC_CP210X - for (size_t i = 0; i < CP210X_PID_COUNT; i++) { - if (cp210x_vid_pid_list[i][0] == vid && cp210x_vid_pid_list[i][1] == pid) { - return cp210x_open(daddr, itf_desc, max_len); - } - } - #endif - - #if CFG_TUH_CDC_CH34X - for (size_t i = 0; i < CH34X_VID_PID_COUNT; i++) { - if ( ch34x_vids_pids[i][0] == vid && ch34x_vids_pids[i][1] == pid ) { - return ch34x_open(daddr, itf_desc, max_len); + for (size_t dr = 1; dr < SERIAL_DRIVER_COUNT; dr++) { + cdch_serial_driver_t const* driver = &serial_drivers[dr]; + for (size_t i = 0; i < driver->vid_pid_count; i++) { + if (driver->vid_pid_list[i][0] == vid && driver->vid_pid_list[i][1] == pid) { + return driver->open(daddr, itf_desc, max_len); + } } } - #endif } - #endif return false; } @@ -683,9 +677,7 @@ static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t i usbh_driver_set_config_complete(p_cdc->daddr, itf_num); } - -bool cdch_set_config(uint8_t daddr, uint8_t itf_num) -{ +bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { tusb_control_request_t request; request.wIndex = tu_htole16((uint16_t) itf_num); -- cgit v1.3.1 From 4e6408ea4940085f66c676772d77e3951e82ea11 Mon Sep 17 00:00:00 2001 From: IngHK Date: Tue, 16 Jan 2024 08:07:22 +0100 Subject: CDCh host: further work on CH340/CH341 support --- examples/host/cdc_msc_hid/src/tusb_config.h | 3 +- .../host/cdc_msc_hid_freertos/src/tusb_config.h | 3 +- src/class/cdc/cdc_debug.h | 65 +++ src/class/cdc/cdc_device.c | 21 +- src/class/cdc/cdc_host.c | 568 ++++++++++----------- src/class/cdc/cdc_host.h | 4 +- src/class/cdc/serial/ch34x.h | 103 +--- 7 files changed, 369 insertions(+), 398 deletions(-) create mode 100644 src/class/cdc/cdc_debug.h (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index 76d59c316..ac14ef97e 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -120,8 +120,7 @@ //------------- CDC -------------// // Set Line Control state on enumeration/mounted: -// DTR ( bit 0), RTS (bit 1) -#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM 0x03 +#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM ( CDC_CONTROL_LINE_STATE_RTS | CDC_CONTROL_LINE_STATE_DTR ) // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t // bit rate = 115200, 1 stop bit, no parity, 8 bit data width diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h index bb7c3388d..1b68dd2d8 100644 --- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h @@ -125,8 +125,7 @@ //------------- CDC -------------// // Set Line Control state on enumeration/mounted: -// DTR ( bit 0), RTS (bit 1) -#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM 0x03 +#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM ( CDC_CONTROL_LINE_STATE_RTS | CDC_CONTROL_LINE_STATE_DTR ) // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t // bit rate = 115200, 1 stop bit, no parity, 8 bit data width diff --git a/src/class/cdc/cdc_debug.h b/src/class/cdc/cdc_debug.h new file mode 100644 index 000000000..879e49a50 --- /dev/null +++ b/src/class/cdc/cdc_debug.h @@ -0,0 +1,65 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * Copyright (c) 2023 IngHK Heiko Kuester + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_CDC_DEBUG_H_ +#define _TUSB_CDC_DEBUG_H_ + +#include "cdc.h" + +#ifdef __cplusplus + extern "C" { +#endif + +// logging of line coding +#define TU_LOG_LINE_CODING(PRE_TEXT,LINE_CODING) \ + TU_LOG_DRV(PRE_TEXT "Line Coding %lu Bd, %u%c%s\r\n", \ + LINE_CODING.bit_rate, \ + LINE_CODING.data_bits, \ + LINE_CODING.parity == CDC_LINE_CODING_PARITY_NONE ? 'N' : \ + LINE_CODING.parity == CDC_LINE_CODING_PARITY_ODD ? 'O' : \ + LINE_CODING.parity == CDC_LINE_CODING_PARITY_EVEN ? 'E' : \ + LINE_CODING.parity == CDC_LINE_CODING_PARITY_MARK ? 'M' : \ + LINE_CODING.parity == CDC_LINE_CODING_PARITY_SPACE ? 'S' : '?', \ + LINE_CODING.stop_bits == CDC_LINE_CODING_STOP_BITS_1 ? "1" : \ + LINE_CODING.stop_bits == CDC_LINE_CODING_STOP_BITS_1_5 ? "1.5" : \ + LINE_CODING.stop_bits == CDC_LINE_CODING_STOP_BITS_2 ? "2" : "?") + +// logging of baudrate +#define TU_LOG_BAUDRATE(PRE_TEXT,BAUDRATE) \ + TU_LOG_DRV(PRE_TEXT "Baudrate %lu Bd\r\n", BAUDRATE) + + // logging of control line state +#define TU_LOG_CONTROL_LINE_STATE(PRE_TEXT,LINE_STATE) \ + TU_LOG_DRV(PRE_TEXT "Control Line State RTS%c DTR%c\r\n", \ + LINE_STATE & CDC_CONTROL_LINE_STATE_RTS ? '+' : '-', \ + LINE_STATE & CDC_CONTROL_LINE_STATE_DTR ? '+' : '-' ) + +#ifdef __cplusplus + } +#endif + +#endif /* _TUSB_CDC_DEBUG_H_ */ diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index c26264e60..b763419e7 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -32,6 +32,9 @@ #include "device/usbd_pvt.h" #include "cdc_device.h" +#if 0 // TODO activate and test +#include "cdc_debug.h" +#endif // Level where CFG_TUSB_DEBUG must be at least for this driver is logged #ifndef CFG_TUD_CDC_LOG_LEVEL @@ -360,7 +363,11 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t case CDC_REQUEST_SET_LINE_CODING: if (stage == CONTROL_STAGE_SETUP) { - TU_LOG_DRV(" Set Line Coding\r\n"); + #if 0 // TODO activate, test and remove else + TU_LOG_LINE_CODING(" Set ", p_cdc->line_coding); + #else + TU_LOG_DRV(" Set Line Coding\r\n"); + #endif tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t)); } else if ( stage == CONTROL_STAGE_ACK) @@ -372,7 +379,11 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t case CDC_REQUEST_GET_LINE_CODING: if (stage == CONTROL_STAGE_SETUP) { - TU_LOG_DRV(" Get Line Coding\r\n"); + #if 0 // TODO activate, test and remove else + TU_LOG_LINE_CODING(" Get ", p_cdc->line_coding); + #else + TU_LOG_DRV(" Get Line Coding\r\n"); + #endif tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t)); } break; @@ -397,7 +408,11 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t // Disable fifo overwriting if DTR bit is set tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr); - TU_LOG_DRV(" Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts); + #if 0 // TODO activate, test and remove else + TU_LOG_CONTROL_LINE_STATE(" Set ", p_cdc->line_state); + #else + TU_LOG_DRV(" Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts); + #endif // Invoke callback if ( tud_cdc_line_state_cb ) tud_cdc_line_state_cb(itf, dtr, rts); diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index f6a6773e0..d46bfecb4 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -2,7 +2,7 @@ * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) - * Copyright (c) 2023 Heiko Kuester (CH34x support) + * Copyright (c) 2023 IngHK Heiko Kuester * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,7 @@ #include "host/usbh_pvt.h" #include "cdc_host.h" +#include "cdc_debug.h" // Level where CFG_TUSB_DEBUG must be at least for this driver is logged #ifndef CFG_TUH_CDC_LOG_LEVEL @@ -55,7 +56,7 @@ typedef struct { cdc_acm_capability_t acm_capability; uint8_t ep_notif; - uint8_t line_state; // DTR (bit0), RTS (bit1) + uint8_t line_state; // RTS, DTR (refer enums CDC_CONTROL_LINE_STATE_RTS, CDC_CONTROL_LINE_STATE_DTR) TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width tuh_xfer_cb_t user_control_cb; @@ -70,16 +71,9 @@ typedef struct { uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE]; } stream; - #if CFG_TUH_CDC_CH34X - struct { - uint32_t baud_rate; - uint8_t mcr; - uint8_t msr; - uint8_t lcr; - uint32_t quirks; - uint8_t version; - } ch34x; - #endif +#if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CH34X + uint32_t baudrate_requested; +#endif } cdch_interface_t; CFG_TUH_MEM_SECTION @@ -106,12 +100,10 @@ enum { FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0]) }; -// Store last request baudrate since divisor to baudrate is not easy -static uint32_t _ftdi_requested_baud; - static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len); static void ftdi_process_config(tuh_xfer_t* xfer); +static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif @@ -128,6 +120,7 @@ enum { static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); static void cp210x_process_config(tuh_xfer_t* xfer); +static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif @@ -144,6 +137,7 @@ enum { static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len ); static void ch34x_process_config ( tuh_xfer_t* xfer ); +static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data ); static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ); #endif @@ -169,35 +163,40 @@ typedef struct { void (*const process_set_config)(tuh_xfer_t* xfer); bool (*const set_control_line_state)(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); bool (*const set_baudrate)(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + bool (*const set_line_coding)(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); } cdch_serial_driver_t; // Note driver list must be in the same order as SERIAL_DRIVER enum static const cdch_serial_driver_t serial_drivers[] = { { .process_set_config = acm_process_config, .set_control_line_state = acm_set_control_line_state, - .set_baudrate = acm_set_baudrate + .set_baudrate = acm_set_baudrate, + .set_line_coding = acm_set_line_coding }, #if CFG_TUH_CDC_FTDI { .process_set_config = ftdi_process_config, .set_control_line_state = ftdi_sio_set_modem_ctrl, - .set_baudrate = ftdi_sio_set_baudrate + .set_baudrate = ftdi_sio_set_baudrate, + .set_line_coding = ftdi_set_line_coding }, #endif #if CFG_TUH_CDC_CP210X { .process_set_config = cp210x_process_config, .set_control_line_state = cp210x_set_modem_ctrl, - .set_baudrate = cp210x_set_baudrate + .set_baudrate = cp210x_set_baudrate, + .set_line_coding = cp210x_set_line_coding }, #endif #if CFG_TUH_CDC_CH34X { .process_set_config = ch34x_process_config, .set_control_line_state = ch34x_set_modem_ctrl, - .set_baudrate = ch34x_set_baudrate + .set_baudrate = ch34x_set_baudrate, + .set_line_coding = ch34x_set_line_coding }, -#endif + #endif }; enum { @@ -304,6 +303,7 @@ bool tuh_cdc_get_dtr(uint8_t idx) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); + TU_LOG_CONTROL_LINE_STATE("CDCh Local ", p_cdc->line_state); return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR) ? true : false; } @@ -312,6 +312,7 @@ bool tuh_cdc_get_rts(uint8_t idx) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); + TU_LOG_CONTROL_LINE_STATE("CDCh Local ", p_cdc->line_state); return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false; } @@ -322,6 +323,7 @@ bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding) TU_VERIFY(p_cdc); *line_coding = p_cdc->line_coding; + TU_LOG_LINE_CODING("CDCh Get ", p_cdc->line_coding); return true; } @@ -440,7 +442,7 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) case FTDI_SIO_SET_BAUD_RATE: // convert from divisor to baudrate is not supported - p_cdc->line_coding.bit_rate = _ftdi_requested_baud; + p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested; break; default: break; @@ -465,12 +467,6 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) break; #endif - #if CFG_TUH_CDC_CH34X - case SERIAL_DRIVER_CH34X: - TU_ASSERT(false, ); // see special ch34x_control_complete function - break; - #endif - default: break; } } @@ -487,7 +483,7 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; if ( complete_cb ) { - return driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data); + TU_VERIFY(driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data)); }else { // blocking xfer_result_t result = XFER_RESULT_INVALID; @@ -501,8 +497,10 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c TU_VERIFY(ret && result == XFER_RESULT_SUCCESS); p_cdc->line_state = (uint8_t) line_state; - return true; } + TU_LOG_CONTROL_LINE_STATE("CDCh Set ", p_cdc->line_state); + + return true; } bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { @@ -511,7 +509,7 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; if ( complete_cb ) { - return driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data); + TU_VERIFY(driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data)); }else { // blocking xfer_result_t result = XFER_RESULT_INVALID; @@ -525,23 +523,24 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete TU_VERIFY(ret && result == XFER_RESULT_SUCCESS); p_cdc->line_coding.bit_rate = baudrate; - return true; } + TU_LOG_BAUDRATE("CDCh Set ", p_cdc->line_coding.bit_rate); + + return true; } bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); - // only ACM support this set line coding request - TU_VERIFY(p_cdc && p_cdc->serial_drid == SERIAL_DRIVER_ACM); - TU_VERIFY(p_cdc->acm_capability.support_line_request); + TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); + cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; if ( complete_cb ) { - return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data); - }else { + TU_VERIFY(driver->set_line_coding(p_cdc, line_coding, complete_cb, user_data)); + } else { // blocking xfer_result_t result = XFER_RESULT_INVALID; - bool ret = acm_set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result); + bool ret = driver->set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result); if (user_data) { // user_data is not NULL, return result via user_data @@ -551,8 +550,10 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, TU_VERIFY(ret && result == XFER_RESULT_SUCCESS); p_cdc->line_coding = *line_coding; - return true; } + TU_LOG_LINE_CODING("CDCh Set ", p_cdc->line_coding); + + return true; } //--------------------------------------------------------------------+ @@ -684,13 +685,8 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d { return acm_open(daddr, itf_desc, max_len); } -<<<<<<< HEAD #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X - else if ( 0xff == itf_desc->bInterfaceClass ) -======= - #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X else if ( TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass ) ->>>>>>> remotes/hathach/master { uint16_t vid, pid; TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid)); @@ -816,6 +812,8 @@ static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint1 TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const *) p_desc)); } + TU_LOG_DRV("[%u] CDCh ACM opened\r\n", daddr); + return true; } @@ -852,6 +850,12 @@ static void acm_process_config(tuh_xfer_t* xfer) TU_ATTR_FALLTHROUGH; case CONFIG_ACM_COMPLETE: + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + TU_LOG_LINE_CODING("CDCh ACM Init ", p_cdc->line_coding); + #endif + #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + TU_LOG_CONTROL_LINE_STATE("CDCh ACM Init", p_cdc->line_state); + #endif // itf_num+1 to account for data interface as well set_config_complete(p_cdc, idx, itf_num+1); break; @@ -893,6 +897,7 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_st static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_DRV("CDC ACM Set Line Conding\r\n"); + TU_VERIFY(p_cdc->acm_capability.support_line_request); tusb_control_request_t const request = { .bmRequestType_bit = { @@ -994,6 +999,12 @@ static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, u return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data); } +static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + TU_ASSERT(false, false); // TODO + return false; +} + static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_DRV("CDC FTDI Set Control Line State\r\n"); @@ -1035,7 +1046,7 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor); p_cdc->user_control_cb = complete_cb; - _ftdi_requested_baud = baudrate; + p_cdc->baudrate_requested = baudrate; TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, complete_cb ? cdch_internal_control_complete : NULL, user_data)); @@ -1088,6 +1099,14 @@ static void ftdi_process_config(tuh_xfer_t* xfer) { case CONFIG_FTDI_COMPLETE: set_config_complete(p_cdc, idx, itf_num); + #if 0 // TODO set data format + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + TU_LOG_LINE_CODING("CDCh FTDI Init ", p_cdc->line_coding); + #endif + #endif + #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + TU_LOG_CONTROL_LINE_STATE("CDCh FTDI Init ", p_cdc->line_state); + #endif break; default: @@ -1166,6 +1185,12 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe return cp210x_set_request(p_cdc, CP210X_IFC_ENABLE, enabled, NULL, 0, complete_cb, user_data); } +static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + TU_ASSERT(false, false); // TODO + return false; +} + static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_DRV("CDC CP210x Set BaudRate = %lu\r\n", baudrate); uint32_t baud_le = tu_htole32(baudrate); @@ -1224,6 +1249,12 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { case CONFIG_CP210X_COMPLETE: set_config_complete(p_cdc, idx, itf_num); + #if defined(CFG_TUH_CDC_LINE_CODING_ON_ENUM) && 0 // skip for now + TU_LOG_LINE_CODING("CDCh CP210x Init ", p_cdc->line_coding); + #endif + #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + TU_LOG_CONTROL_LINE_STATE("CDCh CP210x Init ", p_cdc->line_state); + #endif break; default: break; @@ -1233,20 +1264,19 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { #endif //--------------------------------------------------------------------+ -// CH34x +// CH34x (CH340 & CH341) //--------------------------------------------------------------------+ #if CFG_TUH_CDC_CH34X +#define CH34X_LOGS false + enum { - CONFIG_CH34X_STEP1 = 0, - CONFIG_CH34X_STEP2, - CONFIG_CH34X_STEP3, - CONFIG_CH34X_STEP4, - CONFIG_CH34X_STEP5, - CONFIG_CH34X_STEP6, - CONFIG_CH34X_STEP7, - CONFIG_CH34X_STEP8, + CONFIG_CH34X_READ_VERSION = 0, + CONFIG_CH34X_SERIAL_INIT, + CONFIG_CH34X_SPECIAL_REG_WRITE, + CONFIG_CH34X_FLOW_CONTROL, + CONFIG_CH34X_MODEM_CONTROL, CONFIG_CH34X_COMPLETE }; @@ -1259,17 +1289,22 @@ static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, u cdch_interface_t *p_cdc = make_new_itf ( daddr, itf_desc ); TU_VERIFY ( p_cdc ); - TU_LOG_DRV ( "CH34x opened\r\n" ); + p_cdc->serial_drid = SERIAL_DRIVER_CH34X; // endpoint pair tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next ( itf_desc ); // data endpoints expected to be in pairs - return open_ep_stream_pair ( p_cdc, desc_ep ); + TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep), false); + + TU_LOG_DRV("[%u] CDCh CH34x opened\r\n", daddr); + + return true; } -static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, uint16_t index, + uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { tusb_control_request_t const request_setup = { .bmRequestType_bit = { @@ -1297,212 +1332,66 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint .setup = &request_setup, .buffer = enum_buf, .complete_cb = complete_cb, - // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber - .user_data = (uintptr_t)( ( p_cdc->bInterfaceNumber & 0xff ) << 8 ) | ( user_data & 0xff ) + .user_data = user_data }; return tuh_control_xfer ( &xfer ); - return false; } -static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +static bool ch34x_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { return ch34x_set_request ( p_cdc, TUSB_DIR_OUT, request, value, index, /* buffer */ NULL, /* length */ 0, complete_cb, user_data ); } -static bool ch341_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +static bool ch34x_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, + uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { return ch34x_set_request ( p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize, complete_cb, user_data ); } -static int32_t ch341_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +static bool ch34x_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { - return ch341_control_out ( p_cdc, CH341_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data ); + return ch34x_control_out ( p_cdc, CH34X_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data ); } -static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ - return ch341_control_in ( p_cdc, CH341_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data ); -} +//static bool ch34x_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, +// uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +//{ +// return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data ); +//} -/* - * The device line speed is given by the following equation: - * - * baudrate = 48000000 / (2^(12 - 3 * ps - fact) * div), where - * - * 0 <= ps <= 3, - * 0 <= fact <= 1, - * 2 <= div <= 256 if fact = 0, or - * 9 <= div <= 256 if fact = 1 - */ -// calculate baudrate devisors -// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c -static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) +uint8_t ch34x_xfer_get_itf_num ( tuh_xfer_t* xfer ) +// CH34x needs a special handling to get bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber +// CH340 and CH341 derivates have always only one interface, so it's OK to check only daddr { - uint32_t fact, div, clk_div; - bool force_fact0 = false; - int32_t ps; - static const uint32_t ch341_min_rates[] = { - CH341_MIN_RATE(0), - CH341_MIN_RATE(1), - CH341_MIN_RATE(2), - CH341_MIN_RATE(3), - }; - - /* - * Clamp to supported range, this makes the (ps < 0) and (div < 2) - * sanity checks below redundant. - */ - inline uint32_t max ( uint32_t val, uint32_t maxval ) { return val > maxval ? val : maxval; } - inline uint32_t min ( uint32_t val, uint32_t minval ) { return val < minval ? val : minval; } - inline uint32_t clamp_val ( uint32_t val, uint32_t minval, uint32_t maxval ) { return min ( max ( val, minval ), maxval ); } - speed = clamp_val(speed, CH341_MIN_BPS, CH341_MAX_BPS); - - /* - * Start with highest possible base clock (fact = 1) that will give a - * divisor strictly less than 512. - */ - fact = 1; - for (ps = 3; ps >= 0; ps--) { - if (speed > ch341_min_rates[ps]) - break; - } - - if (ps < 0) - return -EINVAL; - - /* Determine corresponding divisor, rounding down. */ - clk_div = CH341_CLK_DIV(ps, fact); - div = CH341_CLKRATE / (clk_div * speed); - - /* Some devices require a lower base clock if ps < 3. */ - if (ps < 3 && (p_cdc->ch34x.quirks & CH341_QUIRK_LIMITED_PRESCALER)) - force_fact0 = true; - - /* Halve base clock (fact = 0) if required. */ - if (div < 9 || div > 255 || force_fact0) { - div /= 2; - clk_div *= 2; - fact = 0; - } - - if (div < 2) - return -EINVAL; - - /* - * Pick next divisor if resulting rate is closer to the requested one, - * scale up to avoid rounding errors on low rates. - */ - if (16 * CH341_CLKRATE / (clk_div * div) - 16 * speed >= - 16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1))) - div++; - - /* - * Prefer lower base clock (fact = 0) if even divisor. - * - * Note that this makes the receiver more tolerant to errors. - */ - if (fact == 1 && div % 2 == 0) { - div /= 2; - fact = 0; - } - - return (0x100 - div) << 8 | fact << 2 | ps; -} - -// set baudrate (low level) -// do not confuse with ch34x_set_baudrate -// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c -static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ - int val; - - if (!baud_rate) - return -EINVAL; - - val = ch341_get_divisor(p_cdc, baud_rate); - if (val < 0) - return -EINVAL; - - /* - * CH341A buffers data until a full endpoint-size packet (32 bytes) - * has been received unless bit 7 is set. - * - * At least one device with version 0x27 appears to have this bit - * inverted. - */ - if ( p_cdc->ch34x.version > 0x27 ) - val |= BIT(7); - - return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data ); -} - -// set lcr register -// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c -static int32_t ch341_set_lcr ( cdch_interface_t* p_cdc, uint8_t lcr, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ - /* - * Chip versions before version 0x30 as read using - * CH341_REQ_READ_VERSION used separate registers for line control - * (stop bits, parity and word length). Version 0x30 and above use - * CH341_REG_LCR only and CH341_REG_LCR2 is always set to zero. - */ - if ( p_cdc->ch34x.version < 0x30 ) - return 0; - - return ch341_write_reg ( p_cdc, CH341_REG_LCR2 << 8 | CH341_REG_LCR, lcr, complete_cb, user_data ); -} - -// set handshake (modem controls) -// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c -static int32_t ch341_set_handshake ( cdch_interface_t* p_cdc, uint8_t control, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ - return ch341_control_out ( p_cdc, CH341_REQ_MODEM_CTRL, /* value */ ~control, /* index */ 0, complete_cb, user_data ); -} - -// detect quirks (special versions of CH34x) -// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c -static int32_t ch341_detect_quirks ( tuh_xfer_t* xfer, cdch_interface_t* p_cdc, uint8_t step, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ - /* - * A subset of CH34x devices does not support all features. The - * prescaler is limited and there is no support for sending a RS232 - * break condition. A read failure when trying to set up the latter is - * used to detect these devices. - */ - switch ( step ) + for ( uint8_t i=0; ich34x.quirks = 0; - return ch341_read_reg_request ( p_cdc, CH341_REG_BREAK, buffer, buffersize, complete_cb, user_data ); - break; - case 2: - if ( xfer->result != XFER_RESULT_SUCCESS ) - p_cdc->ch34x.quirks |= CH341_QUIRK_LIMITED_PRESCALER | CH341_QUIRK_SIMULATE_BREAK; - return true; - break; - default: - TU_ASSERT ( false ); // suspicious step - break; + const cdch_interface_t* p_cdc = &cdch_data[i]; + if ( p_cdc->daddr == xfer->daddr ) return p_cdc->bInterfaceNumber; } + + return INTERFACE_INVALID_NUMBER; } // internal control complete to update state such as line state, encoding -// CH34x needs a special interface recovery due to abnormal wIndex usage -static void ch34x_control_complete(tuh_xfer_t* xfer) +static void ch34x_control_complete ( tuh_xfer_t* xfer ) { - uint8_t const itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 ); + uint8_t const itf_num = ch34x_xfer_get_itf_num ( xfer ); uint8_t const idx = tuh_cdc_itf_get_index ( xfer->daddr, itf_num ); cdch_interface_t *p_cdc = get_itf ( idx ); + uint16_t value = tu_le16toh ( xfer->setup->wValue ); TU_ASSERT ( p_cdc, ); TU_ASSERT ( p_cdc->serial_drid == SERIAL_DRIVER_CH34X, ); // ch34x_control_complete is only used for CH34x - if (xfer->result == XFER_RESULT_SUCCESS) { - switch (xfer->setup->bRequest) { - case CH341_REQ_WRITE_REG: { // register write request - switch ( tu_le16toh ( xfer->setup->wValue ) ) { - case ( CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER ): { // baudrate write - p_cdc->line_coding.bit_rate = p_cdc->ch34x.baud_rate; + if ( xfer->result == XFER_RESULT_SUCCESS ) { + switch ( xfer->setup->bRequest ) { + case CH34X_REQ_WRITE_REG: { // register write request + switch ( value ) { + case ( 0x1312 ): { // baudrate write + p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested; + #if CH34X_LOGS + TU_LOG_BAUDRATE("CDCh CH34x Control Complete ", p_cdc->line_coding.bit_rate); + #endif break; } default: { @@ -1512,6 +1401,20 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) } break; } + case CH34X_REQ_MODEM_CTRL: { // set modem controls RTS/DTR request + if ( ~value & CH34X_BIT_RTS ) + p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS; + else + p_cdc->line_state &= ~CDC_CONTROL_LINE_STATE_RTS; + if ( ~value & CH34X_BIT_DTR ) + p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR; + else + p_cdc->line_state &= ~CDC_CONTROL_LINE_STATE_DTR; + #if CH34X_LOGS + TU_LOG_CONTROL_LINE_STATE("CDCh CH34x Control Complete ", p_cdc->line_state); + #endif + break; + } default: { TU_ASSERT(false, ); // unexpected request break; @@ -1523,118 +1426,161 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) } } -static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) // do not confuse with ch341_set_baudrate +static bool ch34x_get_factor_divisor ( uint32_t baval, uint8_t *factor, uint8_t *divisor ) +{ // calc baudrate factor and divisor + uint8_t a; + uint8_t b; + uint32_t c; + + switch (baval) { + case 921600: + a = 0xf3; + b = 7; + break; + case 307200: + a = 0xd9; + b = 7; + break; + default: + if (baval > 6000000 / 255) { + b = 3; + c = 6000000; + } else if (baval > 750000 / 255) { + b = 2; + c = 750000; + } else if (baval > 93750 / 255) { + b = 1; + c = 93750; + } else { + b = 0; + c = 11719; + } + a = (unsigned char)(c / baval); + if (a == 0 || a == 0xFF) + return false; + if ((c / a - baval) > (baval - c / (a + 1))) + a++; + a = 256 - a; + break; + } + *factor = a; + *divisor = b; + + return true; +} + +static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG_DRV("CDC CH34x Set BaudRate = %lu\r\n", baudrate); - uint32_t baud_le = tu_htole32(baudrate); - p_cdc->ch34x.baud_rate = baudrate; + TU_ASSERT(false, false); // TODO + return false; +} + +static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +{ + p_cdc->baudrate_requested = baudrate; p_cdc->user_control_cb = complete_cb; - return ch341_set_baudrate ( p_cdc, baud_le, complete_cb ? ch34x_control_complete : NULL, user_data ); + uint8_t factor, divisor; + TU_ASSERT ( ch34x_get_factor_divisor ( baudrate, &factor, &divisor ), false ); + TU_ASSERT ( ch34x_write_reg ( p_cdc, /* reg */ 0x1312, /* value */ (uint16_t)factor << 8 | 0x80 | divisor, + complete_cb ? ch34x_control_complete : NULL, user_data ), false ); + + return true; } static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { - TU_LOG_DRV("CDC CH34x Set Control Line State\r\n"); - // todo later - return false; + p_cdc->user_control_cb = complete_cb; + uint16_t control = 0; + if ( line_state & CDC_CONTROL_LINE_STATE_RTS ) + control |= CH34X_BIT_RTS; + if ( line_state & CDC_CONTROL_LINE_STATE_DTR ) + control |= CH34X_BIT_DTR; + TU_ASSERT ( ch34x_control_out ( p_cdc, /* request */ CH34X_REQ_MODEM_CTRL, /* value */ (uint8_t)~control, + /* index */ 0, complete_cb ? ch34x_control_complete : NULL, user_data ), false ); + return true; } static void ch34x_process_config ( tuh_xfer_t* xfer ) { - uintptr_t const state = xfer->user_data & 0xff; - // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber - uint8_t const itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 ); - uint8_t const idx = tuh_cdc_itf_get_index ( xfer->daddr, itf_num ); - cdch_interface_t *p_cdc = get_itf ( idx ); - uint8_t buffer [ CH34X_BUFFER_SIZE ]; - cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; + uint8_t const itf_num = ch34x_xfer_get_itf_num ( xfer ); + uintptr_t const state = xfer->user_data; + uint8_t const idx = tuh_cdc_itf_get_index ( xfer->daddr, itf_num ); + cdch_interface_t *p_cdc = get_itf ( idx ); + cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; + uint8_t buffer[2]; TU_ASSERT ( p_cdc, ); - if ( state == 0 ) { - // defaults - p_cdc->ch34x.baud_rate = DEFAULT_BAUD_RATE; - p_cdc->ch34x.mcr = 0; - p_cdc->ch34x.msr = 0; - p_cdc->ch34x.quirks = 0; - p_cdc->ch34x.version = 0; - /* - * Some CH340 devices appear unable to change the initial LCR - * settings, so set a sane 8N1 default. - */ - p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX | CH341_LCR_CS8; - } - // This process flow has been taken over from Linux driver /drivers/usb/serial/ch341.c switch ( state ) { - case CONFIG_CH34X_STEP1: // request version read - TU_ASSERT ( ch341_control_in ( p_cdc, /* request */ CH341_REQ_READ_VERSION, /* value */ 0, /* index */ 0, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP2 ), ); - break; - case CONFIG_CH34X_STEP2: // handle version read data, request to init CH34x - p_cdc->ch34x.version = xfer->buffer[0]; - TU_LOG_DRV ( "Chip version=%02x\r\n", p_cdc->ch34x.version ); - TU_ASSERT ( ch341_control_out ( p_cdc, /* request */ CH341_REQ_SERIAL_INIT, /* value */ 0, /* index */ 0, ch34x_process_config, CONFIG_CH34X_STEP3 ), ); - break; - case CONFIG_CH34X_STEP3: // set baudrate with default values (see above) - TU_ASSERT ( ch341_set_baudrate ( p_cdc, p_cdc->ch34x.baud_rate, ch34x_process_config, CONFIG_CH34X_STEP4 ) > 0, ); - break; - case CONFIG_CH34X_STEP4: // set line controls with default values (see above) - TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_STEP5 ) > 0, ); - break; - case CONFIG_CH34X_STEP5: // set handshake RTS/DTR - TU_ASSERT ( ch341_set_handshake ( p_cdc, p_cdc->ch34x.mcr, ch34x_process_config, CONFIG_CH34X_STEP6 ) > 0, ); - break; - case CONFIG_CH34X_STEP6: // detect quirks step 1 - TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 1, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP7 ) > 0, ); - break; - case CONFIG_CH34X_STEP7: // detect quirks step 2 and set baudrate with configured values - TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 2, NULL, 0, NULL, 0 ) > 0, ); -#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - TU_ASSERT ( ch34x_set_baudrate ( p_cdc, line_coding.bit_rate, ch34x_process_config, CONFIG_CH34X_STEP8 ), ); -#else - TU_ATTR_FALLTHROUGH; -#endif + case CONFIG_CH34X_READ_VERSION: // request version read + #if CH34X_LOGS + TU_LOG_DRV ( "[%u] CDCh CH34x Process Config started\r\n", p_cdc->daddr ); + #endif + TU_ASSERT ( ch34x_control_in ( p_cdc, /* request */ CH34X_REQ_READ_VERSION, /* value */ 0, + /* index */ 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT ), ); break; - case CONFIG_CH34X_STEP8: // set data/stop bit quantities, parity -#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX; + case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate + uint8_t version = xfer->buffer[0]; + #if CH34X_LOGS + TU_LOG_DRV ( "[%u] CDCh CH34x Chip version=%02x\r\n", p_cdc->daddr, version ); + #endif + // only versions >= 0x30 are tested, below 0x30 seems having other programming, see WCH vendor, linux kernel and FreeBSD drivers + TU_ASSERT ( version >= 0x30, ); + uint8_t factor, divisor; + TU_ASSERT ( ch34x_get_factor_divisor ( line_coding.bit_rate, &factor, &divisor ), ); + uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX; switch ( line_coding.data_bits ) { case 5: - p_cdc->ch34x.lcr |= CH341_LCR_CS5; + lcr |= CH34X_LCR_CS5; break; case 6: - p_cdc->ch34x.lcr |= CH341_LCR_CS6; + lcr |= CH34X_LCR_CS6; break; case 7: - p_cdc->ch34x.lcr |= CH341_LCR_CS7; + lcr |= CH34X_LCR_CS7; break; case 8: - p_cdc->ch34x.lcr |= CH341_LCR_CS8; + lcr |= CH34X_LCR_CS8; break; default: TU_ASSERT ( false, ); // not supported data_bits - p_cdc->ch34x.lcr |= CH341_LCR_CS8; + lcr |= CH34X_LCR_CS8; break; } if ( line_coding.parity != CDC_LINE_CODING_PARITY_NONE ) { - p_cdc->ch34x.lcr |= CH341_LCR_ENABLE_PAR; + lcr |= CH34X_LCR_ENABLE_PAR; if ( line_coding.parity == CDC_LINE_CODING_PARITY_EVEN || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE ) - p_cdc->ch34x.lcr |= CH341_LCR_PAR_EVEN; + lcr |= CH34X_LCR_PAR_EVEN; if ( line_coding.parity == CDC_LINE_CODING_PARITY_MARK || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE ) - p_cdc->ch34x.lcr |= CH341_LCR_MARK_SPACE; + lcr |= CH34X_LCR_MARK_SPACE; } TU_ASSERT ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2, ); // not supported 1.5 stop bits if ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2 ) - p_cdc->ch34x.lcr |= CH341_LCR_STOP_BITS_2; - TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_COMPLETE ) > 0, ); -#else - TU_ATTR_FALLTHROUGH; -#endif + lcr |= CH34X_LCR_STOP_BITS_2; + TU_ASSERT ( ch34x_control_out ( p_cdc, /* request */ CH34X_REQ_SERIAL_INIT, /* value */ (uint16_t)lcr << 8 | 0x9c, + /* index */ (uint16_t)factor << 8 | 0x80 | divisor, ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE ), ); + break; + } + case CONFIG_CH34X_SPECIAL_REG_WRITE: // do special reg write, purpose unknown, overtaken from WCH driver + TU_ASSERT ( ch34x_write_reg ( p_cdc, /* reg */ 0x0f2c, /* value */ 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL ), ); + break; + case CONFIG_CH34X_FLOW_CONTROL: // no hardware flow control + TU_ASSERT ( ch34x_write_reg ( p_cdc, /* reg */ 0x2727, /* value */ 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL ), ); + break; + case CONFIG_CH34X_MODEM_CONTROL: // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT) + TU_ASSERT ( ch34x_set_modem_ctrl ( p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE ), ); + break; + case CONFIG_CH34X_COMPLETE: + p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete + #if CH34X_LOGS + TU_LOG_DRV("CDCh CH34x Process Config Complete\r\n"); + TU_LOG_LINE_CODING(" ", p_cdc->line_coding); + TU_LOG_CONTROL_LINE_STATE(" ", p_cdc->line_state); + #endif + set_config_complete ( p_cdc, idx, itf_num ); + break; + default: + TU_ASSERT ( false, ); break; - case CONFIG_CH34X_COMPLETE: - set_config_complete ( p_cdc, idx, itf_num ); - break; - default: - TU_ASSERT ( false, ); - break; } } diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 9e5edd94e..8e3a2352a 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -37,7 +37,7 @@ // Class Driver Configuration //--------------------------------------------------------------------+ -// Set Line Control state on enumeration/mounted: DTR ( bit 0), RTS (bit 1) +// Set Line Control state on enumeration/mounted, refer enums CDC_CONTROL_LINE_STATE_RTS, CDC_CONTROL_LINE_STATE_DTR #ifndef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM #define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM 0 #endif @@ -142,7 +142,7 @@ bool tuh_cdc_read_clear (uint8_t idx); // - The function will return true if transfer is successful, false otherwise. //--------------------------------------------------------------------+ -// Request to Set Control Line State: DTR (bit 0), RTS (bit 1) +// Request to Set Control Line State, refer enums CDC_CONTROL_LINE_STATE_RTS, CDC_CONTROL_LINE_STATE_DTR bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); // Request to set baudrate diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h index 94e18b252..262e012fd 100644 --- a/src/class/cdc/serial/ch34x.h +++ b/src/class/cdc/serial/ch34x.h @@ -1,7 +1,7 @@ /* * The MIT License (MIT) * - * Copyright (c) 2023 Heiko Kuester (tinyusb.org) + * Copyright (c) 2023 IngHK Heiko Kuester (tinyusb.org) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,87 +27,34 @@ #ifndef _CH34X_H_ #define _CH34X_H_ -#include - -#define BIT(nr) ( (uint32_t)1 << (nr) ) - -#define CH34X_BUFFER_SIZE 2 - -// The following defines have been taken over from Linux driver /drivers/usb/serial/ch341.c - -#define DEFAULT_BAUD_RATE 9600 - -/* flags for IO-Bits */ -#define CH341_BIT_RTS (1 << 6) -#define CH341_BIT_DTR (1 << 5) - -/******************************/ -/* interrupt pipe definitions */ -/******************************/ -/* always 4 interrupt bytes */ -/* first irq byte normally 0x08 */ -/* second irq byte base 0x7d + below */ -/* third irq byte base 0x94 + below */ -/* fourth irq byte normally 0xee */ - -/* second interrupt byte */ -#define CH341_MULT_STAT 0x04 /* multiple status since last interrupt event */ - -/* status returned in third interrupt answer byte, inverted in data - from irq */ -#define CH341_BIT_CTS 0x01 -#define CH341_BIT_DSR 0x02 -#define CH341_BIT_RI 0x04 -#define CH341_BIT_DCD 0x08 -#define CH341_BITS_MODEM_STAT 0x0f /* all bits */ - -/* Break support - the information used to implement this was gleaned from - * the Net/FreeBSD uchcom.c driver by Takanori Watanabe. Domo arigato. - */ +// set line_coding @ enumeration +#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM +#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM +#else // this default is necessary to work properly +#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X { 9600, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } +#endif // USB requests -#define CH341_REQ_READ_VERSION 0x5F // dec 95 -#define CH341_REQ_WRITE_REG 0x9A -#define CH341_REQ_READ_REG 0x95 -#define CH341_REQ_SERIAL_INIT 0xA1 -#define CH341_REQ_MODEM_CTRL 0xA4 +#define CH34X_REQ_READ_VERSION 0x5F // dec 95 +#define CH34X_REQ_WRITE_REG 0x9A // dec 154 +#define CH34X_REQ_READ_REG 0x95 // dec 149 +#define CH34X_REQ_SERIAL_INIT 0xA1 // dec 161 +#define CH34X_REQ_MODEM_CTRL 0xA4 // dev 164 -// CH34x registers -#define CH341_REG_BREAK 0x05 -#define CH341_REG_PRESCALER 0x12 -#define CH341_REG_DIVISOR 0x13 -#define CH341_REG_LCR 0x18 -#define CH341_REG_LCR2 0x25 - -#define CH341_NBREAK_BITS 0x01 +// modem control bits +#define CH34X_BIT_RTS ( 1 << 6 ) +#define CH34X_BIT_DTR ( 1 << 5 ) // line control bits -#define CH341_LCR_ENABLE_RX 0x80 -#define CH341_LCR_ENABLE_TX 0x40 -#define CH341_LCR_MARK_SPACE 0x20 -#define CH341_LCR_PAR_EVEN 0x10 -#define CH341_LCR_ENABLE_PAR 0x08 -#define CH341_LCR_STOP_BITS_2 0x04 -#define CH341_LCR_CS8 0x03 -#define CH341_LCR_CS7 0x02 -#define CH341_LCR_CS6 0x01 -#define CH341_LCR_CS5 0x00 - -#define CH341_QUIRK_LIMITED_PRESCALER BIT(0) -#define CH341_QUIRK_SIMULATE_BREAK BIT(1) - -#define CH341_CLKRATE 48000000 -#define CH341_CLK_DIV(ps, fact) (1 << (12 - 3 * (ps) - (fact))) -#define CH341_MIN_RATE(ps) (CH341_CLKRATE / (CH341_CLK_DIV((ps), 1) * 512)) - -/* Supported range is 46 to 3000000 bps. */ -#define CH341_MIN_BPS DIV_ROUND_UP(CH341_CLKRATE, CH341_CLK_DIV(0, 0) * 256) -#define CH341_MAX_BPS (CH341_CLKRATE / (CH341_CLK_DIV(3, 0) * 2)) - -#define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP -#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) - -// error codes -#define EINVAL 22 /* Invalid argument */ +#define CH34X_LCR_ENABLE_RX 0x80 +#define CH34X_LCR_ENABLE_TX 0x40 +#define CH34X_LCR_MARK_SPACE 0x20 +#define CH34X_LCR_PAR_EVEN 0x10 +#define CH34X_LCR_ENABLE_PAR 0x08 +#define CH34X_LCR_STOP_BITS_2 0x04 +#define CH34X_LCR_CS8 0x03 +#define CH34X_LCR_CS7 0x02 +#define CH34X_LCR_CS6 0x01 +#define CH34X_LCR_CS5 0x00 #endif /* _CH34X_H_ */ -- cgit v1.3.1 From 07e3d5c69192b1c45d52fc9760ab0ee65d8b0f0c Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 16 Jan 2024 13:16:53 +0700 Subject: fix number of endpoint for ch340x, also open notification even not used for now --- src/class/cdc/cdc_host.c | 67 +++++++++++++++++++++++--------------------- src/class/cdc/serial/ch34x.h | 6 ++-- 2 files changed, 38 insertions(+), 35 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 91e35ec8c..f7213d558 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -471,9 +471,9 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; - if ( complete_cb ) { + if (complete_cb) { return driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data); - }else { + } else { // blocking xfer_result_t result = XFER_RESULT_INVALID; bool ret = driver->set_control_line_state(p_cdc, line_state, complete_cb, (uintptr_t) &result); @@ -494,9 +494,9 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; - if ( complete_cb ) { + if (complete_cb) { return driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data); - }else { + } else { // blocking xfer_result_t result = XFER_RESULT_INVALID; bool ret = driver->set_baudrate(p_cdc, baudrate, complete_cb, (uintptr_t) &result); @@ -512,16 +512,15 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete } } -bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); // only ACM support this set line coding request TU_VERIFY(p_cdc && p_cdc->serial_drid == SERIAL_DRIVER_ACM); TU_VERIFY(p_cdc->acm_capability.support_line_request); - if ( complete_cb ) { + if (complete_cb) { return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data); - }else { + } else { // blocking xfer_result_t result = XFER_RESULT_INVALID; bool ret = acm_set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result); @@ -711,7 +710,6 @@ static bool acm_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint1 cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY(p_cdc); - p_cdc->serial_drid = SERIAL_DRIVER_ACM; //------------- Control Interface -------------// @@ -881,7 +879,6 @@ static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint TU_VERIFY(p_cdc); TU_LOG_DRV("FTDI opened\r\n"); - p_cdc->serial_drid = SERIAL_DRIVER_FTDI; // endpoint pair @@ -921,8 +918,7 @@ static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, u return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data); } -static bool -ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_DRV("CDC FTDI Set Control Line State\r\n"); p_cdc->user_control_cb = complete_cb; TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, @@ -1171,26 +1167,34 @@ enum { CONFIG_CH34X_COMPLETE }; -static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len ) { - // CH34x Interface includes 1 vendor interface + 3 bulk endpoints - TU_VERIFY ( itf_desc->bNumEndpoints == 3 ); - TU_VERIFY ( sizeof ( tusb_desc_interface_t ) + 2 * sizeof ( tusb_desc_endpoint_t ) <= max_len ); +static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) { + // CH34x Interface includes 1 vendor interface + 2 bulk + 1 interrupt endpoints + TU_VERIFY (itf_desc->bNumEndpoints == 3); + TU_VERIFY (sizeof(tusb_desc_interface_t) + 3 * sizeof(tusb_desc_endpoint_t) <= max_len); - cdch_interface_t *p_cdc = make_new_itf ( daddr, itf_desc ); - TU_VERIFY ( p_cdc ); + cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc); + TU_VERIFY (p_cdc); - TU_LOG_DRV ( "CH34x opened\r\n" ); + TU_LOG_DRV ("CH34x opened\r\n"); p_cdc->serial_drid = SERIAL_DRIVER_CH34X; - // endpoint pair - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next ( itf_desc ); + tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(itf_desc); // data endpoints expected to be in pairs - return open_ep_stream_pair ( p_cdc, desc_ep ); + TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep)); + desc_ep += 2; + + // Interrupt endpoint: not used for now + TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(desc_ep) && + TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer); + TU_ASSERT(tuh_edpt_open(daddr, desc_ep)); + p_cdc->ep_notif = desc_ep->bEndpointAddress; + + return true; } -static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ +static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, + uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { tusb_control_request_t const request_setup = { .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_DEVICE, @@ -1198,17 +1202,17 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint .direction = direction & 0x01u }, .bRequest = request, - .wValue = tu_htole16 ( value ), - .wIndex = tu_htole16 ( index ), - .wLength = tu_htole16 ( length ) + .wValue = tu_htole16 (value), + .wIndex = tu_htole16 (index), + .wLength = tu_htole16 (length) }; // use usbh enum buf since application variable does not live long enough uint8_t* enum_buf = NULL; - if ( buffer && length > 0 ) { + if (buffer && length > 0) { enum_buf = usbh_get_enum_buf(); - tu_memcpy_s ( enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length ); + tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length); } tuh_xfer_t xfer = { @@ -1218,11 +1222,10 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint .buffer = enum_buf, .complete_cb = complete_cb, // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber - .user_data = (uintptr_t)( ( p_cdc->bInterfaceNumber & 0xff ) << 8 ) | ( user_data & 0xff ) + .user_data = (uintptr_t) ((p_cdc->bInterfaceNumber & 0xff) << 8) | (user_data & 0xff) }; - return tuh_control_xfer ( &xfer ); - return false; + return tuh_control_xfer(&xfer); } static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h index 4a5e61bbd..cc3ac99fe 100644 --- a/src/class/cdc/serial/ch34x.h +++ b/src/class/cdc/serial/ch34x.h @@ -1,7 +1,7 @@ /* * The MIT License (MIT) * - * Copyright (c) 2023 Heiko Kuester (tinyusb.org) + * Copyright (c) 2023 Heiko Kuester * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,6 +34,7 @@ #define CH34X_BUFFER_SIZE 2 // The following defines have been taken over from Linux driver /drivers/usb/serial/ch341.c +// Note: updated driver can also be found in https://github.com/WCHSoftGroup/ch341ser_linux/tree/main/driver #define DEFAULT_BAUD_RATE 9600 @@ -53,8 +54,7 @@ /* second interrupt byte */ #define CH341_MULT_STAT 0x04 /* multiple status since last interrupt event */ -/* status returned in third interrupt answer byte, inverted in data - from irq */ +/* status returned in third interrupt answer byte, inverted in data from irq */ #define CH341_BIT_CTS 0x01 #define CH341_BIT_DSR 0x02 #define CH341_BIT_RI 0x04 -- cgit v1.3.1 From 46ac03ba8537a32ae2bf1f7d864879657b696f81 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 16 Jan 2024 17:45:16 +0700 Subject: change code style --- src/class/cdc/cdc_host.c | 97 +++++++++++++++++++++++------------------------- 1 file changed, 46 insertions(+), 51 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 8ef26a7d9..5541b5dee 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1291,25 +1291,22 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) { if (xfer->result == XFER_RESULT_SUCCESS) { switch (xfer->setup->bRequest) { - case CH34X_REQ_WRITE_REG: { // register write request + case CH34X_REQ_WRITE_REG: + // register write request switch (value) { - case (0x1312): { // baudrate write + case (0x1312): + // baudrate write p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested; - #if CH34X_LOGS - TU_LOG_BAUDRATE("CDCh CH34x Control Complete ", p_cdc->line_coding.bit_rate); - #endif break; - } - default: { + default: TU_ASSERT(false,); // unexpected register write break; - } } break; - } - case CH34X_REQ_MODEM_CTRL: { // set modem controls RTS/DTR request + case CH34X_REQ_MODEM_CTRL: + // set modem controls RTS/DTR request if (~value & CH34X_BIT_RTS) { p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS; } else { @@ -1322,16 +1319,11 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) { p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_DTR; } - #if CH34X_LOGS - TU_LOG_CONTROL_LINE_STATE("CDCh CH34x Control Complete ", p_cdc->line_state); - #endif break; - } - default: { + default: TU_ASSERT(false,); // unexpected request break; - } } xfer->complete_cb = p_cdc->user_control_cb; @@ -1393,33 +1385,31 @@ static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t con return false; } -static bool -ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, - uintptr_t user_data) { +static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->baudrate_requested = baudrate; p_cdc->user_control_cb = complete_cb; uint8_t factor, divisor; - TU_ASSERT (ch34x_get_factor_divisor(baudrate, &factor, &divisor), false); + TU_ASSERT (ch34x_get_factor_divisor(baudrate, &factor, &divisor)); uint16_t const value = (uint16_t ) (factor << 8 | 0x80 | divisor); - TU_ASSERT ( - ch34x_write_reg(p_cdc, /* reg */ 0x1312, /* value */ value, - complete_cb ? ch34x_control_complete : NULL, user_data), false); + TU_ASSERT (ch34x_write_reg(p_cdc, 0x1312, value, + complete_cb ? ch34x_control_complete : NULL, user_data)); return true; } -static bool -ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, - uintptr_t user_data) { +static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; uint16_t control = 0; - if (line_state & CDC_CONTROL_LINE_STATE_RTS) + if (line_state & CDC_CONTROL_LINE_STATE_RTS) { control |= CH34X_BIT_RTS; - if (line_state & CDC_CONTROL_LINE_STATE_DTR) + } + if (line_state & CDC_CONTROL_LINE_STATE_DTR) { control |= CH34X_BIT_DTR; - TU_ASSERT ( - ch34x_control_out(p_cdc, /* request */ CH34X_REQ_MODEM_CTRL, /* value */ (uint8_t) ~control, - /* index */ 0, complete_cb ? ch34x_control_complete : NULL, user_data), false); + } + TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, (uint8_t) ~control, 0, + complete_cb ? ch34x_control_complete : NULL, user_data)); return true; } @@ -1437,9 +1427,9 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { #if CH34X_LOGS TU_LOG_DRV ( "[%u] CDCh CH34x Process Config started\r\n", p_cdc->daddr ); #endif - TU_ASSERT (ch34x_control_in(p_cdc, /* request */ CH34X_REQ_READ_VERSION, /* value */ 0, - /* index */ 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),); + TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),); break; + case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate uint8_t version = xfer->buffer[0]; #if CH34X_LOGS @@ -1468,46 +1458,51 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { lcr |= CH34X_LCR_CS8; break; } + if (line_coding.parity != CDC_LINE_CODING_PARITY_NONE) { lcr |= CH34X_LCR_ENABLE_PAR; if (line_coding.parity == CDC_LINE_CODING_PARITY_EVEN || - line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) + line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) { lcr |= CH34X_LCR_PAR_EVEN; + } if (line_coding.parity == CDC_LINE_CODING_PARITY_MARK || - line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) + line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) { lcr |= CH34X_LCR_MARK_SPACE; + } } TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2,); // not supported 1.5 stop bits - if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2) + if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2) { lcr |= CH34X_LCR_STOP_BITS_2; - TU_ASSERT (ch34x_control_out(p_cdc, /* request */ CH34X_REQ_SERIAL_INIT, /* value */ - (uint16_t) (lcr << 8 | 0x9c), - /* index */ (uint16_t) (factor << 8 | 0x80 | divisor), ch34x_process_config, - CONFIG_CH34X_SPECIAL_REG_WRITE),); + } + TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor), + ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),); break; } - case CONFIG_CH34X_SPECIAL_REG_WRITE: // do special reg write, purpose unknown, overtaken from WCH driver - TU_ASSERT (ch34x_write_reg(p_cdc, /* reg */ 0x0f2c, /* value */ 0x0007, ch34x_process_config, - CONFIG_CH34X_FLOW_CONTROL),); + + case CONFIG_CH34X_SPECIAL_REG_WRITE: + // do special reg write, purpose unknown, overtaken from WCH driver + TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),); break; - case CONFIG_CH34X_FLOW_CONTROL: // no hardware flow control - TU_ASSERT (ch34x_write_reg(p_cdc, /* reg */ 0x2727, /* value */ 0x0000, ch34x_process_config, - CONFIG_CH34X_MODEM_CONTROL),); + + case CONFIG_CH34X_FLOW_CONTROL: + // no hardware flow control + TU_ASSERT (ch34x_write_reg(p_cdc, 0x2727, 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),); break; - case CONFIG_CH34X_MODEM_CONTROL: // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT) - TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, - CONFIG_CH34X_COMPLETE),); + + case CONFIG_CH34X_MODEM_CONTROL: + // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT) + TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE),); break; + case CONFIG_CH34X_COMPLETE: p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete #if CH34X_LOGS TU_LOG_DRV("CDCh CH34x Process Config Complete\r\n"); - TU_LOG_LINE_CODING(" ", p_cdc->line_coding); - TU_LOG_CONTROL_LINE_STATE(" ", p_cdc->line_state); #endif set_config_complete(p_cdc, idx, itf_num); break; + default: TU_ASSERT (false,); break; -- cgit v1.3.1 From 482a8068a51025ee8c31ccdb4355801c185172cc Mon Sep 17 00:00:00 2001 From: IngHK Date: Tue, 16 Jan 2024 14:51:04 +0100 Subject: change code style and code cleanup --- src/class/cdc/cdc_host.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 5541b5dee..4cecc79a1 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1260,13 +1260,13 @@ static bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, uint16_t } static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data); + return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, value, complete_cb, user_data); } //static bool ch34x_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, // uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) //{ -// return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data ); +// return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data ); //} uint8_t ch34x_xfer_get_itf_num(tuh_xfer_t* xfer) { @@ -1327,7 +1327,9 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) { } xfer->complete_cb = p_cdc->user_control_cb; - if (xfer->complete_cb)xfer->complete_cb(xfer); + if (xfer->complete_cb) { + xfer->complete_cb(xfer); + } } } @@ -1363,8 +1365,12 @@ static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* d c = 11719; } a = (unsigned char) (c / baval); - if (a == 0 || a == 0xFF) return false; - if ((c / a - baval) > (baval - c / (a + 1))) a++; + if (a == 0 || a == 0xFF) { + return false; + } + if ((c / a - baval) > (baval - c / (a + 1))) { + a++; + } a = (uint8_t) (256 - a); break; } @@ -1425,7 +1431,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { switch (state) { case CONFIG_CH34X_READ_VERSION: // request version read #if CH34X_LOGS - TU_LOG_DRV ( "[%u] CDCh CH34x Process Config started\r\n", p_cdc->daddr ); + TU_LOG_DRV ( "[%u] CDCh CH34x Process Config started\r\n", p_cdc->daddr ); #endif TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),); break; @@ -1433,7 +1439,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate uint8_t version = xfer->buffer[0]; #if CH34X_LOGS - TU_LOG_DRV ( "[%u] CDCh CH34x Chip version=%02x\r\n", p_cdc->daddr, version ); + TU_LOG_DRV("[%u] CDCh CH34x Chip version=%02x\r\n", p_cdc->daddr, version); #endif // only versions >= 0x30 are tested, below 0x30 seems having other programming, see WCH vendor, linux kernel and FreeBSD drivers TU_ASSERT (version >= 0x30,); @@ -1470,8 +1476,8 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { lcr |= CH34X_LCR_MARK_SPACE; } } - TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits == - CDC_LINE_CODING_STOP_BITS_2,); // not supported 1.5 stop bits + TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || + line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2,); // 1.5 stop bits not supported if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2) { lcr |= CH34X_LCR_STOP_BITS_2; } @@ -1498,7 +1504,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { case CONFIG_CH34X_COMPLETE: p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete #if CH34X_LOGS - TU_LOG_DRV("CDCh CH34x Process Config Complete\r\n"); + TU_LOG_DRV("CDCh CH34x Process Config Complete\r\n"); #endif set_config_complete(p_cdc, idx, itf_num); break; -- cgit v1.3.1 From f221c0fb6683fc552febbb9a52300d66f031d275 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 17 Jan 2024 14:45:09 +0700 Subject: more clean up --- src/class/cdc/cdc_host.c | 28 ++++++++++------------------ src/class/cdc/serial/ch34x.h | 13 +++++++++++++ 2 files changed, 23 insertions(+), 18 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 4cecc79a1..faee062cf 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -670,6 +670,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d } static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num) { + TU_LOG_DRV("CDCh Set Configure complete\r\n"); if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx); // Prepare for incoming data @@ -1176,8 +1177,6 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { #if CFG_TUH_CDC_CH34X -#define CH34X_LOGS false - enum { CONFIG_CH34X_READ_VERSION = 0, CONFIG_CH34X_SERIAL_INIT, @@ -1247,14 +1246,13 @@ static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_ return tuh_control_xfer(&xfer); } -static bool ch34x_control_out(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - return ch34x_set_request(p_cdc, TUSB_DIR_OUT, request, value, index, /* buffer */ NULL, /* length */ 0, complete_cb, user_data); +static inline bool ch34x_control_out(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + return ch34x_set_request(p_cdc, TUSB_DIR_OUT, request, value, index, NULL, 0, complete_cb, user_data); } -static bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, - uint8_t* buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, - uintptr_t user_data) { +static inline bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, + uint8_t* buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return ch34x_set_request(p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize, complete_cb, user_data); } @@ -1425,27 +1423,24 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t* p_cdc = get_itf(idx); cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; - uint8_t buffer[2]; + uint8_t buffer[2]; // TODO remove TU_ASSERT (p_cdc,); switch (state) { case CONFIG_CH34X_READ_VERSION: // request version read - #if CH34X_LOGS - TU_LOG_DRV ( "[%u] CDCh CH34x Process Config started\r\n", p_cdc->daddr ); - #endif + TU_LOG_DRV("[%u] CDCh CH34x attempt to read version\r\n", p_cdc->daddr); TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),); break; case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate uint8_t version = xfer->buffer[0]; - #if CH34X_LOGS - TU_LOG_DRV("[%u] CDCh CH34x Chip version=%02x\r\n", p_cdc->daddr, version); - #endif + TU_LOG_DRV("[%u] CDCh CH34x Chip version = %02x\r\n", p_cdc->daddr, version); // only versions >= 0x30 are tested, below 0x30 seems having other programming, see WCH vendor, linux kernel and FreeBSD drivers TU_ASSERT (version >= 0x30,); uint8_t factor, divisor; TU_ASSERT (ch34x_get_factor_divisor(line_coding.bit_rate, &factor, &divisor),); uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX; + switch (line_coding.data_bits) { case 5: lcr |= CH34X_LCR_CS5; @@ -1503,9 +1498,6 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { case CONFIG_CH34X_COMPLETE: p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete - #if CH34X_LOGS - TU_LOG_DRV("CDCh CH34x Process Config Complete\r\n"); - #endif set_config_complete(p_cdc, idx, itf_num); break; diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h index 557e093a9..54b5b3560 100644 --- a/src/class/cdc/serial/ch34x.h +++ b/src/class/cdc/serial/ch34x.h @@ -27,6 +27,10 @@ #ifndef _CH34X_H_ #define _CH34X_H_ +// There is no official documentation for the CH34x chips. Reference can be found +// - https://github.com/WCHSoftGroup/ch341ser_linux +// - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/ch341.c + // set line_coding @ enumeration #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM #define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM @@ -41,6 +45,15 @@ #define CH34X_REQ_SERIAL_INIT 0xA1 // dec 161 #define CH34X_REQ_MODEM_CTRL 0xA4 // dev 164 +#define CH34X_REG_BREAK 0x05 +#define CH34X_REG_PRESCALER 0x12 +#define CH34X_REG_DIVISOR 0x13 +#define CH34X_REG_LCR 0x18 +#define CH34X_REG_LCR2 0x25 +#define CH34X_REG_MCR_MSR 0x06 +#define CH34X_REG_MCR_MSR2 0x07 +#define CH34X_NBREAK_BITS 0x01 + // modem control bits #define CH34X_BIT_RTS ( 1 << 6 ) #define CH34X_BIT_DTR ( 1 << 5 ) -- cgit v1.3.1 From 3968a0fff87c794266284af7901e334d122e894c Mon Sep 17 00:00:00 2001 From: IngHK Date: Wed, 17 Jan 2024 16:04:31 +0100 Subject: implemented ch34x_set_line_coding() and some code cleanup --- src/class/cdc/cdc_host.c | 177 ++++++++++++++++++++++++++----------------- src/class/cdc/serial/ch34x.h | 7 ++ 2 files changed, 116 insertions(+), 68 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index faee062cf..45a03a31d 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1179,7 +1179,7 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { enum { CONFIG_CH34X_READ_VERSION = 0, - CONFIG_CH34X_SERIAL_INIT, + CONFIG_CH34X_SET_LINE_CODING, CONFIG_CH34X_SPECIAL_REG_WRITE, CONFIG_CH34X_FLOW_CONTROL, CONFIG_CH34X_MODEM_CONTROL, @@ -1292,11 +1292,10 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) { case CH34X_REQ_WRITE_REG: // register write request switch (value) { - case (0x1312): + case 0x1312: // baudrate write p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested; break; - default: TU_ASSERT(false,); // unexpected register write break; @@ -1310,13 +1309,60 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) { } else { p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_RTS; } - if (~value & CH34X_BIT_DTR) { p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR; } else { p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_DTR; } + break; + case CH34X_REQ_SERIAL_INIT: + // serial init request (set line coding incl. baudrate) + p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested; + uint8_t lcr = (uint8_t) (value >> 8); + TU_ASSERT (lcr & CH34X_LCR_ENABLE_RX && lcr & CH34X_LCR_ENABLE_TX,); // both have to be enabled + switch (lcr & CH34X_LCR_CS_MASK) { + case CH34X_LCR_CS5: + p_cdc->line_coding.data_bits = 5; + break; + case CH34X_LCR_CS6: + p_cdc->line_coding.data_bits = 6; + break; + case CH34X_LCR_CS7: + p_cdc->line_coding.data_bits = 7; + break; + case CH34X_LCR_CS8: + p_cdc->line_coding.data_bits = 8; + break; + default: + TU_ASSERT (false,); // unexpected data_bits lcr + break; + } + if (lcr & CH34X_LCR_STOP_BITS_2) { + p_cdc->line_coding.stop_bits = CDC_LINE_CODING_STOP_BITS_2; + } else { + p_cdc->line_coding.stop_bits = CDC_LINE_CODING_STOP_BITS_1; + } + switch (lcr & CH34X_LCR_PAR_MASK) { + case 0: + p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_NONE; + break; + case CH34X_LCR_ENABLE_PAR: + p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_ODD; + break; + case CH34X_LCR_ENABLE_PAR | CH34X_LCR_PAR_EVEN: + p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_EVEN; + break; + case CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE: + p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_MARK; + break; + case CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN: + p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_SPACE; + break; + default: + TU_ASSERT (false,); // unexpected parity lcr + break; + } break; default: @@ -1378,15 +1424,57 @@ static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* d return true; } +// calc lcr register value (data bits, parity, stop bits) +static bool ch34x_get_lcr(cdc_line_coding_t const* line_coding, uint8_t *lcr) { + *lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX; + switch (line_coding->data_bits) { + case 5: + *lcr |= CH34X_LCR_CS5; + break; + case 6: + *lcr |= CH34X_LCR_CS6; + break; + case 7: + *lcr |= CH34X_LCR_CS7; + break; + case 8: + *lcr |= CH34X_LCR_CS8; + break; + default: + TU_ASSERT (false); // data_bits not supported + break; + } + TU_ASSERT (line_coding->parity == CDC_LINE_CODING_PARITY_NONE || // supported parities + line_coding->parity == CDC_LINE_CODING_PARITY_ODD || line_coding->parity == CDC_LINE_CODING_PARITY_EVEN || + line_coding->parity == CDC_LINE_CODING_PARITY_MARK || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE); + if (line_coding->parity != CDC_LINE_CODING_PARITY_NONE) { + *lcr |= CH34X_LCR_ENABLE_PAR; + if (line_coding->parity == CDC_LINE_CODING_PARITY_EVEN || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE) { + *lcr |= CH34X_LCR_PAR_EVEN; + } + if (line_coding->parity == CDC_LINE_CODING_PARITY_MARK || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE) { + *lcr |= CH34X_LCR_MARK_SPACE; + } + } + TU_ASSERT (line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_1 || + line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_2); // not supported 1.5 stop bits + if (line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_2) { + *lcr |= CH34X_LCR_STOP_BITS_2; + } + + return true; +} + static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - // TODO implement later - (void) p_cdc; - (void) line_coding; - (void) complete_cb; - (void) user_data; - - return false; + p_cdc->baudrate_requested = line_coding->bit_rate; + p_cdc->user_control_cb = complete_cb; + uint8_t factor, divisor, lcr; + TU_ASSERT (ch34x_get_factor_divisor(line_coding->bit_rate, &factor, &divisor)); + TU_ASSERT (ch34x_get_lcr(line_coding, &lcr)); + TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor), + complete_cb ? ch34x_control_complete : NULL, user_data)); + return true; } static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, @@ -1398,7 +1486,6 @@ static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, uint16_t const value = (uint16_t ) (factor << 8 | 0x80 | divisor); TU_ASSERT (ch34x_write_reg(p_cdc, 0x1312, value, complete_cb ? ch34x_control_complete : NULL, user_data)); - return true; } @@ -1427,82 +1514,36 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { TU_ASSERT (p_cdc,); switch (state) { - case CONFIG_CH34X_READ_VERSION: // request version read - TU_LOG_DRV("[%u] CDCh CH34x attempt to read version\r\n", p_cdc->daddr); - TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),); + case CONFIG_CH34X_READ_VERSION: + // version read request + TU_LOG_DRV("[%u] CDCh CH34x attempt to read Chip Version\r\n", p_cdc->daddr); + TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SET_LINE_CODING),); break; - - case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate + case CONFIG_CH34X_SET_LINE_CODING: + // handle version read data, set CH34x line coding (incl. baudrate) uint8_t version = xfer->buffer[0]; - TU_LOG_DRV("[%u] CDCh CH34x Chip version = %02x\r\n", p_cdc->daddr, version); - // only versions >= 0x30 are tested, below 0x30 seems having other programming, see WCH vendor, linux kernel and FreeBSD drivers + TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version); + // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD TU_ASSERT (version >= 0x30,); - uint8_t factor, divisor; - TU_ASSERT (ch34x_get_factor_divisor(line_coding.bit_rate, &factor, &divisor),); - uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX; - - switch (line_coding.data_bits) { - case 5: - lcr |= CH34X_LCR_CS5; - break; - case 6: - lcr |= CH34X_LCR_CS6; - break; - case 7: - lcr |= CH34X_LCR_CS7; - break; - case 8: - lcr |= CH34X_LCR_CS8; - break; - default: - TU_ASSERT (false,); // not supported data_bits - lcr |= CH34X_LCR_CS8; - break; - } - - if (line_coding.parity != CDC_LINE_CODING_PARITY_NONE) { - lcr |= CH34X_LCR_ENABLE_PAR; - if (line_coding.parity == CDC_LINE_CODING_PARITY_EVEN || - line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) { - lcr |= CH34X_LCR_PAR_EVEN; - } - if (line_coding.parity == CDC_LINE_CODING_PARITY_MARK || - line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) { - lcr |= CH34X_LCR_MARK_SPACE; - } - } - TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || - line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2,); // 1.5 stop bits not supported - if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2) { - lcr |= CH34X_LCR_STOP_BITS_2; - } - TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor), - ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),); + TU_ASSERT (ch34x_set_line_coding(p_cdc, &line_coding, ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),); break; - } - case CONFIG_CH34X_SPECIAL_REG_WRITE: // do special reg write, purpose unknown, overtaken from WCH driver TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),); break; - case CONFIG_CH34X_FLOW_CONTROL: // no hardware flow control TU_ASSERT (ch34x_write_reg(p_cdc, 0x2727, 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),); break; - case CONFIG_CH34X_MODEM_CONTROL: // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT) TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE),); break; - case CONFIG_CH34X_COMPLETE: - p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete set_config_complete(p_cdc, idx, itf_num); break; - default: - TU_ASSERT (false,); + TU_ASSERT (false,); // something gone wrong, should never reached break; } } diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h index 54b5b3560..b4ed7420c 100644 --- a/src/class/cdc/serial/ch34x.h +++ b/src/class/cdc/serial/ch34x.h @@ -27,9 +27,13 @@ #ifndef _CH34X_H_ #define _CH34X_H_ +// For simplicity, only the name CH34X is used here, +// but specifically only CH340 and CH341 are supported. + // There is no official documentation for the CH34x chips. Reference can be found // - https://github.com/WCHSoftGroup/ch341ser_linux // - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/ch341.c +// - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uchcom.c // set line_coding @ enumeration #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM @@ -45,6 +49,7 @@ #define CH34X_REQ_SERIAL_INIT 0xA1 // dec 161 #define CH34X_REQ_MODEM_CTRL 0xA4 // dev 164 +// registers #define CH34X_REG_BREAK 0x05 #define CH34X_REG_PRESCALER 0x12 #define CH34X_REG_DIVISOR 0x13 @@ -64,10 +69,12 @@ #define CH34X_LCR_MARK_SPACE 0x20 #define CH34X_LCR_PAR_EVEN 0x10 #define CH34X_LCR_ENABLE_PAR 0x08 +#define CH34X_LCR_PAR_MASK 0x38 // all parity bits #define CH34X_LCR_STOP_BITS_2 0x04 #define CH34X_LCR_CS8 0x03 #define CH34X_LCR_CS7 0x02 #define CH34X_LCR_CS6 0x01 #define CH34X_LCR_CS5 0x00 +#define CH34X_LCR_CS_MASK 0x03 // all CSx bits #endif /* _CH34X_H_ */ -- cgit v1.3.1 From 30eb35f17f1baa4698da0cd45dbc3dff8906d7c0 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 19 Jan 2024 01:06:24 +0700 Subject: - revert the use of serial init for set line coding - update ch34x_get_lcr and ch34x_get_factor_divisor --- src/class/cdc/cdc_host.c | 146 ++++++++++++++++++++++++------------------- src/class/cdc/serial/ch34x.h | 6 ++ 2 files changed, 87 insertions(+), 65 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 45a03a31d..150ac21f2 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1179,7 +1179,7 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { enum { CONFIG_CH34X_READ_VERSION = 0, - CONFIG_CH34X_SET_LINE_CODING, + CONFIG_CH34X_SERIAL_INIT, CONFIG_CH34X_SPECIAL_REG_WRITE, CONFIG_CH34X_FLOW_CONTROL, CONFIG_CH34X_MODEM_CONTROL, @@ -1231,7 +1231,9 @@ static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_ if (buffer && length > 0) { enum_buf = usbh_get_enum_buf(); - tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length); + if (direction == TUSB_DIR_OUT) { + tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length); + } } tuh_xfer_t xfer = { @@ -1257,8 +1259,8 @@ static inline bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, ui complete_cb, user_data); } -static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, value, complete_cb, user_data); +static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, reg_value, complete_cb, user_data); } //static bool ch34x_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, @@ -1292,10 +1294,11 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) { case CH34X_REQ_WRITE_REG: // register write request switch (value) { - case 0x1312: + case CH34X_REG16_DIVISOR_PRESCALER: // baudrate write p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested; break; + default: TU_ASSERT(false,); // unexpected register write break; @@ -1309,6 +1312,7 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) { } else { p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_RTS; } + if (~value & CH34X_BIT_DTR) { p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR; } else { @@ -1377,8 +1381,8 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) { } } -// calc baudrate factor and divisor -static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* divisor) { +// calculate divisor and prescaler for baudrate, return it as 16-bit combined value +static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) { uint8_t a; uint8_t b; uint32_t c; @@ -1410,7 +1414,7 @@ static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* d } a = (unsigned char) (c / baval); if (a == 0 || a == 0xFF) { - return false; + return 0; } if ((c / a - baval) > (baval - c / (a + 1))) { a++; @@ -1418,74 +1422,75 @@ static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* d a = (uint8_t) (256 - a); break; } - *factor = a; - *divisor = b; - return true; + // reg divisor = a, reg prescaler = b + // According to linux code we need to set bit 7 of UCHCOM_REG_BPS_PRE, + // otherwise the chip will buffer data. + return (uint16_t) (a << 8 | 0x80 | b); } -// calc lcr register value (data bits, parity, stop bits) -static bool ch34x_get_lcr(cdc_line_coding_t const* line_coding, uint8_t *lcr) { - *lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX; - switch (line_coding->data_bits) { - case 5: - *lcr |= CH34X_LCR_CS5; - break; - case 6: - *lcr |= CH34X_LCR_CS6; - break; - case 7: - *lcr |= CH34X_LCR_CS7; +static inline uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits) { + uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX; + TU_VERIFY(data_bits >= 5, 0); + lcr |= (uint8_t) (data_bits - 5); + + if (parity) { + lcr |= CH34X_LCR_ENABLE_PAR; + } + switch(parity) { + case CDC_LINE_CODING_PARITY_EVEN: + lcr |= CH34X_LCR_PAR_EVEN; break; - case 8: - *lcr |= CH34X_LCR_CS8; + + case CDC_LINE_CODING_PARITY_MARK: + lcr |= CH34X_LCR_MARK_SPACE; break; - default: - TU_ASSERT (false); // data_bits not supported + + case CDC_LINE_CODING_PARITY_SPACE: + lcr |= CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN; break; + + default: break; } - TU_ASSERT (line_coding->parity == CDC_LINE_CODING_PARITY_NONE || // supported parities - line_coding->parity == CDC_LINE_CODING_PARITY_ODD || line_coding->parity == CDC_LINE_CODING_PARITY_EVEN || - line_coding->parity == CDC_LINE_CODING_PARITY_MARK || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE); - if (line_coding->parity != CDC_LINE_CODING_PARITY_NONE) { - *lcr |= CH34X_LCR_ENABLE_PAR; - if (line_coding->parity == CDC_LINE_CODING_PARITY_EVEN || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE) { - *lcr |= CH34X_LCR_PAR_EVEN; - } - if (line_coding->parity == CDC_LINE_CODING_PARITY_MARK || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE) { - *lcr |= CH34X_LCR_MARK_SPACE; - } - } - TU_ASSERT (line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_1 || - line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_2); // not supported 1.5 stop bits - if (line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_2) { - *lcr |= CH34X_LCR_STOP_BITS_2; + + // 1.5 stop bits not supported + TU_VERIFY(stop_bits != CDC_LINE_CODING_STOP_BITS_1_5, 0); + if (stop_bits == CDC_LINE_CODING_STOP_BITS_2) { + lcr |= CH34X_LCR_STOP_BITS_2; } - return true; + return lcr; } -static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->baudrate_requested = line_coding->bit_rate; - p_cdc->user_control_cb = complete_cb; - uint8_t factor, divisor, lcr; - TU_ASSERT (ch34x_get_factor_divisor(line_coding->bit_rate, &factor, &divisor)); - TU_ASSERT (ch34x_get_lcr(line_coding, &lcr)); - TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor), - complete_cb ? ch34x_control_complete : NULL, user_data)); - return true; -} +//static bool ch34x_set_line_data(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, +// tuh_xfer_cb_t complete_cb, uintptr_t user_data) { static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->baudrate_requested = baudrate; p_cdc->user_control_cb = complete_cb; - uint8_t factor, divisor; - TU_ASSERT (ch34x_get_factor_divisor(baudrate, &factor, &divisor)); - uint16_t const value = (uint16_t ) (factor << 8 | 0x80 | divisor); - TU_ASSERT (ch34x_write_reg(p_cdc, 0x1312, value, - complete_cb ? ch34x_control_complete : NULL, user_data)); + uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate); + TU_VERIFY(div_ps != 0); + TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps, + complete_cb ? ch34x_control_complete : NULL, user_data)); + + return true; +} + +static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +// p_cdc->baudrate_requested = line_coding->bit_rate; +// p_cdc->user_control_cb = complete_cb; +// uint8_t factor, divisor, lcr; +// TU_ASSERT (ch34x_get_factor_divisor(line_coding->bit_rate, &factor, &divisor)); +// TU_ASSERT (ch34x_get_lcr(line_coding, &lcr)); +// TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor), +// complete_cb ? ch34x_control_complete : NULL, user_data)); + (void) p_cdc; + (void) line_coding; + (void) complete_cb; + (void) user_data; + return true; } @@ -1515,35 +1520,46 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { switch (state) { case CONFIG_CH34X_READ_VERSION: - // version read request TU_LOG_DRV("[%u] CDCh CH34x attempt to read Chip Version\r\n", p_cdc->daddr); - TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SET_LINE_CODING),); + TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),); break; - case CONFIG_CH34X_SET_LINE_CODING: + + case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, set CH34x line coding (incl. baudrate) uint8_t version = xfer->buffer[0]; TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version); // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD TU_ASSERT (version >= 0x30,); - TU_ASSERT (ch34x_set_line_coding(p_cdc, &line_coding, ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),); + uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate); + TU_ASSERT(div_ps != 0, ); + + uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits); + TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps, + ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),); break; + } + case CONFIG_CH34X_SPECIAL_REG_WRITE: // do special reg write, purpose unknown, overtaken from WCH driver TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),); break; + case CONFIG_CH34X_FLOW_CONTROL: // no hardware flow control TU_ASSERT (ch34x_write_reg(p_cdc, 0x2727, 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),); break; + case CONFIG_CH34X_MODEM_CONTROL: // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT) TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE),); break; + case CONFIG_CH34X_COMPLETE: set_config_complete(p_cdc, idx, itf_num); break; + default: - TU_ASSERT (false,); // something gone wrong, should never reached + TU_ASSERT (false,); break; } } diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h index b4ed7420c..3f78a3007 100644 --- a/src/class/cdc/serial/ch34x.h +++ b/src/class/cdc/serial/ch34x.h @@ -59,6 +59,12 @@ #define CH34X_REG_MCR_MSR2 0x07 #define CH34X_NBREAK_BITS 0x01 +#define CH341_REG_0x0F 0x0F // undocumented register +#define CH341_REG_0x2C 0x2C // undocumented register +#define CH341_REG_0x27 0x27 // hardware flow control (cts/rts) + +#define CH34X_REG16_DIVISOR_PRESCALER TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER) + // modem control bits #define CH34X_BIT_RTS ( 1 << 6 ) #define CH34X_BIT_DTR ( 1 << 5 ) -- cgit v1.3.1 From c568a6793e99dde311802d4b4cb0633d2d6f5830 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 19 Jan 2024 12:14:45 +0700 Subject: - add requested line coding to make update data format easier - change ch34x_xfer_get_itf_num() to simply 0 --- src/class/cdc/cdc_host.c | 295 ++++++++++++++++++++++------------------------- 1 file changed, 136 insertions(+), 159 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 150ac21f2..3843a8edc 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -60,6 +60,11 @@ typedef struct { uint8_t line_state; // DTR (bit0), RTS (bit1) TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width + #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X + cdc_line_coding_t requested_line_coding; + // 1 byte padding + #endif + tuh_xfer_cb_t user_control_cb; struct { @@ -72,10 +77,6 @@ typedef struct { uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE]; } stream; - -#if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CH34X - uint32_t baudrate_requested; -#endif } cdch_interface_t; CFG_TUH_MEM_SECTION @@ -429,7 +430,7 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) { case FTDI_SIO_SET_BAUD_RATE: // convert from divisor to baudrate is not supported - p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested; + p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; break; default: break; @@ -968,7 +969,7 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor); p_cdc->user_control_cb = complete_cb; - p_cdc->baudrate_requested = baudrate; + p_cdc->requested_line_coding.bit_rate = baudrate; TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, complete_cb ? cdch_internal_control_complete : NULL, user_data)); @@ -1186,6 +1187,9 @@ enum { CONFIG_CH34X_COMPLETE }; +static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits); +static uint16_t ch34x_get_divisor_prescaler(uint32_t baval); + static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) { // CH34x Interface includes 1 vendor interface + 2 bulk + 1 interrupt endpoints TU_VERIFY (itf_desc->bNumEndpoints == 3); @@ -1269,20 +1273,10 @@ static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_ // return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data ); //} -uint8_t ch34x_xfer_get_itf_num(tuh_xfer_t* xfer) { -// CH34x needs a special handling to get bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber -// CH340 and CH341 derivates have always only one interface, so it's OK to check only daddr - for (uint8_t i = 0; i < CFG_TUH_CDC; i++) { - const cdch_interface_t* p_cdc = &cdch_data[i]; - if (p_cdc->daddr == xfer->daddr) return p_cdc->bInterfaceNumber; - } - - return INTERFACE_INVALID_NUMBER; -} - // internal control complete to update state such as line state, encoding static void ch34x_control_complete(tuh_xfer_t* xfer) { - uint8_t const itf_num = ch34x_xfer_get_itf_num(xfer); + // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber + uint8_t const itf_num = 0; uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t* p_cdc = get_itf(idx); uint16_t value = tu_le16toh (xfer->setup->wValue); @@ -1296,7 +1290,14 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) { switch (value) { case CH34X_REG16_DIVISOR_PRESCALER: // baudrate write - p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested; + p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; + break; + + case CH32X_REG16_LCR2_LCR: + // data format write + p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits; + p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity; + p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits; break; default: @@ -1305,68 +1306,26 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) { } break; - case CH34X_REQ_MODEM_CTRL: - // set modem controls RTS/DTR request - if (~value & CH34X_BIT_RTS) { + case CH34X_REQ_MODEM_CTRL: { + // set modem controls RTS/DTR request. Note: signals are inverted + uint16_t const modem_signal = ~value; + if (modem_signal & CH34X_BIT_RTS) { p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS; } else { - p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_RTS; + p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS; } - if (~value & CH34X_BIT_DTR) { + if (modem_signal & CH34X_BIT_DTR) { p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR; } else { - p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_DTR; + p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR; } break; + } case CH34X_REQ_SERIAL_INIT: // serial init request (set line coding incl. baudrate) - p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested; - uint8_t lcr = (uint8_t) (value >> 8); - TU_ASSERT (lcr & CH34X_LCR_ENABLE_RX && lcr & CH34X_LCR_ENABLE_TX,); // both have to be enabled - switch (lcr & CH34X_LCR_CS_MASK) { - case CH34X_LCR_CS5: - p_cdc->line_coding.data_bits = 5; - break; - case CH34X_LCR_CS6: - p_cdc->line_coding.data_bits = 6; - break; - case CH34X_LCR_CS7: - p_cdc->line_coding.data_bits = 7; - break; - case CH34X_LCR_CS8: - p_cdc->line_coding.data_bits = 8; - break; - default: - TU_ASSERT (false,); // unexpected data_bits lcr - break; - } - if (lcr & CH34X_LCR_STOP_BITS_2) { - p_cdc->line_coding.stop_bits = CDC_LINE_CODING_STOP_BITS_2; - } else { - p_cdc->line_coding.stop_bits = CDC_LINE_CODING_STOP_BITS_1; - } - switch (lcr & CH34X_LCR_PAR_MASK) { - case 0: - p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_NONE; - break; - case CH34X_LCR_ENABLE_PAR: - p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_ODD; - break; - case CH34X_LCR_ENABLE_PAR | CH34X_LCR_PAR_EVEN: - p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_EVEN; - break; - case CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE: - p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_MARK; - break; - case CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN: - p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_SPACE; - break; - default: - TU_ASSERT (false,); // unexpected parity lcr - break; - } + p_cdc->line_coding = p_cdc->requested_line_coding; break; default: @@ -1381,93 +1340,17 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) { } } -// calculate divisor and prescaler for baudrate, return it as 16-bit combined value -static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) { - uint8_t a; - uint8_t b; - uint32_t c; - - switch (baval) { - case 921600: - a = 0xf3; - b = 7; - break; - - case 307200: - a = 0xd9; - b = 7; - break; - - default: - if (baval > 6000000 / 255) { - b = 3; - c = 6000000; - } else if (baval > 750000 / 255) { - b = 2; - c = 750000; - } else if (baval > 93750 / 255) { - b = 1; - c = 93750; - } else { - b = 0; - c = 11719; - } - a = (unsigned char) (c / baval); - if (a == 0 || a == 0xFF) { - return 0; - } - if ((c / a - baval) > (baval - c / (a + 1))) { - a++; - } - a = (uint8_t) (256 - a); - break; - } - - // reg divisor = a, reg prescaler = b - // According to linux code we need to set bit 7 of UCHCOM_REG_BPS_PRE, - // otherwise the chip will buffer data. - return (uint16_t) (a << 8 | 0x80 | b); -} - -static inline uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits) { - uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX; - TU_VERIFY(data_bits >= 5, 0); - lcr |= (uint8_t) (data_bits - 5); - - if (parity) { - lcr |= CH34X_LCR_ENABLE_PAR; - } - switch(parity) { - case CDC_LINE_CODING_PARITY_EVEN: - lcr |= CH34X_LCR_PAR_EVEN; - break; - - case CDC_LINE_CODING_PARITY_MARK: - lcr |= CH34X_LCR_MARK_SPACE; - break; - - case CDC_LINE_CODING_PARITY_SPACE: - lcr |= CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN; - break; - - default: break; - } - - // 1.5 stop bits not supported - TU_VERIFY(stop_bits != CDC_LINE_CODING_STOP_BITS_1_5, 0); - if (stop_bits == CDC_LINE_CODING_STOP_BITS_2) { - lcr |= CH34X_LCR_STOP_BITS_2; - } - - return lcr; -} - -//static bool ch34x_set_line_data(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, +//static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, // tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +// uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits); +// TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr, +// complete_cb ? ch34x_control_complete : NULL, user_data)); +// return false; +//} static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->baudrate_requested = baudrate; + p_cdc->requested_line_coding.bit_rate = baudrate; p_cdc->user_control_cb = complete_cb; uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate); TU_VERIFY(div_ps != 0); @@ -1496,24 +1379,29 @@ static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t con static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_control_cb = complete_cb; - uint16_t control = 0; + uint8_t control = 0; if (line_state & CDC_CONTROL_LINE_STATE_RTS) { control |= CH34X_BIT_RTS; } if (line_state & CDC_CONTROL_LINE_STATE_DTR) { control |= CH34X_BIT_DTR; } - TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, (uint8_t) ~control, 0, + + // CH34x signals are inverted + control = ~control; + + p_cdc->user_control_cb = complete_cb; + TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0, complete_cb ? ch34x_control_complete : NULL, user_data)); return true; } static void ch34x_process_config(tuh_xfer_t* xfer) { - uint8_t const itf_num = ch34x_xfer_get_itf_num(xfer); - uintptr_t const state = xfer->user_data; + // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber + uint8_t const itf_num = 0; uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t* p_cdc = get_itf(idx); + uintptr_t const state = xfer->user_data; cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; uint8_t buffer[2]; // TODO remove TU_ASSERT (p_cdc,); @@ -1526,14 +1414,17 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, set CH34x line coding (incl. baudrate) - uint8_t version = xfer->buffer[0]; + uint8_t const version = xfer->buffer[0]; TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version); // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD TU_ASSERT (version >= 0x30,); + uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate); TU_ASSERT(div_ps != 0, ); uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits); + + // Init CH34x with line coding TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps, ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),); break; @@ -1541,6 +1432,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { case CONFIG_CH34X_SPECIAL_REG_WRITE: // do special reg write, purpose unknown, overtaken from WCH driver + p_cdc->line_coding = line_coding; TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),); break; @@ -1564,6 +1456,91 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { } } +//------------- CH34x helper -------------// + +// calculate divisor and prescaler for baudrate, return it as 16-bit combined value +static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) { + uint8_t a; + uint8_t b; + uint32_t c; + + switch (baval) { + case 921600: + a = 0xf3; + b = 7; + break; + + case 307200: + a = 0xd9; + b = 7; + break; + + default: + if (baval > 6000000 / 255) { + b = 3; + c = 6000000; + } else if (baval > 750000 / 255) { + b = 2; + c = 750000; + } else if (baval > 93750 / 255) { + b = 1; + c = 93750; + } else { + b = 0; + c = 11719; + } + a = (unsigned char) (c / baval); + if (a == 0 || a == 0xFF) { + return 0; + } + if ((c / a - baval) > (baval - c / (a + 1))) { + a++; + } + a = (uint8_t) (256 - a); + break; + } + + // reg divisor = a, reg prescaler = b + // According to linux code we need to set bit 7 of UCHCOM_REG_BPS_PRE, + // otherwise the chip will buffer data. + return (uint16_t) (a << 8 | 0x80 | b); +} + +// calculate lcr value from data coding +static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits) { + uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX; + TU_VERIFY(data_bits >= 5, 0); + lcr |= (uint8_t) (data_bits - 5); + + if (parity) { + lcr |= CH34X_LCR_ENABLE_PAR; + } + switch(parity) { + case CDC_LINE_CODING_PARITY_EVEN: + lcr |= CH34X_LCR_PAR_EVEN; + break; + + case CDC_LINE_CODING_PARITY_MARK: + lcr |= CH34X_LCR_MARK_SPACE; + break; + + case CDC_LINE_CODING_PARITY_SPACE: + lcr |= CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN; + break; + + default: break; + } + + // 1.5 stop bits not supported + TU_VERIFY(stop_bits != CDC_LINE_CODING_STOP_BITS_1_5, 0); + if (stop_bits == CDC_LINE_CODING_STOP_BITS_2) { + lcr |= CH34X_LCR_STOP_BITS_2; + } + + return lcr; +} + + #endif // CFG_TUH_CDC_CH34X #endif -- cgit v1.3.1 From 23c2d929a1bae39578b195c7c7b068fb718212bd Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 19 Jan 2024 12:40:37 +0700 Subject: refactor process_internal_control_complete() --- src/class/cdc/cdc_host.c | 142 +++++++++++++++++++++++------------------------ 1 file changed, 69 insertions(+), 73 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 3843a8edc..bfaa64a77 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -396,26 +396,23 @@ bool tuh_cdc_read_clear (uint8_t idx) { // Control Endpoint API //--------------------------------------------------------------------+ -// internal control complete to update state such as line state, encoding -static void cdch_internal_control_complete(tuh_xfer_t* xfer) { - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t* p_cdc = get_itf(idx); +static void process_internal_control_complete(cdch_interface_t* p_cdc, tuh_xfer_t* xfer) { TU_ASSERT(p_cdc, ); + uint16_t const value = tu_le16toh(xfer->setup->wValue); if (xfer->result == XFER_RESULT_SUCCESS) { switch (p_cdc->serial_drid) { case SERIAL_DRIVER_ACM: switch (xfer->setup->bRequest) { case CDC_REQUEST_SET_CONTROL_LINE_STATE: - p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue); + p_cdc->line_state = (uint8_t) value; break; case CDC_REQUEST_SET_LINE_CODING: { uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength)); memcpy(&p_cdc->line_coding, xfer->buffer, len); - } break; + } default: break; } @@ -425,11 +422,10 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) { case SERIAL_DRIVER_FTDI: switch (xfer->setup->bRequest) { case FTDI_SIO_MODEM_CTRL: - p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff); + p_cdc->line_state = (uint8_t) value; break; case FTDI_SIO_SET_BAUD_RATE: - // convert from divisor to baudrate is not supported p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; break; @@ -442,22 +438,62 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) { case SERIAL_DRIVER_CP210X: switch(xfer->setup->bRequest) { case CP210X_SET_MHS: - p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff); + p_cdc->line_state = (uint8_t) value; break; case CP210X_SET_BAUDRATE: { uint32_t baudrate; memcpy(&baudrate, xfer->buffer, sizeof(uint32_t)); p_cdc->line_coding.bit_rate = tu_le32toh(baudrate); - } break; + } + + default: break; } break; #endif #if CFG_TUH_CDC_CH34X case SERIAL_DRIVER_CH34X: - TU_ASSERT(false, ); // see special ch34x_control_complete function + switch (xfer->setup->bRequest) { + case CH34X_REQ_WRITE_REG: + // register write request + switch (value) { + case CH34X_REG16_DIVISOR_PRESCALER: + // baudrate + p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; + break; + + case CH32X_REG16_LCR2_LCR: + // data format + p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits; + p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity; + p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits; + break; + + default: break; + } + break; + + case CH34X_REQ_MODEM_CTRL: { + // set modem controls RTS/DTR request. Note: signals are inverted + uint16_t const modem_signal = ~value; + if (modem_signal & CH34X_BIT_RTS) { + p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS; + } else { + p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS; + } + + if (modem_signal & CH34X_BIT_DTR) { + p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR; + } else { + p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR; + } + break; + } + + default: break; + } break; #endif @@ -471,6 +507,15 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) { } } +// internal control complete to update state such as line state, encoding +static void cdch_internal_control_complete(tuh_xfer_t* xfer) { + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t* p_cdc = get_itf(idx); + + process_internal_control_complete(p_cdc, xfer); +} + bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); @@ -1279,70 +1324,16 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) { uint8_t const itf_num = 0; uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t* p_cdc = get_itf(idx); - uint16_t value = tu_le16toh (xfer->setup->wValue); - TU_ASSERT (p_cdc,); - TU_ASSERT (p_cdc->serial_drid == SERIAL_DRIVER_CH34X,); - - if (xfer->result == XFER_RESULT_SUCCESS) { - switch (xfer->setup->bRequest) { - case CH34X_REQ_WRITE_REG: - // register write request - switch (value) { - case CH34X_REG16_DIVISOR_PRESCALER: - // baudrate write - p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; - break; - - case CH32X_REG16_LCR2_LCR: - // data format write - p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits; - p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity; - p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits; - break; - - default: - TU_ASSERT(false,); // unexpected register write - break; - } - break; - - case CH34X_REQ_MODEM_CTRL: { - // set modem controls RTS/DTR request. Note: signals are inverted - uint16_t const modem_signal = ~value; - if (modem_signal & CH34X_BIT_RTS) { - p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS; - } else { - p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS; - } - - if (modem_signal & CH34X_BIT_DTR) { - p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR; - } else { - p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR; - } - break; - } - - case CH34X_REQ_SERIAL_INIT: - // serial init request (set line coding incl. baudrate) - p_cdc->line_coding = p_cdc->requested_line_coding; - break; - - default: - TU_ASSERT(false,); // unexpected request - break; - } - - xfer->complete_cb = p_cdc->user_control_cb; - if (xfer->complete_cb) { - xfer->complete_cb(xfer); - } - } + process_internal_control_complete(p_cdc, xfer); } //static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, // tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits); +// p_cdc->requested_line_coding.stop_bits = stop_bits; +// p_cdc->requested_line_coding.parity = parity; +// p_cdc->requested_line_coding.data_bits = data_bits; +// // TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr, // complete_cb ? ch34x_control_complete : NULL, user_data)); // return false; @@ -1350,16 +1341,21 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) { static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->requested_line_coding.bit_rate = baudrate; - p_cdc->user_control_cb = complete_cb; uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate); TU_VERIFY(div_ps != 0); + + p_cdc->requested_line_coding.bit_rate = baudrate; + p_cdc->user_control_cb = complete_cb; TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps, complete_cb ? ch34x_control_complete : NULL, user_data)); return true; } +//static void ch34x_set_line_coding_stage1(tuh_xfer_t* xfer) { +// +//} + static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // p_cdc->baudrate_requested = line_coding->bit_rate; -- cgit v1.3.1 From 98781bb903d94190d57ad4b9436a85a31d67404c Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 19 Jan 2024 15:58:05 +0700 Subject: - add ch34x_set_data_format() - add ch34x_set_line_coding() --- examples/host/cdc_msc_hid/src/cdc_app.c | 68 ++++++++++------------ src/class/cdc/cdc_host.c | 100 ++++++++++++++++++++++---------- src/class/cdc/serial/ch34x.h | 3 +- 3 files changed, 102 insertions(+), 69 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c index a1b26e49c..81052047c 100644 --- a/examples/host/cdc_msc_hid/src/cdc_app.c +++ b/examples/host/cdc_msc_hid/src/cdc_app.c @@ -27,20 +27,11 @@ #include "tusb.h" #include "bsp/board_api.h" -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM DECLARATION -//--------------------------------------------------------------------+ - - -//------------- IMPLEMENTATION -------------// - -size_t get_console_inputs(uint8_t* buf, size_t bufsize) -{ +size_t get_console_inputs(uint8_t* buf, size_t bufsize) { size_t count = 0; - while (count < bufsize) - { + while (count < bufsize) { int ch = board_getchar(); - if ( ch <= 0 ) break; + if (ch <= 0) break; buf[count] = (uint8_t) ch; count++; @@ -49,22 +40,18 @@ size_t get_console_inputs(uint8_t* buf, size_t bufsize) return count; } -void cdc_app_task(void) -{ - uint8_t buf[64+1]; // +1 for extra null character - uint32_t const bufsize = sizeof(buf)-1; +void cdc_app_task(void) { + uint8_t buf[64 + 1]; // +1 for extra null character + uint32_t const bufsize = sizeof(buf) - 1; uint32_t count = get_console_inputs(buf, bufsize); buf[count] = 0; // loop over all mounted interfaces - for(uint8_t idx=0; idx cdc interfaces - if (count) - { + if (count) { tuh_cdc_write(idx, buf, count); tuh_cdc_write_flush(idx); } @@ -72,11 +59,14 @@ void cdc_app_task(void) } } +//--------------------------------------------------------------------+ +// TinyUSB callbacks +//--------------------------------------------------------------------+ + // Invoked when received new data -void tuh_cdc_rx_cb(uint8_t idx) -{ - uint8_t buf[64+1]; // +1 for extra null character - uint32_t const bufsize = sizeof(buf)-1; +void tuh_cdc_rx_cb(uint8_t idx) { + uint8_t buf[64 + 1]; // +1 for extra null character + uint32_t const bufsize = sizeof(buf) - 1; // forward cdc interfaces -> console uint32_t count = tuh_cdc_read(idx, buf, bufsize); @@ -85,29 +75,31 @@ void tuh_cdc_rx_cb(uint8_t idx) printf((char*) buf); } -void tuh_cdc_mount_cb(uint8_t idx) -{ - tuh_itf_info_t itf_info = { 0 }; +// Invoked when a device with CDC interface is mounted +// idx is index of cdc interface in the internal pool. +void tuh_cdc_mount_cb(uint8_t idx) { + tuh_itf_info_t itf_info = {0}; tuh_cdc_itf_get_info(idx, &itf_info); - printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber); + printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, + itf_info.desc.bInterfaceNumber); #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration // otherwise you need to call tuh_cdc_set_line_coding() first - cdc_line_coding_t line_coding = { 0 }; - if ( tuh_cdc_get_local_line_coding(idx, &line_coding) ) - { + cdc_line_coding_t line_coding = {0}; + if (tuh_cdc_get_local_line_coding(idx, &line_coding)) { printf(" Baudrate: %lu, Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits); - printf(" Parity : %u, Data Width: %u\r\n", line_coding.parity , line_coding.data_bits); + printf(" Parity : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits); } #endif } -void tuh_cdc_umount_cb(uint8_t idx) -{ - tuh_itf_info_t itf_info = { 0 }; +// Invoked when a device with CDC interface is unmounted +void tuh_cdc_umount_cb(uint8_t idx) { + tuh_itf_info_t itf_info = {0}; tuh_cdc_itf_get_info(idx, &itf_info); - printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber); + printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, + itf_info.desc.bInterfaceNumber); } diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index bfaa64a77..37fa30982 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1327,48 +1327,88 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) { process_internal_control_complete(p_cdc, xfer); } -//static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, -// tuh_xfer_cb_t complete_cb, uintptr_t user_data) { -// uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits); -// p_cdc->requested_line_coding.stop_bits = stop_bits; -// p_cdc->requested_line_coding.parity = parity; -// p_cdc->requested_line_coding.data_bits = data_bits; -// -// TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr, -// complete_cb ? ch34x_control_complete : NULL, user_data)); -// return false; -//} +static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + p_cdc->requested_line_coding.stop_bits = stop_bits; + p_cdc->requested_line_coding.parity = parity; + p_cdc->requested_line_coding.data_bits = data_bits; + + uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits); + TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr, + complete_cb ? ch34x_control_complete : NULL, user_data)); + return true; +} -static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate); TU_VERIFY(div_ps != 0); + TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps, + complete_cb, user_data)); + return true; +} +static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->requested_line_coding.bit_rate = baudrate; p_cdc->user_control_cb = complete_cb; - TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps, - complete_cb ? ch34x_control_complete : NULL, user_data)); - + TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, baudrate, + complete_cb ? ch34x_control_complete : NULL, user_data)); return true; } -//static void ch34x_set_line_coding_stage1(tuh_xfer_t* xfer) { -// -//} +static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t* xfer) { + uint8_t const itf_num = 0; + uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t* p_cdc = get_itf(idx); + TU_ASSERT(p_cdc, ); + if (xfer->result == XFER_RESULT_SUCCESS) { + // stage 1 success, continue to stage 2 + p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; + TU_ASSERT(ch34x_set_data_format(p_cdc, p_cdc->requested_line_coding.stop_bits, p_cdc->requested_line_coding.parity, + p_cdc->requested_line_coding.data_bits, ch34x_control_complete, xfer->user_data), ); + } else { + // stage 1 failed, notify user + xfer->complete_cb = p_cdc->user_control_cb; + if (xfer->complete_cb) { + xfer->complete_cb(xfer); + } + } +} + +// 2 stages: set baudrate (stage1) + set data format (stage2) static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { -// p_cdc->baudrate_requested = line_coding->bit_rate; -// p_cdc->user_control_cb = complete_cb; -// uint8_t factor, divisor, lcr; -// TU_ASSERT (ch34x_get_factor_divisor(line_coding->bit_rate, &factor, &divisor)); -// TU_ASSERT (ch34x_get_lcr(line_coding, &lcr)); -// TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor), -// complete_cb ? ch34x_control_complete : NULL, user_data)); - (void) p_cdc; - (void) line_coding; - (void) complete_cb; - (void) user_data; + p_cdc->requested_line_coding = *line_coding; + p_cdc->user_control_cb = complete_cb; + + if (complete_cb) { + // stage 1 set baudrate + TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, line_coding->bit_rate, + ch34x_set_line_coding_stage1_complete, user_data)); + } else { + // sync call + xfer_result_t result; + + // stage 1 set baudrate + TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, line_coding->bit_rate, NULL, (uintptr_t) &result)); + TU_VERIFY(result == XFER_RESULT_SUCCESS); + p_cdc->line_coding.bit_rate = line_coding->bit_rate; + + // stage 2 set data format + TU_ASSERT(ch34x_set_data_format(p_cdc, line_coding->stop_bits, line_coding->parity, line_coding->data_bits, + NULL, (uintptr_t) &result)); + TU_VERIFY(result == XFER_RESULT_SUCCESS); + p_cdc->line_coding.stop_bits = line_coding->stop_bits; + p_cdc->line_coding.parity = line_coding->parity; + p_cdc->line_coding.data_bits = line_coding->data_bits; + + // update transfer result, user_data is expected to point to xfer_result_t + if (user_data) { + user_data = result; + } + } return true; } diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h index 3f78a3007..5def8d212 100644 --- a/src/class/cdc/serial/ch34x.h +++ b/src/class/cdc/serial/ch34x.h @@ -63,7 +63,8 @@ #define CH341_REG_0x2C 0x2C // undocumented register #define CH341_REG_0x27 0x27 // hardware flow control (cts/rts) -#define CH34X_REG16_DIVISOR_PRESCALER TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER) +#define CH34X_REG16_DIVISOR_PRESCALER TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER) +#define CH32X_REG16_LCR2_LCR TU_U16(CH34X_REG_LCR2, CH34X_REG_LCR) // modem control bits #define CH34X_BIT_RTS ( 1 << 6 ) -- cgit v1.3.1 From c196a2ed9cbd27188472d76ec428fdb24931d0b6 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 19 Jan 2024 16:04:30 +0700 Subject: move code around --- src/class/cdc/cdc_host.c | 94 +++++++++++++++++++++++++----------------------- 1 file changed, 49 insertions(+), 45 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 37fa30982..8965ee261 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1223,46 +1223,12 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { #if CFG_TUH_CDC_CH34X -enum { - CONFIG_CH34X_READ_VERSION = 0, - CONFIG_CH34X_SERIAL_INIT, - CONFIG_CH34X_SPECIAL_REG_WRITE, - CONFIG_CH34X_FLOW_CONTROL, - CONFIG_CH34X_MODEM_CONTROL, - CONFIG_CH34X_COMPLETE -}; - static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits); static uint16_t ch34x_get_divisor_prescaler(uint32_t baval); -static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) { - // CH34x Interface includes 1 vendor interface + 2 bulk + 1 interrupt endpoints - TU_VERIFY (itf_desc->bNumEndpoints == 3); - TU_VERIFY (sizeof(tusb_desc_interface_t) + 3 * sizeof(tusb_desc_endpoint_t) <= max_len); - - cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc); - TU_VERIFY (p_cdc); - - TU_LOG_DRV ("CH34x opened\r\n"); - p_cdc->serial_drid = SERIAL_DRIVER_CH34X; - - tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(itf_desc); - - // data endpoints expected to be in pairs - TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep)); - desc_ep += 2; - - // Interrupt endpoint: not used for now - TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(desc_ep) && - TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer); - TU_ASSERT(tuh_edpt_open(daddr, desc_ep)); - p_cdc->ep_notif = desc_ep->bEndpointAddress; - - return true; -} - +//------------- control requestt -------------// static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, - uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { tusb_control_request_t const request_setup = { .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_DEVICE, @@ -1318,6 +1284,17 @@ static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_ // return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data ); //} +static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate); + TU_VERIFY(div_ps != 0); + TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps, + complete_cb, user_data)); + return true; +} + +//------------- Driver API -------------// + // internal control complete to update state such as line state, encoding static void ch34x_control_complete(tuh_xfer_t* xfer) { // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber @@ -1339,15 +1316,6 @@ static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, ui return true; } -static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate); - TU_VERIFY(div_ps != 0); - TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps, - complete_cb, user_data)); - return true; -} - static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->requested_line_coding.bit_rate = baudrate; @@ -1432,6 +1400,42 @@ static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, return true; } +//------------- Enumeration -------------// +enum { + CONFIG_CH34X_READ_VERSION = 0, + CONFIG_CH34X_SERIAL_INIT, + CONFIG_CH34X_SPECIAL_REG_WRITE, + CONFIG_CH34X_FLOW_CONTROL, + CONFIG_CH34X_MODEM_CONTROL, + CONFIG_CH34X_COMPLETE +}; + +static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) { + // CH34x Interface includes 1 vendor interface + 2 bulk + 1 interrupt endpoints + TU_VERIFY (itf_desc->bNumEndpoints == 3); + TU_VERIFY (sizeof(tusb_desc_interface_t) + 3 * sizeof(tusb_desc_endpoint_t) <= max_len); + + cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc); + TU_VERIFY (p_cdc); + + TU_LOG_DRV ("CH34x opened\r\n"); + p_cdc->serial_drid = SERIAL_DRIVER_CH34X; + + tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(itf_desc); + + // data endpoints expected to be in pairs + TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep)); + desc_ep += 2; + + // Interrupt endpoint: not used for now + TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(desc_ep) && + TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer); + TU_ASSERT(tuh_edpt_open(daddr, desc_ep)); + p_cdc->ep_notif = desc_ep->bEndpointAddress; + + return true; +} + static void ch34x_process_config(tuh_xfer_t* xfer) { // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber uint8_t const itf_num = 0; -- cgit v1.3.1 From 55cb713264a1fe531b548a05290ee8fe1289828f Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 19 Jan 2024 16:56:32 +0700 Subject: - add new API tuh_cdc_set_data_format() - add typedef for cdc enum --- src/class/cdc/cdc.h | 20 +++++------ src/class/cdc/cdc_host.c | 90 ++++++++++++++++++++++++++++++++++++++++++------ src/class/cdc/cdc_host.h | 13 +++---- 3 files changed, 95 insertions(+), 28 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index deec32ae4..5cbd658fe 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -136,8 +136,7 @@ typedef enum{ //--------------------------------------------------------------------+ /// Communication Interface Management Element Request Codes -typedef enum -{ +typedef enum { CDC_REQUEST_SEND_ENCAPSULATED_COMMAND = 0x00, ///< is used to issue a command in the format of the supported control protocol of the Communications Class interface CDC_REQUEST_GET_ENCAPSULATED_RESPONSE = 0x01, ///< is used to request a response in the format of the supported control protocol of the Communications Class interface. CDC_REQUEST_SET_COMM_FEATURE = 0x02, @@ -180,39 +179,38 @@ typedef enum CDC_REQUEST_GET_ATM_VC_STATISTICS = 0x53, CDC_REQUEST_MDLM_SEMANTIC_MODEL = 0x60, -}cdc_management_request_t; +} cdc_management_request_t; -enum { +typedef enum { CDC_CONTROL_LINE_STATE_DTR = 0x01, CDC_CONTROL_LINE_STATE_RTS = 0x02, -}; +} cdc_control_line_state_t; -enum { +typedef enum { CDC_LINE_CODING_STOP_BITS_1 = 0, // 1 bit CDC_LINE_CODING_STOP_BITS_1_5 = 1, // 1.5 bits CDC_LINE_CODING_STOP_BITS_2 = 2, // 2 bits -}; +} cdc_line_coding_stopbits_t; // TODO Backward compatible for typos. Maybe removed in the future release #define CDC_LINE_CONDING_STOP_BITS_1 CDC_LINE_CODING_STOP_BITS_1 #define CDC_LINE_CONDING_STOP_BITS_1_5 CDC_LINE_CODING_STOP_BITS_1_5 #define CDC_LINE_CONDING_STOP_BITS_2 CDC_LINE_CODING_STOP_BITS_2 -enum { +typedef enum { CDC_LINE_CODING_PARITY_NONE = 0, CDC_LINE_CODING_PARITY_ODD = 1, CDC_LINE_CODING_PARITY_EVEN = 2, CDC_LINE_CODING_PARITY_MARK = 3, CDC_LINE_CODING_PARITY_SPACE = 4, -}; +} cdc_line_coding_parity_t; //--------------------------------------------------------------------+ // Management Element Notification (Notification Endpoint) //--------------------------------------------------------------------+ /// 6.3 Notification Codes -typedef enum -{ +typedef enum { CDC_NOTIF_NETWORK_CONNECTION = 0x00, ///< This notification allows the device to notify the host about network connection status. CDC_NOTIF_RESPONSE_AVAILABLE = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request. CDC_NOTIF_AUX_JACK_HOOK_STATE = 0x08, diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 8965ee261..f5182efc2 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -90,9 +90,10 @@ static cdch_interface_t cdch_data[CFG_TUH_CDC]; static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); static void acm_process_config(tuh_xfer_t* xfer); +static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool acm_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); //------------- FTDI prototypes -------------// #if CFG_TUH_CDC_FTDI @@ -100,15 +101,13 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfe static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST}; -// Store last request baudrate since divisor to baudrate is not easy -// static uint32_t _ftdi_requested_baud; - static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len); static void ftdi_process_config(tuh_xfer_t* xfer); +static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ftdi_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif //------------- CP210X prototypes -------------// @@ -120,9 +119,10 @@ static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIS static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); static void cp210x_process_config(tuh_xfer_t* xfer); +static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif //------------- CH34x prototypes -------------// @@ -131,16 +131,16 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_ static uint16_t const ch34x_vid_pid_list[][2] = {CFG_TUH_CDC_CH34X_VID_PID_LIST}; -static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len ); -static void ch34x_process_config ( tuh_xfer_t* xfer ); +static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len); +static void ch34x_process_config(tuh_xfer_t* xfer); +static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data ); -static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ); +static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif //------------- Common -------------// - enum { SERIAL_DRIVER_ACM = 0, @@ -166,6 +166,7 @@ typedef struct { void (*const process_set_config)(tuh_xfer_t* xfer); bool (*const set_control_line_state)(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); bool (*const set_baudrate)(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + bool (*const set_data_format)(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data); bool (*const set_line_coding)(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); } cdch_serial_driver_t; @@ -178,6 +179,7 @@ static const cdch_serial_driver_t serial_drivers[] = { .process_set_config = acm_process_config, .set_control_line_state = acm_set_control_line_state, .set_baudrate = acm_set_baudrate, + .set_data_format = acm_set_data_format, .set_line_coding = acm_set_line_coding }, @@ -189,6 +191,7 @@ static const cdch_serial_driver_t serial_drivers[] = { .process_set_config = ftdi_process_config, .set_control_line_state = ftdi_sio_set_modem_ctrl, .set_baudrate = ftdi_sio_set_baudrate, + .set_data_format = ftdi_set_data_format, .set_line_coding = ftdi_set_line_coding }, #endif @@ -201,6 +204,7 @@ static const cdch_serial_driver_t serial_drivers[] = { .process_set_config = cp210x_process_config, .set_control_line_state = cp210x_set_modem_ctrl, .set_baudrate = cp210x_set_baudrate, + .set_data_format = cp210x_set_data_format, .set_line_coding = cp210x_set_line_coding }, #endif @@ -213,6 +217,7 @@ static const cdch_serial_driver_t serial_drivers[] = { .process_set_config = ch34x_process_config, .set_control_line_state = ch34x_set_modem_ctrl, .set_baudrate = ch34x_set_baudrate, + .set_data_format = ch34x_set_data_format, .set_line_coding = ch34x_set_line_coding }, #endif @@ -562,6 +567,32 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete } } +bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + cdch_interface_t* p_cdc = get_itf(idx); + TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); + cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; + + if (complete_cb) { + return driver->set_data_format(p_cdc, stop_bits, parity, data_bits, complete_cb, user_data); + } else { + // blocking + xfer_result_t result = XFER_RESULT_INVALID; + bool ret = driver->set_data_format(p_cdc, stop_bits, parity, data_bits, complete_cb, (uintptr_t) &result); + + if (user_data) { + // user_data is not NULL, return result via user_data + *((xfer_result_t*) user_data) = result; + } + + TU_VERIFY(ret && result == XFER_RESULT_SUCCESS); + p_cdc->line_coding.stop_bits = stop_bits; + p_cdc->line_coding.parity = parity; + p_cdc->line_coding.data_bits = data_bits; + return true; + } +} + bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); @@ -900,6 +931,19 @@ static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const return true; } +static bool acm_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + TU_LOG_DRV("CDC ACM Set Data Format\r\n"); + + cdc_line_coding_t line_coding; + line_coding.bit_rate = p_cdc->line_coding.bit_rate; + line_coding.stop_bits = stop_bits; + line_coding.parity = parity; + line_coding.data_bits = data_bits; + + return acm_set_line_coding(p_cdc, &line_coding, complete_cb, user_data); +} + static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->acm_capability.support_line_request); cdc_line_coding_t line_coding = p_cdc->line_coding; @@ -968,6 +1012,18 @@ static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, u return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data); } +static bool ftdi_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + (void) p_cdc; + (void) stop_bits; + (void) parity; + (void) data_bits; + (void) complete_cb; + (void) user_data; + // TODO not implemented yet + return false; +} + static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { (void) p_cdc; (void) line_coding; @@ -1161,6 +1217,18 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_ complete_cb ? cdch_internal_control_complete : NULL, user_data); } +static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + (void) p_cdc; + (void) stop_bits; + (void) parity; + (void) data_bits; + (void) complete_cb; + (void) user_data; + // TODO not implemented yet + return false; +} + static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_DRV("CDC CP210x Set Control Line State\r\n"); p_cdc->user_control_cb = complete_cb; diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 9e5edd94e..d512a23a5 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -148,8 +148,11 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c // Request to set baudrate bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -// Request to Set Line Coding (ACM only) -// Should only use if you don't work with serial devices such as FTDI/CP210x +// Request to set data format +bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + +// Request to Set Line Coding = baudrate + data format +// Note: only implemented by ACM and CH34x, not supported by FTDI and CP210x yet bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); // Request to Get Line Coding (ACM only) @@ -159,15 +162,13 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, // Connect by set both DTR, RTS TU_ATTR_ALWAYS_INLINE static inline -bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return tuh_cdc_set_control_line_state(idx, CDC_CONTROL_LINE_STATE_DTR | CDC_CONTROL_LINE_STATE_RTS, complete_cb, user_data); } // Disconnect by clear both DTR, RTS TU_ATTR_ALWAYS_INLINE static inline -bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return tuh_cdc_set_control_line_state(idx, 0x00, complete_cb, user_data); } -- cgit v1.3.1 From 87d509d416ea7c250f4256f897f6cc9a7b7d2121 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 20 Jan 2024 01:42:31 +0700 Subject: make CFG_TUH_CDC_LINE_CODING_ON_ENUM optional for ch34x --- examples/host/cdc_msc_hid/src/cdc_app.c | 8 ++++++-- src/class/cdc/cdc_host.c | 19 ++++++++++++++----- src/class/cdc/serial/ch34x.h | 12 +----------- 3 files changed, 21 insertions(+), 18 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c index 81052047c..e275e7943 100644 --- a/examples/host/cdc_msc_hid/src/cdc_app.c +++ b/examples/host/cdc_msc_hid/src/cdc_app.c @@ -85,13 +85,17 @@ void tuh_cdc_mount_cb(uint8_t idx) { itf_info.desc.bInterfaceNumber); #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration - // otherwise you need to call tuh_cdc_set_line_coding() first + // If CFG_TUH_CDC_LINE_CODING_ON_ENUM is defined, line coding will be set by tinyusb stack + // while eneumerating new cdc device cdc_line_coding_t line_coding = {0}; if (tuh_cdc_get_local_line_coding(idx, &line_coding)) { printf(" Baudrate: %lu, Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits); printf(" Parity : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits); } +#else + // Set Line Coding upon mounted + cdc_line_coding_t new_line_coding = { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }; + tuh_cdc_set_line_coding(idx, &new_line_coding, NULL, 0); #endif } diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index f5182efc2..cd948243d 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1510,10 +1510,11 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t* p_cdc = get_itf(idx); uintptr_t const state = xfer->user_data; - cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; uint8_t buffer[2]; // TODO remove TU_ASSERT (p_cdc,); + // TODO check xfer->result + switch (state) { case CONFIG_CH34X_READ_VERSION: TU_LOG_DRV("[%u] CDCh CH34x attempt to read Chip Version\r\n", p_cdc->daddr); @@ -1527,20 +1528,28 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD TU_ASSERT (version >= 0x30,); + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; + uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits); + uint16_t const first_arg = tu_u16(lcr, 0x9c); uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate); TU_ASSERT(div_ps != 0, ); - - uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits); + #else + uint16_t const first_arg = 0; + uint16_t const div_ps = 0; + #endif // Init CH34x with line coding - TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps, + TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, first_arg, div_ps, ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),); break; } case CONFIG_CH34X_SPECIAL_REG_WRITE: // do special reg write, purpose unknown, overtaken from WCH driver - p_cdc->line_coding = line_coding; + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + p_cdc->line_coding = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM); + #endif TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),); break; diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h index 5def8d212..b9121afb3 100644 --- a/src/class/cdc/serial/ch34x.h +++ b/src/class/cdc/serial/ch34x.h @@ -27,21 +27,11 @@ #ifndef _CH34X_H_ #define _CH34X_H_ -// For simplicity, only the name CH34X is used here, -// but specifically only CH340 and CH341 are supported. - -// There is no official documentation for the CH34x chips. Reference can be found +// There is no official documentation for the CH34x (CH340, CH341) chips. Reference can be found // - https://github.com/WCHSoftGroup/ch341ser_linux // - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/ch341.c // - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uchcom.c -// set line_coding @ enumeration -#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM -#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM -#else // this default is necessary to work properly -#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X { 9600, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } -#endif - // USB requests #define CH34X_REQ_READ_VERSION 0x5F // dec 95 #define CH34X_REQ_WRITE_REG 0x9A // dec 154 -- cgit v1.3.1 From 769a237b19bbe5254e1c83869b463c79afb1af34 Mon Sep 17 00:00:00 2001 From: IngHK Date: Sat, 20 Jan 2024 20:34:50 +0100 Subject: accumulated review changes --- src/class/cdc/cdc_host.c | 68 ++++++++++++++++++++------------------------ src/class/cdc/serial/ch34x.h | 7 +++++ 2 files changed, 38 insertions(+), 37 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index cd948243d..7adaa0c8c 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -401,7 +401,9 @@ bool tuh_cdc_read_clear (uint8_t idx) { // Control Endpoint API //--------------------------------------------------------------------+ -static void process_internal_control_complete(cdch_interface_t* p_cdc, tuh_xfer_t* xfer) { +static void process_internal_control_complete(tuh_xfer_t* xfer, uint8_t itf_num) { + uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t* p_cdc = get_itf(idx); TU_ASSERT(p_cdc, ); uint16_t const value = tu_le16toh(xfer->setup->wValue); @@ -515,10 +517,7 @@ static void process_internal_control_complete(cdch_interface_t* p_cdc, tuh_xfer_ // internal control complete to update state such as line state, encoding static void cdch_internal_control_complete(tuh_xfer_t* xfer) { uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t* p_cdc = get_itf(idx); - - process_internal_control_complete(p_cdc, xfer); + process_internal_control_complete(xfer, itf_num); } bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { @@ -1294,7 +1293,8 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits); static uint16_t ch34x_get_divisor_prescaler(uint32_t baval); -//------------- control requestt -------------// +//------------- control request -------------// + static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { tusb_control_request_t const request_setup = { @@ -1366,10 +1366,7 @@ static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, // internal control complete to update state such as line state, encoding static void ch34x_control_complete(tuh_xfer_t* xfer) { // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber - uint8_t const itf_num = 0; - uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t* p_cdc = get_itf(idx); - process_internal_control_complete(p_cdc, xfer); + process_internal_control_complete(xfer, 0); } static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, @@ -1379,6 +1376,7 @@ static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, ui p_cdc->requested_line_coding.data_bits = data_bits; uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits); + TU_VERIFY(lcr != 0); TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr, complete_cb ? ch34x_control_complete : NULL, user_data)); return true; @@ -1527,35 +1525,26 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version); // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD TU_ASSERT (version >= 0x30,); - - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits); - uint16_t const first_arg = tu_u16(lcr, 0x9c); + // init CH34x with line coding + cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate); TU_ASSERT(div_ps != 0, ); - #else - uint16_t const first_arg = 0; - uint16_t const div_ps = 0; - #endif - - // Init CH34x with line coding - TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, first_arg, div_ps, + uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits); + TU_ASSERT(lcr != 0, ); + TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps, ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),); break; } case CONFIG_CH34X_SPECIAL_REG_WRITE: - // do special reg write, purpose unknown, overtaken from WCH driver - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->line_coding = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM); - #endif - TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),); + // overtake line coding and do special reg write, purpose unknown, overtaken from WCH driver + p_cdc->line_coding = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X); + TU_ASSERT (ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x0F, CH341_REG_0x2C), 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),); break; case CONFIG_CH34X_FLOW_CONTROL: // no hardware flow control - TU_ASSERT (ch34x_write_reg(p_cdc, 0x2727, 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),); + TU_ASSERT (ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x27, CH341_REG_0x27), 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),); break; case CONFIG_CH34X_MODEM_CONTROL: @@ -1581,6 +1570,7 @@ static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) { uint8_t b; uint32_t c; + TU_VERIFY(baval != 0, 0); switch (baval) { case 921600: a = 0xf3; @@ -1606,7 +1596,7 @@ static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) { b = 0; c = 11719; } - a = (unsigned char) (c / baval); + a = (uint8_t) (c / baval); if (a == 0 || a == 0xFF) { return 0; } @@ -1620,29 +1610,33 @@ static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) { // reg divisor = a, reg prescaler = b // According to linux code we need to set bit 7 of UCHCOM_REG_BPS_PRE, // otherwise the chip will buffer data. - return (uint16_t) (a << 8 | 0x80 | b); + return (uint16_t) ((uint16_t)a << 8 | 0x80 | b); } // calculate lcr value from data coding static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits) { uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX; - TU_VERIFY(data_bits >= 5, 0); + TU_VERIFY(data_bits >= 5 && data_bits <= 8, 0); lcr |= (uint8_t) (data_bits - 5); - if (parity) { - lcr |= CH34X_LCR_ENABLE_PAR; - } switch(parity) { + case CDC_LINE_CODING_PARITY_NONE: + break; + + case CDC_LINE_CODING_PARITY_ODD: + lcr |= CH34X_LCR_ENABLE_PAR; + break; + case CDC_LINE_CODING_PARITY_EVEN: - lcr |= CH34X_LCR_PAR_EVEN; + lcr |= CH34X_LCR_ENABLE_PAR | CH34X_LCR_PAR_EVEN; break; case CDC_LINE_CODING_PARITY_MARK: - lcr |= CH34X_LCR_MARK_SPACE; + lcr |= CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE; break; case CDC_LINE_CODING_PARITY_SPACE: - lcr |= CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN; + lcr |= CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN; break; default: break; diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h index b9121afb3..c18066f57 100644 --- a/src/class/cdc/serial/ch34x.h +++ b/src/class/cdc/serial/ch34x.h @@ -32,6 +32,13 @@ // - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/ch341.c // - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uchcom.c +// set line_coding @ enumeration +#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM +#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM +#else // this default is necessary to work properly +#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X { 9600, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } +#endif + // USB requests #define CH34X_REQ_READ_VERSION 0x5F // dec 95 #define CH34X_REQ_WRITE_REG 0x9A // dec 154 -- cgit v1.3.1 From af3c6be79fe9a9829f30831bd7525d2a22cb5529 Mon Sep 17 00:00:00 2001 From: Jonathan Zentgraf Date: Sat, 20 Jan 2024 20:16:54 -0500 Subject: msc_device: Fix check for including MSC lookup tables The _msc_scsi_cmd_lookup and _msc_scsi_cmd_table variables are needed when logging is enabled for the MSC device via CFG_TUD_MSC_LOG_LEVEL. Update the preprocessor check around them to use that definition when deciding whether to define those variables. Closes #2419 --- src/class/msc/msc_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 2589dcd2c..c145d86a6 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -203,7 +203,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) //--------------------------------------------------------------------+ // Debug //--------------------------------------------------------------------+ -#if CFG_TUSB_DEBUG >= 2 +#if CFG_TUSB_DEBUG >= CFG_TUD_MSC_LOG_LEVEL TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = { -- cgit v1.3.1 From 1c9a839401cb7323f93202f600c6f3148100e10a Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Tue, 23 Jan 2024 13:48:09 +0100 Subject: audio_device: Fix unused variable warning In some configurations local variable p_desc_parse_for_params is declared and never used resulting in warning that can be escalated to build error (for mynewt) Now variable is surrounded with same preprocessor condition as function that uses it audiod_parse_for_AS_params() --- src/class/audio/audio_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index d438d0715..4adc558a6 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -1729,7 +1729,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * // Find correct interface if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bInterfaceNumber == itf && ((tusb_desc_interface_t const * )p_desc)->bAlternateSetting == alt) { -#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL +#if (CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_ENCODING)) || (CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING) uint8_t const * p_desc_parse_for_params = p_desc; #endif // From this point forward follow the EP descriptors associated to the current alternate setting interface - Open EPs if necessary -- cgit v1.3.1 From 0b8b8af83dfac97caa7c41f9d5c8c1a3af1b9ac1 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 25 Jan 2024 17:25:48 +0700 Subject: minor update to video capture example --- examples/device/video_capture/src/main.c | 15 +- examples/device/video_capture/src/tusb_config.h | 2 +- .../device/video_capture/src/usb_descriptors.h | 69 +++------ src/class/video/video_device.c | 6 +- src/common/tusb_types.h | 154 ++++++++------------- 5 files changed, 92 insertions(+), 154 deletions(-) (limited to 'src') diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index 7b180dd6b..e63335e67 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -131,8 +131,7 @@ static struct { static uint8_t frame_buffer[FRAME_WIDTH * FRAME_HEIGHT * 16 / 8]; static void fill_color_bar(uint8_t* buffer, unsigned start_position) { - /* EBU color bars - * See also https://stackoverflow.com/questions/6939422 */ + /* EBU color bars: https://stackoverflow.com/questions/6939422 */ static uint8_t const bar_color[8][4] = { /* Y, U, Y, V */ { 235, 128, 235, 128}, /* 100% White */ @@ -184,12 +183,12 @@ void video_task(void) { already_sent = 1; start_ms = board_millis(); #ifdef CFG_EXAMPLE_VIDEO_READONLY -# if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG) + #if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG) tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4], FRAME_WIDTH * FRAME_HEIGHT * 16/8); -# else + #else tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)frames[frame_num % 8].buffer, frames[frame_num % 8].size); -# endif + #endif #else fill_color_bar(frame_buffer, frame_num); tud_video_n_frame_xfer(0, 0, (void*) frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8); @@ -202,12 +201,12 @@ void video_task(void) { start_ms += interval_ms; #ifdef CFG_EXAMPLE_VIDEO_READONLY -# if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG) + #if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG) tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4], FRAME_WIDTH * FRAME_HEIGHT * 16/8); -# else + #else tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)frames[frame_num % 8].buffer, frames[frame_num % 8].size); -# endif + #endif #else fill_color_bar(frame_buffer, frame_num); tud_video_n_frame_xfer(0, 0, (void*) frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8); diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h index 8440b47ef..d563c6f5c 100644 --- a/examples/device/video_capture/src/tusb_config.h +++ b/examples/device/video_capture/src/tusb_config.h @@ -97,7 +97,7 @@ // The number of video streaming interfaces #define CFG_TUD_VIDEO_STREAMING 1 -// video streaming endpoint size +// video streaming endpoint buffer size #define CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE 256 // use bulk endpoint for streaming interface diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h index b924c8dbe..fa3c1fbd2 100644 --- a/examples/device/video_capture/src/usb_descriptors.h +++ b/examples/device/video_capture/src/usb_descriptors.h @@ -126,23 +126,17 @@ enum { #define TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR(_stridx, _epin, _width, _height, _fps, _epsize) \ TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \ /* Video control 0 */ \ - TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \ - TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \ - /* wTotalLength - bLength */ \ - TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \ - UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \ - TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\ - /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\ - /*wObjectiveFocalLength*/0, /*bmControls*/0), \ + TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \ + /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \ + TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \ + /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \ + TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \ TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \ /* Video stream alt. 0 */ \ TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 0, _stridx), \ /* Video stream header for without still image capture */ \ TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \ - /*wTotalLength - bLength */\ - TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\ - + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\ - + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\ + /*wTotalLength - bLength */ TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\ _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \ /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \ /*bmaControls(1)*/0), \ @@ -163,23 +157,17 @@ enum { #define TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG(_stridx, _epin, _width, _height, _fps, _epsize) \ TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \ /* Video control 0 */ \ - TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \ - TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \ - /* wTotalLength - bLength */ \ - TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \ - UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \ - TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\ - /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\ - /*wObjectiveFocalLength*/0, /*bmControls*/0), \ + TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \ + /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \ + TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \ + /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \ + TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \ TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \ /* Video stream alt. 0 */ \ TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 0, _stridx), \ /* Video stream header for without still image capture */ \ TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \ - /*wTotalLength - bLength */\ - TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\ - + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\ - + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\ + /*wTotalLength - bLength */ TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\ _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \ /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \ /*bmaControls(1)*/0), \ @@ -202,22 +190,17 @@ enum { TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \ /* Video control 0 */ \ TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \ - TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \ - /* wTotalLength - bLength */ \ - TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \ - UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \ - TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\ - /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\ - /*wObjectiveFocalLength*/0, /*bmControls*/0), \ + /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \ + TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \ + /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \ + TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \ TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \ /* Video stream alt. 0 */ \ TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \ /* Video stream header for without still image capture */ \ TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \ /*wTotalLength - bLength */\ - TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\ - + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\ - + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\ + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\ _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \ /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \ /*bmaControls(1)*/0), \ @@ -235,23 +218,17 @@ enum { #define TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG_BULK(_stridx, _epin, _width, _height, _fps, _epsize) \ TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \ /* Video control 0 */ \ - TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \ - TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \ - /* wTotalLength - bLength */ \ - TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \ - UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \ - TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\ - /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\ - /*wObjectiveFocalLength*/0, /*bmControls*/0), \ + TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \ + /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \ + TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \ + /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \ + TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \ TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \ /* Video stream alt. 0 */ \ TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \ /* Video stream header for without still image capture */ \ TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \ - /*wTotalLength - bLength */\ - TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\ - + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\ - + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\ + /*wTotalLength - bLength */ TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\ _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \ /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \ /*bmaControls(1)*/0), \ diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 3b29454a3..c16a45fcd 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -434,8 +434,9 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm uint_fast32_t interval_ms = interval / 10000; TU_ASSERT(interval_ms); uint_fast32_t payload_size = (frame_size + interval_ms - 1) / interval_ms + 2; - if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size) + if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size) { payload_size = CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE; + } param->dwMaxPayloadTransferSize = payload_size; return true; } @@ -577,8 +578,9 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const * } else { payload_size = (frame_size + interval_ms - 1) / interval_ms + 2; } - if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size) + if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size) { payload_size = CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE; + } param->dwMaxPayloadTransferSize = payload_size; } return true; diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index fab680989..d4ef1fd09 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -44,43 +44,38 @@ *------------------------------------------------------------------*/ /// defined base on EHCI specs value for Endpoint Speed -typedef enum -{ +typedef enum { TUSB_SPEED_FULL = 0, TUSB_SPEED_LOW = 1, TUSB_SPEED_HIGH = 2, TUSB_SPEED_INVALID = 0xff, -}tusb_speed_t; +} tusb_speed_t; /// defined base on USB Specs Endpoint's bmAttributes -typedef enum -{ +typedef enum { TUSB_XFER_CONTROL = 0 , TUSB_XFER_ISOCHRONOUS , TUSB_XFER_BULK , TUSB_XFER_INTERRUPT -}tusb_xfer_type_t; +} tusb_xfer_type_t; -typedef enum -{ +typedef enum { TUSB_DIR_OUT = 0, TUSB_DIR_IN = 1, TUSB_DIR_IN_MASK = 0x80 -}tusb_dir_t; +} tusb_dir_t; -enum -{ +enum { TUSB_EPSIZE_BULK_FS = 64, - TUSB_EPSIZE_BULK_HS= 512, + TUSB_EPSIZE_BULK_HS = 512, TUSB_EPSIZE_ISO_FS_MAX = 1023, TUSB_EPSIZE_ISO_HS_MAX = 1024, }; -/// Isochronous End Point Attributes -typedef enum -{ +/// Isochronous Endpoint Attributes +typedef enum { TUSB_ISO_EP_ATT_NO_SYNC = 0x00, TUSB_ISO_EP_ATT_ASYNCHRONOUS = 0x04, TUSB_ISO_EP_ATT_ADAPTIVE = 0x08, @@ -88,11 +83,10 @@ typedef enum TUSB_ISO_EP_ATT_DATA = 0x00, ///< Data End Point TUSB_ISO_EP_ATT_EXPLICIT_FB = 0x10, ///< Feedback End Point TUSB_ISO_EP_ATT_IMPLICIT_FB = 0x20, ///< Data endpoint that also serves as an implicit feedback -}tusb_iso_ep_attribute_t; +} tusb_iso_ep_attribute_t; /// USB Descriptor Types -typedef enum -{ +typedef enum { TUSB_DESC_DEVICE = 0x01, TUSB_DESC_CONFIGURATION = 0x02, TUSB_DESC_STRING = 0x03, @@ -119,10 +113,9 @@ typedef enum TUSB_DESC_SUPERSPEED_ENDPOINT_COMPANION = 0x30, TUSB_DESC_SUPERSPEED_ISO_ENDPOINT_COMPANION = 0x31 -}tusb_desc_type_t; +} tusb_desc_type_t; -typedef enum -{ +typedef enum { TUSB_REQ_GET_STATUS = 0 , TUSB_REQ_CLEAR_FEATURE = 1 , TUSB_REQ_RESERVED = 2 , @@ -136,25 +129,22 @@ typedef enum TUSB_REQ_GET_INTERFACE = 10 , TUSB_REQ_SET_INTERFACE = 11 , TUSB_REQ_SYNCH_FRAME = 12 -}tusb_request_code_t; +} tusb_request_code_t; -typedef enum -{ +typedef enum { TUSB_REQ_FEATURE_EDPT_HALT = 0, TUSB_REQ_FEATURE_REMOTE_WAKEUP = 1, TUSB_REQ_FEATURE_TEST_MODE = 2 -}tusb_request_feature_selector_t; +} tusb_request_feature_selector_t; -typedef enum -{ +typedef enum { TUSB_REQ_TYPE_STANDARD = 0, TUSB_REQ_TYPE_CLASS, TUSB_REQ_TYPE_VENDOR, TUSB_REQ_TYPE_INVALID } tusb_request_type_t; -typedef enum -{ +typedef enum { TUSB_REQ_RCPT_DEVICE =0, TUSB_REQ_RCPT_INTERFACE, TUSB_REQ_RCPT_ENDPOINT, @@ -162,8 +152,7 @@ typedef enum } tusb_request_recipient_t; // https://www.usb.org/defined-class-codes -typedef enum -{ +typedef enum { TUSB_CLASS_UNSPECIFIED = 0 , TUSB_CLASS_AUDIO = 1 , TUSB_CLASS_CDC = 2 , @@ -187,26 +176,23 @@ typedef enum TUSB_CLASS_MISC = 0xEF , TUSB_CLASS_APPLICATION_SPECIFIC = 0xFE , TUSB_CLASS_VENDOR_SPECIFIC = 0xFF -}tusb_class_code_t; +} tusb_class_code_t; typedef enum { MISC_SUBCLASS_COMMON = 2 }misc_subclass_type_t; -typedef enum -{ +typedef enum { MISC_PROTOCOL_IAD = 1 -}misc_protocol_type_t; +} misc_protocol_type_t; -typedef enum -{ +typedef enum { APP_SUBCLASS_USBTMC = 0x03, APP_SUBCLASS_DFU_RUNTIME = 0x01 } app_subclass_type_t; -typedef enum -{ +typedef enum { DEVICE_CAPABILITY_WIRELESS_USB = 0x01, DEVICE_CAPABILITY_USB20_EXTENSION = 0x02, DEVICE_CAPABILITY_SUPERSPEED_USB = 0x03, @@ -223,7 +209,7 @@ typedef enum DEVICE_CAPABILITY_AUTHENTICATION = 0x0E, DEVICE_CAPABILITY_BILLBOARD_EX = 0x0F, DEVICE_CAPABILITY_CONFIGURATION_SUMMARY = 0x10 -}device_capability_type_t; +} device_capability_type_t; enum { TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP = TU_BIT(5), @@ -235,28 +221,25 @@ enum { //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ -typedef enum -{ +typedef enum { XFER_RESULT_SUCCESS = 0, XFER_RESULT_FAILED, XFER_RESULT_STALLED, XFER_RESULT_TIMEOUT, XFER_RESULT_INVALID -}xfer_result_t; +} xfer_result_t; -enum // TODO remove -{ +// TODO remove +enum { DESC_OFFSET_LEN = 0, DESC_OFFSET_TYPE = 1 }; -enum -{ +enum { INTERFACE_INVALID_NUMBER = 0xff }; -typedef enum -{ +typedef enum { MS_OS_20_SET_HEADER_DESCRIPTOR = 0x00, MS_OS_20_SUBSET_HEADER_CONFIGURATION = 0x01, MS_OS_20_SUBSET_HEADER_FUNCTION = 0x02, @@ -268,16 +251,14 @@ typedef enum MS_OS_20_FEATURE_VENDOR_REVISION = 0x08 } microsoft_os_20_type_t; -enum -{ +enum { CONTROL_STAGE_IDLE, CONTROL_STAGE_SETUP, CONTROL_STAGE_DATA, CONTROL_STAGE_ACK }; -enum -{ +enum { TUSB_INDEX_INVALID_8 = 0xFFu }; @@ -290,8 +271,7 @@ TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN /// USB Device Descriptor -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of this descriptor in bytes. uint8_t bDescriptorType ; ///< DEVICE Descriptor Type. uint16_t bcdUSB ; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). This field identifies the release of the USB Specification with which the device and its descriptors are compliant. @@ -314,8 +294,7 @@ typedef struct TU_ATTR_PACKED TU_VERIFY_STATIC( sizeof(tusb_desc_device_t) == 18, "size is not correct"); // USB Binary Device Object Store (BOS) Descriptor -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of this descriptor in bytes uint8_t bDescriptorType ; ///< CONFIGURATION Descriptor Type uint16_t wTotalLength ; ///< Total length of data returned for this descriptor @@ -325,8 +304,7 @@ typedef struct TU_ATTR_PACKED TU_VERIFY_STATIC( sizeof(tusb_desc_bos_t) == 5, "size is not correct"); /// USB Configuration Descriptor -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of this descriptor in bytes uint8_t bDescriptorType ; ///< CONFIGURATION Descriptor Type uint16_t wTotalLength ; ///< Total length of data returned for this configuration. Includes the combined length of all descriptors (configuration, interface, endpoint, and class- or vendor-specific) returned for this configuration. @@ -341,8 +319,7 @@ typedef struct TU_ATTR_PACKED TU_VERIFY_STATIC( sizeof(tusb_desc_configuration_t) == 9, "size is not correct"); /// USB Interface Descriptor -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of this descriptor in bytes uint8_t bDescriptorType ; ///< INTERFACE Descriptor Type @@ -358,8 +335,7 @@ typedef struct TU_ATTR_PACKED TU_VERIFY_STATIC( sizeof(tusb_desc_interface_t) == 9, "size is not correct"); /// USB Endpoint Descriptor -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength ; // Size of this descriptor in bytes uint8_t bDescriptorType ; // ENDPOINT Descriptor Type @@ -379,8 +355,7 @@ typedef struct TU_ATTR_PACKED TU_VERIFY_STATIC( sizeof(tusb_desc_endpoint_t) == 7, "size is not correct"); /// USB Other Speed Configuration Descriptor -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of descriptor uint8_t bDescriptorType ; ///< Other_speed_Configuration Type uint16_t wTotalLength ; ///< Total length of data returned @@ -393,8 +368,7 @@ typedef struct TU_ATTR_PACKED } tusb_desc_other_speed_t; /// USB Device Qualifier Descriptor -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of descriptor uint8_t bDescriptorType ; ///< Device Qualifier Type uint16_t bcdUSB ; ///< USB specification version number (e.g., 0200H for V2.00) @@ -411,8 +385,7 @@ typedef struct TU_ATTR_PACKED TU_VERIFY_STATIC( sizeof(tusb_desc_device_qualifier_t) == 10, "size is not correct"); /// USB Interface Association Descriptor (IAD ECN) -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of descriptor uint8_t bDescriptorType ; ///< Other_speed_Configuration Type @@ -427,16 +400,14 @@ typedef struct TU_ATTR_PACKED } tusb_desc_interface_assoc_t; // USB String Descriptor -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of this descriptor in bytes uint8_t bDescriptorType ; ///< Descriptor Type uint16_t unicode_string[]; } tusb_desc_string_t; // USB Binary Device Object Store (BOS) -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength; uint8_t bDescriptorType ; uint8_t bDevCapabilityType; @@ -445,9 +416,8 @@ typedef struct TU_ATTR_PACKED uint8_t CapabilityData[]; } tusb_desc_bos_platform_t; -// USB WebuSB URL Descriptor -typedef struct TU_ATTR_PACKED -{ +// USB WebUSB URL Descriptor +typedef struct TU_ATTR_PACKED { uint8_t bLength; uint8_t bDescriptorType; uint8_t bScheme; @@ -455,8 +425,7 @@ typedef struct TU_ATTR_PACKED } tusb_desc_webusb_url_t; // DFU Functional Descriptor -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength; uint8_t bDescriptorType; @@ -481,7 +450,7 @@ typedef struct TU_ATTR_PACKED // //--------------------------------------------------------------------+ -typedef struct TU_ATTR_PACKED{ +typedef struct TU_ATTR_PACKED { union { struct TU_ATTR_PACKED { uint8_t recipient : 5; ///< Recipient type tusb_request_recipient_t. @@ -509,36 +478,30 @@ TU_ATTR_BIT_FIELD_ORDER_END //--------------------------------------------------------------------+ // Get direction from Endpoint address -TU_ATTR_ALWAYS_INLINE static inline tusb_dir_t tu_edpt_dir(uint8_t addr) -{ +TU_ATTR_ALWAYS_INLINE static inline tusb_dir_t tu_edpt_dir(uint8_t addr) { return (addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; } // Get Endpoint number from address -TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_number(uint8_t addr) -{ +TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_number(uint8_t addr) { return (uint8_t)(addr & (~TUSB_DIR_IN_MASK)); } -TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir) -{ +TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir) { return (uint8_t)(num | (dir ? TUSB_DIR_IN_MASK : 0)); } -TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep) -{ +TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep) { return tu_le16toh(desc_ep->wMaxPacketSize) & TU_GENMASK(10, 0); } #if CFG_TUSB_DEBUG -TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir) -{ +TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir) { tu_static const char *str[] = {"out", "in"}; return str[dir]; } -TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t) -{ +TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t) { tu_static const char *str[] = {"control", "isochronous", "bulk", "interrupt"}; return str[t]; } @@ -549,21 +512,18 @@ TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_ //--------------------------------------------------------------------+ // return next descriptor -TU_ATTR_ALWAYS_INLINE static inline uint8_t const * tu_desc_next(void const* desc) -{ +TU_ATTR_ALWAYS_INLINE static inline uint8_t const * tu_desc_next(void const* desc) { uint8_t const* desc8 = (uint8_t const*) desc; return desc8 + desc8[DESC_OFFSET_LEN]; } // get descriptor type -TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_type(void const* desc) -{ +TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_type(void const* desc) { return ((uint8_t const*) desc)[DESC_OFFSET_TYPE]; } // get descriptor length -TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_len(void const* desc) -{ +TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_len(void const* desc) { return ((uint8_t const*) desc)[DESC_OFFSET_LEN]; } -- cgit v1.3.1 From a7de4ac9b7a2dfb1fa44921fb0f41f249c8cdd5e Mon Sep 17 00:00:00 2001 From: YixingShen Date: Fri, 26 Jan 2024 02:37:15 +0800 Subject: Correct VIDEO_CS_VS_INTERFACE_FRAME_MJPEG to VIDEO_CS_ITF_VS_FRAME_MJPEG for #define TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_DISC --- src/class/video/video.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/video/video.h b/src/class/video/video.h index d9880c291..268e219e2 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -537,7 +537,7 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c /* Motion-JPEG 3.1.1 Table 3-2 and 3-4 */ #define TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, ...) \ TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_DISC_LEN + (TU_ARGS_NUM(__VA_ARGS__)) * 4, \ - TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_MJPEG, \ + TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_MJPEG, \ _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \ U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__ -- cgit v1.3.1 From b5cd673330fc87f2981ecf139b24940df5cb3cfe Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 26 Jan 2024 22:55:55 +0700 Subject: rename and add more video descriptors use struct to define uvc descriptor for video_capture since uvc is rather too complicated to use macro templates --- .../device/video_capture/src/usb_descriptors.c | 233 +++++++++++++++++++-- .../device/video_capture/src/usb_descriptors.h | 4 +- src/class/video/video.h | 224 ++++++++++++++------ src/class/video/video_device.c | 20 +- src/common/tusb_types.h | 3 +- 5 files changed, 389 insertions(+), 95 deletions(-) (limited to 'src') diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c index d38f158c8..8e54d3afd 100644 --- a/examples/device/video_capture/src/usb_descriptors.c +++ b/examples/device/video_capture/src/usb_descriptors.c @@ -40,6 +40,26 @@ #define USB_VID 0xCafe #define USB_BCD 0x0200 +// String Descriptor Index +enum { + STRID_LANGID = 0, + STRID_MANUFACTURER, + STRID_PRODUCT, + STRID_SERIAL, + STRID_UVC_CONTROL, + STRID_UVC_STREAMING, +}; + +// array of pointer to string descriptors +char const* string_desc_arr[] = { + (const char[]) {0x09, 0x04}, // 0: is supported language is English (0x0409) + "TinyUSB", // 1: Manufacturer + "TinyUSB Device", // 2: Product + NULL, // 3: Serials will use unique ID if possible + "TinyUSB UVC Control", // 4: UVC Interface + "TinyUSB UVC Streaming", // 5: UVC Interface +}; + //--------------------------------------------------------------------+ // Device Descriptors //--------------------------------------------------------------------+ @@ -60,9 +80,9 @@ tusb_desc_device_t const desc_device = { .idProduct = USB_PID, .bcdDevice = 0x0100, - .iManufacturer = 0x01, - .iProduct = 0x02, - .iSerialNumber = 0x03, + .iManufacturer = STRID_MANUFACTURER, + .iProduct = STRID_PRODUCT, + .iSerialNumber = STRID_SERIAL, .bNumConfigurations = 0x01 }; @@ -164,6 +184,193 @@ uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) { } #endif // highspeed +typedef struct TU_ATTR_PACKED { + tusb_desc_interface_t itf; + tusb_desc_video_control_header_1itf_t header; + tusb_desc_video_control_camera_terminal_t camera_terminal; + tusb_desc_video_control_output_terminal_t output_terminal; +} uvc_control_desc_t; + +/* Windows support YUY2 and NV12 + * https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/usb-video-class-driver-overview */ + +typedef struct TU_ATTR_PACKED { + tusb_desc_interface_t itf; + tusb_desc_video_streaming_input_header_1byte_t header; + tusb_desc_video_format_uncompressed_t format; + tusb_desc_video_frame_uncompressed_continuous_t frame; + tusb_desc_video_streaming_color_matching_t color; + tusb_desc_endpoint_t ep; +} uvc_streaming_desc_t; + +typedef struct TU_ATTR_PACKED { + tusb_desc_configuration_t config; + tusb_desc_interface_assoc_t iad; + uvc_control_desc_t video_control; + uvc_streaming_desc_t video_streaming; +} uvc_cfg_desc_t; + +const uvc_cfg_desc_t config_desc = { + .config = { + .bLength = sizeof(tusb_desc_configuration_t), + .bDescriptorType = TUSB_DESC_CONFIGURATION, + + .wTotalLength = sizeof(uvc_cfg_desc_t), + .bNumInterfaces = ITF_NUM_TOTAL, + .bConfigurationValue = 1, + .iConfiguration = 0, + .bmAttributes = TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, + .bMaxPower = 100 / 2 + }, + .iad = { + .bLength = sizeof(tusb_desc_interface_assoc_t), + .bDescriptorType = TUSB_DESC_INTERFACE_ASSOCIATION, + + .bFirstInterface = ITF_NUM_VIDEO_CONTROL, + .bInterfaceCount = 2, + .bFunctionClass = TUSB_CLASS_VIDEO, + .bFunctionSubClass = VIDEO_SUBCLASS_INTERFACE_COLLECTION, + .bFunctionProtocol = VIDEO_ITF_PROTOCOL_UNDEFINED, + .iFunction = 0 + }, + + .video_control = { + .itf = { + .bLength = sizeof(tusb_desc_interface_t), + .bDescriptorType = TUSB_DESC_INTERFACE, + + .bInterfaceNumber = ITF_NUM_VIDEO_CONTROL, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = TUSB_CLASS_VIDEO, + .bInterfaceSubClass = VIDEO_SUBCLASS_CONTROL, + .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15, + .iInterface = STRID_UVC_CONTROL + }, + .header = { + .bLength = sizeof(tusb_desc_video_control_header_1itf_t), + .bDescriptorType = TUSB_DESC_CS_INTERFACE, + .bDescriptorSubType = VIDEO_CS_ITF_VC_HEADER, + + .bcdUVC = VIDEO_BCD_1_50, + .wTotalLength = sizeof(uvc_control_desc_t) - sizeof(tusb_desc_interface_t), // CS VC descriptors only + .dwClockFrequency = UVC_CLOCK_FREQUENCY, + .bInCollection = 1, + .baInterfaceNr = { ITF_NUM_VIDEO_STREAMING } + }, + .camera_terminal = { + .bLength = sizeof(tusb_desc_video_control_camera_terminal_t), + .bDescriptorType = TUSB_DESC_CS_INTERFACE, + .bDescriptorSubType = VIDEO_CS_ITF_VC_INPUT_TERMINAL, + + .bTerminalID = UVC_ENTITY_CAP_INPUT_TERMINAL, + .wTerminalType = VIDEO_ITT_CAMERA, + .bAssocTerminal = 0, + .iTerminal = 0, + .wObjectiveFocalLengthMin = 0, + .wObjectiveFocalLengthMax = 0, + .wOcularFocalLength = 0, + .bControlSize = 3, + .bmControls = { 0, 0, 0 } + }, + .output_terminal = { + .bLength = sizeof(tusb_desc_video_control_output_terminal_t), + .bDescriptorType = TUSB_DESC_CS_INTERFACE, + .bDescriptorSubType = VIDEO_CS_ITF_VC_OUTPUT_TERMINAL, + + .bTerminalID = UVC_ENTITY_CAP_OUTPUT_TERMINAL, + .wTerminalType = VIDEO_TT_STREAMING, + .bAssocTerminal = 0, + .bSourceID = UVC_ENTITY_CAP_INPUT_TERMINAL, + .iTerminal = 0 + } + }, + + .video_streaming = { + .itf = { + .bLength = sizeof(tusb_desc_interface_t), + .bDescriptorType = TUSB_DESC_INTERFACE, + + .bInterfaceNumber = ITF_NUM_VIDEO_STREAMING, + .bAlternateSetting = 0, + .bNumEndpoints = 1, + .bInterfaceClass = TUSB_CLASS_VIDEO, + .bInterfaceSubClass = VIDEO_SUBCLASS_STREAMING, + .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15, + .iInterface = STRID_UVC_STREAMING + }, + .header = { + .bLength = sizeof(tusb_desc_video_streaming_input_header_1byte_t), + .bDescriptorType = TUSB_DESC_CS_INTERFACE, + .bDescriptorSubType = VIDEO_CS_ITF_VS_INPUT_HEADER, + + .bNumFormats = 1, + .wTotalLength = sizeof(uvc_streaming_desc_t) - sizeof(tusb_desc_interface_t) - sizeof(tusb_desc_endpoint_t), // CS VS descriptors only + .bEndpointAddress = EPNUM_VIDEO_IN, + .bmInfo = 0, + .bTerminalLink = UVC_ENTITY_CAP_OUTPUT_TERMINAL, + .bStillCaptureMethod = 0, + .bTriggerSupport = 0, + .bTriggerUsage = 0, + .bControlSize = 1, + .bmaControls = { 0 } + }, + .format = { + .bLength = sizeof(tusb_desc_video_format_uncompressed_t), + .bDescriptorType = TUSB_DESC_CS_INTERFACE, + .bDescriptorSubType = VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED, + + .bFormatIndex = 1, // 1-based index + .bNumFrameDescriptors = 1, + .guidFormat = { TUD_VIDEO_GUID_YUY2 }, + .bBitsPerPixel = 16, + .bDefaultFrameIndex = 1, + .bAspectRatioX = 0, + .bAspectRatioY = 0, + .bmInterlaceFlags = 0, + .bCopyProtect = 0 + }, + .frame = { + .bLength = sizeof(tusb_desc_video_frame_uncompressed_continuous_t), + .bDescriptorType = TUSB_DESC_CS_INTERFACE, + .bDescriptorSubType = VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED, + + .bFrameIndex = 1, // 1-based index + .bmCapabilities = 0, + .wWidth = FRAME_WIDTH, + .wHeight = FRAME_HEIGHT, + .dwMinBitRate = FRAME_WIDTH * FRAME_HEIGHT * 16 * 1, + .dwMaxBitRate = FRAME_WIDTH * FRAME_HEIGHT * 16 * FRAME_RATE, + .dwMaxVideoFrameBufferSize = FRAME_WIDTH * FRAME_HEIGHT * 16 / 8, + .dwDefaultFrameInterval = 10000000 / FRAME_RATE, + .bFrameIntervalType = 0, // continuous + .dwFrameInterval = { + 10000000 / FRAME_RATE, // min + 10000000, // max + 10000000 / FRAME_RATE // step + } + }, + .color = { + .bLength = sizeof(tusb_desc_video_streaming_color_matching_t), + .bDescriptorType = TUSB_DESC_CS_INTERFACE, + .bDescriptorSubType = VIDEO_CS_ITF_VS_COLORFORMAT, + + .bColorPrimaries = VIDEO_COLOR_PRIMARIES_BT709, + .bTransferCharacteristics = VIDEO_COLOR_XFER_CH_BT709, + .bMatrixCoefficients = VIDEO_COLOR_COEF_SMPTE170M + }, + .ep = { + .bLength = sizeof(tusb_desc_endpoint_t), + .bDescriptorType = TUSB_DESC_ENDPOINT, + + .bEndpointAddress = EPNUM_VIDEO_IN, + .bmAttributes = { .xfer = TUSB_XFER_BULK }, + .wMaxPacketSize = CFG_TUD_VIDEO_STREAMING_BULK ? 64 : CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE, + .bInterval = 1 + } + } +}; + // Invoked when received GET CONFIGURATION DESCRIPTOR // Application return pointer to descriptor // Descriptor contents must exist long enough for transfer to complete @@ -174,7 +381,8 @@ uint8_t const* tud_descriptor_configuration_cb(uint8_t index) { // Although we are highspeed, host may be fullspeed. return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration; #else - return desc_fs_configuration; +// return desc_fs_configuration; + return (uint8_t const*) &config_desc; #endif } @@ -182,23 +390,6 @@ uint8_t const* tud_descriptor_configuration_cb(uint8_t index) { // String Descriptors //--------------------------------------------------------------------+ -// String Descriptor Index -enum { - STRID_LANGID = 0, - STRID_MANUFACTURER, - STRID_PRODUCT, - STRID_SERIAL, -}; - -// array of pointer to string descriptors -char const* string_desc_arr[] = { - (const char[]) {0x09, 0x04}, // 0: is supported language is English (0x0409) - "TinyUSB", // 1: Manufacturer - "TinyUSB Device", // 2: Product - NULL, // 3: Serials will use unique ID if possible - "TinyUSB UVC", // 4: UVC Interface -}; - static uint16_t _desc_str[32 + 1]; // Invoked when received GET STRING DESCRIPTOR request diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h index fa3c1fbd2..fd908c9c2 100644 --- a/examples/device/video_capture/src/usb_descriptors.h +++ b/examples/device/video_capture/src/usb_descriptors.h @@ -210,7 +210,7 @@ enum { /* Video stream frame format */ \ TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \ _width * _height * 16, _width * _height * 16 * _fps, \ - _width * _height * 16, \ + _width * _height * 16 / 8, \ (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \ TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \ TUD_VIDEO_DESC_EP_BULK(_epin, _epsize, 1) @@ -223,7 +223,7 @@ enum { TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \ /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \ TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \ - TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \ + TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, UVC_ENTITY_CAP_INPUT_TERMINAL, 0), \ /* Video stream alt. 0 */ \ TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \ /* Video stream header for without still image capture */ \ diff --git a/src/class/video/video.h b/src/class/video/video.h index d9880c291..162d4e4c4 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -29,6 +29,10 @@ #include "common/tusb_common.h" +enum { + VIDEO_BCD_1_50 = 0x0150, +}; + // Table 3-19 Color Matching Descriptor typedef enum { VIDEO_COLOR_PRIMARIES_UNDEFINED = 0x00, @@ -198,55 +202,98 @@ typedef enum { } video_terminal_type_t; //--------------------------------------------------------------------+ -// Descriptors +// Video Control (VC) Descriptors //--------------------------------------------------------------------+ /* 2.3.4.2 */ +#define tusb_desc_video_control_header_nitf_t(_nitf) \ + struct TU_ATTR_PACKED { \ + uint8_t bLength; \ + uint8_t bDescriptorType; \ + uint8_t bDescriptorSubType; \ + uint16_t bcdUVC; \ + uint16_t wTotalLength; \ + uint32_t dwClockFrequency; /* deprecated */ \ + uint8_t bInCollection; \ + uint8_t baInterfaceNr[_nitf]; \ + } + +typedef tusb_desc_video_control_header_nitf_t() tusb_desc_video_control_header_t; +typedef tusb_desc_video_control_header_nitf_t(1) tusb_desc_video_control_header_1itf_t; +typedef tusb_desc_video_control_header_nitf_t(2) tusb_desc_video_control_header_2itf_t; +typedef tusb_desc_video_control_header_nitf_t(3) tusb_desc_video_control_header_3itf_t; +typedef tusb_desc_video_control_header_nitf_t(4) tusb_desc_video_control_header_4itf_t; + typedef struct TU_ATTR_PACKED { uint8_t bLength; uint8_t bDescriptorType; uint8_t bDescriptorSubType; - uint16_t bcdUVC; - uint16_t wTotalLength; - uint32_t dwClockFrequency; - uint8_t bInCollection; - uint8_t baInterfaceNr[]; -} tusb_desc_cs_video_ctl_itf_hdr_t; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t iTerminal; +} tusb_desc_video_control_input_terminal_t; + +TU_VERIFY_STATIC(sizeof(tusb_desc_video_control_input_terminal_t) == 8, "size is not correct"); -/* 2.4.3.3 */ typedef struct TU_ATTR_PACKED { - uint8_t bHeaderLength; - union { - uint8_t bmHeaderInfo; - struct { - uint8_t FrameID: 1; - uint8_t EndOfFrame: 1; - uint8_t PresentationTime: 1; - uint8_t SourceClockReference: 1; - uint8_t PayloadSpecific: 1; - uint8_t StillImage: 1; - uint8_t Error: 1; - uint8_t EndOfHeader: 1; - }; - }; -} tusb_video_payload_header_t; + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t bSourceID; + uint8_t iTerminal; +} tusb_desc_video_control_output_terminal_t; + +TU_VERIFY_STATIC(sizeof(tusb_desc_video_control_output_terminal_t) == 9, "size is not correct"); -/* 3.9.2.1 */ typedef struct TU_ATTR_PACKED { uint8_t bLength; uint8_t bDescriptorType; uint8_t bDescriptorSubType; - uint8_t bNumFormats; - uint16_t wTotalLength; - uint8_t bEndpointAddress; - uint8_t bmInfo; - uint8_t bTerminalLink; - uint8_t bStillCaptureMethod; - uint8_t bTriggerSupport; - uint8_t bTriggerUsage; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t iTerminal; + + uint16_t wObjectiveFocalLengthMin; + uint16_t wObjectiveFocalLengthMax; + uint16_t wOcularFocalLength; uint8_t bControlSize; - uint8_t bmaControls[]; -} tusb_desc_cs_video_stm_itf_in_hdr_t; + uint8_t bmControls[3]; +} tusb_desc_video_control_camera_terminal_t; + +TU_VERIFY_STATIC(sizeof(tusb_desc_video_control_camera_terminal_t) == 18, "size is not correct"); + +//--------------------------------------------------------------------+ +// Video Streaming (VS) Descriptors +//--------------------------------------------------------------------+ + +/* 3.9.2.1 */ +#define tusb_desc_video_streaming_input_header_nbyte_t(_nb) \ + struct TU_ATTR_PACKED { \ + uint8_t bLength; \ + uint8_t bDescriptorType; \ + uint8_t bDescriptorSubType; \ + uint8_t bNumFormats; /* Number of video payload Format descriptors for this interface */ \ + uint16_t wTotalLength; \ + uint8_t bEndpointAddress; \ + uint8_t bmInfo; /* Bit 0: dynamic format change supported */ \ + uint8_t bTerminalLink; \ + uint8_t bStillCaptureMethod; \ + uint8_t bTriggerSupport; /* Hardware trigger supported */ \ + uint8_t bTriggerUsage; \ + uint8_t bControlSize; /* sizeof of each control item */ \ + uint8_t bmaControls[_nb]; \ + } + +typedef tusb_desc_video_streaming_input_header_nbyte_t() tusb_desc_video_streaming_input_header_t; +typedef tusb_desc_video_streaming_input_header_nbyte_t(1) tusb_desc_video_streaming_input_header_1byte_t; +typedef tusb_desc_video_streaming_input_header_nbyte_t(2) tusb_desc_video_streaming_input_header_2byte_t; +typedef tusb_desc_video_streaming_input_header_nbyte_t(3) tusb_desc_video_streaming_input_header_3byte_t; +typedef tusb_desc_video_streaming_input_header_nbyte_t(4) tusb_desc_video_streaming_input_header_4byte_t; /* 3.9.2.2 */ typedef struct TU_ATTR_PACKED { @@ -259,7 +306,7 @@ typedef struct TU_ATTR_PACKED { uint8_t bTerminalLink; uint8_t bControlSize; uint8_t bmaControls[]; -} tusb_desc_cs_video_stm_itf_out_hdr_t; +} tusb_desc_video_streaming_output_header_t; typedef struct TU_ATTR_PACKED { uint8_t bLength; @@ -285,14 +332,33 @@ typedef struct TU_ATTR_PACKED { uint8_t bmaControls[]; } output; }; -} tusb_desc_cs_video_stm_itf_hdr_t; +} tusb_desc_video_streaming_inout_header_t; +// 3.9.2.6 Color Matching Descriptor +typedef struct TU_ATTR_PACKED { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bColorPrimaries; + uint8_t bTransferCharacteristics; + uint8_t bMatrixCoefficients; +} tusb_desc_video_streaming_color_matching_t; + +TU_VERIFY_STATIC(sizeof(tusb_desc_video_streaming_color_matching_t) == 6, "size is not correct"); + +//--------------------------------------------------------------------+ +// Format and Frame Descriptor +// Note: bFormatIndex & bFrameIndex are 1-based index +//--------------------------------------------------------------------+ + +//------------- Uncompressed -------------// +// Uncompressed payload specs: 3.1.1 format descriptor typedef struct TU_ATTR_PACKED { uint8_t bLength; uint8_t bDescriptorType; uint8_t bDescriptorSubType; uint8_t bFormatIndex; - uint8_t bNumFrameDescriptors; + uint8_t bNumFrameDescriptors; // Number of frame descriptors for this format uint8_t guidFormat[16]; uint8_t bBitsPerPixel; uint8_t bDefaultFrameIndex; @@ -300,8 +366,39 @@ typedef struct TU_ATTR_PACKED { uint8_t bAspectRatioY; uint8_t bmInterlaceFlags; uint8_t bCopyProtect; -} tusb_desc_cs_video_fmt_uncompressed_t; - +} tusb_desc_video_format_uncompressed_t; + +// Uncompressed payload specs: 3.1.2 frame descriptor +#define tusb_desc_video_frame_uncompressed_nint_t(_nint) \ + struct TU_ATTR_PACKED { \ + uint8_t bLength; \ + uint8_t bDescriptorType; \ + uint8_t bDescriptorSubType; \ + uint8_t bFrameIndex; \ + uint8_t bmCapabilities; \ + uint16_t wWidth; \ + uint16_t wHeight; \ + uint32_t dwMinBitRate; \ + uint32_t dwMaxBitRate; \ + uint32_t dwMaxVideoFrameBufferSize; /* deprecated in 1.5 */ \ + uint32_t dwDefaultFrameInterval; \ + uint8_t bFrameIntervalType; \ + uint32_t dwFrameInterval[_nint]; \ + } + +typedef tusb_desc_video_frame_uncompressed_nint_t() tusb_desc_video_frame_uncompressed_t; +typedef tusb_desc_video_frame_uncompressed_nint_t(1) tusb_desc_video_frame_uncompressed_1int_t; +typedef tusb_desc_video_frame_uncompressed_nint_t(2) tusb_desc_video_frame_uncompressed_2int_t; +typedef tusb_desc_video_frame_uncompressed_nint_t(3) tusb_desc_video_frame_uncompressed_3int_t; +typedef tusb_desc_video_frame_uncompressed_nint_t(4) tusb_desc_video_frame_uncompressed_4int_t; + +// continuous = 3 intervals: min, max, step +typedef tusb_desc_video_frame_uncompressed_3int_t tusb_desc_video_frame_uncompressed_continuous_t; + +TU_VERIFY_STATIC(sizeof(tusb_desc_video_frame_uncompressed_continuous_t) == 38, "size is not correct"); + +//------------- MJPEG -------------// +// MJPEG payload specs: 3.1.1 formatt descriptor typedef struct TU_ATTR_PACKED { uint8_t bLength; uint8_t bDescriptorType; @@ -314,8 +411,12 @@ typedef struct TU_ATTR_PACKED { uint8_t bAspectRatioY; uint8_t bmInterlaceFlags; uint8_t bCopyProtect; -} tusb_desc_cs_video_fmt_mjpeg_t; +} tusb_desc_video_format_mjpeg_t; +// MJPEG payload specs: 3.1.2 frame descriptor (same as uncompressed) +typedef tusb_desc_video_frame_uncompressed_t tusb_desc_video_frame_mjpeg_t; + +// DV payload specs: 3.1.1 typedef struct TU_ATTR_PACKED { uint8_t bLength; uint8_t bDescriptorType; @@ -323,8 +424,9 @@ typedef struct TU_ATTR_PACKED { uint8_t bFormatIndex; uint32_t dwMaxVideoFrameBufferSize; /* deprecated */ uint8_t bFormatType; -} tusb_desc_cs_video_fmt_dv_t; +} tusb_desc_video_format_dv_t; +// Frame Based payload specs: 3.1.1 typedef struct TU_ATTR_PACKED { uint8_t bLength; uint8_t bDescriptorType; @@ -339,25 +441,7 @@ typedef struct TU_ATTR_PACKED { uint8_t bmInterlaceFlags; uint8_t bCopyProtect; uint8_t bVaribaleSize; -} tusb_desc_cs_video_fmt_frame_based_t; - -typedef struct TU_ATTR_PACKED { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubType; - uint8_t bFrameIndex; - uint8_t bmCapabilities; - uint16_t wWidth; - uint16_t wHeight; - uint32_t dwMinBitRate; - uint32_t dwMaxBitRate; - uint32_t dwMaxVideoFrameBufferSize; /* deprecated */ - uint32_t dwDefaultFrameInterval; - uint8_t bFrameIntervalType; - uint32_t dwFrameInterval[]; -} tusb_desc_cs_video_frm_uncompressed_t; - -typedef tusb_desc_cs_video_frm_uncompressed_t tusb_desc_cs_video_frm_mjpeg_t; +} tusb_desc_video_format_framebased_t; typedef struct TU_ATTR_PACKED { uint8_t bLength; @@ -373,12 +457,30 @@ typedef struct TU_ATTR_PACKED { uint8_t bFrameIntervalType; uint32_t dwBytesPerLine; uint32_t dwFrameInterval[]; -} tusb_desc_cs_video_frm_frame_based_t; +} tusb_desc_video_frame_framebased_t; //--------------------------------------------------------------------+ // Requests //--------------------------------------------------------------------+ +/* 2.4.3.3 */ +typedef struct TU_ATTR_PACKED { + uint8_t bHeaderLength; + union { + uint8_t bmHeaderInfo; + struct { + uint8_t FrameID: 1; + uint8_t EndOfFrame: 1; + uint8_t PresentationTime: 1; + uint8_t SourceClockReference: 1; + uint8_t PayloadSpecific: 1; + uint8_t StillImage: 1; + uint8_t Error: 1; + uint8_t EndOfHeader: 1; + }; + }; +} tusb_video_payload_header_t; + /* 4.3.1.1 */ typedef struct TU_ATTR_PACKED { union { diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index c16a45fcd..1affd615e 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -50,17 +50,17 @@ typedef struct { tusb_desc_interface_t std; - tusb_desc_cs_video_ctl_itf_hdr_t ctl; + tusb_desc_video_control_header_t ctl; } tusb_desc_vc_itf_t; typedef struct { tusb_desc_interface_t std; - tusb_desc_cs_video_stm_itf_hdr_t stm; + tusb_desc_video_streaming_inout_header_t stm; } tusb_desc_vs_itf_t; typedef union { - tusb_desc_cs_video_ctl_itf_hdr_t ctl; - tusb_desc_cs_video_stm_itf_hdr_t stm; + tusb_desc_video_control_header_t ctl; + tusb_desc_video_streaming_inout_header_t stm; } tusb_desc_video_itf_hdr_t; typedef struct TU_ATTR_PACKED { @@ -78,9 +78,9 @@ typedef union { uint8_t bFormatIndex; uint8_t bNumFrameDescriptors; }; - tusb_desc_cs_video_fmt_uncompressed_t uncompressed; - tusb_desc_cs_video_fmt_mjpeg_t mjpeg; - tusb_desc_cs_video_fmt_frame_based_t frame_based; + tusb_desc_video_format_uncompressed_t uncompressed; + tusb_desc_video_format_mjpeg_t mjpeg; + tusb_desc_video_format_framebased_t frame_based; } tusb_desc_cs_video_fmt_t; typedef union { @@ -93,9 +93,9 @@ typedef union { uint16_t wWidth; uint16_t wHeight; }; - tusb_desc_cs_video_frm_uncompressed_t uncompressed; - tusb_desc_cs_video_frm_mjpeg_t mjpeg; - tusb_desc_cs_video_frm_frame_based_t frame_based; + tusb_desc_video_frame_uncompressed_t uncompressed; + tusb_desc_video_frame_mjpeg_t mjpeg; + tusb_desc_video_frame_framebased_t frame_based; } tusb_desc_cs_video_frm_t; /* video streaming interface */ diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index d4ef1fd09..2c5dce723 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -399,6 +399,8 @@ typedef struct TU_ATTR_PACKED { uint8_t iFunction ; ///< Index of the string descriptor describing the interface association. } tusb_desc_interface_assoc_t; +TU_VERIFY_STATIC( sizeof(tusb_desc_interface_assoc_t) == 8, "size is not correct"); + // USB String Descriptor typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of this descriptor in bytes @@ -469,7 +471,6 @@ typedef struct TU_ATTR_PACKED { TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct"); - TU_ATTR_PACKED_END // End of all packed definitions TU_ATTR_BIT_FIELD_ORDER_END -- cgit v1.3.1 From 0daf8ec51b9513fbab9601fedb2150dda3927b05 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 26 Jan 2024 23:23:38 +0700 Subject: update example to work bulk mjpeg --- .../device/video_capture/src/usb_descriptors.c | 27 +++++++++++++++++++++- src/class/video/video.h | 10 +++++++- 2 files changed, 35 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c index 8e54d3afd..90a6b27a2 100644 --- a/examples/device/video_capture/src/usb_descriptors.c +++ b/examples/device/video_capture/src/usb_descriptors.c @@ -109,6 +109,10 @@ uint8_t const* tud_descriptor_device_cb(void) { #define EPNUM_VIDEO_IN 0x81 #endif +#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG) + #define USE_MJPEG +#endif + // For mcus that does not have enough SRAM for frame buffer, we use fixed frame data. // To further reduce the size, we use MJPEG format instead of YUY2. // Select interface descriptor and length accordingly. @@ -197,8 +201,15 @@ typedef struct TU_ATTR_PACKED { typedef struct TU_ATTR_PACKED { tusb_desc_interface_t itf; tusb_desc_video_streaming_input_header_1byte_t header; + +#ifdef USE_MJPEG + tusb_desc_video_format_mjpeg_t format; + tusb_desc_video_frame_mjpeg_continuous_t frame; +#else tusb_desc_video_format_uncompressed_t format; tusb_desc_video_frame_uncompressed_continuous_t frame; +#endif + tusb_desc_video_streaming_color_matching_t color; tusb_desc_endpoint_t ep; } uvc_streaming_desc_t; @@ -316,14 +327,22 @@ const uvc_cfg_desc_t config_desc = { .bmaControls = { 0 } }, .format = { +#ifdef USE_MJPEG + .bLength = sizeof(tusb_desc_video_format_mjpeg_t), + .bDescriptorType = TUSB_DESC_CS_INTERFACE, + .bDescriptorSubType = VIDEO_CS_ITF_VS_FORMAT_MJPEG, + .bFormatIndex = 1, // 1-based index + .bNumFrameDescriptors = 1, + .bmFlags = 0, +#else .bLength = sizeof(tusb_desc_video_format_uncompressed_t), .bDescriptorType = TUSB_DESC_CS_INTERFACE, .bDescriptorSubType = VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED, - .bFormatIndex = 1, // 1-based index .bNumFrameDescriptors = 1, .guidFormat = { TUD_VIDEO_GUID_YUY2 }, .bBitsPerPixel = 16, +#endif .bDefaultFrameIndex = 1, .bAspectRatioX = 0, .bAspectRatioY = 0, @@ -331,9 +350,15 @@ const uvc_cfg_desc_t config_desc = { .bCopyProtect = 0 }, .frame = { +#ifdef USE_MJPEG + .bLength = sizeof(tusb_desc_video_frame_mjpeg_continuous_t), + .bDescriptorType = TUSB_DESC_CS_INTERFACE, + .bDescriptorSubType = VIDEO_CS_ITF_VS_FRAME_MJPEG, +#else .bLength = sizeof(tusb_desc_video_frame_uncompressed_continuous_t), .bDescriptorType = TUSB_DESC_CS_INTERFACE, .bDescriptorSubType = VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED, +#endif .bFrameIndex = 1, // 1-based index .bmCapabilities = 0, diff --git a/src/class/video/video.h b/src/class/video/video.h index 162d4e4c4..bed8eeecf 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -405,7 +405,7 @@ typedef struct TU_ATTR_PACKED { uint8_t bDescriptorSubType; uint8_t bFormatIndex; uint8_t bNumFrameDescriptors; - uint8_t bmFlags; + uint8_t bmFlags; // Bit 0: fixed size samples (1 = yes) uint8_t bDefaultFrameIndex; uint8_t bAspectRatioX; uint8_t bAspectRatioY; @@ -415,7 +415,15 @@ typedef struct TU_ATTR_PACKED { // MJPEG payload specs: 3.1.2 frame descriptor (same as uncompressed) typedef tusb_desc_video_frame_uncompressed_t tusb_desc_video_frame_mjpeg_t; +typedef tusb_desc_video_frame_uncompressed_1int_t tusb_desc_video_frame_mjpeg_1int_t; +typedef tusb_desc_video_frame_uncompressed_2int_t tusb_desc_video_frame_mjpeg_2int_t; +typedef tusb_desc_video_frame_uncompressed_3int_t tusb_desc_video_frame_mjpeg_3int_t; +typedef tusb_desc_video_frame_uncompressed_4int_t tusb_desc_video_frame_mjpeg_4int_t; +// continuous = 3 intervals: min, max, step +typedef tusb_desc_video_frame_mjpeg_3int_t tusb_desc_video_frame_mjpeg_continuous_t; + +//------------- DV -------------// // DV payload specs: 3.1.1 typedef struct TU_ATTR_PACKED { uint8_t bLength; -- cgit v1.3.1 From 82be2477e8201fe6ea61324b8995b79d1b4cab46 Mon Sep 17 00:00:00 2001 From: IngHK Date: Mon, 29 Jan 2024 12:04:00 +0100 Subject: fixed #2437 --- src/class/cdc/cdc_host.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 7adaa0c8c..36b5d4234 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -77,6 +77,8 @@ typedef struct { uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE]; } stream; + + bool configured; } cdch_interface_t; CFG_TUH_MEM_SECTION @@ -257,6 +259,7 @@ static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass; p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol; p_cdc->line_state = 0; + p_cdc->configured = false; return p_cdc; } } @@ -305,7 +308,8 @@ bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) { bool tuh_cdc_mounted(uint8_t idx) { cdch_interface_t* p_cdc = get_itf(idx); - return p_cdc != NULL; + TU_VERIFY(p_cdc); + return p_cdc->configured; } bool tuh_cdc_get_dtr(uint8_t idx) { @@ -747,6 +751,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num) { TU_LOG_DRV("CDCh Set Configure complete\r\n"); + p_cdc->configured = true; if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx); // Prepare for incoming data -- cgit v1.3.1 From 55950656cbee915662a9a33477ddd549489ffcf0 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 29 Jan 2024 23:23:06 +0700 Subject: add freertos build support for video_capture example --- examples/device/video_capture/src/CMakeLists.txt | 4 + examples/device/video_capture/src/main.c | 131 ++++++++++++++++++--- examples/device/video_capture/src/tusb_config.h | 8 ++ .../device/video_capture/src/usb_descriptors.c | 29 +++-- hw/bsp/board_api.h | 19 ++- src/class/video/video.h | 2 +- 6 files changed, 170 insertions(+), 23 deletions(-) create mode 100644 examples/device/video_capture/src/CMakeLists.txt (limited to 'src') diff --git a/examples/device/video_capture/src/CMakeLists.txt b/examples/device/video_capture/src/CMakeLists.txt new file mode 100644 index 000000000..cef2b46ee --- /dev/null +++ b/examples/device/video_capture/src/CMakeLists.txt @@ -0,0 +1,4 @@ +# This file is for ESP-IDF only +idf_component_register(SRCS "main.c" "usb_descriptors.c" + INCLUDE_DIRS "." + REQUIRES boards tinyusb_src) diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index e63335e67..091eb8d0c 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -48,13 +48,25 @@ enum { static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED; -void led_blinking_task(void); -void video_task(void); +void led_blinking_task(void* param); +void usb_device_task(void *param); +void video_task(void* param); -/*------------- MAIN -------------*/ +#if CFG_TUSB_OS == OPT_OS_FREERTOS +void freertos_init_task(void); +#endif + + +//--------------------------------------------------------------------+ +// Main +//--------------------------------------------------------------------+ int main(void) { board_init(); + // If using FreeRTOS: create blinky, tinyusb device, video task +#if CFG_TUSB_OS == OPT_OS_FREERTOS + freertos_init_task(); +#else // init device stack on configured roothub port tud_init(BOARD_TUD_RHPORT); @@ -64,10 +76,10 @@ int main(void) { while (1) { tud_task(); // tinyusb device task - led_blinking_task(); - - video_task(); + led_blinking_task(NULL); + video_task(NULL); } +#endif } //--------------------------------------------------------------------+ @@ -169,7 +181,7 @@ static void fill_color_bar(uint8_t* buffer, unsigned start_position) { #endif -void video_task(void) { +void video_send_frame(void) { static unsigned start_ms = 0; static unsigned already_sent = 0; @@ -213,6 +225,21 @@ void video_task(void) { #endif } + +void video_task(void* param) { + (void) param; + + while(1) { + video_send_frame(); + + #if CFG_TUSB_OS == OPT_OS_FREERTOS + vTaskDelay(interval_ms / portTICK_PERIOD_MS); + #else + return; + #endif + } +} + void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) { (void) ctl_idx; (void) stm_idx; @@ -231,16 +258,92 @@ int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, } //--------------------------------------------------------------------+ -// BLINKING TASK +// Blinking Task //--------------------------------------------------------------------+ -void led_blinking_task(void) { +void led_blinking_task(void* param) { + (void) param; static uint32_t start_ms = 0; static bool led_state = false; - // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) return; // not enough time - start_ms += blink_interval_ms; + while (1) { + #if CFG_TUSB_OS == OPT_OS_FREERTOS + vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS); + #else + if (board_millis() - start_ms < blink_interval_ms) return; // not enough time + #endif + + start_ms += blink_interval_ms; + board_led_write(led_state); + led_state = 1 - led_state; // toggle + } +} + +//--------------------------------------------------------------------+ +// FreeRTOS +//--------------------------------------------------------------------+ +#if CFG_TUSB_OS == OPT_OS_FREERTOS + +#define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE +#define VIDEO_STACK_SIZE (configMINIMAL_STACK_SIZE*4) + +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) + #define USBD_STACK_SIZE 4096 + int main(void); + void app_main(void) { + main(); + } +#else + // Increase stack size when debug log is enabled + #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1) +#endif + +// static task +#if configSUPPORT_STATIC_ALLOCATION +StackType_t blinky_stack[BLINKY_STACK_SIZE]; +StaticTask_t blinky_taskdef; + +StackType_t usb_device_stack[USBD_STACK_SIZE]; +StaticTask_t usb_device_taskdef; + +StackType_t video_stack[VIDEO_STACK_SIZE]; +StaticTask_t video_taskdef; +#endif + +// USB Device Driver task +// This top level thread process all usb events and invoke callbacks +void usb_device_task(void *param) { + (void) param; + + // init device stack on configured roothub port + // This should be called after scheduler/kernel is started. + // Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API. + tud_init(BOARD_TUD_RHPORT); + + if (board_init_after_tusb) { + board_init_after_tusb(); + } - board_led_write(led_state); - led_state = 1 - led_state; // toggle + // RTOS forever loop + while (1) { + // put this thread to waiting state until there is new events + tud_task(); + } } + +void freertos_init_task(void) { + #if configSUPPORT_STATIC_ALLOCATION + xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef); + xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef); + xTaskCreateStatic(video_task, "cdc", VIDEO_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, video_stack, &video_taskdef); + #else + xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL); + xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL); + xTaskCreate(video_task, "video", VIDEO_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL); + #endif + + // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 + #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) + vTaskStartScheduler(); + #endif +} +#endif diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h index d563c6f5c..bdfc37d87 100644 --- a/examples/device/video_capture/src/tusb_config.h +++ b/examples/device/video_capture/src/tusb_config.h @@ -57,6 +57,11 @@ #define CFG_TUSB_OS OPT_OS_NONE #endif +// Espressif IDF requires "freertos/" prefix in include path +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) +#define CFG_TUSB_OS_INC_PATH freertos/ +#endif + #ifndef CFG_TUSB_DEBUG #define CFG_TUSB_DEBUG 0 #endif @@ -103,6 +108,9 @@ // use bulk endpoint for streaming interface #define CFG_TUD_VIDEO_STREAMING_BULK 1 +//#define CFG_EXAMPLE_VIDEO_READONLY +//#define CFG_EXAMPLE_VIDEO_DISABLE_MJPEG + #ifdef __cplusplus } #endif diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c index 17e11229d..f308c75a7 100644 --- a/examples/device/video_capture/src/usb_descriptors.c +++ b/examples/device/video_capture/src/usb_descriptors.c @@ -364,7 +364,22 @@ const uvc_cfg_desc_t desc_fs_configuration = { }; #if TUD_OPT_HIGH_SPEED -uvc_cfg_desc_t desc_hs_configuration = desc_fs_configuration; +uvc_cfg_desc_t desc_hs_configuration; + +static uint8_t * get_hs_configuration_desc(void) { + static bool init = false; + + if (!init) { + desc_hs_configuration = desc_fs_configuration; + // change endpoint bulk size to 512 if bulk streaming + if (CFG_TUD_VIDEO_STREAMING_BULK) { + desc_hs_configuration.video_streaming.ep.wMaxPacketSize = 512; + } + } + init = true; + + return (uint8_t *) &desc_hs_configuration; +} // device qualifier is mostly similar to device descriptor since we don't change configuration based on speed tusb_desc_device_qualifier_t const desc_device_qualifier = { @@ -395,7 +410,11 @@ uint8_t const* tud_descriptor_device_qualifier_cb(void) { uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) { (void) index; // for multiple configurations // if link speed is high return fullspeed config, and vice versa - return (uint8_t const*) ((tud_speed_get() == TUSB_SPEED_HIGH) ? &desc_fs_configuration : &desc_hs_configuration); + if (tud_speed_get() == TUSB_SPEED_HIGH) { + return (uint8_t const*) &desc_fs_configuration; + } else { + return get_hs_configuration_desc(); + } } #endif // highspeed @@ -408,11 +427,7 @@ uint8_t const* tud_descriptor_configuration_cb(uint8_t index) { #if TUD_OPT_HIGH_SPEED // Although we are highspeed, host may be fullspeed. if (tud_speed_get() == TUSB_SPEED_HIGH) { - // change endpoint bulk size to 512 if bulk streaming - if (CFG_TUD_VIDEO_STREAMING_BULK) { - desc_hs_configuration.video_streaming.ep.wMaxPacketSize = 512; - } - return (uint8_t const*) &desc_hs_configuration; + return get_hs_configuration_desc(); } else #endif { diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h index 404509a28..0c8a35924 100644 --- a/hw/bsp/board_api.h +++ b/hw/bsp/board_api.h @@ -33,9 +33,26 @@ extern "C" { #include #include - #include "tusb.h" +#if CFG_TUSB_OS == OPT_OS_FREERTOS +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) + // ESP-IDF need "freertos/" prefix in include path. + // CFG_TUSB_OS_INC_PATH should be defined accordingly. + #include "freertos/FreeRTOS.h" + #include "freertos/semphr.h" + #include "freertos/queue.h" + #include "freertos/task.h" + #include "freertos/timers.h" +#else + #include "FreeRTOS.h" + #include "semphr.h" + #include "queue.h" + #include "task.h" + #include "timers.h" +#endif +#endif + // Define the default baudrate #ifndef CFG_BOARD_UART_BAUDRATE #define CFG_BOARD_UART_BAUDRATE 115200 ///< Default baud rate diff --git a/src/class/video/video.h b/src/class/video/video.h index bed8eeecf..fb0d0af1d 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -398,7 +398,7 @@ typedef tusb_desc_video_frame_uncompressed_3int_t tusb_desc_video_frame_uncompre TU_VERIFY_STATIC(sizeof(tusb_desc_video_frame_uncompressed_continuous_t) == 38, "size is not correct"); //------------- MJPEG -------------// -// MJPEG payload specs: 3.1.1 formatt descriptor +// MJPEG payload specs: 3.1.1 format descriptor typedef struct TU_ATTR_PACKED { uint8_t bLength; uint8_t bDescriptorType; -- cgit v1.3.1 From 00ba4e95acec64da4446fa89a40c3a2e38beed3c Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 30 Jan 2024 10:59:12 +0700 Subject: cdch: de-configure when closing, rename configured to mounted --- src/class/cdc/cdc_host.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 36b5d4234..4e0a9499f 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -53,12 +53,13 @@ typedef struct { uint8_t bInterfaceSubClass; uint8_t bInterfaceProtocol; + uint8_t ep_notif; uint8_t serial_drid; // Serial Driver ID + bool mounted; // Enumeration is complete cdc_acm_capability_t acm_capability; - uint8_t ep_notif; - uint8_t line_state; // DTR (bit0), RTS (bit1) TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width + uint8_t line_state; // DTR (bit0), RTS (bit1) #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X cdc_line_coding_t requested_line_coding; @@ -77,8 +78,6 @@ typedef struct { uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE]; } stream; - - bool configured; } cdch_interface_t; CFG_TUH_MEM_SECTION @@ -259,7 +258,6 @@ static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass; p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol; p_cdc->line_state = 0; - p_cdc->configured = false; return p_cdc; } } @@ -309,7 +307,7 @@ bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) { bool tuh_cdc_mounted(uint8_t idx) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return p_cdc->configured; + return p_cdc->mounted; } bool tuh_cdc_get_dtr(uint8_t idx) { @@ -648,9 +646,9 @@ void cdch_close(uint8_t daddr) { // Invoke application callback if (tuh_cdc_umount_cb) tuh_cdc_umount_cb(idx); - //tu_memclr(p_cdc, sizeof(cdch_interface_t)); p_cdc->daddr = 0; p_cdc->bInterfaceNumber = 0; + p_cdc->mounted = false; tu_edpt_stream_close(&p_cdc->stream.tx); tu_edpt_stream_close(&p_cdc->stream.rx); } @@ -751,7 +749,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num) { TU_LOG_DRV("CDCh Set Configure complete\r\n"); - p_cdc->configured = true; + p_cdc->mounted = true; if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx); // Prepare for incoming data -- cgit v1.3.1 From f600a8a0fc263b764ea018f0d0912f8001dd3160 Mon Sep 17 00:00:00 2001 From: IngHK Date: Tue, 30 Jan 2024 10:33:55 +0100 Subject: fix tuh_hid_mounted() similar to #2437 --- src/class/hid/hid_host.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index db52b503f..709fa3dd8 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -50,6 +50,7 @@ typedef struct uint8_t itf_num; uint8_t ep_in; uint8_t ep_out; + bool mounted; // Enumeration is complete uint8_t itf_protocol; // None, Keyboard, Mouse uint8_t protocol_mode; // Boot (0) or Report protocol (1) @@ -139,7 +140,8 @@ uint8_t tuh_hid_itf_get_total_count(void) bool tuh_hid_mounted(uint8_t daddr, uint8_t idx) { hidh_interface_t* p_hid = get_hid_itf(daddr, idx); - return p_hid != NULL; + TU_VERIFY(p_hid); + return p_hid->mounted; } bool tuh_hid_itf_get_info(uint8_t daddr, uint8_t idx, tuh_itf_info_t* info) @@ -463,6 +465,7 @@ void hidh_close(uint8_t daddr) TU_LOG_DRV(" HIDh close addr = %u index = %u\r\n", daddr, i); if(tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i); p_hid->daddr = 0; + p_hid->mounted = false; } } } @@ -632,6 +635,7 @@ static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t con { hidh_interface_t* p_hid = get_hid_itf(daddr, idx); TU_VERIFY(p_hid, ); + p_hid->mounted = true; // enumeration is complete if (tuh_hid_mount_cb) tuh_hid_mount_cb(daddr, idx, desc_report, desc_len); -- cgit v1.3.1 From 82776aaca9f7a8ae1b627c42cd69a021b1b50fe3 Mon Sep 17 00:00:00 2001 From: mamiral Date: Wed, 31 Jan 2024 10:48:15 +0100 Subject: Update vendor_device.c fifo mutex config similar to cdc_device.c. --- src/class/vendor/vendor_device.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index 389a29696..a68cb2156 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -49,10 +49,8 @@ typedef struct uint8_t rx_ff_buf[CFG_TUD_VENDOR_RX_BUFSIZE]; uint8_t tx_ff_buf[CFG_TUD_VENDOR_TX_BUFSIZE]; -#if CFG_FIFO_MUTEX - osal_mutex_def_t rx_ff_mutex; - osal_mutex_def_t tx_ff_mutex; -#endif + OSAL_MUTEX_DEF(rx_ff_mutex); + OSAL_MUTEX_DEF(tx_ff_mutex); // Endpoint Transfer buffer CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_VENDOR_EPSIZE]; @@ -183,10 +181,8 @@ void vendord_init(void) tu_fifo_config(&p_itf->rx_ff, p_itf->rx_ff_buf, CFG_TUD_VENDOR_RX_BUFSIZE, 1, false); tu_fifo_config(&p_itf->tx_ff, p_itf->tx_ff_buf, CFG_TUD_VENDOR_TX_BUFSIZE, 1, false); -#if CFG_FIFO_MUTEX tu_fifo_config_mutex(&p_itf->rx_ff, NULL, osal_mutex_create(&p_itf->rx_ff_mutex)); tu_fifo_config_mutex(&p_itf->tx_ff, osal_mutex_create(&p_itf->tx_ff_mutex), NULL); -#endif } } -- cgit v1.3.1 From e63a2f5c58b111a5f990ad1b6a0260f09a248c53 Mon Sep 17 00:00:00 2001 From: IngHK Date: Wed, 31 Jan 2024 18:00:25 +0100 Subject: fix #2444 and other small things --- src/class/cdc/cdc_host.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 4e0a9499f..2fb37d835 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1345,7 +1345,7 @@ static inline bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, ui complete_cb, user_data); } -static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static inline bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, reg_value, complete_cb, user_data); } @@ -1358,7 +1358,7 @@ static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_ static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate); - TU_VERIFY(div_ps != 0); + TU_VERIFY(div_ps); TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps, complete_cb, user_data)); return true; @@ -1379,7 +1379,7 @@ static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, ui p_cdc->requested_line_coding.data_bits = data_bits; uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits); - TU_VERIFY(lcr != 0); + TU_VERIFY(lcr); TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr, complete_cb ? ch34x_control_complete : NULL, user_data)); return true; @@ -1395,6 +1395,7 @@ static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, } static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t* xfer) { + // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber uint8_t const itf_num = 0; uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t* p_cdc = get_itf(idx); @@ -1443,7 +1444,7 @@ static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t con // update transfer result, user_data is expected to point to xfer_result_t if (user_data) { - user_data = result; + *((xfer_result_t*) user_data) = result; } } @@ -1513,8 +1514,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { uintptr_t const state = xfer->user_data; uint8_t buffer[2]; // TODO remove TU_ASSERT (p_cdc,); - - // TODO check xfer->result + TU_ASSERT (xfer->result == XFER_RESULT_SUCCESS,); switch (state) { case CONFIG_CH34X_READ_VERSION: @@ -1531,9 +1531,9 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { // init CH34x with line coding cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate); - TU_ASSERT(div_ps != 0, ); + TU_ASSERT(div_ps, ); uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits); - TU_ASSERT(lcr != 0, ); + TU_ASSERT(lcr, ); TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps, ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),); break; @@ -1573,7 +1573,7 @@ static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) { uint8_t b; uint32_t c; - TU_VERIFY(baval != 0, 0); + TU_VERIFY(baval != 0 && baval <= 2000000, 0); switch (baval) { case 921600: a = 0xf3; @@ -1627,7 +1627,7 @@ static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bit break; case CDC_LINE_CODING_PARITY_ODD: - lcr |= CH34X_LCR_ENABLE_PAR; + lcr |= CH34X_LCR_ENABLE_PAR; break; case CDC_LINE_CODING_PARITY_EVEN: -- cgit v1.3.1 From e784e20b93068f4b063e066eb50ea005aeec99f4 Mon Sep 17 00:00:00 2001 From: IngHK Date: Wed, 7 Feb 2024 10:11:28 +0100 Subject: changes after review --- src/host/usbh.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index ee7424ed9..d4f308e48 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -291,9 +291,6 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t *vid, uint16_t *pid) { *vid = dev->vid; *pid = dev->pid; - TU_LOG_HEX_USBH(*vid); - TU_LOG_HEX_USBH(*pid); - return true; } @@ -863,7 +860,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b // HCD error, mark endpoint as ready to allow next transfer ep_state->busy = 0; ep_state->claimed = 0; - TU_LOG_USBH("Failed\r\n"); + TU_LOG1("Failed\r\n"); // TU_BREAKPOINT(); return false; } @@ -1321,7 +1318,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { if ( retry ) { failed_count++; osal_task_delay(ATTEMPT_DELAY_MS); // delay a bit - TU_LOG_USBH("Enumeration attempt %u\r\n", failed_count); + TU_LOG1("Enumeration attempt %u\r\n", failed_count); retry = tuh_control_xfer(xfer); } -- cgit v1.3.1 From 4d4e20b71efe8d9e1b5a141d84e058ff54801c67 Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 8 Feb 2024 12:00:44 +0100 Subject: missing \r\n after TU_LOG_BUF => moved \r\n to tu_print_buf() --- src/common/tusb_debug.h | 1 + src/device/usbd.c | 1 - src/host/usbh.c | 2 -- 3 files changed, 1 insertion(+), 3 deletions(-) (limited to 'src') diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h index 8db1606ae..2e9f1d9cd 100644 --- a/src/common/tusb_debug.h +++ b/src/common/tusb_debug.h @@ -60,6 +60,7 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent); static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) { for(uint32_t i=0; isetup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ? tu_str_std_request[xfer->setup->bRequest] : "Class Request"); TU_LOG_BUF_USBH(xfer->setup, 8); - TU_LOG_USBH("\r\n"); if (xfer->complete_cb) { TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) ); @@ -662,7 +661,6 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result if (XFER_RESULT_SUCCESS != result) { TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes); TU_LOG_BUF_USBH(request, 8); - TU_LOG_USBH("\r\n"); // terminate transfer if any stage failed _xfer_complete(dev_addr, result); -- cgit v1.3.1 From 68bb85840639b2a3d8c4ad51e31245bd039e5b9f Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Mon, 12 Feb 2024 16:12:32 +0100 Subject: nrf5x: Handle ISOOUT CRC errors NRF5x USB controller can detect ISO OUT CRC errors. In such case USBEVENT is signaled with EVENTCAUSE_ISOOUTCRC set. Even if controller detects corrupted ISO OUT packet it allows to data transfer from ednpoint to RAM however packet is corrupted and code could just as well drop packet altogether. With current implementation incoming ISO OUT packets were put in FIFO and exact information how much data already in FIFO is correct was hard to keep track of. If was observed that on certain configurations HS hub when FS device was connected occasionally sent invalid (short) packet. In such case if packet length was reported odd audio stream was not recognizable any more. With this change corrupted packets are not passed to upper layers and are silently dropped. --- src/portable/nordic/nrf5x/dcd_nrf5x.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index 4e702aed4..841cda752 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -653,7 +653,11 @@ void dcd_int_handler(uint8_t rhport) if (NRF_USBD->EPOUTEN & USBD_EPOUTEN_ISOOUT_Msk) { iso_enabled = true; - xact_out_dma(EP_ISO_NUM); + // Transfer from endpoint to RAM only if data is not corrupted + if ((int_status & USBD_INTEN_USBEVENT_Msk) == 0 || + (NRF_USBD->EVENTCAUSE & USBD_EVENTCAUSE_ISOOUTCRC_Msk) == 0) { + xact_out_dma(EP_ISO_NUM); + } } // ISOIN: Notify client that data was transferred @@ -683,7 +687,7 @@ void dcd_int_handler(uint8_t rhport) { TU_LOG(2, "EVENTCAUSE = 0x%04lX\r\n", NRF_USBD->EVENTCAUSE); - enum { EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk }; + enum { EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk | USBD_EVENTCAUSE_ISOOUTCRC_Msk }; uint32_t const evt_cause = NRF_USBD->EVENTCAUSE & EVT_CAUSE_MASK; NRF_USBD->EVENTCAUSE = evt_cause; // clear interrupt -- cgit v1.3.1 From 79aecf3fb7d6a384eb745253d11a95d657469eed Mon Sep 17 00:00:00 2001 From: IngHK Date: Wed, 14 Feb 2024 09:16:18 +0100 Subject: fixed #2469 --- src/common/tusb_fifo.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index d6c3db4ce..76696396b 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -224,6 +224,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t if (wrap_bytes > 0) _ff_push_const_addr(ff_buf, app_buf, wrap_bytes); } break; + default: break; } } -- cgit v1.3.1 From 5ca99800604ec3ed9d45bf4660db04101aa737ce Mon Sep 17 00:00:00 2001 From: Chris Desjardins Date: Thu, 15 Feb 2024 16:27:49 +0100 Subject: Do not enable the Mode mismatch interrupt source, it is not cleared If this interrupt ever hits it will result in an infinite interrupt loop as it is never cleared. --- src/portable/synopsys/dwc2/dcd_dwc2.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 3e15d51c6..3f00243e5 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -462,9 +462,7 @@ void dcd_init(uint8_t rhport) { dwc2->gotgint |= int_mask; // Required as part of core initialization. - // TODO: How should mode mismatch be handled? It will cause - // the core to stop working/require reset. - dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_MMISM | GINTMSK_RXFLVLM | + dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_RXFLVLM | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; // Enable global interrupt -- cgit v1.3.1 From 27c125416a60986c4bce670097efbd88744fab9b Mon Sep 17 00:00:00 2001 From: Kai <60053077+kaidegit@users.noreply.github.com> Date: Fri, 16 Feb 2024 15:16:17 +0800 Subject: use rt-thread 5+ mq recv api --- src/osal/osal_rtthread.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h index 18eb9c693..d03b53bee 100644 --- a/src/osal/osal_rtthread.h +++ b/src/osal/osal_rtthread.h @@ -2,6 +2,7 @@ * The MIT License (MIT) * * Copyright (c) 2020 tfx2001 (2479727366@qq.com) + * Copyright (c) 2020 yekai (2857693944@qq.com) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -111,9 +112,12 @@ TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_de } TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void *data, uint32_t msec) { - rt_tick_t tick = rt_tick_from_millisecond((rt_int32_t) msec); +#if RT_VERSION_MAJOR >= 5 + return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) > 0; +#else return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) == RT_EOK; +#endif /* RT_VERSION_MAJOR >= 5 */ } TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) { -- cgit v1.3.1 From e9dc8f3e7dc6799ad674139df97e253acc71f4d7 Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Mon, 19 Feb 2024 18:12:03 +0700 Subject: fix wrong volatile usage in ohci gtd --- src/portable/ohci/ohci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h index 4feefd771..94bad5df7 100644 --- a/src/portable/ohci/ohci.h +++ b/src/portable/ohci/ohci.h @@ -83,7 +83,7 @@ typedef struct TU_ATTR_ALIGNED(16) volatile uint32_t condition_code : 4; // Word 1 - volatile uint8_t* current_buffer_pointer; + uint8_t* volatile current_buffer_pointer; // Word 2 : next TD volatile uint32_t next; -- cgit v1.3.1 From 3f2df94457e917dda2fed05c7ee17deefe55199e Mon Sep 17 00:00:00 2001 From: Bob Abeles Date: Tue, 20 Feb 2024 08:16:39 -0800 Subject: video_device: fix uninitialized warning --- src/class/video/video_device.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 1affd615e..c33dfa0b0 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -559,6 +559,7 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const * uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType; if (num_intervals) { interval = 0; + interval_ms = 0; } else { interval = frm->uncompressed.dwFrameInterval[2]; interval_ms = interval / 10000; -- cgit v1.3.1 From 13d26d216613792e814dda4742ef7ab4fb9b0d37 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 22 Feb 2024 19:20:28 +0700 Subject: slightly change cdc_msc_freertos example --- examples/device/cdc_msc_freertos/src/main.c | 51 +++++++++++++++-------------- src/class/video/video.h | 6 +++- 2 files changed, 32 insertions(+), 25 deletions(-) (limited to 'src') diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index 1dadc4513..e94e8eaec 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -52,7 +52,8 @@ #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1) #endif -#define CDC_STACK_SZIE configMINIMAL_STACK_SIZE +#define CDC_STACK_SIZE configMINIMAL_STACK_SIZE +#define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTOTYPES @@ -69,21 +70,22 @@ enum { BLINK_SUSPENDED = 2500, }; -// static timer & task +// static task #if configSUPPORT_STATIC_ALLOCATION -StaticTimer_t blinky_tmdef; +StackType_t blinky_stack[BLINKY_STACK_SIZE]; +StaticTask_t blinky_taskdef; StackType_t usb_device_stack[USBD_STACK_SIZE]; StaticTask_t usb_device_taskdef; -StackType_t cdc_stack[CDC_STACK_SZIE]; +StackType_t cdc_stack[CDC_STACK_SIZE]; StaticTask_t cdc_taskdef; #endif -TimerHandle_t blinky_tm; +static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED; -static void led_blinky_cb(TimerHandle_t xTimer); static void usb_device_task(void *param); +void led_blinking_task(void* param); void cdc_task(void *params); //--------------------------------------------------------------------+ @@ -94,22 +96,20 @@ int main(void) { board_init(); #if configSUPPORT_STATIC_ALLOCATION - // soft timer for blinky - blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef); + // blinky task + xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef); // Create a task for tinyusb device stack xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef); // Create CDC task - xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef); + xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, cdc_stack, &cdc_taskdef); #else - blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb); + xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL); xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL); xTaskCreate(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL); #endif - xTimerStart(blinky_tm, 0); - // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) vTaskStartScheduler(); @@ -154,12 +154,12 @@ static void usb_device_task(void *param) { // Invoked when device is mounted void tud_mount_cb(void) { - xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0); + blink_interval_ms = BLINK_MOUNTED; } // Invoked when device is unmounted void tud_umount_cb(void) { - xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0); + blink_interval_ms = BLINK_NOT_MOUNTED; } // Invoked when usb bus is suspended @@ -167,16 +167,12 @@ void tud_umount_cb(void) { // Within 7ms, device must draw an average of current less than 2.5 mA from bus void tud_suspend_cb(bool remote_wakeup_en) { (void) remote_wakeup_en; - xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_SUSPENDED), 0); + blink_interval_ms = BLINK_SUSPENDED; } // Invoked when usb bus is resumed void tud_resume_cb(void) { - if (tud_mounted()) { - xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0); - } else { - xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0); - } + blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED; } //--------------------------------------------------------------------+ @@ -235,10 +231,17 @@ void tud_cdc_rx_cb(uint8_t itf) { //--------------------------------------------------------------------+ // BLINKING TASK //--------------------------------------------------------------------+ -static void led_blinky_cb(TimerHandle_t xTimer) { - (void) xTimer; +void led_blinking_task(void* param) { + (void) param; + static uint32_t start_ms = 0; static bool led_state = false; - board_led_write(led_state); - led_state = 1 - led_state; // toggle + while (1) { + // Blink every interval ms + vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS); + start_ms += blink_interval_ms; + + board_led_write(led_state); + led_state = 1 - led_state; // toggle + } } diff --git a/src/class/video/video.h b/src/class/video/video.h index 6319c6536..abf1e34b9 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -368,6 +368,8 @@ typedef struct TU_ATTR_PACKED { uint8_t bCopyProtect; } tusb_desc_video_format_uncompressed_t; +TU_VERIFY_STATIC(sizeof(tusb_desc_video_format_uncompressed_t) == 27, "size is not correct"); + // Uncompressed payload specs: 3.1.2 frame descriptor #define tusb_desc_video_frame_uncompressed_nint_t(_nint) \ struct TU_ATTR_PACKED { \ @@ -381,7 +383,7 @@ typedef struct TU_ATTR_PACKED { uint32_t dwMinBitRate; \ uint32_t dwMaxBitRate; \ uint32_t dwMaxVideoFrameBufferSize; /* deprecated in 1.5 */ \ - uint32_t dwDefaultFrameInterval; \ + uint32_t dwDefaultFrameInterval; /* 100ns unit */\ uint8_t bFrameIntervalType; \ uint32_t dwFrameInterval[_nint]; \ } @@ -413,6 +415,8 @@ typedef struct TU_ATTR_PACKED { uint8_t bCopyProtect; } tusb_desc_video_format_mjpeg_t; +TU_VERIFY_STATIC(sizeof(tusb_desc_video_format_mjpeg_t) == 11, "size is not correct"); + // MJPEG payload specs: 3.1.2 frame descriptor (same as uncompressed) typedef tusb_desc_video_frame_uncompressed_t tusb_desc_video_frame_mjpeg_t; typedef tusb_desc_video_frame_uncompressed_1int_t tusb_desc_video_frame_mjpeg_1int_t; -- cgit v1.3.1 From 3d3bf45102ded992fc10be09f3e9b9c981379ad1 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 24 Feb 2024 00:36:07 +0700 Subject: frdm k64f usb work well, add kinetis_k to ci cmake --- .github/workflows/cmake_arm.yml | 2 +- hw/bsp/kinetis_k/boards/frdm_k64f/frdm_k64f.mex | 43 +++++++++++++++++++++++-- hw/bsp/kinetis_k/family.c | 4 ++- hw/bsp/kinetis_k/family.cmake | 1 + hw/bsp/kinetis_k/family.mk | 1 + src/portable/chipidea/ci_fs/ci_fs_kinetis.h | 6 ++-- src/portable/chipidea/ci_fs/dcd_ci_fs.c | 8 +++++ src/portable/nxp/khci/dcd_khci.c | 14 +++----- 8 files changed, 60 insertions(+), 19 deletions(-) (limited to 'src') diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml index f97645ad1..80ab1ea71 100644 --- a/.github/workflows/cmake_arm.yml +++ b/.github/workflows/cmake_arm.yml @@ -38,7 +38,7 @@ jobs: family: # Alphabetical order - 'imxrt' - - 'kinetis_kl' + - 'kinetis_k kinetis_kl' - 'lpc17 lpc18 lpc40 lpc43' - 'lpc54 lpc55' - 'mcx' diff --git a/hw/bsp/kinetis_k/boards/frdm_k64f/frdm_k64f.mex b/hw/bsp/kinetis_k/boards/frdm_k64f/frdm_k64f.mex index 28d1ea612..4a8c77f95 100644 --- a/hw/bsp/kinetis_k/boards/frdm_k64f/frdm_k64f.mex +++ b/hw/bsp/kinetis_k/boards/frdm_k64f/frdm_k64f.mex @@ -732,15 +732,27 @@ - + - true + true + + + + + 2.8.0 + + + + + + + 14.0.0 @@ -755,6 +767,31 @@ true + + + true + + + + + true + + + + + 0 + + + + + true + + + + + true + + @@ -789,7 +826,7 @@ - + diff --git a/hw/bsp/kinetis_k/family.c b/hw/bsp/kinetis_k/family.c index 38cfc45e3..6df29c1fc 100644 --- a/hw/bsp/kinetis_k/family.c +++ b/hw/bsp/kinetis_k/family.c @@ -30,6 +30,7 @@ #include "fsl_port.h" #include "fsl_clock.h" #include "fsl_uart.h" +#include "fsl_sysmpu.h" #include "board/clock_config.h" #include "board/pin_mux.h" @@ -50,6 +51,7 @@ void board_init(void) { BOARD_InitBootPins(); BOARD_BootClockRUN(); SystemCoreClockUpdate(); + SYSMPU_Enable(SYSMPU, 0); #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer @@ -84,7 +86,7 @@ void board_init(void) { #endif // USB - CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk)); + // USB clock is configured in BOARD_BootClockRUN() } //--------------------------------------------------------------------+ diff --git a/hw/bsp/kinetis_k/family.cmake b/hw/bsp/kinetis_k/family.cmake index 6d642c101..e0b5fcfc8 100644 --- a/hw/bsp/kinetis_k/family.cmake +++ b/hw/bsp/kinetis_k/family.cmake @@ -40,6 +40,7 @@ function(add_board_target BOARD_TARGET) ${SDK_DIR}/drivers/gpio ${SDK_DIR}/drivers/port ${SDK_DIR}/drivers/smc + ${SDK_DIR}/drivers/sysmpu ${SDK_DIR}/drivers/uart ) diff --git a/hw/bsp/kinetis_k/family.mk b/hw/bsp/kinetis_k/family.mk index de352a6a9..995873eec 100644 --- a/hw/bsp/kinetis_k/family.mk +++ b/hw/bsp/kinetis_k/family.mk @@ -29,6 +29,7 @@ INC += \ $(TOP)/$(SDK_DIR)/drivers/gpio \ $(TOP)/$(SDK_DIR)/drivers/port \ $(TOP)/$(SDK_DIR)/drivers/smc \ + $(TOP)/$(SDK_DIR)/drivers/sysmpu \ $(TOP)/$(SDK_DIR)/drivers/uart \ SRC_S += ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S diff --git a/src/portable/chipidea/ci_fs/ci_fs_kinetis.h b/src/portable/chipidea/ci_fs/ci_fs_kinetis.h index cd21af1c7..31e14a546 100644 --- a/src/portable/chipidea/ci_fs/ci_fs_kinetis.h +++ b/src/portable/chipidea/ci_fs/ci_fs_kinetis.h @@ -36,14 +36,12 @@ #define CI_FS_REG(_port) ((ci_fs_regs_t*) USB0_BASE) #define CI_REG CI_FS_REG(0) -void dcd_int_enable(uint8_t rhport) -{ +void dcd_int_enable(uint8_t rhport) { (void) rhport; NVIC_EnableIRQ(USB0_IRQn); } -void dcd_int_disable(uint8_t rhport) -{ +void dcd_int_disable(uint8_t rhport) { (void) rhport; NVIC_DisableIRQ(USB0_IRQn); } diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c index 9327e09d8..4b1d488b5 100644 --- a/src/portable/chipidea/ci_fs/dcd_ci_fs.c +++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c @@ -271,9 +271,17 @@ void dcd_init(uint8_t rhport) { (void) rhport; + // save crystal-less setting (recovery clock) + uint32_t clk_recover_irc_en = CI_REG->CLK_RECOVER_IRC_EN; + uint32_t clk_recover_ctrl = CI_REG->CLK_RECOVER_CTRL;; + CI_REG->USBTRC0 |= USB_USBTRC0_USBRESET_MASK; while (CI_REG->USBTRC0 & USB_USBTRC0_USBRESET_MASK); + // restore crystal-less setting + CI_REG->CLK_RECOVER_IRC_EN = clk_recover_irc_en; + CI_REG->CLK_RECOVER_CTRL |= clk_recover_ctrl; + tu_memclr(&_dcd, sizeof(_dcd)); CI_REG->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */ CI_REG->BDT_PAGE1 = (uint8_t)((uintptr_t)_dcd.bdt >> 8); diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 5a2f768b3..5d04a524a 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -269,22 +269,16 @@ void dcd_init(uint8_t rhport) { (void) rhport; -#if (CFG_TUSB_MCU == OPT_MCU_KINETIS_K) - uint32_t clk_recover_irc_en; - uint32_t clk_recover_ctrl; - - clk_recover_irc_en = KHCI->CLK_RECOVER_IRC_EN; - clk_recover_ctrl = KHCI->CLK_RECOVER_CTRL; + // save crystal-less setting (recovery clock) + uint32_t clk_recover_irc_en = KHCI->CLK_RECOVER_IRC_EN; + uint32_t clk_recover_ctrl = KHCI->CLK_RECOVER_CTRL; KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK; while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK); + // restore crystal-less setting KHCI->CLK_RECOVER_IRC_EN = clk_recover_irc_en; KHCI->CLK_RECOVER_CTRL |= clk_recover_ctrl; -#else - KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK; - while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK); -#endif tu_memclr(&_dcd, sizeof(_dcd)); KHCI->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */ -- cgit v1.3.1 From 65a2e5cdf8d708b88bb8edf7b718f698e5a18ffc Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 24 Feb 2024 00:53:05 +0700 Subject: fix build with cpu without USB_CLK_RECOVER using old dcd_khci driver --- .idea/cmake.xml | 2 +- src/portable/nxp/khci/dcd_khci.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index dbb34aaab..ebc6a0570 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -59,7 +59,7 @@ - + diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 5d04a524a..3419c2565 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -270,15 +270,19 @@ void dcd_init(uint8_t rhport) (void) rhport; // save crystal-less setting (recovery clock) + #ifdef USB_CLK_RECOVER_IRC_EN_IRC_EN uint32_t clk_recover_irc_en = KHCI->CLK_RECOVER_IRC_EN; uint32_t clk_recover_ctrl = KHCI->CLK_RECOVER_CTRL; + #endif KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK; while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK); // restore crystal-less setting + #ifdef USB_CLK_RECOVER_IRC_EN_IRC_EN KHCI->CLK_RECOVER_IRC_EN = clk_recover_irc_en; KHCI->CLK_RECOVER_CTRL |= clk_recover_ctrl; + #endif tu_memclr(&_dcd, sizeof(_dcd)); KHCI->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */ -- cgit v1.3.1 From a52b4647ec20414bbfde986c13a18598ffd426d6 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 24 Feb 2024 17:18:30 +0700 Subject: only save/restore CLK_RECOVER_IRC_EN/CTRL if FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED is defined to 1 --- src/portable/chipidea/ci_fs/dcd_ci_fs.c | 10 +++++++--- src/portable/nxp/khci/dcd_khci.c | 8 ++++---- 2 files changed, 11 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c index 4b1d488b5..a68ecf8c9 100644 --- a/src/portable/chipidea/ci_fs/dcd_ci_fs.c +++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c @@ -271,16 +271,20 @@ void dcd_init(uint8_t rhport) { (void) rhport; - // save crystal-less setting (recovery clock) + // save crystal-less setting (if available) + #if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1 uint32_t clk_recover_irc_en = CI_REG->CLK_RECOVER_IRC_EN; - uint32_t clk_recover_ctrl = CI_REG->CLK_RECOVER_CTRL;; + uint32_t clk_recover_ctrl = CI_REG->CLK_RECOVER_CTRL; + #endif CI_REG->USBTRC0 |= USB_USBTRC0_USBRESET_MASK; while (CI_REG->USBTRC0 & USB_USBTRC0_USBRESET_MASK); - // restore crystal-less setting + // restore crystal-less setting (if available) + #if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1 CI_REG->CLK_RECOVER_IRC_EN = clk_recover_irc_en; CI_REG->CLK_RECOVER_CTRL |= clk_recover_ctrl; + #endif tu_memclr(&_dcd, sizeof(_dcd)); CI_REG->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */ diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 3419c2565..dc71117b3 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -269,8 +269,8 @@ void dcd_init(uint8_t rhport) { (void) rhport; - // save crystal-less setting (recovery clock) - #ifdef USB_CLK_RECOVER_IRC_EN_IRC_EN + // save crystal-less setting (if available) + #if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1 uint32_t clk_recover_irc_en = KHCI->CLK_RECOVER_IRC_EN; uint32_t clk_recover_ctrl = KHCI->CLK_RECOVER_CTRL; #endif @@ -278,8 +278,8 @@ void dcd_init(uint8_t rhport) KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK; while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK); - // restore crystal-less setting - #ifdef USB_CLK_RECOVER_IRC_EN_IRC_EN + // restore crystal-less setting (if available) + #if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1 KHCI->CLK_RECOVER_IRC_EN = clk_recover_irc_en; KHCI->CLK_RECOVER_CTRL |= clk_recover_ctrl; #endif -- cgit v1.3.1 From 23450d4f6bba4b5b92e242a61684dfcf171e6cbe Mon Sep 17 00:00:00 2001 From: IngHK Date: Sat, 24 Feb 2024 15:51:02 +0100 Subject: fixed compiler warning src/tusb.c --- src/tusb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/tusb.c b/src/tusb.c index 7943ea5ef..3ef380c83 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -477,7 +477,7 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent) uint8_t const *buf8 = (uint8_t const *) buf; char format[] = "%00X"; - format[2] += 2*size; + format[2] += (uint8_t) (2*size); // 1 byte = 2 hex digits const uint8_t item_per_line = 16 / size; -- cgit v1.3.1 From 473d400cfde768e26fe8644bab3d655c81777b64 Mon Sep 17 00:00:00 2001 From: Taylor Yu Date: Sun, 25 Feb 2024 11:12:24 -0600 Subject: work around possible RP2040 erratum RP2040 device controller does not seem to clear pending transactions configured in EP0 buffer controls when the host aborts a control transfer. This causes assertion failures, including when a buffer AVAILABLE flag set for a previous transfer causes an unexpected transaction completion. --- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index e8cee73fd..51174f709 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -217,6 +217,18 @@ static void __tusb_irq_path_func(hw_handle_buff_status)(void) TU_ATTR_ALWAYS_INLINE static inline void reset_ep0_pid(void) { + // Abort any transactions from a prior control transfer, because + // receiving SETUP doesn't reset buffer control state. This works around + // a possible USB hardware erratum. + + // With this workaround a race window still exists, but smaller. + // ABORT flag is unusable prior to hardware B2 (RP2040-E2), so a larger + // race window exists for B1 and earlier. + if (rp2040_chip_version() >= 2) { + usb_hw_set->abort = 0x3; + while ((usb_hw->abort_done & 0x3) != 0x3) + ; + } // If we have finished this transfer on EP0 set pid back to 1 for next // setup transfer. Also clear a stall in case uint8_t addrs[] = {0x0, 0x80}; @@ -224,6 +236,25 @@ TU_ATTR_ALWAYS_INLINE static inline void reset_ep0_pid(void) { struct hw_endpoint *ep = hw_endpoint_get_by_addr(addrs[i]); ep->next_pid = 1u; + // Reset the buffer control now to minimize race conditions + _hw_endpoint_buffer_control_set_value32(ep, USB_BUF_CTRL_DATA1_PID | USB_BUF_CTRL_SEL); + // Explicit delay, because the one in + // _hw_endpoint_buffer_control_set_value32 is only to set AVAILABLE + __asm volatile ( + "b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1:\n" + : : : "memory"); + // Make sure local ep state matches peripheral + hw_endpoint_reset_transfer(ep); + } + if (rp2040_chip_version() >= 2) { + usb_hw_clear->abort = 0x3; + usb_hw_clear->abort_done = 0x3; } } -- cgit v1.3.1 From 4ed02ae5f97b57bd442521234b81a381c507d3a1 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 1 Mar 2024 17:34:14 +0700 Subject: reformat code hid_host.c - fix ceedling with ruby 3.1 - allow overwrite CMAKE_C_COMPILER/CMAKE_CXX_COMPILER from command line --- .../build_system/cmake/toolchain/arm_gcc.cmake | 12 +- src/class/hid/hid_host.c | 519 +++++++++------------ test/unit-test/project.yml | 13 +- 3 files changed, 231 insertions(+), 313 deletions(-) (limited to 'src') diff --git a/examples/build_system/cmake/toolchain/arm_gcc.cmake b/examples/build_system/cmake/toolchain/arm_gcc.cmake index 7680d75ab..d3fd5b557 100644 --- a/examples/build_system/cmake/toolchain/arm_gcc.cmake +++ b/examples/build_system/cmake/toolchain/arm_gcc.cmake @@ -1,8 +1,14 @@ set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_C_COMPILER "arm-none-eabi-gcc") -set(CMAKE_CXX_COMPILER "arm-none-eabi-g++") -set(CMAKE_ASM_COMPILER "arm-none-eabi-gcc") +if (NOT DEFINED CMAKE_C_COMPILER) + set(CMAKE_C_COMPILER "arm-none-eabi-gcc") +endif () + +if (NOT DEFINED CMAKE_CXX_COMPILER) + set(CMAKE_CXX_COMPILER "arm-none-eabi-g++") +endif () + +set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) set(CMAKE_SIZE "arm-none-eabi-size" CACHE FILEPATH "") set(CMAKE_OBJCOPY "arm-none-eabi-objcopy" CACHE FILEPATH "") diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 709fa3dd8..21aee531a 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -39,12 +39,11 @@ #endif #define TU_LOG_DRV(...) TU_LOG(CFG_TUH_HID_LOG_LEVEL, __VA_ARGS__) + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ - -typedef struct -{ +typedef struct { uint8_t daddr; uint8_t itf_num; @@ -55,7 +54,7 @@ typedef struct uint8_t itf_protocol; // None, Keyboard, Mouse uint8_t protocol_mode; // Boot (0) or Report protocol (1) - uint8_t report_desc_type; + uint8_t report_desc_type; uint16_t report_desc_len; uint16_t epin_size; @@ -73,79 +72,57 @@ tu_static uint8_t _hidh_default_protocol = HID_PROTOCOL_BOOT; //--------------------------------------------------------------------+ // Helper //--------------------------------------------------------------------+ - -TU_ATTR_ALWAYS_INLINE static inline -hidh_interface_t* get_hid_itf(uint8_t daddr, uint8_t idx) -{ +TU_ATTR_ALWAYS_INLINE static inline hidh_interface_t* get_hid_itf(uint8_t daddr, uint8_t idx) { TU_ASSERT(daddr > 0 && idx < CFG_TUH_HID, NULL); hidh_interface_t* p_hid = &_hidh_itf[idx]; return (p_hid->daddr == daddr) ? p_hid : NULL; } // Get instance ID by endpoint address -static uint8_t get_idx_by_epaddr(uint8_t daddr, uint8_t ep_addr) -{ - for ( uint8_t idx = 0; idx < CFG_TUH_HID; idx++ ) - { - hidh_interface_t const * p_hid = &_hidh_itf[idx]; - - if ( p_hid->daddr == daddr && - (p_hid->ep_in == ep_addr || p_hid->ep_out == ep_addr) ) - { +static uint8_t get_idx_by_epaddr(uint8_t daddr, uint8_t ep_addr) { + for (uint8_t idx = 0; idx < CFG_TUH_HID; idx++) { + hidh_interface_t const* p_hid = &_hidh_itf[idx]; + if (p_hid->daddr == daddr && + (p_hid->ep_in == ep_addr || p_hid->ep_out == ep_addr)) { return idx; } } - return TUSB_INDEX_INVALID_8; } -static hidh_interface_t* find_new_itf(void) -{ - for(uint8_t i=0; imounted; } -bool tuh_hid_itf_get_info(uint8_t daddr, uint8_t idx, tuh_itf_info_t* info) -{ +bool tuh_hid_itf_get_info(uint8_t daddr, uint8_t idx, tuh_itf_info_t* info) { hidh_interface_t* p_hid = get_hid_itf(daddr, idx); TU_VERIFY(p_hid && info); @@ -153,34 +130,30 @@ bool tuh_hid_itf_get_info(uint8_t daddr, uint8_t idx, tuh_itf_info_t* info) // re-construct descriptor tusb_desc_interface_t* desc = &info->desc; - desc->bLength = sizeof(tusb_desc_interface_t); - desc->bDescriptorType = TUSB_DESC_INTERFACE; + desc->bLength = sizeof(tusb_desc_interface_t); + desc->bDescriptorType = TUSB_DESC_INTERFACE; - desc->bInterfaceNumber = p_hid->itf_num; - desc->bAlternateSetting = 0; - desc->bNumEndpoints = (uint8_t) ((p_hid->ep_in ? 1u : 0u) + (p_hid->ep_out ? 1u : 0u)); - desc->bInterfaceClass = TUSB_CLASS_HID; + desc->bInterfaceNumber = p_hid->itf_num; + desc->bAlternateSetting = 0; + desc->bNumEndpoints = (uint8_t) ((p_hid->ep_in ? 1u : 0u) + (p_hid->ep_out ? 1u : 0u)); + desc->bInterfaceClass = TUSB_CLASS_HID; desc->bInterfaceSubClass = (p_hid->itf_protocol ? HID_SUBCLASS_BOOT : HID_SUBCLASS_NONE); desc->bInterfaceProtocol = p_hid->itf_protocol; - desc->iInterface = 0; // not used yet + desc->iInterface = 0; // not used yet return true; } -uint8_t tuh_hid_itf_get_index(uint8_t daddr, uint8_t itf_num) -{ - for ( uint8_t idx = 0; idx < CFG_TUH_HID; idx++ ) - { - hidh_interface_t const * p_hid = &_hidh_itf[idx]; - - if ( p_hid->daddr == daddr && p_hid->itf_num == itf_num) return idx; +uint8_t tuh_hid_itf_get_index(uint8_t daddr, uint8_t itf_num) { + for (uint8_t idx = 0; idx < CFG_TUH_HID; idx++) { + hidh_interface_t const* p_hid = &_hidh_itf[idx]; + if (p_hid->daddr == daddr && p_hid->itf_num == itf_num) return idx; } return TUSB_INDEX_INVALID_8; } -uint8_t tuh_hid_interface_protocol(uint8_t daddr, uint8_t idx) -{ +uint8_t tuh_hid_interface_protocol(uint8_t daddr, uint8_t idx) { hidh_interface_t* p_hid = get_hid_itf(daddr, idx); return p_hid ? p_hid->itf_protocol : 0; } @@ -188,29 +161,24 @@ uint8_t tuh_hid_interface_protocol(uint8_t daddr, uint8_t idx) //--------------------------------------------------------------------+ // Control Endpoint API //--------------------------------------------------------------------+ - -uint8_t tuh_hid_get_protocol(uint8_t daddr, uint8_t idx) -{ +uint8_t tuh_hid_get_protocol(uint8_t daddr, uint8_t idx) { hidh_interface_t* p_hid = get_hid_itf(daddr, idx); return p_hid ? p_hid->protocol_mode : 0; } -static void set_protocol_complete(tuh_xfer_t* xfer) -{ +static void set_protocol_complete(tuh_xfer_t* xfer) { uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t const daddr = xfer->daddr; - uint8_t const idx = tuh_hid_itf_get_index(daddr, itf_num); + uint8_t const daddr = xfer->daddr; + uint8_t const idx = tuh_hid_itf_get_index(daddr, itf_num); hidh_interface_t* p_hid = get_hid_itf(daddr, idx); - TU_VERIFY(p_hid, ); + TU_VERIFY(p_hid,); - if (XFER_RESULT_SUCCESS == xfer->result) - { + if (XFER_RESULT_SUCCESS == xfer->result) { p_hid->protocol_mode = (uint8_t) tu_le16toh(xfer->setup->wValue); } - if (tuh_hid_set_protocol_complete_cb) - { + if (tuh_hid_set_protocol_complete_cb) { tuh_hid_set_protocol_complete_cb(daddr, idx, p_hid->protocol_mode); } } @@ -219,123 +187,109 @@ void tuh_hid_set_default_protocol(uint8_t protocol) { _hidh_default_protocol = protocol; } -static bool _hidh_set_protocol(uint8_t daddr, uint8_t itf_num, uint8_t protocol, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +static bool _hidh_set_protocol(uint8_t daddr, uint8_t itf_num, uint8_t protocol, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_DRV("HID Set Protocol = %d\r\n", protocol); - tusb_control_request_t const request = - { - .bmRequestType_bit = - { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_CLASS, - .direction = TUSB_DIR_OUT - }, - .bRequest = HID_REQ_CONTROL_SET_PROTOCOL, - .wValue = protocol, - .wIndex = itf_num, - .wLength = 0 + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_CLASS, + .direction = TUSB_DIR_OUT + }, + .bRequest = HID_REQ_CONTROL_SET_PROTOCOL, + .wValue = protocol, + .wIndex = itf_num, + .wLength = 0 }; - tuh_xfer_t xfer = - { - .daddr = daddr, - .ep_addr = 0, - .setup = &request, - .buffer = NULL, - .complete_cb = complete_cb, - .user_data = user_data + tuh_xfer_t xfer = { + .daddr = daddr, + .ep_addr = 0, + .setup = &request, + .buffer = NULL, + .complete_cb = complete_cb, + .user_data = user_data }; return tuh_control_xfer(&xfer); } -bool tuh_hid_set_protocol(uint8_t daddr, uint8_t idx, uint8_t protocol) -{ +bool tuh_hid_set_protocol(uint8_t daddr, uint8_t idx, uint8_t protocol) { hidh_interface_t* p_hid = get_hid_itf(daddr, idx); TU_VERIFY(p_hid && p_hid->itf_protocol != HID_ITF_PROTOCOL_NONE); return _hidh_set_protocol(daddr, p_hid->itf_num, protocol, set_protocol_complete, 0); } -static void set_report_complete(tuh_xfer_t* xfer) -{ +static void set_report_complete(tuh_xfer_t* xfer) { TU_LOG_DRV("HID Set Report complete\r\n"); - if (tuh_hid_set_report_complete_cb) - { + if (tuh_hid_set_report_complete_cb) { uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t const idx = tuh_hid_itf_get_index(xfer->daddr, itf_num); + uint8_t const idx = tuh_hid_itf_get_index(xfer->daddr, itf_num); uint8_t const report_type = tu_u16_high(xfer->setup->wValue); - uint8_t const report_id = tu_u16_low(xfer->setup->wValue); + uint8_t const report_id = tu_u16_low(xfer->setup->wValue); tuh_hid_set_report_complete_cb(xfer->daddr, idx, report_id, report_type, (xfer->result == XFER_RESULT_SUCCESS) ? xfer->setup->wLength : 0); } } -bool tuh_hid_set_report(uint8_t daddr, uint8_t idx, uint8_t report_id, uint8_t report_type, void* report, uint16_t len) -{ +bool tuh_hid_set_report(uint8_t daddr, uint8_t idx, uint8_t report_id, uint8_t report_type, void* report, uint16_t len) { hidh_interface_t* p_hid = get_hid_itf(daddr, idx); TU_VERIFY(p_hid); - TU_LOG_DRV("HID Set Report: id = %u, type = %u, len = %u\r\n", report_id, report_type, len); - tusb_control_request_t const request = - { - .bmRequestType_bit = - { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_CLASS, - .direction = TUSB_DIR_OUT - }, - .bRequest = HID_REQ_CONTROL_SET_REPORT, - .wValue = tu_htole16(tu_u16(report_type, report_id)), - .wIndex = tu_htole16((uint16_t)p_hid->itf_num), - .wLength = len + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_CLASS, + .direction = TUSB_DIR_OUT + }, + .bRequest = HID_REQ_CONTROL_SET_REPORT, + .wValue = tu_htole16(tu_u16(report_type, report_id)), + .wIndex = tu_htole16((uint16_t) p_hid->itf_num), + .wLength = len }; - tuh_xfer_t xfer = - { - .daddr = daddr, - .ep_addr = 0, - .setup = &request, - .buffer = report, - .complete_cb = set_report_complete, - .user_data = 0 + tuh_xfer_t xfer = { + .daddr = daddr, + .ep_addr = 0, + .setup = &request, + .buffer = report, + .complete_cb = set_report_complete, + .user_data = 0 }; return tuh_control_xfer(&xfer); } -static bool _hidh_set_idle(uint8_t daddr, uint8_t itf_num, uint16_t idle_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +static bool _hidh_set_idle(uint8_t daddr, uint8_t itf_num, uint16_t idle_rate, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // SET IDLE request, device can stall if not support this request TU_LOG_DRV("HID Set Idle \r\n"); - tusb_control_request_t const request = - { - .bmRequestType_bit = - { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_CLASS, - .direction = TUSB_DIR_OUT - }, - .bRequest = HID_REQ_CONTROL_SET_IDLE, - .wValue = tu_htole16(idle_rate), - .wIndex = tu_htole16((uint16_t)itf_num), - .wLength = 0 + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_CLASS, + .direction = TUSB_DIR_OUT + }, + .bRequest = HID_REQ_CONTROL_SET_IDLE, + .wValue = tu_htole16(idle_rate), + .wIndex = tu_htole16((uint16_t) itf_num), + .wLength = 0 }; - tuh_xfer_t xfer = - { - .daddr = daddr, - .ep_addr = 0, - .setup = &request, - .buffer = NULL, - .complete_cb = complete_cb, - .user_data = user_data + tuh_xfer_t xfer = { + .daddr = daddr, + .ep_addr = 0, + .setup = &request, + .buffer = NULL, + .complete_cb = complete_cb, + .user_data = user_data }; return tuh_control_xfer(&xfer); @@ -346,24 +300,20 @@ static bool _hidh_set_idle(uint8_t daddr, uint8_t itf_num, uint16_t idle_rate, t //--------------------------------------------------------------------+ // Check if HID interface is ready to receive report -bool tuh_hid_receive_ready(uint8_t dev_addr, uint8_t idx) -{ +bool tuh_hid_receive_ready(uint8_t dev_addr, uint8_t idx) { hidh_interface_t* p_hid = get_hid_itf(dev_addr, idx); TU_VERIFY(p_hid); - return !usbh_edpt_busy(dev_addr, p_hid->ep_in); } -bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx) -{ +bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx) { hidh_interface_t* p_hid = get_hid_itf(daddr, idx); TU_VERIFY(p_hid); // claim endpoint - TU_VERIFY( usbh_edpt_claim(daddr, p_hid->ep_in) ); + TU_VERIFY(usbh_edpt_claim(daddr, p_hid->ep_in)); - if ( !usbh_edpt_xfer(daddr, p_hid->ep_in, p_hid->epin_buf, p_hid->epin_size) ) - { + if (!usbh_edpt_xfer(daddr, p_hid->ep_in, p_hid->epin_buf, p_hid->epin_size)) { usbh_edpt_release(daddr, p_hid->ep_in); return false; } @@ -371,43 +321,34 @@ bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx) return true; } -bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx) -{ +bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx) { hidh_interface_t* p_hid = get_hid_itf(dev_addr, idx); TU_VERIFY(p_hid); - return !usbh_edpt_busy(dev_addr, p_hid->ep_out); } -bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len) -{ +bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len) { TU_LOG_DRV("HID Send Report %d\r\n", report_id); hidh_interface_t* p_hid = get_hid_itf(daddr, idx); TU_VERIFY(p_hid); - if (p_hid->ep_out == 0) - { + if (p_hid->ep_out == 0) { // This HID does not have an out endpoint (other than control) return false; - } - else if (len > CFG_TUH_HID_EPOUT_BUFSIZE || - (report_id != 0 && len > (CFG_TUH_HID_EPOUT_BUFSIZE - 1))) - { + } else if (len > CFG_TUH_HID_EPOUT_BUFSIZE || + (report_id != 0 && len > (CFG_TUH_HID_EPOUT_BUFSIZE - 1))) { // ep_out buffer is not large enough to hold contents return false; } // claim endpoint - TU_VERIFY( usbh_edpt_claim(daddr, p_hid->ep_out) ); + TU_VERIFY(usbh_edpt_claim(daddr, p_hid->ep_out)); - if (report_id == 0) - { + if (report_id == 0) { // No report ID in transmission memcpy(&p_hid->epout_buf[0], report, len); - } - else - { + } else { p_hid->epout_buf[0] = report_id; memcpy(&p_hid->epout_buf[1], report, len); ++len; // 1 more byte for report_id @@ -415,8 +356,7 @@ bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const vo TU_LOG3_MEM(p_hid->epout_buf, len, 2); - if ( !usbh_edpt_xfer(daddr, p_hid->ep_out, p_hid->epout_buf, len) ) - { + if (!usbh_edpt_xfer(daddr, p_hid->ep_out, p_hid->epout_buf, len)) { usbh_edpt_release(daddr, p_hid->ep_out); return false; } @@ -427,13 +367,11 @@ bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const vo //--------------------------------------------------------------------+ // USBH API //--------------------------------------------------------------------+ -void hidh_init(void) -{ +void hidh_init(void) { tu_memclr(_hidh_itf, sizeof(_hidh_itf)); } -bool hidh_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) -{ +bool hidh_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { (void) result; uint8_t const dir = tu_edpt_dir(ep_addr); @@ -442,28 +380,25 @@ bool hidh_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t hidh_interface_t* p_hid = get_hid_itf(daddr, idx); TU_VERIFY(p_hid); - if ( dir == TUSB_DIR_IN ) - { + if (dir == TUSB_DIR_IN) { TU_LOG_DRV(" Get Report callback (%u, %u)\r\n", daddr, idx); TU_LOG3_MEM(p_hid->epin_buf, xferred_bytes, 2); tuh_hid_report_received_cb(daddr, idx, p_hid->epin_buf, (uint16_t) xferred_bytes); - }else - { - if (tuh_hid_report_sent_cb) tuh_hid_report_sent_cb(daddr, idx, p_hid->epout_buf, (uint16_t) xferred_bytes); + } else { + if (tuh_hid_report_sent_cb) { + tuh_hid_report_sent_cb(daddr, idx, p_hid->epout_buf, (uint16_t) xferred_bytes); + } } return true; } -void hidh_close(uint8_t daddr) -{ - for(uint8_t i=0; idaddr == daddr) - { + if (p_hid->daddr == daddr) { TU_LOG_DRV(" HIDh close addr = %u index = %u\r\n", daddr, i); - if(tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i); + if (tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i); p_hid->daddr = 0; p_hid->mounted = false; } @@ -474,25 +409,22 @@ void hidh_close(uint8_t daddr) // Enumeration //--------------------------------------------------------------------+ -bool hidh_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len) -{ +bool hidh_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const* desc_itf, uint16_t max_len) { (void) rhport; (void) max_len; TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass); - TU_LOG_DRV("[%u] HID opening Interface %u\r\n", daddr, desc_itf->bInterfaceNumber); // len = interface + hid + n*endpoints uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t)); TU_ASSERT(max_len >= drv_len); - - uint8_t const *p_desc = (uint8_t const *) desc_itf; + uint8_t const* p_desc = (uint8_t const*) desc_itf; //------------- HID descriptor -------------// p_desc = tu_desc_next(p_desc); - tusb_hid_descriptor_hid_t const *desc_hid = (tusb_hid_descriptor_hid_t const *) p_desc; + tusb_hid_descriptor_hid_t const* desc_hid = (tusb_hid_descriptor_hid_t const*) p_desc; TU_ASSERT(HID_DESC_TYPE_HID == desc_hid->bDescriptorType); hidh_interface_t* p_hid = find_new_itf(); @@ -501,38 +433,33 @@ bool hidh_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *desc_ //------------- Endpoint Descriptors -------------// p_desc = tu_desc_next(p_desc); - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc; + tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) p_desc; - for(int i = 0; i < desc_itf->bNumEndpoints; i++) - { + for (int i = 0; i < desc_itf->bNumEndpoints; i++) { TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType); - TU_ASSERT( tuh_edpt_open(daddr, desc_ep) ); + TU_ASSERT(tuh_edpt_open(daddr, desc_ep)); - if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) - { - p_hid->ep_in = desc_ep->bEndpointAddress; + if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { + p_hid->ep_in = desc_ep->bEndpointAddress; p_hid->epin_size = tu_edpt_packet_size(desc_ep); - } - else - { - p_hid->ep_out = desc_ep->bEndpointAddress; + } else { + p_hid->ep_out = desc_ep->bEndpointAddress; p_hid->epout_size = tu_edpt_packet_size(desc_ep); } p_desc = tu_desc_next(p_desc); - desc_ep = (tusb_desc_endpoint_t const *) p_desc; + desc_ep = (tusb_desc_endpoint_t const*) p_desc; } - p_hid->itf_num = desc_itf->bInterfaceNumber; + p_hid->itf_num = desc_itf->bInterfaceNumber; // Assume bNumDescriptors = 1 p_hid->report_desc_type = desc_hid->bReportType; - p_hid->report_desc_len = tu_unaligned_read16(&desc_hid->wReportLength); + p_hid->report_desc_len = tu_unaligned_read16(&desc_hid->wReportLength); // Per HID Specs: default is Report protocol, though we will force Boot protocol when set_config p_hid->protocol_mode = _hidh_default_protocol; - if ( HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass ) - { + if (HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass) { p_hid->itf_protocol = desc_itf->bInterfaceProtocol; } @@ -553,15 +480,14 @@ enum { static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t const* desc_report, uint16_t desc_len); static void process_set_config(tuh_xfer_t* xfer); -bool hidh_set_config(uint8_t daddr, uint8_t itf_num) -{ +bool hidh_set_config(uint8_t daddr, uint8_t itf_num) { tusb_control_request_t request; request.wIndex = tu_htole16((uint16_t) itf_num); tuh_xfer_t xfer; - xfer.daddr = daddr; - xfer.result = XFER_RESULT_SUCCESS; - xfer.setup = &request; + xfer.daddr = daddr; + xfer.result = XFER_RESULT_SUCCESS; + xfer.setup = &request; xfer.user_data = CONFG_SET_IDLE; // fake request to kick-off the set config process @@ -570,71 +496,67 @@ bool hidh_set_config(uint8_t daddr, uint8_t itf_num) return true; } -static void process_set_config(tuh_xfer_t* xfer) -{ +static void process_set_config(tuh_xfer_t* xfer) { // Stall is a valid response for SET_IDLE, sometime SET_PROTOCOL as well // therefore we could ignore its result - if ( !(xfer->setup->bRequest == HID_REQ_CONTROL_SET_IDLE || - xfer->setup->bRequest == HID_REQ_CONTROL_SET_PROTOCOL) ) - { - TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, ); + if (!(xfer->setup->bRequest == HID_REQ_CONTROL_SET_IDLE || + xfer->setup->bRequest == HID_REQ_CONTROL_SET_PROTOCOL)) { + TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS,); } uintptr_t const state = xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t const daddr = xfer->daddr; + uint8_t const daddr = xfer->daddr; - uint8_t const idx = tuh_hid_itf_get_index(daddr, itf_num); + uint8_t const idx = tuh_hid_itf_get_index(daddr, itf_num); hidh_interface_t* p_hid = get_hid_itf(daddr, idx); - TU_VERIFY(p_hid, ); + TU_VERIFY(p_hid,); - switch(state) - { - case CONFG_SET_IDLE: - { + switch (state) { + case CONFG_SET_IDLE: { // Idle rate = 0 mean only report when there is changes const uint16_t idle_rate = 0; - const uintptr_t next_state = (p_hid->itf_protocol != HID_ITF_PROTOCOL_NONE) ? CONFIG_SET_PROTOCOL : CONFIG_GET_REPORT_DESC; + const uintptr_t next_state = (p_hid->itf_protocol != HID_ITF_PROTOCOL_NONE) + ? CONFIG_SET_PROTOCOL : CONFIG_GET_REPORT_DESC; _hidh_set_idle(daddr, itf_num, idle_rate, process_set_config, next_state); + break; } - break; case CONFIG_SET_PROTOCOL: _hidh_set_protocol(daddr, p_hid->itf_num, _hidh_default_protocol, process_set_config, CONFIG_GET_REPORT_DESC); - break; + break; case CONFIG_GET_REPORT_DESC: // Get Report Descriptor if possible // using usbh enumeration buffer since report descriptor can be very long - if( p_hid->report_desc_len > CFG_TUH_ENUMERATION_BUFSIZE ) - { + if (p_hid->report_desc_len > CFG_TUH_ENUMERATION_BUFSIZE) { TU_LOG_DRV("HID Skip Report Descriptor since it is too large %u bytes\r\n", p_hid->report_desc_len); // Driver is mounted without report descriptor config_driver_mount_complete(daddr, idx, NULL, 0); - }else - { - tuh_descriptor_get_hid_report(daddr, itf_num, p_hid->report_desc_type, 0, usbh_get_enum_buf(), p_hid->report_desc_len, process_set_config, CONFIG_COMPLETE); + } else { + tuh_descriptor_get_hid_report(daddr, itf_num, p_hid->report_desc_type, 0, + usbh_get_enum_buf(), p_hid->report_desc_len, + process_set_config, CONFIG_COMPLETE); } break; - case CONFIG_COMPLETE: - { + case CONFIG_COMPLETE: { uint8_t const* desc_report = usbh_get_enum_buf(); - uint16_t const desc_len = tu_le16toh(xfer->setup->wLength); + uint16_t const desc_len = tu_le16toh(xfer->setup->wLength); config_driver_mount_complete(daddr, idx, desc_report, desc_len); + break; } - break; - default: break; + default: + break; } } -static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t const* desc_report, uint16_t desc_len) -{ +static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t const* desc_report, uint16_t desc_len) { hidh_interface_t* p_hid = get_hid_itf(daddr, idx); - TU_VERIFY(p_hid, ); + TU_VERIFY(p_hid,); p_hid->mounted = true; // enumeration is complete @@ -648,21 +570,19 @@ static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t con // Report Descriptor Parser //--------------------------------------------------------------------+ -uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr, uint8_t arr_count, uint8_t const* desc_report, uint16_t desc_len) -{ +uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr, uint8_t arr_count, + uint8_t const* desc_report, uint16_t desc_len) { // Report Item 6.2.2.2 USB HID 1.11 - union TU_ATTR_PACKED - { + union TU_ATTR_PACKED { uint8_t byte; - struct TU_ATTR_PACKED - { - uint8_t size : 2; - uint8_t type : 2; - uint8_t tag : 4; + struct TU_ATTR_PACKED { + uint8_t size : 2; + uint8_t type : 2; + uint8_t tag : 4; }; } header; - tu_memclr(report_info_arr, arr_count*sizeof(tuh_hid_report_info_t)); + tu_memclr(report_info_arr, arr_count * sizeof(tuh_hid_report_info_t)); uint8_t report_num = 0; tuh_hid_report_info_t* info = report_info_arr; @@ -672,114 +592,105 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr, // uint8_t ri_report_size = 0; uint8_t ri_collection_depth = 0; - - while(desc_len && report_num < arr_count) - { + while (desc_len && report_num < arr_count) { header.byte = *desc_report++; desc_len--; - uint8_t const tag = header.tag; + uint8_t const tag = header.tag; uint8_t const type = header.type; uint8_t const size = header.size; uint8_t const data8 = desc_report[0]; TU_LOG(3, "tag = %d, type = %d, size = %d, data = ", tag, type, size); - for(uint32_t i=0; iusage_page, desc_report, size); - break; + if (ri_collection_depth == 0) memcpy(&info->usage_page, desc_report, size); + break; - case RI_GLOBAL_LOGICAL_MIN : break; - case RI_GLOBAL_LOGICAL_MAX : break; - case RI_GLOBAL_PHYSICAL_MIN : break; - case RI_GLOBAL_PHYSICAL_MAX : break; + case RI_GLOBAL_LOGICAL_MIN: break; + case RI_GLOBAL_LOGICAL_MAX: break; + case RI_GLOBAL_PHYSICAL_MIN: break; + case RI_GLOBAL_PHYSICAL_MAX: break; case RI_GLOBAL_REPORT_ID: info->report_id = data8; - break; + break; case RI_GLOBAL_REPORT_SIZE: // ri_report_size = data8; - break; + break; case RI_GLOBAL_REPORT_COUNT: // ri_report_count = data8; - break; + break; - case RI_GLOBAL_UNIT_EXPONENT : break; - case RI_GLOBAL_UNIT : break; - case RI_GLOBAL_PUSH : break; - case RI_GLOBAL_POP : break; + case RI_GLOBAL_UNIT_EXPONENT: break; + case RI_GLOBAL_UNIT: break; + case RI_GLOBAL_PUSH: break; + case RI_GLOBAL_POP: break; default: break; } - break; + break; case RI_TYPE_LOCAL: - switch(tag) - { + switch (tag) { case RI_LOCAL_USAGE: // only take in account the "usage" before starting REPORT ID - if ( ri_collection_depth == 0 ) info->usage = data8; - break; - - case RI_LOCAL_USAGE_MIN : break; - case RI_LOCAL_USAGE_MAX : break; - case RI_LOCAL_DESIGNATOR_INDEX : break; - case RI_LOCAL_DESIGNATOR_MIN : break; - case RI_LOCAL_DESIGNATOR_MAX : break; - case RI_LOCAL_STRING_INDEX : break; - case RI_LOCAL_STRING_MIN : break; - case RI_LOCAL_STRING_MAX : break; - case RI_LOCAL_DELIMITER : break; + if (ri_collection_depth == 0) info->usage = data8; + break; + + case RI_LOCAL_USAGE_MIN: break; + case RI_LOCAL_USAGE_MAX: break; + case RI_LOCAL_DESIGNATOR_INDEX: break; + case RI_LOCAL_DESIGNATOR_MIN: break; + case RI_LOCAL_DESIGNATOR_MAX: break; + case RI_LOCAL_STRING_INDEX: break; + case RI_LOCAL_STRING_MIN: break; + case RI_LOCAL_STRING_MAX: break; + case RI_LOCAL_DELIMITER: break; default: break; } - break; + break; - // error + // error default: break; } desc_report += size; - desc_len -= size; + desc_len -= size; } - for ( uint8_t i = 0; i < report_num; i++ ) - { - info = report_info_arr+i; + for (uint8_t i = 0; i < report_num; i++) { + info = report_info_arr + i; TU_LOG_DRV("%u: id = %u, usage_page = %u, usage = %u\r\n", i, info->report_id, info->usage_page, info->usage); } diff --git a/test/unit-test/project.yml b/test/unit-test/project.yml index 562dbca09..82528f68c 100644 --- a/test/unit-test/project.yml +++ b/test/unit-test/project.yml @@ -44,12 +44,13 @@ # in order to add common defines: # 1) remove the trailing [] from the :common: section # 2) add entries to the :common: section (e.g. :test: has TEST defined) - :common: &common_defines - - _UNITY_TEST_ + :common: &common_defines [] :test: - - *common_defines + - _UNITY_TEST_ + #- *common_defines :test_preprocess: - - *common_defines + - _UNITY_TEST_ + #- *common_defines :cmock: :mock_prefix: mock_ @@ -106,9 +107,9 @@ :flag: "${1}" # or "-L ${1}" for example :common: &common_libraries [] :test: - - *common_libraries + #- *common_libraries :release: - - *common_libraries + #- *common_libraries :plugins: :load_paths: -- cgit v1.3.1 From 4f5d80d3976fb0dc5cd190b1768225aacf34211b Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 1 Mar 2024 17:40:38 +0700 Subject: add tuh_hid_receive_abort() API --- src/class/hid/hid_host.c | 5 +++++ src/class/hid/hid_host.h | 28 ++++++++++++++++------------ 2 files changed, 21 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 21aee531a..7330fa237 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -320,6 +320,11 @@ bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx) { return true; } +bool tuh_hid_receive_abort(uint8_t dev_addr, uint8_t idx) { + hidh_interface_t* p_hid = get_hid_itf(dev_addr, idx); + TU_VERIFY(p_hid); + return tuh_edpt_abort_xfer(dev_addr, p_hid->ep_in); +} bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx) { hidh_interface_t* p_hid = get_hid_itf(dev_addr, idx); diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h index 238b7c627..17f4e27c0 100644 --- a/src/class/hid/hid_host.h +++ b/src/class/hid/hid_host.h @@ -30,7 +30,7 @@ #include "hid.h" #ifdef __cplusplus - extern "C" { +extern "C" { #endif //--------------------------------------------------------------------+ @@ -47,10 +47,9 @@ #endif -typedef struct -{ - uint8_t report_id; - uint8_t usage; +typedef struct { + uint8_t report_id; + uint8_t usage; uint16_t usage_page; // TODO still use the endpoint size for now @@ -86,7 +85,8 @@ bool tuh_hid_mounted(uint8_t dev_addr, uint8_t idx); // Parse report descriptor into array of report_info struct and return number of reports. // For complicated report, application should write its own parser. -uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr, uint8_t arr_count, uint8_t const* desc_report, uint16_t desc_len) TU_ATTR_UNUSED; +TU_ATTR_UNUSED uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr, uint8_t arr_count, + uint8_t const* desc_report, uint16_t desc_len); //--------------------------------------------------------------------+ // Control Endpoint API @@ -107,7 +107,8 @@ bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t idx, uint8_t protocol); // Set Report using control endpoint // report_type is either Input, Output or Feature, (value from hid_report_type_t) -bool tuh_hid_set_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type, void* report, uint16_t len); +bool tuh_hid_set_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type, + void* report, uint16_t len); //--------------------------------------------------------------------+ // Interrupt Endpoint API @@ -121,6 +122,9 @@ bool tuh_hid_receive_ready(uint8_t dev_addr, uint8_t idx); // - false if failed to queue the transfer e.g endpoint is busy bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t idx); +// Abort receiving report on Interrupt Endpoint +bool tuh_hid_receive_abort(uint8_t dev_addr, uint8_t idx); + // Check if HID interface is ready to send report bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx); @@ -159,11 +163,11 @@ TU_ATTR_WEAK void tuh_hid_set_protocol_complete_cb(uint8_t dev_addr, uint8_t idx //--------------------------------------------------------------------+ // Internal Class Driver API //--------------------------------------------------------------------+ -void hidh_init (void); -bool hidh_open (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len); -bool hidh_set_config (uint8_t dev_addr, uint8_t itf_num); -bool hidh_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); -void hidh_close (uint8_t dev_addr); +void hidh_init(void); +bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const* desc_itf, uint16_t max_len); +bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num); +bool hidh_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); +void hidh_close(uint8_t dev_addr); #ifdef __cplusplus } -- cgit v1.3.1 From ff76eca311f4026c1a9b36e9ad37bbb53b39cf5d Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 4 Mar 2024 16:15:26 +0700 Subject: code reformat --- src/host/usbh.c | 563 ++++++++++++++++++++++++-------------------------------- src/tusb.c | 12 +- 2 files changed, 245 insertions(+), 330 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index f56290a0c..407d97234 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -420,20 +420,18 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { (void) in_isr; // not implemented yet // Skip if stack is not initialized - if ( !tuh_inited() ) return; + if (!tuh_inited()) return; // Loop until there is no more events in the queue - while (1) - { + while (1) { hcd_event_t event; - if ( !osal_queue_receive(_usbh_q, &event, timeout_ms) ) return; + if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) return; - switch (event.event_id) - { + switch (event.event_id) { case HCD_EVENT_DEVICE_ATTACH: // due to the shared _usbh_ctrl_buf, we must complete enumerating one device before enumerating another one. // TODO better to have an separated queue for newly attached devices - if ( _dev0.enumerating ) { + if (_dev0.enumerating) { TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport); bool is_empty = osal_queue_empty(_usbh_q); @@ -443,12 +441,12 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { // Exit if this is the only event in the queue, otherwise we may loop forever return; } - }else { + } else { TU_LOG_USBH("[%u:] USBH DEVICE ATTACH\r\n", event.rhport); _dev0.enumerating = 1; enum_new_device(&event); } - break; + break; case HCD_EVENT_DEVICE_REMOVE: TU_LOG_USBH("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port); @@ -456,37 +454,34 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { #if CFG_TUH_HUB // TODO remove - if ( event.connection.hub_addr != 0 && event.connection.hub_port != 0) { + if (event.connection.hub_addr != 0 && event.connection.hub_port != 0) { // done with hub, waiting for next data on status pipe - (void) hub_edpt_status_xfer( event.connection.hub_addr ); + (void) hub_edpt_status_xfer(event.connection.hub_addr); } #endif - break; + break; - case HCD_EVENT_XFER_COMPLETE: - { + case HCD_EVENT_XFER_COMPLETE: { uint8_t const ep_addr = event.xfer_complete.ep_addr; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const ep_dir = tu_edpt_dir(ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const ep_dir = (uint8_t) tu_edpt_dir(ep_addr); - TU_LOG_USBH("on EP %02X with %u bytes: %s\r\n", ep_addr, (unsigned int) event.xfer_complete.len, - tu_str_xfer_result[event.xfer_complete.result]); + TU_LOG_USBH("on EP %02X with %u bytes: %s\r\n", ep_addr, (unsigned int) event.xfer_complete.len, tu_str_xfer_result[event.xfer_complete.result]); if (event.dev_addr == 0) { // device 0 only has control endpoint - TU_ASSERT(epnum == 0, ); + TU_ASSERT(epnum == 0,); usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len); } else { usbh_device_t* dev = get_device(event.dev_addr); - TU_VERIFY(dev && dev->connected, ); + TU_VERIFY(dev && dev->connected,); - dev->ep_status[epnum][ep_dir].busy = 0; + dev->ep_status[epnum][ep_dir].busy = 0; dev->ep_status[epnum][ep_dir].claimed = 0; - if ( 0 == epnum ) { - usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, - event.xfer_complete.len); - }else { + if (0 == epnum) { + usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len); + } else { // Prefer application callback over built-in one if available. This occurs when tuh_edpt_xfer() is used // with enabled driver e.g HID endpoint #if CFG_TUH_API_EDPT_XFER @@ -503,35 +498,32 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { .complete_cb = complete_cb, .user_data = dev->ep_callback[epnum][ep_dir].user_data }; - complete_cb(&xfer); }else #endif { uint8_t drv_id = dev->ep2drv[epnum][ep_dir]; - usbh_class_driver_t const * driver = get_driver(drv_id); - if ( driver ) - { + usbh_class_driver_t const* driver = get_driver(drv_id); + if (driver) { TU_LOG_USBH("%s xfer callback\r\n", driver->name); driver->xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len); - } - else - { + } else { // no driver/callback responsible for this transfer TU_ASSERT(false,); } } } } + break; } - break; case USBH_EVENT_FUNC_CALL: - if ( event.func_call.func ) event.func_call.func(event.func_call.param); - break; + if (event.func_call.func) event.func_call.func(event.func_call.param); + break; - default: break; + default: + break; } #if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO @@ -708,7 +700,6 @@ bool tuh_edpt_xfer(tuh_xfer_t* xfer) { uint8_t const ep_addr = xfer->ep_addr; TU_VERIFY(daddr && ep_addr); - TU_VERIFY(usbh_edpt_claim(daddr, ep_addr)); if (!usbh_edpt_xfer_with_callback(daddr, ep_addr, xfer->buffer, (uint16_t) xfer->buflen, @@ -783,14 +774,13 @@ void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr) { //--------------------------------------------------------------------+ // Claim an endpoint for transfer -bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr) -{ +bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr) { // Note: addr0 only use tuh_control_xfer usbh_device_t* dev = get_device(dev_addr); TU_ASSERT(dev && dev->connected); uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); TU_VERIFY(tu_edpt_claim(&dev->ep_status[epnum][dir], _usbh_mutex)); TU_LOG_USBH("[%u] Claimed EP 0x%02x\r\n", dev_addr, ep_addr); @@ -799,14 +789,13 @@ bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr) } // Release an claimed endpoint due to failed transfer attempt -bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr) -{ +bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr) { // Note: addr0 only use tuh_control_xfer usbh_device_t* dev = get_device(dev_addr); TU_VERIFY(dev && dev->connected); uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); TU_VERIFY(tu_edpt_release(&dev->ep_status[epnum][dir], _usbh_mutex)); TU_LOG_USBH("[%u] Released EP 0x%02x\r\n", dev_addr, ep_addr); @@ -816,9 +805,8 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr) // Submit an transfer // TODO call usbh_edpt_release if failed -bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { (void) complete_cb; (void) user_data; @@ -826,7 +814,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b TU_VERIFY(dev); uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir]; TU_LOG_USBH(" Queue EP %02X with %u bytes ... \r\n", ep_addr, total_bytes); @@ -843,14 +831,12 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b dev->ep_callback[epnum][dir].user_data = user_data; #endif - if ( hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes) ) - { + if (hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes)) { TU_LOG_USBH("OK\r\n"); return true; - }else - { + } else { // HCD error, mark endpoint as ready to allow next transfer - ep_state->busy = 0; + ep_state->busy = 0; ep_state->claimed = 0; TU_LOG1("Failed\r\n"); // TU_BREAKPOINT(); @@ -858,12 +844,9 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b } } -static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size) -{ +static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size) { TU_LOG_USBH("[%u:%u] Open EP0 with Size = %u\r\n", usbh_get_rhport(dev_addr), dev_addr, max_packet_size); - - tusb_desc_endpoint_t ep0_desc = - { + tusb_desc_endpoint_t ep0_desc = { .bLength = sizeof(tusb_desc_endpoint_t), .bDescriptorType = TUSB_DESC_ENDPOINT, .bEndpointAddress = 0, @@ -875,10 +858,8 @@ static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size) return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, &ep0_desc); } -bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep) -{ - TU_ASSERT( tu_edpt_validate(desc_ep, tuh_speed_get(dev_addr)) ); - +bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const* desc_ep) { + TU_ASSERT(tu_edpt_validate(desc_ep, tuh_speed_get(dev_addr))); return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, desc_ep); } @@ -887,7 +868,7 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr) { TU_VERIFY(dev); uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); return dev->ep_status[epnum][dir].busy; } @@ -896,22 +877,18 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr) { // HCD Event Handler //--------------------------------------------------------------------+ -void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info) -{ +void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info) { usbh_device_t const* dev = get_device(dev_addr); - - if (dev) - { - devtree_info->rhport = dev->rhport; + if (dev) { + devtree_info->rhport = dev->rhport; devtree_info->hub_addr = dev->hub_addr; devtree_info->hub_port = dev->hub_port; - devtree_info->speed = dev->speed; - }else - { - devtree_info->rhport = _dev0.rhport; + devtree_info->speed = dev->speed; + } else { + devtree_info->rhport = _dev0.rhport; devtree_info->hub_addr = _dev0.hub_addr; devtree_info->hub_port = _dev0.hub_port; - devtree_info->speed = _dev0.speed; + devtree_info->speed = _dev0.speed; } } @@ -941,12 +918,9 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) // generic helper to get a descriptor // if blocking, user_data is pointed to xfer_result static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t language_id, void* buffer, uint16_t len, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ - tusb_control_request_t const request = - { - .bmRequestType_bit = - { + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + tusb_control_request_t const request = { + .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_DEVICE, .type = TUSB_REQ_TYPE_STANDARD, .direction = TUSB_DIR_IN @@ -956,9 +930,7 @@ static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t .wIndex = tu_htole16(language_id), .wLength = tu_htole16(len) }; - - tuh_xfer_t xfer = - { + tuh_xfer_t xfer = { .daddr = daddr, .ep_addr = 0, .setup = &request, @@ -971,29 +943,25 @@ static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t } bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return _get_descriptor(daddr, type, index, 0x0000, buffer, len, complete_cb, user_data); } bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { len = tu_min16(len, sizeof(tusb_desc_device_t)); return tuh_descriptor_get(daddr, TUSB_DESC_DEVICE, 0, buffer, len, complete_cb, user_data); } bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return tuh_descriptor_get(daddr, TUSB_DESC_CONFIGURATION, index, buffer, len, complete_cb, user_data); } //------------- String Descriptor -------------// bool tuh_descriptor_get_string(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return _get_descriptor(daddr, TUSB_DESC_STRING, index, language_id, buffer, len, complete_cb, user_data); } @@ -1008,8 +976,7 @@ bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, // Get product string descriptor bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { usbh_device_t const* dev = get_device(daddr); TU_VERIFY(dev && dev->i_product); return tuh_descriptor_get_string(daddr, dev->i_product, language_id, buffer, len, complete_cb, user_data); @@ -1017,8 +984,7 @@ bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void // Get serial string descriptor bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { usbh_device_t const* dev = get_device(daddr); TU_VERIFY(dev && dev->i_serial); return tuh_descriptor_get_string(daddr, dev->i_serial, language_id, buffer, len, complete_cb, user_data); @@ -1027,95 +993,78 @@ bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* // Get HID report descriptor // if blocking, user_data is pointed to xfer_result bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_USBH("HID Get Report Descriptor\r\n"); - tusb_control_request_t const request = - { - .bmRequestType_bit = - { - .recipient = TUSB_REQ_RCPT_INTERFACE, - .type = TUSB_REQ_TYPE_STANDARD, - .direction = TUSB_DIR_IN - }, - .bRequest = TUSB_REQ_GET_DESCRIPTOR, - .wValue = tu_htole16(TU_U16(desc_type, index)), - .wIndex = tu_htole16((uint16_t) itf_num), - .wLength = len + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_STANDARD, + .direction = TUSB_DIR_IN + }, + .bRequest = TUSB_REQ_GET_DESCRIPTOR, + .wValue = tu_htole16(TU_U16(desc_type, index)), + .wIndex = tu_htole16((uint16_t) itf_num), + .wLength = len }; - - tuh_xfer_t xfer = - { - .daddr = daddr, - .ep_addr = 0, - .setup = &request, - .buffer = buffer, - .complete_cb = complete_cb, - .user_data = user_data + tuh_xfer_t xfer = { + .daddr = daddr, + .ep_addr = 0, + .setup = &request, + .buffer = buffer, + .complete_cb = complete_cb, + .user_data = user_data }; return tuh_control_xfer(&xfer); } bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_USBH("Set Configuration = %d\r\n", config_num); - - tusb_control_request_t const request = - { - .bmRequestType_bit = - { - .recipient = TUSB_REQ_RCPT_DEVICE, - .type = TUSB_REQ_TYPE_STANDARD, - .direction = TUSB_DIR_OUT - }, - .bRequest = TUSB_REQ_SET_CONFIGURATION, - .wValue = tu_htole16(config_num), - .wIndex = 0, - .wLength = 0 + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_DEVICE, + .type = TUSB_REQ_TYPE_STANDARD, + .direction = TUSB_DIR_OUT + }, + .bRequest = TUSB_REQ_SET_CONFIGURATION, + .wValue = tu_htole16(config_num), + .wIndex = 0, + .wLength = 0 }; - - tuh_xfer_t xfer = - { - .daddr = daddr, - .ep_addr = 0, - .setup = &request, - .buffer = NULL, - .complete_cb = complete_cb, - .user_data = user_data + tuh_xfer_t xfer = { + .daddr = daddr, + .ep_addr = 0, + .setup = &request, + .buffer = NULL, + .complete_cb = complete_cb, + .user_data = user_data }; return tuh_control_xfer(&xfer); } bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_USBH("Set Interface %u Alternate %u\r\n", itf_num, itf_alt); - - tusb_control_request_t const request = - { - .bmRequestType_bit = - { - .recipient = TUSB_REQ_RCPT_DEVICE, - .type = TUSB_REQ_TYPE_STANDARD, - .direction = TUSB_DIR_OUT - }, - .bRequest = TUSB_REQ_SET_INTERFACE, - .wValue = tu_htole16(itf_alt), - .wIndex = tu_htole16(itf_num), - .wLength = 0 + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_DEVICE, + .type = TUSB_REQ_TYPE_STANDARD, + .direction = TUSB_DIR_OUT + }, + .bRequest = TUSB_REQ_SET_INTERFACE, + .wValue = tu_htole16(itf_alt), + .wIndex = tu_htole16(itf_num), + .wLength = 0 }; - - tuh_xfer_t xfer = - { - .daddr = daddr, - .ep_addr = 0, - .setup = &request, - .buffer = NULL, - .complete_cb = complete_cb, - .user_data = user_data + tuh_xfer_t xfer = { + .daddr = daddr, + .ep_addr = 0, + .setup = &request, + .buffer = NULL, + .complete_cb = complete_cb, + .user_data = user_data }; return tuh_control_xfer(&xfer); @@ -1174,9 +1123,7 @@ uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_i // Detaching //--------------------------------------------------------------------+ -TU_ATTR_ALWAYS_INLINE -static inline bool is_hub_addr(uint8_t daddr) -{ +TU_ATTR_ALWAYS_INLINE static inline bool is_hub_addr(uint8_t daddr) { return (CFG_TUH_HUB > 0) && (daddr > CFG_TUH_DEVICE_MAX); } @@ -1201,8 +1148,7 @@ static inline bool is_hub_addr(uint8_t daddr) //} // a device unplugged from rhport:hub_addr:hub_port -static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) -{ +static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) { //------------- find the all devices (star-network) under port that is unplugged -------------// // TODO mark as disconnected in ISR, also handle dev0 @@ -1217,8 +1163,7 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu uint8_t nop_count = 0; #endif - for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) - { + for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) { usbh_device_t *dev = &_usbh_devices[dev_id]; uint8_t const daddr = dev_id + 1; @@ -1325,165 +1270,160 @@ static void process_enumeration(tuh_xfer_t* xfer) { uint8_t const daddr = xfer->daddr; uintptr_t const state = xfer->user_data; - switch(state) - { -#if CFG_TUH_HUB + switch (state) { + #if CFG_TUH_HUB //case ENUM_HUB_GET_STATUS_1: break; - case ENUM_HUB_CLEAR_RESET_1: - { + case ENUM_HUB_CLEAR_RESET_1: { hub_port_status_response_t port_status; memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t)); - if ( !port_status.status.connection ) - { + if (!port_status.status.connection) { // device unplugged while delaying, nothing else to do enum_full_complete(); return; } _dev0.speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH : - (port_status.status.low_speed ) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL; + (port_status.status.low_speed) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL; // Acknowledge Port Reset Change - if (port_status.change.reset) - { - hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_ADDR0_DEVICE_DESC); + if (port_status.change.reset) { + hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port, + process_enumeration, ENUM_ADDR0_DEVICE_DESC); } + break; } - break; case ENUM_HUB_GET_STATUS_2: osal_task_delay(ENUM_RESET_DELAY); - TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, process_enumeration, ENUM_HUB_CLEAR_RESET_2), ); - break; + TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, + process_enumeration, ENUM_HUB_CLEAR_RESET_2),); + break; - case ENUM_HUB_CLEAR_RESET_2: - { + case ENUM_HUB_CLEAR_RESET_2: { hub_port_status_response_t port_status; memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t)); // Acknowledge Port Reset Change if Reset Successful - if (port_status.change.reset) - { - TU_ASSERT( hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_SET_ADDR), ); + if (port_status.change.reset) { + TU_ASSERT(hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port, + process_enumeration, ENUM_SET_ADDR),); } + break; } - break; -#endif + #endif - case ENUM_ADDR0_DEVICE_DESC: - { + case ENUM_ADDR0_DEVICE_DESC: { // TODO probably doesn't need to open/close each enumeration uint8_t const addr0 = 0; - TU_ASSERT( usbh_edpt_control_open(addr0, 8), ); + TU_ASSERT(usbh_edpt_control_open(addr0, 8),); // Get first 8 bytes of device descriptor for Control Endpoint size TU_LOG_USBH("Get 8 byte of Device Descriptor\r\n"); - TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, process_enumeration, ENUM_SET_ADDR), ); + TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, + process_enumeration, ENUM_SET_ADDR),); + break; } - break; #if 0 - case ENUM_RESET_2: - // TODO not used by now, but may be needed for some devices !? - // Reset device again before Set Address - TU_LOG_USBH("Port reset2 \r\n"); - if (_dev0.hub_addr == 0) - { - // connected directly to roothub - hcd_port_reset( _dev0.rhport ); - osal_task_delay(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since - // sof of controller may not running while resetting - hcd_port_reset_end(_dev0.rhport); - // TODO: fall through to SET ADDRESS, refactor later - } - #if CFG_TUH_HUB - else - { - // after RESET_DELAY the hub_port_reset() already complete - TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_HUB_GET_STATUS_2), ); - break; - } - #endif - TU_ATTR_FALLTHROUGH; + case ENUM_RESET_2: + // TODO not used by now, but may be needed for some devices !? + // Reset device again before Set Address + TU_LOG_USBH("Port reset2 \r\n"); + if (_dev0.hub_addr == 0) { + // connected directly to roothub + hcd_port_reset( _dev0.rhport ); + osal_task_delay(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since + // sof of controller may not running while resetting + hcd_port_reset_end(_dev0.rhport); + // TODO: fall through to SET ADDRESS, refactor later + } +#if CFG_TUH_HUB + else { + // after RESET_DELAY the hub_port_reset() already complete + TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port, + process_enumeration, ENUM_HUB_GET_STATUS_2), ); + break; + } +#endif + TU_ATTR_FALLTHROUGH; #endif case ENUM_SET_ADDR: enum_request_set_addr(); - break; + break; - case ENUM_GET_DEVICE_DESC: - { + case ENUM_GET_DEVICE_DESC: { uint8_t const new_addr = (uint8_t) tu_le16toh(xfer->setup->wValue); usbh_device_t* new_dev = get_device(new_addr); - TU_ASSERT(new_dev, ); + TU_ASSERT(new_dev,); new_dev->addressed = 1; // Close device 0 hcd_device_close(_dev0.rhport, 0); // open control pipe for new address - TU_ASSERT( usbh_edpt_control_open(new_addr, new_dev->ep0_size), ); + TU_ASSERT(usbh_edpt_control_open(new_addr, new_dev->ep0_size),); // Get full device descriptor TU_LOG_USBH("Get Device Descriptor\r\n"); - TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC), ); + TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), + process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC),); + break; } - break; - case ENUM_GET_9BYTE_CONFIG_DESC: - { - tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf; + case ENUM_GET_9BYTE_CONFIG_DESC: { + tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf; usbh_device_t* dev = get_device(daddr); - TU_ASSERT(dev, ); + TU_ASSERT(dev,); - dev->vid = desc_device->idVendor; - dev->pid = desc_device->idProduct; + dev->vid = desc_device->idVendor; + dev->pid = desc_device->idProduct; dev->i_manufacturer = desc_device->iManufacturer; - dev->i_product = desc_device->iProduct; - dev->i_serial = desc_device->iSerialNumber; + dev->i_product = desc_device->iProduct; + dev->i_serial = desc_device->iSerialNumber; - // if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf); + // if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf); // Get 9-byte for total length uint8_t const config_idx = CONFIG_NUM - 1; TU_LOG_USBH("Get Configuration[0] Descriptor (9 bytes)\r\n"); - TU_ASSERT( tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, 9, process_enumeration, ENUM_GET_FULL_CONFIG_DESC), ); + TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, 9, + process_enumeration, ENUM_GET_FULL_CONFIG_DESC),); + break; } - break; - case ENUM_GET_FULL_CONFIG_DESC: - { - uint8_t const * desc_config = _usbh_ctrl_buf; + case ENUM_GET_FULL_CONFIG_DESC: { + uint8_t const* desc_config = _usbh_ctrl_buf; // Use offsetof to avoid pointer to the odd/misaligned address - uint16_t const total_len = tu_le16toh( tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)) ); + uint16_t const total_len = tu_le16toh( + tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength))); // TODO not enough buffer to hold configuration descriptor - TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE, ); + TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE,); // Get full configuration descriptor uint8_t const config_idx = CONFIG_NUM - 1; TU_LOG_USBH("Get Configuration[0] Descriptor\r\n"); - TU_ASSERT( tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, total_len, process_enumeration, ENUM_SET_CONFIG), ); + TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, total_len, + process_enumeration, ENUM_SET_CONFIG),); + break; } - break; case ENUM_SET_CONFIG: // Parse configuration & set up drivers // Driver open aren't allowed to make any usb transfer yet - TU_ASSERT( _parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_ctrl_buf), ); - - TU_ASSERT( tuh_configuration_set(daddr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER), ); - break; + TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_ctrl_buf),); + TU_ASSERT(tuh_configuration_set(daddr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER),); + break; - case ENUM_CONFIG_DRIVER: - { + case ENUM_CONFIG_DRIVER: { TU_LOG_USBH("Device configured\r\n"); usbh_device_t* dev = get_device(daddr); - TU_ASSERT(dev, ); + TU_ASSERT(dev,); dev->configured = 1; @@ -1492,60 +1432,58 @@ static void process_enumeration(tuh_xfer_t* xfer) { // The process continue with next interface when class driver complete its sequence with usbh_driver_set_config_complete() // TODO use separated API instead of using TUSB_INDEX_INVALID_8 usbh_driver_set_config_complete(daddr, TUSB_INDEX_INVALID_8); + break; } - break; default: // stop enumeration if unknown state enum_full_complete(); - break; + break; } } -static bool enum_new_device(hcd_event_t* event) -{ - _dev0.rhport = event->rhport; +static bool enum_new_device(hcd_event_t* event) { + _dev0.rhport = event->rhport; _dev0.hub_addr = event->connection.hub_addr; _dev0.hub_port = event->connection.hub_port; - if (_dev0.hub_addr == 0) - { + if (_dev0.hub_addr == 0) { // connected/disconnected directly with roothub hcd_port_reset(_dev0.rhport); osal_task_delay(ENUM_RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since - // sof of controller may not running while resetting - hcd_port_reset_end( _dev0.rhport); + // sof of controller may not running while resetting + hcd_port_reset_end(_dev0.rhport); // wait until device connection is stable TODO non blocking osal_task_delay(ENUM_CONTACT_DEBOUNCING_DELAY); // device unplugged while delaying - if ( !hcd_port_connect_status(_dev0.rhport) ) { + if (!hcd_port_connect_status(_dev0.rhport)) { enum_full_complete(); return true; } - _dev0.speed = hcd_port_speed_get(_dev0.rhport ); + _dev0.speed = hcd_port_speed_get(_dev0.rhport); TU_LOG_USBH("%s Speed\r\n", tu_str_speed[_dev0.speed]); // fake transfer to kick-off the enumeration process tuh_xfer_t xfer; - xfer.daddr = 0; - xfer.result = XFER_RESULT_SUCCESS; + xfer.daddr = 0; + xfer.result = XFER_RESULT_SUCCESS; xfer.user_data = ENUM_ADDR0_DEVICE_DESC; process_enumeration(&xfer); } #if CFG_TUH_HUB - else - { + else { // connected/disconnected via external hub // wait until device connection is stable TODO non blocking osal_task_delay(ENUM_CONTACT_DEBOUNCING_DELAY); // ENUM_HUB_GET_STATUS //TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status0_complete, 0) ); - TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, process_enumeration, ENUM_HUB_CLEAR_RESET_1) ); + TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, + process_enumeration, ENUM_HUB_CLEAR_RESET_1)); } #endif // hub @@ -1571,58 +1509,48 @@ static uint8_t get_new_address(bool is_hub) { return 0; // invalid address } -static bool enum_request_set_addr(void) -{ - tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf; +static bool enum_request_set_addr(void) { + tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf; // Get new address uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB); TU_ASSERT(new_addr != 0); - TU_LOG_USBH("Set Address = %d\r\n", new_addr); usbh_device_t* new_dev = get_device(new_addr); - - new_dev->rhport = _dev0.rhport; - new_dev->hub_addr = _dev0.hub_addr; - new_dev->hub_port = _dev0.hub_port; - new_dev->speed = _dev0.speed; + new_dev->rhport = _dev0.rhport; + new_dev->hub_addr = _dev0.hub_addr; + new_dev->hub_port = _dev0.hub_port; + new_dev->speed = _dev0.speed; new_dev->connected = 1; - new_dev->ep0_size = desc_device->bMaxPacketSize0; - - tusb_control_request_t const request = - { - .bmRequestType_bit = - { - .recipient = TUSB_REQ_RCPT_DEVICE, - .type = TUSB_REQ_TYPE_STANDARD, - .direction = TUSB_DIR_OUT - }, - .bRequest = TUSB_REQ_SET_ADDRESS, - .wValue = tu_htole16(new_addr), - .wIndex = 0, - .wLength = 0 + new_dev->ep0_size = desc_device->bMaxPacketSize0; + + tusb_control_request_t const request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_DEVICE, + .type = TUSB_REQ_TYPE_STANDARD, + .direction = TUSB_DIR_OUT + }, + .bRequest = TUSB_REQ_SET_ADDRESS, + .wValue = tu_htole16(new_addr), + .wIndex = 0, + .wLength = 0 }; - - tuh_xfer_t xfer = - { - .daddr = 0, // dev0 - .ep_addr = 0, - .setup = &request, - .buffer = NULL, - .complete_cb = process_enumeration, - .user_data = ENUM_GET_DEVICE_DESC + tuh_xfer_t xfer = { + .daddr = 0, // dev0 + .ep_addr = 0, + .setup = &request, + .buffer = NULL, + .complete_cb = process_enumeration, + .user_data = ENUM_GET_DEVICE_DESC }; - TU_ASSERT( tuh_control_xfer(&xfer) ); - + TU_ASSERT(tuh_control_xfer(&xfer)); return true; } -static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg) -{ +static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg) { usbh_device_t* dev = get_device(dev_addr); - uint16_t const total_len = tu_le16toh(desc_cfg->wTotalLength); uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + total_len; uint8_t const* p_desc = tu_desc_next(desc_cfg); @@ -1630,13 +1558,11 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur TU_LOG_USBH("Parsing Configuration descriptor (wTotalLength = %u)\r\n", total_len); // parse each interfaces - while( p_desc < desc_end ) - { + while( p_desc < desc_end ) { uint8_t assoc_itf_count = 1; // Class will always starts with Interface Association (if any) and then Interface descriptor - if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) ) - { + if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) ) { tusb_desc_interface_assoc_t const * desc_iad = (tusb_desc_interface_assoc_t const *) p_desc; assoc_itf_count = desc_iad->bInterfaceCount; @@ -1656,8 +1582,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur if (1 == assoc_itf_count && TUSB_CLASS_AUDIO == desc_itf->bInterfaceClass && AUDIO_SUBCLASS_CONTROL == desc_itf->bInterfaceSubClass && - AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol) - { + AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol) { assoc_itf_count = 2; } #endif @@ -1667,8 +1592,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur // manually force associated count = 2 if (1 == assoc_itf_count && TUSB_CLASS_CDC == desc_itf->bInterfaceClass && - CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == desc_itf->bInterfaceSubClass) - { + CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == desc_itf->bInterfaceSubClass) { assoc_itf_count = 2; } #endif @@ -1677,18 +1601,14 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t)); // Find driver for this interface - for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) - { + for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) { usbh_class_driver_t const * driver = get_driver(drv_id); - - if (driver && driver->open(dev->rhport, dev_addr, desc_itf, drv_len) ) - { + if (driver && driver->open(dev->rhport, dev_addr, desc_itf, drv_len) ) { // open successfully TU_LOG_USBH(" %s opened\r\n", driver->name); // bind (associated) interfaces to found driver - for(uint8_t i=0; ibInterfaceNumber+i; // Interface number must not be used already @@ -1702,8 +1622,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur break; // exit driver find loop } - if ( drv_id == TOTAL_DRIVER_COUNT - 1 ) - { + if ( drv_id == TOTAL_DRIVER_COUNT - 1 ) { TU_LOG_USBH("[%u:%u] Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n", dev->rhport, dev_addr, desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol); } diff --git a/src/tusb.c b/src/tusb.c index 3ef380c83..7c86f1ca5 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -112,8 +112,7 @@ uint8_t const * tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t b // Endpoint Helper for both Host and Device stack //--------------------------------------------------------------------+ -bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex) -{ +bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex) { (void) mutex; // pre-check to help reducing mutex lock @@ -122,8 +121,7 @@ bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex) // can only claim the endpoint if it is not busy and not claimed yet. bool const available = (ep_state->busy == 0) && (ep_state->claimed == 0); - if (available) - { + if (available) { ep_state->claimed = 1; } @@ -132,16 +130,14 @@ bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex) return available; } -bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex) -{ +bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex) { (void) mutex; (void) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER); // can only release the endpoint if it is claimed and not busy bool const ret = (ep_state->claimed == 1) && (ep_state->busy == 0); - if (ret) - { + if (ret) { ep_state->claimed = 0; } -- cgit v1.3.1 From 1d3969acbd1d85753c8ad085097a26dcd628afcb Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 4 Mar 2024 17:44:53 +0700 Subject: - usbh enumeration: move _parse_configuration_descriptor after SET_CONFIGURATION is successful - usbh: abort all pending xfer when SET_CONFIGURATION is complete - use tu_edpt_release in tuh_edpt_abort_xfer instead of usbh_edpt_release - rename _xfer_complete -> _control_xfer_complete --- src/host/usbh.c | 44 ++++++++++++++++++++++++++++---------------- 1 file changed, 28 insertions(+), 16 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 407d97234..625857683 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -621,7 +621,7 @@ TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage) (void) osal_mutex_unlock(_usbh_mutex); } -static void _xfer_complete(uint8_t daddr, xfer_result_t result) { +static void _control_xfer_complete(uint8_t daddr, xfer_result_t result) { TU_LOG_USBH("\r\n"); // duplicate xfer since user can execute control transfer within callback @@ -644,32 +644,32 @@ static void _xfer_complete(uint8_t daddr, xfer_result_t result) { } } -static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { +static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { (void) ep_addr; - const uint8_t rhport = usbh_get_rhport(dev_addr); + const uint8_t rhport = usbh_get_rhport(daddr); tusb_control_request_t const * request = &_ctrl_xfer.request; if (XFER_RESULT_SUCCESS != result) { - TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes); + TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, daddr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes); TU_LOG_BUF_USBH(request, 8); // terminate transfer if any stage failed - _xfer_complete(dev_addr, result); + _control_xfer_complete(daddr, result); }else { switch(_ctrl_xfer.stage) { case CONTROL_STAGE_SETUP: if (request->wLength) { // DATA stage: initial data toggle is always 1 _set_control_xfer_stage(CONTROL_STAGE_DATA); - TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength) ); + TU_ASSERT( hcd_edpt_xfer(rhport, daddr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength) ); return true; } TU_ATTR_FALLTHROUGH; case CONTROL_STAGE_DATA: if (request->wLength) { - TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, dev_addr); + TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, daddr); TU_LOG_MEM_USBH(_ctrl_xfer.buffer, xferred_bytes, 2); } @@ -677,12 +677,23 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result // ACK stage: toggle is always 1 _set_control_xfer_stage(CONTROL_STAGE_ACK); - TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0) ); - break; + TU_ASSERT( hcd_edpt_xfer(rhport, daddr, tu_edpt_addr(0, 1 - request->bmRequestType_bit.direction), NULL, 0) ); + break; - case CONTROL_STAGE_ACK: - _xfer_complete(dev_addr, result); - break; + case CONTROL_STAGE_ACK: { + // Abort all pending transfers if SET_CONFIGURATION request + // NOTE: should we force closing all non-control endpoints in the future? + if (request->bRequest == TUSB_REQ_SET_CONFIGURATION && request->bmRequestType == 0x00) { + for(uint8_t epnum=1; epnumrhport, daddr, ep_addr)); // mark as ready and release endpoint if transfer is aborted dev->ep_status[epnum][dir].busy = false; - usbh_edpt_release(daddr, ep_addr); + tu_edpt_release(&dev->ep_status[epnum][dir], _usbh_mutex); } return true; @@ -1414,9 +1425,6 @@ static void process_enumeration(tuh_xfer_t* xfer) { } case ENUM_SET_CONFIG: - // Parse configuration & set up drivers - // Driver open aren't allowed to make any usb transfer yet - TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_ctrl_buf),); TU_ASSERT(tuh_configuration_set(daddr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER),); break; @@ -1427,6 +1435,10 @@ static void process_enumeration(tuh_xfer_t* xfer) { dev->configured = 1; + // Parse configuration & set up drivers + // driver_open() must not make any usb transfer + TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_ctrl_buf),); + // Start the Set Configuration process for interfaces (itf = TUSB_INDEX_INVALID_8) // Since driver can perform control transfer within its set_config, this is done asynchronously. // The process continue with next interface when class driver complete its sequence with usbh_driver_set_config_complete() -- cgit v1.3.1 From 56532321443ed1ada8c2f33bd9eb6f075da66394 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 5 Mar 2024 19:43:37 +0700 Subject: reformat code --- src/device/usbd.c | 306 +++++++++---------------- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 330 +++++++++++---------------- src/portable/raspberrypi/rp2040/rp2040_usb.c | 167 ++++++-------- 3 files changed, 316 insertions(+), 487 deletions(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index be85d7769..87542e9aa 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -372,10 +372,9 @@ bool tud_inited(void) { return _usbd_rhport != RHPORT_INVALID; } -bool tud_init (uint8_t rhport) -{ +bool tud_init(uint8_t rhport) { // skip if already initialized - if ( tud_inited() ) return true; + if (tud_inited()) return true; TU_LOG_USBD("USBD init on controller %u\r\n", rhport); TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(usbd_device_t)); @@ -395,15 +394,13 @@ bool tud_init (uint8_t rhport) TU_ASSERT(_usbd_q); // Get application driver if available - if ( usbd_app_driver_get_cb ) - { + if (usbd_app_driver_get_cb) { _app_driver = usbd_app_driver_get_cb(&_app_driver_count); } // Init class drivers - for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) - { - usbd_class_driver_t const * driver = get_driver(i); + for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) { + usbd_class_driver_t const* driver = get_driver(i); TU_ASSERT(driver); TU_LOG_USBD("%s init\r\n", driver->name); driver->init(); @@ -418,31 +415,26 @@ bool tud_init (uint8_t rhport) return true; } -static void configuration_reset(uint8_t rhport) -{ - for ( uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++ ) - { - usbd_class_driver_t const * driver = get_driver(i); - TU_ASSERT(driver, ); +static void configuration_reset(uint8_t rhport) { + for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) { + usbd_class_driver_t const* driver = get_driver(i); + TU_ASSERT(driver,); driver->reset(rhport); } tu_varclr(&_usbd_dev); memset(_usbd_dev.itf2drv, DRVID_INVALID, sizeof(_usbd_dev.itf2drv)); // invalid mapping - memset(_usbd_dev.ep2drv , DRVID_INVALID, sizeof(_usbd_dev.ep2drv )); // invalid mapping + memset(_usbd_dev.ep2drv, DRVID_INVALID, sizeof(_usbd_dev.ep2drv)); // invalid mapping } -static void usbd_reset(uint8_t rhport) -{ +static void usbd_reset(uint8_t rhport) { configuration_reset(rhport); usbd_control_reset(); } -bool tud_task_event_ready(void) -{ +bool tud_task_event_ready(void) { // Skip if stack is not initialized - if ( !tud_inited() ) return false; - + if (!tud_inited()) return false; return !osal_queue_empty(_usbd_q); } @@ -450,53 +442,44 @@ bool tud_task_event_ready(void) * This top level thread manages all device controller event and delegates events to class-specific drivers. * This should be called periodically within the mainloop or rtos thread. * - @code - int main(void) - { + int main(void) { application_init(); tusb_init(); - while(1) // the mainloop - { + while(1) { // the mainloop application_code(); tud_task(); // tinyusb device task } } - @endcode */ -void tud_task_ext(uint32_t timeout_ms, bool in_isr) -{ +void tud_task_ext(uint32_t timeout_ms, bool in_isr) { (void) in_isr; // not implemented yet // Skip if stack is not initialized - if ( !tud_inited() ) return; + if (!tud_inited()) return; // Loop until there is no more events in the queue - while (1) - { + while (1) { dcd_event_t event; - if ( !osal_queue_receive(_usbd_q, &event, timeout_ms) ) return; + if (!osal_queue_receive(_usbd_q, &event, timeout_ms)) return; #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL if (event.event_id == DCD_EVENT_SETUP_RECEIVED) TU_LOG_USBD("\r\n"); // extra line for setup TU_LOG_USBD("USBD %s ", event.event_id < DCD_EVENT_COUNT ? _usbd_event_str[event.event_id] : "CORRUPTED"); #endif - switch ( event.event_id ) - { + switch (event.event_id) { case DCD_EVENT_BUS_RESET: TU_LOG_USBD(": %s Speed\r\n", tu_str_speed[event.bus_reset.speed]); usbd_reset(event.rhport); _usbd_dev.speed = event.bus_reset.speed; - break; + break; case DCD_EVENT_UNPLUGGED: TU_LOG_USBD("\r\n"); usbd_reset(event.rhport); - - // invoke callback if (tud_umount_cb) tud_umount_cb(); - break; + break; case DCD_EVENT_SETUP_RECEIVED: TU_LOG_BUF(CFG_TUD_LOG_LEVEL, &event.setup_received, 8); @@ -508,81 +491,72 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) // mark both in & out control as free _usbd_dev.ep_status[0][TUSB_DIR_OUT].busy = 0; _usbd_dev.ep_status[0][TUSB_DIR_OUT].claimed = 0; - _usbd_dev.ep_status[0][TUSB_DIR_IN ].busy = 0; - _usbd_dev.ep_status[0][TUSB_DIR_IN ].claimed = 0; + _usbd_dev.ep_status[0][TUSB_DIR_IN].busy = 0; + _usbd_dev.ep_status[0][TUSB_DIR_IN].claimed = 0; // Process control request - if ( !process_control_request(event.rhport, &event.setup_received) ) - { + if (!process_control_request(event.rhport, &event.setup_received)) { TU_LOG_USBD(" Stall EP0\r\n"); // Failed -> stall both control endpoint IN and OUT dcd_edpt_stall(event.rhport, 0); dcd_edpt_stall(event.rhport, 0 | TUSB_DIR_IN_MASK); } - break; + break; - case DCD_EVENT_XFER_COMPLETE: - { + case DCD_EVENT_XFER_COMPLETE: { // Invoke the class callback associated with the endpoint address uint8_t const ep_addr = event.xfer_complete.ep_addr; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const ep_dir = tu_edpt_dir(ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const ep_dir = tu_edpt_dir(ep_addr); TU_LOG_USBD("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len); _usbd_dev.ep_status[epnum][ep_dir].busy = 0; _usbd_dev.ep_status[epnum][ep_dir].claimed = 0; - if ( 0 == epnum ) - { - usbd_control_xfer_cb(event.rhport, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete - .len); - } - else - { - usbd_class_driver_t const * driver = get_driver( _usbd_dev.ep2drv[epnum][ep_dir] ); - TU_ASSERT(driver, ); + if (0 == epnum) { + usbd_control_xfer_cb(event.rhport, ep_addr, (xfer_result_t) event.xfer_complete.result, + event.xfer_complete.len); + } else { + usbd_class_driver_t const* driver = get_driver(_usbd_dev.ep2drv[epnum][ep_dir]); + TU_ASSERT(driver,); TU_LOG_USBD(" %s xfer callback\r\n", driver->name); driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len); } + break; } - break; case DCD_EVENT_SUSPEND: // NOTE: When plugging/unplugging device, the D+/D- state are unstable and // can accidentally meet the SUSPEND condition ( Bus Idle for 3ms ), which result in a series of event // e.g suspend -> resume -> unplug/plug. Skip suspend/resume if not connected - if ( _usbd_dev.connected ) - { + if (_usbd_dev.connected) { TU_LOG_USBD(": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en); if (tud_suspend_cb) tud_suspend_cb(_usbd_dev.remote_wakeup_en); - }else - { + } else { TU_LOG_USBD(" Skipped\r\n"); } - break; + break; case DCD_EVENT_RESUME: - if ( _usbd_dev.connected ) - { + if (_usbd_dev.connected) { TU_LOG_USBD("\r\n"); if (tud_resume_cb) tud_resume_cb(); - }else - { + } else { TU_LOG_USBD(" Skipped\r\n"); } - break; + break; case USBD_EVENT_FUNC_CALL: TU_LOG_USBD("\r\n"); - if ( event.func_call.func ) event.func_call.func(event.func_call.param); - break; + if (event.func_call.func) event.func_call.func(event.func_call.param); + break; case DCD_EVENT_SOF: default: TU_BREAKPOINT(); - break; + break; } #if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO @@ -597,8 +571,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) //--------------------------------------------------------------------+ // Helper to invoke class driver control request handler -static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * driver, tusb_control_request_t const * request) -{ +static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * driver, tusb_control_request_t const * request) { usbd_control_set_complete_callback(driver->control_xfer_cb); TU_LOG_USBD(" %s control request\r\n", driver->name); return driver->control_xfer_cb(rhport, CONTROL_STAGE_SETUP, request); @@ -606,15 +579,12 @@ static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * dri // This handles the actual request and its response. // return false will cause its caller to stall control endpoint -static bool process_control_request(uint8_t rhport, tusb_control_request_t const * p_request) -{ +static bool process_control_request(uint8_t rhport, tusb_control_request_t const * p_request) { usbd_control_set_complete_callback(NULL); - TU_ASSERT(p_request->bmRequestType_bit.type < TUSB_REQ_TYPE_INVALID); // Vendor request - if ( p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR ) - { + if ( p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR ) { TU_VERIFY(tud_vendor_control_xfer_cb); usbd_control_set_complete_callback(tud_vendor_control_xfer_cb); @@ -622,19 +592,16 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const } #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL - if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME) - { + if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME) { TU_LOG_USBD(" %s", tu_str_std_request[p_request->bRequest]); if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG_USBD("\r\n"); } #endif - switch ( p_request->bmRequestType_bit.recipient ) - { + switch ( p_request->bmRequestType_bit.recipient ) { //------------- Device Requests e.g in enumeration -------------// case TUSB_REQ_RCPT_DEVICE: - if ( TUSB_REQ_TYPE_CLASS == p_request->bmRequestType_bit.type ) - { + if ( TUSB_REQ_TYPE_CLASS == p_request->bmRequestType_bit.type ) { uint8_t const itf = tu_u16_low(p_request->wIndex); TU_VERIFY(itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv)); @@ -645,15 +612,13 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const return invoke_class_control(rhport, driver, p_request); } - if ( TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type ) - { + if ( TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type ) { // Non standard request is not supported TU_BREAKPOINT(); return false; } - switch ( p_request->bRequest ) - { + switch ( p_request->bRequest ) { case TUSB_REQ_SET_ADDRESS: // Depending on mcu, status phase could be sent either before or after changing device address, // or even require stack to not response with status at all @@ -664,22 +629,18 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const _usbd_dev.addressed = 1; break; - case TUSB_REQ_GET_CONFIGURATION: - { + case TUSB_REQ_GET_CONFIGURATION: { uint8_t cfg_num = _usbd_dev.cfg_num; tud_control_xfer(rhport, p_request, &cfg_num, 1); } break; - case TUSB_REQ_SET_CONFIGURATION: - { + case TUSB_REQ_SET_CONFIGURATION: { uint8_t const cfg_num = (uint8_t) p_request->wValue; // Only process if new configure is different - if (_usbd_dev.cfg_num != cfg_num) - { - if ( _usbd_dev.cfg_num ) - { + if (_usbd_dev.cfg_num != cfg_num) { + if ( _usbd_dev.cfg_num ) { // already configured: need to clear all endpoints and driver first TU_LOG_USBD(" Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num); @@ -694,15 +655,11 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const } // Handle the new configuration and execute the corresponding callback - if ( cfg_num ) - { + if ( cfg_num ) { // switch to new configuration if not zero TU_ASSERT( process_set_config(rhport, cfg_num) ); - if ( tud_mount_cb ) tud_mount_cb(); - } - else - { + } else { if ( tud_umount_cb ) tud_umount_cb(); } } @@ -738,15 +695,14 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const tud_control_status(rhport, p_request); break; - case TUSB_REQ_GET_STATUS: - { + case TUSB_REQ_GET_STATUS: { // Device status bit mask // - Bit 0: Self Powered // - Bit 1: Remote Wakeup enabled uint16_t status = (uint16_t) ((_usbd_dev.self_powered ? 1u : 0u) | (_usbd_dev.remote_wakeup_en ? 2u : 0u)); tud_control_xfer(rhport, p_request, &status, 2); + break; } - break; // Unknown/Unsupported request default: TU_BREAKPOINT(); return false; @@ -754,8 +710,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const break; //------------- Class/Interface Specific Request -------------// - case TUSB_REQ_RCPT_INTERFACE: - { + case TUSB_REQ_RCPT_INTERFACE: { uint8_t const itf = tu_u16_low(p_request->wIndex); TU_VERIFY(itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv)); @@ -764,25 +719,21 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const // all requests to Interface (STD or Class) is forwarded to class driver. // notable requests are: GET HID REPORT DESCRIPTOR, SET_INTERFACE, GET_INTERFACE - if ( !invoke_class_control(rhport, driver, p_request) ) - { + if ( !invoke_class_control(rhport, driver, p_request) ) { // For GET_INTERFACE and SET_INTERFACE, it is mandatory to respond even if the class // driver doesn't use alternate settings or implement this TU_VERIFY(TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type); - switch(p_request->bRequest) - { + switch(p_request->bRequest) { case TUSB_REQ_GET_INTERFACE: case TUSB_REQ_SET_INTERFACE: // Clear complete callback if driver set since it can also stall the request. usbd_control_set_complete_callback(NULL); - if (TUSB_REQ_GET_INTERFACE == p_request->bRequest) - { + if (TUSB_REQ_GET_INTERFACE == p_request->bRequest) { uint8_t alternate = 0; tud_control_xfer(rhport, p_request, &alternate, 1); - }else - { + }else { tud_control_status(rhport, p_request); } break; @@ -790,54 +741,42 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const default: return false; } } + break; } - break; //------------- Endpoint Request -------------// - case TUSB_REQ_RCPT_ENDPOINT: - { + case TUSB_REQ_RCPT_ENDPOINT: { uint8_t const ep_addr = tu_u16_low(p_request->wIndex); uint8_t const ep_num = tu_edpt_number(ep_addr); uint8_t const ep_dir = tu_edpt_dir(ep_addr); TU_ASSERT(ep_num < TU_ARRAY_SIZE(_usbd_dev.ep2drv) ); - usbd_class_driver_t const * driver = get_driver(_usbd_dev.ep2drv[ep_num][ep_dir]); - if ( TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type ) - { + if ( TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type ) { // Forward class request to its driver TU_VERIFY(driver); return invoke_class_control(rhport, driver, p_request); - } - else - { + } else { // Handle STD request to endpoint - switch ( p_request->bRequest ) - { - case TUSB_REQ_GET_STATUS: - { + switch ( p_request->bRequest ) { + case TUSB_REQ_GET_STATUS: { uint16_t status = usbd_edpt_stalled(rhport, ep_addr) ? 0x0001 : 0x0000; tud_control_xfer(rhport, p_request, &status, 2); } break; case TUSB_REQ_CLEAR_FEATURE: - case TUSB_REQ_SET_FEATURE: - { - if ( TUSB_REQ_FEATURE_EDPT_HALT == p_request->wValue ) - { - if ( TUSB_REQ_CLEAR_FEATURE == p_request->bRequest ) - { + case TUSB_REQ_SET_FEATURE: { + if ( TUSB_REQ_FEATURE_EDPT_HALT == p_request->wValue ) { + if ( TUSB_REQ_CLEAR_FEATURE == p_request->bRequest ) { usbd_edpt_clear_stall(rhport, ep_addr); - }else - { + }else { usbd_edpt_stall(rhport, ep_addr); } } - if (driver) - { + if (driver) { // Some classes such as USBTMC needs to clear/re-init its buffer when receiving CLEAR_FEATURE request // We will also forward std request targeted endpoint to class drivers as well @@ -853,14 +792,18 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const break; // Unknown/Unsupported request - default: TU_BREAKPOINT(); return false; + default: + TU_BREAKPOINT(); + return false; } } } break; // Unknown recipient - default: TU_BREAKPOINT(); return false; + default: + TU_BREAKPOINT(); + return false; } return true; @@ -1185,8 +1128,7 @@ void usbd_defer_func(osal_task_func_t func, void* param, bool in_isr) { // USBD Endpoint API //--------------------------------------------------------------------+ -bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) -{ +bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_ep) { rhport = _usbd_rhport; TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < CFG_TUD_ENDPPOINT_MAX); @@ -1195,37 +1137,34 @@ bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) return dcd_edpt_open(rhport, desc_ep); } -bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr) -{ +bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr) { (void) rhport; // TODO add this check later, also make sure we don't starve an out endpoint while suspending // TU_VERIFY(tud_ready()); - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); tu_edpt_state_t* ep_state = &_usbd_dev.ep_status[epnum][dir]; return tu_edpt_claim(ep_state, _usbd_mutex); } -bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr) -{ +bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr) { (void) rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); tu_edpt_state_t* ep_state = &_usbd_dev.ep_status[epnum][dir]; return tu_edpt_release(ep_state, _usbd_mutex); } -bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) -{ +bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { rhport = _usbd_rhport; uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); // TODO skip ready() check for now since enumeration also use this API // TU_VERIFY(tud_ready()); @@ -1239,11 +1178,9 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t // could return and USBD task can preempt and clear the busy _usbd_dev.ep_status[epnum][dir].busy = 1; - if ( dcd_edpt_xfer(rhport, ep_addr, buffer, total_bytes) ) - { + if (dcd_edpt_xfer(rhport, ep_addr, buffer, total_bytes)) { return true; - }else - { + } else { // DCD error, mark endpoint as ready to allow next transfer _usbd_dev.ep_status[epnum][dir].busy = 0; _usbd_dev.ep_status[epnum][dir].claimed = 0; @@ -1257,12 +1194,11 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t // bytes should be written and second to keep the return value free to give back a boolean // success message. If total_bytes is too big, the FIFO will copy only what is available // into the USB buffer! -bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) -{ +bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t total_bytes) { rhport = _usbd_rhport; uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); TU_LOG_USBD(" Queue ISO EP %02X with %u bytes ... ", ep_addr, total_bytes); @@ -1273,12 +1209,10 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 // and usbd task can preempt and clear the busy _usbd_dev.ep_status[epnum][dir].busy = 1; - if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes)) - { + if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes)) { TU_LOG_USBD("OK\r\n"); return true; - }else - { + } else { // DCD error, mark endpoint as ready to allow next transfer _usbd_dev.ep_status[epnum][dir].busy = 0; _usbd_dev.ep_status[epnum][dir].claimed = 0; @@ -1288,26 +1222,23 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 } } -bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr) -{ +bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr) { (void) rhport; uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); return _usbd_dev.ep_status[epnum][dir].busy; } -void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) -{ +void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { rhport = _usbd_rhport; uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); // only stalled if currently cleared - if ( !_usbd_dev.ep_status[epnum][dir].stalled ) - { + if (!_usbd_dev.ep_status[epnum][dir].stalled) { TU_LOG_USBD(" Stall EP %02X\r\n", ep_addr); dcd_edpt_stall(rhport, ep_addr); _usbd_dev.ep_status[epnum][dir].stalled = 1; @@ -1315,16 +1246,14 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) } } -void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) -{ +void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { rhport = _usbd_rhport; uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); // only clear if currently stalled - if ( _usbd_dev.ep_status[epnum][dir].stalled ) - { + if (_usbd_dev.ep_status[epnum][dir].stalled) { TU_LOG_USBD(" Clear Stall EP %02X\r\n", ep_addr); dcd_edpt_clear_stall(rhport, ep_addr); _usbd_dev.ep_status[epnum][dir].stalled = 0; @@ -1332,31 +1261,27 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) } } -bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr) -{ +bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr) { (void) rhport; uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); return _usbd_dev.ep_status[epnum][dir].stalled; } /** * usbd_edpt_close will disable an endpoint. - * * In progress transfers on this EP may be delivered after this call. - * */ -void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr) -{ +void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr) { rhport = _usbd_rhport; TU_ASSERT(dcd_edpt_close, /**/); TU_LOG_USBD(" CLOSING Endpoint: 0x%02X\r\n", ep_addr); uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); dcd_edpt_close(rhport, ep_addr); _usbd_dev.ep_status[epnum][dir].stalled = 0; @@ -1366,8 +1291,7 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr) return; } -void usbd_sof_enable(uint8_t rhport, bool en) -{ +void usbd_sof_enable(uint8_t rhport, bool en) { rhport = _usbd_rhport; // TODO: Check needed if all drivers including the user sof_cb does not need an active SOF ISR any more. @@ -1375,8 +1299,7 @@ void usbd_sof_enable(uint8_t rhport, bool en) dcd_sof_enable(rhport, en); } -bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) -{ +bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { rhport = _usbd_rhport; TU_ASSERT(dcd_edpt_iso_alloc); @@ -1385,12 +1308,11 @@ bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packe return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size); } -bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) -{ +bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const* desc_ep) { rhport = _usbd_rhport; uint8_t const epnum = tu_edpt_number(desc_ep->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(desc_ep->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(desc_ep->bEndpointAddress); TU_ASSERT(dcd_edpt_iso_activate); TU_ASSERT(epnum < CFG_TUD_ENDPPOINT_MAX); diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index e8cee73fd..ba7e9f912 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -48,7 +48,7 @@ *------------------------------------------------------------------*/ // Init these in dcd_init -static uint8_t *next_buffer_ptr; +static uint8_t* next_buffer_ptr; // USB_MAX_ENDPOINTS Endpoints, direction TUSB_DIR_OUT for out and TUSB_DIR_IN for in. static struct hw_endpoint hw_endpoints[USB_MAX_ENDPOINTS][2]; @@ -56,79 +56,70 @@ static struct hw_endpoint hw_endpoints[USB_MAX_ENDPOINTS][2]; // SOF may be used by remote wakeup as RESUME, this indicate whether SOF is actually used by usbd static bool _sof_enable = false; -TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint *hw_endpoint_get_by_num(uint8_t num, tusb_dir_t dir) -{ +TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint* hw_endpoint_get_by_num(uint8_t num, tusb_dir_t dir) { return &hw_endpoints[num][dir]; } -static struct hw_endpoint *hw_endpoint_get_by_addr(uint8_t ep_addr) -{ +static struct hw_endpoint* hw_endpoint_get_by_addr(uint8_t ep_addr) { uint8_t num = tu_edpt_number(ep_addr); tusb_dir_t dir = tu_edpt_dir(ep_addr); return hw_endpoint_get_by_num(num, dir); } -static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type) -{ +static void _hw_endpoint_alloc(struct hw_endpoint* ep, uint8_t transfer_type) { // size must be multiple of 64 uint size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u; // double buffered Bulk endpoint - if ( transfer_type == TUSB_XFER_BULK ) - { + if (transfer_type == TUSB_XFER_BULK) { size *= 2u; } ep->hw_data_buf = next_buffer_ptr; next_buffer_ptr += size; - assert(((uintptr_t )next_buffer_ptr & 0b111111u) == 0); + assert(((uintptr_t) next_buffer_ptr & 0b111111u) == 0); uint dpram_offset = hw_data_offset(ep->hw_data_buf); hard_assert(hw_data_offset(next_buffer_ptr) <= USB_DPRAM_MAX); pico_info(" Allocated %d bytes at offset 0x%x (0x%p)\r\n", size, dpram_offset, ep->hw_data_buf); // Fill in endpoint control register with buffer offset - uint32_t const reg = EP_CTRL_ENABLE_BITS | ((uint)transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset; + uint32_t const reg = EP_CTRL_ENABLE_BITS | ((uint) transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset; *ep->endpoint_control = reg; } -static void _hw_endpoint_close(struct hw_endpoint *ep) -{ - // Clear hardware registers and then zero the struct - // Clears endpoint enable - *ep->endpoint_control = 0; - // Clears buffer available, etc - *ep->buffer_control = 0; - // Clear any endpoint state - memset(ep, 0, sizeof(struct hw_endpoint)); - - // Reclaim buffer space if all endpoints are closed - bool reclaim_buffers = true; - for ( uint8_t i = 1; i < USB_MAX_ENDPOINTS; i++ ) - { - if (hw_endpoint_get_by_num(i, TUSB_DIR_OUT)->hw_data_buf != NULL || hw_endpoint_get_by_num(i, TUSB_DIR_IN)->hw_data_buf != NULL) - { - reclaim_buffers = false; - break; - } - } - if (reclaim_buffers) - { - next_buffer_ptr = &usb_dpram->epx_data[0]; +static void _hw_endpoint_close(struct hw_endpoint* ep) { + // Clear hardware registers and then zero the struct + // Clears endpoint enable + *ep->endpoint_control = 0; + // Clears buffer available, etc + *ep->buffer_control = 0; + // Clear any endpoint state + memset(ep, 0, sizeof(struct hw_endpoint)); + + // Reclaim buffer space if all endpoints are closed + bool reclaim_buffers = true; + for (uint8_t i = 1; i < USB_MAX_ENDPOINTS; i++) { + if (hw_endpoint_get_by_num(i, TUSB_DIR_OUT)->hw_data_buf != NULL || + hw_endpoint_get_by_num(i, TUSB_DIR_IN)->hw_data_buf != NULL) { + reclaim_buffers = false; + break; } + } + if (reclaim_buffers) { + next_buffer_ptr = &usb_dpram->epx_data[0]; + } } -static void hw_endpoint_close(uint8_t ep_addr) -{ - struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr); - _hw_endpoint_close(ep); +static void hw_endpoint_close(uint8_t ep_addr) { + struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); + _hw_endpoint_close(ep); } -static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type) -{ - struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr); +static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type) { + struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); const uint8_t num = tu_edpt_number(ep_addr); const tusb_dir_t dir = tu_edpt_dir(ep_addr); @@ -143,35 +134,26 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t ep->transfer_type = transfer_type; // Every endpoint has a buffer control register in dpram - if ( dir == TUSB_DIR_IN ) - { + if (dir == TUSB_DIR_IN) { ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].in; - } - else - { + } else { ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].out; } // Clear existing buffer control state *ep->buffer_control = 0; - if ( num == 0 ) - { + if (num == 0) { // EP0 has no endpoint control register because the buffer offsets are fixed ep->endpoint_control = NULL; // Buffer offset is fixed (also double buffered) ep->hw_data_buf = (uint8_t*) &usb_dpram->ep0_buf_a[0]; - } - else - { + } else { // Set the endpoint control register (starts at EP1, hence num-1) - if ( dir == TUSB_DIR_IN ) - { + if (dir == TUSB_DIR_IN) { ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].in; - } - else - { + } else { ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].out; } @@ -180,76 +162,65 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t } } -static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) -{ - struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr); - hw_endpoint_xfer_start(ep, buffer, total_bytes); +static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { + struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); + hw_endpoint_xfer_start(ep, buffer, total_bytes); } -static void __tusb_irq_path_func(hw_handle_buff_status)(void) -{ - uint32_t remaining_buffers = usb_hw->buf_status; - pico_trace("buf_status = 0x%08lx\r\n", remaining_buffers); - uint bit = 1u; - for (uint8_t i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++) - { - if (remaining_buffers & bit) - { - // clear this in advance - usb_hw_clear->buf_status = bit; - - // IN transfer for even i, OUT transfer for odd i - struct hw_endpoint *ep = hw_endpoint_get_by_num(i >> 1u, (i & 1u) ? TUSB_DIR_OUT : TUSB_DIR_IN); - - // Continue xfer - bool done = hw_endpoint_xfer_continue(ep); - if (done) - { - // Notify - dcd_event_xfer_complete(0, ep->ep_addr, ep->xferred_len, XFER_RESULT_SUCCESS, true); - hw_endpoint_reset_transfer(ep); - } - remaining_buffers &= ~bit; - } - bit <<= 1u; +static void __tusb_irq_path_func(hw_handle_buff_status)(void) { + uint32_t remaining_buffers = usb_hw->buf_status; + pico_trace("buf_status = 0x%08lx\r\n", remaining_buffers); + uint bit = 1u; + for (uint8_t i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++) { + if (remaining_buffers & bit) { + // clear this in advance + usb_hw_clear->buf_status = bit; + + // IN transfer for even i, OUT transfer for odd i + struct hw_endpoint* ep = hw_endpoint_get_by_num(i >> 1u, (i & 1u) ? TUSB_DIR_OUT : TUSB_DIR_IN); + + // Continue xfer + bool done = hw_endpoint_xfer_continue(ep); + if (done) { + // Notify + dcd_event_xfer_complete(0, ep->ep_addr, ep->xferred_len, XFER_RESULT_SUCCESS, true); + hw_endpoint_reset_transfer(ep); + } + remaining_buffers &= ~bit; } + bit <<= 1u; + } } -TU_ATTR_ALWAYS_INLINE static inline void reset_ep0_pid(void) -{ - // If we have finished this transfer on EP0 set pid back to 1 for next - // setup transfer. Also clear a stall in case - uint8_t addrs[] = {0x0, 0x80}; - for (uint i = 0 ; i < TU_ARRAY_SIZE(addrs); i++) - { - struct hw_endpoint *ep = hw_endpoint_get_by_addr(addrs[i]); - ep->next_pid = 1u; - } +TU_ATTR_ALWAYS_INLINE static inline void reset_ep0_pid(void) { + // If we have finished this transfer on EP0 set pid back to 1 for next + // setup transfer. Also clear a stall in case + uint8_t addrs[] = {0x0, 0x80}; + for (uint i = 0; i < TU_ARRAY_SIZE(addrs); i++) { + struct hw_endpoint* ep = hw_endpoint_get_by_addr(addrs[i]); + ep->next_pid = 1u; + } } -static void __tusb_irq_path_func(reset_non_control_endpoints)(void) -{ +static void __tusb_irq_path_func(reset_non_control_endpoints)(void) { // Disable all non-control - for ( uint8_t i = 0; i < USB_MAX_ENDPOINTS-1; i++ ) - { + for (uint8_t i = 0; i < USB_MAX_ENDPOINTS - 1; i++) { usb_dpram->ep_ctrl[i].in = 0; usb_dpram->ep_ctrl[i].out = 0; } // clear non-control hw endpoints - tu_memclr(hw_endpoints[1], sizeof(hw_endpoints) - 2*sizeof(hw_endpoint_t)); + tu_memclr(hw_endpoints[1], sizeof(hw_endpoints) - 2 * sizeof(hw_endpoint_t)); // reclaim buffer space next_buffer_ptr = &usb_dpram->epx_data[0]; } -static void __tusb_irq_path_func(dcd_rp2040_irq)(void) -{ +static void __tusb_irq_path_func(dcd_rp2040_irq)(void) { uint32_t const status = usb_hw->ints; uint32_t handled = 0; - if ( status & USB_INTF_DEV_SOF_BITS ) - { + if (status & USB_INTF_DEV_SOF_BITS) { bool keep_sof_alive = false; handled |= USB_INTF_DEV_SOF_BITS; @@ -258,20 +229,17 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) // Errata 15 workaround for Device Bulk-In endpoint e15_last_sof = time_us_32(); - for ( uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++ ) - { - struct hw_endpoint * ep = hw_endpoint_get_by_num(i, TUSB_DIR_IN); + for (uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++) { + struct hw_endpoint* ep = hw_endpoint_get_by_num(i, TUSB_DIR_IN); // Active Bulk IN endpoint requires SOF - if ( (ep->transfer_type == TUSB_XFER_BULK) && ep->active ) - { + if ((ep->transfer_type == TUSB_XFER_BULK) && ep->active) { keep_sof_alive = true; hw_endpoint_lock_update(ep, 1); // Deferred enable? - if ( ep->pending ) - { + if (ep->pending) { ep->pending = 0; hw_endpoint_start_next_buffer(ep); } @@ -282,23 +250,21 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) #endif // disable SOF interrupt if it is used for RESUME in remote wakeup - if ( !keep_sof_alive && !_sof_enable ) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS; + if (!keep_sof_alive && !_sof_enable) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS; dcd_event_sof(0, usb_hw->sof_rd & USB_SOF_RD_BITS, true); } // xfer events are handled before setup req. So if a transfer completes immediately // before closing the EP, the events will be delivered in same order. - if ( status & USB_INTS_BUFF_STATUS_BITS ) - { + if (status & USB_INTS_BUFF_STATUS_BITS) { handled |= USB_INTS_BUFF_STATUS_BITS; hw_handle_buff_status(); } - if ( status & USB_INTS_SETUP_REQ_BITS ) - { + if (status & USB_INTS_SETUP_REQ_BITS) { handled |= USB_INTS_SETUP_REQ_BITS; - uint8_t const * setup = remove_volatile_cast(uint8_t const*, &usb_dpram->setup_packet); + uint8_t const* setup = remove_volatile_cast(uint8_t const*, &usb_dpram->setup_packet); // reset pid to both 1 (data and ack) reset_ep0_pid(); @@ -329,8 +295,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) #endif // SE0 for 2.5 us or more (will last at least 10ms) - if ( status & USB_INTS_BUS_RESET_BITS ) - { + if (status & USB_INTS_BUS_RESET_BITS) { pico_trace("BUS RESET\r\n"); handled |= USB_INTS_BUS_RESET_BITS; @@ -342,7 +307,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) #if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX // Only run enumeration workaround if pull up is enabled - if ( usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS ) rp2040_usb_device_enumeration_fix(); + if (usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS) rp2040_usb_device_enumeration_fix(); #endif } @@ -354,22 +319,19 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) * because without VBUS detection, it is impossible to tell the difference between * being disconnected and suspended. */ - if ( status & USB_INTS_DEV_SUSPEND_BITS ) - { + if (status & USB_INTS_DEV_SUSPEND_BITS) { handled |= USB_INTS_DEV_SUSPEND_BITS; dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); usb_hw_clear->sie_status = USB_SIE_STATUS_SUSPENDED_BITS; } - if ( status & USB_INTS_DEV_RESUME_FROM_HOST_BITS ) - { + if (status & USB_INTS_DEV_RESUME_FROM_HOST_BITS) { handled |= USB_INTS_DEV_RESUME_FROM_HOST_BITS; dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); usb_hw_clear->sie_status = USB_SIE_STATUS_RESUME_BITS; } - if ( status ^ handled ) - { + if (status ^ handled) { panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled)); } } @@ -390,8 +352,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) #define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff #endif -void dcd_init (uint8_t rhport) -{ +void dcd_init(uint8_t rhport) { assert(rhport == 0); // Reset hardware to default state @@ -405,7 +366,7 @@ void dcd_init (uint8_t rhport) irq_add_shared_handler(USBCTRL_IRQ, dcd_rp2040_irq, PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY); // Init control endpoints - tu_memclr(hw_endpoints[0], 2*sizeof(hw_endpoint_t)); + tu_memclr(hw_endpoints[0], 2 * sizeof(hw_endpoint_t)); hw_endpoint_init(0x0, 64, TUSB_XFER_CONTROL); hw_endpoint_init(0x80, 64, TUSB_XFER_CONTROL); @@ -420,27 +381,24 @@ void dcd_init (uint8_t rhport) // for the global interrupt enable... // Note: Force VBUS detect cause disconnection not detectable usb_hw->sie_ctrl = USB_SIE_CTRL_EP0_INT_1BUF_BITS; - usb_hw->inte = USB_INTS_BUFF_STATUS_BITS | USB_INTS_BUS_RESET_BITS | USB_INTS_SETUP_REQ_BITS | - USB_INTS_DEV_SUSPEND_BITS | USB_INTS_DEV_RESUME_FROM_HOST_BITS | - (FORCE_VBUS_DETECT ? 0 : USB_INTS_DEV_CONN_DIS_BITS); + usb_hw->inte = USB_INTS_BUFF_STATUS_BITS | USB_INTS_BUS_RESET_BITS | USB_INTS_SETUP_REQ_BITS | + USB_INTS_DEV_SUSPEND_BITS | USB_INTS_DEV_RESUME_FROM_HOST_BITS | + (FORCE_VBUS_DETECT ? 0 : USB_INTS_DEV_CONN_DIS_BITS); dcd_connect(rhport); } -void dcd_int_enable(__unused uint8_t rhport) -{ - assert(rhport == 0); - irq_set_enabled(USBCTRL_IRQ, true); +void dcd_int_enable(__unused uint8_t rhport) { + assert(rhport == 0); + irq_set_enabled(USBCTRL_IRQ, true); } -void dcd_int_disable(__unused uint8_t rhport) -{ - assert(rhport == 0); - irq_set_enabled(USBCTRL_IRQ, false); +void dcd_int_disable(__unused uint8_t rhport) { + assert(rhport == 0); + irq_set_enabled(USBCTRL_IRQ, false); } -void dcd_set_address (__unused uint8_t rhport, __unused uint8_t dev_addr) -{ +void dcd_set_address(__unused uint8_t rhport, __unused uint8_t dev_addr) { assert(rhport == 0); // Can't set device address in hardware until status xfer has complete @@ -448,8 +406,7 @@ void dcd_set_address (__unused uint8_t rhport, __unused uint8_t dev_addr) hw_endpoint_xfer(0x80, NULL, 0); } -void dcd_remote_wakeup(__unused uint8_t rhport) -{ +void dcd_remote_wakeup(__unused uint8_t rhport) { pico_info("dcd_remote_wakeup %d\n", rhport); assert(rhport == 0); @@ -460,100 +417,88 @@ void dcd_remote_wakeup(__unused uint8_t rhport) } // disconnect by disabling internal pull-up resistor on D+/D- -void dcd_disconnect(__unused uint8_t rhport) -{ +void dcd_disconnect(__unused uint8_t rhport) { (void) rhport; usb_hw_clear->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS; } // connect by enabling internal pull-up resistor on D+/D- -void dcd_connect(__unused uint8_t rhport) -{ +void dcd_connect(__unused uint8_t rhport) { (void) rhport; usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS; } -void dcd_sof_enable(uint8_t rhport, bool en) -{ +void dcd_sof_enable(uint8_t rhport, bool en) { (void) rhport; _sof_enable = en; - if (en) - { + if (en) { usb_hw_set->inte = USB_INTS_DEV_SOF_BITS; - }else - { + } +#if !TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX + else { // Don't clear immediately if the SOF workaround is in use. // The SOF handler will conditionally disable the interrupt. -#if !TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS; -#endif } +#endif } /*------------------------------------------------------------------*/ /* DCD Endpoint port *------------------------------------------------------------------*/ -void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) -{ +void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* request) { (void) rhport; - if ( request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && - request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && - request->bRequest == TUSB_REQ_SET_ADDRESS ) - { + if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && + request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && + request->bRequest == TUSB_REQ_SET_ADDRESS) { usb_hw->dev_addr_ctrl = (uint8_t) request->wValue; } } -bool dcd_edpt_open (__unused uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) -{ - assert(rhport == 0); - hw_endpoint_init(desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt), desc_edpt->bmAttributes.xfer); - return true; +bool dcd_edpt_open(__unused uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) { + assert(rhport == 0); + hw_endpoint_init(desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt), desc_edpt->bmAttributes.xfer); + return true; } -void dcd_edpt_close_all (uint8_t rhport) -{ +void dcd_edpt_close_all(uint8_t rhport) { (void) rhport; // may need to use EP Abort reset_non_control_endpoints(); } -bool dcd_edpt_xfer(__unused uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) -{ - assert(rhport == 0); - hw_endpoint_xfer(ep_addr, buffer, total_bytes); - return true; +bool dcd_edpt_xfer(__unused uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { + assert(rhport == 0); + hw_endpoint_xfer(ep_addr, buffer, total_bytes); + return true; } -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) -{ +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { (void) rhport; - if ( tu_edpt_number(ep_addr) == 0 ) - { + if (tu_edpt_number(ep_addr) == 0) { // A stall on EP0 has to be armed so it can be cleared on the next setup packet - usb_hw_set->ep_stall_arm = (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) ? USB_EP_STALL_ARM_EP0_IN_BITS : USB_EP_STALL_ARM_EP0_OUT_BITS; + usb_hw_set->ep_stall_arm = (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) ? USB_EP_STALL_ARM_EP0_IN_BITS + : USB_EP_STALL_ARM_EP0_OUT_BITS; } - struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr); + struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); // stall and clear current pending buffer // may need to use EP_ABORT _hw_endpoint_buffer_control_set_value32(ep, USB_BUF_CTRL_STALL); } -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) -{ +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { (void) rhport; - if (tu_edpt_number(ep_addr)) - { - struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr); + if (tu_edpt_number(ep_addr)) { + struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); // clear stall also reset toggle to DATA0, ready for next transfer ep->next_pid = 0; @@ -561,16 +506,13 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) } } -void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) -{ - (void) rhport; - - pico_trace("dcd_edpt_close %02x\r\n", ep_addr); - hw_endpoint_close(ep_addr); +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; + pico_trace("dcd_edpt_close %02x\r\n", ep_addr); + hw_endpoint_close(ep_addr); } -void __tusb_irq_path_func(dcd_int_handler)(uint8_t rhport) -{ +void __tusb_irq_path_func(dcd_int_handler)(uint8_t rhport) { (void) rhport; dcd_rp2040_irq(); } diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index a512dc34f..b5bace972 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -37,24 +37,23 @@ //--------------------------------------------------------------------+ // Direction strings for debug -const char *ep_dir_string[] = { - "out", - "in", +const char* ep_dir_string[] = { + "out", + "in", }; -static void _hw_endpoint_xfer_sync(struct hw_endpoint *ep); +static void _hw_endpoint_xfer_sync(struct hw_endpoint* ep); #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX - static bool e15_is_bulkin_ep(struct hw_endpoint *ep); - static bool e15_is_critical_frame_period(struct hw_endpoint *ep); + static bool e15_is_bulkin_ep(struct hw_endpoint* ep); + static bool e15_is_critical_frame_period(struct hw_endpoint* ep); #else #define e15_is_bulkin_ep(x) (false) #define e15_is_critical_frame_period(x) (false) #endif // if usb hardware is in host mode -TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void) -{ +TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void) { return (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) ? true : false; } @@ -62,8 +61,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void) // Implementation //--------------------------------------------------------------------+ -void rp2040_usb_init(void) -{ +void rp2040_usb_init(void) { // Reset usb controller reset_block(RESETS_RESET_USBCTRL_BITS); unreset_block_wait(RESETS_RESET_USBCTRL_BITS); @@ -88,45 +86,40 @@ void rp2040_usb_init(void) TU_LOG2_INT(sizeof(hw_endpoint_t)); } -void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep) -{ +void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint* ep) { ep->active = false; ep->remaining_len = 0; ep->xferred_len = 0; ep->user_buf = 0; } -void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask) -{ +void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint* ep, uint32_t and_mask, + uint32_t or_mask) { uint32_t value = 0; - if ( and_mask ) - { + if (and_mask) { value = *ep->buffer_control & and_mask; } - if ( or_mask ) - { + if (or_mask) { value |= or_mask; - if ( or_mask & USB_BUF_CTRL_AVAIL ) - { - if ( *ep->buffer_control & USB_BUF_CTRL_AVAIL ) - { + if (or_mask & USB_BUF_CTRL_AVAIL) { + if (*ep->buffer_control & USB_BUF_CTRL_AVAIL) { panic("ep %d %s was already available", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]); } *ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL; // 12 cycle delay.. (should be good for 48*12Mhz = 576Mhz) // Don't need delay in host mode as host is in charge #if !CFG_TUH_ENABLED - __asm volatile ( - "b 1f\n" - "1: b 1f\n" - "1: b 1f\n" - "1: b 1f\n" - "1: b 1f\n" - "1: b 1f\n" - "1:\n" - : : : "memory"); + __asm volatile ( + "b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1:\n" + : : : "memory"); #endif } } @@ -135,10 +128,9 @@ void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoi } // prepare buffer, return buffer control -static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep, uint8_t buf_id) -{ +static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint* ep, uint8_t buf_id) { uint16_t const buflen = tu_min16(ep->remaining_len, ep->wMaxPacketSize); - ep->remaining_len = (uint16_t)(ep->remaining_len - buflen); + ep->remaining_len = (uint16_t) (ep->remaining_len - buflen); uint32_t buf_ctrl = buflen | USB_BUF_CTRL_AVAIL; @@ -146,10 +138,9 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep, buf_ctrl |= ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID; ep->next_pid ^= 1u; - if ( !ep->rx ) - { + if (!ep->rx) { // Copy data from user buffer to hw buffer - memcpy(ep->hw_data_buf + buf_id*64, ep->user_buf, buflen); + memcpy(ep->hw_data_buf + buf_id * 64, ep->user_buf, buflen); ep->user_buf += buflen; // Mark as full @@ -159,8 +150,7 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep, // Is this the last buffer? Only really matters for host mode. Will trigger // the trans complete irq but also stop it polling. We only really care about // trans complete for setup packets being sent - if (ep->remaining_len == 0) - { + if (ep->remaining_len == 0) { buf_ctrl |= USB_BUF_CTRL_LAST; } @@ -170,8 +160,7 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep, } // Prepare buffer control register value -void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint *ep) -{ +void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint* ep) { uint32_t ep_ctrl = *ep->endpoint_control; // always compute and start with buffer 0 @@ -186,8 +175,7 @@ void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint *ep) bool const force_single = (!is_host && !tu_edpt_dir(ep->ep_addr)) || (is_host && tu_edpt_number(ep->ep_addr) != 0); - if(ep->remaining_len && !force_single) - { + if (ep->remaining_len && !force_single) { // Use buffer 1 (double buffered) if there is still data // TODO: Isochronous for buffer1 bit-field is different than CBI (control bulk, interrupt) @@ -196,8 +184,7 @@ void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint *ep) // Set endpoint control double buffered bit if needed ep_ctrl &= ~EP_CTRL_INTERRUPT_PER_BUFFER; ep_ctrl |= EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER; - }else - { + } else { // Single buffered since 1 is enough ep_ctrl &= ~(EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER); ep_ctrl |= EP_CTRL_INTERRUPT_PER_BUFFER; @@ -212,35 +199,30 @@ void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint *ep) _hw_endpoint_buffer_control_set_value32(ep, buf_ctrl); } -void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len) -{ +void hw_endpoint_xfer_start(struct hw_endpoint* ep, uint8_t* buffer, uint16_t total_len) { hw_endpoint_lock_update(ep, 1); - if ( ep->active ) - { + if (ep->active) { // TODO: Is this acceptable for interrupt packets? TU_LOG(1, "WARN: starting new transfer on already active ep %d %s\r\n", tu_edpt_number(ep->ep_addr), - ep_dir_string[tu_edpt_dir(ep->ep_addr)]); + ep_dir_string[tu_edpt_dir(ep->ep_addr)]); hw_endpoint_reset_transfer(ep); } // Fill in info now that we're kicking off the hw ep->remaining_len = total_len; - ep->xferred_len = 0; - ep->active = true; - ep->user_buf = buffer; + ep->xferred_len = 0; + ep->active = true; + ep->user_buf = buffer; - if ( e15_is_bulkin_ep(ep) ) - { + if (e15_is_bulkin_ep(ep)) { usb_hw_set->inte = USB_INTS_DEV_SOF_BITS; } - if ( e15_is_critical_frame_period(ep) ) - { + if (e15_is_critical_frame_period(ep)) { ep->pending = 1; - } else - { + } else { hw_endpoint_start_next_buffer(ep); } @@ -248,34 +230,30 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to } // sync endpoint buffer and return transferred bytes -static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint *ep, uint8_t buf_id) -{ +static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint* ep, uint8_t buf_id) { uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep); - if (buf_id) buf_ctrl = buf_ctrl >> 16; + if (buf_id) buf_ctrl = buf_ctrl >> 16; uint16_t xferred_bytes = buf_ctrl & USB_BUF_CTRL_LEN_MASK; - if ( !ep->rx ) - { + if (!ep->rx) { // We are continuing a transfer here. If we are TX, we have successfully // sent some data can increase the length we have sent assert(!(buf_ctrl & USB_BUF_CTRL_FULL)); - ep->xferred_len = (uint16_t)(ep->xferred_len + xferred_bytes); - }else - { + ep->xferred_len = (uint16_t) (ep->xferred_len + xferred_bytes); + } else { // If we have received some data, so can increase the length // we have received AFTER we have copied it to the user buffer at the appropriate offset assert(buf_ctrl & USB_BUF_CTRL_FULL); - memcpy(ep->user_buf, ep->hw_data_buf + buf_id*64, xferred_bytes); - ep->xferred_len = (uint16_t)(ep->xferred_len + xferred_bytes); + memcpy(ep->user_buf, ep->hw_data_buf + buf_id * 64, xferred_bytes); + ep->xferred_len = (uint16_t) (ep->xferred_len + xferred_bytes); ep->user_buf += xferred_bytes; } // Short packet - if (xferred_bytes < ep->wMaxPacketSize) - { + if (xferred_bytes < ep->wMaxPacketSize) { pico_trace(" Short packet on buffer %d with %u bytes\r\n", buf_id, xferred_bytes); // Reduce total length as this is last packet ep->remaining_len = 0; @@ -284,8 +262,7 @@ static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint *ep, uin return xferred_bytes; } -static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep) -{ +static void __tusb_irq_path_func(_hw_endpoint_xfer_sync)(struct hw_endpoint* ep) { // Update hw endpoint struct with info from hardware // after a buff status interrupt @@ -296,14 +273,11 @@ static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep uint16_t buf0_bytes = sync_ep_buffer(ep, 0); // sync buffer 1 if double buffered - if ( (*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS ) - { - if (buf0_bytes == ep->wMaxPacketSize) - { + if ((*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS) { + if (buf0_bytes == ep->wMaxPacketSize) { // sync buffer 1 if not short packet sync_ep_buffer(ep, 1); - }else - { + } else { // short packet on buffer 0 // TODO couldn't figure out how to handle this case which happen with net_lwip_webserver example // At this time (currently trigger per 2 buffer), the buffer1 is probably filled with data from @@ -335,14 +309,13 @@ static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep } // Returns true if transfer is complete -bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep) -{ +bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint* ep) { hw_endpoint_lock_update(ep, 1); // Part way through a transfer - if (!ep->active) - { - panic("Can't continue xfer on inactive ep %d %s", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]); + if (!ep->active) { + panic("Can't continue xfer on inactive ep %d %s", tu_edpt_number(ep->ep_addr), + ep_dir_string[tu_edpt_dir(ep->ep_addr)]); } // Update EP struct from hardware state @@ -350,21 +323,16 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep) // Now we have synced our state with the hardware. Is there more data to transfer? // If we are done then notify tinyusb - if (ep->remaining_len == 0) - { + if (ep->remaining_len == 0) { pico_trace("Completed transfer of %d bytes on ep %d %s\r\n", ep->xferred_len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]); // Notify caller we are done so it can notify the tinyusb stack hw_endpoint_lock_update(ep, -1); return true; - } - else - { - if ( e15_is_critical_frame_period(ep) ) - { + } else { + if (e15_is_critical_frame_period(ep)) { ep->pending = 1; - } else - { + } else { hw_endpoint_start_next_buffer(ep); } } @@ -399,16 +367,14 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep) volatile uint32_t e15_last_sof = 0; // check if Errata 15 is needed for this endpoint i.e device bulk-in -static bool __tusb_irq_path_func(e15_is_bulkin_ep) (struct hw_endpoint *ep) -{ +static bool __tusb_irq_path_func(e15_is_bulkin_ep)(struct hw_endpoint* ep) { return (!is_host_mode() && tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN && ep->transfer_type == TUSB_XFER_BULK); } // check if we need to apply Errata 15 workaround : i.e // Endpoint is BULK IN and is currently in critical frame period i.e 20% of last usb frame -static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoint *ep) -{ +static bool __tusb_irq_path_func(e15_is_critical_frame_period)(struct hw_endpoint* ep) { TU_VERIFY(e15_is_bulkin_ep(ep)); /* Avoid the last 200us (uframe 6.5-7) of a frame, up to the EOF2 point. @@ -419,11 +385,10 @@ static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoi if (delta < 800 || delta > 998) { return false; } - TU_LOG(3, "Avoiding sof %lu now %lu last %lu\r\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof); + TU_LOG(3, "Avoiding sof %lu now %lu last %lu\r\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), + e15_last_sof); return true; } -#endif - - +#endif // TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX #endif -- cgit v1.3.1 From 6dc714b6de8eaa58e4239f831786d383b7f9bb86 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 13 Mar 2024 11:41:58 +0700 Subject: - only abort ep0 if it is active - rename reset_ep0_pid() to reset_ep0() - minor update log message --- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 70 +++++++++++----------------- src/portable/raspberrypi/rp2040/rp2040_usb.c | 35 ++++---------- 2 files changed, 36 insertions(+), 69 deletions(-) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 0e9dd84e5..5c564cb1c 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -60,7 +60,7 @@ TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint* hw_endpoint_get_by_num(u return &hw_endpoints[num][dir]; } -static struct hw_endpoint* hw_endpoint_get_by_addr(uint8_t ep_addr) { +TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint* hw_endpoint_get_by_addr(uint8_t ep_addr) { uint8_t num = tu_edpt_number(ep_addr); tusb_dir_t dir = tu_edpt_dir(ep_addr); return hw_endpoint_get_by_num(num, dir); @@ -192,47 +192,31 @@ static void __tusb_irq_path_func(hw_handle_buff_status)(void) { } } -TU_ATTR_ALWAYS_INLINE static inline void reset_ep0_pid(void) -{ - // Abort any transactions from a prior control transfer, because - // receiving SETUP doesn't reset buffer control state. This works around - // a possible USB hardware erratum. - - // With this workaround a race window still exists, but smaller. - // ABORT flag is unusable prior to hardware B2 (RP2040-E2), so a larger - // race window exists for B1 and earlier. - if (rp2040_chip_version() >= 2) { - usb_hw_set->abort = 0x3; - while ((usb_hw->abort_done & 0x3) != 0x3) - ; - } - // If we have finished this transfer on EP0 set pid back to 1 for next - // setup transfer. Also clear a stall in case - uint8_t addrs[] = {0x0, 0x80}; - for (uint i = 0 ; i < TU_ARRAY_SIZE(addrs); i++) - { - struct hw_endpoint *ep = hw_endpoint_get_by_addr(addrs[i]); - ep->next_pid = 1u; - // Reset the buffer control now to minimize race conditions - _hw_endpoint_buffer_control_set_value32(ep, USB_BUF_CTRL_DATA1_PID | USB_BUF_CTRL_SEL); - // Explicit delay, because the one in - // _hw_endpoint_buffer_control_set_value32 is only to set AVAILABLE - __asm volatile ( - "b 1f\n" - "1: b 1f\n" - "1: b 1f\n" - "1: b 1f\n" - "1: b 1f\n" - "1: b 1f\n" - "1:\n" - : : : "memory"); - // Make sure local ep state matches peripheral - hw_endpoint_reset_transfer(ep); - } - if (rp2040_chip_version() >= 2) { - usb_hw_clear->abort = 0x3; - usb_hw_clear->abort_done = 0x3; +TU_ATTR_ALWAYS_INLINE static inline void reset_ep0(void) { + // If we have finished this transfer on EP0 set pid back to 1 for next + // setup transfer. Also clear a stall in case + for (uint8_t dir = 0; dir < 2; dir++) { + struct hw_endpoint* ep = hw_endpoint_get_by_num(0, dir); + if (ep->active) { + // Abort any pending transfer from a prior control transfer per USB specs + // Due to Errata RP2040-E2: ABORT flag is only applicable for B2 and later (unusable for B0, B1). + // Which means we are not guaranteed to safely abort pending transfer on B0 and B1. + uint32_t const abort_mask = (dir ? USB_EP_ABORT_EP0_IN_BITS : USB_EP_ABORT_EP0_OUT_BITS); + if (rp2040_chip_version() >= 2) { + usb_hw_set->abort = abort_mask; + while ((usb_hw->abort_done & abort_mask) != abort_mask) {} + } + + _hw_endpoint_buffer_control_set_value32(ep, USB_BUF_CTRL_DATA1_PID | USB_BUF_CTRL_SEL); + hw_endpoint_reset_transfer(ep); + + if (rp2040_chip_version() >= 2) { + usb_hw_clear->abort_done = abort_mask; + usb_hw_clear->abort = abort_mask; + } } + ep->next_pid = 1u; + } } static void __tusb_irq_path_func(reset_non_control_endpoints)(void) { @@ -300,7 +284,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) { uint8_t const* setup = remove_volatile_cast(uint8_t const*, &usb_dpram->setup_packet); // reset pid to both 1 (data and ack) - reset_ep0_pid(); + reset_ep0(); // Pass setup packet to tiny usb dcd_event_setup_received(0, setup, true); @@ -388,6 +372,8 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) { void dcd_init(uint8_t rhport) { assert(rhport == 0); + TU_LOG(2, "Chip Version B%u\r\n", rp2040_chip_version()); + // Reset hardware to default state rp2040_usb_init(); diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index b5bace972..1ca711c77 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -35,13 +35,6 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTOTYPE //--------------------------------------------------------------------+ - -// Direction strings for debug -const char* ep_dir_string[] = { - "out", - "in", -}; - static void _hw_endpoint_xfer_sync(struct hw_endpoint* ep); #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX @@ -105,22 +98,14 @@ void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoi value |= or_mask; if (or_mask & USB_BUF_CTRL_AVAIL) { if (*ep->buffer_control & USB_BUF_CTRL_AVAIL) { - panic("ep %d %s was already available", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]); + panic("ep %02X was already available", ep->ep_addr); } *ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL; - // 12 cycle delay.. (should be good for 48*12Mhz = 576Mhz) + // 4.1.2.5.1 Con-current access: 12 cycles (should be good for 48*12Mhz = 576Mhz) after write to buffer control // Don't need delay in host mode as host is in charge -#if !CFG_TUH_ENABLED - __asm volatile ( - "b 1f\n" - "1: b 1f\n" - "1: b 1f\n" - "1: b 1f\n" - "1: b 1f\n" - "1: b 1f\n" - "1:\n" - : : : "memory"); -#endif + if ( !is_host_mode()) { + busy_wait_at_least_cycles(12); + } } } @@ -204,9 +189,7 @@ void hw_endpoint_xfer_start(struct hw_endpoint* ep, uint8_t* buffer, uint16_t to if (ep->active) { // TODO: Is this acceptable for interrupt packets? - TU_LOG(1, "WARN: starting new transfer on already active ep %d %s\r\n", tu_edpt_number(ep->ep_addr), - ep_dir_string[tu_edpt_dir(ep->ep_addr)]); - + TU_LOG(1, "WARN: starting new transfer on already active ep %02X\r\n", ep->ep_addr); hw_endpoint_reset_transfer(ep); } @@ -314,8 +297,7 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint* ep) { // Part way through a transfer if (!ep->active) { - panic("Can't continue xfer on inactive ep %d %s", tu_edpt_number(ep->ep_addr), - ep_dir_string[tu_edpt_dir(ep->ep_addr)]); + panic("Can't continue xfer on inactive ep %02X", ep->ep_addr); } // Update EP struct from hardware state @@ -324,8 +306,7 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint* ep) { // Now we have synced our state with the hardware. Is there more data to transfer? // If we are done then notify tinyusb if (ep->remaining_len == 0) { - pico_trace("Completed transfer of %d bytes on ep %d %s\r\n", - ep->xferred_len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]); + pico_trace("Completed transfer of %d bytes on ep %02X\r\n", ep->xferred_len, ep->ep_addr); // Notify caller we are done so it can notify the tinyusb stack hw_endpoint_lock_update(ep, -1); return true; -- cgit v1.3.1 From 834e2c956007709b69f5f85c426dcf51bb2abf63 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 13 Mar 2024 11:46:23 +0700 Subject: usbd only process last setup packet in the event queue --- .idea/.gitignore | 2 ++ src/device/usbd.c | 13 ++++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/.idea/.gitignore b/.idea/.gitignore index 73f69e095..b0811f163 100644 --- a/.idea/.gitignore +++ b/.idea/.gitignore @@ -6,3 +6,5 @@ /dataSources.local.xml # Editor-based HTTP Client requests /httpRequests/ +# GitHub Copilot persisted chat sessions +/copilot/chatSessions diff --git a/src/device/usbd.c b/src/device/usbd.c index 87542e9aa..ab572e095 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -68,9 +68,9 @@ typedef struct { uint8_t remote_wakeup_support : 1; // configuration descriptor's attribute uint8_t self_powered : 1; // configuration descriptor's attribute }; - volatile uint8_t cfg_num; // current active configuration (0x00 is not configured) uint8_t speed; + volatile uint8_t setup_count; uint8_t itf2drv[CFG_TUD_INTERFACE_MAX]; // map interface number to driver (0xff is invalid) uint8_t ep2drv[CFG_TUD_ENDPPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid ), can use only 4-bit each @@ -378,6 +378,7 @@ bool tud_init(uint8_t rhport) { TU_LOG_USBD("USBD init on controller %u\r\n", rhport); TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(usbd_device_t)); + TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(dcd_event_t)); TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_fifo_t)); TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_edpt_stream_t)); @@ -482,7 +483,12 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) { break; case DCD_EVENT_SETUP_RECEIVED: + _usbd_dev.setup_count--; TU_LOG_BUF(CFG_TUD_LOG_LEVEL, &event.setup_received, 8); + if (_usbd_dev.setup_count) { + TU_LOG_USBD(" Skipped since there is other SETUP in queue\r\n"); + break; + } // Mark as connected after receiving 1st setup packet. // But it is easier to set it every time instead of wasting time to check then set @@ -1063,6 +1069,11 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const* event, bool in_isr) // skip osal queue for SOF in usbd task break; + case DCD_EVENT_SETUP_RECEIVED: + _usbd_dev.setup_count++; + send = true; + break; + default: send = true; break; -- cgit v1.3.1 From 5a854ef2dc03373f125b48e93accf302c2fbdd66 Mon Sep 17 00:00:00 2001 From: henneboi Date: Mon, 11 Mar 2024 13:36:25 +0100 Subject: dcd_stm32_fsdev.c: Fix a bug seend with stm32h5xxx when the driver is compiled with cubeide O1/O2/O3 --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 3f4db985d..e0df21860 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -296,6 +296,19 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USB { #ifdef FSDEV_BUS_32BIT (void) USBx; + volatile uint32_t count = 10; + /* + WA: few cycles for RX PMA descriptor to update + This workaround is ported from stm32h5xx_hal_pcd.h : PCD_GET_EP_RX_CNT H5 + This code fixes an issue when the code is compiled in GCC with a fast optimization(O2/O3) and device with an high frequency. + The function doesn't return the correct value. + Issue observed on Windows 10 and stm32h573i_dk and tud_task() scheduled by IT, the device is not migrated the USB device is not visible . + */ + while (count > 0U) + { + asm("NOP"); + count--; + } return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16; #else __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx); -- cgit v1.3.1 From f9c85ae47b0aacd6716b671a5b6ea289b43275c0 Mon Sep 17 00:00:00 2001 From: henneboi Date: Wed, 6 Mar 2024 17:46:47 +0100 Subject: IAR Warning: Fixed due to an boolean operation between enum (Pa089) Warning[Pa089]: enumerated type mixed with another enumerated type ...tusb_uac2_audio.c 199 This issue stops the build if we treat warning as error --- src/device/usbd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/device/usbd.h b/src/device/usbd.h index 3ab6c813f..cf500143a 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -421,7 +421,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */ #define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN 7 #define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(_ep, _interval) \ - TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_NO_SYNC | TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval + TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_NO_SYNC | (uint8_t)TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval // AUDIO simple descriptor (UAC2) for 1 microphone input // - 1 Input Terminal, 1 Feature Unit (Mute and Volume Control), 1 Output Terminal, 1 Clock Source -- cgit v1.3.1 From 5d1f6934fbbeee3238267b0444172d47033a2fd9 Mon Sep 17 00:00:00 2001 From: Li Junru Date: Thu, 14 Mar 2024 20:55:05 +0800 Subject: fix: uvc multiple interface support 1. fix next interface may have IAD_DESC 2. fix vs_itf can't be open on bulk mode. --- src/class/video/video_device.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index c33dfa0b0..249ced83d 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -207,6 +207,24 @@ static void const* _find_desc(void const *beg, void const *end, uint_fast8_t des return cur; } +/** Find the first descriptor of two given types + * + * @param[in] beg The head of descriptor byte array. + * @param[in] end The tail of descriptor byte array. + * @param[in] desc_type_0 The first target descriptor type. + * @param[in] desc_type_1 The second target descriptor type. + * + * @return The pointer for interface descriptor. + * @retval end did not found interface descriptor */ +static void const* _find_desc_2_type(void const *beg, void const *end, uint_fast8_t desc_type_0, uint_fast8_t desc_type_1) +{ + void const *cur = beg; + while ((cur < end) && (desc_type_0 != tu_desc_type(cur)) && (desc_type_1 != tu_desc_type(cur))) { + cur = tu_desc_next(cur); + } + return cur; +} + /** Find the first descriptor specified by the arguments * * @param[in] beg The head of descriptor byte array. @@ -233,6 +251,10 @@ static void const* _find_desc_3(void const *beg, void const *end, } /** Return the next interface descriptor which has another interface number. + * If there are multiple VC interfaces, there will be an IAD descriptor before + * the next interface descriptor. Check both the IAD descriptor and the interface + * descriptor. + * 3.1 Descriptor Layout Overview * * @param[in] beg The head of descriptor byte array. * @param[in] end The tail of descriptor byte array. @@ -245,7 +267,7 @@ static void const* _next_desc_itf(void const *beg, void const *end) uint_fast8_t itfnum = ((tusb_desc_interface_t const*)cur)->bInterfaceNumber; while ((cur < end) && (itfnum == ((tusb_desc_interface_t const*)cur)->bInterfaceNumber)) { - cur = _find_desc(tu_desc_next(cur), end, TUSB_DESC_INTERFACE); + cur = _find_desc_2_type(tu_desc_next(cur), end, TUSB_DESC_INTERFACE, TUSB_DESC_INTERFACE_ASSOCIATION); } return cur; } @@ -1216,7 +1238,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin * host may not issue set_interface so open the streaming interface here. */ uint8_t const *sbeg = (uint8_t const*)itf_desc + stm->desc.beg; uint8_t const *send = (uint8_t const*)itf_desc + stm->desc.end; - if (end == _find_desc_itf(sbeg, send, _desc_itfnum(sbeg), 1)) { + if (send == _find_desc_itf(sbeg, send, _desc_itfnum(sbeg), 1)) { TU_VERIFY(_open_vs_itf(rhport, stm, 0), 0); } } -- cgit v1.3.1 From 6352081ded448ef64d5d3285dafab684d14fd649 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 15 Mar 2024 17:58:27 +0700 Subject: code format --- src/tusb.c | 248 +++++++++++++++++++++++-------------------------------------- 1 file changed, 93 insertions(+), 155 deletions(-) (limited to 'src') diff --git a/src/tusb.c b/src/tusb.c index 7c86f1ca5..ccb2a44bf 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -43,8 +43,7 @@ // Public API //--------------------------------------------------------------------+ -bool tusb_init(void) -{ +bool tusb_init(void) { #if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT) // init device stack CFG_TUSB_RHPORTx_MODE must be defined TU_ASSERT ( tud_init(TUD_OPT_RHPORT) ); @@ -58,8 +57,7 @@ bool tusb_init(void) return true; } -bool tusb_inited(void) -{ +bool tusb_inited(void) { bool ret = false; #if CFG_TUD_ENABLED @@ -77,37 +75,30 @@ bool tusb_inited(void) // Descriptor helper //--------------------------------------------------------------------+ -uint8_t const * tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1) -{ - while(desc+1 < end) - { - if ( desc[1] == byte1 ) return desc; +uint8_t const* tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1) { + while (desc + 1 < end) { + if (desc[1] == byte1) return desc; desc += desc[DESC_OFFSET_LEN]; } return NULL; } -uint8_t const * tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2) -{ - while(desc+2 < end) - { - if ( desc[1] == byte1 && desc[2] == byte2) return desc; +uint8_t const* tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2) { + while (desc + 2 < end) { + if (desc[1] == byte1 && desc[2] == byte2) return desc; desc += desc[DESC_OFFSET_LEN]; } return NULL; } -uint8_t const * tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3) -{ - while(desc+3 < end) - { +uint8_t const* tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3) { + while (desc + 3 < end) { if (desc[1] == byte1 && desc[2] == byte2 && desc[3] == byte3) return desc; desc += desc[DESC_OFFSET_LEN]; } return NULL; } - //--------------------------------------------------------------------+ // Endpoint Helper for both Host and Device stack //--------------------------------------------------------------------+ @@ -126,13 +117,11 @@ bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex) { } (void) osal_mutex_unlock(mutex); - return available; } bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex) { (void) mutex; - (void) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER); // can only release the endpoint if it is claimed and not busy @@ -142,58 +131,49 @@ bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex) { } (void) osal_mutex_unlock(mutex); - return ret; } -bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed) -{ +bool tu_edpt_validate(tusb_desc_endpoint_t const* desc_ep, tusb_speed_t speed) { uint16_t const max_packet_size = tu_edpt_packet_size(desc_ep); TU_LOG2(" Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, max_packet_size); - switch (desc_ep->bmAttributes.xfer) - { - case TUSB_XFER_ISOCHRONOUS: - { + switch (desc_ep->bmAttributes.xfer) { + case TUSB_XFER_ISOCHRONOUS: { uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 1023); TU_ASSERT(max_packet_size <= spec_size); + break; } - break; case TUSB_XFER_BULK: - if (speed == TUSB_SPEED_HIGH) - { + if (speed == TUSB_SPEED_HIGH) { // Bulk highspeed must be EXACTLY 512 TU_ASSERT(max_packet_size == 512); - }else - { + } else { // TODO Bulk fullspeed can only be 8, 16, 32, 64 TU_ASSERT(max_packet_size <= 64); } - break; + break; - case TUSB_XFER_INTERRUPT: - { + case TUSB_XFER_INTERRUPT: { uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 64); TU_ASSERT(max_packet_size <= spec_size); + break; } - break; - default: return false; + default: + return false; } return true; } -void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_itf, uint16_t desc_len, uint8_t driver_id) -{ +void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_itf, uint16_t desc_len, uint8_t driver_id) { uint8_t const* p_desc = (uint8_t const*) desc_itf; uint8_t const* desc_end = p_desc + desc_len; - while( p_desc < desc_end ) - { - if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) ) - { + while (p_desc < desc_end) { + if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)) { uint8_t const ep_addr = ((tusb_desc_endpoint_t const*) p_desc)->bEndpointAddress; TU_LOG(2, " Bind EP %02x to driver id %u\r\n", ep_addr, driver_id); @@ -204,25 +184,21 @@ void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_ } } -uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len) -{ +uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len) { uint8_t const* p_desc = (uint8_t const*) desc_itf; uint16_t len = 0; - while (itf_count--) - { + while (itf_count--) { // Next on interface desc len += tu_desc_len(desc_itf); p_desc = tu_desc_next(p_desc); - while (len < max_len) - { + while (len < max_len) { // return on IAD regardless of itf count - if ( tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION ) return len; + if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION) return len; - if ( (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) && - ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0 ) - { + if ((tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) && + ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0) { break; } @@ -239,8 +215,7 @@ uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, //--------------------------------------------------------------------+ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable, - void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize) -{ + void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize) { osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutex); (void) new_mutex; (void) is_tx; @@ -255,16 +230,12 @@ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool ove return true; } -TU_ATTR_ALWAYS_INLINE static inline -bool stream_claim(tu_edpt_stream_t* s) -{ - if (s->is_host) - { +TU_ATTR_ALWAYS_INLINE static inline bool stream_claim(tu_edpt_stream_t* s) { + if (s->is_host) { #if CFG_TUH_ENABLED return usbh_edpt_claim(s->daddr, s->ep_addr); #endif - }else - { + } else { #if CFG_TUD_ENABLED return usbd_edpt_claim(s->rhport, s->ep_addr); #endif @@ -273,16 +244,12 @@ bool stream_claim(tu_edpt_stream_t* s) return false; } -TU_ATTR_ALWAYS_INLINE static inline -bool stream_xfer(tu_edpt_stream_t* s, uint16_t count) -{ - if (s->is_host) - { +TU_ATTR_ALWAYS_INLINE static inline bool stream_xfer(tu_edpt_stream_t* s, uint16_t count) { + if (s->is_host) { #if CFG_TUH_ENABLED return usbh_edpt_xfer(s->daddr, s->ep_addr, count ? s->ep_buf : NULL, count); #endif - }else - { + } else { #if CFG_TUD_ENABLED return usbd_edpt_xfer(s->rhport, s->ep_addr, count ? s->ep_buf : NULL, count); #endif @@ -291,16 +258,12 @@ bool stream_xfer(tu_edpt_stream_t* s, uint16_t count) return false; } -TU_ATTR_ALWAYS_INLINE static inline -bool stream_release(tu_edpt_stream_t* s) -{ - if (s->is_host) - { +TU_ATTR_ALWAYS_INLINE static inline bool stream_release(tu_edpt_stream_t* s) { + if (s->is_host) { #if CFG_TUH_ENABLED return usbh_edpt_release(s->daddr, s->ep_addr); #endif - }else - { + } else { #if CFG_TUD_ENABLED return usbd_edpt_release(s->rhport, s->ep_addr); #endif @@ -313,34 +276,29 @@ bool stream_release(tu_edpt_stream_t* s) // Stream Write //--------------------------------------------------------------------+ -bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes) -{ +bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes) { // ZLP condition: no pending data, last transferred bytes is multiple of packet size - TU_VERIFY( !tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (s->ep_packetsize-1))) ); - - TU_VERIFY( stream_claim(s) ); - TU_ASSERT( stream_xfer(s, 0) ); + TU_VERIFY(!tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (s->ep_packetsize - 1)))); + TU_VERIFY(stream_claim(s)); + TU_ASSERT(stream_xfer(s, 0)); return true; } -uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s) -{ +uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s) { // skip if no data - TU_VERIFY( tu_fifo_count(&s->ff), 0 ); + TU_VERIFY(tu_fifo_count(&s->ff), 0); // Claim the endpoint - TU_VERIFY( stream_claim(s), 0 ); + TU_VERIFY(stream_claim(s), 0); // Pull data from FIFO -> EP buf uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize); - if ( count ) - { - TU_ASSERT( stream_xfer(s, count), 0 ); + if (count) { + TU_ASSERT(stream_xfer(s, count), 0); return count; - }else - { + } else { // Release endpoint since we don't make any transfer // Note: data is dropped if terminal is not connected stream_release(s); @@ -348,16 +306,14 @@ uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s) } } -uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize) -{ +uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const* buffer, uint32_t bufsize) { TU_VERIFY(bufsize); // TODO support ZLP uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize); // flush if fifo has more than packet size or // in rare case: fifo depth is configured too small (which never reach packet size) - if ( (tu_fifo_count(&s->ff) >= s->ep_packetsize) || (tu_fifo_depth(&s->ff) < s->ep_packetsize) ) - { + if ((tu_fifo_count(&s->ff) >= s->ep_packetsize) || (tu_fifo_depth(&s->ff) < s->ep_packetsize)) { tu_edpt_stream_write_xfer(s); } @@ -368,8 +324,7 @@ uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t // Stream Read //--------------------------------------------------------------------+ -uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s) -{ +uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s) { uint16_t available = tu_fifo_remaining(&s->ff); // Prepare for incoming data but only allow what we can store in the ring buffer. @@ -384,25 +339,20 @@ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s) // get available again since fifo can be changed before endpoint is claimed available = tu_fifo_remaining(&s->ff); - if ( available >= s->ep_packetsize ) - { + if (available >= s->ep_packetsize) { // multiple of packet size limit by ep bufsize - uint16_t count = (uint16_t) (available & ~(s->ep_packetsize -1)); + uint16_t count = (uint16_t) (available & ~(s->ep_packetsize - 1)); count = tu_min16(count, s->ep_bufsize); - - TU_ASSERT( stream_xfer(s, count), 0 ); - + TU_ASSERT(stream_xfer(s, count), 0); return count; - }else - { + } else { // Release endpoint since we don't make any transfer stream_release(s); return 0; } } -uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize) -{ +uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize) { uint32_t num_read = tu_fifo_read_n(&s->ff, buffer, (uint16_t) bufsize); tu_edpt_stream_read_xfer(s); return num_read; @@ -416,38 +366,33 @@ uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize #include #if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL || CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL - -char const* const tu_str_speed[] = { "Full", "Low", "High" }; -char const* const tu_str_std_request[] = -{ - "Get Status" , - "Clear Feature" , - "Reserved" , - "Set Feature" , - "Reserved" , - "Set Address" , - "Get Descriptor" , - "Set Descriptor" , - "Get Configuration" , - "Set Configuration" , - "Get Interface" , - "Set Interface" , - "Synch Frame" +char const* const tu_str_speed[] = {"Full", "Low", "High"}; +char const* const tu_str_std_request[] = { + "Get Status", + "Clear Feature", + "Reserved", + "Set Feature", + "Reserved", + "Set Address", + "Get Descriptor", + "Set Descriptor", + "Get Configuration", + "Set Configuration", + "Get Interface", + "Set Interface", + "Synch Frame" }; char const* const tu_str_xfer_result[] = { "OK", "FAILED", "STALLED", "TIMEOUT" }; - #endif -static void dump_str_line(uint8_t const* buf, uint16_t count) -{ +static void dump_str_line(uint8_t const* buf, uint16_t count) { tu_printf(" |"); // each line is 16 bytes - for(uint16_t i=0; i Date: Fri, 15 Mar 2024 20:39:45 +0700 Subject: improve uvc debug message --- src/class/video/video.h | 23 ++-- src/class/video/video_device.c | 223 ++++++++++++++++++++++------------ src/device/usbd.c | 2 +- src/portable/nordic/nrf5x/dcd_nrf5x.c | 4 +- 4 files changed, 157 insertions(+), 95 deletions(-) (limited to 'src') diff --git a/src/class/video/video.h b/src/class/video/video.h index abf1e34b9..b8a9b6369 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -160,22 +160,23 @@ typedef enum { /* A.9.1 VideoControl Interface Control Selectors */ typedef enum { VIDEO_VC_CTL_UNDEFINED = 0x00, - VIDEO_VC_CTL_VIDEO_POWER_MODE, - VIDEO_VC_CTL_REQUEST_ERROR_CODE, + VIDEO_VC_CTL_VIDEO_POWER_MODE, // 0x01 + VIDEO_VC_CTL_REQUEST_ERROR_CODE, // 0x02 } video_interface_control_selector_t; /* A.9.8 VideoStreaming Interface Control Selectors */ typedef enum { VIDEO_VS_CTL_UNDEFINED = 0x00, - VIDEO_VS_CTL_PROBE, - VIDEO_VS_CTL_COMMIT, - VIDEO_VS_CTL_STILL_PROBE, - VIDEO_VS_CTL_STILL_COMMIT, - VIDEO_VS_CTL_STILL_IMAGE_TRIGGER, - VIDEO_VS_CTL_STREAM_ERROR_CODE, - VIDEO_VS_CTL_GENERATE_KEY_FRAME, - VIDEO_VS_CTL_UPDATE_FRAME_SEGMENT, - VIDEO_VS_CTL_SYNCH_DELAY_CONTROL, + VIDEO_VS_CTL_PROBE, // 0x01 + VIDEO_VS_CTL_COMMIT, // 0x02 + VIDEO_VS_CTL_STILL_PROBE, // 0x03 + VIDEO_VS_CTL_STILL_COMMIT, // 0x04 + VIDEO_VS_CTL_STILL_IMAGE_TRIGGER, // 0x05 + VIDEO_VS_CTL_STREAM_ERROR_CODE, // 0x06 + VIDEO_VS_CTL_GENERATE_KEY_FRAME, // 0x07 + VIDEO_VS_CTL_UPDATE_FRAME_SEGMENT, // 0x08 + VIDEO_VS_CTL_SYNCH_DELAY_CONTROL, // 0x09 + } video_interface_streaming_selector_t; /* B. Terminal Types */ diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 249ced83d..dc3f8d897 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -143,13 +143,65 @@ CFG_TUD_MEM_SECTION tu_static videod_streaming_interface_t _videod_streaming_itf tu_static uint8_t const _cap_get = 0x1u; /* support for GET */ tu_static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */ +//--------------------------------------------------------------------+ +// Debug +//--------------------------------------------------------------------+ +#if CFG_TUSB_DEBUG >= CFG_TUD_VIDEO_LOG_LEVEL + +static tu_lookup_entry_t const tu_lookup_video_request[] = { + {.key = VIDEO_REQUEST_UNDEFINED, .data = "Undefined"}, + {.key = VIDEO_REQUEST_SET_CUR, .data = "SetCur"}, + {.key = VIDEO_REQUEST_SET_CUR_ALL, .data = "SetCurAll"}, + {.key = VIDEO_REQUEST_GET_CUR, .data = "GetCur"}, + {.key = VIDEO_REQUEST_GET_MIN, .data = "GetMin"}, + {.key = VIDEO_REQUEST_GET_MAX, .data = "GetMax"}, + {.key = VIDEO_REQUEST_GET_RES, .data = "GetRes"}, + {.key = VIDEO_REQUEST_GET_LEN, .data = "GetLen"}, + {.key = VIDEO_REQUEST_GET_INFO, .data = "GetInfo"}, + {.key = VIDEO_REQUEST_GET_DEF, .data = "GetDef"}, + {.key = VIDEO_REQUEST_GET_CUR_ALL, .data = "GetCurAll"}, + {.key = VIDEO_REQUEST_GET_MIN_ALL, .data = "GetMinAll"}, + {.key = VIDEO_REQUEST_GET_MAX_ALL, .data = "GetMaxAll"}, + {.key = VIDEO_REQUEST_GET_RES_ALL, .data = "GetResAll"}, + {.key = VIDEO_REQUEST_GET_DEF_ALL, .data = "GetDefAll"}, +}; + +static tu_lookup_table_t const tu_table_video_request = { + .count = TU_ARRAY_SIZE(tu_lookup_video_request), + .items = tu_lookup_video_request +}; + +static char const* const tu_str_video_vc_control_selector[] = { + "Undefined", + "Video Power Mode", + "Request Error Code", +}; + +static char const* const tu_str_video_vs_control_selector[] = { + "Undefined", + "Probe", + "Commit", + "Still Probe", + "Still Commit", + "Still Image Trigger", + "Stream Error Code", + "Generate Key Frame", + "Update Frame Segment", + "Sync Delay", +}; + +#endif + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + /** Get interface number from the interface descriptor * * @param[in] desc interface descriptor * * @return bInterfaceNumber */ -static inline uint8_t _desc_itfnum(void const *desc) -{ +static inline uint8_t _desc_itfnum(void const *desc) { return ((uint8_t const*)desc)[2]; } @@ -158,8 +210,7 @@ static inline uint8_t _desc_itfnum(void const *desc) * @param[in] desc endpoint descriptor * * @return bEndpointAddress */ -static inline uint8_t _desc_ep_addr(void const *desc) -{ +static inline uint8_t _desc_ep_addr(void const *desc) { return ((uint8_t const*)desc)[2]; } @@ -169,8 +220,7 @@ static inline uint8_t _desc_ep_addr(void const *desc) * @param[in] stm_idx index number of streaming interface * * @return instance */ -static videod_streaming_interface_t* _get_instance_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) -{ +static videod_streaming_interface_t* _get_instance_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) { videod_interface_t *ctl = &_videod_itf[ctl_idx]; if (!ctl->beg) return NULL; videod_streaming_interface_t *stm = &_videod_streaming_itf[ctl->stm[stm_idx]]; @@ -178,13 +228,11 @@ static videod_streaming_interface_t* _get_instance_streaming(uint_fast8_t ctl_id return stm; } -static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self) -{ +static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self) { return (tusb_desc_vc_itf_t const *)(self->beg + self->cur); } -static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const *self) -{ +static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const *self) { if (!self->desc.cur) return NULL; uint8_t const *desc = _videod_itf[self->index_vc].beg; return (tusb_desc_vs_itf_t const*)(desc + self->desc.cur); @@ -198,8 +246,7 @@ static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static void const* _find_desc(void const *beg, void const *end, uint_fast8_t desc_type) -{ +static void const* _find_desc(void const *beg, void const *end, uint_fast8_t desc_type) { void const *cur = beg; while ((cur < end) && (desc_type != tu_desc_type(cur))) { cur = tu_desc_next(cur); @@ -238,8 +285,7 @@ static void const* _find_desc_2_type(void const *beg, void const *end, uint_fast static void const* _find_desc_3(void const *beg, void const *end, uint_fast8_t desc_type, uint_fast8_t element_0, - uint_fast8_t element_1) -{ + uint_fast8_t element_1) { for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, desc_type)) { uint8_t const *p = (uint8_t const *)cur; if ((p[2] == element_0) && (p[3] == element_1)) { @@ -261,8 +307,7 @@ static void const* _find_desc_3(void const *beg, void const *end, * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static void const* _next_desc_itf(void const *beg, void const *end) -{ +static void const* _next_desc_itf(void const *beg, void const *end) { void const *cur = beg; uint_fast8_t itfnum = ((tusb_desc_interface_t const*)cur)->bInterfaceNumber; while ((cur < end) && @@ -413,8 +458,10 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED: param->wCompQuality = 1; /* 1 to 10000 */ break; - case VIDEO_CS_ITF_VS_FORMAT_MJPEG: + + case VIDEO_CS_ITF_VS_FORMAT_MJPEG: break; + default: return false; } @@ -435,9 +482,11 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED: frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * fmt->uncompressed.bBitsPerPixel / 8; break; + case VIDEO_CS_ITF_VS_FORMAT_MJPEG: frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * 16 / 8; /* YUV422 */ break; + default: break; } param->dwMaxVideoFrameSize = frame_size; @@ -478,10 +527,12 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const * if (_get_desc_vs(stm)) param->bFormatIndex = _get_desc_vs(stm)->stm.bNumFormats; break; + case VIDEO_REQUEST_GET_MIN: case VIDEO_REQUEST_GET_DEF: param->bFormatIndex = 1; break; + default: return false; } /* Set the parameters determined by the format */ @@ -510,18 +561,22 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const * case VIDEO_REQUEST_GET_MAX: frmnum = fmt->bNumFrameDescriptors; break; + case VIDEO_REQUEST_GET_MIN: frmnum = 1; break; + case VIDEO_REQUEST_GET_DEF: switch (fmt->bDescriptorSubType) { - case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED: - frmnum = fmt->uncompressed.bDefaultFrameIndex; - break; - case VIDEO_CS_ITF_VS_FORMAT_MJPEG: - frmnum = fmt->mjpeg.bDefaultFrameIndex; - break; - default: return false; + case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED: + frmnum = fmt->uncompressed.bDefaultFrameIndex; + break; + + case VIDEO_CS_ITF_VS_FORMAT_MJPEG: + frmnum = fmt->mjpeg.bDefaultFrameIndex; + break; + + default: return false; } break; default: return false; @@ -534,9 +589,11 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const * case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED: frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * fmt->uncompressed.bBitsPerPixel / 8; break; + case VIDEO_CS_ITF_VS_FORMAT_MJPEG: frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * 16 / 8; /* YUV422 */ break; + default: return false; } param->dwMaxVideoFrameSize = frame_size; @@ -552,42 +609,43 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const * uint_fast32_t interval, interval_ms; switch (request) { - case VIDEO_REQUEST_GET_MAX: - { - uint_fast32_t min_interval, max_interval; - uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType; - max_interval = num_intervals ? frm->uncompressed.dwFrameInterval[num_intervals - 1]: frm->uncompressed.dwFrameInterval[1]; - min_interval = frm->uncompressed.dwFrameInterval[0]; - interval = max_interval; - interval_ms = min_interval / 10000; - } + case VIDEO_REQUEST_GET_MAX: { + uint_fast32_t min_interval, max_interval; + uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType; + max_interval = num_intervals ? frm->uncompressed.dwFrameInterval[num_intervals - 1]: frm->uncompressed.dwFrameInterval[1]; + min_interval = frm->uncompressed.dwFrameInterval[0]; + interval = max_interval; + interval_ms = min_interval / 10000; break; - case VIDEO_REQUEST_GET_MIN: - { - uint_fast32_t min_interval, max_interval; - uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType; - max_interval = num_intervals ? frm->uncompressed.dwFrameInterval[num_intervals - 1]: frm->uncompressed.dwFrameInterval[1]; - min_interval = frm->uncompressed.dwFrameInterval[0]; - interval = min_interval; - interval_ms = max_interval / 10000; - } + } + + case VIDEO_REQUEST_GET_MIN: { + uint_fast32_t min_interval, max_interval; + uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType; + max_interval = num_intervals ? frm->uncompressed.dwFrameInterval[num_intervals - 1]: frm->uncompressed.dwFrameInterval[1]; + min_interval = frm->uncompressed.dwFrameInterval[0]; + interval = min_interval; + interval_ms = max_interval / 10000; break; + } + case VIDEO_REQUEST_GET_DEF: interval = frm->uncompressed.dwDefaultFrameInterval; interval_ms = interval / 10000; break; - case VIDEO_REQUEST_GET_RES: - { - uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType; - if (num_intervals) { - interval = 0; - interval_ms = 0; - } else { - interval = frm->uncompressed.dwFrameInterval[2]; - interval_ms = interval / 10000; - } + + case VIDEO_REQUEST_GET_RES: { + uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType; + if (num_intervals) { + interval = 0; + interval_ms = 0; + } else { + interval = frm->uncompressed.dwFrameInterval[2]; + interval_ms = interval / 10000; } break; + } + default: return false; } param->dwFrameInterval = interval; @@ -681,8 +739,7 @@ static bool _init_vs_configuration(videod_streaming_interface_t *stm) /* initialize streaming settings */ stm->state = VS_STATE_PROBING; stm->max_payload_transfer_size = 0; - video_probe_and_commit_control_t *param = - (video_probe_and_commit_control_t *)&stm->ep_buf; + video_probe_and_commit_control_t *param = (video_probe_and_commit_control_t *)&stm->ep_buf; tu_memclr(param, sizeof(*param)); return _update_streaming_parameters(stm, param); } @@ -760,6 +817,10 @@ static uint_fast16_t _prepare_in_payload(videod_streaming_interface_t *stm) pkt_len = hdr_len + remaining; } uint_fast16_t data_len = pkt_len - hdr_len; + TU_LOG2(" prepare remain = %u, hdr_len = %u, pkt_len = %u, offset = %lu, data_len = %u\r\n", remaining, hdr_len, pkt_len, stm->offset, data_len); + if ( data_len > sizeof(stm->ep_buf) ) { + TU_BREAKPOINT(); + } memcpy(&stm->ep_buf[hdr_len], stm->buffer + stm->offset, data_len); stm->offset += data_len; remaining -= data_len; @@ -775,6 +836,7 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t ctl_idx) { + TU_LOG_DRV("\r\n"); switch (request->bRequest) { case TUSB_REQ_GET_INTERFACE: if (stage == CONTROL_STAGE_SETUP) @@ -812,7 +874,10 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, videod_interface_t *self = &_videod_itf[ctl_idx]; /* 4.2.1 Interface Control Request */ - switch (TU_U16_HIGH(request->wValue)) { + uint8_t const ctrl_sel = TU_U16_HIGH(request->wValue); + TU_LOG_DRV("%s_Control(%s)\r\n", tu_str_video_vc_control_selector[ctrl_sel], tu_lookup_find(&tu_table_video_request, request->bRequest)); + + switch (ctrl_sel) { case VIDEO_VC_CTL_VIDEO_POWER_MODE: switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: @@ -876,19 +941,19 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t ctl_idx) { - uint_fast8_t entity_id; switch (request->bmRequestType_bit.type) { case TUSB_REQ_TYPE_STANDARD: return handle_video_ctl_std_req(rhport, stage, request, ctl_idx); - case TUSB_REQ_TYPE_CLASS: - entity_id = TU_U16_HIGH(request->wIndex); + case TUSB_REQ_TYPE_CLASS: { + uint_fast8_t entity_id = TU_U16_HIGH(request->wIndex); if (!entity_id) { return handle_video_ctl_cs_req(rhport, stage, request, ctl_idx); } else { TU_VERIFY(_find_desc_entity(_get_desc_vc(&_videod_itf[ctl_idx]), entity_id), VIDEO_ERROR_INVALID_REQUEST); return VIDEO_ERROR_NONE; } + } default: return VIDEO_ERROR_INVALID_REQUEST; @@ -899,6 +964,7 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t stm_idx) { + TU_LOG_DRV("\r\n"); videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx]; switch (request->bRequest) { case TUSB_REQ_GET_INTERFACE: @@ -914,8 +980,7 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, return VIDEO_ERROR_NONE; case TUSB_REQ_SET_INTERFACE: - if (stage == CONTROL_STAGE_SETUP) - { + if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(_open_vs_itf(rhport, self, request->wValue), VIDEO_ERROR_UNKNOWN); tud_control_status(rhport, request); } @@ -929,26 +994,26 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, - uint_fast8_t stm_idx) -{ + uint_fast8_t stm_idx) { (void)rhport; videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx]; + uint8_t const ctrl_sel = TU_U16_HIGH(request->wValue); + TU_LOG_DRV("%s_Control(%s)\r\n", tu_str_video_vs_control_selector[ctrl_sel], tu_lookup_find(&tu_table_video_request, request->bRequest)); + /* 4.2.1 Interface Control Request */ - switch (TU_U16_HIGH(request->wValue)) { + switch (ctrl_sel) { case VIDEO_VS_CTL_STREAM_ERROR_CODE: switch (request->bRequest) { case VIDEO_REQUEST_GET_CUR: - if (stage == CONTROL_STAGE_SETUP) - { + if (stage == CONTROL_STAGE_SETUP) { /* TODO */ TU_VERIFY(tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t)), VIDEO_ERROR_UNKNOWN); } return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_INFO: - if (stage == CONTROL_STAGE_SETUP) - { + if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get, sizeof(_cap_get)), VIDEO_ERROR_UNKNOWN); } return VIDEO_ERROR_NONE; @@ -962,6 +1027,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, self->state = VS_STATE_PROBING; _init_vs_configuration(self); } + switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: if (stage == CONTROL_STAGE_SETUP) { @@ -975,8 +1041,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_CUR: - if (stage == CONTROL_STAGE_SETUP) - { + if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); } @@ -986,8 +1051,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, case VIDEO_REQUEST_GET_MAX: case VIDEO_REQUEST_GET_RES: case VIDEO_REQUEST_GET_DEF: - if (stage == CONTROL_STAGE_SETUP) - { + if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); video_probe_and_commit_control_t tmp; tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; @@ -997,8 +1061,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_LEN: - if (stage == CONTROL_STAGE_SETUP) - { + if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(2 == request->wLength, VIDEO_ERROR_UNKNOWN); uint16_t len = sizeof(video_probe_and_commit_control_t); TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&len, sizeof(len)), VIDEO_ERROR_UNKNOWN); @@ -1006,8 +1069,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_INFO: - if (stage == CONTROL_STAGE_SETUP) - { + if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN); } @@ -1046,16 +1108,14 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_CUR: - if (stage == CONTROL_STAGE_SETUP) - { + if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); } return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_LEN: - if (stage == CONTROL_STAGE_SETUP) - { + if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(2 == request->wLength, VIDEO_ERROR_UNKNOWN); uint16_t len = sizeof(video_probe_and_commit_control_t); TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&len, sizeof(len)), VIDEO_ERROR_UNKNOWN); @@ -1063,8 +1123,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_INFO: - if (stage == CONTROL_STAGE_SETUP) - { + if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN); } @@ -1264,6 +1323,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ } if (itf < CFG_TUD_VIDEO) { + TU_LOG_DRV(" VC[%d]: ", itf); err = handle_video_ctl_req(rhport, stage, request, itf); _videod_itf[itf].error_code = (uint8_t)err; if (err) return false; @@ -1279,6 +1339,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ } if (itf < CFG_TUD_VIDEO_STREAMING) { + TU_LOG_DRV(" VS[%d]: ", itf); err = handle_video_stm_req(rhport, stage, request, itf); _videod_streaming_itf[itf].error_code = (uint8_t)err; if (err) return false; diff --git a/src/device/usbd.c b/src/device/usbd.c index ab572e095..96d0b698b 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -319,7 +319,7 @@ void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback) { for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) { usbd_class_driver_t const* driver = get_driver(i); if (driver && driver->control_xfer_cb == callback) { - TU_LOG_USBD(" %s control complete\r\n", driver->name); + TU_LOG_USBD("%s control complete\r\n", driver->name); return; } } diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index 841cda752..80a285ef0 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -246,7 +246,7 @@ static void xact_in_dma(uint8_t epnum) //--------------------------------------------------------------------+ void dcd_init (uint8_t rhport) { - TU_LOG1("dcd init\r\n"); + TU_LOG2("dcd init\r\n"); (void) rhport; } @@ -685,7 +685,7 @@ void dcd_int_handler(uint8_t rhport) if ( int_status & USBD_INTEN_USBEVENT_Msk ) { - TU_LOG(2, "EVENTCAUSE = 0x%04lX\r\n", NRF_USBD->EVENTCAUSE); + TU_LOG(3, "EVENTCAUSE = 0x%04lX\r\n", NRF_USBD->EVENTCAUSE); enum { EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk | USBD_EVENTCAUSE_ISOOUTCRC_Msk }; uint32_t const evt_cause = NRF_USBD->EVENTCAUSE & EVT_CAUSE_MASK; -- cgit v1.3.1 From ff12544c9ac1f61c5d25d58608f16f5991e9f776 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 20 Mar 2024 22:45:46 +0700 Subject: added dedicate buffer for probe commit payload --- src/class/video/video_device.c | 45 ++++++++++++++++-------------------------- 1 file changed, 17 insertions(+), 28 deletions(-) (limited to 'src') diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index dc3f8d897..5306356ba 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -114,6 +114,8 @@ typedef struct TU_ATTR_PACKED { uint32_t max_payload_transfer_size; uint8_t error_code;/* error code */ uint8_t state; /* 0:probing 1:committed 2:streaming */ + + video_probe_and_commit_control_t probe_commit_payload; /* Probe and Commit control */ /*------------- From this point, data is not cleared by bus reset -------------*/ CFG_TUSB_MEM_ALIGN uint8_t ep_buf[CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE]; /* EP transfer buffer for streaming */ } videod_streaming_interface_t; @@ -734,12 +736,11 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t return true; } -static bool _init_vs_configuration(videod_streaming_interface_t *stm) -{ +static bool _init_vs_configuration(videod_streaming_interface_t *stm) { /* initialize streaming settings */ stm->state = VS_STATE_PROBING; stm->max_payload_transfer_size = 0; - video_probe_and_commit_control_t *param = (video_probe_and_commit_control_t *)&stm->ep_buf; + video_probe_and_commit_control_t *param = &stm->probe_commit_payload; tu_memclr(param, sizeof(*param)); return _update_streaming_parameters(stm, param); } @@ -816,11 +817,8 @@ static uint_fast16_t _prepare_in_payload(videod_streaming_interface_t *stm) if (hdr_len + remaining < pkt_len) { pkt_len = hdr_len + remaining; } + TU_ASSERT(pkt_len >= hdr_len); uint_fast16_t data_len = pkt_len - hdr_len; - TU_LOG2(" prepare remain = %u, hdr_len = %u, pkt_len = %u, offset = %lu, data_len = %u\r\n", remaining, hdr_len, pkt_len, stm->offset, data_len); - if ( data_len > sizeof(stm->ep_buf) ) { - TU_BREAKPOINT(); - } memcpy(&stm->ep_buf[hdr_len], stm->buffer + stm->offset, data_len); stm->offset += data_len; remaining -= data_len; @@ -1025,17 +1023,15 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, case VIDEO_VS_CTL_PROBE: if (self->state != VS_STATE_PROBING) { self->state = VS_STATE_PROBING; - _init_vs_configuration(self); } switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: if (stage == CONTROL_STAGE_SETUP) { - TU_VERIFY(sizeof(video_probe_and_commit_control_t) >= request->wLength, VIDEO_ERROR_UNKNOWN); - TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), + TU_VERIFY(tud_control_xfer(rhport, request, &self->probe_commit_payload, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); } else if (stage == CONTROL_STAGE_DATA) { - TU_VERIFY(_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf), + TU_VERIFY(_update_streaming_parameters(self, &self->probe_commit_payload), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); } return VIDEO_ERROR_NONE; @@ -1043,7 +1039,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, case VIDEO_REQUEST_GET_CUR: if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); - TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, &self->probe_commit_payload, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); } return VIDEO_ERROR_NONE; @@ -1053,8 +1049,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, case VIDEO_REQUEST_GET_DEF: if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); - video_probe_and_commit_control_t tmp; - tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; + video_probe_and_commit_control_t tmp = self->probe_commit_payload; TU_VERIFY(_negotiate_streaming_parameters(self, request->bRequest, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); TU_VERIFY(tud_control_xfer(rhport, request, &tmp, sizeof(tmp)), VIDEO_ERROR_UNKNOWN); } @@ -1083,10 +1078,9 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: if (stage == CONTROL_STAGE_SETUP) { - TU_VERIFY(sizeof(video_probe_and_commit_control_t) >= request->wLength, VIDEO_ERROR_UNKNOWN); - TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, &self->probe_commit_payload, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); } else if (stage == CONTROL_STAGE_DATA) { - video_probe_and_commit_control_t *param = (video_probe_and_commit_control_t*)self->ep_buf; + video_probe_and_commit_control_t *param = &self->probe_commit_payload; TU_VERIFY(_update_streaming_parameters(self, param), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); /* Set the negotiated value */ self->max_payload_transfer_size = param->dwMaxPayloadTransferSize; @@ -1110,7 +1104,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, case VIDEO_REQUEST_GET_CUR: if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); - TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, &self->probe_commit_payload, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); } return VIDEO_ERROR_NONE; @@ -1224,8 +1218,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu //--------------------------------------------------------------------+ // USBD Driver API //--------------------------------------------------------------------+ -void videod_init(void) -{ +void videod_init(void) { for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO; ++i) { videod_interface_t* ctl = &_videod_itf[i]; tu_memclr(ctl, sizeof(*ctl)); @@ -1236,8 +1229,7 @@ void videod_init(void) } } -void videod_reset(uint8_t rhport) -{ +void videod_reset(uint8_t rhport) { (void) rhport; for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO; ++i) { videod_interface_t* ctl = &_videod_itf[i]; @@ -1249,8 +1241,7 @@ void videod_reset(uint8_t rhport) } } -uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) -{ +uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) { TU_VERIFY((TUSB_CLASS_VIDEO == itf_desc->bInterfaceClass) && (VIDEO_SUBCLASS_CONTROL == itf_desc->bInterfaceSubClass) && (VIDEO_ITF_PROTOCOL_15 == itf_desc->bInterfaceProtocol), 0); @@ -1309,8 +1300,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin // Invoked when a control transfer occurred on an interface of this class // Driver response accordingly to the request and the transfer stage (setup/data/ack) // return false to stall control endpoint (e.g unsupported request) -bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) -{ +bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) { int err; TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE); uint_fast8_t itfnum = tu_u16_low(request->wIndex); @@ -1348,8 +1338,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ return false; } -bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) -{ +bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { (void)result; (void)xferred_bytes; /* find streaming handle */ -- cgit v1.3.1 From 61a31db8ecf66460e4888aef7915da66d98964d0 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Wed, 20 Mar 2024 15:20:24 -0700 Subject: Tweaks for ESP-IDF 5.2.1 --- src/portable/espressif/esp32sx/dcd_esp32sx.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c index 1fcfb6241..bfc0baa56 100644 --- a/src/portable/espressif/esp32sx/dcd_esp32sx.c +++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c @@ -31,16 +31,26 @@ #if (((CFG_TUSB_MCU == OPT_MCU_ESP32S2) || (CFG_TUSB_MCU == OPT_MCU_ESP32S3)) && CFG_TUD_ENABLED) // Espressif -#include "freertos/xtensa_api.h" +#include "xtensa_api.h" #include "esp_intr_alloc.h" #include "esp_log.h" #include "soc/dport_reg.h" #include "soc/gpio_sig_map.h" #include "soc/usb_periph.h" +#include "soc/usb_reg.h" +#include "soc/usb_struct.h" #include "soc/periph_defs.h" // for interrupt source #include "device/dcd.h" +#ifndef USB_OUT_EP_NUM +#define USB_OUT_EP_NUM ((int) (sizeof(USB0.out_ep_reg) / sizeof(USB0.out_ep_reg[0]))) +#endif + +#ifndef USB_IN_EP_NUM +#define USB_IN_EP_NUM ((int) (sizeof(USB0.in_ep_reg) / sizeof(USB0.in_ep_reg[0]))) +#endif + // Max number of bi-directional endpoints including EP0 // Note: ESP32S2 specs say there are only up to 5 IN active endpoints include EP0 // We should probably prohibit enabling Endpoint IN > 4 (not done yet) -- cgit v1.3.1 From 74bd2647589790b3bee49146774133c2061a34fe Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 22 Mar 2024 11:42:33 +0700 Subject: adding deinit() stub for usbh/hcd class driver add TUSB_VERSION_BUILD, also add TUSB_VERSION_NUMBER --- src/class/cdc/cdc_host.c | 4 ++++ src/class/cdc/cdc_host.h | 1 + src/class/hid/hid_host.c | 4 ++++ src/class/hid/hid_host.h | 1 + src/class/msc/msc_host.c | 5 +++++ src/class/msc/msc_host.h | 1 + src/host/hcd.h | 3 +++ src/host/hub.c | 7 ++++-- src/host/hub.h | 1 + src/host/usbh.c | 55 ++++++++++++++++++++++++++++++++++++------------ src/host/usbh.h | 4 ++++ src/host/usbh_pvt.h | 4 +--- src/tusb_option.h | 5 +++++ 13 files changed, 76 insertions(+), 19 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 2fb37d835..14f380b40 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -637,6 +637,10 @@ void cdch_init(void) { } } +bool cdch_deinit(void) { + return true; +} + void cdch_close(uint8_t daddr) { for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) { cdch_interface_t* p_cdc = &cdch_data[idx]; diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index d512a23a5..7530b1e9d 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -193,6 +193,7 @@ TU_ATTR_WEAK extern void tuh_cdc_tx_complete_cb(uint8_t idx); // Internal Class Driver API //--------------------------------------------------------------------+ void cdch_init (void); +bool cdch_deinit (void); bool cdch_open (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); bool cdch_set_config (uint8_t dev_addr, uint8_t itf_num); bool cdch_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes); diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 7330fa237..16e2d3c2c 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -376,6 +376,10 @@ void hidh_init(void) { tu_memclr(_hidh_itf, sizeof(_hidh_itf)); } +bool hidh_deinit(void) { + return true; +} + bool hidh_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { (void) result; diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h index 17f4e27c0..9ea222b3d 100644 --- a/src/class/hid/hid_host.h +++ b/src/class/hid/hid_host.h @@ -164,6 +164,7 @@ TU_ATTR_WEAK void tuh_hid_set_protocol_complete_cb(uint8_t dev_addr, uint8_t idx // Internal Class Driver API //--------------------------------------------------------------------+ void hidh_init(void); +bool hidh_deinit(void); bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const* desc_itf, uint16_t max_len); bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num); bool hidh_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c index 39f2d9f1c..61ecb8e4e 100644 --- a/src/class/msc/msc_host.c +++ b/src/class/msc/msc_host.c @@ -288,6 +288,11 @@ void msch_init(void) { tu_memclr(_msch_itf, sizeof(_msch_itf)); } +bool msch_deinit(void) { + return true; +} + + void msch_close(uint8_t dev_addr) { TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX,); msch_interface_t* p_msc = get_itf(dev_addr); diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h index 9ca1b4703..5bf2e62e3 100644 --- a/src/class/msc/msc_host.h +++ b/src/class/msc/msc_host.h @@ -114,6 +114,7 @@ TU_ATTR_WEAK void tuh_msc_umount_cb(uint8_t dev_addr); //--------------------------------------------------------------------+ void msch_init (void); +bool msch_deinit (void); bool msch_open (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len); bool msch_set_config (uint8_t dev_addr, uint8_t itf_num); void msch_close (uint8_t dev_addr); diff --git a/src/host/hcd.h b/src/host/hcd.h index 2bde289df..d5804c608 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -130,6 +130,9 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) TU_AT // Initialize controller to host mode bool hcd_init(uint8_t rhport); +// De-initialize controller +bool hcd_deinit(uint8_t rhport); + // Interrupt Handler void hcd_int_handler(uint8_t rhport, bool in_isr); diff --git a/src/host/hub.c b/src/host/hub.c index 3bac18698..0853ff27a 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -182,11 +182,14 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, //--------------------------------------------------------------------+ // CLASS-USBH API (don't require to verify parameters) //--------------------------------------------------------------------+ -void hub_init(void) -{ +void hub_init(void) { tu_memclr(hub_data, sizeof(hub_data)); } +bool hub_deinit(void) { + return true; +} + bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { (void) rhport; diff --git a/src/host/hub.h b/src/host/hub.h index 390740e1f..c3f4a3612 100644 --- a/src/host/hub.h +++ b/src/host/hub.h @@ -205,6 +205,7 @@ static inline bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_por // Internal Class Driver API //--------------------------------------------------------------------+ void hub_init (void); +bool hub_deinit (void); bool hub_open (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); bool hub_set_config (uint8_t dev_addr, uint8_t itf_num); bool hub_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes); diff --git a/src/host/usbh.c b/src/host/usbh.c index 625857683..cf348bbb2 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -45,8 +45,13 @@ #endif //--------------------------------------------------------------------+ -// Callback weak stubs (called if application does not provide) +// Weak stubs: invoked if no strong implementation is available //--------------------------------------------------------------------+ +TU_ATTR_WEAK bool hcd_deinit(uint8_t rhport) { + (void) rhport; + return false; +} + TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) { (void) rhport; (void) eventid; @@ -119,16 +124,17 @@ typedef struct { // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL - #define DRIVER_NAME(_name) .name = _name, + #define DRIVER_NAME(_name) _name #else - #define DRIVER_NAME(_name) + #define DRIVER_NAME(_name) NULL #endif static usbh_class_driver_t const usbh_class_drivers[] = { #if CFG_TUH_CDC { - DRIVER_NAME("CDC") + .name = DRIVER_NAME("CDC"), .init = cdch_init, + .deinit = cdch_deinit, .open = cdch_open, .set_config = cdch_set_config, .xfer_cb = cdch_xfer_cb, @@ -138,8 +144,9 @@ static usbh_class_driver_t const usbh_class_drivers[] = { #if CFG_TUH_MSC { - DRIVER_NAME("MSC") + .name = DRIVER_NAME("MSC"), .init = msch_init, + .deinit = msch_deinit, .open = msch_open, .set_config = msch_set_config, .xfer_cb = msch_xfer_cb, @@ -149,8 +156,9 @@ static usbh_class_driver_t const usbh_class_drivers[] = { #if CFG_TUH_HID { - DRIVER_NAME("HID") + .name = DRIVER_NAME("HID"), .init = hidh_init, + .deinit = hidh_deinit, .open = hidh_open, .set_config = hidh_set_config, .xfer_cb = hidh_xfer_cb, @@ -160,8 +168,9 @@ static usbh_class_driver_t const usbh_class_drivers[] = { #if CFG_TUH_HUB { - DRIVER_NAME("HUB") + .name = DRIVER_NAME("HUB"), .init = hub_init, + .deinit = hub_deinit, .open = hub_open, .set_config = hub_set_config, .xfer_cb = hub_xfer_cb, @@ -171,9 +180,11 @@ static usbh_class_driver_t const usbh_class_drivers[] = { #if CFG_TUH_VENDOR { - DRIVER_NAME("VENDOR") + .name = DRIVER_NAME("VENDOR"), .init = cush_init, - .open = cush_open_subtask, + .deinit = cush_deinit, + .open = cush_open, + .set_config = cush_set_config, .xfer_cb = cush_isr, .close = cush_close } @@ -338,11 +349,11 @@ bool tuh_inited(void) { return _usbh_controller != TUSB_INDEX_INVALID_8; } -bool tuh_init(uint8_t controller_id) { +bool tuh_init(uint8_t rhport) { // skip if already initialized if ( tuh_inited() ) return true; - TU_LOG_USBH("USBH init on controller %u\r\n", controller_id); + TU_LOG_USBH("USBH init on controller %u\r\n", rhport); TU_LOG_INT_USBH(sizeof(usbh_device_t)); TU_LOG_INT_USBH(sizeof(hcd_event_t)); TU_LOG_INT_USBH(sizeof(_ctrl_xfer)); @@ -383,10 +394,26 @@ bool tuh_init(uint8_t controller_id) { } } - _usbh_controller = controller_id;; + _usbh_controller = rhport;; + + TU_ASSERT(hcd_init(rhport)); + hcd_int_enable(rhport); + + return true; +} + +bool tuh_deinit(uint8_t rhport) { + if (!tuh_rhport_is_active(rhport)) return true; + + hcd_int_disable(rhport); + hcd_deinit(rhport); - TU_ASSERT(hcd_init(controller_id)); - hcd_int_enable(controller_id); + _usbh_controller = TUSB_INDEX_INVALID_8; + + // no other controller is active, deinit the stack + if (!tuh_inited()) { + + } return true; } diff --git a/src/host/usbh.h b/src/host/usbh.h index 9ff118543..0e31e80a7 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -109,7 +109,11 @@ bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param); // Init host stack bool tuh_init(uint8_t rhport); +// Deinit host stack on rhport +bool tuh_deinit(uint8_t rhport); + // Check if host stack is already initialized with any roothub ports +// To check if an rhport is initialized, use tuh_rhport_is_active() bool tuh_inited(void); // Task function should be called in main/rtos loop, extended version of tuh_task() diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h index 4ed2a72b5..204315175 100644 --- a/src/host/usbh_pvt.h +++ b/src/host/usbh_pvt.h @@ -50,11 +50,9 @@ enum { //--------------------------------------------------------------------+ typedef struct { - #if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL char const* name; - #endif - void (* const init )(void); + bool (* const deinit )(void); bool (* const open )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); bool (* const set_config )(uint8_t dev_addr, uint8_t itf_num); bool (* const xfer_cb )(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); diff --git a/src/tusb_option.h b/src/tusb_option.h index 96378cb80..22f27e9e1 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -29,9 +29,14 @@ #include "common/tusb_compiler.h" +// Version is release as major.minor.revision eg 1.0.0. though there could be notable APIs before a new release. +// For notable API changes within a release, we increase the build number. #define TUSB_VERSION_MAJOR 0 #define TUSB_VERSION_MINOR 16 #define TUSB_VERSION_REVISION 0 +#define TUSB_VERSION_BUILD 1 + +#define TUSB_VERSION_NUMBER (TUSB_VERSION_MAJOR << 24 | TUSB_VERSION_MINOR << 16 | TUSB_VERSION_REVISION << 8 | TUSB_VERSION_BUILD) #define TUSB_VERSION_STRING TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION) //--------------------------------------------------------------------+ -- cgit v1.3.1 From 2cf171095e02d8562ff138520cbe686e013f4522 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 22 Mar 2024 12:30:14 +0700 Subject: code format --- src/common/tusb_fifo.h | 31 ++---- src/tusb.c | 277 ++++++++++++++++++------------------------------- 2 files changed, 113 insertions(+), 195 deletions(-) (limited to 'src') diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h index 2f60ec2f4..2d9f5e667 100644 --- a/src/common/tusb_fifo.h +++ b/src/common/tusb_fifo.h @@ -102,10 +102,8 @@ extern "C" { * | * ------------------------- * | R | 1 | 2 | W | 4 | 5 | - */ -typedef struct -{ +typedef struct { uint8_t* buffer ; // buffer pointer uint16_t depth ; // max items @@ -124,16 +122,14 @@ typedef struct } tu_fifo_t; -typedef struct -{ +typedef struct { uint16_t len_lin ; ///< linear length in item size uint16_t len_wrap ; ///< wrapped length in item size void * ptr_lin ; ///< linear part start pointer void * ptr_wrap ; ///< wrapped part start pointer } tu_fifo_buffer_info_t; -#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable) \ -{ \ +#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable){\ .buffer = _buffer, \ .depth = _depth, \ .item_size = sizeof(_type), \ @@ -144,23 +140,18 @@ typedef struct uint8_t _name##_buf[_depth*sizeof(_type)]; \ tu_fifo_t _name = TU_FIFO_INIT(_name##_buf, _depth, _type, _overwritable) - bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable); bool tu_fifo_clear(tu_fifo_t *f); bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable); #if OSAL_MUTEX_REQUIRED -TU_ATTR_ALWAYS_INLINE static inline -void tu_fifo_config_mutex(tu_fifo_t *f, osal_mutex_t wr_mutex, osal_mutex_t rd_mutex) -{ - f->mutex_wr = wr_mutex; - f->mutex_rd = rd_mutex; -} - + TU_ATTR_ALWAYS_INLINE static inline + void tu_fifo_config_mutex(tu_fifo_t *f, osal_mutex_t wr_mutex, osal_mutex_t rd_mutex) { + f->mutex_wr = wr_mutex; + f->mutex_rd = rd_mutex; + } #else - -#define tu_fifo_config_mutex(_f, _wr_mutex, _rd_mutex) - + #define tu_fifo_config_mutex(_f, _wr_mutex, _rd_mutex) #endif bool tu_fifo_write (tu_fifo_t* f, void const * p_data); @@ -182,8 +173,7 @@ bool tu_fifo_overflowed (tu_fifo_t* f); void tu_fifo_correct_read_pointer (tu_fifo_t* f); TU_ATTR_ALWAYS_INLINE static inline -uint16_t tu_fifo_depth(tu_fifo_t* f) -{ +uint16_t tu_fifo_depth(tu_fifo_t* f) { return f->depth; } @@ -198,7 +188,6 @@ void tu_fifo_advance_read_pointer (tu_fifo_t *f, uint16_t n); void tu_fifo_get_read_info (tu_fifo_t *f, tu_fifo_buffer_info_t *info); void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info); - #ifdef __cplusplus } #endif diff --git a/src/tusb.c b/src/tusb.c index 7c86f1ca5..2256dc3b9 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -43,32 +43,30 @@ // Public API //--------------------------------------------------------------------+ -bool tusb_init(void) -{ -#if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT) +bool tusb_init(void) { + #if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT) // init device stack CFG_TUSB_RHPORTx_MODE must be defined TU_ASSERT ( tud_init(TUD_OPT_RHPORT) ); -#endif + #endif -#if CFG_TUH_ENABLED && defined(TUH_OPT_RHPORT) + #if CFG_TUH_ENABLED && defined(TUH_OPT_RHPORT) // init host stack CFG_TUSB_RHPORTx_MODE must be defined TU_ASSERT( tuh_init(TUH_OPT_RHPORT) ); -#endif + #endif return true; } -bool tusb_inited(void) -{ +bool tusb_inited(void) { bool ret = false; -#if CFG_TUD_ENABLED + #if CFG_TUD_ENABLED ret = ret || tud_inited(); -#endif + #endif -#if CFG_TUH_ENABLED + #if CFG_TUH_ENABLED ret = ret || tuh_inited(); -#endif + #endif return ret; } @@ -77,30 +75,24 @@ bool tusb_inited(void) // Descriptor helper //--------------------------------------------------------------------+ -uint8_t const * tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1) -{ - while(desc+1 < end) - { - if ( desc[1] == byte1 ) return desc; +uint8_t const* tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1) { + while (desc + 1 < end) { + if (desc[1] == byte1) return desc; desc += desc[DESC_OFFSET_LEN]; } return NULL; } -uint8_t const * tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2) -{ - while(desc+2 < end) - { - if ( desc[1] == byte1 && desc[2] == byte2) return desc; +uint8_t const* tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2) { + while (desc + 2 < end) { + if (desc[1] == byte1 && desc[2] == byte2) return desc; desc += desc[DESC_OFFSET_LEN]; } return NULL; } -uint8_t const * tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3) -{ - while(desc+3 < end) - { +uint8_t const* tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3) { + while (desc + 3 < end) { if (desc[1] == byte1 && desc[2] == byte2 && desc[3] == byte3) return desc; desc += desc[DESC_OFFSET_LEN]; } @@ -146,83 +138,71 @@ bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex) { return ret; } -bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed) -{ +bool tu_edpt_validate(tusb_desc_endpoint_t const* desc_ep, tusb_speed_t speed) { uint16_t const max_packet_size = tu_edpt_packet_size(desc_ep); TU_LOG2(" Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, max_packet_size); - switch (desc_ep->bmAttributes.xfer) - { - case TUSB_XFER_ISOCHRONOUS: - { + switch (desc_ep->bmAttributes.xfer) { + case TUSB_XFER_ISOCHRONOUS: { uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 1023); TU_ASSERT(max_packet_size <= spec_size); + break; } - break; case TUSB_XFER_BULK: - if (speed == TUSB_SPEED_HIGH) - { + if (speed == TUSB_SPEED_HIGH) { // Bulk highspeed must be EXACTLY 512 TU_ASSERT(max_packet_size == 512); - }else - { + } else { // TODO Bulk fullspeed can only be 8, 16, 32, 64 TU_ASSERT(max_packet_size <= 64); } - break; + break; - case TUSB_XFER_INTERRUPT: - { + case TUSB_XFER_INTERRUPT: { uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 64); TU_ASSERT(max_packet_size <= spec_size); + break; } - break; - default: return false; + default: + return false; } return true; } -void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_itf, uint16_t desc_len, uint8_t driver_id) -{ +void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_itf, uint16_t desc_len, + uint8_t driver_id) { uint8_t const* p_desc = (uint8_t const*) desc_itf; uint8_t const* desc_end = p_desc + desc_len; - while( p_desc < desc_end ) - { - if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) ) - { + while (p_desc < desc_end) { + if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)) { uint8_t const ep_addr = ((tusb_desc_endpoint_t const*) p_desc)->bEndpointAddress; - TU_LOG(2, " Bind EP %02x to driver id %u\r\n", ep_addr, driver_id); ep2drv[tu_edpt_number(ep_addr)][tu_edpt_dir(ep_addr)] = driver_id; } - p_desc = tu_desc_next(p_desc); } } -uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len) -{ +uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len) { uint8_t const* p_desc = (uint8_t const*) desc_itf; uint16_t len = 0; - while (itf_count--) - { + while (itf_count--) { // Next on interface desc len += tu_desc_len(desc_itf); p_desc = tu_desc_next(p_desc); - while (len < max_len) - { + while (len < max_len) { // return on IAD regardless of itf count - if ( tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION ) return len; - - if ( (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) && - ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0 ) - { + if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION) { + return len; + } + if ((tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) && + ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0) { break; } @@ -239,8 +219,7 @@ uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, //--------------------------------------------------------------------+ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable, - void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize) -{ + void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize) { osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutex); (void) new_mutex; (void) is_tx; @@ -256,91 +235,72 @@ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool ove } TU_ATTR_ALWAYS_INLINE static inline -bool stream_claim(tu_edpt_stream_t* s) -{ - if (s->is_host) - { +bool stream_claim(tu_edpt_stream_t* s) { + if (s->is_host) { #if CFG_TUH_ENABLED return usbh_edpt_claim(s->daddr, s->ep_addr); #endif - }else - { + } else { #if CFG_TUD_ENABLED return usbd_edpt_claim(s->rhport, s->ep_addr); #endif } - return false; } TU_ATTR_ALWAYS_INLINE static inline -bool stream_xfer(tu_edpt_stream_t* s, uint16_t count) -{ - if (s->is_host) - { +bool stream_xfer(tu_edpt_stream_t* s, uint16_t count) { + if (s->is_host) { #if CFG_TUH_ENABLED return usbh_edpt_xfer(s->daddr, s->ep_addr, count ? s->ep_buf : NULL, count); #endif - }else - { + } else { #if CFG_TUD_ENABLED return usbd_edpt_xfer(s->rhport, s->ep_addr, count ? s->ep_buf : NULL, count); #endif } - return false; } TU_ATTR_ALWAYS_INLINE static inline -bool stream_release(tu_edpt_stream_t* s) -{ - if (s->is_host) - { +bool stream_release(tu_edpt_stream_t* s) { + if (s->is_host) { #if CFG_TUH_ENABLED return usbh_edpt_release(s->daddr, s->ep_addr); #endif - }else - { + } else { #if CFG_TUD_ENABLED return usbd_edpt_release(s->rhport, s->ep_addr); #endif } - return false; } //--------------------------------------------------------------------+ // Stream Write //--------------------------------------------------------------------+ - -bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes) -{ +bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes) { // ZLP condition: no pending data, last transferred bytes is multiple of packet size - TU_VERIFY( !tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (s->ep_packetsize-1))) ); - - TU_VERIFY( stream_claim(s) ); - TU_ASSERT( stream_xfer(s, 0) ); - + TU_VERIFY(!tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (s->ep_packetsize - 1)))); + TU_VERIFY(stream_claim(s)); + TU_ASSERT(stream_xfer(s, 0)); return true; } -uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s) -{ +uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s) { // skip if no data - TU_VERIFY( tu_fifo_count(&s->ff), 0 ); + TU_VERIFY(tu_fifo_count(&s->ff), 0); // Claim the endpoint - TU_VERIFY( stream_claim(s), 0 ); + TU_VERIFY(stream_claim(s), 0); // Pull data from FIFO -> EP buf uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize); - if ( count ) - { - TU_ASSERT( stream_xfer(s, count), 0 ); + if (count) { + TU_ASSERT(stream_xfer(s, count), 0); return count; - }else - { + } else { // Release endpoint since we don't make any transfer // Note: data is dropped if terminal is not connected stream_release(s); @@ -348,16 +308,13 @@ uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s) } } -uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize) -{ +uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const* buffer, uint32_t bufsize) { TU_VERIFY(bufsize); // TODO support ZLP - uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize); // flush if fifo has more than packet size or // in rare case: fifo depth is configured too small (which never reach packet size) - if ( (tu_fifo_count(&s->ff) >= s->ep_packetsize) || (tu_fifo_depth(&s->ff) < s->ep_packetsize) ) - { + if ((tu_fifo_count(&s->ff) >= s->ep_packetsize) || (tu_fifo_depth(&s->ff) < s->ep_packetsize)) { tu_edpt_stream_write_xfer(s); } @@ -367,9 +324,7 @@ uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t //--------------------------------------------------------------------+ // Stream Read //--------------------------------------------------------------------+ - -uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s) -{ +uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s) { uint16_t available = tu_fifo_remaining(&s->ff); // Prepare for incoming data but only allow what we can store in the ring buffer. @@ -384,25 +339,21 @@ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s) // get available again since fifo can be changed before endpoint is claimed available = tu_fifo_remaining(&s->ff); - if ( available >= s->ep_packetsize ) - { + if (available >= s->ep_packetsize) { // multiple of packet size limit by ep bufsize - uint16_t count = (uint16_t) (available & ~(s->ep_packetsize -1)); + uint16_t count = (uint16_t) (available & ~(s->ep_packetsize - 1)); count = tu_min16(count, s->ep_bufsize); - TU_ASSERT( stream_xfer(s, count), 0 ); - + TU_ASSERT(stream_xfer(s, count), 0); return count; - }else - { + } else { // Release endpoint since we don't make any transfer stream_release(s); return 0; } } -uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize) -{ +uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize) { uint32_t num_read = tu_fifo_read_n(&s->ff, buffer, (uint16_t) bufsize); tu_edpt_stream_read_xfer(s); return num_read; @@ -416,42 +367,35 @@ uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize #include #if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL || CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL - -char const* const tu_str_speed[] = { "Full", "Low", "High" }; -char const* const tu_str_std_request[] = -{ - "Get Status" , - "Clear Feature" , - "Reserved" , - "Set Feature" , - "Reserved" , - "Set Address" , - "Get Descriptor" , - "Set Descriptor" , - "Get Configuration" , - "Set Configuration" , - "Get Interface" , - "Set Interface" , - "Synch Frame" +char const* const tu_str_speed[] = {"Full", "Low", "High"}; +char const* const tu_str_std_request[] = { + "Get Status", + "Clear Feature", + "Reserved", + "Set Feature", + "Reserved", + "Set Address", + "Get Descriptor", + "Set Descriptor", + "Get Configuration", + "Set Configuration", + "Get Interface", + "Set Interface", + "Synch Frame" }; char const* const tu_str_xfer_result[] = { "OK", "FAILED", "STALLED", "TIMEOUT" }; - #endif -static void dump_str_line(uint8_t const* buf, uint16_t count) -{ +static void dump_str_line(uint8_t const* buf, uint16_t count) { tu_printf(" |"); - // each line is 16 bytes - for(uint16_t i=0; i Date: Fri, 22 Mar 2024 12:53:31 +0700 Subject: add tu_edpt_stream_deinit() --- src/common/tusb_private.h | 19 +++++++++---------- src/tusb.c | 11 ++++++++++- 2 files changed, 19 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h index db1ba974d..373a50256 100644 --- a/src/common/tusb_private.h +++ b/src/common/tusb_private.h @@ -60,7 +60,7 @@ typedef struct { tu_fifo_t ff; // mutex: read if ep rx, write if e tx - OSAL_MUTEX_DEF(ff_mutex); + OSAL_MUTEX_DEF(ff_mutexdef); }tu_edpt_stream_t; @@ -87,15 +87,17 @@ bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex); // Endpoint Stream //--------------------------------------------------------------------+ -// Init an stream, should only be called once +// Init an endpoint stream bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable, void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize); +// Deinit an endpoint stream +bool tu_edpt_stream_deinit(tu_edpt_stream_t* s); + // Open an stream for an endpoint // hwid is either device address (host mode) or rhport (device mode) TU_ATTR_ALWAYS_INLINE static inline -void tu_edpt_stream_open(tu_edpt_stream_t* s, uint8_t hwid, tusb_desc_endpoint_t const *desc_ep) -{ +void tu_edpt_stream_open(tu_edpt_stream_t* s, uint8_t hwid, tusb_desc_endpoint_t const *desc_ep) { tu_fifo_clear(&s->ff); s->hwid = hwid; s->ep_addr = desc_ep->bEndpointAddress; @@ -103,16 +105,14 @@ void tu_edpt_stream_open(tu_edpt_stream_t* s, uint8_t hwid, tusb_desc_endpoint_t } TU_ATTR_ALWAYS_INLINE static inline -void tu_edpt_stream_close(tu_edpt_stream_t* s) -{ +void tu_edpt_stream_close(tu_edpt_stream_t* s) { s->hwid = 0; s->ep_addr = 0; } // Clear fifo TU_ATTR_ALWAYS_INLINE static inline -bool tu_edpt_stream_clear(tu_edpt_stream_t* s) -{ +bool tu_edpt_stream_clear(tu_edpt_stream_t* s) { return tu_fifo_clear(&s->ff); } @@ -131,8 +131,7 @@ bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferr // Get the number of bytes available for writing TU_ATTR_ALWAYS_INLINE static inline -uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s) -{ +uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s) { return (uint32_t) tu_fifo_remaining(&s->ff); } diff --git a/src/tusb.c b/src/tusb.c index 2256dc3b9..074dcce96 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -220,7 +220,7 @@ uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable, void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize) { - osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutex); + osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutexdef); (void) new_mutex; (void) is_tx; @@ -234,6 +234,15 @@ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool ove return true; } +bool tu_edpt_stream_deinit(tu_edpt_stream_t* s) { + (void) s; + #if OSAL_MUTEX_REQUIRED + if (s->ff->mutex_wr) osal_mutex_delete(s->ff->mutex_wr); + if (s->ff->mutex_rd) osal_mutex_delete(s->ff->mutex_rd); + #endif + return true; +} + TU_ATTR_ALWAYS_INLINE static inline bool stream_claim(tu_edpt_stream_t* s) { if (s->is_host) { -- cgit v1.3.1 From 31f68495cf66706926c408ad15ea90a646c62198 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 22 Mar 2024 16:10:26 +0700 Subject: update osal API add osal_semaphore_delete(), osal_mutex_delete(), osal_queue_delete() --- src/osal/osal.h | 3 ++ src/osal/osal_freertos.h | 19 ++++++++- src/osal/osal_mynewt.h | 61 +++++++++++++-------------- src/osal/osal_none.h | 16 ++++++++ src/osal/osal_pico.h | 105 +++++++++++++++++++---------------------------- src/osal/osal_rtthread.h | 6 +-- src/osal/osal_rtx4.h | 61 ++++++++++++++------------- src/tusb.c | 4 +- 8 files changed, 147 insertions(+), 128 deletions(-) (limited to 'src') diff --git a/src/osal/osal.h b/src/osal/osal.h index f092e8ffb..8f45ea5c1 100644 --- a/src/osal/osal.h +++ b/src/osal/osal.h @@ -74,15 +74,18 @@ typedef void (*osal_task_func_t)( void * ); // Should be implemented as static inline function in osal_port.h header /* osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef); + bool osal_semaphore_delete(osal_semaphore_t semd_hdl); bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr); bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec); void osal_semaphore_reset(osal_semaphore_t sem_hdl); // TODO removed osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef); + bool osal_mutex_delete(osal_mutex_t mutex_hdl) bool osal_mutex_lock (osal_mutex_t sem_hdl, uint32_t msec); bool osal_mutex_unlock(osal_mutex_t mutex_hdl); osal_queue_t osal_queue_create(osal_queue_def_t* qdef); + bool osal_queue_delete(osal_queue_t qhdl); bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec); bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr); bool osal_queue_empty(osal_queue_t qhdl); diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index 501e0bddd..f1f05f353 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -24,8 +24,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef _TUSB_OSAL_FREERTOS_H_ -#define _TUSB_OSAL_FREERTOS_H_ +#ifndef TUSB_OSAL_FREERTOS_H_ +#define TUSB_OSAL_FREERTOS_H_ // FreeRTOS Headers #include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,FreeRTOS.h) @@ -114,6 +114,11 @@ TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_ #endif } +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) { + vSemaphoreDelete(semd_hdl); + return true; +} + TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) { if ( !in_isr ) { return xSemaphoreGive(sem_hdl) != 0; @@ -153,6 +158,11 @@ TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_de #endif } +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) { + vSemaphoreDelete(mutex_hdl); + return true; +} + TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) { return osal_semaphore_wait(mutex_hdl, msec); } @@ -181,6 +191,11 @@ TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_de return q; } +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) { + vQueueDelete(qhdl); + return true; +} + TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) { return xQueueReceive(qhdl, data, _osal_ms2tick(msec)); } diff --git a/src/osal/osal_mynewt.h b/src/osal/osal_mynewt.h index b8ea2087c..16def0d2a 100644 --- a/src/osal/osal_mynewt.h +++ b/src/osal/osal_mynewt.h @@ -36,8 +36,7 @@ //--------------------------------------------------------------------+ // TASK API //--------------------------------------------------------------------+ -TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { os_time_delay( os_time_ms_to_ticks32(msec) ); } @@ -47,25 +46,26 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) typedef struct os_sem osal_semaphore_def_t; typedef struct os_sem* osal_semaphore_t; -TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) { return (os_sem_init(semdef, 0) == OS_OK) ? (osal_semaphore_t) semdef : NULL; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) { + (void) semd_hdl; + return true; // nothing to do +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) { (void) in_isr; return os_sem_release(sem_hdl) == OS_OK; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) { uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? OS_TIMEOUT_NEVER : os_time_ms_to_ticks32(msec); return os_sem_pend(sem_hdl, ticks) == OS_OK; } -static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) -{ +static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) { // TODO implement later } @@ -75,19 +75,21 @@ static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) typedef struct os_mutex osal_mutex_def_t; typedef struct os_mutex* osal_mutex_t; -TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) { return (os_mutex_init(mdef) == OS_OK) ? (osal_mutex_t) mdef : NULL; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) { + (void) mutex_hdl; + return true; // nothing to do +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) { uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? OS_TIMEOUT_NEVER : os_time_ms_to_ticks32(msec); return os_mutex_pend(mutex_hdl, ticks) == OS_OK; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) { return os_mutex_release(mutex_hdl) == OS_OK; } @@ -101,8 +103,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd static struct os_event _name##_##evbuf[_depth];\ osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, .evbuf = _name##_##evbuf};\ -typedef struct -{ +typedef struct { uint16_t depth; uint16_t item_sz; void* buf; @@ -116,17 +117,20 @@ typedef struct typedef osal_queue_def_t* osal_queue_t; -TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) -{ - if ( OS_OK != os_mempool_init(&qdef->mpool, qdef->depth, qdef->item_sz, qdef->buf, "usbd queue") ) return NULL; - if ( OS_OK != os_mempool_init(&qdef->epool, qdef->depth, sizeof(struct os_event), qdef->evbuf, "usbd evqueue") ) return NULL; +TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) { + if ( OS_OK != os_mempool_init(&qdef->mpool, qdef->depth, qdef->item_sz, qdef->buf, "usb queue") ) return NULL; + if ( OS_OK != os_mempool_init(&qdef->epool, qdef->depth, sizeof(struct os_event), qdef->evbuf, "usb evqueue") ) return NULL; os_eventq_init(&qdef->evq); return (osal_queue_t) qdef; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) { + (void) qhdl; + return true; // nothing to do +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) { (void) msec; // os_eventq_get() does not take timeout, always behave as msec = WAIT_FOREVER struct os_event* ev; @@ -139,8 +143,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v return true; } -static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) -{ +static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) { (void) in_isr; // get a block from mem pool for data @@ -150,8 +153,7 @@ static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in // get a block from event pool to put into queue struct os_event* ev = (struct os_event*) os_memblock_get(&qhdl->epool); - if (!ev) - { + if (!ev) { os_memblock_put(&qhdl->mpool, ptr); return false; } @@ -163,8 +165,7 @@ static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in return true; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) { return STAILQ_EMPTY(&qhdl->evq.evq_list); } diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h index a07d39828..c954fcfe8 100644 --- a/src/osal/osal_none.h +++ b/src/osal/osal_none.h @@ -54,6 +54,12 @@ TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_ return semdef; } +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) { + (void) semd_hdl; + return true; // nothing to do +} + + TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) { (void) in_isr; sem_hdl->count++; @@ -90,6 +96,11 @@ TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_de return mdef; } +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) { + (void) mutex_hdl; + return true; // nothing to do +} + TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) { return osal_semaphore_wait(mutex_hdl, msec); } @@ -143,6 +154,11 @@ TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_de return (osal_queue_t) qdef; } +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) { + (void) qhdl; + return true; // nothing to do +} + TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) { (void) msec; // not used, always behave as msec = 0 diff --git a/src/osal/osal_pico.h b/src/osal/osal_pico.h index e6efa0968..00c589ef9 100644 --- a/src/osal/osal_pico.h +++ b/src/osal/osal_pico.h @@ -24,8 +24,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef _TUSB_OSAL_PICO_H_ -#define _TUSB_OSAL_PICO_H_ +#ifndef TUSB_OSAL_PICO_H_ +#define TUSB_OSAL_PICO_H_ #include "pico/time.h" #include "pico/sem.h" @@ -33,42 +33,42 @@ #include "pico/critical_section.h" #ifdef __cplusplus - extern "C" { +extern "C" { #endif //--------------------------------------------------------------------+ // TASK API //--------------------------------------------------------------------+ -TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { sleep_ms(msec); } //--------------------------------------------------------------------+ // Binary Semaphore API //--------------------------------------------------------------------+ -typedef struct semaphore osal_semaphore_def_t, *osal_semaphore_t; +typedef struct semaphore osal_semaphore_def_t, * osal_semaphore_t; -TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) { sem_init(semdef, 0, 255); return semdef; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) { + (void) semd_hdl; + return true; // nothing to do +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) { (void) in_isr; sem_release(sem_hdl); return true; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) { return sem_acquire_timeout_ms(sem_hdl, msec); } -TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) -{ +TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) { sem_reset(sem_hdl, 0); } @@ -76,21 +76,23 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t s // MUTEX API // Within tinyusb, mutex is never used in ISR context //--------------------------------------------------------------------+ -typedef struct mutex osal_mutex_def_t, *osal_mutex_t; +typedef struct mutex osal_mutex_def_t, * osal_mutex_t; -TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) { mutex_init(mdef); return mdef; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) { + (void) mutex_hdl; + return true; // nothing to do +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) { return mutex_enter_timeout_ms(mutex_hdl, msec); } -TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) { mutex_exit(mutex_hdl); return true; } @@ -100,75 +102,54 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd //--------------------------------------------------------------------+ #include "common/tusb_fifo.h" -typedef struct -{ - tu_fifo_t ff; - struct critical_section critsec; // osal_queue may be used in IRQs, so need critical section +typedef struct { + tu_fifo_t ff; + struct critical_section critsec; // osal_queue may be used in IRQs, so need critical section } osal_queue_def_t; typedef osal_queue_def_t* osal_queue_t; // role device/host is used by OS NONE for mutex (disable usb isr) only -#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \ +#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \ uint8_t _name##_buf[_depth*sizeof(_type)]; \ osal_queue_def_t _name = { \ .ff = TU_FIFO_INIT(_name##_buf, _depth, _type, false) \ } -// lock queue by disable USB interrupt -TU_ATTR_ALWAYS_INLINE static inline void _osal_q_lock(osal_queue_t qhdl) -{ - critical_section_enter_blocking(&qhdl->critsec); -} - -// unlock queue -TU_ATTR_ALWAYS_INLINE static inline void _osal_q_unlock(osal_queue_t qhdl) -{ - critical_section_exit(&qhdl->critsec); -} - -TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) { critical_section_init(&qdef->critsec); tu_fifo_clear(&qdef->ff); return (osal_queue_t) qdef; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) -{ - (void) msec; // not used, always behave as msec = 0 +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) { + osal_queue_def_t* qdef = (osal_queue_def_t*) qhdl; + critical_section_deinit(&qdef->critsec); + return true; +} - // TODO: revisit... docs say that mutexes are never used from IRQ context, - // however osal_queue_recieve may be. therefore my assumption is that - // the fifo mutex is not populated for queues used from an IRQ context - //assert(!qhdl->ff.mutex); +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) { + (void) msec; // not used, always behave as msec = 0 - _osal_q_lock(qhdl); + critical_section_enter_blocking(&qhdl->critsec); bool success = tu_fifo_read(&qhdl->ff, data); - _osal_q_unlock(qhdl); + critical_section_exit(&qhdl->critsec); return success; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) -{ - // TODO: revisit... docs say that mutexes are never used from IRQ context, - // however osal_queue_recieve may be. therefore my assumption is that - // the fifo mutex is not populated for queues used from an IRQ context - //assert(!qhdl->ff.mutex); +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const* data, bool in_isr) { (void) in_isr; - _osal_q_lock(qhdl); + critical_section_enter_blocking(&qhdl->critsec); bool success = tu_fifo_write(&qhdl->ff, data); - _osal_q_unlock(qhdl); + critical_section_exit(&qhdl->critsec); TU_ASSERT(success); - return success; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) { // TODO: revisit; whether this is true or not currently, tu_fifo_empty is a single // volatile read. @@ -178,7 +159,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) } #ifdef __cplusplus - } +} #endif -#endif /* _TUSB_OSAL_PICO_H_ */ +#endif diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h index d03b53bee..a8423086f 100644 --- a/src/osal/osal_rtthread.h +++ b/src/osal/osal_rtthread.h @@ -25,8 +25,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef _TUSB_OSAL_RTTHREAD_H_ -#define _TUSB_OSAL_RTTHREAD_H_ +#ifndef TUSB_OSAL_RTTHREAD_H_ +#define TUSB_OSAL_RTTHREAD_H_ // RT-Thread Headers #include "rtthread.h" @@ -133,4 +133,4 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) { } #endif -#endif /* _TUSB_OSAL_RTTHREAD_H_ */ +#endif diff --git a/src/osal/osal_rtx4.h b/src/osal/osal_rtx4.h index e443135e0..35909e4d6 100644 --- a/src/osal/osal_rtx4.h +++ b/src/osal/osal_rtx4.h @@ -25,8 +25,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef _TUSB_OSAL_RTX4_H_ -#define _TUSB_OSAL_RTX4_H_ +#ifndef TUSB_OSAL_RTX4_H_ +#define TUSB_OSAL_RTX4_H_ #include @@ -37,8 +37,7 @@ extern "C" { //--------------------------------------------------------------------+ // TASK API //--------------------------------------------------------------------+ -TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { uint16_t hi = msec >> 16; uint16_t lo = msec; while (hi--) { @@ -48,12 +47,13 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) } TU_ATTR_ALWAYS_INLINE static inline uint16_t msec2wait(uint32_t msec) { - if (msec == OSAL_TIMEOUT_WAIT_FOREVER) + if (msec == OSAL_TIMEOUT_WAIT_FOREVER) { return 0xFFFF; - else if (msec >= 0xFFFE) + } else if (msec >= 0xFFFE) { return 0xFFFE; - else + } else { return msec; + } } //--------------------------------------------------------------------+ @@ -67,6 +67,11 @@ TU_ATTR_ALWAYS_INLINE static inline OS_ID osal_semaphore_create(osal_semaphore_d return semdef; } +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) { + (void) semd_hdl; + return true; // nothing to do +} + TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) { if ( !in_isr ) { os_sem_send(sem_hdl); @@ -90,19 +95,21 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t c typedef OS_MUT osal_mutex_def_t; typedef OS_ID osal_mutex_t; -TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) { os_mut_init(mdef); return mdef; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) { + (void) mutex_hdl; + return true; // nothing to do +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) { return os_mut_wait(mutex_hdl, msec2wait(msec)) != OS_R_TMO; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) { return os_mut_release(mutex_hdl) == OS_R_OK; } @@ -116,9 +123,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd _declare_box(_name##__pool, sizeof(_type), _depth); \ osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .pool = _name##__pool, .mbox = _name##__mbox }; - -typedef struct -{ +typedef struct { uint16_t depth; uint16_t item_sz; U32* pool; @@ -127,15 +132,13 @@ typedef struct typedef osal_queue_def_t* osal_queue_t; -TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) { os_mbx_init(qdef->mbox, (qdef->depth + 4) * 4); _init_box(qdef->pool, ((qdef->item_sz+3)/4)*(qdef->depth) + 3, qdef->item_sz); return qdef; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) { void* buf; os_mbx_wait(qhdl->mbox, &buf, msec2wait(msec)); memcpy(data, buf, qhdl->item_sz); @@ -143,23 +146,23 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v return true; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) { + (void) qhdl; + return true; // nothing to do ? +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) { void* buf = _alloc_box(qhdl->pool); memcpy(buf, data, qhdl->item_sz); - if ( !in_isr ) - { + if ( !in_isr ) { os_mbx_send(qhdl->mbox, buf, 0xFFFF); - } - else - { + } else { isr_mbx_send(qhdl->mbox, buf); } return true; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) { return os_mbx_check(qhdl->mbox) == qhdl->depth; } diff --git a/src/tusb.c b/src/tusb.c index 074dcce96..0f09acb64 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -237,8 +237,8 @@ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool ove bool tu_edpt_stream_deinit(tu_edpt_stream_t* s) { (void) s; #if OSAL_MUTEX_REQUIRED - if (s->ff->mutex_wr) osal_mutex_delete(s->ff->mutex_wr); - if (s->ff->mutex_rd) osal_mutex_delete(s->ff->mutex_rd); + if (s->ff.mutex_wr) osal_mutex_delete(s->ff.mutex_wr); + if (s->ff.mutex_rd) osal_mutex_delete(s->ff.mutex_rd); #endif return true; } -- cgit v1.3.1 From e84c9f3e221092687808f175e1e19732a10fea72 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 22 Mar 2024 16:12:57 +0700 Subject: implement tuh_init() change usbh driver init() return type from void to bool --- src/class/cdc/cdc_host.c | 12 +++++-- src/class/cdc/cdc_host.h | 2 +- src/class/hid/hid_host.c | 4 ++- src/class/hid/hid_host.h | 2 +- src/class/msc/msc_host.c | 5 +-- src/class/msc/msc_host.h | 2 +- src/host/hub.c | 3 +- src/host/hub.h | 12 +++---- src/host/usbh.c | 85 ++++++++++++++++++++++++++++++------------------ src/host/usbh_pvt.h | 2 +- 10 files changed, 79 insertions(+), 50 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 14f380b40..5bdd41f1f 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -621,12 +621,11 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, // CLASS-USBH API //--------------------------------------------------------------------+ -void cdch_init(void) { +bool cdch_init(void) { + TU_LOG_DRV("sizeof(cdch_interface_t) = %u\r\n", sizeof(cdch_interface_t)); tu_memclr(cdch_data, sizeof(cdch_data)); - for (size_t i = 0; i < CFG_TUH_CDC; i++) { cdch_interface_t* p_cdc = &cdch_data[i]; - tu_edpt_stream_init(&p_cdc->stream.tx, true, true, false, p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE, p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE); @@ -635,9 +634,16 @@ void cdch_init(void) { p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE, p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE); } + + return true; } bool cdch_deinit(void) { + for (size_t i = 0; i < CFG_TUH_CDC; i++) { + cdch_interface_t* p_cdc = &cdch_data[i]; + tu_edpt_stream_deinit(&p_cdc->stream.tx); + tu_edpt_stream_deinit(&p_cdc->stream.rx); + } return true; } diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 7530b1e9d..b63dd1530 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -192,7 +192,7 @@ TU_ATTR_WEAK extern void tuh_cdc_tx_complete_cb(uint8_t idx); //--------------------------------------------------------------------+ // Internal Class Driver API //--------------------------------------------------------------------+ -void cdch_init (void); +bool cdch_init (void); bool cdch_deinit (void); bool cdch_open (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); bool cdch_set_config (uint8_t dev_addr, uint8_t itf_num); diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 16e2d3c2c..efc54656e 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -372,8 +372,10 @@ bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const vo //--------------------------------------------------------------------+ // USBH API //--------------------------------------------------------------------+ -void hidh_init(void) { +bool hidh_init(void) { + TU_LOG_DRV("sizeof(hidh_interface_t) = %u\r\n", sizeof(hidh_interface_t)); tu_memclr(_hidh_itf, sizeof(_hidh_itf)); + return true; } bool hidh_deinit(void) { diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h index 9ea222b3d..0902bf1af 100644 --- a/src/class/hid/hid_host.h +++ b/src/class/hid/hid_host.h @@ -163,7 +163,7 @@ TU_ATTR_WEAK void tuh_hid_set_protocol_complete_cb(uint8_t dev_addr, uint8_t idx //--------------------------------------------------------------------+ // Internal Class Driver API //--------------------------------------------------------------------+ -void hidh_init(void); +bool hidh_init(void); bool hidh_deinit(void); bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const* desc_itf, uint16_t max_len); bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num); diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c index 61ecb8e4e..ce6e7fb2d 100644 --- a/src/class/msc/msc_host.c +++ b/src/class/msc/msc_host.c @@ -284,15 +284,16 @@ bool tuh_msc_reset(uint8_t dev_addr) { //--------------------------------------------------------------------+ // CLASS-USBH API //--------------------------------------------------------------------+ -void msch_init(void) { +bool msch_init(void) { + TU_LOG_DRV("sizeof(msch_interface_t) = %u\r\n", sizeof(msch_interface_t)); tu_memclr(_msch_itf, sizeof(_msch_itf)); + return true; } bool msch_deinit(void) { return true; } - void msch_close(uint8_t dev_addr) { TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX,); msch_interface_t* p_msc = get_itf(dev_addr); diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h index 5bf2e62e3..9fda566d8 100644 --- a/src/class/msc/msc_host.h +++ b/src/class/msc/msc_host.h @@ -113,7 +113,7 @@ TU_ATTR_WEAK void tuh_msc_umount_cb(uint8_t dev_addr); // Internal Class Driver API //--------------------------------------------------------------------+ -void msch_init (void); +bool msch_init (void); bool msch_deinit (void); bool msch_open (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len); bool msch_set_config (uint8_t dev_addr, uint8_t itf_num); diff --git a/src/host/hub.c b/src/host/hub.c index 0853ff27a..e97014443 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -182,8 +182,9 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, //--------------------------------------------------------------------+ // CLASS-USBH API (don't require to verify parameters) //--------------------------------------------------------------------+ -void hub_init(void) { +bool hub_init(void) { tu_memclr(hub_data, sizeof(hub_data)); + return true; } bool hub_deinit(void) { diff --git a/src/host/hub.h b/src/host/hub.h index c3f4a3612..385efe6b2 100644 --- a/src/host/hub.h +++ b/src/host/hub.h @@ -187,16 +187,14 @@ bool hub_port_get_status (uint8_t hub_addr, uint8_t hub_port, void* resp, bool hub_edpt_status_xfer(uint8_t dev_addr); // Reset a port -static inline bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +TU_ATTR_ALWAYS_INLINE static inline +bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return hub_port_set_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET, complete_cb, user_data); } // Clear Reset Change -static inline bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_port, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +TU_ATTR_ALWAYS_INLINE static inline +bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_port, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return hub_port_clear_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET_CHANGE, complete_cb, user_data); } @@ -204,7 +202,7 @@ static inline bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_por //--------------------------------------------------------------------+ // Internal Class Driver API //--------------------------------------------------------------------+ -void hub_init (void); +bool hub_init (void); bool hub_deinit (void); bool hub_open (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); bool hub_set_config (uint8_t dev_addr, uint8_t itf_num); diff --git a/src/host/usbh.c b/src/host/usbh.c index cf348bbb2..1edc43fd6 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -351,51 +351,55 @@ bool tuh_inited(void) { bool tuh_init(uint8_t rhport) { // skip if already initialized - if ( tuh_inited() ) return true; + if (tuh_rhport_is_active(rhport)) return true; TU_LOG_USBH("USBH init on controller %u\r\n", rhport); - TU_LOG_INT_USBH(sizeof(usbh_device_t)); - TU_LOG_INT_USBH(sizeof(hcd_event_t)); - TU_LOG_INT_USBH(sizeof(_ctrl_xfer)); - TU_LOG_INT_USBH(sizeof(tuh_xfer_t)); - TU_LOG_INT_USBH(sizeof(tu_fifo_t)); - TU_LOG_INT_USBH(sizeof(tu_edpt_stream_t)); - // Event queue - _usbh_q = osal_queue_create( &_usbh_qdef ); - TU_ASSERT(_usbh_q != NULL); + // Init host stack if not already + if (!tuh_inited()) { + TU_LOG_INT_USBH(sizeof(usbh_device_t)); + TU_LOG_INT_USBH(sizeof(hcd_event_t)); + TU_LOG_INT_USBH(sizeof(_ctrl_xfer)); + TU_LOG_INT_USBH(sizeof(tuh_xfer_t)); + TU_LOG_INT_USBH(sizeof(tu_fifo_t)); + TU_LOG_INT_USBH(sizeof(tu_edpt_stream_t)); + + // Event queue + _usbh_q = osal_queue_create(&_usbh_qdef); + TU_ASSERT(_usbh_q != NULL); #if OSAL_MUTEX_REQUIRED - // Init mutex - _usbh_mutex = osal_mutex_create(&_usbh_mutexdef); - TU_ASSERT(_usbh_mutex); + // Init mutex + _usbh_mutex = osal_mutex_create(&_usbh_mutexdef); + TU_ASSERT(_usbh_mutex); #endif - // Get application driver if available - if ( usbh_app_driver_get_cb ) { - _app_driver = usbh_app_driver_get_cb(&_app_driver_count); - } + // Get application driver if available + if (usbh_app_driver_get_cb) { + _app_driver = usbh_app_driver_get_cb(&_app_driver_count); + } - // Device - tu_memclr(&_dev0, sizeof(_dev0)); - tu_memclr(_usbh_devices, sizeof(_usbh_devices)); - tu_memclr(&_ctrl_xfer, sizeof(_ctrl_xfer)); + // Device + tu_memclr(&_dev0, sizeof(_dev0)); + tu_memclr(_usbh_devices, sizeof(_usbh_devices)); + tu_memclr(&_ctrl_xfer, sizeof(_ctrl_xfer)); - for(uint8_t i=0; iname); - driver->init(); + // Class drivers + for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) { + usbh_class_driver_t const* driver = get_driver(drv_id); + if (driver) { + TU_LOG_USBH("%s init\r\n", driver->name); + driver->init(); + } } } + // Init host controller _usbh_controller = rhport;; - TU_ASSERT(hcd_init(rhport)); hcd_int_enable(rhport); @@ -405,14 +409,31 @@ bool tuh_init(uint8_t rhport) { bool tuh_deinit(uint8_t rhport) { if (!tuh_rhport_is_active(rhport)) return true; + // deinit host controller hcd_int_disable(rhport); hcd_deinit(rhport); _usbh_controller = TUSB_INDEX_INVALID_8; - // no other controller is active, deinit the stack + // deinit host stack if no controller is active if (!tuh_inited()) { + // Class drivers + for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) { + usbh_class_driver_t const* driver = get_driver(drv_id); + if (driver) { + TU_LOG_USBH("%s deinit\r\n", driver->name); + driver->deinit(); + } + } + + osal_queue_delete(_usbh_q); + _usbh_q = NULL; + #if OSAL_MUTEX_REQUIRED + // TODO make sure there is no task waiting on this mutex + osal_mutex_delete(_usbh_mutex); + _usbh_mutex = NULL; + #endif } return true; diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h index 204315175..95de915e9 100644 --- a/src/host/usbh_pvt.h +++ b/src/host/usbh_pvt.h @@ -51,7 +51,7 @@ enum { typedef struct { char const* name; - void (* const init )(void); + bool (* const init )(void); bool (* const deinit )(void); bool (* const open )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); bool (* const set_config )(uint8_t dev_addr, uint8_t itf_num); -- cgit v1.3.1 From a7a65e5d6d43fbb0c07eb82b3ab9fd8286dd3013 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 25 Mar 2024 18:30:03 +0700 Subject: add delete API for rtthread --- src/osal/osal_rtthread.h | 54 +++++++++++++++++++++++++++++------------------- 1 file changed, 33 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h index a8423086f..c27814835 100644 --- a/src/osal/osal_rtthread.h +++ b/src/osal/osal_rtthread.h @@ -48,23 +48,27 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { typedef struct rt_semaphore osal_semaphore_def_t; typedef rt_sem_t osal_semaphore_t; -TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t -osal_semaphore_create(osal_semaphore_def_t *semdef) { - rt_sem_init(semdef, "tusb", 0, RT_IPC_FLAG_PRIO); - return semdef; +TU_ATTR_ALWAYS_INLINE static inline +osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) { + rt_sem_init(semdef, "tusb", 0, RT_IPC_FLAG_PRIO); + return semdef; +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) { + return RT_EOK == rt_sem_detach(semd_hdl); } TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) { - (void) in_isr; - return rt_sem_release(sem_hdl) == RT_EOK; + (void) in_isr; + return rt_sem_release(sem_hdl) == RT_EOK; } TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) { - return rt_sem_take(sem_hdl, rt_tick_from_millisecond((rt_int32_t) msec)) == RT_EOK; + return rt_sem_take(sem_hdl, rt_tick_from_millisecond((rt_int32_t) msec)) == RT_EOK; } TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) { - rt_sem_control(sem_hdl, RT_IPC_CMD_RESET, 0); + rt_sem_control(sem_hdl, RT_IPC_CMD_RESET, 0); } //--------------------------------------------------------------------+ @@ -74,16 +78,20 @@ typedef struct rt_mutex osal_mutex_def_t; typedef rt_mutex_t osal_mutex_t; TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) { - rt_mutex_init(mdef, "tusb", RT_IPC_FLAG_PRIO); - return mdef; + rt_mutex_init(mdef, "tusb", RT_IPC_FLAG_PRIO); + return mdef; +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) { + return RT_EOK == rt_mutex_detach(mutex_hdl); } TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) { - return rt_mutex_take(mutex_hdl, rt_tick_from_millisecond((rt_int32_t) msec)) == RT_EOK; + return rt_mutex_take(mutex_hdl, rt_tick_from_millisecond((rt_int32_t) msec)) == RT_EOK; } TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) { - return rt_mutex_release(mutex_hdl) == RT_EOK; + return rt_mutex_release(mutex_hdl) == RT_EOK; } //--------------------------------------------------------------------+ @@ -106,27 +114,31 @@ typedef struct { typedef rt_mq_t osal_queue_t; TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef) { - rt_mq_init(&(qdef->sq), "tusb", qdef->buf, qdef->item_sz, - qdef->item_sz * qdef->depth, RT_IPC_FLAG_PRIO); - return &(qdef->sq); + rt_mq_init(&(qdef->sq), "tusb", qdef->buf, qdef->item_sz, + qdef->item_sz * qdef->depth, RT_IPC_FLAG_PRIO); + return &(qdef->sq); +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) { + return RT_EOK == rt_mq_detach(qhdl); } TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void *data, uint32_t msec) { - rt_tick_t tick = rt_tick_from_millisecond((rt_int32_t) msec); + rt_tick_t tick = rt_tick_from_millisecond((rt_int32_t) msec); #if RT_VERSION_MAJOR >= 5 - return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) > 0; + return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) > 0; #else - return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) == RT_EOK; + return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) == RT_EOK; #endif /* RT_VERSION_MAJOR >= 5 */ } TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) { - (void) in_isr; - return rt_mq_send(qhdl, (void *)data, qhdl->msg_size) == RT_EOK; + (void) in_isr; + return rt_mq_send(qhdl, (void *)data, qhdl->msg_size) == RT_EOK; } TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) { - return (qhdl->entry) == 0; + return (qhdl->entry) == 0; } #ifdef __cplusplus -- cgit v1.3.1 From 0610070d07babf3623016603325afa938d4fc9f7 Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Mon, 25 Mar 2024 18:44:51 +0700 Subject: Update dcd_stm32_fsdev_pvt_st.h --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index e0df21860..5a129ecf8 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -296,17 +296,14 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USB { #ifdef FSDEV_BUS_32BIT (void) USBx; - volatile uint32_t count = 10; - /* - WA: few cycles for RX PMA descriptor to update - This workaround is ported from stm32h5xx_hal_pcd.h : PCD_GET_EP_RX_CNT H5 - This code fixes an issue when the code is compiled in GCC with a fast optimization(O2/O3) and device with an high frequency. - The function doesn't return the correct value. - Issue observed on Windows 10 and stm32h573i_dk and tud_task() scheduled by IT, the device is not migrated the USB device is not visible . + /* WA: few cycles for RX PMA descriptor to update, otherwise doesn't return the correct value. + Note: required for G0, U5, H5 etc. + This workaround is ported from stm32h5xx_hal_pcd.h and fixes the issue when calling this function fast enough. + Reproduced with GCC ast optimization(O2/O3) and stm32h573i_dk with an high frequency. + Observed on Windows 10 where tud_task() is scheduled by interrupt handler. */ - while (count > 0U) - { - asm("NOP"); + volatile uint32_t count = 10; // defined as PCD_RX_PMA_CNT in stm32 hal_driver + while (count > 0U) { count--; } return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16; -- cgit v1.3.1 From 29f016ae15eb94654748bf29b81557f6ab611384 Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Mon, 25 Mar 2024 18:59:05 +0700 Subject: fix pre-commit --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 5a129ecf8..ade64b4fb 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -297,9 +297,9 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USB #ifdef FSDEV_BUS_32BIT (void) USBx; /* WA: few cycles for RX PMA descriptor to update, otherwise doesn't return the correct value. - Note: required for G0, U5, H5 etc. + Note: required for G0, U5, H5 etc. This workaround is ported from stm32h5xx_hal_pcd.h and fixes the issue when calling this function fast enough. - Reproduced with GCC ast optimization(O2/O3) and stm32h573i_dk with an high frequency. + Reproduced with GCC ast optimization(O2/O3) and stm32h573i_dk with an high frequency. Observed on Windows 10 where tud_task() is scheduled by interrupt handler. */ volatile uint32_t count = 10; // defined as PCD_RX_PMA_CNT in stm32 hal_driver -- cgit v1.3.1 From fbb20373c1b22c8eb1aed4fa95972c851be819f3 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Mar 2024 10:26:42 +0700 Subject: implement hcd_deinit() for max3421 --- src/portable/analog/max3421/hcd_max3421.c | 35 ++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index cc4799dd6..d70cf7208 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -321,35 +321,35 @@ static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_is } //------------- register write helper -------------// -static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) { +TU_ATTR_ALWAYS_INLINE static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) { reg_write(rhport, HIRQ_ADDR, data, in_isr); // HIRQ write 1 is clear _hcd_data.hirq &= (uint8_t) ~data; } -static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) { +TU_ATTR_ALWAYS_INLINE static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) { _hcd_data.hien = data; reg_write(rhport, HIEN_ADDR, data, in_isr); } -static inline void mode_write(uint8_t rhport, uint8_t data, bool in_isr) { +TU_ATTR_ALWAYS_INLINE static inline void mode_write(uint8_t rhport, uint8_t data, bool in_isr) { _hcd_data.mode = data; reg_write(rhport, MODE_ADDR, data, in_isr); } -static inline void peraddr_write(uint8_t rhport, uint8_t data, bool in_isr) { +TU_ATTR_ALWAYS_INLINE static inline void peraddr_write(uint8_t rhport, uint8_t data, bool in_isr) { if ( _hcd_data.peraddr == data ) return; // no need to change address _hcd_data.peraddr = data; reg_write(rhport, PERADDR_ADDR, data, in_isr); } -static inline void hxfr_write(uint8_t rhport, uint8_t data, bool in_isr) { +TU_ATTR_ALWAYS_INLINE static inline void hxfr_write(uint8_t rhport, uint8_t data, bool in_isr) { _hcd_data.hxfr = data; reg_write(rhport, HXFR_ADDR, data, in_isr); } -static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) { +TU_ATTR_ALWAYS_INLINE static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) { _hcd_data.sndbc = data; reg_write(rhport, SNDBC_ADDR, data, in_isr); } @@ -449,7 +449,7 @@ bool hcd_init(uint8_t rhport) { // full duplex, interrupt negative edge reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false); - // V1 is 0x01, V2 is 0x12, V3 is 0x13 + // v1 is 0x01, v2 is 0x12, v3 is 0x13 uint8_t const revision = reg_read(rhport, REVISION_ADDR, false); TU_ASSERT(revision == 0x01 || revision == 0x12 || revision == 0x13, false); TU_LOG2_HEX(revision); @@ -481,6 +481,24 @@ bool hcd_init(uint8_t rhport) { return true; } +bool hcd_deinit(uint8_t rhport) { + (void) rhport; + + // disable interrupt + tuh_max3421_int_api(rhport, false); + + // reset max3421 + reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false); + reg_write(rhport, USBCTL_ADDR, 0, false); + + #if OSAL_MUTEX_REQUIRED + osal_mutex_delete(_hcd_data.spi_mutex); + _hcd_data.spi_mutex = NULL; + #endif + + return true; +} + // Enable USB interrupt // Not actually enable GPIO interrupt, just set variable to prevent handler to process void hcd_int_enable (uint8_t rhport) { @@ -598,7 +616,8 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { hxfr_write(rhport, hxfr, in_isr); } -TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { +TU_ATTR_ALWAYS_INLINE static inline +void xact_inout(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { if (ep->ep_num == 0 ) { // setup if (ep->is_setup) { -- cgit v1.3.1 From 0da1da942a735bcac7b48786a511a38b02519e88 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 28 Mar 2024 16:32:02 +0700 Subject: enhance hub removal using while loop to unroll recursive instead of event queue. --- src/host/usbh.c | 117 +++++++++++++++++++++++++++----------------------------- 1 file changed, 57 insertions(+), 60 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 1edc43fd6..71691fad6 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1138,43 +1138,42 @@ bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt, TU_VERIFY(_async_func(__VA_ARGS__, NULL, (uintptr_t) &result), XFER_RESULT_TIMEOUT); \ return (uint8_t) result -uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len) -{ +uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, + void* buffer, uint16_t len) { _CONTROL_SYNC_API(tuh_descriptor_get, daddr, type, index, buffer, len); } -uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len) -{ +uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len) { _CONTROL_SYNC_API(tuh_descriptor_get_device, daddr, buffer, len); } -uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, void* buffer, uint16_t len) -{ +uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, + void* buffer, uint16_t len) { _CONTROL_SYNC_API(tuh_descriptor_get_configuration, daddr, index, buffer, len); } -uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len) -{ +uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, + void* buffer, uint16_t len) { _CONTROL_SYNC_API(tuh_descriptor_get_hid_report, daddr, itf_num, desc_type, index, buffer, len); } -uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len) -{ +uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, + void* buffer, uint16_t len) { _CONTROL_SYNC_API(tuh_descriptor_get_string, daddr, index, language_id, buffer, len); } -uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len) -{ +uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, + void* buffer, uint16_t len) { _CONTROL_SYNC_API(tuh_descriptor_get_manufacturer_string, daddr, language_id, buffer, len); } -uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len) -{ +uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, + void* buffer, uint16_t len) { _CONTROL_SYNC_API(tuh_descriptor_get_product_string, daddr, language_id, buffer, len); } -uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len) -{ +uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, + void* buffer, uint16_t len) { _CONTROL_SYNC_API(tuh_descriptor_get_serial_string, daddr, language_id, buffer, len); } @@ -1210,57 +1209,55 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_hub_addr(uint8_t daddr) { static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) { //------------- find the all devices (star-network) under port that is unplugged -------------// // TODO mark as disconnected in ISR, also handle dev0 + uint32_t removing_hubs = 0; + do { + for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) { + usbh_device_t* dev = &_usbh_devices[dev_id]; + uint8_t const daddr = dev_id + 1; + + // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub + if (dev->rhport == rhport && dev->connected && + (hub_addr == 0 || dev->hub_addr == hub_addr) && + (hub_port == 0 || dev->hub_port == hub_port)) { + TU_LOG_USBH("Device unplugged address = %u\r\n", daddr); + + if (is_hub_addr(daddr)) { + TU_LOG_USBH(" is a HUB device %u\r\n", daddr); + // marking this hub to run the loop on its children next (unroll recursive) + removing_hubs |= TU_BIT(dev_id - CFG_TUH_DEVICE_MAX); + } else { + // Invoke callback before closing driver (maybe call it later ?) + if (tuh_umount_cb) tuh_umount_cb(daddr); + } -#if 0 - // index as hub addr, value is hub port (0xFF for invalid) - uint8_t removing_hubs[CFG_TUH_HUB]; - memset(removing_hubs, TUSB_INDEX_INVALID_8, sizeof(removing_hubs)); - - removing_hubs[hub_addr-CFG_TUH_DEVICE_MAX] = hub_port; + // Close class driver + for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) { + usbh_class_driver_t const* driver = get_driver(drv_id); + if (driver) driver->close(daddr); + } - // consecutive non-removing hub - uint8_t nop_count = 0; -#endif + hcd_device_close(rhport, daddr); + clear_device(dev); - for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) { - usbh_device_t *dev = &_usbh_devices[dev_id]; - uint8_t const daddr = dev_id + 1; - - // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub - if (dev->rhport == rhport && dev->connected && - (hub_addr == 0 || dev->hub_addr == hub_addr) && - (hub_port == 0 || dev->hub_port == hub_port)) { - TU_LOG_USBH("Device unplugged address = %u\r\n", daddr); - - if (is_hub_addr(daddr)) { - TU_LOG_USBH(" is a HUB device %u\r\n", daddr); - - // Submit removed event If the device itself is a hub (un-rolled recursive) - // TODO a better to unroll recursrive is using array of removing_hubs and mark it here - hcd_event_t event; - event.rhport = rhport; - event.event_id = HCD_EVENT_DEVICE_REMOVE; - event.connection.hub_addr = daddr; - event.connection.hub_port = 0; - - hcd_event_handler(&event, false); - } else { - // Invoke callback before closing driver (maybe call it later ?) - if (tuh_umount_cb) tuh_umount_cb(daddr); + // abort on-going control xfer on this device if any + if (_ctrl_xfer.daddr == daddr) _set_control_xfer_stage(CONTROL_STAGE_IDLE); } + } - // Close class driver - for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) { - usbh_class_driver_t const * driver = get_driver(drv_id); - if ( driver ) driver->close(daddr); - } + if (removing_hubs == 0) break; + + // find the next hub to process + for (uint8_t h_id = 0; h_id < CFG_TUH_HUB; h_id++) { + if (tu_bit_test(removing_hubs, h_id)) { + removing_hubs &= ~TU_BIT(h_id); - hcd_device_close(rhport, daddr); - clear_device(dev); - // abort on-going control xfer if any - if (_ctrl_xfer.daddr == daddr) _set_control_xfer_stage(CONTROL_STAGE_IDLE); + // update hub_addr and hub_port for next loop + hub_addr = h_id + 1 + CFG_TUH_DEVICE_MAX; + hub_port = 0; + break; + } } - } + } while(1); } //--------------------------------------------------------------------+ -- cgit v1.3.1 From 3dcb7362aa8f0e710157da4b28be44abb2c26230 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 28 Mar 2024 19:18:20 +0700 Subject: fix build when CFG_TUH_HUB == 0 --- src/host/usbh.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 71691fad6..f2dc2f7c1 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1219,11 +1219,10 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu if (dev->rhport == rhport && dev->connected && (hub_addr == 0 || dev->hub_addr == hub_addr) && (hub_port == 0 || dev->hub_port == hub_port)) { - TU_LOG_USBH("Device unplugged address = %u\r\n", daddr); + TU_LOG_USBH("[%u:%u:%u] unplugged address = %u\r\n", rhport, hub_addr, hub_port, daddr); if (is_hub_addr(daddr)) { TU_LOG_USBH(" is a HUB device %u\r\n", daddr); - // marking this hub to run the loop on its children next (unroll recursive) removing_hubs |= TU_BIT(dev_id - CFG_TUH_DEVICE_MAX); } else { // Invoke callback before closing driver (maybe call it later ?) @@ -1244,9 +1243,11 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu } } + // if removing a hub, we need to remove its downstream devices + #if CFG_TUH_HUB if (removing_hubs == 0) break; - // find the next hub to process + // find a marked hub to process for (uint8_t h_id = 0; h_id < CFG_TUH_HUB; h_id++) { if (tu_bit_test(removing_hubs, h_id)) { removing_hubs &= ~TU_BIT(h_id); @@ -1257,6 +1258,10 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu break; } } + #else + (void) removing_hubs; + break; + #endif } while(1); } -- cgit v1.3.1 From d50003e33d89740c0993ae236629392df82453c2 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Wed, 27 Mar 2024 11:21:13 -0700 Subject: Fake unplug devices when a root hub is deinit --- src/host/usbh.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index f2dc2f7c1..29c6eb1e9 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -415,6 +415,15 @@ bool tuh_deinit(uint8_t rhport) { _usbh_controller = TUSB_INDEX_INVALID_8; + // "unplug" all devices on this rhport + for (uint8_t idx = 0; idx < CFG_TUH_DEVICE_MAX + CFG_TUH_HUB; idx++) { + usbh_device_t *dev = &_usbh_devices[idx]; + if (!dev->connected || dev->rhport != rhport) { + continue; + } + process_removing_device(rhport, dev->hub_addr, dev->hub_port); + } + // deinit host stack if no controller is active if (!tuh_inited()) { // Class drivers -- cgit v1.3.1 From ddb1034a9c77d8ef4efccf3df76013f86efe5e09 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 28 Mar 2024 21:45:52 +0700 Subject: use hub_addr=0, hub_port=0 for removing root hub port --- src/host/usbh.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 29c6eb1e9..05091736e 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -412,17 +412,10 @@ bool tuh_deinit(uint8_t rhport) { // deinit host controller hcd_int_disable(rhport); hcd_deinit(rhport); - _usbh_controller = TUSB_INDEX_INVALID_8; - // "unplug" all devices on this rhport - for (uint8_t idx = 0; idx < CFG_TUH_DEVICE_MAX + CFG_TUH_HUB; idx++) { - usbh_device_t *dev = &_usbh_devices[idx]; - if (!dev->connected || dev->rhport != rhport) { - continue; - } - process_removing_device(rhport, dev->hub_addr, dev->hub_port); - } + // "unplug" all devices on this rhport (hub_addr = 0, hub_port = 0) + process_removing_device(rhport, 0, 0); // deinit host stack if no controller is active if (!tuh_inited()) { -- cgit v1.3.1 From b9400df4c8bd49f1dd1e3047ca2a2c0284fa785e Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 29 Mar 2024 11:23:36 +0700 Subject: fix rp2 debug build with level 3 --- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 08aef9314..b351a9a07 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -113,7 +113,7 @@ static void __tusb_irq_path_func(_handle_buff_status_bit)(uint bit, struct hw_en static void __tusb_irq_path_func(hw_handle_buff_status)(void) { uint32_t remaining_buffers = usb_hw->buf_status; - pico_trace("buf_status 0x%08x\n", remaining_buffers); + pico_trace("buf_status 0x%08lx\n", remaining_buffers); // Check EPX first uint bit = 0b1; @@ -325,10 +325,8 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t ep->wMaxPacketSize = wMaxPacketSize; ep->transfer_type = transfer_type; - pico_trace("hw_endpoint_init dev %d ep %d %s xfer %d\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), - ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->transfer_type); - pico_trace("dev %d ep %d %s setup buffer @ 0x%p\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), - ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->hw_data_buf); + pico_trace("hw_endpoint_init dev %d ep %02X xfer %d\n", ep->dev_addr, ep->ep_addr, ep->transfer_type); + pico_trace("dev %d ep %02X setup buffer @ 0x%p\n", ep->dev_addr, ep->ep_addr, ep->hw_data_buf); uint dpram_offset = hw_data_offset(ep->hw_data_buf); // Bits 0-5 should be 0 assert(!(dpram_offset & 0b111111)); @@ -343,7 +341,7 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t ep_reg |= (uint32_t) ((bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB); } *ep->endpoint_control = ep_reg; - pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg); + pico_trace("endpoint control (0x%p) <- 0x%lx\n", ep->endpoint_control, ep_reg); ep->configured = true; if ( ep != &epx ) -- cgit v1.3.1 From cab11064160deab42af654cd766bbfaca7f688cd Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Tue, 21 Nov 2023 18:06:57 +0100 Subject: dwc2: add endpoint allocation support. --- src/class/audio/audio_device.c | 4 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 102 ++++++++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 4adc558a6..293defd96 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -96,8 +96,8 @@ #define USE_LINEAR_BUFFER 1 #endif -// Temporarily put the check here for stm32_fsdev -#ifdef TUP_USBIP_FSDEV +// Temporarily put the check here +#if defined(TUP_USBIP_FSDEV) || defined(TUP_USBIP_DWC2) #define USE_ISO_EP_ALLOCATION 1 #else #define USE_ISO_EP_ALLOCATION 0 diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 3f00243e5..b0149a9a9 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -648,6 +648,108 @@ void dcd_edpt_close_all(uint8_t rhport) { _allocated_fifo_words_tx = 16; } +bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) +{ + (void)rhport; + + TU_ASSERT(largest_packet_size <= 1024); + + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + uint8_t const ep_count = _dwc2_controller[rhport].ep_count; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + TU_ASSERT(epnum < ep_count); + + uint16_t const fifo_size = tu_div_ceil(largest_packet_size, 4); + + if (dir == TUSB_DIR_OUT) { + // Calculate required size of RX FIFO + uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count); + + // If size_rx needs to be extended check if possible and if so enlarge it + if (dwc2->grxfsiz < sz) { + TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4); + + // Enlarge RX FIFO + dwc2->grxfsiz = sz; + } + + } else + { + // "USB Data FIFOs" section in reference manual + // Peripheral FIFO architecture + // + // --------------- 320 or 1024 ( 1280 or 4096 bytes ) + // | IN FIFO 0 | + // --------------- (320 or 1024) - 16 + // | IN FIFO 1 | + // --------------- (320 or 1024) - 16 - x + // | . . . . | + // --------------- (320 or 1024) - 16 - x - y - ... - z + // | IN FIFO MAX | + // --------------- + // | FREE | + // --------------- GRXFSIZ + // | OUT FIFO | + // | ( Shared ) | + // --------------- 0 + // + // In FIFO is allocated by following rules: + // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". + + // Check if free space is available + TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4); + + _allocated_fifo_words_tx += fifo_size; + + TU_LOG(DWC2_DEBUG, " Allocated %u bytes at offset %lu", fifo_size * 4, + _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4); + + // DIEPTXF starts at FIFO #1. + // Both TXFD and TXSA are in unit of 32-bit words. + dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | + (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx); + } + + return true; +} + +bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) +{ + (void)rhport; + + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); + + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); + xfer->max_size = tu_edpt_packet_size(p_endpoint_desc); + xfer->interval = p_endpoint_desc->bInterval; + + if (dir == TUSB_DIR_OUT) { + dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) | + (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | + (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | + (xfer->max_size << DOEPCTL_MPSIZ_Pos); + + dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum); + } else + { + dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) | + (epnum << DIEPCTL_TXFNUM_Pos) | + (p_endpoint_desc->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) | + (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) | + (xfer->max_size << DIEPCTL_MPSIZ_Pos); + + dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum)); + } + + return true; +} + bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); -- cgit v1.3.1 From 4116a962a6c3073e6c617797e3d87643eafc4375 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Thu, 23 Nov 2023 19:20:03 +0100 Subject: Flush FIFO on bus reset. --- src/portable/synopsys/dwc2/dcd_dwc2.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index b0149a9a9..a411b54f4 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -139,6 +139,14 @@ static void bus_reset(uint8_t rhport) { dwc2->epout[n].doepctl |= DOEPCTL_SNAK; } + // flush all TX fifo and wait for it cleared + dwc2->grstctl = GRSTCTL_TXFFLSH | (0x10u << GRSTCTL_TXFNUM_Pos); + while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {} + + // flush RX fifo and wait for it cleared + dwc2->grstctl = GRSTCTL_RXFFLSH; + while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {} + // 2. Set up interrupt mask dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos); dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; -- cgit v1.3.1 From 8055bc88d8f606c1f69d669a1c022d1a7bca44a2 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 12 Jan 2024 15:59:51 +0100 Subject: Code refactor. --- src/portable/synopsys/dwc2/dcd_dwc2.c | 375 ++++++++++++++-------------------- 1 file changed, 157 insertions(+), 218 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index a411b54f4..f302b29b3 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -121,6 +121,155 @@ static void update_grxfsiz(uint8_t rhport) { dwc2->grxfsiz = calc_grxfsiz(max_epsize, ep_count); } +static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) +{ + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + uint8_t const ep_count = _dwc2_controller[rhport].ep_count; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + TU_ASSERT(epnum < ep_count); + + uint16_t const fifo_size = tu_div_ceil(packet_size, 4); + + if (dir == TUSB_DIR_OUT) { + // Calculate required size of RX FIFO + uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count); + + // If size_rx needs to be extended check if possible and if so enlarge it + if (dwc2->grxfsiz < sz) { + TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4); + + // Enlarge RX FIFO + dwc2->grxfsiz = sz; + } + + } else + { + // "USB Data FIFOs" section in reference manual + // Peripheral FIFO architecture + // + // --------------- 320 or 1024 ( 1280 or 4096 bytes ) + // | IN FIFO 0 | + // --------------- (320 or 1024) - 16 + // | IN FIFO 1 | + // --------------- (320 or 1024) - 16 - x + // | . . . . | + // --------------- (320 or 1024) - 16 - x - y - ... - z + // | IN FIFO MAX | + // --------------- + // | FREE | + // --------------- GRXFSIZ + // | OUT FIFO | + // | ( Shared ) | + // --------------- 0 + // + // In FIFO is allocated by following rules: + // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". + + // Check if free space is available + TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4); + + _allocated_fifo_words_tx += fifo_size; + + TU_LOG(DWC2_DEBUG, " Allocated %u bytes at offset %lu", fifo_size * 4, + _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4); + + // DIEPTXF starts at FIFO #1. + // Both TXFD and TXSA are in unit of 32-bit words. + dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | + (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx); + } + + return true; +} + +static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) +{ + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); + + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); + xfer->max_size = tu_edpt_packet_size(p_endpoint_desc); + xfer->interval = p_endpoint_desc->bInterval; + + if (dir == TUSB_DIR_OUT) { + dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) | + (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | + (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | + (xfer->max_size << DOEPCTL_MPSIZ_Pos); + + dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum); + } else + { + dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) | + (epnum << DIEPCTL_TXFNUM_Pos) | + (p_endpoint_desc->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) | + (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) | + (xfer->max_size << DIEPCTL_MPSIZ_Pos); + + dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum)); + } +} + +static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { + (void) rhport; + + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if (dir == TUSB_DIR_IN) { + dwc2_epin_t* epin = dwc2->epin; + + // Only disable currently enabled non-control endpoint + if ((epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA)) { + epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); + } else { + // Stop transmitting packets and NAK IN xfers. + epin[epnum].diepctl |= DIEPCTL_SNAK; + while ((epin[epnum].diepint & DIEPINT_INEPNE) == 0) {} + + // Disable the endpoint. + epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0); + while ((epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0) {} + + epin[epnum].diepint = DIEPINT_EPDISD; + } + + // Flush the FIFO, and wait until we have confirmed it cleared. + dwc2->grstctl = ((epnum << GRSTCTL_TXFNUM_Pos) | GRSTCTL_TXFFLSH); + while ((dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0) {} + } else { + dwc2_epout_t* epout = dwc2->epout; + + // Only disable currently enabled non-control endpoint + if ((epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA)) { + epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0; + } else { + // Asserting GONAK is required to STALL an OUT endpoint. + // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt + // anyway, and it can't be cleared by user code. If this while loop never + // finishes, we have bigger problems than just the stack. + dwc2->dctl |= DCTL_SGONAK; + while ((dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0) {} + + // Ditto here- disable the endpoint. + epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); + while ((epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0) {} + + epout[epnum].doepint = DOEPINT_EPDISD; + + // Allow other OUT endpoints to keep receiving. + dwc2->dctl |= DCTL_CGONAK; + } + } +} + // Start of Bus Reset static void bus_reset(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -555,81 +704,9 @@ void dcd_sof_enable(uint8_t rhport, bool en) { bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) { (void) rhport; - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t const ep_count = _dwc2_controller[rhport].ep_count; + TU_ASSERT(fifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt))); - uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); - - TU_ASSERT(epnum < ep_count); - - xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); - xfer->max_size = tu_edpt_packet_size(desc_edpt); - xfer->interval = desc_edpt->bInterval; - - uint16_t const fifo_size = tu_div_ceil(xfer->max_size, 4); - - if (dir == TUSB_DIR_OUT) { - // Calculate required size of RX FIFO - uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count); - - // If size_rx needs to be extended check if possible and if so enlarge it - if (dwc2->grxfsiz < sz) { - TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4); - - // Enlarge RX FIFO - dwc2->grxfsiz = sz; - } - - dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) | - (desc_edpt->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | - (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << DOEPCTL_MPSIZ_Pos); - - dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum); - } else { - // "USB Data FIFOs" section in reference manual - // Peripheral FIFO architecture - // - // --------------- 320 or 1024 ( 1280 or 4096 bytes ) - // | IN FIFO 0 | - // --------------- (320 or 1024) - 16 - // | IN FIFO 1 | - // --------------- (320 or 1024) - 16 - x - // | . . . . | - // --------------- (320 or 1024) - 16 - x - y - ... - z - // | IN FIFO MAX | - // --------------- - // | FREE | - // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | - // --------------- 0 - // - // In FIFO is allocated by following rules: - // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". - - // Check if free space is available - TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4); - - _allocated_fifo_words_tx += fifo_size; - - TU_LOG(DWC2_DEBUG, " Allocated %u bytes at offset %lu", fifo_size * 4, - _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4); - - // DIEPTXF starts at FIFO #1. - // Both TXFD and TXSA are in unit of 32-bit words. - dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | - (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx); - - dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) | - (epnum << DIEPCTL_TXFNUM_Pos) | - (desc_edpt->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) | - (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << DIEPCTL_MPSIZ_Pos); - - dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum)); - } + edpt_activate(rhport, desc_edpt); return true; } @@ -658,102 +735,17 @@ void dcd_edpt_close_all(uint8_t rhport) { bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { - (void)rhport; - - TU_ASSERT(largest_packet_size <= 1024); - - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t const ep_count = _dwc2_controller[rhport].ep_count; - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - TU_ASSERT(epnum < ep_count); - - uint16_t const fifo_size = tu_div_ceil(largest_packet_size, 4); - - if (dir == TUSB_DIR_OUT) { - // Calculate required size of RX FIFO - uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count); - - // If size_rx needs to be extended check if possible and if so enlarge it - if (dwc2->grxfsiz < sz) { - TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4); - - // Enlarge RX FIFO - dwc2->grxfsiz = sz; - } - - } else - { - // "USB Data FIFOs" section in reference manual - // Peripheral FIFO architecture - // - // --------------- 320 or 1024 ( 1280 or 4096 bytes ) - // | IN FIFO 0 | - // --------------- (320 or 1024) - 16 - // | IN FIFO 1 | - // --------------- (320 or 1024) - 16 - x - // | . . . . | - // --------------- (320 or 1024) - 16 - x - y - ... - z - // | IN FIFO MAX | - // --------------- - // | FREE | - // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | - // --------------- 0 - // - // In FIFO is allocated by following rules: - // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". - - // Check if free space is available - TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4); - - _allocated_fifo_words_tx += fifo_size; - - TU_LOG(DWC2_DEBUG, " Allocated %u bytes at offset %lu", fifo_size * 4, - _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4); - - // DIEPTXF starts at FIFO #1. - // Both TXFD and TXSA are in unit of 32-bit words. - dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | - (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx); - } + TU_ASSERT(fifo_alloc(rhport, ep_addr, largest_packet_size)); return true; } bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { - (void)rhport; - - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - - uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); - - xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); - xfer->max_size = tu_edpt_packet_size(p_endpoint_desc); - xfer->interval = p_endpoint_desc->bInterval; + // Disable EP to clear potential incomplete transfers + edpt_disable(rhport, p_endpoint_desc->bEndpointAddress, false); - if (dir == TUSB_DIR_OUT) { - dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) | - (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | - (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << DOEPCTL_MPSIZ_Pos); - - dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum); - } else - { - dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) | - (epnum << DIEPCTL_TXFNUM_Pos) | - (p_endpoint_desc->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) | - (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << DIEPCTL_MPSIZ_Pos); - - dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum)); - } + edpt_activate(rhport, p_endpoint_desc); return true; } @@ -815,60 +807,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t return true; } -static void dcd_edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { - (void) rhport; - - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - if (dir == TUSB_DIR_IN) { - dwc2_epin_t* epin = dwc2->epin; - - // Only disable currently enabled non-control endpoint - if ((epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA)) { - epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); - } else { - // Stop transmitting packets and NAK IN xfers. - epin[epnum].diepctl |= DIEPCTL_SNAK; - while ((epin[epnum].diepint & DIEPINT_INEPNE) == 0) {} - - // Disable the endpoint. - epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0); - while ((epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0) {} - - epin[epnum].diepint = DIEPINT_EPDISD; - } - // Flush the FIFO, and wait until we have confirmed it cleared. - dwc2->grstctl = ((epnum << GRSTCTL_TXFNUM_Pos) | GRSTCTL_TXFFLSH); - while ((dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0) {} - } else { - dwc2_epout_t* epout = dwc2->epout; - - // Only disable currently enabled non-control endpoint - if ((epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA)) { - epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0; - } else { - // Asserting GONAK is required to STALL an OUT endpoint. - // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt - // anyway, and it can't be cleared by user code. If this while loop never - // finishes, we have bigger problems than just the stack. - dwc2->dctl |= DCTL_SGONAK; - while ((dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0) {} - - // Ditto here- disable the endpoint. - epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); - while ((epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0) {} - - epout[epnum].doepint = DOEPINT_EPDISD; - - // Allow other OUT endpoints to keep receiving. - dwc2->dctl |= DCTL_CGONAK; - } - } -} /** * Close an endpoint. @@ -879,7 +818,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - dcd_edpt_disable(rhport, ep_addr, false); + edpt_disable(rhport, ep_addr, false); // Update max_size xfer_status[epnum][dir].max_size = 0; // max_size = 0 marks a disabled EP - required for changing FIFO allocation @@ -897,7 +836,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { } void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - dcd_edpt_disable(rhport, ep_addr, true); + edpt_disable(rhport, ep_addr, true); } void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { -- cgit v1.3.1 From 85420c61c780e260d0afd21de4a39c17ceba5d87 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 31 Mar 2024 13:49:41 +0700 Subject: minor clean up --- src/portable/synopsys/dwc2/dcd_dwc2.c | 104 ++++++++++++++-------------------- 1 file changed, 41 insertions(+), 63 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index f302b29b3..cf8f3be50 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -102,7 +102,13 @@ static bool _out_ep_closed; // Flag to check if RX FIFO size n // SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by static bool _sof_en; -// Calculate the RX FIFO size according to recommendations from reference manual +// Calculate the RX FIFO size according to minimum recommendations from reference manual +// RxFIFO = (5 * number of control endpoints + 8) + +// ((largest USB packet used / 4) + 1 for status information) + +// (2 * number of OUT endpoints) + 1 for Global NAK +// with number of control endpoints = 1 we have +// RxFIFO = 15 + (largest USB packet used / 4) + 2 * number of OUT endpoints +// we double the largest USB packet size to be able to hold up to 2 packets static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count) { return 15 + 2 * (max_ep_size / 4) + 2 * ep_count; } @@ -121,11 +127,9 @@ static void update_grxfsiz(uint8_t rhport) { dwc2->grxfsiz = calc_grxfsiz(max_epsize, ep_count); } -static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) -{ +static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; - uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); @@ -133,6 +137,26 @@ static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) uint16_t const fifo_size = tu_div_ceil(packet_size, 4); + // "USB Data FIFOs" section in reference manual + // Peripheral FIFO architecture + // + // --------------- 320 or 1024 ( 1280 or 4096 bytes ) + // | IN FIFO 0 | + // --------------- (320 or 1024) - 16 + // | IN FIFO 1 | + // --------------- (320 or 1024) - 16 - x + // | . . . . | + // --------------- (320 or 1024) - 16 - x - y - ... - z + // | IN FIFO MAX | + // --------------- + // | FREE | + // --------------- GRXFSIZ + // | OUT FIFO | + // | ( Shared ) | + // --------------- 0 + // + // In FIFO is allocated by following rules: + // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". if (dir == TUSB_DIR_OUT) { // Calculate required size of RX FIFO uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count); @@ -144,35 +168,10 @@ static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) // Enlarge RX FIFO dwc2->grxfsiz = sz; } - - } else - { - // "USB Data FIFOs" section in reference manual - // Peripheral FIFO architecture - // - // --------------- 320 or 1024 ( 1280 or 4096 bytes ) - // | IN FIFO 0 | - // --------------- (320 or 1024) - 16 - // | IN FIFO 1 | - // --------------- (320 or 1024) - 16 - x - // | . . . . | - // --------------- (320 or 1024) - 16 - x - y - ... - z - // | IN FIFO MAX | - // --------------- - // | FREE | - // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | - // --------------- 0 - // - // In FIFO is allocated by following rules: - // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". - + } else { // Check if free space is available TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4); - _allocated_fifo_words_tx += fifo_size; - TU_LOG(DWC2_DEBUG, " Allocated %u bytes at offset %lu", fifo_size * 4, _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4); @@ -185,10 +184,8 @@ static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) return true; } -static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) -{ +static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); @@ -196,21 +193,17 @@ static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoi xfer->max_size = tu_edpt_packet_size(p_endpoint_desc); xfer->interval = p_endpoint_desc->bInterval; - if (dir == TUSB_DIR_OUT) { - dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) | - (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | - (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << DOEPCTL_MPSIZ_Pos); + // USBAEP, EPTYP, SD0PID_SEVNFRM, MPSIZ are the same for IN and OUT endpoints. + uint32_t const dxepctl = (1 << DOEPCTL_USBAEP_Pos) | + (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | + (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | + (xfer->max_size << DOEPCTL_MPSIZ_Pos); + if (dir == TUSB_DIR_OUT) { + dwc2->epout[epnum].doepctl |= dxepctl; dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum); - } else - { - dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) | - (epnum << DIEPCTL_TXFNUM_Pos) | - (p_endpoint_desc->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) | - (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << DIEPCTL_MPSIZ_Pos); - + } else { + dwc2->epin[epnum].diepctl |= dxepctl | (epnum << DIEPCTL_TXFNUM_Pos); dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum)); } } @@ -219,7 +212,6 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { (void) rhport; dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); @@ -426,7 +418,6 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c /* Controller API *------------------------------------------------------------------*/ #if CFG_TUSB_DEBUG >= DWC2_DEBUG - void print_dwc2_info(dwc2_regs_t* dwc2) { // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 // use dwc2_info.py/md for bit-field value and comparison with other ports @@ -437,7 +428,6 @@ void print_dwc2_info(dwc2_regs_t* dwc2) { } TU_LOG(DWC2_DEBUG, "0x%08lX\r\n", p[5]); } - #endif static void reset_core(dwc2_regs_t* dwc2) { @@ -702,12 +692,8 @@ void dcd_sof_enable(uint8_t rhport, bool en) { *------------------------------------------------------------------*/ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) { - (void) rhport; - TU_ASSERT(fifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt))); - edpt_activate(rhport, desc_edpt); - return true; } @@ -733,15 +719,12 @@ void dcd_edpt_close_all(uint8_t rhport) { _allocated_fifo_words_tx = 16; } -bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) -{ +bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { TU_ASSERT(fifo_alloc(rhport, ep_addr, largest_packet_size)); - return true; } -bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) -{ +bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { // Disable EP to clear potential incomplete transfers edpt_disable(rhport, p_endpoint_desc->bEndpointAddress, false); @@ -807,11 +790,6 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t return true; } - - -/** - * Close an endpoint. - */ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); -- cgit v1.3.1 From 2012a0d369badbc671ac061184ddc3f5961e985e Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 31 Mar 2024 15:48:26 +0700 Subject: fix hid close not clear data --- src/class/hid/hid_host.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index efc54656e..621fb2a55 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -410,8 +410,7 @@ void hidh_close(uint8_t daddr) { if (p_hid->daddr == daddr) { TU_LOG_DRV(" HIDh close addr = %u index = %u\r\n", daddr, i); if (tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i); - p_hid->daddr = 0; - p_hid->mounted = false; + tu_memclr(p_hid, sizeof(hidh_interface_t)); } } } -- cgit v1.3.1 From ac4e649e56b7ace537670d1cc261a64a4e650d02 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 31 Mar 2024 18:41:59 +0700 Subject: code format --- .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 176 +++++++++------------ 1 file changed, 71 insertions(+), 105 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index ade64b4fb..15de95d23 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -1,30 +1,32 @@ -/** - * Copyright(c) 2016 STMicroelectronics - * Copyright(c) N Conrad - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ +/* + * Copyright(c) 2016 STMicroelectronics + * Copyright(c) N Conrad + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the TinyUSB stack. + */ // This file contains source copied from ST's HAL, and thus should have their copyright statement. @@ -138,7 +140,6 @@ #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY #define USB_CNTR_FSUSP USB_CNTR_SUSPEN - #elif CFG_TUSB_MCU == OPT_MCU_STM32WB #include "stm32wbxx.h" #define FSDEV_PMA_SIZE (1024u) @@ -182,27 +183,23 @@ typedef uint16_t fsdev_bus_t; // Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden) static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR; -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) -{ +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) { size_t total_word_offset = (((USBx)->BTABLE)>>1) + x; total_word_offset *= FSDEV_PMA_STRIDE; return &(pma[total_word_offset]); } -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) -{ +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) { return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 1u); } -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) -{ +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) { return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 3u); } #endif /* Aligned buffer size according to hardware */ -TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size) -{ +TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size) { /* The STM32 full speed USB peripheral supports only a limited set of * buffer sizes given by the RX buffer entry format in the USB_BTABLE. */ uint16_t blocksize = (size > 62) ? 32 : 2; @@ -213,9 +210,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t si return numblocks * blocksize; } -/* SetENDPOINT */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue) { #ifdef FSDEV_BUS_32BIT (void) USBx; __O uint32_t *reg = (__O uint32_t *)(USB_DRD_BASE + bEpIdx*4); @@ -226,7 +221,6 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, ui #endif } -/* GetENDPOINT */ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) { #ifdef FSDEV_BUS_32BIT (void) USBx; @@ -237,8 +231,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx return *reg; } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wType) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wType) { uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= (uint32_t)USB_EP_T_MASK; regVal |= wType; @@ -246,20 +239,19 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint pcd_set_endpoint(USBx, bEpIdx, regVal); } -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpIdx) -{ +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpIdx) { uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EP_T_FIELD; return regVal; } + /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. * @param USBx USB peripheral instance register address. * @param bEpIdx Endpoint Number. * @retval None */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) { uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPREG_MASK; regVal &= ~USB_EP_CTR_RX; @@ -267,22 +259,21 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, pcd_set_endpoint(USBx, bEpIdx, regVal); } -TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) { uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPREG_MASK; regVal &= ~USB_EP_CTR_TX; regVal |= USB_EP_CTR_RX; // preserve CTR_RX (clears on writing 0) pcd_set_endpoint(USBx, bEpIdx,regVal); } + /** * @brief gets counter of the tx buffer. * @param USBx USB peripheral instance register address. * @param bEpIdx Endpoint Number. * @retval Counter value */ -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) -{ +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) { #ifdef FSDEV_BUS_32BIT (void) USBx; return (pma32[2*bEpIdx] & 0x03FF0000) >> 16; @@ -292,8 +283,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USB #endif } -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) -{ +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) { #ifdef FSDEV_BUS_32BIT (void) USBx; /* WA: few cycles for RX PMA descriptor to update, otherwise doesn't return the correct value. @@ -320,8 +310,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USB * @param bAddr Address. * @retval None */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t bAddr) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t bAddr) { uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPREG_MASK; regVal |= bAddr; @@ -329,8 +318,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx, pcd_set_endpoint(USBx, bEpIdx,regVal); } -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx) -{ +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx) { #ifdef FSDEV_BUS_32BIT (void) USBx; return pma32[2*bEpIdx] & 0x0000FFFFu ; @@ -339,8 +327,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * #endif } -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx) -{ +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx) { #ifdef FSDEV_BUS_32BIT (void) USBx; return pma32[2*bEpIdx + 1] & 0x0000FFFFu; @@ -349,8 +336,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * #endif } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) { #ifdef FSDEV_BUS_32BIT (void) USBx; pma32[2*bEpIdx] = (pma32[2*bEpIdx] & 0xFFFF0000u) | (addr & 0x0000FFFCu); @@ -359,8 +345,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USB #endif } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) { #ifdef FSDEV_BUS_32BIT (void) USBx; pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & 0xFFFF0000u) | (addr & 0x0000FFFCu); @@ -369,8 +354,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USB #endif } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { #ifdef FSDEV_BUS_32BIT (void) USBx; pma32[2*bEpIdx] = (pma32[2*bEpIdx] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16); @@ -380,8 +364,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, u #endif } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { #ifdef FSDEV_BUS_32BIT (void) USBx; pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16); @@ -391,8 +374,8 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, u #endif } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t blocksize, uint32_t numblocks) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDef * USBx, uint32_t rxtx_idx, + uint32_t blocksize, uint32_t numblocks) { /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */ #ifdef FSDEV_BUS_32BIT (void) USBx; @@ -403,8 +386,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDe #endif } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_bufsize(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t wCount) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_bufsize(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t wCount) { wCount = pcd_aligned_buffer_size(wCount); /* We assume that the buffer size is already aligned to hardware requirements. */ @@ -418,13 +400,11 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_bufsize(USB_TypeDef * USBx, pcd_set_ep_blsize_num_blocks(USBx, rxtx_idx, blocksize, numblocks); } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { pcd_set_ep_bufsize(USBx, 2*bEpIdx, wCount); } -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { pcd_set_ep_bufsize(USBx, 2*bEpIdx + 1, wCount); } @@ -435,8 +415,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USB * @param wState new state * @retval None */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) { uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPTX_DTOGMASK; @@ -453,7 +432,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; pcd_set_endpoint(USBx, bEpIdx, regVal); -} /* pcd_set_ep_tx_status */ +} /** * @brief sets the status for rx transfer (bits STAT_TX[1:0]) @@ -463,31 +442,27 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx * @retval None */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) { uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPRX_DTOGMASK; /* toggle first bit ? */ - if((USB_EPRX_DTOG1 & wState)!= 0U) - { + if((USB_EPRX_DTOG1 & wState)!= 0U) { regVal ^= USB_EPRX_DTOG1; } /* toggle second bit ? */ - if((USB_EPRX_DTOG2 & wState)!= 0U) - { + if((USB_EPRX_DTOG2 & wState)!= 0U) { regVal ^= USB_EPRX_DTOG2; } regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; pcd_set_endpoint(USBx, bEpIdx, regVal); -} /* pcd_set_ep_rx_status */ +} -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx) -{ +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx) { uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); return (regVal & USB_EPRX_STAT) >> (12u); -} /* pcd_get_ep_rx_status */ +} /** @@ -496,16 +471,14 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * * @param bEpIdx Endpoint Number. * @retval None */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPREG_MASK; regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX; pcd_set_endpoint(USBx, bEpIdx, regVal); } -TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPREG_MASK; regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX; @@ -518,21 +491,16 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx, uint32 * @param bEpIdx Endpoint Number. * @retval None */ - -TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - if((regVal & USB_EP_DTOG_RX) != 0) - { + if((regVal & USB_EP_DTOG_RX) != 0) { pcd_rx_dtog(USBx,bEpIdx); } } -TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - if((regVal & USB_EP_DTOG_TX) != 0) - { + if((regVal & USB_EP_DTOG_TX) != 0) { pcd_tx_dtog(USBx,bEpIdx); } } @@ -543,17 +511,15 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx, * @param bEpIdx Endpoint Number. * @retval None */ - -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx) -{ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx) { uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal |= USB_EP_KIND; regVal &= USB_EPREG_MASK; regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; pcd_set_endpoint(USBx, bEpIdx, regVal); } -TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx) -{ + +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx) { uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); regVal &= USB_EPKIND_MASK; regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; -- cgit v1.3.1 From 27afa568445d193a075c6ca2b7bb1df76039d956 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 31 Mar 2024 18:42:49 +0700 Subject: rename dcd_stm32_fsdev_pvt_st.h to simply dcd_stm32_fsdev.h --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 2 +- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h | 543 +++++++++++++++++++++ .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 543 --------------------- 3 files changed, 544 insertions(+), 544 deletions(-) create mode 100644 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h delete mode 100644 src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 9c37f1f98..5e54d0f56 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -109,7 +109,7 @@ #ifdef TUP_USBIP_FSDEV_STM32 // Undefine to reduce the dependence on HAL #undef USE_HAL_DRIVER - #include "portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h" + #include "portable/st/stm32_fsdev/dcd_stm32_fsdev.h" #endif /***************************************************** diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h new file mode 100644 index 000000000..15de95d23 --- /dev/null +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h @@ -0,0 +1,543 @@ +/* + * Copyright(c) 2016 STMicroelectronics + * Copyright(c) N Conrad + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the TinyUSB stack. + */ + +// This file contains source copied from ST's HAL, and thus should have their copyright statement. + +// FSDEV_PMA_SIZE is PMA buffer size in bytes. +// On 512-byte devices, access with a stride of two words (use every other 16-bit address) +// On 1024-byte devices, access with a stride of one word (use every 16-bit address) + +#ifndef PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ +#define PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ + +#if CFG_TUSB_MCU == OPT_MCU_STM32F0 + #include "stm32f0xx.h" + #define FSDEV_PMA_SIZE (1024u) + // F0x2 models are crystal-less + // All have internal D+ pull-up + // 070RB: 2 x 16 bits/word memory LPM Support, BCD Support + // PMA dedicated to USB (no sharing with CAN) + +#elif CFG_TUSB_MCU == OPT_MCU_STM32F1 + #include "stm32f1xx.h" + #define FSDEV_PMA_SIZE (512u) + // NO internal Pull-ups + // *B, and *C: 2 x 16 bits/word + + // F1 names this differently from the rest + #define USB_CNTR_LPMODE USB_CNTR_LP_MODE + +#elif defined(STM32F302xB) || defined(STM32F302xC) || \ + defined(STM32F303xB) || defined(STM32F303xC) || \ + defined(STM32F373xC) + #include "stm32f3xx.h" + #define FSDEV_PMA_SIZE (512u) + // NO internal Pull-ups + // *B, and *C: 1 x 16 bits/word + // PMA dedicated to USB (no sharing with CAN) + +#elif defined(STM32F302x6) || defined(STM32F302x8) || \ + defined(STM32F302xD) || defined(STM32F302xE) || \ + defined(STM32F303xD) || defined(STM32F303xE) + #include "stm32f3xx.h" + #define FSDEV_PMA_SIZE (1024u) + // NO internal Pull-ups + // *6, *8, *D, and *E: 2 x 16 bits/word LPM Support + // When CAN clock is enabled, USB can use first 768 bytes ONLY. + +#elif CFG_TUSB_MCU == OPT_MCU_STM32L0 + #include "stm32l0xx.h" + #define FSDEV_PMA_SIZE (1024u) + +#elif CFG_TUSB_MCU == OPT_MCU_STM32L1 + #include "stm32l1xx.h" + #define FSDEV_PMA_SIZE (512u) + +#elif CFG_TUSB_MCU == OPT_MCU_STM32G4 + #include "stm32g4xx.h" + #define FSDEV_PMA_SIZE (1024u) + +#elif CFG_TUSB_MCU == OPT_MCU_STM32G0 + #include "stm32g0xx.h" + #define FSDEV_BUS_32BIT + #define FSDEV_PMA_SIZE (2048u) + #undef USB_PMAADDR + #define USB_PMAADDR USB_DRD_PMAADDR + #define USB_TypeDef USB_DRD_TypeDef + #define EP0R CHEP0R + #define USB_EP_CTR_RX USB_EP_VTRX + #define USB_EP_CTR_TX USB_EP_VTTX + #define USB_EP_T_FIELD USB_CHEP_UTYPE + #define USB_EPREG_MASK USB_CHEP_REG_MASK + #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK + #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK + #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1 + #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2 + #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1 + #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2 + #define USB_EPRX_STAT USB_CH_RX_VALID + #define USB_EPKIND_MASK USB_EP_KIND_MASK + #define USB USB_DRD_FS + #define USB_CNTR_FRES USB_CNTR_USBRST + #define USB_CNTR_RESUME USB_CNTR_L2RES + #define USB_ISTR_EP_ID USB_ISTR_IDN + #define USB_EPADDR_FIELD USB_CHEP_ADDR + #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY + #define USB_CNTR_FSUSP USB_CNTR_SUSPEN + +#elif CFG_TUSB_MCU == OPT_MCU_STM32H5 + #include "stm32h5xx.h" + #define FSDEV_BUS_32BIT + #define FSDEV_PMA_SIZE (2048u) + #undef USB_PMAADDR + #define USB_PMAADDR USB_DRD_PMAADDR + #define USB_TypeDef USB_DRD_TypeDef + #define EP0R CHEP0R + #define USB_EP_CTR_RX USB_EP_VTRX + #define USB_EP_CTR_TX USB_EP_VTTX + #define USB_EP_T_FIELD USB_CHEP_UTYPE + #define USB_EPREG_MASK USB_CHEP_REG_MASK + #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK + #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK + #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1 + #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2 + #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1 + #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2 + #define USB_EPRX_STAT USB_CH_RX_VALID + #define USB_EPKIND_MASK USB_EP_KIND_MASK + #define USB USB_DRD_FS + #define USB_CNTR_FRES USB_CNTR_USBRST + #define USB_CNTR_RESUME USB_CNTR_L2RES + #define USB_ISTR_EP_ID USB_ISTR_IDN + #define USB_EPADDR_FIELD USB_CHEP_ADDR + #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY + #define USB_CNTR_FSUSP USB_CNTR_SUSPEN + +#elif CFG_TUSB_MCU == OPT_MCU_STM32WB + #include "stm32wbxx.h" + #define FSDEV_PMA_SIZE (1024u) + /* ST provided header has incorrect value */ + #undef USB_PMAADDR + #define USB_PMAADDR USB1_PMAADDR + +#elif CFG_TUSB_MCU == OPT_MCU_STM32L4 + #include "stm32l4xx.h" + #define FSDEV_PMA_SIZE (1024u) + +#elif CFG_TUSB_MCU == OPT_MCU_STM32L5 + #include "stm32l5xx.h" + #define FSDEV_PMA_SIZE (1024u) + + #ifndef USB_PMAADDR + #define USB_PMAADDR (USB_BASE + (USB_PMAADDR_NS - USB_BASE_NS)) + #endif + +#else + #error You are using an untested or unimplemented STM32 variant. Please update the driver. + // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4 +#endif + +// For purposes of accessing the packet +#if ((FSDEV_PMA_SIZE) == 512u) + #define FSDEV_PMA_STRIDE (2u) +#elif ((FSDEV_PMA_SIZE) == 1024u) + #define FSDEV_PMA_STRIDE (1u) +#endif + +// The fsdev_bus_t type can be used for both register and PMA access necessities +// For type-safety create a new macro for the volatile address of PMAADDR +// The compiler should warn us if we cast it to a non-volatile type? +#ifdef FSDEV_BUS_32BIT +typedef uint32_t fsdev_bus_t; +static __IO uint32_t * const pma32 = (__IO uint32_t*)USB_PMAADDR; + +#else +typedef uint16_t fsdev_bus_t; +// Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden) +static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR; + +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) { + size_t total_word_offset = (((USBx)->BTABLE)>>1) + x; + total_word_offset *= FSDEV_PMA_STRIDE; + return &(pma[total_word_offset]); +} + +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) { + return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 1u); +} + +TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) { + return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 3u); +} +#endif + +/* Aligned buffer size according to hardware */ +TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size) { + /* The STM32 full speed USB peripheral supports only a limited set of + * buffer sizes given by the RX buffer entry format in the USB_BTABLE. */ + uint16_t blocksize = (size > 62) ? 32 : 2; + + // Round up while dividing requested size by blocksize + uint16_t numblocks = (size + blocksize - 1) / blocksize ; + + return numblocks * blocksize; +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue) { +#ifdef FSDEV_BUS_32BIT + (void) USBx; + __O uint32_t *reg = (__O uint32_t *)(USB_DRD_BASE + bEpIdx*4); + *reg = wRegValue; +#else + __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpIdx*2u); + *reg = (uint16_t)wRegValue; +#endif +} + +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) { +#ifdef FSDEV_BUS_32BIT + (void) USBx; + __I uint32_t *reg = (__I uint32_t *)(USB_DRD_BASE + bEpIdx*4); +#else + __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpIdx*2u); +#endif + return *reg; +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wType) { + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); + regVal &= (uint32_t)USB_EP_T_MASK; + regVal |= wType; + regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; // These clear on write0, so must set high + pcd_set_endpoint(USBx, bEpIdx, regVal); +} + +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpIdx) { + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); + regVal &= USB_EP_T_FIELD; + return regVal; +} + +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpIdx Endpoint Number. + * @retval None + */ +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) { + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); + regVal &= USB_EPREG_MASK; + regVal &= ~USB_EP_CTR_RX; + regVal |= USB_EP_CTR_TX; // preserve CTR_TX (clears on writing 0) + pcd_set_endpoint(USBx, bEpIdx, regVal); +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) { + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); + regVal &= USB_EPREG_MASK; + regVal &= ~USB_EP_CTR_TX; + regVal |= USB_EP_CTR_RX; // preserve CTR_RX (clears on writing 0) + pcd_set_endpoint(USBx, bEpIdx,regVal); +} + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpIdx Endpoint Number. + * @retval Counter value + */ +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) { +#ifdef FSDEV_BUS_32BIT + (void) USBx; + return (pma32[2*bEpIdx] & 0x03FF0000) >> 16; +#else + __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpIdx); + return *regPtr & 0x3ffU; +#endif +} + +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) { +#ifdef FSDEV_BUS_32BIT + (void) USBx; + /* WA: few cycles for RX PMA descriptor to update, otherwise doesn't return the correct value. + Note: required for G0, U5, H5 etc. + This workaround is ported from stm32h5xx_hal_pcd.h and fixes the issue when calling this function fast enough. + Reproduced with GCC ast optimization(O2/O3) and stm32h573i_dk with an high frequency. + Observed on Windows 10 where tud_task() is scheduled by interrupt handler. + */ + volatile uint32_t count = 10; // defined as PCD_RX_PMA_CNT in stm32 hal_driver + while (count > 0U) { + count--; + } + return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16; +#else + __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx); + return *regPtr & 0x3ffU; +#endif +} + +/** + * @brief Sets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpIdx Endpoint Number. + * @param bAddr Address. + * @retval None + */ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t bAddr) { + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); + regVal &= USB_EPREG_MASK; + regVal |= bAddr; + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; + pcd_set_endpoint(USBx, bEpIdx,regVal); +} + +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx) { +#ifdef FSDEV_BUS_32BIT + (void) USBx; + return pma32[2*bEpIdx] & 0x0000FFFFu ; +#else + return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u); +#endif +} + +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx) { +#ifdef FSDEV_BUS_32BIT + (void) USBx; + return pma32[2*bEpIdx + 1] & 0x0000FFFFu; +#else + return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u); +#endif +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) { +#ifdef FSDEV_BUS_32BIT + (void) USBx; + pma32[2*bEpIdx] = (pma32[2*bEpIdx] & 0xFFFF0000u) | (addr & 0x0000FFFCu); +#else + *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u) = addr; +#endif +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) { +#ifdef FSDEV_BUS_32BIT + (void) USBx; + pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & 0xFFFF0000u) | (addr & 0x0000FFFCu); +#else + *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u) = addr; +#endif +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { +#ifdef FSDEV_BUS_32BIT + (void) USBx; + pma32[2*bEpIdx] = (pma32[2*bEpIdx] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16); +#else + __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpIdx); + *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU); +#endif +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { +#ifdef FSDEV_BUS_32BIT + (void) USBx; + pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16); +#else + __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpIdx); + *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU); +#endif +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDef * USBx, uint32_t rxtx_idx, + uint32_t blocksize, uint32_t numblocks) { + /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */ +#ifdef FSDEV_BUS_32BIT + (void) USBx; + pma32[rxtx_idx] = (pma32[rxtx_idx] & 0x0000FFFFu) | (blocksize << 31) | ((numblocks - blocksize) << 26); +#else + __IO uint16_t *pdwReg = pcd_btable_word_ptr(USBx, rxtx_idx*2u + 1u); + *pdwReg = (blocksize << 15) | ((numblocks - blocksize) << 10); +#endif +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_bufsize(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t wCount) { + wCount = pcd_aligned_buffer_size(wCount); + + /* We assume that the buffer size is already aligned to hardware requirements. */ + uint16_t blocksize = (wCount > 62) ? 1 : 0; + uint16_t numblocks = wCount / (blocksize ? 32 : 2); + + /* There should be no remainder in the above calculation */ + TU_ASSERT((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/); + + /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */ + pcd_set_ep_blsize_num_blocks(USBx, rxtx_idx, blocksize, numblocks); +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { + pcd_set_ep_bufsize(USBx, 2*bEpIdx, wCount); +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { + pcd_set_ep_bufsize(USBx, 2*bEpIdx + 1, wCount); +} + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bEpIdx Endpoint Number. + * @param wState new state + * @retval None + */ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) { + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); + regVal &= USB_EPTX_DTOGMASK; + + /* toggle first bit ? */ + if((USB_EPTX_DTOG1 & (wState))!= 0U) + { + regVal ^= USB_EPTX_DTOG1; + } + /* toggle second bit ? */ + if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U) + { + regVal ^= USB_EPTX_DTOG2; + } + + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; + pcd_set_endpoint(USBx, bEpIdx, regVal); +} + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpIdx Endpoint Number. + * @param wState new state + * @retval None + */ + +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) { + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); + regVal &= USB_EPRX_DTOGMASK; + + /* toggle first bit ? */ + if((USB_EPRX_DTOG1 & wState)!= 0U) { + regVal ^= USB_EPRX_DTOG1; + } + /* toggle second bit ? */ + if((USB_EPRX_DTOG2 & wState)!= 0U) { + regVal ^= USB_EPRX_DTOG2; + } + + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; + pcd_set_endpoint(USBx, bEpIdx, regVal); +} + +TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx) { + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); + return (regVal & USB_EPRX_STAT) >> (12u); +} + + +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpIdx Endpoint Number. + * @retval None + */ +TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); + regVal &= USB_EPREG_MASK; + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX; + pcd_set_endpoint(USBx, bEpIdx, regVal); +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); + regVal &= USB_EPREG_MASK; + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX; + pcd_set_endpoint(USBx, bEpIdx, regVal); +} + +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpIdx Endpoint Number. + * @retval None + */ +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); + if((regVal & USB_EP_DTOG_RX) != 0) { + pcd_rx_dtog(USBx,bEpIdx); + } +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); + if((regVal & USB_EP_DTOG_TX) != 0) { + pcd_tx_dtog(USBx,bEpIdx); + } +} + +/** + * @brief set & clear EP_KIND bit. + * @param USBx USB peripheral instance register address. + * @param bEpIdx Endpoint Number. + * @retval None + */ +TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx) { + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); + regVal |= USB_EP_KIND; + regVal &= USB_EPREG_MASK; + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; + pcd_set_endpoint(USBx, bEpIdx, regVal); +} + +TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx) { + uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); + regVal &= USB_EPKIND_MASK; + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; + pcd_set_endpoint(USBx, bEpIdx, regVal); +} + +// This checks if the device has "LPM" +#if defined(USB_ISTR_L1REQ) +#define USB_ISTR_L1REQ_FORCED (USB_ISTR_L1REQ) +#else +#define USB_ISTR_L1REQ_FORCED ((uint16_t)0x0000U) +#endif + +#define USB_ISTR_ALL_EVENTS (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | \ + USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED ) + +// Number of endpoints in hardware +// TODO should use TUP_DCD_ENDPOINT_MAX +#define STFSDEV_EP_COUNT (8u) + +#endif /* PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ */ diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h deleted file mode 100644 index 15de95d23..000000000 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ /dev/null @@ -1,543 +0,0 @@ -/* - * Copyright(c) 2016 STMicroelectronics - * Copyright(c) N Conrad - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the TinyUSB stack. - */ - -// This file contains source copied from ST's HAL, and thus should have their copyright statement. - -// FSDEV_PMA_SIZE is PMA buffer size in bytes. -// On 512-byte devices, access with a stride of two words (use every other 16-bit address) -// On 1024-byte devices, access with a stride of one word (use every 16-bit address) - -#ifndef PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ -#define PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ - -#if CFG_TUSB_MCU == OPT_MCU_STM32F0 - #include "stm32f0xx.h" - #define FSDEV_PMA_SIZE (1024u) - // F0x2 models are crystal-less - // All have internal D+ pull-up - // 070RB: 2 x 16 bits/word memory LPM Support, BCD Support - // PMA dedicated to USB (no sharing with CAN) - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F1 - #include "stm32f1xx.h" - #define FSDEV_PMA_SIZE (512u) - // NO internal Pull-ups - // *B, and *C: 2 x 16 bits/word - - // F1 names this differently from the rest - #define USB_CNTR_LPMODE USB_CNTR_LP_MODE - -#elif defined(STM32F302xB) || defined(STM32F302xC) || \ - defined(STM32F303xB) || defined(STM32F303xC) || \ - defined(STM32F373xC) - #include "stm32f3xx.h" - #define FSDEV_PMA_SIZE (512u) - // NO internal Pull-ups - // *B, and *C: 1 x 16 bits/word - // PMA dedicated to USB (no sharing with CAN) - -#elif defined(STM32F302x6) || defined(STM32F302x8) || \ - defined(STM32F302xD) || defined(STM32F302xE) || \ - defined(STM32F303xD) || defined(STM32F303xE) - #include "stm32f3xx.h" - #define FSDEV_PMA_SIZE (1024u) - // NO internal Pull-ups - // *6, *8, *D, and *E: 2 x 16 bits/word LPM Support - // When CAN clock is enabled, USB can use first 768 bytes ONLY. - -#elif CFG_TUSB_MCU == OPT_MCU_STM32L0 - #include "stm32l0xx.h" - #define FSDEV_PMA_SIZE (1024u) - -#elif CFG_TUSB_MCU == OPT_MCU_STM32L1 - #include "stm32l1xx.h" - #define FSDEV_PMA_SIZE (512u) - -#elif CFG_TUSB_MCU == OPT_MCU_STM32G4 - #include "stm32g4xx.h" - #define FSDEV_PMA_SIZE (1024u) - -#elif CFG_TUSB_MCU == OPT_MCU_STM32G0 - #include "stm32g0xx.h" - #define FSDEV_BUS_32BIT - #define FSDEV_PMA_SIZE (2048u) - #undef USB_PMAADDR - #define USB_PMAADDR USB_DRD_PMAADDR - #define USB_TypeDef USB_DRD_TypeDef - #define EP0R CHEP0R - #define USB_EP_CTR_RX USB_EP_VTRX - #define USB_EP_CTR_TX USB_EP_VTTX - #define USB_EP_T_FIELD USB_CHEP_UTYPE - #define USB_EPREG_MASK USB_CHEP_REG_MASK - #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK - #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK - #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1 - #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2 - #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1 - #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2 - #define USB_EPRX_STAT USB_CH_RX_VALID - #define USB_EPKIND_MASK USB_EP_KIND_MASK - #define USB USB_DRD_FS - #define USB_CNTR_FRES USB_CNTR_USBRST - #define USB_CNTR_RESUME USB_CNTR_L2RES - #define USB_ISTR_EP_ID USB_ISTR_IDN - #define USB_EPADDR_FIELD USB_CHEP_ADDR - #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY - #define USB_CNTR_FSUSP USB_CNTR_SUSPEN - -#elif CFG_TUSB_MCU == OPT_MCU_STM32H5 - #include "stm32h5xx.h" - #define FSDEV_BUS_32BIT - #define FSDEV_PMA_SIZE (2048u) - #undef USB_PMAADDR - #define USB_PMAADDR USB_DRD_PMAADDR - #define USB_TypeDef USB_DRD_TypeDef - #define EP0R CHEP0R - #define USB_EP_CTR_RX USB_EP_VTRX - #define USB_EP_CTR_TX USB_EP_VTTX - #define USB_EP_T_FIELD USB_CHEP_UTYPE - #define USB_EPREG_MASK USB_CHEP_REG_MASK - #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK - #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK - #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1 - #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2 - #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1 - #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2 - #define USB_EPRX_STAT USB_CH_RX_VALID - #define USB_EPKIND_MASK USB_EP_KIND_MASK - #define USB USB_DRD_FS - #define USB_CNTR_FRES USB_CNTR_USBRST - #define USB_CNTR_RESUME USB_CNTR_L2RES - #define USB_ISTR_EP_ID USB_ISTR_IDN - #define USB_EPADDR_FIELD USB_CHEP_ADDR - #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY - #define USB_CNTR_FSUSP USB_CNTR_SUSPEN - -#elif CFG_TUSB_MCU == OPT_MCU_STM32WB - #include "stm32wbxx.h" - #define FSDEV_PMA_SIZE (1024u) - /* ST provided header has incorrect value */ - #undef USB_PMAADDR - #define USB_PMAADDR USB1_PMAADDR - -#elif CFG_TUSB_MCU == OPT_MCU_STM32L4 - #include "stm32l4xx.h" - #define FSDEV_PMA_SIZE (1024u) - -#elif CFG_TUSB_MCU == OPT_MCU_STM32L5 - #include "stm32l5xx.h" - #define FSDEV_PMA_SIZE (1024u) - - #ifndef USB_PMAADDR - #define USB_PMAADDR (USB_BASE + (USB_PMAADDR_NS - USB_BASE_NS)) - #endif - -#else - #error You are using an untested or unimplemented STM32 variant. Please update the driver. - // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4 -#endif - -// For purposes of accessing the packet -#if ((FSDEV_PMA_SIZE) == 512u) - #define FSDEV_PMA_STRIDE (2u) -#elif ((FSDEV_PMA_SIZE) == 1024u) - #define FSDEV_PMA_STRIDE (1u) -#endif - -// The fsdev_bus_t type can be used for both register and PMA access necessities -// For type-safety create a new macro for the volatile address of PMAADDR -// The compiler should warn us if we cast it to a non-volatile type? -#ifdef FSDEV_BUS_32BIT -typedef uint32_t fsdev_bus_t; -static __IO uint32_t * const pma32 = (__IO uint32_t*)USB_PMAADDR; - -#else -typedef uint16_t fsdev_bus_t; -// Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden) -static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR; - -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) { - size_t total_word_offset = (((USBx)->BTABLE)>>1) + x; - total_word_offset *= FSDEV_PMA_STRIDE; - return &(pma[total_word_offset]); -} - -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) { - return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 1u); -} - -TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) { - return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 3u); -} -#endif - -/* Aligned buffer size according to hardware */ -TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size) { - /* The STM32 full speed USB peripheral supports only a limited set of - * buffer sizes given by the RX buffer entry format in the USB_BTABLE. */ - uint16_t blocksize = (size > 62) ? 32 : 2; - - // Round up while dividing requested size by blocksize - uint16_t numblocks = (size + blocksize - 1) / blocksize ; - - return numblocks * blocksize; -} - -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue) { -#ifdef FSDEV_BUS_32BIT - (void) USBx; - __O uint32_t *reg = (__O uint32_t *)(USB_DRD_BASE + bEpIdx*4); - *reg = wRegValue; -#else - __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpIdx*2u); - *reg = (uint16_t)wRegValue; -#endif -} - -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) { -#ifdef FSDEV_BUS_32BIT - (void) USBx; - __I uint32_t *reg = (__I uint32_t *)(USB_DRD_BASE + bEpIdx*4); -#else - __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpIdx*2u); -#endif - return *reg; -} - -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wType) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - regVal &= (uint32_t)USB_EP_T_MASK; - regVal |= wType; - regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; // These clear on write0, so must set high - pcd_set_endpoint(USBx, bEpIdx, regVal); -} - -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - regVal &= USB_EP_T_FIELD; - return regVal; -} - -/** - * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpIdx Endpoint Number. - * @retval None - */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - regVal &= USB_EPREG_MASK; - regVal &= ~USB_EP_CTR_RX; - regVal |= USB_EP_CTR_TX; // preserve CTR_TX (clears on writing 0) - pcd_set_endpoint(USBx, bEpIdx, regVal); -} - -TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - regVal &= USB_EPREG_MASK; - regVal &= ~USB_EP_CTR_TX; - regVal |= USB_EP_CTR_RX; // preserve CTR_RX (clears on writing 0) - pcd_set_endpoint(USBx, bEpIdx,regVal); -} - -/** - * @brief gets counter of the tx buffer. - * @param USBx USB peripheral instance register address. - * @param bEpIdx Endpoint Number. - * @retval Counter value - */ -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) { -#ifdef FSDEV_BUS_32BIT - (void) USBx; - return (pma32[2*bEpIdx] & 0x03FF0000) >> 16; -#else - __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpIdx); - return *regPtr & 0x3ffU; -#endif -} - -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) { -#ifdef FSDEV_BUS_32BIT - (void) USBx; - /* WA: few cycles for RX PMA descriptor to update, otherwise doesn't return the correct value. - Note: required for G0, U5, H5 etc. - This workaround is ported from stm32h5xx_hal_pcd.h and fixes the issue when calling this function fast enough. - Reproduced with GCC ast optimization(O2/O3) and stm32h573i_dk with an high frequency. - Observed on Windows 10 where tud_task() is scheduled by interrupt handler. - */ - volatile uint32_t count = 10; // defined as PCD_RX_PMA_CNT in stm32 hal_driver - while (count > 0U) { - count--; - } - return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16; -#else - __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx); - return *regPtr & 0x3ffU; -#endif -} - -/** - * @brief Sets address in an endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpIdx Endpoint Number. - * @param bAddr Address. - * @retval None - */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t bAddr) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - regVal &= USB_EPREG_MASK; - regVal |= bAddr; - regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; - pcd_set_endpoint(USBx, bEpIdx,regVal); -} - -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx) { -#ifdef FSDEV_BUS_32BIT - (void) USBx; - return pma32[2*bEpIdx] & 0x0000FFFFu ; -#else - return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u); -#endif -} - -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx) { -#ifdef FSDEV_BUS_32BIT - (void) USBx; - return pma32[2*bEpIdx + 1] & 0x0000FFFFu; -#else - return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u); -#endif -} - -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) { -#ifdef FSDEV_BUS_32BIT - (void) USBx; - pma32[2*bEpIdx] = (pma32[2*bEpIdx] & 0xFFFF0000u) | (addr & 0x0000FFFCu); -#else - *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u) = addr; -#endif -} - -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) { -#ifdef FSDEV_BUS_32BIT - (void) USBx; - pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & 0xFFFF0000u) | (addr & 0x0000FFFCu); -#else - *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u) = addr; -#endif -} - -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { -#ifdef FSDEV_BUS_32BIT - (void) USBx; - pma32[2*bEpIdx] = (pma32[2*bEpIdx] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16); -#else - __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpIdx); - *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU); -#endif -} - -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { -#ifdef FSDEV_BUS_32BIT - (void) USBx; - pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16); -#else - __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpIdx); - *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU); -#endif -} - -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDef * USBx, uint32_t rxtx_idx, - uint32_t blocksize, uint32_t numblocks) { - /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */ -#ifdef FSDEV_BUS_32BIT - (void) USBx; - pma32[rxtx_idx] = (pma32[rxtx_idx] & 0x0000FFFFu) | (blocksize << 31) | ((numblocks - blocksize) << 26); -#else - __IO uint16_t *pdwReg = pcd_btable_word_ptr(USBx, rxtx_idx*2u + 1u); - *pdwReg = (blocksize << 15) | ((numblocks - blocksize) << 10); -#endif -} - -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_bufsize(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t wCount) { - wCount = pcd_aligned_buffer_size(wCount); - - /* We assume that the buffer size is already aligned to hardware requirements. */ - uint16_t blocksize = (wCount > 62) ? 1 : 0; - uint16_t numblocks = wCount / (blocksize ? 32 : 2); - - /* There should be no remainder in the above calculation */ - TU_ASSERT((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/); - - /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */ - pcd_set_ep_blsize_num_blocks(USBx, rxtx_idx, blocksize, numblocks); -} - -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { - pcd_set_ep_bufsize(USBx, 2*bEpIdx, wCount); -} - -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) { - pcd_set_ep_bufsize(USBx, 2*bEpIdx + 1, wCount); -} - -/** - * @brief sets the status for tx transfer (bits STAT_TX[1:0]). - * @param USBx USB peripheral instance register address. - * @param bEpIdx Endpoint Number. - * @param wState new state - * @retval None - */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - regVal &= USB_EPTX_DTOGMASK; - - /* toggle first bit ? */ - if((USB_EPTX_DTOG1 & (wState))!= 0U) - { - regVal ^= USB_EPTX_DTOG1; - } - /* toggle second bit ? */ - if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U) - { - regVal ^= USB_EPTX_DTOG2; - } - - regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; - pcd_set_endpoint(USBx, bEpIdx, regVal); -} - -/** - * @brief sets the status for rx transfer (bits STAT_TX[1:0]) - * @param USBx USB peripheral instance register address. - * @param bEpIdx Endpoint Number. - * @param wState new state - * @retval None - */ - -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - regVal &= USB_EPRX_DTOGMASK; - - /* toggle first bit ? */ - if((USB_EPRX_DTOG1 & wState)!= 0U) { - regVal ^= USB_EPRX_DTOG1; - } - /* toggle second bit ? */ - if((USB_EPRX_DTOG2 & wState)!= 0U) { - regVal ^= USB_EPRX_DTOG2; - } - - regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; - pcd_set_endpoint(USBx, bEpIdx, regVal); -} - -TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - return (regVal & USB_EPRX_STAT) >> (12u); -} - - -/** - * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpIdx Endpoint Number. - * @retval None - */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - regVal &= USB_EPREG_MASK; - regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX; - pcd_set_endpoint(USBx, bEpIdx, regVal); -} - -TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - regVal &= USB_EPREG_MASK; - regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX; - pcd_set_endpoint(USBx, bEpIdx, regVal); -} - -/** - * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpIdx Endpoint Number. - * @retval None - */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - if((regVal & USB_EP_DTOG_RX) != 0) { - pcd_rx_dtog(USBx,bEpIdx); - } -} - -TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - if((regVal & USB_EP_DTOG_TX) != 0) { - pcd_tx_dtog(USBx,bEpIdx); - } -} - -/** - * @brief set & clear EP_KIND bit. - * @param USBx USB peripheral instance register address. - * @param bEpIdx Endpoint Number. - * @retval None - */ -TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - regVal |= USB_EP_KIND; - regVal &= USB_EPREG_MASK; - regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; - pcd_set_endpoint(USBx, bEpIdx, regVal); -} - -TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); - regVal &= USB_EPKIND_MASK; - regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; - pcd_set_endpoint(USBx, bEpIdx, regVal); -} - -// This checks if the device has "LPM" -#if defined(USB_ISTR_L1REQ) -#define USB_ISTR_L1REQ_FORCED (USB_ISTR_L1REQ) -#else -#define USB_ISTR_L1REQ_FORCED ((uint16_t)0x0000U) -#endif - -#define USB_ISTR_ALL_EVENTS (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | \ - USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED ) - -// Number of endpoints in hardware -// TODO should use TUP_DCD_ENDPOINT_MAX -#define STFSDEV_EP_COUNT (8u) - -#endif /* PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ */ -- cgit v1.3.1 From fc54ad43b1ac89efa8853d69e836b16ddfe156fa Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 31 Mar 2024 21:53:12 +0700 Subject: move walkaround to dcd_ep_ctr_rx_handler(), increase cycle_count from 10 to 20 (40 cycle) --- .idea/runConfigurations/stlink.xml | 4 +-- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 51 +++++++++++++++++---------- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h | 10 ------ 3 files changed, 34 insertions(+), 31 deletions(-) (limited to 'src') diff --git a/.idea/runConfigurations/stlink.xml b/.idea/runConfigurations/stlink.xml index babb8b463..c82f37d59 100644 --- a/.idea/runConfigurations/stlink.xml +++ b/.idea/runConfigurations/stlink.xml @@ -1,6 +1,6 @@ - - + + diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 5e54d0f56..7bf726f3f 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -200,8 +200,7 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB // Inline helper //--------------------------------------------------------------------+ -TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr) -{ +TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr) { uint8_t epnum = tu_edpt_number(ep_addr); uint8_t dir = tu_edpt_dir(ep_addr); // Fix -Werror=null-dereference @@ -524,7 +523,7 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr) xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr); if((xfer->total_len != xfer->queued_len)) /* TX not complete */ { - dcd_transmit_packet(xfer, EPindex); + dcd_transmit_packet(xfer, EPindex); } else /* TX Complete */ { @@ -533,10 +532,29 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr) } // Handle CTR interrupt for the RX/OUT direction -// // Upon call, (wIstr & USB_ISTR_DIR) == 0U -static void dcd_ep_ctr_rx_handler(uint32_t wIstr) -{ +static void dcd_ep_ctr_rx_handler(uint32_t wIstr) { + #ifdef FSDEV_BUS_32BIT + /* https://www.st.com/resource/en/errata_sheet/es0561-stm32h503cbebkbrb-device-errata-stmicroelectronics.pdf + * From STM32H503 errata 2.15.1: Buffer description table update completes after CTR interrupt triggers + * Description: + * - During OUT transfers, the correct transfer interrupt (CTR) is triggered a little before the last USB SRAM accesses + * have completed. If the software responds quickly to the interrupt, the full buffer contents may not be correct. + * Workaround: + * - Software should ensure that a small delay is included before accessing the SRAM contents. This delay + * should be 800 ns in Full Speed mode and 6.4 μs in Low Speed mode + * - Since H5 can run up to 250Mhz -> 1 cycle = 4ns. Per errata, we need to wait 200 cycles. Though executing code + * also takes time, so we'll wait 40 cycles (count = 20). + * - Since Low Speed mode is not supported/popular, we will ignore it for now. + * + * Note: this errata also seems to apply to G0, U5, H5 etc. + */ + volatile uint32_t cycle_count = 20; // defined as PCD_RX_PMA_CNT in stm32 hal_driver + while (cycle_count > 0U) { + cycle_count--; // each count take 2 cycle (1 cycle for sub, 1 cycle for compare/jump) + } + #endif + uint32_t EPindex = wIstr & USB_ISTR_EP_ID; uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex); uint8_t ep_addr = wEPRegVal & USB_EPADDR_FIELD; @@ -545,8 +563,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) // Verify the CTR_RX bit is set. This was in the ST Micro code, // but I'm not sure it's actually necessary? - if((wEPRegVal & USB_EP_CTR_RX) == 0U) - { + if((wEPRegVal & USB_EP_CTR_RX) == 0U) { return; } @@ -633,26 +650,22 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) // (Based on the docs, it seems SETUP will always be accepted after CTR is cleared) if(ep_addr == 0u) { - // Always be prepared for a status packet... + // Always be prepared for a status packet... pcd_set_ep_rx_bufsize(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE); pcd_clear_rx_ep_ctr(USB, EPindex); } } -static void dcd_ep_ctr_handler(void) -{ +static void dcd_ep_ctr_handler(void) { uint32_t wIstr; /* stay in loop while pending interrupts */ - while (((wIstr = USB->ISTR) & USB_ISTR_CTR) != 0U) - { - - if ((wIstr & USB_ISTR_DIR) == 0U) /* TX/IN */ - { + while (((wIstr = USB->ISTR) & USB_ISTR_CTR) != 0U) { + if ((wIstr & USB_ISTR_DIR) == 0U) { + /* TX/IN */ dcd_ep_ctr_tx_handler(wIstr); - } - else /* RX/OUT*/ - { + } else { + /* RX/OUT*/ dcd_ep_ctr_rx_handler(wIstr); } } diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h index 15de95d23..5de25765d 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h @@ -286,16 +286,6 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USB TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) { #ifdef FSDEV_BUS_32BIT (void) USBx; - /* WA: few cycles for RX PMA descriptor to update, otherwise doesn't return the correct value. - Note: required for G0, U5, H5 etc. - This workaround is ported from stm32h5xx_hal_pcd.h and fixes the issue when calling this function fast enough. - Reproduced with GCC ast optimization(O2/O3) and stm32h573i_dk with an high frequency. - Observed on Windows 10 where tud_task() is scheduled by interrupt handler. - */ - volatile uint32_t count = 10; // defined as PCD_RX_PMA_CNT in stm32 hal_driver - while (count > 0U) { - count--; - } return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16; #else __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx); -- cgit v1.3.1