From ca8e8041ef05ba06d7d01bf1567106a76a793cab Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Tue, 15 Jun 2021 17:53:09 +0200 Subject: Fix resume, always init FS clock. Signed-off-by: MasterPhi --- src/portable/microchip/samx7x/dcd_samx7x.c | 5 ++--- src/tusb_option.h | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c index a864fda5b..f486e0eed 100644 --- a/src/portable/microchip/samx7x/dcd_samx7x.c +++ b/src/portable/microchip/samx7x/dcd_samx7x.c @@ -49,7 +49,7 @@ # if TUD_OPT_HIGH_SPEED # define USE_DUAL_BANK 0 # else -# define USE_DUAL_BANK 1 +# define USE_DUAL_BANK 0 # endif #endif @@ -108,12 +108,10 @@ void dcd_init (uint8_t rhport) PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0x3fU); // Wait until USB UTMI stabilize while (!(PMC->PMC_SR & PMC_SR_LOCKU)); -#if !TUD_OPT_HIGH_SPEED // Enable USB FS clk PMC->PMC_MCKR &= ~PMC_MCKR_UPLLDIV2; PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(10 - 1); PMC->PMC_SCER = PMC_SCER_USBCLK; -#endif dcd_connect(rhport); } @@ -346,6 +344,7 @@ void dcd_int_handler(uint8_t rhport) { (void) rhport; uint32_t int_status = USBHS->USBHS_DEVISR; + int_status &= USBHS->USBHS_DEVIMR; // End of reset interrupt if (int_status & USBHS_DEVISR_EORST) { diff --git a/src/tusb_option.h b/src/tusb_option.h index 3f5710362..69c5fb0bd 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -61,7 +61,7 @@ #define OPT_MCU_SAME5X 203 ///< MicroChip SAM E5x #define OPT_MCU_SAMD11 204 ///< MicroChip SAMD11 #define OPT_MCU_SAML22 205 ///< MicroChip SAML22 -#define OPT_MCU_SAMX7X 206 ///< MicroChip SAME70, S70, V70, V71 family +#define OPT_MCU_SAMX7X 206 ///< MicroChip SAME70, S70, V70, V71 family // STM32 -- cgit v1.3.1